drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61 #include "i40e_pf.h"
  62
  63 /* Maximun number of MAC addresses */
  64 #define I40E_NUM_MACADDR_MAX       64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 /* Default queue interrupt throttling time in microseconds */
  78 #define I40E_ITR_INDEX_DEFAULT          0
  79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  80 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA  0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 115
 116 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 117 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 118 static int i40e_dev_configure(struct rte_eth_dev *dev);
 119 static int i40e_dev_start(struct rte_eth_dev *dev);
 120 static void i40e_dev_stop(struct rte_eth_dev *dev);
 121 static void i40e_dev_close(struct rte_eth_dev *dev);
 122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 129                                struct rte_eth_stats *stats);
 130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 132                                             uint16_t queue_id,
 133                                             uint8_t stat_idx,
 134                                             uint8_t is_rx);
 135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 136                               struct rte_eth_dev_info *dev_info);
 137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 138                                 uint16_t vlan_id,
 139                                 int on);
 140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 143                                       uint16_t queue,
 144                                       int on);
 145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 149                               struct rte_eth_fc_conf *fc_conf);
 150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 151                                        struct rte_eth_pfc_conf *pfc_conf);
 152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 153                           struct ether_addr *mac_addr,
 154                           uint32_t index,
 155                           uint32_t pool);
 156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 158                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 159                                     uint16_t reta_size);
 160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 161                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 162                                    uint16_t reta_size);
 163
 164 static int i40e_get_cap(struct i40e_hw *hw);
 165 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 166 static int i40e_pf_setup(struct i40e_pf *pf);
 167 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 168 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 170                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 171 static void i40e_stat_update_48(struct i40e_hw *hw,
 172                                uint32_t hireg,
 173                                uint32_t loreg,
 174                                bool offset_loaded,
 175                                uint64_t *offset,
 176                                uint64_t *stat);
 177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 178 static void i40e_dev_interrupt_handler(
 179                 __rte_unused struct rte_intr_handle *handle, void *param);
 180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 181                                 uint32_t base, uint32_t num);
 182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 184                         uint32_t base);
 185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 186                         uint16_t num);
 187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 188 static int i40e_veb_release(struct i40e_veb *veb);
 189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 190                                                 struct i40e_vsi *vsi);
 191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 194                                              struct i40e_macvlan_filter *mv_f,
 195                                              int num,
 196                                              struct ether_addr *addr);
 197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 198                                              struct i40e_macvlan_filter *mv_f,
 199                                              int num,
 200                                              uint16_t vlan);
 201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 203                                     struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 205                                       struct rte_eth_rss_conf *rss_conf);
 206 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 207                                 struct rte_eth_udp_tunnel *udp_tunnel);
 208 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 209                                 struct rte_eth_udp_tunnel *udp_tunnel);
 210 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 217                                 enum rte_filter_type filter_type,
 218                                 enum rte_filter_op filter_op,
 219                                 void *arg);
 220 static void i40e_configure_registers(struct i40e_hw *hw);
 221 static void i40e_hw_init(struct i40e_hw *hw);
 222 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 223 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 224                         struct rte_eth_mirror_conf *mirror_conf,
 225                         uint8_t sw_id, uint8_t on);
 226 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 227
 228 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 229 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 230 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 231                                            struct timespec *timestamp,
 232                                            uint32_t flags);
 233 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 234                                            struct timespec *timestamp);
 235
 236 static const struct rte_pci_id pci_id_i40e_map[] = {
 237 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 238 #include "rte_pci_dev_ids.h"
 239 { .vendor_id = 0, /* sentinel */ },
 240 };
 241
 242 static const struct eth_dev_ops i40e_eth_dev_ops = {
 243         .dev_configure                = i40e_dev_configure,
 244         .dev_start                    = i40e_dev_start,
 245         .dev_stop                     = i40e_dev_stop,
 246         .dev_close                    = i40e_dev_close,
 247         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 248         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 249         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 250         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 251         .dev_set_link_up              = i40e_dev_set_link_up,
 252         .dev_set_link_down            = i40e_dev_set_link_down,
 253         .link_update                  = i40e_dev_link_update,
 254         .stats_get                    = i40e_dev_stats_get,
 255         .stats_reset                  = i40e_dev_stats_reset,
 256         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 257         .dev_infos_get                = i40e_dev_info_get,
 258         .vlan_filter_set              = i40e_vlan_filter_set,
 259         .vlan_tpid_set                = i40e_vlan_tpid_set,
 260         .vlan_offload_set             = i40e_vlan_offload_set,
 261         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 262         .vlan_pvid_set                = i40e_vlan_pvid_set,
 263         .rx_queue_start               = i40e_dev_rx_queue_start,
 264         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 265         .tx_queue_start               = i40e_dev_tx_queue_start,
 266         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 267         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 268         .rx_queue_release             = i40e_dev_rx_queue_release,
 269         .rx_queue_count               = i40e_dev_rx_queue_count,
 270         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 271         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 272         .tx_queue_release             = i40e_dev_tx_queue_release,
 273         .dev_led_on                   = i40e_dev_led_on,
 274         .dev_led_off                  = i40e_dev_led_off,
 275         .flow_ctrl_set                = i40e_flow_ctrl_set,
 276         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 277         .mac_addr_add                 = i40e_macaddr_add,
 278         .mac_addr_remove              = i40e_macaddr_remove,
 279         .reta_update                  = i40e_dev_rss_reta_update,
 280         .reta_query                   = i40e_dev_rss_reta_query,
 281         .rss_hash_update              = i40e_dev_rss_hash_update,
 282         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 283         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 284         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 285         .filter_ctrl                  = i40e_dev_filter_ctrl,
 286         .mirror_rule_set              = i40e_mirror_rule_set,
 287         .mirror_rule_reset            = i40e_mirror_rule_reset,
 288         .timesync_enable              = i40e_timesync_enable,
 289         .timesync_disable             = i40e_timesync_disable,
 290         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 291         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 292 };
 293
 294 static struct eth_driver rte_i40e_pmd = {
 295         .pci_drv = {
 296                 .name = "rte_i40e_pmd",
 297                 .id_table = pci_id_i40e_map,
 298                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 299                         RTE_PCI_DRV_DETACHABLE,
 300         },
 301         .eth_dev_init = eth_i40e_dev_init,
 302         .eth_dev_uninit = eth_i40e_dev_uninit,
 303         .dev_private_size = sizeof(struct i40e_adapter),
 304 };
 305
 306 static inline int
 307 i40e_align_floor(int n)
 308 {
 309         if (n == 0)
 310                 return 0;
 311         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 312 }
 313
 314 static inline int
 315 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 316                                      struct rte_eth_link *link)
 317 {
 318         struct rte_eth_link *dst = link;
 319         struct rte_eth_link *src = &(dev->data->dev_link);
 320
 321         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 322                                         *(uint64_t *)src) == 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 static inline int
 329 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 330                                       struct rte_eth_link *link)
 331 {
 332         struct rte_eth_link *dst = &(dev->data->dev_link);
 333         struct rte_eth_link *src = link;
 334
 335         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 336                                         *(uint64_t *)src) == 0)
 337                 return -1;
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * Driver initialization routine.
 344  * Invoked once at EAL init time.
 345  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 346  */
 347 static int
 348 rte_i40e_pmd_init(const char *name __rte_unused,
 349                   const char *params __rte_unused)
 350 {
 351         PMD_INIT_FUNC_TRACE();
 352         rte_eth_driver_register(&rte_i40e_pmd);
 353
 354         return 0;
 355 }
 356
 357 static struct rte_driver rte_i40e_driver = {
 358         .type = PMD_PDEV,
 359         .init = rte_i40e_pmd_init,
 360 };
 361
 362 PMD_REGISTER_DRIVER(rte_i40e_driver);
 363
 364 /*
 365  * Initialize registers for flexible payload, which should be set by NVM.
 366  * This should be removed from code once it is fixed in NVM.
 367  */
 368 #ifndef I40E_GLQF_ORT
 369 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 370 #endif
 371 #ifndef I40E_GLQF_PIT
 372 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 373 #endif
 374
 375 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 376 {
 377         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 378         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 379         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 380         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 381         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 382         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 383         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 384         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 385         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 386         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 387
 388         /* GLQF_PIT Registers */
 389         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 390         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 391 }
 392
 393 static int
 394 eth_i40e_dev_init(struct rte_eth_dev *dev)
 395 {
 396         struct rte_pci_device *pci_dev;
 397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 399         struct i40e_vsi *vsi;
 400         int ret;
 401         uint32_t len;
 402         uint8_t aq_fail = 0;
 403
 404         PMD_INIT_FUNC_TRACE();
 405
 406         dev->dev_ops = &i40e_eth_dev_ops;
 407         dev->rx_pkt_burst = i40e_recv_pkts;
 408         dev->tx_pkt_burst = i40e_xmit_pkts;
 409
 410         /* for secondary processes, we don't initialise any further as primary
 411          * has already done this work. Only check we don't need a different
 412          * RX function */
 413         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 414                 if (dev->data->scattered_rx)
 415                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 416                 return 0;
 417         }
 418         pci_dev = dev->pci_dev;
 419         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 420         pf->adapter->eth_dev = dev;
 421         pf->dev_data = dev->data;
 422
 423         hw->back = I40E_PF_TO_ADAPTER(pf);
 424         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 425         if (!hw->hw_addr) {
 426                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 427                              "as address is NULL");
 428                 return -ENODEV;
 429         }
 430
 431         hw->vendor_id = pci_dev->id.vendor_id;
 432         hw->device_id = pci_dev->id.device_id;
 433         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 434         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 435         hw->bus.device = pci_dev->addr.devid;
 436         hw->bus.func = pci_dev->addr.function;
 437         hw->adapter_stopped = 0;
 438
 439         /* Make sure all is clean before doing PF reset */
 440         i40e_clear_hw(hw);
 441
 442         /* Initialize the hardware */
 443         i40e_hw_init(hw);
 444
 445         /* Reset here to make sure all is clean for each PF */
 446         ret = i40e_pf_reset(hw);
 447         if (ret) {
 448                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 449                 return ret;
 450         }
 451
 452         /* Initialize the shared code (base driver) */
 453         ret = i40e_init_shared_code(hw);
 454         if (ret) {
 455                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 456                 return ret;
 457         }
 458
 459         /*
 460          * To work around the NVM issue,initialize registers
 461          * for flexible payload by software.
 462          * It should be removed once issues are fixed in NVM.
 463          */
 464         i40e_flex_payload_reg_init(hw);
 465
 466         /* Initialize the parameters for adminq */
 467         i40e_init_adminq_parameter(hw);
 468         ret = i40e_init_adminq(hw);
 469         if (ret != I40E_SUCCESS) {
 470                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 471                 return -EIO;
 472         }
 473         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 474                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 475                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 476                      ((hw->nvm.version >> 12) & 0xf),
 477                      ((hw->nvm.version >> 4) & 0xff),
 478                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 479
 480         /* Disable LLDP */
 481         ret = i40e_aq_stop_lldp(hw, true, NULL);
 482         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 483                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 484
 485         /* Clear PXE mode */
 486         i40e_clear_pxe_mode(hw);
 487
 488         /*
 489          * On X710, performance number is far from the expectation on recent
 490          * firmware versions. The fix for this issue may not be integrated in
 491          * the following firmware version. So the workaround in software driver
 492          * is needed. It needs to modify the initial values of 3 internal only
 493          * registers. Note that the workaround can be removed when it is fixed
 494          * in firmware in the future.
 495          */
 496         i40e_configure_registers(hw);
 497
 498         /* Get hw capabilities */
 499         ret = i40e_get_cap(hw);
 500         if (ret != I40E_SUCCESS) {
 501                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 502                 goto err_get_capabilities;
 503         }
 504
 505         /* Initialize parameters for PF */
 506         ret = i40e_pf_parameter_init(dev);
 507         if (ret != 0) {
 508                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 509                 goto err_parameter_init;
 510         }
 511
 512         /* Initialize the queue management */
 513         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 514         if (ret < 0) {
 515                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 516                 goto err_qp_pool_init;
 517         }
 518         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 519                                 hw->func_caps.num_msix_vectors - 1);
 520         if (ret < 0) {
 521                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 522                 goto err_msix_pool_init;
 523         }
 524
 525         /* Initialize lan hmc */
 526         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 527                                 hw->func_caps.num_rx_qp, 0, 0);
 528         if (ret != I40E_SUCCESS) {
 529                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 530                 goto err_init_lan_hmc;
 531         }
 532
 533         /* Configure lan hmc */
 534         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 535         if (ret != I40E_SUCCESS) {
 536                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 537                 goto err_configure_lan_hmc;
 538         }
 539
 540         /* Get and check the mac address */
 541         i40e_get_mac_addr(hw, hw->mac.addr);
 542         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 543                 PMD_INIT_LOG(ERR, "mac address is not valid");
 544                 ret = -EIO;
 545                 goto err_get_mac_addr;
 546         }
 547         /* Copy the permanent MAC address */
 548         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 549                         (struct ether_addr *) hw->mac.perm_addr);
 550
 551         /* Disable flow control */
 552         hw->fc.requested_mode = I40E_FC_NONE;
 553         i40e_set_fc(hw, &aq_fail, TRUE);
 554
 555         /* PF setup, which includes VSI setup */
 556         ret = i40e_pf_setup(pf);
 557         if (ret) {
 558                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 559                 goto err_setup_pf_switch;
 560         }
 561
 562         vsi = pf->main_vsi;
 563
 564         /* Disable double vlan by default */
 565         i40e_vsi_config_double_vlan(vsi, FALSE);
 566
 567         if (!vsi->max_macaddrs)
 568                 len = ETHER_ADDR_LEN;
 569         else
 570                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 571
 572         /* Should be after VSI initialized */
 573         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 574         if (!dev->data->mac_addrs) {
 575                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 576                                         "for storing mac address");
 577                 goto err_mac_alloc;
 578         }
 579         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 580                                         &dev->data->mac_addrs[0]);
 581
 582         /* initialize pf host driver to setup SRIOV resource if applicable */
 583         i40e_pf_host_init(dev);
 584
 585         /* register callback func to eal lib */
 586         rte_intr_callback_register(&(pci_dev->intr_handle),
 587                 i40e_dev_interrupt_handler, (void *)dev);
 588
 589         /* configure and enable device interrupt */
 590         i40e_pf_config_irq0(hw);
 591         i40e_pf_enable_irq0(hw);
 592
 593         /* enable uio intr after callback register */
 594         rte_intr_enable(&(pci_dev->intr_handle));
 595
 596         /* initialize mirror rule list */
 597         TAILQ_INIT(&pf->mirror_list);
 598
 599         return 0;
 600
 601 err_mac_alloc:
 602         i40e_vsi_release(pf->main_vsi);
 603 err_setup_pf_switch:
 604 err_get_mac_addr:
 605 err_configure_lan_hmc:
 606         (void)i40e_shutdown_lan_hmc(hw);
 607 err_init_lan_hmc:
 608         i40e_res_pool_destroy(&pf->msix_pool);
 609 err_msix_pool_init:
 610         i40e_res_pool_destroy(&pf->qp_pool);
 611 err_qp_pool_init:
 612 err_parameter_init:
 613 err_get_capabilities:
 614         (void)i40e_shutdown_adminq(hw);
 615
 616         return ret;
 617 }
 618
 619 static int
 620 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 621 {
 622         struct rte_pci_device *pci_dev;
 623         struct i40e_hw *hw;
 624         struct i40e_filter_control_settings settings;
 625         int ret;
 626         uint8_t aq_fail = 0;
 627
 628         PMD_INIT_FUNC_TRACE();
 629
 630         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 631                 return 0;
 632
 633         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 634         pci_dev = dev->pci_dev;
 635
 636         if (hw->adapter_stopped == 0)
 637                 i40e_dev_close(dev);
 638
 639         dev->dev_ops = NULL;
 640         dev->rx_pkt_burst = NULL;
 641         dev->tx_pkt_burst = NULL;
 642
 643         /* Disable LLDP */
 644         ret = i40e_aq_stop_lldp(hw, true, NULL);
 645         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 646                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 647
 648         /* Clear PXE mode */
 649         i40e_clear_pxe_mode(hw);
 650
 651         /* Unconfigure filter control */
 652         memset(&settings, 0, sizeof(settings));
 653         ret = i40e_set_filter_control(hw, &settings);
 654         if (ret)
 655                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 656                                         ret);
 657
 658         /* Disable flow control */
 659         hw->fc.requested_mode = I40E_FC_NONE;
 660         i40e_set_fc(hw, &aq_fail, TRUE);
 661
 662         /* uninitialize pf host driver */
 663         i40e_pf_host_uninit(dev);
 664
 665         rte_free(dev->data->mac_addrs);
 666         dev->data->mac_addrs = NULL;
 667
 668         /* disable uio intr before callback unregister */
 669         rte_intr_disable(&(pci_dev->intr_handle));
 670
 671         /* register callback func to eal lib */
 672         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 673                 i40e_dev_interrupt_handler, (void *)dev);
 674
 675         return 0;
 676 }
 677
 678 static int
 679 i40e_dev_configure(struct rte_eth_dev *dev)
 680 {
 681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 682         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 683         int ret;
 684
 685         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 686                 ret = i40e_fdir_setup(pf);
 687                 if (ret != I40E_SUCCESS) {
 688                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 689                         return -ENOTSUP;
 690                 }
 691                 ret = i40e_fdir_configure(dev);
 692                 if (ret < 0) {
 693                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 694                         goto err;
 695                 }
 696         } else
 697                 i40e_fdir_teardown(pf);
 698
 699         ret = i40e_dev_init_vlan(dev);
 700         if (ret < 0)
 701                 goto err;
 702
 703         /* VMDQ setup.
 704          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 705          *  RSS setting have different requirements.
 706          *  General PMD driver call sequence are NIC init, configure,
 707          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 708          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 709          *  applicable. So, VMDQ setting has to be done before
 710          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 711          *  For RSS setting, it will try to calculate actual configured RX queue
 712          *  number, which will be available after rx_queue_setup(). dev_start()
 713          *  function is good to place RSS setup.
 714          */
 715         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 716                 ret = i40e_vmdq_setup(dev);
 717                 if (ret)
 718                         goto err;
 719         }
 720         return 0;
 721 err:
 722         i40e_fdir_teardown(pf);
 723         return ret;
 724 }
 725
 726 void
 727 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 728 {
 729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 730         uint16_t msix_vect = vsi->msix_intr;
 731         uint16_t i;
 732
 733         for (i = 0; i < vsi->nb_qps; i++) {
 734                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 735                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 736                 rte_wmb();
 737         }
 738
 739         if (vsi->type != I40E_VSI_SRIOV) {
 740                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 741                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 742                                 msix_vect - 1), 0);
 743         } else {
 744                 uint32_t reg;
 745                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 746                         vsi->user_param + (msix_vect - 1);
 747
 748                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 749         }
 750         I40E_WRITE_FLUSH(hw);
 751 }
 752
 753 static inline uint16_t
 754 i40e_calc_itr_interval(int16_t interval)
 755 {
 756         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 757                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 758
 759         /* Convert to hardware count, as writing each 1 represents 2 us */
 760         return (interval/2);
 761 }
 762
 763 void
 764 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 765 {
 766         uint32_t val;
 767         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 768         uint16_t msix_vect = vsi->msix_intr;
 769         int i;
 770
 771         for (i = 0; i < vsi->nb_qps; i++)
 772                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 773
 774         /* Bind all RX queues to allocated MSIX interrupt */
 775         for (i = 0; i < vsi->nb_qps; i++) {
 776                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 777                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 778                         ((vsi->base_queue + i + 1) <<
 779                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 780                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 781                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 782
 783                 if (i == vsi->nb_qps - 1)
 784                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 785                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 786         }
 787
 788         /* Write first RX queue to Link list register as the head element */
 789         if (vsi->type != I40E_VSI_SRIOV) {
 790                 uint16_t interval =
 791                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 792
 793                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 794                                                 (vsi->base_queue <<
 795                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 796                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 797
 798                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 799                                                 msix_vect - 1), interval);
 800
 801 #ifndef I40E_GLINT_CTL
 802 #define I40E_GLINT_CTL                     0x0003F800
 803 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 804 #endif
 805                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 806                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 807                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 808         } else {
 809                 uint32_t reg;
 810
 811                 /* num_msix_vectors_vf needs to minus irq0 */
 812                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 813                         vsi->user_param + (msix_vect - 1);
 814
 815                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 816                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 817                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 818         }
 819
 820         I40E_WRITE_FLUSH(hw);
 821 }
 822
 823 static void
 824 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 825 {
 826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 827         uint16_t interval = i40e_calc_itr_interval(\
 828                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 829
 830         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 831                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 832                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 833                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 834                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 835 }
 836
 837 static void
 838 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 839 {
 840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 841
 842         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 843 }
 844
 845 static inline uint8_t
 846 i40e_parse_link_speed(uint16_t eth_link_speed)
 847 {
 848         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 849
 850         switch (eth_link_speed) {
 851         case ETH_LINK_SPEED_40G:
 852                 link_speed = I40E_LINK_SPEED_40GB;
 853                 break;
 854         case ETH_LINK_SPEED_20G:
 855                 link_speed = I40E_LINK_SPEED_20GB;
 856                 break;
 857         case ETH_LINK_SPEED_10G:
 858                 link_speed = I40E_LINK_SPEED_10GB;
 859                 break;
 860         case ETH_LINK_SPEED_1000:
 861                 link_speed = I40E_LINK_SPEED_1GB;
 862                 break;
 863         case ETH_LINK_SPEED_100:
 864                 link_speed = I40E_LINK_SPEED_100MB;
 865                 break;
 866         }
 867
 868         return link_speed;
 869 }
 870
 871 static int
 872 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 873 {
 874         enum i40e_status_code status;
 875         struct i40e_aq_get_phy_abilities_resp phy_ab;
 876         struct i40e_aq_set_phy_config phy_conf;
 877         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 878                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 879                         I40E_AQ_PHY_FLAG_LOW_POWER;
 880         const uint8_t advt = I40E_LINK_SPEED_40GB |
 881                         I40E_LINK_SPEED_10GB |
 882                         I40E_LINK_SPEED_1GB |
 883                         I40E_LINK_SPEED_100MB;
 884         int ret = -ENOTSUP;
 885
 886         /* Skip it on 40G interfaces, as a workaround for the link issue */
 887         if (i40e_is_40G_device(hw->device_id))
 888                 return I40E_SUCCESS;
 889
 890         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 891                                               NULL);
 892         if (status)
 893                 return ret;
 894
 895         memset(&phy_conf, 0, sizeof(phy_conf));
 896
 897         /* bits 0-2 use the values from get_phy_abilities_resp */
 898         abilities &= ~mask;
 899         abilities |= phy_ab.abilities & mask;
 900
 901         /* update ablities and speed */
 902         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 903                 phy_conf.link_speed = advt;
 904         else
 905                 phy_conf.link_speed = force_speed;
 906
 907         phy_conf.abilities = abilities;
 908
 909         /* use get_phy_abilities_resp value for the rest */
 910         phy_conf.phy_type = phy_ab.phy_type;
 911         phy_conf.eee_capability = phy_ab.eee_capability;
 912         phy_conf.eeer = phy_ab.eeer_val;
 913         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 914
 915         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 916                     phy_ab.abilities, phy_ab.link_speed);
 917         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 918                     phy_conf.abilities, phy_conf.link_speed);
 919
 920         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 921         if (status)
 922                 return ret;
 923
 924         return I40E_SUCCESS;
 925 }
 926
 927 static int
 928 i40e_apply_link_speed(struct rte_eth_dev *dev)
 929 {
 930         uint8_t speed;
 931         uint8_t abilities = 0;
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933         struct rte_eth_conf *conf = &dev->data->dev_conf;
 934
 935         speed = i40e_parse_link_speed(conf->link_speed);
 936         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 937         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 938                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 939         else
 940                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 941
 942         return i40e_phy_conf_link(hw, abilities, speed);
 943 }
 944
 945 static int
 946 i40e_dev_start(struct rte_eth_dev *dev)
 947 {
 948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         struct i40e_vsi *main_vsi = pf->main_vsi;
 951         int ret, i;
 952
 953         hw->adapter_stopped = 0;
 954
 955         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 956                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 957                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 958                              dev->data->dev_conf.link_duplex,
 959                              dev->data->port_id);
 960                 return -EINVAL;
 961         }
 962
 963         /* Initialize VSI */
 964         ret = i40e_dev_rxtx_init(pf);
 965         if (ret != I40E_SUCCESS) {
 966                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 967                 goto err_up;
 968         }
 969
 970         /* Map queues with MSIX interrupt */
 971         i40e_vsi_queues_bind_intr(main_vsi);
 972         i40e_vsi_enable_queues_intr(main_vsi);
 973
 974         /* Map VMDQ VSI queues with MSIX interrupt */
 975         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 976                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 977                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 978         }
 979
 980         /* enable FDIR MSIX interrupt */
 981         if (pf->fdir.fdir_vsi) {
 982                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 983                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 984         }
 985
 986         /* Enable all queues which have been configured */
 987         ret = i40e_dev_switch_queues(pf, TRUE);
 988         if (ret != I40E_SUCCESS) {
 989                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 990                 goto err_up;
 991         }
 992
 993         /* Enable receiving broadcast packets */
 994         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 995         if (ret != I40E_SUCCESS)
 996                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 997
 998         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 999                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1000                                                 true, NULL);
1001                 if (ret != I40E_SUCCESS)
1002                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1003         }
1004
1005         /* Apply link configure */
1006         ret = i40e_apply_link_speed(dev);
1007         if (I40E_SUCCESS != ret) {
1008                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1009                 goto err_up;
1010         }
1011
1012         return I40E_SUCCESS;
1013
1014 err_up:
1015         i40e_dev_switch_queues(pf, FALSE);
1016         i40e_dev_clear_queues(dev);
1017
1018         return ret;
1019 }
1020
1021 static void
1022 i40e_dev_stop(struct rte_eth_dev *dev)
1023 {
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_vsi *main_vsi = pf->main_vsi;
1026         struct i40e_mirror_rule *p_mirror;
1027         int i;
1028
1029         /* Disable all queues */
1030         i40e_dev_switch_queues(pf, FALSE);
1031
1032         /* un-map queues with interrupt registers */
1033         i40e_vsi_disable_queues_intr(main_vsi);
1034         i40e_vsi_queues_unbind_intr(main_vsi);
1035
1036         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1037                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1038                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1039         }
1040
1041         if (pf->fdir.fdir_vsi) {
1042                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1043                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1044         }
1045         /* Clear all queues and release memory */
1046         i40e_dev_clear_queues(dev);
1047
1048         /* Set link down */
1049         i40e_dev_set_link_down(dev);
1050
1051         /* Remove all mirror rules */
1052         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1053                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1054                 rte_free(p_mirror);
1055         }
1056         pf->nb_mirror_rule = 0;
1057
1058 }
1059
1060 static void
1061 i40e_dev_close(struct rte_eth_dev *dev)
1062 {
1063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065         uint32_t reg;
1066         int i;
1067
1068         PMD_INIT_FUNC_TRACE();
1069
1070         i40e_dev_stop(dev);
1071         hw->adapter_stopped = 1;
1072         i40e_dev_free_queues(dev);
1073
1074         /* Disable interrupt */
1075         i40e_pf_disable_irq0(hw);
1076         rte_intr_disable(&(dev->pci_dev->intr_handle));
1077
1078         /* shutdown and destroy the HMC */
1079         i40e_shutdown_lan_hmc(hw);
1080
1081         /* release all the existing VSIs and VEBs */
1082         i40e_fdir_teardown(pf);
1083         i40e_vsi_release(pf->main_vsi);
1084
1085         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1086                 i40e_vsi_release(pf->vmdq[i].vsi);
1087                 pf->vmdq[i].vsi = NULL;
1088         }
1089
1090         rte_free(pf->vmdq);
1091         pf->vmdq = NULL;
1092
1093         /* shutdown the adminq */
1094         i40e_aq_queue_shutdown(hw, true);
1095         i40e_shutdown_adminq(hw);
1096
1097         i40e_res_pool_destroy(&pf->qp_pool);
1098         i40e_res_pool_destroy(&pf->msix_pool);
1099
1100         /* force a PF reset to clean anything leftover */
1101         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1102         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1103                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1104         I40E_WRITE_FLUSH(hw);
1105 }
1106
1107 static void
1108 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1109 {
1110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1112         struct i40e_vsi *vsi = pf->main_vsi;
1113         int status;
1114
1115         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1116                                                         true, NULL);
1117         if (status != I40E_SUCCESS)
1118                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1119
1120         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1121                                                         TRUE, NULL);
1122         if (status != I40E_SUCCESS)
1123                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1124
1125 }
1126
1127 static void
1128 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1129 {
1130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1132         struct i40e_vsi *vsi = pf->main_vsi;
1133         int status;
1134
1135         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1136                                                         false, NULL);
1137         if (status != I40E_SUCCESS)
1138                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1139
1140         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1141                                                         false, NULL);
1142         if (status != I40E_SUCCESS)
1143                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1144 }
1145
1146 static void
1147 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1148 {
1149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151         struct i40e_vsi *vsi = pf->main_vsi;
1152         int ret;
1153
1154         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1155         if (ret != I40E_SUCCESS)
1156                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1157 }
1158
1159 static void
1160 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1161 {
1162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164         struct i40e_vsi *vsi = pf->main_vsi;
1165         int ret;
1166
1167         if (dev->data->promiscuous == 1)
1168                 return; /* must remain in all_multicast mode */
1169
1170         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1171                                 vsi->seid, FALSE, NULL);
1172         if (ret != I40E_SUCCESS)
1173                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1174 }
1175
1176 /*
1177  * Set device link up.
1178  */
1179 static int
1180 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1181 {
1182         /* re-apply link speed setting */
1183         return i40e_apply_link_speed(dev);
1184 }
1185
1186 /*
1187  * Set device link down.
1188  */
1189 static int
1190 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1191 {
1192         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1193         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1194         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1195
1196         return i40e_phy_conf_link(hw, abilities, speed);
1197 }
1198
1199 int
1200 i40e_dev_link_update(struct rte_eth_dev *dev,
1201                      int wait_to_complete)
1202 {
1203 #define CHECK_INTERVAL 100  /* 100ms */
1204 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1206         struct i40e_link_status link_status;
1207         struct rte_eth_link link, old;
1208         int status;
1209         unsigned rep_cnt = MAX_REPEAT_TIME;
1210
1211         memset(&link, 0, sizeof(link));
1212         memset(&old, 0, sizeof(old));
1213         memset(&link_status, 0, sizeof(link_status));
1214         rte_i40e_dev_atomic_read_link_status(dev, &old);
1215
1216         do {
1217                 /* Get link status information from hardware */
1218                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1219                 if (status != I40E_SUCCESS) {
1220                         link.link_speed = ETH_LINK_SPEED_100;
1221                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1222                         PMD_DRV_LOG(ERR, "Failed to get link info");
1223                         goto out;
1224                 }
1225
1226                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1227                 if (!wait_to_complete)
1228                         break;
1229
1230                 rte_delay_ms(CHECK_INTERVAL);
1231         } while (!link.link_status && rep_cnt--);
1232
1233         if (!link.link_status)
1234                 goto out;
1235
1236         /* i40e uses full duplex only */
1237         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1238
1239         /* Parse the link status */
1240         switch (link_status.link_speed) {
1241         case I40E_LINK_SPEED_100MB:
1242                 link.link_speed = ETH_LINK_SPEED_100;
1243                 break;
1244         case I40E_LINK_SPEED_1GB:
1245                 link.link_speed = ETH_LINK_SPEED_1000;
1246                 break;
1247         case I40E_LINK_SPEED_10GB:
1248                 link.link_speed = ETH_LINK_SPEED_10G;
1249                 break;
1250         case I40E_LINK_SPEED_20GB:
1251                 link.link_speed = ETH_LINK_SPEED_20G;
1252                 break;
1253         case I40E_LINK_SPEED_40GB:
1254                 link.link_speed = ETH_LINK_SPEED_40G;
1255                 break;
1256         default:
1257                 link.link_speed = ETH_LINK_SPEED_100;
1258                 break;
1259         }
1260
1261 out:
1262         rte_i40e_dev_atomic_write_link_status(dev, &link);
1263         if (link.link_status == old.link_status)
1264                 return -1;
1265
1266         return 0;
1267 }
1268
1269 /* Get all the statistics of a VSI */
1270 void
1271 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1272 {
1273         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1274         struct i40e_eth_stats *nes = &vsi->eth_stats;
1275         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1276         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1277
1278         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1279                             vsi->offset_loaded, &oes->rx_bytes,
1280                             &nes->rx_bytes);
1281         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1282                             vsi->offset_loaded, &oes->rx_unicast,
1283                             &nes->rx_unicast);
1284         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1285                             vsi->offset_loaded, &oes->rx_multicast,
1286                             &nes->rx_multicast);
1287         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1288                             vsi->offset_loaded, &oes->rx_broadcast,
1289                             &nes->rx_broadcast);
1290         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1291                             &oes->rx_discards, &nes->rx_discards);
1292         /* GLV_REPC not supported */
1293         /* GLV_RMPC not supported */
1294         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1295                             &oes->rx_unknown_protocol,
1296                             &nes->rx_unknown_protocol);
1297         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1298                             vsi->offset_loaded, &oes->tx_bytes,
1299                             &nes->tx_bytes);
1300         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1301                             vsi->offset_loaded, &oes->tx_unicast,
1302                             &nes->tx_unicast);
1303         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1304                             vsi->offset_loaded, &oes->tx_multicast,
1305                             &nes->tx_multicast);
1306         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1307                             vsi->offset_loaded,  &oes->tx_broadcast,
1308                             &nes->tx_broadcast);
1309         /* GLV_TDPC not supported */
1310         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1311                             &oes->tx_errors, &nes->tx_errors);
1312         vsi->offset_loaded = true;
1313
1314         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1315                     vsi->vsi_id);
1316         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1317         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1318         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1319         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1320         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1321         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1322                     nes->rx_unknown_protocol);
1323         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1324         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1325         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1326         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1327         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1328         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1329         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1330                     vsi->vsi_id);
1331 }
1332
1333 /* Get all statistics of a port */
1334 static void
1335 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1336 {
1337         uint32_t i;
1338         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1340         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1341         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1342
1343         /* Get statistics of struct i40e_eth_stats */
1344         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1345                             I40E_GLPRT_GORCL(hw->port),
1346                             pf->offset_loaded, &os->eth.rx_bytes,
1347                             &ns->eth.rx_bytes);
1348         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1349                             I40E_GLPRT_UPRCL(hw->port),
1350                             pf->offset_loaded, &os->eth.rx_unicast,
1351                             &ns->eth.rx_unicast);
1352         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1353                             I40E_GLPRT_MPRCL(hw->port),
1354                             pf->offset_loaded, &os->eth.rx_multicast,
1355                             &ns->eth.rx_multicast);
1356         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1357                             I40E_GLPRT_BPRCL(hw->port),
1358                             pf->offset_loaded, &os->eth.rx_broadcast,
1359                             &ns->eth.rx_broadcast);
1360         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1361                             pf->offset_loaded, &os->eth.rx_discards,
1362                             &ns->eth.rx_discards);
1363         /* GLPRT_REPC not supported */
1364         /* GLPRT_RMPC not supported */
1365         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1366                             pf->offset_loaded,
1367                             &os->eth.rx_unknown_protocol,
1368                             &ns->eth.rx_unknown_protocol);
1369         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1370                             I40E_GLPRT_GOTCL(hw->port),
1371                             pf->offset_loaded, &os->eth.tx_bytes,
1372                             &ns->eth.tx_bytes);
1373         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1374                             I40E_GLPRT_UPTCL(hw->port),
1375                             pf->offset_loaded, &os->eth.tx_unicast,
1376                             &ns->eth.tx_unicast);
1377         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1378                             I40E_GLPRT_MPTCL(hw->port),
1379                             pf->offset_loaded, &os->eth.tx_multicast,
1380                             &ns->eth.tx_multicast);
1381         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1382                             I40E_GLPRT_BPTCL(hw->port),
1383                             pf->offset_loaded, &os->eth.tx_broadcast,
1384                             &ns->eth.tx_broadcast);
1385         /* GLPRT_TEPC not supported */
1386
1387         /* additional port specific stats */
1388         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1389                             pf->offset_loaded, &os->tx_dropped_link_down,
1390                             &ns->tx_dropped_link_down);
1391         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1392                             pf->offset_loaded, &os->crc_errors,
1393                             &ns->crc_errors);
1394         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1395                             pf->offset_loaded, &os->illegal_bytes,
1396                             &ns->illegal_bytes);
1397         /* GLPRT_ERRBC not supported */
1398         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1399                             pf->offset_loaded, &os->mac_local_faults,
1400                             &ns->mac_local_faults);
1401         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1402                             pf->offset_loaded, &os->mac_remote_faults,
1403                             &ns->mac_remote_faults);
1404         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1405                             pf->offset_loaded, &os->rx_length_errors,
1406                             &ns->rx_length_errors);
1407         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1408                             pf->offset_loaded, &os->link_xon_rx,
1409                             &ns->link_xon_rx);
1410         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1411                             pf->offset_loaded, &os->link_xoff_rx,
1412                             &ns->link_xoff_rx);
1413         for (i = 0; i < 8; i++) {
1414                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1415                                     pf->offset_loaded,
1416                                     &os->priority_xon_rx[i],
1417                                     &ns->priority_xon_rx[i]);
1418                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1419                                     pf->offset_loaded,
1420                                     &os->priority_xoff_rx[i],
1421                                     &ns->priority_xoff_rx[i]);
1422         }
1423         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1424                             pf->offset_loaded, &os->link_xon_tx,
1425                             &ns->link_xon_tx);
1426         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1427                             pf->offset_loaded, &os->link_xoff_tx,
1428                             &ns->link_xoff_tx);
1429         for (i = 0; i < 8; i++) {
1430                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1431                                     pf->offset_loaded,
1432                                     &os->priority_xon_tx[i],
1433                                     &ns->priority_xon_tx[i]);
1434                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1435                                     pf->offset_loaded,
1436                                     &os->priority_xoff_tx[i],
1437                                     &ns->priority_xoff_tx[i]);
1438                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1439                                     pf->offset_loaded,
1440                                     &os->priority_xon_2_xoff[i],
1441                                     &ns->priority_xon_2_xoff[i]);
1442         }
1443         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1444                             I40E_GLPRT_PRC64L(hw->port),
1445                             pf->offset_loaded, &os->rx_size_64,
1446                             &ns->rx_size_64);
1447         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1448                             I40E_GLPRT_PRC127L(hw->port),
1449                             pf->offset_loaded, &os->rx_size_127,
1450                             &ns->rx_size_127);
1451         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1452                             I40E_GLPRT_PRC255L(hw->port),
1453                             pf->offset_loaded, &os->rx_size_255,
1454                             &ns->rx_size_255);
1455         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1456                             I40E_GLPRT_PRC511L(hw->port),
1457                             pf->offset_loaded, &os->rx_size_511,
1458                             &ns->rx_size_511);
1459         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1460                             I40E_GLPRT_PRC1023L(hw->port),
1461                             pf->offset_loaded, &os->rx_size_1023,
1462                             &ns->rx_size_1023);
1463         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1464                             I40E_GLPRT_PRC1522L(hw->port),
1465                             pf->offset_loaded, &os->rx_size_1522,
1466                             &ns->rx_size_1522);
1467         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1468                             I40E_GLPRT_PRC9522L(hw->port),
1469                             pf->offset_loaded, &os->rx_size_big,
1470                             &ns->rx_size_big);
1471         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1472                             pf->offset_loaded, &os->rx_undersize,
1473                             &ns->rx_undersize);
1474         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1475                             pf->offset_loaded, &os->rx_fragments,
1476                             &ns->rx_fragments);
1477         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1478                             pf->offset_loaded, &os->rx_oversize,
1479                             &ns->rx_oversize);
1480         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1481                             pf->offset_loaded, &os->rx_jabber,
1482                             &ns->rx_jabber);
1483         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1484                             I40E_GLPRT_PTC64L(hw->port),
1485                             pf->offset_loaded, &os->tx_size_64,
1486                             &ns->tx_size_64);
1487         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1488                             I40E_GLPRT_PTC127L(hw->port),
1489                             pf->offset_loaded, &os->tx_size_127,
1490                             &ns->tx_size_127);
1491         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1492                             I40E_GLPRT_PTC255L(hw->port),
1493                             pf->offset_loaded, &os->tx_size_255,
1494                             &ns->tx_size_255);
1495         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1496                             I40E_GLPRT_PTC511L(hw->port),
1497                             pf->offset_loaded, &os->tx_size_511,
1498                             &ns->tx_size_511);
1499         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1500                             I40E_GLPRT_PTC1023L(hw->port),
1501                             pf->offset_loaded, &os->tx_size_1023,
1502                             &ns->tx_size_1023);
1503         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1504                             I40E_GLPRT_PTC1522L(hw->port),
1505                             pf->offset_loaded, &os->tx_size_1522,
1506                             &ns->tx_size_1522);
1507         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1508                             I40E_GLPRT_PTC9522L(hw->port),
1509                             pf->offset_loaded, &os->tx_size_big,
1510                             &ns->tx_size_big);
1511         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1512                            pf->offset_loaded,
1513                            &os->fd_sb_match, &ns->fd_sb_match);
1514         /* GLPRT_MSPDC not supported */
1515         /* GLPRT_XEC not supported */
1516
1517         pf->offset_loaded = true;
1518
1519         if (pf->main_vsi)
1520                 i40e_update_vsi_stats(pf->main_vsi);
1521
1522         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1523                                                 ns->eth.rx_broadcast;
1524         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1525                                                 ns->eth.tx_broadcast;
1526         stats->ibytes   = ns->eth.rx_bytes;
1527         stats->obytes   = ns->eth.tx_bytes;
1528         stats->oerrors  = ns->eth.tx_errors;
1529         stats->imcasts  = ns->eth.rx_multicast;
1530         stats->fdirmatch = ns->fd_sb_match;
1531
1532         /* Rx Errors */
1533         stats->ibadcrc  = ns->crc_errors;
1534         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1535                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1536         stats->imissed  = ns->eth.rx_discards;
1537         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1538
1539         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1540         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1541         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1542         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1543         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1544         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1545         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1546                     ns->eth.rx_unknown_protocol);
1547         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1548         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1549         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1550         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1551         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1552         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1553
1554         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1555                     ns->tx_dropped_link_down);
1556         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1557         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1558                     ns->illegal_bytes);
1559         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1560         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1561                     ns->mac_local_faults);
1562         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1563                     ns->mac_remote_faults);
1564         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1565                     ns->rx_length_errors);
1566         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1567         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1568         for (i = 0; i < 8; i++) {
1569                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1570                                 i, ns->priority_xon_rx[i]);
1571                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1572                                 i, ns->priority_xoff_rx[i]);
1573         }
1574         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1575         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1576         for (i = 0; i < 8; i++) {
1577                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1578                                 i, ns->priority_xon_tx[i]);
1579                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1580                                 i, ns->priority_xoff_tx[i]);
1581                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1582                                 i, ns->priority_xon_2_xoff[i]);
1583         }
1584         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1585         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1586         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1587         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1588         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1589         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1590         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1591         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1592         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1593         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1594         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1595         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1596         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1597         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1598         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1599         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1600         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1601         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1602         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1603                         ns->mac_short_packet_dropped);
1604         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1605                     ns->checksum_error);
1606         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1607         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1608 }
1609
1610 /* Reset the statistics */
1611 static void
1612 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1613 {
1614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1615
1616         /* It results in reloading the start point of each counter */
1617         pf->offset_loaded = false;
1618 }
1619
1620 static int
1621 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1622                                  __rte_unused uint16_t queue_id,
1623                                  __rte_unused uint8_t stat_idx,
1624                                  __rte_unused uint8_t is_rx)
1625 {
1626         PMD_INIT_FUNC_TRACE();
1627
1628         return -ENOSYS;
1629 }
1630
1631 static void
1632 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1633 {
1634         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1635         struct i40e_vsi *vsi = pf->main_vsi;
1636
1637         dev_info->max_rx_queues = vsi->nb_qps;
1638         dev_info->max_tx_queues = vsi->nb_qps;
1639         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1640         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1641         dev_info->max_mac_addrs = vsi->max_macaddrs;
1642         dev_info->max_vfs = dev->pci_dev->max_vfs;
1643         dev_info->rx_offload_capa =
1644                 DEV_RX_OFFLOAD_VLAN_STRIP |
1645                 DEV_RX_OFFLOAD_QINQ_STRIP |
1646                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1647                 DEV_RX_OFFLOAD_UDP_CKSUM |
1648                 DEV_RX_OFFLOAD_TCP_CKSUM;
1649         dev_info->tx_offload_capa =
1650                 DEV_TX_OFFLOAD_VLAN_INSERT |
1651                 DEV_TX_OFFLOAD_QINQ_INSERT |
1652                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1653                 DEV_TX_OFFLOAD_UDP_CKSUM |
1654                 DEV_TX_OFFLOAD_TCP_CKSUM |
1655                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1656                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1657                 DEV_TX_OFFLOAD_TCP_TSO;
1658         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1659                                                 sizeof(uint32_t);
1660         dev_info->reta_size = pf->hash_lut_size;
1661         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1662
1663         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1664                 .rx_thresh = {
1665                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1666                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1667                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1668                 },
1669                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1670                 .rx_drop_en = 0,
1671         };
1672
1673         dev_info->default_txconf = (struct rte_eth_txconf) {
1674                 .tx_thresh = {
1675                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1676                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1677                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1678                 },
1679                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1680                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1681                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1682                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1683         };
1684
1685         if (pf->flags & I40E_FLAG_VMDQ) {
1686                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1687                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1688                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1689                                                 pf->max_nb_vmdq_vsi;
1690                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1691                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1692                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1693         }
1694 }
1695
1696 static int
1697 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1698 {
1699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1700         struct i40e_vsi *vsi = pf->main_vsi;
1701         PMD_INIT_FUNC_TRACE();
1702
1703         if (on)
1704                 return i40e_vsi_add_vlan(vsi, vlan_id);
1705         else
1706                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1707 }
1708
1709 static void
1710 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1711                    __rte_unused uint16_t tpid)
1712 {
1713         PMD_INIT_FUNC_TRACE();
1714 }
1715
1716 static void
1717 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1718 {
1719         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1720         struct i40e_vsi *vsi = pf->main_vsi;
1721
1722         if (mask & ETH_VLAN_STRIP_MASK) {
1723                 /* Enable or disable VLAN stripping */
1724                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1725                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1726                 else
1727                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1728         }
1729
1730         if (mask & ETH_VLAN_EXTEND_MASK) {
1731                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1732                         i40e_vsi_config_double_vlan(vsi, TRUE);
1733                 else
1734                         i40e_vsi_config_double_vlan(vsi, FALSE);
1735         }
1736 }
1737
1738 static void
1739 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1740                           __rte_unused uint16_t queue,
1741                           __rte_unused int on)
1742 {
1743         PMD_INIT_FUNC_TRACE();
1744 }
1745
1746 static int
1747 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1748 {
1749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1750         struct i40e_vsi *vsi = pf->main_vsi;
1751         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1752         struct i40e_vsi_vlan_pvid_info info;
1753
1754         memset(&info, 0, sizeof(info));
1755         info.on = on;
1756         if (info.on)
1757                 info.config.pvid = pvid;
1758         else {
1759                 info.config.reject.tagged =
1760                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1761                 info.config.reject.untagged =
1762                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1763         }
1764
1765         return i40e_vsi_vlan_pvid_set(vsi, &info);
1766 }
1767
1768 static int
1769 i40e_dev_led_on(struct rte_eth_dev *dev)
1770 {
1771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         uint32_t mode = i40e_led_get(hw);
1773
1774         if (mode == 0)
1775                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1776
1777         return 0;
1778 }
1779
1780 static int
1781 i40e_dev_led_off(struct rte_eth_dev *dev)
1782 {
1783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784         uint32_t mode = i40e_led_get(hw);
1785
1786         if (mode != 0)
1787                 i40e_led_set(hw, 0, false);
1788
1789         return 0;
1790 }
1791
1792 static int
1793 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1794                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1795 {
1796         PMD_INIT_FUNC_TRACE();
1797
1798         return -ENOSYS;
1799 }
1800
1801 static int
1802 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1803                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1804 {
1805         PMD_INIT_FUNC_TRACE();
1806
1807         return -ENOSYS;
1808 }
1809
1810 /* Add a MAC address, and update filters */
1811 static void
1812 i40e_macaddr_add(struct rte_eth_dev *dev,
1813                  struct ether_addr *mac_addr,
1814                  __rte_unused uint32_t index,
1815                  uint32_t pool)
1816 {
1817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1818         struct i40e_mac_filter_info mac_filter;
1819         struct i40e_vsi *vsi;
1820         int ret;
1821
1822         /* If VMDQ not enabled or configured, return */
1823         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1824                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1825                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1826                         pool);
1827                 return;
1828         }
1829
1830         if (pool > pf->nb_cfg_vmdq_vsi) {
1831                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1832                                 pool, pf->nb_cfg_vmdq_vsi);
1833                 return;
1834         }
1835
1836         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1837         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1838
1839         if (pool == 0)
1840                 vsi = pf->main_vsi;
1841         else
1842                 vsi = pf->vmdq[pool - 1].vsi;
1843
1844         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1845         if (ret != I40E_SUCCESS) {
1846                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1847                 return;
1848         }
1849 }
1850
1851 /* Remove a MAC address, and update filters */
1852 static void
1853 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1854 {
1855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1856         struct i40e_vsi *vsi;
1857         struct rte_eth_dev_data *data = dev->data;
1858         struct ether_addr *macaddr;
1859         int ret;
1860         uint32_t i;
1861         uint64_t pool_sel;
1862
1863         macaddr = &(data->mac_addrs[index]);
1864
1865         pool_sel = dev->data->mac_pool_sel[index];
1866
1867         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1868                 if (pool_sel & (1ULL << i)) {
1869                         if (i == 0)
1870                                 vsi = pf->main_vsi;
1871                         else {
1872                                 /* No VMDQ pool enabled or configured */
1873                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1874                                         (i > pf->nb_cfg_vmdq_vsi)) {
1875                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1876                                                         "/configured");
1877                                         return;
1878                                 }
1879                                 vsi = pf->vmdq[i - 1].vsi;
1880                         }
1881                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1882
1883                         if (ret) {
1884                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1885                                 return;
1886                         }
1887                 }
1888         }
1889 }
1890
1891 /* Set perfect match or hash match of MAC and VLAN for a VF */
1892 static int
1893 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1894                  struct rte_eth_mac_filter *filter,
1895                  bool add)
1896 {
1897         struct i40e_hw *hw;
1898         struct i40e_mac_filter_info mac_filter;
1899         struct ether_addr old_mac;
1900         struct ether_addr *new_mac;
1901         struct i40e_pf_vf *vf = NULL;
1902         uint16_t vf_id;
1903         int ret;
1904
1905         if (pf == NULL) {
1906                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1907                 return -EINVAL;
1908         }
1909         hw = I40E_PF_TO_HW(pf);
1910
1911         if (filter == NULL) {
1912                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1913                 return -EINVAL;
1914         }
1915
1916         new_mac = &filter->mac_addr;
1917
1918         if (is_zero_ether_addr(new_mac)) {
1919                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1920                 return -EINVAL;
1921         }
1922
1923         vf_id = filter->dst_id;
1924
1925         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1926                 PMD_DRV_LOG(ERR, "Invalid argument.");
1927                 return -EINVAL;
1928         }
1929         vf = &pf->vfs[vf_id];
1930
1931         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1932                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1933                 return -EINVAL;
1934         }
1935
1936         if (add) {
1937                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1938                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1939                                 ETHER_ADDR_LEN);
1940                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1941                                  ETHER_ADDR_LEN);
1942
1943                 mac_filter.filter_type = filter->filter_type;
1944                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1945                 if (ret != I40E_SUCCESS) {
1946                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1947                         return -1;
1948                 }
1949                 ether_addr_copy(new_mac, &pf->dev_addr);
1950         } else {
1951                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1952                                 ETHER_ADDR_LEN);
1953                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1954                 if (ret != I40E_SUCCESS) {
1955                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1956                         return -1;
1957                 }
1958
1959                 /* Clear device address as it has been removed */
1960                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1961                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1962         }
1963
1964         return 0;
1965 }
1966
1967 /* MAC filter handle */
1968 static int
1969 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1970                 void *arg)
1971 {
1972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1973         struct rte_eth_mac_filter *filter;
1974         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1975         int ret = I40E_NOT_SUPPORTED;
1976
1977         filter = (struct rte_eth_mac_filter *)(arg);
1978
1979         switch (filter_op) {
1980         case RTE_ETH_FILTER_NOP:
1981                 ret = I40E_SUCCESS;
1982                 break;
1983         case RTE_ETH_FILTER_ADD:
1984                 i40e_pf_disable_irq0(hw);
1985                 if (filter->is_vf)
1986                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1987                 i40e_pf_enable_irq0(hw);
1988                 break;
1989         case RTE_ETH_FILTER_DELETE:
1990                 i40e_pf_disable_irq0(hw);
1991                 if (filter->is_vf)
1992                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1993                 i40e_pf_enable_irq0(hw);
1994                 break;
1995         default:
1996                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1997                 ret = I40E_ERR_PARAM;
1998                 break;
1999         }
2000
2001         return ret;
2002 }
2003
2004 static int
2005 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2006                          struct rte_eth_rss_reta_entry64 *reta_conf,
2007                          uint16_t reta_size)
2008 {
2009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2010         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011         uint32_t lut, l;
2012         uint16_t i, j, lut_size = pf->hash_lut_size;
2013         uint16_t idx, shift;
2014         uint8_t mask;
2015
2016         if (reta_size != lut_size ||
2017                 reta_size > ETH_RSS_RETA_SIZE_512) {
2018                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2019                         "(%d) doesn't match the number hardware can supported "
2020                                         "(%d)\n", reta_size, lut_size);
2021                 return -EINVAL;
2022         }
2023
2024         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2025                 idx = i / RTE_RETA_GROUP_SIZE;
2026                 shift = i % RTE_RETA_GROUP_SIZE;
2027                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2028                                                 I40E_4_BIT_MASK);
2029                 if (!mask)
2030                         continue;
2031                 if (mask == I40E_4_BIT_MASK)
2032                         l = 0;
2033                 else
2034                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2035                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2036                         if (mask & (0x1 << j))
2037                                 lut |= reta_conf[idx].reta[shift + j] <<
2038                                                         (CHAR_BIT * j);
2039                         else
2040                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2041                 }
2042                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2043         }
2044
2045         return 0;
2046 }
2047
2048 static int
2049 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2050                         struct rte_eth_rss_reta_entry64 *reta_conf,
2051                         uint16_t reta_size)
2052 {
2053         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055         uint32_t lut;
2056         uint16_t i, j, lut_size = pf->hash_lut_size;
2057         uint16_t idx, shift;
2058         uint8_t mask;
2059
2060         if (reta_size != lut_size ||
2061                 reta_size > ETH_RSS_RETA_SIZE_512) {
2062                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2063                         "(%d) doesn't match the number hardware can supported "
2064                                         "(%d)\n", reta_size, lut_size);
2065                 return -EINVAL;
2066         }
2067
2068         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2069                 idx = i / RTE_RETA_GROUP_SIZE;
2070                 shift = i % RTE_RETA_GROUP_SIZE;
2071                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2072                                                 I40E_4_BIT_MASK);
2073                 if (!mask)
2074                         continue;
2075
2076                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2077                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2078                         if (mask & (0x1 << j))
2079                                 reta_conf[idx].reta[shift + j] = ((lut >>
2080                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2081                 }
2082         }
2083
2084         return 0;
2085 }
2086
2087 /**
2088  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2089  * @hw:   pointer to the HW structure
2090  * @mem:  pointer to mem struct to fill out
2091  * @size: size of memory requested
2092  * @alignment: what to align the allocation to
2093  **/
2094 enum i40e_status_code
2095 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2096                         struct i40e_dma_mem *mem,
2097                         u64 size,
2098                         u32 alignment)
2099 {
2100         static uint64_t id = 0;
2101         const struct rte_memzone *mz = NULL;
2102         char z_name[RTE_MEMZONE_NAMESIZE];
2103
2104         if (!mem)
2105                 return I40E_ERR_PARAM;
2106
2107         id++;
2108         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2109 #ifdef RTE_LIBRTE_XEN_DOM0
2110         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2111                                                         RTE_PGSIZE_2M);
2112 #else
2113         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2114 #endif
2115         if (!mz)
2116                 return I40E_ERR_NO_MEMORY;
2117
2118         mem->id = id;
2119         mem->size = size;
2120         mem->va = mz->addr;
2121 #ifdef RTE_LIBRTE_XEN_DOM0
2122         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2123 #else
2124         mem->pa = mz->phys_addr;
2125 #endif
2126
2127         return I40E_SUCCESS;
2128 }
2129
2130 /**
2131  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2132  * @hw:   pointer to the HW structure
2133  * @mem:  ptr to mem struct to free
2134  **/
2135 enum i40e_status_code
2136 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2137                     struct i40e_dma_mem *mem)
2138 {
2139         if (!mem || !mem->va)
2140                 return I40E_ERR_PARAM;
2141
2142         mem->va = NULL;
2143         mem->pa = (u64)0;
2144
2145         return I40E_SUCCESS;
2146 }
2147
2148 /**
2149  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2150  * @hw:   pointer to the HW structure
2151  * @mem:  pointer to mem struct to fill out
2152  * @size: size of memory requested
2153  **/
2154 enum i40e_status_code
2155 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2156                          struct i40e_virt_mem *mem,
2157                          u32 size)
2158 {
2159         if (!mem)
2160                 return I40E_ERR_PARAM;
2161
2162         mem->size = size;
2163         mem->va = rte_zmalloc("i40e", size, 0);
2164
2165         if (mem->va)
2166                 return I40E_SUCCESS;
2167         else
2168                 return I40E_ERR_NO_MEMORY;
2169 }
2170
2171 /**
2172  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2173  * @hw:   pointer to the HW structure
2174  * @mem:  pointer to mem struct to free
2175  **/
2176 enum i40e_status_code
2177 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2178                      struct i40e_virt_mem *mem)
2179 {
2180         if (!mem)
2181                 return I40E_ERR_PARAM;
2182
2183         rte_free(mem->va);
2184         mem->va = NULL;
2185
2186         return I40E_SUCCESS;
2187 }
2188
2189 void
2190 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2191 {
2192         rte_spinlock_init(&sp->spinlock);
2193 }
2194
2195 void
2196 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2197 {
2198         rte_spinlock_lock(&sp->spinlock);
2199 }
2200
2201 void
2202 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2203 {
2204         rte_spinlock_unlock(&sp->spinlock);
2205 }
2206
2207 void
2208 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2209 {
2210         return;
2211 }
2212
2213 /**
2214  * Get the hardware capabilities, which will be parsed
2215  * and saved into struct i40e_hw.
2216  */
2217 static int
2218 i40e_get_cap(struct i40e_hw *hw)
2219 {
2220         struct i40e_aqc_list_capabilities_element_resp *buf;
2221         uint16_t len, size = 0;
2222         int ret;
2223
2224         /* Calculate a huge enough buff for saving response data temporarily */
2225         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2226                                                 I40E_MAX_CAP_ELE_NUM;
2227         buf = rte_zmalloc("i40e", len, 0);
2228         if (!buf) {
2229                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2230                 return I40E_ERR_NO_MEMORY;
2231         }
2232
2233         /* Get, parse the capabilities and save it to hw */
2234         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2235                         i40e_aqc_opc_list_func_capabilities, NULL);
2236         if (ret != I40E_SUCCESS)
2237                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2238
2239         /* Free the temporary buffer after being used */
2240         rte_free(buf);
2241
2242         return ret;
2243 }
2244
2245 static int
2246 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2247 {
2248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2249         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2250         uint16_t sum_queues = 0, sum_vsis, left_queues;
2251
2252         /* First check if FW support SRIOV */
2253         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2254                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2255                 return -EINVAL;
2256         }
2257
2258         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2259         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2260         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2261         /* Allocate queues for pf */
2262         if (hw->func_caps.rss) {
2263                 pf->flags |= I40E_FLAG_RSS;
2264                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2265                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2266                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2267         } else
2268                 pf->lan_nb_qps = 1;
2269         sum_queues = pf->lan_nb_qps;
2270         /* Default VSI is not counted in */
2271         sum_vsis = 0;
2272         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2273
2274         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2275                 pf->flags |= I40E_FLAG_SRIOV;
2276                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2277                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2278                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2279                                      "max supported %u.",
2280                                      dev->pci_dev->max_vfs,
2281                                      hw->func_caps.num_vfs);
2282                         return -EINVAL;
2283                 }
2284                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2285                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2286                                      "max support %u queues.",
2287                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2288                         return -EINVAL;
2289                 }
2290                 pf->vf_num = dev->pci_dev->max_vfs;
2291                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2292                 sum_vsis   += pf->vf_num;
2293                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2294                              pf->vf_num, pf->vf_nb_qps);
2295         } else
2296                 pf->vf_num = 0;
2297
2298         if (hw->func_caps.vmdq) {
2299                 pf->flags |= I40E_FLAG_VMDQ;
2300                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2301                 pf->max_nb_vmdq_vsi = 1;
2302                 /*
2303                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2304                  * later.
2305                  */
2306                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2307                 sum_vsis += pf->max_nb_vmdq_vsi;
2308         } else {
2309                 pf->vmdq_nb_qps = 0;
2310                 pf->max_nb_vmdq_vsi = 0;
2311         }
2312         pf->nb_cfg_vmdq_vsi = 0;
2313
2314         if (hw->func_caps.fd) {
2315                 pf->flags |= I40E_FLAG_FDIR;
2316                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2317                 /**
2318                  * Each flow director consumes one VSI and one queue,
2319                  * but can't calculate out predictably here.
2320                  */
2321         }
2322
2323         if (sum_vsis > pf->max_num_vsi ||
2324                 sum_queues > hw->func_caps.num_rx_qp) {
2325                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2326                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2327                              pf->max_num_vsi, sum_vsis);
2328                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2329                              hw->func_caps.num_rx_qp, sum_queues);
2330                 return -EINVAL;
2331         }
2332
2333         /* Adjust VMDQ setting to support as many VMs as possible */
2334         if (pf->flags & I40E_FLAG_VMDQ) {
2335                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2336
2337                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2338                                         pf->max_num_vsi - sum_vsis);
2339
2340                 /* Limit the max VMDQ number that rte_ether that can support  */
2341                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2342                                         ETH_64_POOLS - 1);
2343
2344                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2345                                 pf->max_nb_vmdq_vsi);
2346                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2347         }
2348
2349         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2350          * cause */
2351         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2352                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2353                              sum_vsis, hw->func_caps.num_msix_vectors);
2354                 return -EINVAL;
2355         }
2356         return I40E_SUCCESS;
2357 }
2358
2359 static int
2360 i40e_pf_get_switch_config(struct i40e_pf *pf)
2361 {
2362         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2363         struct i40e_aqc_get_switch_config_resp *switch_config;
2364         struct i40e_aqc_switch_config_element_resp *element;
2365         uint16_t start_seid = 0, num_reported;
2366         int ret;
2367
2368         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2369                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2370         if (!switch_config) {
2371                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2372                 return -ENOMEM;
2373         }
2374
2375         /* Get the switch configurations */
2376         ret = i40e_aq_get_switch_config(hw, switch_config,
2377                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2378         if (ret != I40E_SUCCESS) {
2379                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2380                 goto fail;
2381         }
2382         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2383         if (num_reported != 1) { /* The number should be 1 */
2384                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2385                 goto fail;
2386         }
2387
2388         /* Parse the switch configuration elements */
2389         element = &(switch_config->element[0]);
2390         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2391                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2392                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2393         } else
2394                 PMD_DRV_LOG(INFO, "Unknown element type");
2395
2396 fail:
2397         rte_free(switch_config);
2398
2399         return ret;
2400 }
2401
2402 static int
2403 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2404                         uint32_t num)
2405 {
2406         struct pool_entry *entry;
2407
2408         if (pool == NULL || num == 0)
2409                 return -EINVAL;
2410
2411         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2412         if (entry == NULL) {
2413                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2414                 return -ENOMEM;
2415         }
2416
2417         /* queue heap initialize */
2418         pool->num_free = num;
2419         pool->num_alloc = 0;
2420         pool->base = base;
2421         LIST_INIT(&pool->alloc_list);
2422         LIST_INIT(&pool->free_list);
2423
2424         /* Initialize element  */
2425         entry->base = 0;
2426         entry->len = num;
2427
2428         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2429         return 0;
2430 }
2431
2432 static void
2433 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2434 {
2435         struct pool_entry *entry;
2436
2437         if (pool == NULL)
2438                 return;
2439
2440         LIST_FOREACH(entry, &pool->alloc_list, next) {
2441                 LIST_REMOVE(entry, next);
2442                 rte_free(entry);
2443         }
2444
2445         LIST_FOREACH(entry, &pool->free_list, next) {
2446                 LIST_REMOVE(entry, next);
2447                 rte_free(entry);
2448         }
2449
2450         pool->num_free = 0;
2451         pool->num_alloc = 0;
2452         pool->base = 0;
2453         LIST_INIT(&pool->alloc_list);
2454         LIST_INIT(&pool->free_list);
2455 }
2456
2457 static int
2458 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2459                        uint32_t base)
2460 {
2461         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2462         uint32_t pool_offset;
2463         int insert;
2464
2465         if (pool == NULL) {
2466                 PMD_DRV_LOG(ERR, "Invalid parameter");
2467                 return -EINVAL;
2468         }
2469
2470         pool_offset = base - pool->base;
2471         /* Lookup in alloc list */
2472         LIST_FOREACH(entry, &pool->alloc_list, next) {
2473                 if (entry->base == pool_offset) {
2474                         valid_entry = entry;
2475                         LIST_REMOVE(entry, next);
2476                         break;
2477                 }
2478         }
2479
2480         /* Not find, return */
2481         if (valid_entry == NULL) {
2482                 PMD_DRV_LOG(ERR, "Failed to find entry");
2483                 return -EINVAL;
2484         }
2485
2486         /**
2487          * Found it, move it to free list  and try to merge.
2488          * In order to make merge easier, always sort it by qbase.
2489          * Find adjacent prev and last entries.
2490          */
2491         prev = next = NULL;
2492         LIST_FOREACH(entry, &pool->free_list, next) {
2493                 if (entry->base > valid_entry->base) {
2494                         next = entry;
2495                         break;
2496                 }
2497                 prev = entry;
2498         }
2499
2500         insert = 0;
2501         /* Try to merge with next one*/
2502         if (next != NULL) {
2503                 /* Merge with next one */
2504                 if (valid_entry->base + valid_entry->len == next->base) {
2505                         next->base = valid_entry->base;
2506                         next->len += valid_entry->len;
2507                         rte_free(valid_entry);
2508                         valid_entry = next;
2509                         insert = 1;
2510                 }
2511         }
2512
2513         if (prev != NULL) {
2514                 /* Merge with previous one */
2515                 if (prev->base + prev->len == valid_entry->base) {
2516                         prev->len += valid_entry->len;
2517                         /* If it merge with next one, remove next node */
2518                         if (insert == 1) {
2519                                 LIST_REMOVE(valid_entry, next);
2520                                 rte_free(valid_entry);
2521                         } else {
2522                                 rte_free(valid_entry);
2523                                 insert = 1;
2524                         }
2525                 }
2526         }
2527
2528         /* Not find any entry to merge, insert */
2529         if (insert == 0) {
2530                 if (prev != NULL)
2531                         LIST_INSERT_AFTER(prev, valid_entry, next);
2532                 else if (next != NULL)
2533                         LIST_INSERT_BEFORE(next, valid_entry, next);
2534                 else /* It's empty list, insert to head */
2535                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2536         }
2537
2538         pool->num_free += valid_entry->len;
2539         pool->num_alloc -= valid_entry->len;
2540
2541         return 0;
2542 }
2543
2544 static int
2545 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2546                        uint16_t num)
2547 {
2548         struct pool_entry *entry, *valid_entry;
2549
2550         if (pool == NULL || num == 0) {
2551                 PMD_DRV_LOG(ERR, "Invalid parameter");
2552                 return -EINVAL;
2553         }
2554
2555         if (pool->num_free < num) {
2556                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2557                             num, pool->num_free);
2558                 return -ENOMEM;
2559         }
2560
2561         valid_entry = NULL;
2562         /* Lookup  in free list and find most fit one */
2563         LIST_FOREACH(entry, &pool->free_list, next) {
2564                 if (entry->len >= num) {
2565                         /* Find best one */
2566                         if (entry->len == num) {
2567                                 valid_entry = entry;
2568                                 break;
2569                         }
2570                         if (valid_entry == NULL || valid_entry->len > entry->len)
2571                                 valid_entry = entry;
2572                 }
2573         }
2574
2575         /* Not find one to satisfy the request, return */
2576         if (valid_entry == NULL) {
2577                 PMD_DRV_LOG(ERR, "No valid entry found");
2578                 return -ENOMEM;
2579         }
2580         /**
2581          * The entry have equal queue number as requested,
2582          * remove it from alloc_list.
2583          */
2584         if (valid_entry->len == num) {
2585                 LIST_REMOVE(valid_entry, next);
2586         } else {
2587                 /**
2588                  * The entry have more numbers than requested,
2589                  * create a new entry for alloc_list and minus its
2590                  * queue base and number in free_list.
2591                  */
2592                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2593                 if (entry == NULL) {
2594                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2595                                     "resource pool");
2596                         return -ENOMEM;
2597                 }
2598                 entry->base = valid_entry->base;
2599                 entry->len = num;
2600                 valid_entry->base += num;
2601                 valid_entry->len -= num;
2602                 valid_entry = entry;
2603         }
2604
2605         /* Insert it into alloc list, not sorted */
2606         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2607
2608         pool->num_free -= valid_entry->len;
2609         pool->num_alloc += valid_entry->len;
2610
2611         return (valid_entry->base + pool->base);
2612 }
2613
2614 /**
2615  * bitmap_is_subset - Check whether src2 is subset of src1
2616  **/
2617 static inline int
2618 bitmap_is_subset(uint8_t src1, uint8_t src2)
2619 {
2620         return !((src1 ^ src2) & src2);
2621 }
2622
2623 static int
2624 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2625 {
2626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2627
2628         /* If DCB is not supported, only default TC is supported */
2629         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2630                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2631                 return -EINVAL;
2632         }
2633
2634         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2635                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2636                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2637                             enabled_tcmap);
2638                 return -EINVAL;
2639         }
2640         return I40E_SUCCESS;
2641 }
2642
2643 int
2644 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2645                                 struct i40e_vsi_vlan_pvid_info *info)
2646 {
2647         struct i40e_hw *hw;
2648         struct i40e_vsi_context ctxt;
2649         uint8_t vlan_flags = 0;
2650         int ret;
2651
2652         if (vsi == NULL || info == NULL) {
2653                 PMD_DRV_LOG(ERR, "invalid parameters");
2654                 return I40E_ERR_PARAM;
2655         }
2656
2657         if (info->on) {
2658                 vsi->info.pvid = info->config.pvid;
2659                 /**
2660                  * If insert pvid is enabled, only tagged pkts are
2661                  * allowed to be sent out.
2662                  */
2663                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2664                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2665         } else {
2666                 vsi->info.pvid = 0;
2667                 if (info->config.reject.tagged == 0)
2668                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2669
2670                 if (info->config.reject.untagged == 0)
2671                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2672         }
2673         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2674                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2675         vsi->info.port_vlan_flags |= vlan_flags;
2676         vsi->info.valid_sections =
2677                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2678         memset(&ctxt, 0, sizeof(ctxt));
2679         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2680         ctxt.seid = vsi->seid;
2681
2682         hw = I40E_VSI_TO_HW(vsi);
2683         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2684         if (ret != I40E_SUCCESS)
2685                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2686
2687         return ret;
2688 }
2689
2690 static int
2691 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2692 {
2693         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2694         int i, ret;
2695         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2696
2697         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2698         if (ret != I40E_SUCCESS)
2699                 return ret;
2700
2701         if (!vsi->seid) {
2702                 PMD_DRV_LOG(ERR, "seid not valid");
2703                 return -EINVAL;
2704         }
2705
2706         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2707         tc_bw_data.tc_valid_bits = enabled_tcmap;
2708         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2709                 tc_bw_data.tc_bw_credits[i] =
2710                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2711
2712         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2713         if (ret != I40E_SUCCESS) {
2714                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2715                 return ret;
2716         }
2717
2718         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2719                                         sizeof(vsi->info.qs_handle));
2720         return I40E_SUCCESS;
2721 }
2722
2723 static int
2724 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2725                                  struct i40e_aqc_vsi_properties_data *info,
2726                                  uint8_t enabled_tcmap)
2727 {
2728         int ret, total_tc = 0, i;
2729         uint16_t qpnum_per_tc, bsf, qp_idx;
2730
2731         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2732         if (ret != I40E_SUCCESS)
2733                 return ret;
2734
2735         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2736                 if (enabled_tcmap & (1 << i))
2737                         total_tc++;
2738         vsi->enabled_tc = enabled_tcmap;
2739
2740         /* Number of queues per enabled TC */
2741         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2742         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2743         bsf = rte_bsf32(qpnum_per_tc);
2744
2745         /* Adjust the queue number to actual queues that can be applied */
2746         vsi->nb_qps = qpnum_per_tc * total_tc;
2747
2748         /**
2749          * Configure TC and queue mapping parameters, for enabled TC,
2750          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2751          * default queue will serve it.
2752          */
2753         qp_idx = 0;
2754         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2755                 if (vsi->enabled_tc & (1 << i)) {
2756                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2757                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2758                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2759                         qp_idx += qpnum_per_tc;
2760                 } else
2761                         info->tc_mapping[i] = 0;
2762         }
2763
2764         /* Associate queue number with VSI */
2765         if (vsi->type == I40E_VSI_SRIOV) {
2766                 info->mapping_flags |=
2767                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2768                 for (i = 0; i < vsi->nb_qps; i++)
2769                         info->queue_mapping[i] =
2770                                 rte_cpu_to_le_16(vsi->base_queue + i);
2771         } else {
2772                 info->mapping_flags |=
2773                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2774                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2775         }
2776         info->valid_sections |=
2777                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2778
2779         return I40E_SUCCESS;
2780 }
2781
2782 static int
2783 i40e_veb_release(struct i40e_veb *veb)
2784 {
2785         struct i40e_vsi *vsi;
2786         struct i40e_hw *hw;
2787
2788         if (veb == NULL || veb->associate_vsi == NULL)
2789                 return -EINVAL;
2790
2791         if (!TAILQ_EMPTY(&veb->head)) {
2792                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2793                 return -EACCES;
2794         }
2795
2796         vsi = veb->associate_vsi;
2797         hw = I40E_VSI_TO_HW(vsi);
2798
2799         vsi->uplink_seid = veb->uplink_seid;
2800         i40e_aq_delete_element(hw, veb->seid, NULL);
2801         rte_free(veb);
2802         vsi->veb = NULL;
2803         return I40E_SUCCESS;
2804 }
2805
2806 /* Setup a veb */
2807 static struct i40e_veb *
2808 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2809 {
2810         struct i40e_veb *veb;
2811         int ret;
2812         struct i40e_hw *hw;
2813
2814         if (NULL == pf || vsi == NULL) {
2815                 PMD_DRV_LOG(ERR, "veb setup failed, "
2816                             "associated VSI shouldn't null");
2817                 return NULL;
2818         }
2819         hw = I40E_PF_TO_HW(pf);
2820
2821         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2822         if (!veb) {
2823                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2824                 goto fail;
2825         }
2826
2827         veb->associate_vsi = vsi;
2828         TAILQ_INIT(&veb->head);
2829         veb->uplink_seid = vsi->uplink_seid;
2830
2831         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2832                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2833
2834         if (ret != I40E_SUCCESS) {
2835                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2836                             hw->aq.asq_last_status);
2837                 goto fail;
2838         }
2839
2840         /* get statistics index */
2841         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2842                                 &veb->stats_idx, NULL, NULL, NULL);
2843         if (ret != I40E_SUCCESS) {
2844                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2845                             hw->aq.asq_last_status);
2846                 goto fail;
2847         }
2848
2849         /* Get VEB bandwidth, to be implemented */
2850         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2851         vsi->uplink_seid = veb->seid;
2852
2853         return veb;
2854 fail:
2855         rte_free(veb);
2856         return NULL;
2857 }
2858
2859 int
2860 i40e_vsi_release(struct i40e_vsi *vsi)
2861 {
2862         struct i40e_pf *pf;
2863         struct i40e_hw *hw;
2864         struct i40e_vsi_list *vsi_list;
2865         int ret;
2866         struct i40e_mac_filter *f;
2867
2868         if (!vsi)
2869                 return I40E_SUCCESS;
2870
2871         pf = I40E_VSI_TO_PF(vsi);
2872         hw = I40E_VSI_TO_HW(vsi);
2873
2874         /* VSI has child to attach, release child first */
2875         if (vsi->veb) {
2876                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2877                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2878                                 return -1;
2879                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2880                 }
2881                 i40e_veb_release(vsi->veb);
2882         }
2883
2884         /* Remove all macvlan filters of the VSI */
2885         i40e_vsi_remove_all_macvlan_filter(vsi);
2886         TAILQ_FOREACH(f, &vsi->mac_list, next)
2887                 rte_free(f);
2888
2889         if (vsi->type != I40E_VSI_MAIN) {
2890                 /* Remove vsi from parent's sibling list */
2891                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2892                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2893                         return I40E_ERR_PARAM;
2894                 }
2895                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2896                                 &vsi->sib_vsi_list, list);
2897
2898                 /* Remove all switch element of the VSI */
2899                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2900                 if (ret != I40E_SUCCESS)
2901                         PMD_DRV_LOG(ERR, "Failed to delete element");
2902         }
2903         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2904
2905         if (vsi->type != I40E_VSI_SRIOV)
2906                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2907         rte_free(vsi);
2908
2909         return I40E_SUCCESS;
2910 }
2911
2912 static int
2913 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2914 {
2915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2916         struct i40e_aqc_remove_macvlan_element_data def_filter;
2917         struct i40e_mac_filter_info filter;
2918         int ret;
2919
2920         if (vsi->type != I40E_VSI_MAIN)
2921                 return I40E_ERR_CONFIG;
2922         memset(&def_filter, 0, sizeof(def_filter));
2923         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2924                                         ETH_ADDR_LEN);
2925         def_filter.vlan_tag = 0;
2926         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2927                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2928         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2929         if (ret != I40E_SUCCESS) {
2930                 struct i40e_mac_filter *f;
2931                 struct ether_addr *mac;
2932
2933                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2934                             "macvlan filter");
2935                 /* It needs to add the permanent mac into mac list */
2936                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2937                 if (f == NULL) {
2938                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2939                         return I40E_ERR_NO_MEMORY;
2940                 }
2941                 mac = &f->mac_info.mac_addr;
2942                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2943                                 ETH_ADDR_LEN);
2944                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2945                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2946                 vsi->mac_num++;
2947
2948                 return ret;
2949         }
2950         (void)rte_memcpy(&filter.mac_addr,
2951                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2952         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2953         return i40e_vsi_add_mac(vsi, &filter);
2954 }
2955
2956 static int
2957 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2958 {
2959         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2960         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2961         struct i40e_hw *hw = &vsi->adapter->hw;
2962         i40e_status ret;
2963         int i;
2964
2965         memset(&bw_config, 0, sizeof(bw_config));
2966         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2967         if (ret != I40E_SUCCESS) {
2968                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2969                             hw->aq.asq_last_status);
2970                 return ret;
2971         }
2972
2973         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2974         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2975                                         &ets_sla_config, NULL);
2976         if (ret != I40E_SUCCESS) {
2977                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2978                             "configuration %u", hw->aq.asq_last_status);
2979                 return ret;
2980         }
2981
2982         /* Not store the info yet, just print out */
2983         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2984         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2985         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2986                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2987                             ets_sla_config.share_credits[i]);
2988                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2989                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2990                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2991                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2992                             (i * 4));
2993         }
2994
2995         return 0;
2996 }
2997
2998 /* Setup a VSI */
2999 struct i40e_vsi *
3000 i40e_vsi_setup(struct i40e_pf *pf,
3001                enum i40e_vsi_type type,
3002                struct i40e_vsi *uplink_vsi,
3003                uint16_t user_param)
3004 {
3005         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3006         struct i40e_vsi *vsi;
3007         struct i40e_mac_filter_info filter;
3008         int ret;
3009         struct i40e_vsi_context ctxt;
3010         struct ether_addr broadcast =
3011                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3012
3013         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3014                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3015                             "VSI link shouldn't be NULL");
3016                 return NULL;
3017         }
3018
3019         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3020                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3021                             "uplink VSI should be NULL");
3022                 return NULL;
3023         }
3024
3025         /* If uplink vsi didn't setup VEB, create one first */
3026         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3027                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3028
3029                 if (NULL == uplink_vsi->veb) {
3030                         PMD_DRV_LOG(ERR, "VEB setup failed");
3031                         return NULL;
3032                 }
3033         }
3034
3035         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3036         if (!vsi) {
3037                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3038                 return NULL;
3039         }
3040         TAILQ_INIT(&vsi->mac_list);
3041         vsi->type = type;
3042         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3043         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3044         vsi->parent_vsi = uplink_vsi;
3045         vsi->user_param = user_param;
3046         /* Allocate queues */
3047         switch (vsi->type) {
3048         case I40E_VSI_MAIN  :
3049                 vsi->nb_qps = pf->lan_nb_qps;
3050                 break;
3051         case I40E_VSI_SRIOV :
3052                 vsi->nb_qps = pf->vf_nb_qps;
3053                 break;
3054         case I40E_VSI_VMDQ2:
3055                 vsi->nb_qps = pf->vmdq_nb_qps;
3056                 break;
3057         case I40E_VSI_FDIR:
3058                 vsi->nb_qps = pf->fdir_nb_qps;
3059                 break;
3060         default:
3061                 goto fail_mem;
3062         }
3063         /*
3064          * The filter status descriptor is reported in rx queue 0,
3065          * while the tx queue for fdir filter programming has no
3066          * such constraints, can be non-zero queues.
3067          * To simplify it, choose FDIR vsi use queue 0 pair.
3068          * To make sure it will use queue 0 pair, queue allocation
3069          * need be done before this function is called
3070          */
3071         if (type != I40E_VSI_FDIR) {
3072                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3073                         if (ret < 0) {
3074                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3075                                                 vsi->seid, ret);
3076                                 goto fail_mem;
3077                         }
3078                         vsi->base_queue = ret;
3079         } else
3080                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3081
3082         /* VF has MSIX interrupt in VF range, don't allocate here */
3083         if (type != I40E_VSI_SRIOV) {
3084                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3085                 if (ret < 0) {
3086                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3087                         goto fail_queue_alloc;
3088                 }
3089                 vsi->msix_intr = ret;
3090         } else
3091                 vsi->msix_intr = 0;
3092         /* Add VSI */
3093         if (type == I40E_VSI_MAIN) {
3094                 /* For main VSI, no need to add since it's default one */
3095                 vsi->uplink_seid = pf->mac_seid;
3096                 vsi->seid = pf->main_vsi_seid;
3097                 /* Bind queues with specific MSIX interrupt */
3098                 /**
3099                  * Needs 2 interrupt at least, one for misc cause which will
3100                  * enabled from OS side, Another for queues binding the
3101                  * interrupt from device side only.
3102                  */
3103
3104                 /* Get default VSI parameters from hardware */
3105                 memset(&ctxt, 0, sizeof(ctxt));
3106                 ctxt.seid = vsi->seid;
3107                 ctxt.pf_num = hw->pf_id;
3108                 ctxt.uplink_seid = vsi->uplink_seid;
3109                 ctxt.vf_num = 0;
3110                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3111                 if (ret != I40E_SUCCESS) {
3112                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3113                         goto fail_msix_alloc;
3114                 }
3115                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3116                         sizeof(struct i40e_aqc_vsi_properties_data));
3117                 vsi->vsi_id = ctxt.vsi_number;
3118                 vsi->info.valid_sections = 0;
3119
3120                 /* Configure tc, enabled TC0 only */
3121                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3122                         I40E_SUCCESS) {
3123                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3124                         goto fail_msix_alloc;
3125                 }
3126
3127                 /* TC, queue mapping */
3128                 memset(&ctxt, 0, sizeof(ctxt));
3129                 vsi->info.valid_sections |=
3130                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3131                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3132                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3133                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3134                         sizeof(struct i40e_aqc_vsi_properties_data));
3135                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3136                                                 I40E_DEFAULT_TCMAP);
3137                 if (ret != I40E_SUCCESS) {
3138                         PMD_DRV_LOG(ERR, "Failed to configure "
3139                                     "TC queue mapping");
3140                         goto fail_msix_alloc;
3141                 }
3142                 ctxt.seid = vsi->seid;
3143                 ctxt.pf_num = hw->pf_id;
3144                 ctxt.uplink_seid = vsi->uplink_seid;
3145                 ctxt.vf_num = 0;
3146
3147                 /* Update VSI parameters */
3148                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3149                 if (ret != I40E_SUCCESS) {
3150                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3151                         goto fail_msix_alloc;
3152                 }
3153
3154                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3155                                                 sizeof(vsi->info.tc_mapping));
3156                 (void)rte_memcpy(&vsi->info.queue_mapping,
3157                                 &ctxt.info.queue_mapping,
3158                         sizeof(vsi->info.queue_mapping));
3159                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3160                 vsi->info.valid_sections = 0;
3161
3162                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3163                                 ETH_ADDR_LEN);
3164
3165                 /**
3166                  * Updating default filter settings are necessary to prevent
3167                  * reception of tagged packets.
3168                  * Some old firmware configurations load a default macvlan
3169                  * filter which accepts both tagged and untagged packets.
3170                  * The updating is to use a normal filter instead if needed.
3171                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3172                  * The firmware with correct configurations load the default
3173                  * macvlan filter which is expected and cannot be removed.
3174                  */
3175                 i40e_update_default_filter_setting(vsi);
3176                 i40e_config_qinq(hw, vsi);
3177         } else if (type == I40E_VSI_SRIOV) {
3178                 memset(&ctxt, 0, sizeof(ctxt));
3179                 /**
3180                  * For other VSI, the uplink_seid equals to uplink VSI's
3181                  * uplink_seid since they share same VEB
3182                  */
3183                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3184                 ctxt.pf_num = hw->pf_id;
3185                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3186                 ctxt.uplink_seid = vsi->uplink_seid;
3187                 ctxt.connection_type = 0x1;
3188                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3189
3190                 /**
3191                  * Do not configure switch ID to enable VEB switch by
3192                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3193                  * if the source mac address of packet sent from VF is not
3194                  * listed in the VEB's mac table, the VEB will switch the
3195                  * packet back to the VF. Need to enable it when HW issue
3196                  * is fixed.
3197                  */
3198
3199                 /* Configure port/vlan */
3200                 ctxt.info.valid_sections |=
3201                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3202                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3203                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3204                                                 I40E_DEFAULT_TCMAP);
3205                 if (ret != I40E_SUCCESS) {
3206                         PMD_DRV_LOG(ERR, "Failed to configure "
3207                                     "TC queue mapping");
3208                         goto fail_msix_alloc;
3209                 }
3210                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3211                 ctxt.info.valid_sections |=
3212                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3213                 /**
3214                  * Since VSI is not created yet, only configure parameter,
3215                  * will add vsi below.
3216                  */
3217
3218                 i40e_config_qinq(hw, vsi);
3219         } else if (type == I40E_VSI_VMDQ2) {
3220                 memset(&ctxt, 0, sizeof(ctxt));
3221                 /*
3222                  * For other VSI, the uplink_seid equals to uplink VSI's
3223                  * uplink_seid since they share same VEB
3224                  */
3225                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3226                 ctxt.pf_num = hw->pf_id;
3227                 ctxt.vf_num = 0;
3228                 ctxt.uplink_seid = vsi->uplink_seid;
3229                 ctxt.connection_type = 0x1;
3230                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3231
3232                 ctxt.info.valid_sections |=
3233                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3234                 /* user_param carries flag to enable loop back */
3235                 if (user_param) {
3236                         ctxt.info.switch_id =
3237                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3238                         ctxt.info.switch_id |=
3239                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3240                 }
3241
3242                 /* Configure port/vlan */
3243                 ctxt.info.valid_sections |=
3244                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3245                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3246                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3247                                                 I40E_DEFAULT_TCMAP);
3248                 if (ret != I40E_SUCCESS) {
3249                         PMD_DRV_LOG(ERR, "Failed to configure "
3250                                         "TC queue mapping");
3251                         goto fail_msix_alloc;
3252                 }
3253                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3254                 ctxt.info.valid_sections |=
3255                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3256         } else if (type == I40E_VSI_FDIR) {
3257                 memset(&ctxt, 0, sizeof(ctxt));
3258                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3259                 ctxt.pf_num = hw->pf_id;
3260                 ctxt.vf_num = 0;
3261                 ctxt.uplink_seid = vsi->uplink_seid;
3262                 ctxt.connection_type = 0x1;     /* regular data port */
3263                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3264                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3265                                                 I40E_DEFAULT_TCMAP);
3266                 if (ret != I40E_SUCCESS) {
3267                         PMD_DRV_LOG(ERR, "Failed to configure "
3268                                         "TC queue mapping.");
3269                         goto fail_msix_alloc;
3270                 }
3271                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3272                 ctxt.info.valid_sections |=
3273                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3274         } else {
3275                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3276                 goto fail_msix_alloc;
3277         }
3278
3279         if (vsi->type != I40E_VSI_MAIN) {
3280                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3281                 if (ret != I40E_SUCCESS) {
3282                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3283                                     hw->aq.asq_last_status);
3284                         goto fail_msix_alloc;
3285                 }
3286                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3287                 vsi->info.valid_sections = 0;
3288                 vsi->seid = ctxt.seid;
3289                 vsi->vsi_id = ctxt.vsi_number;
3290                 vsi->sib_vsi_list.vsi = vsi;
3291                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3292                                 &vsi->sib_vsi_list, list);
3293         }
3294
3295         /* MAC/VLAN configuration */
3296         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3297         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3298
3299         ret = i40e_vsi_add_mac(vsi, &filter);
3300         if (ret != I40E_SUCCESS) {
3301                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3302                 goto fail_msix_alloc;
3303         }
3304
3305         /* Get VSI BW information */
3306         i40e_vsi_dump_bw_config(vsi);
3307         return vsi;
3308 fail_msix_alloc:
3309         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3310 fail_queue_alloc:
3311         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3312 fail_mem:
3313         rte_free(vsi);
3314         return NULL;
3315 }
3316
3317 /* Configure vlan stripping on or off */
3318 int
3319 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3320 {
3321         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3322         struct i40e_vsi_context ctxt;
3323         uint8_t vlan_flags;
3324         int ret = I40E_SUCCESS;
3325
3326         /* Check if it has been already on or off */
3327         if (vsi->info.valid_sections &
3328                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3329                 if (on) {
3330                         if ((vsi->info.port_vlan_flags &
3331                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3332                                 return 0; /* already on */
3333                 } else {
3334                         if ((vsi->info.port_vlan_flags &
3335                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3336                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3337                                 return 0; /* already off */
3338                 }
3339         }
3340
3341         if (on)
3342                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3343         else
3344                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3345         vsi->info.valid_sections =
3346                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3347         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3348         vsi->info.port_vlan_flags |= vlan_flags;
3349         ctxt.seid = vsi->seid;
3350         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3351         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3352         if (ret)
3353                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3354                             on ? "enable" : "disable");
3355
3356         return ret;
3357 }
3358
3359 static int
3360 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3361 {
3362         struct rte_eth_dev_data *data = dev->data;
3363         int ret;
3364
3365         /* Apply vlan offload setting */
3366         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3367
3368         /* Apply double-vlan setting, not implemented yet */
3369
3370         /* Apply pvid setting */
3371         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3372                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3373         if (ret)
3374                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3375
3376         return ret;
3377 }
3378
3379 static int
3380 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3381 {
3382         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3383
3384         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3385 }
3386
3387 static int
3388 i40e_update_flow_control(struct i40e_hw *hw)
3389 {
3390 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3391         struct i40e_link_status link_status;
3392         uint32_t rxfc = 0, txfc = 0, reg;
3393         uint8_t an_info;
3394         int ret;
3395
3396         memset(&link_status, 0, sizeof(link_status));
3397         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3398         if (ret != I40E_SUCCESS) {
3399                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3400                 goto write_reg; /* Disable flow control */
3401         }
3402
3403         an_info = hw->phy.link_info.an_info;
3404         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3405                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3406                 ret = I40E_ERR_NOT_READY;
3407                 goto write_reg; /* Disable flow control */
3408         }
3409         /**
3410          * If link auto negotiation is enabled, flow control needs to
3411          * be configured according to it
3412          */
3413         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3414         case I40E_LINK_PAUSE_RXTX:
3415                 rxfc = 1;
3416                 txfc = 1;
3417                 hw->fc.current_mode = I40E_FC_FULL;
3418                 break;
3419         case I40E_AQ_LINK_PAUSE_RX:
3420                 rxfc = 1;
3421                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3422                 break;
3423         case I40E_AQ_LINK_PAUSE_TX:
3424                 txfc = 1;
3425                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3426                 break;
3427         default:
3428                 hw->fc.current_mode = I40E_FC_NONE;
3429                 break;
3430         }
3431
3432 write_reg:
3433         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3434                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3435         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3436         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3437         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3438         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3439
3440         return ret;
3441 }
3442
3443 /* PF setup */
3444 static int
3445 i40e_pf_setup(struct i40e_pf *pf)
3446 {
3447         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3448         struct i40e_filter_control_settings settings;
3449         struct i40e_vsi *vsi;
3450         int ret;
3451
3452         /* Clear all stats counters */
3453         pf->offset_loaded = FALSE;
3454         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3455         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3456
3457         ret = i40e_pf_get_switch_config(pf);
3458         if (ret != I40E_SUCCESS) {
3459                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3460                 return ret;
3461         }
3462         if (pf->flags & I40E_FLAG_FDIR) {
3463                 /* make queue allocated first, let FDIR use queue pair 0*/
3464                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3465                 if (ret != I40E_FDIR_QUEUE_ID) {
3466                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3467                                     " ret =%d", ret);
3468                         pf->flags &= ~I40E_FLAG_FDIR;
3469                 }
3470         }
3471         /*  main VSI setup */
3472         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3473         if (!vsi) {
3474                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3475                 return I40E_ERR_NOT_READY;
3476         }
3477         pf->main_vsi = vsi;
3478
3479         /* Configure filter control */
3480         memset(&settings, 0, sizeof(settings));
3481         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3482                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3483         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3484                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3485         else {
3486                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3487                                                 hw->func_caps.rss_table_size);
3488                 return I40E_ERR_PARAM;
3489         }
3490         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3491                         "size: %u\n", hw->func_caps.rss_table_size);
3492         pf->hash_lut_size = hw->func_caps.rss_table_size;
3493
3494         /* Enable ethtype and macvlan filters */
3495         settings.enable_ethtype = TRUE;
3496         settings.enable_macvlan = TRUE;
3497         ret = i40e_set_filter_control(hw, &settings);
3498         if (ret)
3499                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3500                                                                 ret);
3501
3502         /* Update flow control according to the auto negotiation */
3503         i40e_update_flow_control(hw);
3504
3505         return I40E_SUCCESS;
3506 }
3507
3508 int
3509 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3510 {
3511         uint32_t reg;
3512         uint16_t j;
3513
3514         /**
3515          * Set or clear TX Queue Disable flags,
3516          * which is required by hardware.
3517          */
3518         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3519         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3520
3521         /* Wait until the request is finished */
3522         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3523                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3524                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3525                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3526                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3527                                                         & 0x1))) {
3528                         break;
3529                 }
3530         }
3531         if (on) {
3532                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3533                         return I40E_SUCCESS; /* already on, skip next steps */
3534
3535                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3536                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3537         } else {
3538                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3539                         return I40E_SUCCESS; /* already off, skip next steps */
3540                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3541         }
3542         /* Write the register */
3543         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3544         /* Check the result */
3545         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3546                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3547                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3548                 if (on) {
3549                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3550                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3551                                 break;
3552                 } else {
3553                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3554                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3555                                 break;
3556                 }
3557         }
3558         /* Check if it is timeout */
3559         if (j >= I40E_CHK_Q_ENA_COUNT) {
3560                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3561                             (on ? "enable" : "disable"), q_idx);
3562                 return I40E_ERR_TIMEOUT;
3563         }
3564
3565         return I40E_SUCCESS;
3566 }
3567
3568 /* Swith on or off the tx queues */
3569 static int
3570 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3571 {
3572         struct rte_eth_dev_data *dev_data = pf->dev_data;
3573         struct i40e_tx_queue *txq;
3574         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3575         uint16_t i;
3576         int ret;
3577
3578         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3579                 txq = dev_data->tx_queues[i];
3580                 /* Don't operate the queue if not configured or
3581                  * if starting only per queue */
3582                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3583                         continue;
3584                 if (on)
3585                         ret = i40e_dev_tx_queue_start(dev, i);
3586                 else
3587                         ret = i40e_dev_tx_queue_stop(dev, i);
3588                 if ( ret != I40E_SUCCESS)
3589                         return ret;
3590         }
3591
3592         return I40E_SUCCESS;
3593 }
3594
3595 int
3596 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3597 {
3598         uint32_t reg;
3599         uint16_t j;
3600
3601         /* Wait until the request is finished */
3602         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3603                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3604                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3605                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3606                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3607                         break;
3608         }
3609
3610         if (on) {
3611                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3612                         return I40E_SUCCESS; /* Already on, skip next steps */
3613                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3614         } else {
3615                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3616                         return I40E_SUCCESS; /* Already off, skip next steps */
3617                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3618         }
3619
3620         /* Write the register */
3621         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3622         /* Check the result */
3623         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3624                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3625                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3626                 if (on) {
3627                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3628                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3629                                 break;
3630                 } else {
3631                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3632                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3633                                 break;
3634                 }
3635         }
3636
3637         /* Check if it is timeout */
3638         if (j >= I40E_CHK_Q_ENA_COUNT) {
3639                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3640                             (on ? "enable" : "disable"), q_idx);
3641                 return I40E_ERR_TIMEOUT;
3642         }
3643
3644         return I40E_SUCCESS;
3645 }
3646 /* Switch on or off the rx queues */
3647 static int
3648 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3649 {
3650         struct rte_eth_dev_data *dev_data = pf->dev_data;
3651         struct i40e_rx_queue *rxq;
3652         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3653         uint16_t i;
3654         int ret;
3655
3656         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3657                 rxq = dev_data->rx_queues[i];
3658                 /* Don't operate the queue if not configured or
3659                  * if starting only per queue */
3660                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3661                         continue;
3662                 if (on)
3663                         ret = i40e_dev_rx_queue_start(dev, i);
3664                 else
3665                         ret = i40e_dev_rx_queue_stop(dev, i);
3666                 if (ret != I40E_SUCCESS)
3667                         return ret;
3668         }
3669
3670         return I40E_SUCCESS;
3671 }
3672
3673 /* Switch on or off all the rx/tx queues */
3674 int
3675 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3676 {
3677         int ret;
3678
3679         if (on) {
3680                 /* enable rx queues before enabling tx queues */
3681                 ret = i40e_dev_switch_rx_queues(pf, on);
3682                 if (ret) {
3683                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3684                         return ret;
3685                 }
3686                 ret = i40e_dev_switch_tx_queues(pf, on);
3687         } else {
3688                 /* Stop tx queues before stopping rx queues */
3689                 ret = i40e_dev_switch_tx_queues(pf, on);
3690                 if (ret) {
3691                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3692                         return ret;
3693                 }
3694                 ret = i40e_dev_switch_rx_queues(pf, on);
3695         }
3696
3697         return ret;
3698 }
3699
3700 /* Initialize VSI for TX */
3701 static int
3702 i40e_dev_tx_init(struct i40e_pf *pf)
3703 {
3704         struct rte_eth_dev_data *data = pf->dev_data;
3705         uint16_t i;
3706         uint32_t ret = I40E_SUCCESS;
3707         struct i40e_tx_queue *txq;
3708
3709         for (i = 0; i < data->nb_tx_queues; i++) {
3710                 txq = data->tx_queues[i];
3711                 if (!txq || !txq->q_set)
3712                         continue;
3713                 ret = i40e_tx_queue_init(txq);
3714                 if (ret != I40E_SUCCESS)
3715                         break;
3716         }
3717
3718         return ret;
3719 }
3720
3721 /* Initialize VSI for RX */
3722 static int
3723 i40e_dev_rx_init(struct i40e_pf *pf)
3724 {
3725         struct rte_eth_dev_data *data = pf->dev_data;
3726         int ret = I40E_SUCCESS;
3727         uint16_t i;
3728         struct i40e_rx_queue *rxq;
3729
3730         i40e_pf_config_mq_rx(pf);
3731         for (i = 0; i < data->nb_rx_queues; i++) {
3732                 rxq = data->rx_queues[i];
3733                 if (!rxq || !rxq->q_set)
3734                         continue;
3735
3736                 ret = i40e_rx_queue_init(rxq);
3737                 if (ret != I40E_SUCCESS) {
3738                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3739                                     "initialization");
3740                         break;
3741                 }
3742         }
3743
3744         return ret;
3745 }
3746
3747 static int
3748 i40e_dev_rxtx_init(struct i40e_pf *pf)
3749 {
3750         int err;
3751
3752         err = i40e_dev_tx_init(pf);
3753         if (err) {
3754                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3755                 return err;
3756         }
3757         err = i40e_dev_rx_init(pf);
3758         if (err) {
3759                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3760                 return err;
3761         }
3762
3763         return err;
3764 }
3765
3766 static int
3767 i40e_vmdq_setup(struct rte_eth_dev *dev)
3768 {
3769         struct rte_eth_conf *conf = &dev->data->dev_conf;
3770         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3771         int i, err, conf_vsis, j, loop;
3772         struct i40e_vsi *vsi;
3773         struct i40e_vmdq_info *vmdq_info;
3774         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3776
3777         /*
3778          * Disable interrupt to avoid message from VF. Furthermore, it will
3779          * avoid race condition in VSI creation/destroy.
3780          */
3781         i40e_pf_disable_irq0(hw);
3782
3783         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3784                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3785                 return -ENOTSUP;
3786         }
3787
3788         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3789         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3790                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3791                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3792                         pf->max_nb_vmdq_vsi);
3793                 return -ENOTSUP;
3794         }
3795
3796         if (pf->vmdq != NULL) {
3797                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3798                 return 0;
3799         }
3800
3801         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3802                                 sizeof(*vmdq_info) * conf_vsis, 0);
3803
3804         if (pf->vmdq == NULL) {
3805                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3806                 return -ENOMEM;
3807         }
3808
3809         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3810
3811         /* Create VMDQ VSI */
3812         for (i = 0; i < conf_vsis; i++) {
3813                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3814                                 vmdq_conf->enable_loop_back);
3815                 if (vsi == NULL) {
3816                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3817                         err = -1;
3818                         goto err_vsi_setup;
3819                 }
3820                 vmdq_info = &pf->vmdq[i];
3821                 vmdq_info->pf = pf;
3822                 vmdq_info->vsi = vsi;
3823         }
3824         pf->nb_cfg_vmdq_vsi = conf_vsis;
3825
3826         /* Configure Vlan */
3827         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3828         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3829                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3830                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3831                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3832                                         vmdq_conf->pool_map[i].vlan_id, j);
3833
3834                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3835                                                 vmdq_conf->pool_map[i].vlan_id);
3836                                 if (err) {
3837                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3838                                         err = -1;
3839                                         goto err_vsi_setup;
3840                                 }
3841                         }
3842                 }
3843         }
3844
3845         i40e_pf_enable_irq0(hw);
3846
3847         return 0;
3848
3849 err_vsi_setup:
3850         for (i = 0; i < conf_vsis; i++)
3851                 if (pf->vmdq[i].vsi == NULL)
3852                         break;
3853                 else
3854                         i40e_vsi_release(pf->vmdq[i].vsi);
3855
3856         rte_free(pf->vmdq);
3857         pf->vmdq = NULL;
3858         i40e_pf_enable_irq0(hw);
3859         return err;
3860 }
3861
3862 static void
3863 i40e_stat_update_32(struct i40e_hw *hw,
3864                    uint32_t reg,
3865                    bool offset_loaded,
3866                    uint64_t *offset,
3867                    uint64_t *stat)
3868 {
3869         uint64_t new_data;
3870
3871         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3872         if (!offset_loaded)
3873                 *offset = new_data;
3874
3875         if (new_data >= *offset)
3876                 *stat = (uint64_t)(new_data - *offset);
3877         else
3878                 *stat = (uint64_t)((new_data +
3879                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3880 }
3881
3882 static void
3883 i40e_stat_update_48(struct i40e_hw *hw,
3884                    uint32_t hireg,
3885                    uint32_t loreg,
3886                    bool offset_loaded,
3887                    uint64_t *offset,
3888                    uint64_t *stat)
3889 {
3890         uint64_t new_data;
3891
3892         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3893         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3894                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3895
3896         if (!offset_loaded)
3897                 *offset = new_data;
3898
3899         if (new_data >= *offset)
3900                 *stat = new_data - *offset;
3901         else
3902                 *stat = (uint64_t)((new_data +
3903                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3904
3905         *stat &= I40E_48_BIT_MASK;
3906 }
3907
3908 /* Disable IRQ0 */
3909 void
3910 i40e_pf_disable_irq0(struct i40e_hw *hw)
3911 {
3912         /* Disable all interrupt types */
3913         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3914         I40E_WRITE_FLUSH(hw);
3915 }
3916
3917 /* Enable IRQ0 */
3918 void
3919 i40e_pf_enable_irq0(struct i40e_hw *hw)
3920 {
3921         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3922                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3923                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3924                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3925         I40E_WRITE_FLUSH(hw);
3926 }
3927
3928 static void
3929 i40e_pf_config_irq0(struct i40e_hw *hw)
3930 {
3931         /* read pending request and disable first */
3932         i40e_pf_disable_irq0(hw);
3933         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3934         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3935                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3936
3937         /* Link no queues with irq0 */
3938         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3939                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3940 }
3941
3942 static void
3943 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3944 {
3945         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3946         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3947         int i;
3948         uint16_t abs_vf_id;
3949         uint32_t index, offset, val;
3950
3951         if (!pf->vfs)
3952                 return;
3953         /**
3954          * Try to find which VF trigger a reset, use absolute VF id to access
3955          * since the reg is global register.
3956          */
3957         for (i = 0; i < pf->vf_num; i++) {
3958                 abs_vf_id = hw->func_caps.vf_base_id + i;
3959                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3960                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3961                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3962                 /* VFR event occured */
3963                 if (val & (0x1 << offset)) {
3964                         int ret;
3965
3966                         /* Clear the event first */
3967                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3968                                                         (0x1 << offset));
3969                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3970                         /**
3971                          * Only notify a VF reset event occured,
3972                          * don't trigger another SW reset
3973                          */
3974                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3975                         if (ret != I40E_SUCCESS)
3976                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3977                 }
3978         }
3979 }
3980
3981 static void
3982 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3983 {
3984         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3985         struct i40e_arq_event_info info;
3986         uint16_t pending, opcode;
3987         int ret;
3988
3989         info.buf_len = I40E_AQ_BUF_SZ;
3990         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3991         if (!info.msg_buf) {
3992                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3993                 return;
3994         }
3995
3996         pending = 1;
3997         while (pending) {
3998                 ret = i40e_clean_arq_element(hw, &info, &pending);
3999
4000                 if (ret != I40E_SUCCESS) {
4001                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4002                                     "aq_err: %u", hw->aq.asq_last_status);
4003                         break;
4004                 }
4005                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4006
4007                 switch (opcode) {
4008                 case i40e_aqc_opc_send_msg_to_pf:
4009                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4010                         i40e_pf_host_handle_vf_msg(dev,
4011                                         rte_le_to_cpu_16(info.desc.retval),
4012                                         rte_le_to_cpu_32(info.desc.cookie_high),
4013                                         rte_le_to_cpu_32(info.desc.cookie_low),
4014                                         info.msg_buf,
4015                                         info.msg_len);
4016                         break;
4017                 default:
4018                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4019                                     opcode);
4020                         break;
4021                 }
4022         }
4023         rte_free(info.msg_buf);
4024 }
4025
4026 /*
4027  * Interrupt handler is registered as the alarm callback for handling LSC
4028  * interrupt in a definite of time, in order to wait the NIC into a stable
4029  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4030  * no need for link down interrupt.
4031  */
4032 static void
4033 i40e_dev_interrupt_delayed_handler(void *param)
4034 {
4035         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4037         uint32_t icr0;
4038
4039         /* read interrupt causes again */
4040         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4041
4042 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4043         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4044                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4045         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4046                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4047         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4048                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4049         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4050                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4051         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4052                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4053                                                                 "state\n");
4054         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4055                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4056         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4057                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4058 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4059
4060         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4061                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4062                 i40e_dev_handle_vfr_event(dev);
4063         }
4064         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4065                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4066                 i40e_dev_handle_aq_msg(dev);
4067         }
4068
4069         /* handle the link up interrupt in an alarm callback */
4070         i40e_dev_link_update(dev, 0);
4071         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4072
4073         i40e_pf_enable_irq0(hw);
4074         rte_intr_enable(&(dev->pci_dev->intr_handle));
4075 }
4076
4077 /**
4078  * Interrupt handler triggered by NIC  for handling
4079  * specific interrupt.
4080  *
4081  * @param handle
4082  *  Pointer to interrupt handle.
4083  * @param param
4084  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4085  *
4086  * @return
4087  *  void
4088  */
4089 static void
4090 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4091                            void *param)
4092 {
4093         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4095         uint32_t icr0;
4096
4097         /* Disable interrupt */
4098         i40e_pf_disable_irq0(hw);
4099
4100         /* read out interrupt causes */
4101         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4102
4103         /* No interrupt event indicated */
4104         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4105                 PMD_DRV_LOG(INFO, "No interrupt event");
4106                 goto done;
4107         }
4108 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4109         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4110                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4111         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4112                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4113         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4114                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4115         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4116                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4117         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4118                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4119         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4120                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4121         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4122                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4123 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4124
4125         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4126                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4127                 i40e_dev_handle_vfr_event(dev);
4128         }
4129         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4130                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4131                 i40e_dev_handle_aq_msg(dev);
4132         }
4133
4134         /* Link Status Change interrupt */
4135         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4136 #define I40E_US_PER_SECOND 1000000
4137                 struct rte_eth_link link;
4138
4139                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4140                 memset(&link, 0, sizeof(link));
4141                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4142                 i40e_dev_link_update(dev, 0);
4143
4144                 /*
4145                  * For link up interrupt, it needs to wait 1 second to let the
4146                  * hardware be a stable state. Otherwise several consecutive
4147                  * interrupts can be observed.
4148                  * For link down interrupt, no need to wait.
4149                  */
4150                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4151                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4152                         return;
4153                 else
4154                         _rte_eth_dev_callback_process(dev,
4155                                 RTE_ETH_EVENT_INTR_LSC);
4156         }
4157
4158 done:
4159         /* Enable interrupt */
4160         i40e_pf_enable_irq0(hw);
4161         rte_intr_enable(&(dev->pci_dev->intr_handle));
4162 }
4163
4164 static int
4165 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4166                          struct i40e_macvlan_filter *filter,
4167                          int total)
4168 {
4169         int ele_num, ele_buff_size;
4170         int num, actual_num, i;
4171         uint16_t flags;
4172         int ret = I40E_SUCCESS;
4173         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4174         struct i40e_aqc_add_macvlan_element_data *req_list;
4175
4176         if (filter == NULL  || total == 0)
4177                 return I40E_ERR_PARAM;
4178         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4179         ele_buff_size = hw->aq.asq_buf_size;
4180
4181         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4182         if (req_list == NULL) {
4183                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4184                 return I40E_ERR_NO_MEMORY;
4185         }
4186
4187         num = 0;
4188         do {
4189                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4190                 memset(req_list, 0, ele_buff_size);
4191
4192                 for (i = 0; i < actual_num; i++) {
4193                         (void)rte_memcpy(req_list[i].mac_addr,
4194                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4195                         req_list[i].vlan_tag =
4196                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4197
4198                         switch (filter[num + i].filter_type) {
4199                         case RTE_MAC_PERFECT_MATCH:
4200                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4201                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4202                                 break;
4203                         case RTE_MACVLAN_PERFECT_MATCH:
4204                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4205                                 break;
4206                         case RTE_MAC_HASH_MATCH:
4207                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4208                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4209                                 break;
4210                         case RTE_MACVLAN_HASH_MATCH:
4211                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4212                                 break;
4213                         default:
4214                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4215                                 ret = I40E_ERR_PARAM;
4216                                 goto DONE;
4217                         }
4218
4219                         req_list[i].queue_number = 0;
4220
4221                         req_list[i].flags = rte_cpu_to_le_16(flags);
4222                 }
4223
4224                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4225                                                 actual_num, NULL);
4226                 if (ret != I40E_SUCCESS) {
4227                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4228                         goto DONE;
4229                 }
4230                 num += actual_num;
4231         } while (num < total);
4232
4233 DONE:
4234         rte_free(req_list);
4235         return ret;
4236 }
4237
4238 static int
4239 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4240                             struct i40e_macvlan_filter *filter,
4241                             int total)
4242 {
4243         int ele_num, ele_buff_size;
4244         int num, actual_num, i;
4245         uint16_t flags;
4246         int ret = I40E_SUCCESS;
4247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4248         struct i40e_aqc_remove_macvlan_element_data *req_list;
4249
4250         if (filter == NULL  || total == 0)
4251                 return I40E_ERR_PARAM;
4252
4253         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4254         ele_buff_size = hw->aq.asq_buf_size;
4255
4256         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4257         if (req_list == NULL) {
4258                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4259                 return I40E_ERR_NO_MEMORY;
4260         }
4261
4262         num = 0;
4263         do {
4264                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4265                 memset(req_list, 0, ele_buff_size);
4266
4267                 for (i = 0; i < actual_num; i++) {
4268                         (void)rte_memcpy(req_list[i].mac_addr,
4269                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4270                         req_list[i].vlan_tag =
4271                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4272
4273                         switch (filter[num + i].filter_type) {
4274                         case RTE_MAC_PERFECT_MATCH:
4275                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4276                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4277                                 break;
4278                         case RTE_MACVLAN_PERFECT_MATCH:
4279                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4280                                 break;
4281                         case RTE_MAC_HASH_MATCH:
4282                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4283                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4284                                 break;
4285                         case RTE_MACVLAN_HASH_MATCH:
4286                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4287                                 break;
4288                         default:
4289                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4290                                 ret = I40E_ERR_PARAM;
4291                                 goto DONE;
4292                         }
4293                         req_list[i].flags = rte_cpu_to_le_16(flags);
4294                 }
4295
4296                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4297                                                 actual_num, NULL);
4298                 if (ret != I40E_SUCCESS) {
4299                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4300                         goto DONE;
4301                 }
4302                 num += actual_num;
4303         } while (num < total);
4304
4305 DONE:
4306         rte_free(req_list);
4307         return ret;
4308 }
4309
4310 /* Find out specific MAC filter */
4311 static struct i40e_mac_filter *
4312 i40e_find_mac_filter(struct i40e_vsi *vsi,
4313                          struct ether_addr *macaddr)
4314 {
4315         struct i40e_mac_filter *f;
4316
4317         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4318                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4319                         return f;
4320         }
4321
4322         return NULL;
4323 }
4324
4325 static bool
4326 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4327                          uint16_t vlan_id)
4328 {
4329         uint32_t vid_idx, vid_bit;
4330
4331         if (vlan_id > ETH_VLAN_ID_MAX)
4332                 return 0;
4333
4334         vid_idx = I40E_VFTA_IDX(vlan_id);
4335         vid_bit = I40E_VFTA_BIT(vlan_id);
4336
4337         if (vsi->vfta[vid_idx] & vid_bit)
4338                 return 1;
4339         else
4340                 return 0;
4341 }
4342
4343 static void
4344 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4345                          uint16_t vlan_id, bool on)
4346 {
4347         uint32_t vid_idx, vid_bit;
4348
4349         if (vlan_id > ETH_VLAN_ID_MAX)
4350                 return;
4351
4352         vid_idx = I40E_VFTA_IDX(vlan_id);
4353         vid_bit = I40E_VFTA_BIT(vlan_id);
4354
4355         if (on)
4356                 vsi->vfta[vid_idx] |= vid_bit;
4357         else
4358                 vsi->vfta[vid_idx] &= ~vid_bit;
4359 }
4360
4361 /**
4362  * Find all vlan options for specific mac addr,
4363  * return with actual vlan found.
4364  */
4365 static inline int
4366 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4367                            struct i40e_macvlan_filter *mv_f,
4368                            int num, struct ether_addr *addr)
4369 {
4370         int i;
4371         uint32_t j, k;
4372
4373         /**
4374          * Not to use i40e_find_vlan_filter to decrease the loop time,
4375          * although the code looks complex.
4376           */
4377         if (num < vsi->vlan_num)
4378                 return I40E_ERR_PARAM;
4379
4380         i = 0;
4381         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4382                 if (vsi->vfta[j]) {
4383                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4384                                 if (vsi->vfta[j] & (1 << k)) {
4385                                         if (i > num - 1) {
4386                                                 PMD_DRV_LOG(ERR, "vlan number "
4387                                                             "not match");
4388                                                 return I40E_ERR_PARAM;
4389                                         }
4390                                         (void)rte_memcpy(&mv_f[i].macaddr,
4391                                                         addr, ETH_ADDR_LEN);
4392                                         mv_f[i].vlan_id =
4393                                                 j * I40E_UINT32_BIT_SIZE + k;
4394                                         i++;
4395                                 }
4396                         }
4397                 }
4398         }
4399         return I40E_SUCCESS;
4400 }
4401
4402 static inline int
4403 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4404                            struct i40e_macvlan_filter *mv_f,
4405                            int num,
4406                            uint16_t vlan)
4407 {
4408         int i = 0;
4409         struct i40e_mac_filter *f;
4410
4411         if (num < vsi->mac_num)
4412                 return I40E_ERR_PARAM;
4413
4414         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4415                 if (i > num - 1) {
4416                         PMD_DRV_LOG(ERR, "buffer number not match");
4417                         return I40E_ERR_PARAM;
4418                 }
4419                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4420                                 ETH_ADDR_LEN);
4421                 mv_f[i].vlan_id = vlan;
4422                 mv_f[i].filter_type = f->mac_info.filter_type;
4423                 i++;
4424         }
4425
4426         return I40E_SUCCESS;
4427 }
4428
4429 static int
4430 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4431 {
4432         int i, num;
4433         struct i40e_mac_filter *f;
4434         struct i40e_macvlan_filter *mv_f;
4435         int ret = I40E_SUCCESS;
4436
4437         if (vsi == NULL || vsi->mac_num == 0)
4438                 return I40E_ERR_PARAM;
4439
4440         /* Case that no vlan is set */
4441         if (vsi->vlan_num == 0)
4442                 num = vsi->mac_num;
4443         else
4444                 num = vsi->mac_num * vsi->vlan_num;
4445
4446         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4447         if (mv_f == NULL) {
4448                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4449                 return I40E_ERR_NO_MEMORY;
4450         }
4451
4452         i = 0;
4453         if (vsi->vlan_num == 0) {
4454                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4455                         (void)rte_memcpy(&mv_f[i].macaddr,
4456                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4457                         mv_f[i].vlan_id = 0;
4458                         i++;
4459                 }
4460         } else {
4461                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4462                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4463                                         vsi->vlan_num, &f->mac_info.mac_addr);
4464                         if (ret != I40E_SUCCESS)
4465                                 goto DONE;
4466                         i += vsi->vlan_num;
4467                 }
4468         }
4469
4470         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4471 DONE:
4472         rte_free(mv_f);
4473
4474         return ret;
4475 }
4476
4477 int
4478 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4479 {
4480         struct i40e_macvlan_filter *mv_f;
4481         int mac_num;
4482         int ret = I40E_SUCCESS;
4483
4484         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4485                 return I40E_ERR_PARAM;
4486
4487         /* If it's already set, just return */
4488         if (i40e_find_vlan_filter(vsi,vlan))
4489                 return I40E_SUCCESS;
4490
4491         mac_num = vsi->mac_num;
4492
4493         if (mac_num == 0) {
4494                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4495                 return I40E_ERR_PARAM;
4496         }
4497
4498         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4499
4500         if (mv_f == NULL) {
4501                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4502                 return I40E_ERR_NO_MEMORY;
4503         }
4504
4505         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4506
4507         if (ret != I40E_SUCCESS)
4508                 goto DONE;
4509
4510         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4511
4512         if (ret != I40E_SUCCESS)
4513                 goto DONE;
4514
4515         i40e_set_vlan_filter(vsi, vlan, 1);
4516
4517         vsi->vlan_num++;
4518         ret = I40E_SUCCESS;
4519 DONE:
4520         rte_free(mv_f);
4521         return ret;
4522 }
4523
4524 int
4525 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4526 {
4527         struct i40e_macvlan_filter *mv_f;
4528         int mac_num;
4529         int ret = I40E_SUCCESS;
4530
4531         /**
4532          * Vlan 0 is the generic filter for untagged packets
4533          * and can't be removed.
4534          */
4535         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4536                 return I40E_ERR_PARAM;
4537
4538         /* If can't find it, just return */
4539         if (!i40e_find_vlan_filter(vsi, vlan))
4540                 return I40E_ERR_PARAM;
4541
4542         mac_num = vsi->mac_num;
4543
4544         if (mac_num == 0) {
4545                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4546                 return I40E_ERR_PARAM;
4547         }
4548
4549         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4550
4551         if (mv_f == NULL) {
4552                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4553                 return I40E_ERR_NO_MEMORY;
4554         }
4555
4556         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4557
4558         if (ret != I40E_SUCCESS)
4559                 goto DONE;
4560
4561         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4562
4563         if (ret != I40E_SUCCESS)
4564                 goto DONE;
4565
4566         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4567         if (vsi->vlan_num == 1) {
4568                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4569                 if (ret != I40E_SUCCESS)
4570                         goto DONE;
4571
4572                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4573                 if (ret != I40E_SUCCESS)
4574                         goto DONE;
4575         }
4576
4577         i40e_set_vlan_filter(vsi, vlan, 0);
4578
4579         vsi->vlan_num--;
4580         ret = I40E_SUCCESS;
4581 DONE:
4582         rte_free(mv_f);
4583         return ret;
4584 }
4585
4586 int
4587 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4588 {
4589         struct i40e_mac_filter *f;
4590         struct i40e_macvlan_filter *mv_f;
4591         int i, vlan_num = 0;
4592         int ret = I40E_SUCCESS;
4593
4594         /* If it's add and we've config it, return */
4595         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4596         if (f != NULL)
4597                 return I40E_SUCCESS;
4598         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4599                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4600
4601                 /**
4602                  * If vlan_num is 0, that's the first time to add mac,
4603                  * set mask for vlan_id 0.
4604                  */
4605                 if (vsi->vlan_num == 0) {
4606                         i40e_set_vlan_filter(vsi, 0, 1);
4607                         vsi->vlan_num = 1;
4608                 }
4609                 vlan_num = vsi->vlan_num;
4610         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4611                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4612                 vlan_num = 1;
4613
4614         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4615         if (mv_f == NULL) {
4616                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4617                 return I40E_ERR_NO_MEMORY;
4618         }
4619
4620         for (i = 0; i < vlan_num; i++) {
4621                 mv_f[i].filter_type = mac_filter->filter_type;
4622                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4623                                 ETH_ADDR_LEN);
4624         }
4625
4626         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4627                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4628                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4629                                         &mac_filter->mac_addr);
4630                 if (ret != I40E_SUCCESS)
4631                         goto DONE;
4632         }
4633
4634         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4635         if (ret != I40E_SUCCESS)
4636                 goto DONE;
4637
4638         /* Add the mac addr into mac list */
4639         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4640         if (f == NULL) {
4641                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4642                 ret = I40E_ERR_NO_MEMORY;
4643                 goto DONE;
4644         }
4645         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4646                         ETH_ADDR_LEN);
4647         f->mac_info.filter_type = mac_filter->filter_type;
4648         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4649         vsi->mac_num++;
4650
4651         ret = I40E_SUCCESS;
4652 DONE:
4653         rte_free(mv_f);
4654
4655         return ret;
4656 }
4657
4658 int
4659 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4660 {
4661         struct i40e_mac_filter *f;
4662         struct i40e_macvlan_filter *mv_f;
4663         int i, vlan_num;
4664         enum rte_mac_filter_type filter_type;
4665         int ret = I40E_SUCCESS;
4666
4667         /* Can't find it, return an error */
4668         f = i40e_find_mac_filter(vsi, addr);
4669         if (f == NULL)
4670                 return I40E_ERR_PARAM;
4671
4672         vlan_num = vsi->vlan_num;
4673         filter_type = f->mac_info.filter_type;
4674         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4675                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4676                 if (vlan_num == 0) {
4677                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4678                         return I40E_ERR_PARAM;
4679                 }
4680         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4681                         filter_type == RTE_MAC_HASH_MATCH)
4682                 vlan_num = 1;
4683
4684         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4685         if (mv_f == NULL) {
4686                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4687                 return I40E_ERR_NO_MEMORY;
4688         }
4689
4690         for (i = 0; i < vlan_num; i++) {
4691                 mv_f[i].filter_type = filter_type;
4692                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4693                                 ETH_ADDR_LEN);
4694         }
4695         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4696                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4697                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4698                 if (ret != I40E_SUCCESS)
4699                         goto DONE;
4700         }
4701
4702         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4703         if (ret != I40E_SUCCESS)
4704                 goto DONE;
4705
4706         /* Remove the mac addr into mac list */
4707         TAILQ_REMOVE(&vsi->mac_list, f, next);
4708         rte_free(f);
4709         vsi->mac_num--;
4710
4711         ret = I40E_SUCCESS;
4712 DONE:
4713         rte_free(mv_f);
4714         return ret;
4715 }
4716
4717 /* Configure hash enable flags for RSS */
4718 uint64_t
4719 i40e_config_hena(uint64_t flags)
4720 {
4721         uint64_t hena = 0;
4722
4723         if (!flags)
4724                 return hena;
4725
4726         if (flags & ETH_RSS_FRAG_IPV4)
4727                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4728         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4729                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4730         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4731                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4732         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4733                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4734         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4735                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4736         if (flags & ETH_RSS_FRAG_IPV6)
4737                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4738         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4739                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4740         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4741                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4742         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4743                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4744         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4745                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4746         if (flags & ETH_RSS_L2_PAYLOAD)
4747                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4748
4749         return hena;
4750 }
4751
4752 /* Parse the hash enable flags */
4753 uint64_t
4754 i40e_parse_hena(uint64_t flags)
4755 {
4756         uint64_t rss_hf = 0;
4757
4758         if (!flags)
4759                 return rss_hf;
4760         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4761                 rss_hf |= ETH_RSS_FRAG_IPV4;
4762         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4763                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4764         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4765                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4766         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4767                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4768         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4769                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4770         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4771                 rss_hf |= ETH_RSS_FRAG_IPV6;
4772         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4773                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4774         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4775                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4776         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4777                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4778         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4779                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4780         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4781                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4782
4783         return rss_hf;
4784 }
4785
4786 /* Disable RSS */
4787 static void
4788 i40e_pf_disable_rss(struct i40e_pf *pf)
4789 {
4790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4791         uint64_t hena;
4792
4793         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4794         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4795         hena &= ~I40E_RSS_HENA_ALL;
4796         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4797         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4798         I40E_WRITE_FLUSH(hw);
4799 }
4800
4801 static int
4802 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4803 {
4804         uint32_t *hash_key;
4805         uint8_t hash_key_len;
4806         uint64_t rss_hf;
4807         uint16_t i;
4808         uint64_t hena;
4809
4810         hash_key = (uint32_t *)(rss_conf->rss_key);
4811         hash_key_len = rss_conf->rss_key_len;
4812         if (hash_key != NULL && hash_key_len >=
4813                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4814                 /* Fill in RSS hash key */
4815                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4816                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4817         }
4818
4819         rss_hf = rss_conf->rss_hf;
4820         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4821         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4822         hena &= ~I40E_RSS_HENA_ALL;
4823         hena |= i40e_config_hena(rss_hf);
4824         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4825         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4826         I40E_WRITE_FLUSH(hw);
4827
4828         return 0;
4829 }
4830
4831 static int
4832 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4833                          struct rte_eth_rss_conf *rss_conf)
4834 {
4835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4836         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4837         uint64_t hena;
4838
4839         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4840         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4841         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4842                 if (rss_hf != 0) /* Enable RSS */
4843                         return -EINVAL;
4844                 return 0; /* Nothing to do */
4845         }
4846         /* RSS enabled */
4847         if (rss_hf == 0) /* Disable RSS */
4848                 return -EINVAL;
4849
4850         return i40e_hw_rss_hash_set(hw, rss_conf);
4851 }
4852
4853 static int
4854 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4855                            struct rte_eth_rss_conf *rss_conf)
4856 {
4857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4858         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4859         uint64_t hena;
4860         uint16_t i;
4861
4862         if (hash_key != NULL) {
4863                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4864                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4865                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4866         }
4867         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4868         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4869         rss_conf->rss_hf = i40e_parse_hena(hena);
4870
4871         return 0;
4872 }
4873
4874 static int
4875 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4876 {
4877         switch (filter_type) {
4878         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4879                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4880                 break;
4881         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4882                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4883                 break;
4884         case RTE_TUNNEL_FILTER_IMAC_TENID:
4885                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4886                 break;
4887         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4888                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4889                 break;
4890         case ETH_TUNNEL_FILTER_IMAC:
4891                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4892                 break;
4893         default:
4894                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4895                 return -EINVAL;
4896         }
4897
4898         return 0;
4899 }
4900
4901 static int
4902 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4903                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4904                         uint8_t add)
4905 {
4906         uint16_t ip_type;
4907         uint8_t tun_type = 0;
4908         int val, ret = 0;
4909         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4910         struct i40e_vsi *vsi = pf->main_vsi;
4911         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4912         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4913
4914         cld_filter = rte_zmalloc("tunnel_filter",
4915                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4916                 0);
4917
4918         if (NULL == cld_filter) {
4919                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4920                 return -EINVAL;
4921         }
4922         pfilter = cld_filter;
4923
4924         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4925                         sizeof(struct ether_addr));
4926         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4927                         sizeof(struct ether_addr));
4928
4929         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4930         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4931                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4932                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4933                                 &tunnel_filter->ip_addr,
4934                                 sizeof(pfilter->ipaddr.v4.data));
4935         } else {
4936                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4937                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4938                                 &tunnel_filter->ip_addr,
4939                                 sizeof(pfilter->ipaddr.v6.data));
4940         }
4941
4942         /* check tunneled type */
4943         switch (tunnel_filter->tunnel_type) {
4944         case RTE_TUNNEL_TYPE_VXLAN:
4945                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4946                 break;
4947         case RTE_TUNNEL_TYPE_NVGRE:
4948                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4949                 break;
4950         default:
4951                 /* Other tunnel types is not supported. */
4952                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4953                 rte_free(cld_filter);
4954                 return -EINVAL;
4955         }
4956
4957         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4958                                                 &pfilter->flags);
4959         if (val < 0) {
4960                 rte_free(cld_filter);
4961                 return -EINVAL;
4962         }
4963
4964         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4965                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4966         pfilter->tenant_id = tunnel_filter->tenant_id;
4967         pfilter->queue_number = tunnel_filter->queue_id;
4968
4969         if (add)
4970                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4971         else
4972                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4973                                                 cld_filter, 1);
4974
4975         rte_free(cld_filter);
4976         return ret;
4977 }
4978
4979 static int
4980 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4981 {
4982         uint8_t i;
4983
4984         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4985                 if (pf->vxlan_ports[i] == port)
4986                         return i;
4987         }
4988
4989         return -1;
4990 }
4991
4992 static int
4993 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4994 {
4995         int  idx, ret;
4996         uint8_t filter_idx;
4997         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4998
4999         idx = i40e_get_vxlan_port_idx(pf, port);
5000
5001         /* Check if port already exists */
5002         if (idx >= 0) {
5003                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5004                 return -EINVAL;
5005         }
5006
5007         /* Now check if there is space to add the new port */
5008         idx = i40e_get_vxlan_port_idx(pf, 0);
5009         if (idx < 0) {
5010                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5011                         "not adding port %d", port);
5012                 return -ENOSPC;
5013         }
5014
5015         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5016                                         &filter_idx, NULL);
5017         if (ret < 0) {
5018                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5019                 return -1;
5020         }
5021
5022         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5023                          port,  filter_idx);
5024
5025         /* New port: add it and mark its index in the bitmap */
5026         pf->vxlan_ports[idx] = port;
5027         pf->vxlan_bitmap |= (1 << idx);
5028
5029         if (!(pf->flags & I40E_FLAG_VXLAN))
5030                 pf->flags |= I40E_FLAG_VXLAN;
5031
5032         return 0;
5033 }
5034
5035 static int
5036 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5037 {
5038         int idx;
5039         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5040
5041         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5042                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5043                 return -EINVAL;
5044         }
5045
5046         idx = i40e_get_vxlan_port_idx(pf, port);
5047
5048         if (idx < 0) {
5049                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5050                 return -EINVAL;
5051         }
5052
5053         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5054                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5055                 return -1;
5056         }
5057
5058         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5059                         port, idx);
5060
5061         pf->vxlan_ports[idx] = 0;
5062         pf->vxlan_bitmap &= ~(1 << idx);
5063
5064         if (!pf->vxlan_bitmap)
5065                 pf->flags &= ~I40E_FLAG_VXLAN;
5066
5067         return 0;
5068 }
5069
5070 /* Add UDP tunneling port */
5071 static int
5072 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5073                         struct rte_eth_udp_tunnel *udp_tunnel)
5074 {
5075         int ret = 0;
5076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5077
5078         if (udp_tunnel == NULL)
5079                 return -EINVAL;
5080
5081         switch (udp_tunnel->prot_type) {
5082         case RTE_TUNNEL_TYPE_VXLAN:
5083                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5084                 break;
5085
5086         case RTE_TUNNEL_TYPE_GENEVE:
5087         case RTE_TUNNEL_TYPE_TEREDO:
5088                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5089                 ret = -1;
5090                 break;
5091
5092         default:
5093                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5094                 ret = -1;
5095                 break;
5096         }
5097
5098         return ret;
5099 }
5100
5101 /* Remove UDP tunneling port */
5102 static int
5103 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5104                         struct rte_eth_udp_tunnel *udp_tunnel)
5105 {
5106         int ret = 0;
5107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5108
5109         if (udp_tunnel == NULL)
5110                 return -EINVAL;
5111
5112         switch (udp_tunnel->prot_type) {
5113         case RTE_TUNNEL_TYPE_VXLAN:
5114                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5115                 break;
5116         case RTE_TUNNEL_TYPE_GENEVE:
5117         case RTE_TUNNEL_TYPE_TEREDO:
5118                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5119                 ret = -1;
5120                 break;
5121         default:
5122                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5123                 ret = -1;
5124                 break;
5125         }
5126
5127         return ret;
5128 }
5129
5130 /* Calculate the maximum number of contiguous PF queues that are configured */
5131 static int
5132 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5133 {
5134         struct rte_eth_dev_data *data = pf->dev_data;
5135         int i, num;
5136         struct i40e_rx_queue *rxq;
5137
5138         num = 0;
5139         for (i = 0; i < pf->lan_nb_qps; i++) {
5140                 rxq = data->rx_queues[i];
5141                 if (rxq && rxq->q_set)
5142                         num++;
5143                 else
5144                         break;
5145         }
5146
5147         return num;
5148 }
5149
5150 /* Configure RSS */
5151 static int
5152 i40e_pf_config_rss(struct i40e_pf *pf)
5153 {
5154         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5155         struct rte_eth_rss_conf rss_conf;
5156         uint32_t i, lut = 0;
5157         uint16_t j, num;
5158
5159         /*
5160          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5161          * It's necessary to calulate the actual PF queues that are configured.
5162          */
5163         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5164                 num = i40e_pf_calc_configured_queues_num(pf);
5165                 num = i40e_align_floor(num);
5166         } else
5167                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5168
5169         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5170                         num);
5171
5172         if (num == 0) {
5173                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5174                 return -ENOTSUP;
5175         }
5176
5177         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5178                 if (j == num)
5179                         j = 0;
5180                 lut = (lut << 8) | (j & ((0x1 <<
5181                         hw->func_caps.rss_table_entry_width) - 1));
5182                 if ((i & 3) == 3)
5183                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5184         }
5185
5186         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5187         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5188                 i40e_pf_disable_rss(pf);
5189                 return 0;
5190         }
5191         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5192                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5193                 /* Random default keys */
5194                 static uint32_t rss_key_default[] = {0x6b793944,
5195                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5196                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5197                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5198
5199                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5200                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5201                                                         sizeof(uint32_t);
5202         }
5203
5204         return i40e_hw_rss_hash_set(hw, &rss_conf);
5205 }
5206
5207 static int
5208 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5209                         struct rte_eth_tunnel_filter_conf *filter)
5210 {
5211         if (pf == NULL || filter == NULL) {
5212                 PMD_DRV_LOG(ERR, "Invalid parameter");
5213                 return -EINVAL;
5214         }
5215
5216         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5217                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5218                 return -EINVAL;
5219         }
5220
5221         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5222                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5223                 return -EINVAL;
5224         }
5225
5226         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5227                 (is_zero_ether_addr(filter->outer_mac))) {
5228                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5229                 return -EINVAL;
5230         }
5231
5232         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5233                 (is_zero_ether_addr(filter->inner_mac))) {
5234                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5235                 return -EINVAL;
5236         }
5237
5238         return 0;
5239 }
5240
5241 static int
5242 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5243                         void *arg)
5244 {
5245         struct rte_eth_tunnel_filter_conf *filter;
5246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5247         int ret = I40E_SUCCESS;
5248
5249         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5250
5251         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5252                 return I40E_ERR_PARAM;
5253
5254         switch (filter_op) {
5255         case RTE_ETH_FILTER_NOP:
5256                 if (!(pf->flags & I40E_FLAG_VXLAN))
5257                         ret = I40E_NOT_SUPPORTED;
5258         case RTE_ETH_FILTER_ADD:
5259                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5260                 break;
5261         case RTE_ETH_FILTER_DELETE:
5262                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5263                 break;
5264         default:
5265                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5266                 ret = I40E_ERR_PARAM;
5267                 break;
5268         }
5269
5270         return ret;
5271 }
5272
5273 static int
5274 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5275 {
5276         int ret = 0;
5277         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5278
5279         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5280                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5281                 return -ENOTSUP;
5282         }
5283
5284         /* RSS setup */
5285         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5286                 ret = i40e_pf_config_rss(pf);
5287         else
5288                 i40e_pf_disable_rss(pf);
5289
5290         return ret;
5291 }
5292
5293 /* Get the symmetric hash enable configurations per port */
5294 static void
5295 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5296 {
5297         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5298
5299         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5300 }
5301
5302 /* Set the symmetric hash enable configurations per port */
5303 static void
5304 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5305 {
5306         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5307
5308         if (enable > 0) {
5309                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5310                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5311                                                         "been enabled");
5312                         return;
5313                 }
5314                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5315         } else {
5316                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5317                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5318                                                         "been disabled");
5319                         return;
5320                 }
5321                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5322         }
5323         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5324         I40E_WRITE_FLUSH(hw);
5325 }
5326
5327 /*
5328  * Get global configurations of hash function type and symmetric hash enable
5329  * per flow type (pctype). Note that global configuration means it affects all
5330  * the ports on the same NIC.
5331  */
5332 static int
5333 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5334                                    struct rte_eth_hash_global_conf *g_cfg)
5335 {
5336         uint32_t reg, mask = I40E_FLOW_TYPES;
5337         uint16_t i;
5338         enum i40e_filter_pctype pctype;
5339
5340         memset(g_cfg, 0, sizeof(*g_cfg));
5341         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5342         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5343                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5344         else
5345                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5346         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5347                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5348
5349         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5350                 if (!(mask & (1UL << i)))
5351                         continue;
5352                 mask &= ~(1UL << i);
5353                 /* Bit set indicats the coresponding flow type is supported */
5354                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5355                 pctype = i40e_flowtype_to_pctype(i);
5356                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5357                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5358                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5359         }
5360
5361         return 0;
5362 }
5363
5364 static int
5365 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5366 {
5367         uint32_t i;
5368         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5369
5370         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5371                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5372                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5373                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5374                                                 g_cfg->hash_func);
5375                 return -EINVAL;
5376         }
5377
5378         /*
5379          * As i40e supports less than 32 flow types, only first 32 bits need to
5380          * be checked.
5381          */
5382         mask0 = g_cfg->valid_bit_mask[0];
5383         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5384                 if (i == 0) {
5385                         /* Check if any unsupported flow type configured */
5386                         if ((mask0 | i40e_mask) ^ i40e_mask)
5387                                 goto mask_err;
5388                 } else {
5389                         if (g_cfg->valid_bit_mask[i])
5390                                 goto mask_err;
5391                 }
5392         }
5393
5394         return 0;
5395
5396 mask_err:
5397         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5398
5399         return -EINVAL;
5400 }
5401
5402 /*
5403  * Set global configurations of hash function type and symmetric hash enable
5404  * per flow type (pctype). Note any modifying global configuration will affect
5405  * all the ports on the same NIC.
5406  */
5407 static int
5408 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5409                                    struct rte_eth_hash_global_conf *g_cfg)
5410 {
5411         int ret;
5412         uint16_t i;
5413         uint32_t reg;
5414         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5415         enum i40e_filter_pctype pctype;
5416
5417         /* Check the input parameters */
5418         ret = i40e_hash_global_config_check(g_cfg);
5419         if (ret < 0)
5420                 return ret;
5421
5422         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5423                 if (!(mask0 & (1UL << i)))
5424                         continue;
5425                 mask0 &= ~(1UL << i);
5426                 pctype = i40e_flowtype_to_pctype(i);
5427                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5428                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5429                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5430         }
5431
5432         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5433         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5434                 /* Toeplitz */
5435                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5436                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5437                                                                 "Toeplitz");
5438                         goto out;
5439                 }
5440                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5441         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5442                 /* Simple XOR */
5443                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5444                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5445                                                         "Simple XOR");
5446                         goto out;
5447                 }
5448                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5449         } else
5450                 /* Use the default, and keep it as it is */
5451                 goto out;
5452
5453         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5454
5455 out:
5456         I40E_WRITE_FLUSH(hw);
5457
5458         return 0;
5459 }
5460
5461 static int
5462 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5463 {
5464         int ret = 0;
5465
5466         if (!hw || !info) {
5467                 PMD_DRV_LOG(ERR, "Invalid pointer");
5468                 return -EFAULT;
5469         }
5470
5471         switch (info->info_type) {
5472         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5473                 i40e_get_symmetric_hash_enable_per_port(hw,
5474                                         &(info->info.enable));
5475                 break;
5476         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5477                 ret = i40e_get_hash_filter_global_config(hw,
5478                                 &(info->info.global_conf));
5479                 break;
5480         default:
5481                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5482                                                         info->info_type);
5483                 ret = -EINVAL;
5484                 break;
5485         }
5486
5487         return ret;
5488 }
5489
5490 static int
5491 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5492 {
5493         int ret = 0;
5494
5495         if (!hw || !info) {
5496                 PMD_DRV_LOG(ERR, "Invalid pointer");
5497                 return -EFAULT;
5498         }
5499
5500         switch (info->info_type) {
5501         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5502                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5503                 break;
5504         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5505                 ret = i40e_set_hash_filter_global_config(hw,
5506                                 &(info->info.global_conf));
5507                 break;
5508         default:
5509                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5510                                                         info->info_type);
5511                 ret = -EINVAL;
5512                 break;
5513         }
5514
5515         return ret;
5516 }
5517
5518 /* Operations for hash function */
5519 static int
5520 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5521                       enum rte_filter_op filter_op,
5522                       void *arg)
5523 {
5524         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5525         int ret = 0;
5526
5527         switch (filter_op) {
5528         case RTE_ETH_FILTER_NOP:
5529                 break;
5530         case RTE_ETH_FILTER_GET:
5531                 ret = i40e_hash_filter_get(hw,
5532                         (struct rte_eth_hash_filter_info *)arg);
5533                 break;
5534         case RTE_ETH_FILTER_SET:
5535                 ret = i40e_hash_filter_set(hw,
5536                         (struct rte_eth_hash_filter_info *)arg);
5537                 break;
5538         default:
5539                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5540                                                                 filter_op);
5541                 ret = -ENOTSUP;
5542                 break;
5543         }
5544
5545         return ret;
5546 }
5547
5548 /*
5549  * Configure ethertype filter, which can director packet by filtering
5550  * with mac address and ether_type or only ether_type
5551  */
5552 static int
5553 i40e_ethertype_filter_set(struct i40e_pf *pf,
5554                         struct rte_eth_ethertype_filter *filter,
5555                         bool add)
5556 {
5557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5558         struct i40e_control_filter_stats stats;
5559         uint16_t flags = 0;
5560         int ret;
5561
5562         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5563                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5564                 return -EINVAL;
5565         }
5566         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5567                 filter->ether_type == ETHER_TYPE_IPv6) {
5568                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5569                         " control packet filter.", filter->ether_type);
5570                 return -EINVAL;
5571         }
5572         if (filter->ether_type == ETHER_TYPE_VLAN)
5573                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5574                         " not supported.");
5575
5576         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5577                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5578         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5579                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5580         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5581
5582         memset(&stats, 0, sizeof(stats));
5583         ret = i40e_aq_add_rem_control_packet_filter(hw,
5584                         filter->mac_addr.addr_bytes,
5585                         filter->ether_type, flags,
5586                         pf->main_vsi->seid,
5587                         filter->queue, add, &stats, NULL);
5588
5589         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5590                          " mac_etype_used = %u, etype_used = %u,"
5591                          " mac_etype_free = %u, etype_free = %u\n",
5592                          ret, stats.mac_etype_used, stats.etype_used,
5593                          stats.mac_etype_free, stats.etype_free);
5594         if (ret < 0)
5595                 return -ENOSYS;
5596         return 0;
5597 }
5598
5599 /*
5600  * Handle operations for ethertype filter.
5601  */
5602 static int
5603 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5604                                 enum rte_filter_op filter_op,
5605                                 void *arg)
5606 {
5607         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5608         int ret = 0;
5609
5610         if (filter_op == RTE_ETH_FILTER_NOP)
5611                 return ret;
5612
5613         if (arg == NULL) {
5614                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5615                             filter_op);
5616                 return -EINVAL;
5617         }
5618
5619         switch (filter_op) {
5620         case RTE_ETH_FILTER_ADD:
5621                 ret = i40e_ethertype_filter_set(pf,
5622                         (struct rte_eth_ethertype_filter *)arg,
5623                         TRUE);
5624                 break;
5625         case RTE_ETH_FILTER_DELETE:
5626                 ret = i40e_ethertype_filter_set(pf,
5627                         (struct rte_eth_ethertype_filter *)arg,
5628                         FALSE);
5629                 break;
5630         default:
5631                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5632                 ret = -ENOSYS;
5633                 break;
5634         }
5635         return ret;
5636 }
5637
5638 static int
5639 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5640                      enum rte_filter_type filter_type,
5641                      enum rte_filter_op filter_op,
5642                      void *arg)
5643 {
5644         int ret = 0;
5645
5646         if (dev == NULL)
5647                 return -EINVAL;
5648
5649         switch (filter_type) {
5650         case RTE_ETH_FILTER_HASH:
5651                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5652                 break;
5653         case RTE_ETH_FILTER_MACVLAN:
5654                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5655                 break;
5656         case RTE_ETH_FILTER_ETHERTYPE:
5657                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5658                 break;
5659         case RTE_ETH_FILTER_TUNNEL:
5660                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5661                 break;
5662         case RTE_ETH_FILTER_FDIR:
5663                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5664                 break;
5665         default:
5666                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5667                                                         filter_type);
5668                 ret = -EINVAL;
5669                 break;
5670         }
5671
5672         return ret;
5673 }
5674
5675 /*
5676  * As some registers wouldn't be reset unless a global hardware reset,
5677  * hardware initialization is needed to put those registers into an
5678  * expected initial state.
5679  */
5680 static void
5681 i40e_hw_init(struct i40e_hw *hw)
5682 {
5683         /* clear the PF Queue Filter control register */
5684         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5685
5686         /* Disable symmetric hash per port */
5687         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5688 }
5689
5690 enum i40e_filter_pctype
5691 i40e_flowtype_to_pctype(uint16_t flow_type)
5692 {
5693         static const enum i40e_filter_pctype pctype_table[] = {
5694                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5695                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5696                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5697                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5698                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5699                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5700                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5701                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5702                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5703                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5704                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5705                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5706                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5707                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5708                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5709                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5710                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5711                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5712                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5713         };
5714
5715         return pctype_table[flow_type];
5716 }
5717
5718 uint16_t
5719 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5720 {
5721         static const uint16_t flowtype_table[] = {
5722                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5723                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5724                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5725                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5726                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5727                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5728                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5729                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5730                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5731                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5732                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5733                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5734                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5735                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5736                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5737                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5738                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5739                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5740                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5741         };
5742
5743         return flowtype_table[pctype];
5744 }
5745
5746 /*
5747  * On X710, performance number is far from the expectation on recent firmware
5748  * versions; on XL710, performance number is also far from the expectation on
5749  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5750  * mode is enabled and port MAC address is equal to the packet destination MAC
5751  * address. The fix for this issue may not be integrated in the following
5752  * firmware version. So the workaround in software driver is needed. It needs
5753  * to modify the initial values of 3 internal only registers for both X710 and
5754  * XL710. Note that the values for X710 or XL710 could be different, and the
5755  * workaround can be removed when it is fixed in firmware in the future.
5756  */
5757
5758 /* For both X710 and XL710 */
5759 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5760 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5761
5762 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5763 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5764
5765 /* For X710 */
5766 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5767 /* For XL710 */
5768 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5769 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5770
5771 static void
5772 i40e_configure_registers(struct i40e_hw *hw)
5773 {
5774         static struct {
5775                 uint32_t addr;
5776                 uint64_t val;
5777         } reg_table[] = {
5778                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5779                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5780                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5781         };
5782         uint64_t reg;
5783         uint32_t i;
5784         int ret;
5785
5786         for (i = 0; i < RTE_DIM(reg_table); i++) {
5787                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5788                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5789                                 reg_table[i].val =
5790                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5791                         else /* For X710 */
5792                                 reg_table[i].val =
5793                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5794                 }
5795
5796                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5797                                                         &reg, NULL);
5798                 if (ret < 0) {
5799                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5800                                                         reg_table[i].addr);
5801                         break;
5802                 }
5803                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5804                                                 reg_table[i].addr, reg);
5805                 if (reg == reg_table[i].val)
5806                         continue;
5807
5808                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5809                                                 reg_table[i].val, NULL);
5810                 if (ret < 0) {
5811                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5812                                 "address of 0x%"PRIx32, reg_table[i].val,
5813                                                         reg_table[i].addr);
5814                         break;
5815                 }
5816                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5817                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5818         }
5819 }
5820
5821 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
5822 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
5823 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
5824 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5825 static int
5826 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5827 {
5828         uint32_t reg;
5829         int ret;
5830
5831         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5832                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5833                 return -EINVAL;
5834         }
5835
5836         /* Configure for double VLAN RX stripping */
5837         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5838         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5839                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5840                 ret = i40e_aq_debug_write_register(hw,
5841                                                    I40E_VSI_TSR(vsi->vsi_id),
5842                                                    reg, NULL);
5843                 if (ret < 0) {
5844                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5845                                     vsi->vsi_id);
5846                         return I40E_ERR_CONFIG;
5847                 }
5848         }
5849
5850         /* Configure for double VLAN TX insertion */
5851         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5852         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5853                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5854                 ret = i40e_aq_debug_write_register(hw,
5855                                                    I40E_VSI_L2TAGSTXVALID(
5856                                                    vsi->vsi_id), reg, NULL);
5857                 if (ret < 0) {
5858                         PMD_DRV_LOG(ERR, "Failed to update "
5859                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5860                         return I40E_ERR_CONFIG;
5861                 }
5862         }
5863
5864         return 0;
5865 }
5866
5867 /**
5868  * i40e_aq_add_mirror_rule
5869  * @hw: pointer to the hardware structure
5870  * @seid: VEB seid to add mirror rule to
5871  * @dst_id: destination vsi seid
5872  * @entries: Buffer which contains the entities to be mirrored
5873  * @count: number of entities contained in the buffer
5874  * @rule_id:the rule_id of the rule to be added
5875  *
5876  * Add a mirror rule for a given veb.
5877  *
5878  **/
5879 static enum i40e_status_code
5880 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5881                         uint16_t seid, uint16_t dst_id,
5882                         uint16_t rule_type, uint16_t *entries,
5883                         uint16_t count, uint16_t *rule_id)
5884 {
5885         struct i40e_aq_desc desc;
5886         struct i40e_aqc_add_delete_mirror_rule cmd;
5887         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5888                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5889                 &desc.params.raw;
5890         uint16_t buff_len;
5891         enum i40e_status_code status;
5892
5893         i40e_fill_default_direct_cmd_desc(&desc,
5894                                           i40e_aqc_opc_add_mirror_rule);
5895         memset(&cmd, 0, sizeof(cmd));
5896
5897         buff_len = sizeof(uint16_t) * count;
5898         desc.datalen = rte_cpu_to_le_16(buff_len);
5899         if (buff_len > 0)
5900                 desc.flags |= rte_cpu_to_le_16(
5901                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5902         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5903                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5904         cmd.num_entries = rte_cpu_to_le_16(count);
5905         cmd.seid = rte_cpu_to_le_16(seid);
5906         cmd.destination = rte_cpu_to_le_16(dst_id);
5907
5908         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5909         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5910         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5911                          "rule_id = %u"
5912                          " mirror_rules_used = %u, mirror_rules_free = %u,",
5913                          hw->aq.asq_last_status, resp->rule_id,
5914                          resp->mirror_rules_used, resp->mirror_rules_free);
5915         *rule_id = rte_le_to_cpu_16(resp->rule_id);
5916
5917         return status;
5918 }
5919
5920 /**
5921  * i40e_aq_del_mirror_rule
5922  * @hw: pointer to the hardware structure
5923  * @seid: VEB seid to add mirror rule to
5924  * @entries: Buffer which contains the entities to be mirrored
5925  * @count: number of entities contained in the buffer
5926  * @rule_id:the rule_id of the rule to be delete
5927  *
5928  * Delete a mirror rule for a given veb.
5929  *
5930  **/
5931 static enum i40e_status_code
5932 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5933                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5934                 uint16_t count, uint16_t rule_id)
5935 {
5936         struct i40e_aq_desc desc;
5937         struct i40e_aqc_add_delete_mirror_rule cmd;
5938         uint16_t buff_len = 0;
5939         enum i40e_status_code status;
5940         void *buff = NULL;
5941
5942         i40e_fill_default_direct_cmd_desc(&desc,
5943                                           i40e_aqc_opc_delete_mirror_rule);
5944         memset(&cmd, 0, sizeof(cmd));
5945         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5946                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5947                                                           I40E_AQ_FLAG_RD));
5948                 cmd.num_entries = count;
5949                 buff_len = sizeof(uint16_t) * count;
5950                 desc.datalen = rte_cpu_to_le_16(buff_len);
5951                 buff = (void *)entries;
5952         } else
5953                 /* rule id is filled in destination field for deleting mirror rule */
5954                 cmd.destination = rte_cpu_to_le_16(rule_id);
5955
5956         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5957                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5958         cmd.seid = rte_cpu_to_le_16(seid);
5959
5960         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5961         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5962
5963         return status;
5964 }
5965
5966 /**
5967  * i40e_mirror_rule_set
5968  * @dev: pointer to the hardware structure
5969  * @mirror_conf: mirror rule info
5970  * @sw_id: mirror rule's sw_id
5971  * @on: enable/disable
5972  *
5973  * set a mirror rule.
5974  *
5975  **/
5976 static int
5977 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5978                         struct rte_eth_mirror_conf *mirror_conf,
5979                         uint8_t sw_id, uint8_t on)
5980 {
5981         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5983         struct i40e_mirror_rule *it, *mirr_rule = NULL;
5984         struct i40e_mirror_rule *parent = NULL;
5985         uint16_t seid, dst_seid, rule_id;
5986         uint16_t i, j = 0;
5987         int ret;
5988
5989         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5990
5991         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5992                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5993                         " without veb or vfs.");
5994                 return -ENOSYS;
5995         }
5996         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5997                 PMD_DRV_LOG(ERR, "mirror table is full.");
5998                 return -ENOSPC;
5999         }
6000         if (mirror_conf->dst_pool > pf->vf_num) {
6001                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6002                                  mirror_conf->dst_pool);
6003                 return -EINVAL;
6004         }
6005
6006         seid = pf->main_vsi->veb->seid;
6007
6008         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6009                 if (sw_id <= it->index) {
6010                         mirr_rule = it;
6011                         break;
6012                 }
6013                 parent = it;
6014         }
6015         if (mirr_rule && sw_id == mirr_rule->index) {
6016                 if (on) {
6017                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6018                         return -EEXIST;
6019                 } else {
6020                         ret = i40e_aq_del_mirror_rule(hw, seid,
6021                                         mirr_rule->rule_type,
6022                                         mirr_rule->entries,
6023                                         mirr_rule->num_entries, mirr_rule->id);
6024                         if (ret < 0) {
6025                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6026                                                    " ret = %d, aq_err = %d.",
6027                                                    ret, hw->aq.asq_last_status);
6028                                 return -ENOSYS;
6029                         }
6030                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6031                         rte_free(mirr_rule);
6032                         pf->nb_mirror_rule--;
6033                         return 0;
6034                 }
6035         } else if (!on) {
6036                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6037                 return -ENOENT;
6038         }
6039
6040         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6041                                 sizeof(struct i40e_mirror_rule) , 0);
6042         if (!mirr_rule) {
6043                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6044                 return I40E_ERR_NO_MEMORY;
6045         }
6046         switch (mirror_conf->rule_type) {
6047         case ETH_MIRROR_VLAN:
6048                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6049                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6050                                 mirr_rule->entries[j] =
6051                                         mirror_conf->vlan.vlan_id[i];
6052                                 j++;
6053                         }
6054                 }
6055                 if (j == 0) {
6056                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6057                         rte_free(mirr_rule);
6058                         return -EINVAL;
6059                 }
6060                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6061                 break;
6062         case ETH_MIRROR_VIRTUAL_POOL_UP:
6063         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6064                 /* check if the specified pool bit is out of range */
6065                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6066                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6067                         rte_free(mirr_rule);
6068                         return -EINVAL;
6069                 }
6070                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6071                         if (mirror_conf->pool_mask & (1ULL << i)) {
6072                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6073                                 j++;
6074                         }
6075                 }
6076                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6077                         /* add pf vsi to entries */
6078                         mirr_rule->entries[j] = pf->main_vsi_seid;
6079                         j++;
6080                 }
6081                 if (j == 0) {
6082                         PMD_DRV_LOG(ERR, "pool is not specified.");
6083                         rte_free(mirr_rule);
6084                         return -EINVAL;
6085                 }
6086                 /* egress and ingress in aq commands means from switch but not port */
6087                 mirr_rule->rule_type =
6088                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6089                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6090                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6091                 break;
6092         case ETH_MIRROR_UPLINK_PORT:
6093                 /* egress and ingress in aq commands means from switch but not port*/
6094                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6095                 break;
6096         case ETH_MIRROR_DOWNLINK_PORT:
6097                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6098                 break;
6099         default:
6100                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6101                         mirror_conf->rule_type);
6102                 rte_free(mirr_rule);
6103                 return -EINVAL;
6104         }
6105
6106         /* If the dst_pool is equal to vf_num, consider it as PF */
6107         if (mirror_conf->dst_pool == pf->vf_num)
6108                 dst_seid = pf->main_vsi_seid;
6109         else
6110                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6111
6112         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6113                                       mirr_rule->rule_type, mirr_rule->entries,
6114                                       j, &rule_id);
6115         if (ret < 0) {
6116                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6117                                    " ret = %d, aq_err = %d.",
6118                                    ret, hw->aq.asq_last_status);
6119                 rte_free(mirr_rule);
6120                 return -ENOSYS;
6121         }
6122
6123         mirr_rule->index = sw_id;
6124         mirr_rule->num_entries = j;
6125         mirr_rule->id = rule_id;
6126         mirr_rule->dst_vsi_seid = dst_seid;
6127
6128         if (parent)
6129                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6130         else
6131                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6132
6133         pf->nb_mirror_rule++;
6134         return 0;
6135 }
6136
6137 /**
6138  * i40e_mirror_rule_reset
6139  * @dev: pointer to the device
6140  * @sw_id: mirror rule's sw_id
6141  *
6142  * reset a mirror rule.
6143  *
6144  **/
6145 static int
6146 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6147 {
6148         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6149         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6150         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6151         uint16_t seid;
6152         int ret;
6153
6154         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6155
6156         seid = pf->main_vsi->veb->seid;
6157
6158         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6159                 if (sw_id == it->index) {
6160                         mirr_rule = it;
6161                         break;
6162                 }
6163         }
6164         if (mirr_rule) {
6165                 ret = i40e_aq_del_mirror_rule(hw, seid,
6166                                 mirr_rule->rule_type,
6167                                 mirr_rule->entries,
6168                                 mirr_rule->num_entries, mirr_rule->id);
6169                 if (ret < 0) {
6170                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6171                                            " status = %d, aq_err = %d.",
6172                                            ret, hw->aq.asq_last_status);
6173                         return -ENOSYS;
6174                 }
6175                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6176                 rte_free(mirr_rule);
6177                 pf->nb_mirror_rule--;
6178         } else {
6179                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6180                 return -ENOENT;
6181         }
6182         return 0;
6183 }
6184
6185 static int
6186 i40e_timesync_enable(struct rte_eth_dev *dev)
6187 {
6188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6189         struct rte_eth_link *link = &dev->data->dev_link;
6190         uint32_t tsync_ctl_l;
6191         uint32_t tsync_ctl_h;
6192         uint32_t tsync_inc_l;
6193         uint32_t tsync_inc_h;
6194
6195         switch (link->link_speed) {
6196         case ETH_LINK_SPEED_40G:
6197                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6198                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6199                 break;
6200         case ETH_LINK_SPEED_10G:
6201                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6202                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6203                 break;
6204         case ETH_LINK_SPEED_1000:
6205                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6206                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6207                 break;
6208         default:
6209                 tsync_inc_l = 0x0;
6210                 tsync_inc_h = 0x0;
6211         }
6212
6213         /* Clear timesync registers. */
6214         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6215         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6216         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6217         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6218         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6219         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6220         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6221
6222         /* Set the timesync increment value. */
6223         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6224         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6225
6226         /* Enable timestamping of PTP packets. */
6227         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6228         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6229
6230         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6231         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6232         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6233
6234         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6235         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6236
6237         return 0;
6238 }
6239
6240 static int
6241 i40e_timesync_disable(struct rte_eth_dev *dev)
6242 {
6243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6244         uint32_t tsync_ctl_l;
6245         uint32_t tsync_ctl_h;
6246
6247         /* Disable timestamping of transmitted PTP packets. */
6248         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6249         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6250
6251         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6252         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6253
6254         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6255         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6256
6257         /* Set the timesync increment value. */
6258         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6259         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6260
6261         return 0;
6262 }
6263
6264 static int
6265 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6266                                 struct timespec *timestamp, uint32_t flags)
6267 {
6268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6269         uint32_t sync_status;
6270         uint32_t rx_stmpl;
6271         uint32_t rx_stmph;
6272         uint32_t index = flags & 0x03;
6273
6274         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6275         if ((sync_status & (1 << index)) == 0)
6276                 return -EINVAL;
6277
6278         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6279         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6280
6281         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6282         timestamp->tv_nsec = 0;
6283
6284         return  0;
6285 }
6286
6287 static int
6288 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6289                                 struct timespec *timestamp)
6290 {
6291         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6292         uint32_t sync_status;
6293         uint32_t tx_stmpl;
6294         uint32_t tx_stmph;
6295
6296         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6297         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6298                 return -EINVAL;
6299
6300         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6301         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6302
6303         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6304         timestamp->tv_nsec = 0;
6305
6306         return  0;
6307 }