drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline void
 631 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 632 {
 633         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 634         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 635                     "with value 0x%08x",
 636                     reg_addr, reg_val);
 637 }
 638
 639 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 640 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 641 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 642
 643 #ifndef I40E_GLQF_ORT
 644 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 645 #endif
 646 #ifndef I40E_GLQF_PIT
 647 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 648 #endif
 649 #ifndef I40E_GLQF_L3_MAP
 650 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 651 #endif
 652
 653 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 654 {
 655         /*
 656          * Initialize registers for parsing packet type of QinQ
 657          * This should be removed from code once proper
 658          * configuration API is added to avoid configuration conflicts
 659          * between ports of the same device.
 660          */
 661         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 662         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 663         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 664 }
 665
 666 static inline void i40e_config_automask(struct i40e_pf *pf)
 667 {
 668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 669         uint32_t val;
 670
 671         /* INTENA flag is not auto-cleared for interrupt */
 672         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 673         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 674                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 675
 676         /* If support multi-driver, PF will use INT0. */
 677         if (!pf->support_multi_driver)
 678                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 679
 680         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 681 }
 682
 683 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 684
 685 /*
 686  * Add a ethertype filter to drop all flow control frames transmitted
 687  * from VSIs.
 688 */
 689 static void
 690 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 691 {
 692         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 693         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 694                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 695                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 696         int ret;
 697
 698         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 699                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 700                                 pf->main_vsi_seid, 0,
 701                                 TRUE, NULL, NULL);
 702         if (ret)
 703                 PMD_INIT_LOG(ERR,
 704                         "Failed to add filter to drop flow control frames from VSIs.");
 705 }
 706
 707 static int
 708 floating_veb_list_handler(__rte_unused const char *key,
 709                           const char *floating_veb_value,
 710                           void *opaque)
 711 {
 712         int idx = 0;
 713         unsigned int count = 0;
 714         char *end = NULL;
 715         int min, max;
 716         bool *vf_floating_veb = opaque;
 717
 718         while (isblank(*floating_veb_value))
 719                 floating_veb_value++;
 720
 721         /* Reset floating VEB configuration for VFs */
 722         for (idx = 0; idx < I40E_MAX_VF; idx++)
 723                 vf_floating_veb[idx] = false;
 724
 725         min = I40E_MAX_VF;
 726         do {
 727                 while (isblank(*floating_veb_value))
 728                         floating_veb_value++;
 729                 if (*floating_veb_value == '\0')
 730                         return -1;
 731                 errno = 0;
 732                 idx = strtoul(floating_veb_value, &end, 10);
 733                 if (errno || end == NULL)
 734                         return -1;
 735                 while (isblank(*end))
 736                         end++;
 737                 if (*end == '-') {
 738                         min = idx;
 739                 } else if ((*end == ';') || (*end == '\0')) {
 740                         max = idx;
 741                         if (min == I40E_MAX_VF)
 742                                 min = idx;
 743                         if (max >= I40E_MAX_VF)
 744                                 max = I40E_MAX_VF - 1;
 745                         for (idx = min; idx <= max; idx++) {
 746                                 vf_floating_veb[idx] = true;
 747                                 count++;
 748                         }
 749                         min = I40E_MAX_VF;
 750                 } else {
 751                         return -1;
 752                 }
 753                 floating_veb_value = end + 1;
 754         } while (*end != '\0');
 755
 756         if (count == 0)
 757                 return -1;
 758
 759         return 0;
 760 }
 761
 762 static void
 763 config_vf_floating_veb(struct rte_devargs *devargs,
 764                        uint16_t floating_veb,
 765                        bool *vf_floating_veb)
 766 {
 767         struct rte_kvargs *kvlist;
 768         int i;
 769         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 770
 771         if (!floating_veb)
 772                 return;
 773         /* All the VFs attach to the floating VEB by default
 774          * when the floating VEB is enabled.
 775          */
 776         for (i = 0; i < I40E_MAX_VF; i++)
 777                 vf_floating_veb[i] = true;
 778
 779         if (devargs == NULL)
 780                 return;
 781
 782         kvlist = rte_kvargs_parse(devargs->args, NULL);
 783         if (kvlist == NULL)
 784                 return;
 785
 786         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 787                 rte_kvargs_free(kvlist);
 788                 return;
 789         }
 790         /* When the floating_veb_list parameter exists, all the VFs
 791          * will attach to the legacy VEB firstly, then configure VFs
 792          * to the floating VEB according to the floating_veb_list.
 793          */
 794         if (rte_kvargs_process(kvlist, floating_veb_list,
 795                                floating_veb_list_handler,
 796                                vf_floating_veb) < 0) {
 797                 rte_kvargs_free(kvlist);
 798                 return;
 799         }
 800         rte_kvargs_free(kvlist);
 801 }
 802
 803 static int
 804 i40e_check_floating_handler(__rte_unused const char *key,
 805                             const char *value,
 806                             __rte_unused void *opaque)
 807 {
 808         if (strcmp(value, "1"))
 809                 return -1;
 810
 811         return 0;
 812 }
 813
 814 static int
 815 is_floating_veb_supported(struct rte_devargs *devargs)
 816 {
 817         struct rte_kvargs *kvlist;
 818         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 819
 820         if (devargs == NULL)
 821                 return 0;
 822
 823         kvlist = rte_kvargs_parse(devargs->args, NULL);
 824         if (kvlist == NULL)
 825                 return 0;
 826
 827         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 828                 rte_kvargs_free(kvlist);
 829                 return 0;
 830         }
 831         /* Floating VEB is enabled when there's key-value:
 832          * enable_floating_veb=1
 833          */
 834         if (rte_kvargs_process(kvlist, floating_veb_key,
 835                                i40e_check_floating_handler, NULL) < 0) {
 836                 rte_kvargs_free(kvlist);
 837                 return 0;
 838         }
 839         rte_kvargs_free(kvlist);
 840
 841         return 1;
 842 }
 843
 844 static void
 845 config_floating_veb(struct rte_eth_dev *dev)
 846 {
 847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 850
 851         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 852
 853         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 854                 pf->floating_veb =
 855                         is_floating_veb_supported(pci_dev->device.devargs);
 856                 config_vf_floating_veb(pci_dev->device.devargs,
 857                                        pf->floating_veb,
 858                                        pf->floating_veb_list);
 859         } else {
 860                 pf->floating_veb = false;
 861         }
 862 }
 863
 864 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 865 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 866
 867 static int
 868 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 869 {
 870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 871         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 872         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 873         int ret;
 874
 875         struct rte_hash_parameters ethertype_hash_params = {
 876                 .name = ethertype_hash_name,
 877                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 878                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 879                 .hash_func = rte_hash_crc,
 880                 .hash_func_init_val = 0,
 881                 .socket_id = rte_socket_id(),
 882         };
 883
 884         /* Initialize ethertype filter rule list and hash */
 885         TAILQ_INIT(&ethertype_rule->ethertype_list);
 886         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 887                  "ethertype_%s", dev->device->name);
 888         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 889         if (!ethertype_rule->hash_table) {
 890                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 891                 return -EINVAL;
 892         }
 893         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 894                                        sizeof(struct i40e_ethertype_filter *) *
 895                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 896                                        0);
 897         if (!ethertype_rule->hash_map) {
 898                 PMD_INIT_LOG(ERR,
 899                              "Failed to allocate memory for ethertype hash map!");
 900                 ret = -ENOMEM;
 901                 goto err_ethertype_hash_map_alloc;
 902         }
 903
 904         return 0;
 905
 906 err_ethertype_hash_map_alloc:
 907         rte_hash_free(ethertype_rule->hash_table);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 914 {
 915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 916         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 917         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 918         int ret;
 919
 920         struct rte_hash_parameters tunnel_hash_params = {
 921                 .name = tunnel_hash_name,
 922                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 923                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 924                 .hash_func = rte_hash_crc,
 925                 .hash_func_init_val = 0,
 926                 .socket_id = rte_socket_id(),
 927         };
 928
 929         /* Initialize tunnel filter rule list and hash */
 930         TAILQ_INIT(&tunnel_rule->tunnel_list);
 931         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 932                  "tunnel_%s", dev->device->name);
 933         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 934         if (!tunnel_rule->hash_table) {
 935                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 936                 return -EINVAL;
 937         }
 938         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 939                                     sizeof(struct i40e_tunnel_filter *) *
 940                                     I40E_MAX_TUNNEL_FILTER_NUM,
 941                                     0);
 942         if (!tunnel_rule->hash_map) {
 943                 PMD_INIT_LOG(ERR,
 944                              "Failed to allocate memory for tunnel hash map!");
 945                 ret = -ENOMEM;
 946                 goto err_tunnel_hash_map_alloc;
 947         }
 948
 949         return 0;
 950
 951 err_tunnel_hash_map_alloc:
 952         rte_hash_free(tunnel_rule->hash_table);
 953
 954         return ret;
 955 }
 956
 957 static int
 958 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 959 {
 960         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 961         struct i40e_fdir_info *fdir_info = &pf->fdir;
 962         char fdir_hash_name[RTE_HASH_NAMESIZE];
 963         int ret;
 964
 965         struct rte_hash_parameters fdir_hash_params = {
 966                 .name = fdir_hash_name,
 967                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 968                 .key_len = sizeof(struct i40e_fdir_input),
 969                 .hash_func = rte_hash_crc,
 970                 .hash_func_init_val = 0,
 971                 .socket_id = rte_socket_id(),
 972         };
 973
 974         /* Initialize flow director filter rule list and hash */
 975         TAILQ_INIT(&fdir_info->fdir_list);
 976         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 977                  "fdir_%s", dev->device->name);
 978         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 979         if (!fdir_info->hash_table) {
 980                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 981                 return -EINVAL;
 982         }
 983         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 984                                           sizeof(struct i40e_fdir_filter *) *
 985                                           I40E_MAX_FDIR_FILTER_NUM,
 986                                           0);
 987         if (!fdir_info->hash_map) {
 988                 PMD_INIT_LOG(ERR,
 989                              "Failed to allocate memory for fdir hash map!");
 990                 ret = -ENOMEM;
 991                 goto err_fdir_hash_map_alloc;
 992         }
 993         return 0;
 994
 995 err_fdir_hash_map_alloc:
 996         rte_hash_free(fdir_info->hash_table);
 997
 998         return ret;
 999 }
1000
1001 static void
1002 i40e_init_customized_info(struct i40e_pf *pf)
1003 {
1004         int i;
1005
1006         /* Initialize customized pctype */
1007         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1008                 pf->customized_pctype[i].index = i;
1009                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1010                 pf->customized_pctype[i].valid = false;
1011         }
1012
1013         pf->gtp_support = false;
1014 }
1015
1016 void
1017 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1018 {
1019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1021         struct i40e_queue_regions *info = &pf->queue_region;
1022         uint16_t i;
1023
1024         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1025                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1026
1027         memset(info, 0, sizeof(struct i40e_queue_regions));
1028 }
1029
1030 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1031
1032 static int
1033 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1034                                const char *value,
1035                                void *opaque)
1036 {
1037         struct i40e_pf *pf;
1038         unsigned long support_multi_driver;
1039         char *end;
1040
1041         pf = (struct i40e_pf *)opaque;
1042
1043         errno = 0;
1044         support_multi_driver = strtoul(value, &end, 10);
1045         if (errno != 0 || end == value || *end != 0) {
1046                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1047                 return -(EINVAL);
1048         }
1049
1050         if (support_multi_driver == 1 || support_multi_driver == 0)
1051                 pf->support_multi_driver = (bool)support_multi_driver;
1052         else
1053                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1054                             "enable global configuration by default."
1055                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1056         return 0;
1057 }
1058
1059 static int
1060 i40e_support_multi_driver(struct rte_eth_dev *dev)
1061 {
1062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1063         static const char *const valid_keys[] = {
1064                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1065         struct rte_kvargs *kvlist;
1066
1067         /* Enable global configuration by default */
1068         pf->support_multi_driver = false;
1069
1070         if (!dev->device->devargs)
1071                 return 0;
1072
1073         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1074         if (!kvlist)
1075                 return -EINVAL;
1076
1077         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1078                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1079                             "the first invalid or last valid one is used !",
1080                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1081
1082         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1083                                i40e_parse_multi_drv_handler, pf) < 0) {
1084                 rte_kvargs_free(kvlist);
1085                 return -EINVAL;
1086         }
1087
1088         rte_kvargs_free(kvlist);
1089         return 0;
1090 }
1091
1092 static int
1093 eth_i40e_dev_init(struct rte_eth_dev *dev)
1094 {
1095         struct rte_pci_device *pci_dev;
1096         struct rte_intr_handle *intr_handle;
1097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1098         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1099         struct i40e_vsi *vsi;
1100         int ret;
1101         uint32_t len;
1102         uint8_t aq_fail = 0;
1103
1104         PMD_INIT_FUNC_TRACE();
1105
1106         dev->dev_ops = &i40e_eth_dev_ops;
1107         dev->rx_pkt_burst = i40e_recv_pkts;
1108         dev->tx_pkt_burst = i40e_xmit_pkts;
1109         dev->tx_pkt_prepare = i40e_prep_pkts;
1110
1111         /* for secondary processes, we don't initialise any further as primary
1112          * has already done this work. Only check we don't need a different
1113          * RX function */
1114         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1115                 i40e_set_rx_function(dev);
1116                 i40e_set_tx_function(dev);
1117                 return 0;
1118         }
1119         i40e_set_default_ptype_table(dev);
1120         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1121         intr_handle = &pci_dev->intr_handle;
1122
1123         rte_eth_copy_pci_info(dev, pci_dev);
1124
1125         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1126         pf->adapter->eth_dev = dev;
1127         pf->dev_data = dev->data;
1128
1129         hw->back = I40E_PF_TO_ADAPTER(pf);
1130         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1131         if (!hw->hw_addr) {
1132                 PMD_INIT_LOG(ERR,
1133                         "Hardware is not available, as address is NULL");
1134                 return -ENODEV;
1135         }
1136
1137         hw->vendor_id = pci_dev->id.vendor_id;
1138         hw->device_id = pci_dev->id.device_id;
1139         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1140         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1141         hw->bus.device = pci_dev->addr.devid;
1142         hw->bus.func = pci_dev->addr.function;
1143         hw->adapter_stopped = 0;
1144
1145         /* Check if need to support multi-driver */
1146         i40e_support_multi_driver(dev);
1147
1148         /* Make sure all is clean before doing PF reset */
1149         i40e_clear_hw(hw);
1150
1151         /* Initialize the hardware */
1152         i40e_hw_init(dev);
1153
1154         /* Reset here to make sure all is clean for each PF */
1155         ret = i40e_pf_reset(hw);
1156         if (ret) {
1157                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1158                 return ret;
1159         }
1160
1161         /* Initialize the shared code (base driver) */
1162         ret = i40e_init_shared_code(hw);
1163         if (ret) {
1164                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1165                 return ret;
1166         }
1167
1168         i40e_config_automask(pf);
1169
1170         i40e_set_default_pctype_table(dev);
1171
1172         /*
1173          * To work around the NVM issue, initialize registers
1174          * for packet type of QinQ by software.
1175          * It should be removed once issues are fixed in NVM.
1176          */
1177         if (!pf->support_multi_driver)
1178                 i40e_GLQF_reg_init(hw);
1179
1180         /* Initialize the input set for filters (hash and fd) to default value */
1181         i40e_filter_input_set_init(pf);
1182
1183         /* Initialize the parameters for adminq */
1184         i40e_init_adminq_parameter(hw);
1185         ret = i40e_init_adminq(hw);
1186         if (ret != I40E_SUCCESS) {
1187                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1188                 return -EIO;
1189         }
1190         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1191                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1192                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1193                      ((hw->nvm.version >> 12) & 0xf),
1194                      ((hw->nvm.version >> 4) & 0xff),
1195                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1196
1197         /* initialise the L3_MAP register */
1198         if (!pf->support_multi_driver) {
1199                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1200                                                    0x00000028,  NULL);
1201                 if (ret)
1202                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1203                                      ret);
1204                 PMD_INIT_LOG(DEBUG,
1205                              "Global register 0x%08x is changed with 0x28",
1206                              I40E_GLQF_L3_MAP(40));
1207                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1208         }
1209
1210         /* Need the special FW version to support floating VEB */
1211         config_floating_veb(dev);
1212         /* Clear PXE mode */
1213         i40e_clear_pxe_mode(hw);
1214         i40e_dev_sync_phy_type(hw);
1215
1216         /*
1217          * On X710, performance number is far from the expectation on recent
1218          * firmware versions. The fix for this issue may not be integrated in
1219          * the following firmware version. So the workaround in software driver
1220          * is needed. It needs to modify the initial values of 3 internal only
1221          * registers. Note that the workaround can be removed when it is fixed
1222          * in firmware in the future.
1223          */
1224         i40e_configure_registers(hw);
1225
1226         /* Get hw capabilities */
1227         ret = i40e_get_cap(hw);
1228         if (ret != I40E_SUCCESS) {
1229                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1230                 goto err_get_capabilities;
1231         }
1232
1233         /* Initialize parameters for PF */
1234         ret = i40e_pf_parameter_init(dev);
1235         if (ret != 0) {
1236                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1237                 goto err_parameter_init;
1238         }
1239
1240         /* Initialize the queue management */
1241         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1242         if (ret < 0) {
1243                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1244                 goto err_qp_pool_init;
1245         }
1246         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1247                                 hw->func_caps.num_msix_vectors - 1);
1248         if (ret < 0) {
1249                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1250                 goto err_msix_pool_init;
1251         }
1252
1253         /* Initialize lan hmc */
1254         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1255                                 hw->func_caps.num_rx_qp, 0, 0);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1258                 goto err_init_lan_hmc;
1259         }
1260
1261         /* Configure lan hmc */
1262         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1263         if (ret != I40E_SUCCESS) {
1264                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1265                 goto err_configure_lan_hmc;
1266         }
1267
1268         /* Get and check the mac address */
1269         i40e_get_mac_addr(hw, hw->mac.addr);
1270         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(ERR, "mac address is not valid");
1272                 ret = -EIO;
1273                 goto err_get_mac_addr;
1274         }
1275         /* Copy the permanent MAC address */
1276         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1277                         (struct ether_addr *) hw->mac.perm_addr);
1278
1279         /* Disable flow control */
1280         hw->fc.requested_mode = I40E_FC_NONE;
1281         i40e_set_fc(hw, &aq_fail, TRUE);
1282
1283         /* Set the global registers with default ether type value */
1284         if (!pf->support_multi_driver) {
1285                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1286                                          ETHER_TYPE_VLAN);
1287                 if (ret != I40E_SUCCESS) {
1288                         PMD_INIT_LOG(ERR,
1289                                      "Failed to set the default outer "
1290                                      "VLAN ether type");
1291                         goto err_setup_pf_switch;
1292                 }
1293         }
1294
1295         /* PF setup, which includes VSI setup */
1296         ret = i40e_pf_setup(pf);
1297         if (ret) {
1298                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1299                 goto err_setup_pf_switch;
1300         }
1301
1302         /* reset all stats of the device, including pf and main vsi */
1303         i40e_dev_stats_reset(dev);
1304
1305         vsi = pf->main_vsi;
1306
1307         /* Disable double vlan by default */
1308         i40e_vsi_config_double_vlan(vsi, FALSE);
1309
1310         /* Disable S-TAG identification when floating_veb is disabled */
1311         if (!pf->floating_veb) {
1312                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1313                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1314                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1315                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1316                 }
1317         }
1318
1319         if (!vsi->max_macaddrs)
1320                 len = ETHER_ADDR_LEN;
1321         else
1322                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1323
1324         /* Should be after VSI initialized */
1325         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1326         if (!dev->data->mac_addrs) {
1327                 PMD_INIT_LOG(ERR,
1328                         "Failed to allocated memory for storing mac address");
1329                 goto err_mac_alloc;
1330         }
1331         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1332                                         &dev->data->mac_addrs[0]);
1333
1334         /* Init dcb to sw mode by default */
1335         ret = i40e_dcb_init_configure(dev, TRUE);
1336         if (ret != I40E_SUCCESS) {
1337                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1338                 pf->flags &= ~I40E_FLAG_DCB;
1339         }
1340         /* Update HW struct after DCB configuration */
1341         i40e_get_cap(hw);
1342
1343         /* initialize pf host driver to setup SRIOV resource if applicable */
1344         i40e_pf_host_init(dev);
1345
1346         /* register callback func to eal lib */
1347         rte_intr_callback_register(intr_handle,
1348                                    i40e_dev_interrupt_handler, dev);
1349
1350         /* configure and enable device interrupt */
1351         i40e_pf_config_irq0(hw, TRUE);
1352         i40e_pf_enable_irq0(hw);
1353
1354         /* enable uio intr after callback register */
1355         rte_intr_enable(intr_handle);
1356
1357         /* By default disable flexible payload in global configuration */
1358         if (!pf->support_multi_driver)
1359                 i40e_flex_payload_reg_set_default(hw);
1360
1361         /*
1362          * Add an ethertype filter to drop all flow control frames transmitted
1363          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1364          * frames to wire.
1365          */
1366         i40e_add_tx_flow_control_drop_filter(pf);
1367
1368         /* Set the max frame size to 0x2600 by default,
1369          * in case other drivers changed the default value.
1370          */
1371         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1372
1373         /* initialize mirror rule list */
1374         TAILQ_INIT(&pf->mirror_list);
1375
1376         /* initialize Traffic Manager configuration */
1377         i40e_tm_conf_init(dev);
1378
1379         /* Initialize customized information */
1380         i40e_init_customized_info(pf);
1381
1382         ret = i40e_init_ethtype_filter_list(dev);
1383         if (ret < 0)
1384                 goto err_init_ethtype_filter_list;
1385         ret = i40e_init_tunnel_filter_list(dev);
1386         if (ret < 0)
1387                 goto err_init_tunnel_filter_list;
1388         ret = i40e_init_fdir_filter_list(dev);
1389         if (ret < 0)
1390                 goto err_init_fdir_filter_list;
1391
1392         /* initialize queue region configuration */
1393         i40e_init_queue_region_conf(dev);
1394
1395         /* initialize rss configuration from rte_flow */
1396         memset(&pf->rss_info, 0,
1397                 sizeof(struct i40e_rte_flow_rss_conf));
1398
1399         return 0;
1400
1401 err_init_fdir_filter_list:
1402         rte_free(pf->tunnel.hash_table);
1403         rte_free(pf->tunnel.hash_map);
1404 err_init_tunnel_filter_list:
1405         rte_free(pf->ethertype.hash_table);
1406         rte_free(pf->ethertype.hash_map);
1407 err_init_ethtype_filter_list:
1408         rte_free(dev->data->mac_addrs);
1409 err_mac_alloc:
1410         i40e_vsi_release(pf->main_vsi);
1411 err_setup_pf_switch:
1412 err_get_mac_addr:
1413 err_configure_lan_hmc:
1414         (void)i40e_shutdown_lan_hmc(hw);
1415 err_init_lan_hmc:
1416         i40e_res_pool_destroy(&pf->msix_pool);
1417 err_msix_pool_init:
1418         i40e_res_pool_destroy(&pf->qp_pool);
1419 err_qp_pool_init:
1420 err_parameter_init:
1421 err_get_capabilities:
1422         (void)i40e_shutdown_adminq(hw);
1423
1424         return ret;
1425 }
1426
1427 static void
1428 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1429 {
1430         struct i40e_ethertype_filter *p_ethertype;
1431         struct i40e_ethertype_rule *ethertype_rule;
1432
1433         ethertype_rule = &pf->ethertype;
1434         /* Remove all ethertype filter rules and hash */
1435         if (ethertype_rule->hash_map)
1436                 rte_free(ethertype_rule->hash_map);
1437         if (ethertype_rule->hash_table)
1438                 rte_hash_free(ethertype_rule->hash_table);
1439
1440         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1441                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1442                              p_ethertype, rules);
1443                 rte_free(p_ethertype);
1444         }
1445 }
1446
1447 static void
1448 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1449 {
1450         struct i40e_tunnel_filter *p_tunnel;
1451         struct i40e_tunnel_rule *tunnel_rule;
1452
1453         tunnel_rule = &pf->tunnel;
1454         /* Remove all tunnel director rules and hash */
1455         if (tunnel_rule->hash_map)
1456                 rte_free(tunnel_rule->hash_map);
1457         if (tunnel_rule->hash_table)
1458                 rte_hash_free(tunnel_rule->hash_table);
1459
1460         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1461                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1462                 rte_free(p_tunnel);
1463         }
1464 }
1465
1466 static void
1467 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1468 {
1469         struct i40e_fdir_filter *p_fdir;
1470         struct i40e_fdir_info *fdir_info;
1471
1472         fdir_info = &pf->fdir;
1473         /* Remove all flow director rules and hash */
1474         if (fdir_info->hash_map)
1475                 rte_free(fdir_info->hash_map);
1476         if (fdir_info->hash_table)
1477                 rte_hash_free(fdir_info->hash_table);
1478
1479         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1480                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1481                 rte_free(p_fdir);
1482         }
1483 }
1484
1485 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1486 {
1487         /*
1488          * Disable by default flexible payload
1489          * for corresponding L2/L3/L4 layers.
1490          */
1491         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1492         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1493         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1494         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1495 }
1496
1497 static int
1498 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1499 {
1500         struct i40e_pf *pf;
1501         struct rte_pci_device *pci_dev;
1502         struct rte_intr_handle *intr_handle;
1503         struct i40e_hw *hw;
1504         struct i40e_filter_control_settings settings;
1505         struct rte_flow *p_flow;
1506         int ret;
1507         uint8_t aq_fail = 0;
1508         int retries = 0;
1509
1510         PMD_INIT_FUNC_TRACE();
1511
1512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1513                 return 0;
1514
1515         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1518         intr_handle = &pci_dev->intr_handle;
1519
1520         if (hw->adapter_stopped == 0)
1521                 i40e_dev_close(dev);
1522
1523         dev->dev_ops = NULL;
1524         dev->rx_pkt_burst = NULL;
1525         dev->tx_pkt_burst = NULL;
1526
1527         /* Clear PXE mode */
1528         i40e_clear_pxe_mode(hw);
1529
1530         /* Unconfigure filter control */
1531         memset(&settings, 0, sizeof(settings));
1532         ret = i40e_set_filter_control(hw, &settings);
1533         if (ret)
1534                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1535                                         ret);
1536
1537         /* Disable flow control */
1538         hw->fc.requested_mode = I40E_FC_NONE;
1539         i40e_set_fc(hw, &aq_fail, TRUE);
1540
1541         /* uninitialize pf host driver */
1542         i40e_pf_host_uninit(dev);
1543
1544         rte_free(dev->data->mac_addrs);
1545         dev->data->mac_addrs = NULL;
1546
1547         /* disable uio intr before callback unregister */
1548         rte_intr_disable(intr_handle);
1549
1550         /* unregister callback func to eal lib */
1551         do {
1552                 ret = rte_intr_callback_unregister(intr_handle,
1553                                 i40e_dev_interrupt_handler, dev);
1554                 if (ret >= 0) {
1555                         break;
1556                 } else if (ret != -EAGAIN) {
1557                         PMD_INIT_LOG(ERR,
1558                                  "intr callback unregister failed: %d",
1559                                  ret);
1560                         return ret;
1561                 }
1562                 i40e_msec_delay(500);
1563         } while (retries++ < 5);
1564
1565         i40e_rm_ethtype_filter_list(pf);
1566         i40e_rm_tunnel_filter_list(pf);
1567         i40e_rm_fdir_filter_list(pf);
1568
1569         /* Remove all flows */
1570         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1571                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1572                 rte_free(p_flow);
1573         }
1574
1575         /* Remove all Traffic Manager configuration */
1576         i40e_tm_conf_uninit(dev);
1577
1578         return 0;
1579 }
1580
1581 static int
1582 i40e_dev_configure(struct rte_eth_dev *dev)
1583 {
1584         struct i40e_adapter *ad =
1585                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1589         int i, ret;
1590
1591         ret = i40e_dev_sync_phy_type(hw);
1592         if (ret)
1593                 return ret;
1594
1595         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1596          * bulk allocation or vector Rx preconditions we will reset it.
1597          */
1598         ad->rx_bulk_alloc_allowed = true;
1599         ad->rx_vec_allowed = true;
1600         ad->tx_simple_allowed = true;
1601         ad->tx_vec_allowed = true;
1602
1603         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1604                 ret = i40e_fdir_setup(pf);
1605                 if (ret != I40E_SUCCESS) {
1606                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1607                         return -ENOTSUP;
1608                 }
1609                 ret = i40e_fdir_configure(dev);
1610                 if (ret < 0) {
1611                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1612                         goto err;
1613                 }
1614         } else
1615                 i40e_fdir_teardown(pf);
1616
1617         ret = i40e_dev_init_vlan(dev);
1618         if (ret < 0)
1619                 goto err;
1620
1621         /* VMDQ setup.
1622          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1623          *  RSS setting have different requirements.
1624          *  General PMD driver call sequence are NIC init, configure,
1625          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1626          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1627          *  applicable. So, VMDQ setting has to be done before
1628          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1629          *  For RSS setting, it will try to calculate actual configured RX queue
1630          *  number, which will be available after rx_queue_setup(). dev_start()
1631          *  function is good to place RSS setup.
1632          */
1633         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1634                 ret = i40e_vmdq_setup(dev);
1635                 if (ret)
1636                         goto err;
1637         }
1638
1639         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1640                 ret = i40e_dcb_setup(dev);
1641                 if (ret) {
1642                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1643                         goto err_dcb;
1644                 }
1645         }
1646
1647         TAILQ_INIT(&pf->flow_list);
1648
1649         return 0;
1650
1651 err_dcb:
1652         /* need to release vmdq resource if exists */
1653         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1654                 i40e_vsi_release(pf->vmdq[i].vsi);
1655                 pf->vmdq[i].vsi = NULL;
1656         }
1657         rte_free(pf->vmdq);
1658         pf->vmdq = NULL;
1659 err:
1660         /* need to release fdir resource if exists */
1661         i40e_fdir_teardown(pf);
1662         return ret;
1663 }
1664
1665 void
1666 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1667 {
1668         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1669         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1670         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1671         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1672         uint16_t msix_vect = vsi->msix_intr;
1673         uint16_t i;
1674
1675         for (i = 0; i < vsi->nb_qps; i++) {
1676                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1677                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1678                 rte_wmb();
1679         }
1680
1681         if (vsi->type != I40E_VSI_SRIOV) {
1682                 if (!rte_intr_allow_others(intr_handle)) {
1683                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1684                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1685                         I40E_WRITE_REG(hw,
1686                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1687                                        0);
1688                 } else {
1689                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1690                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1691                         I40E_WRITE_REG(hw,
1692                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1693                                                        msix_vect - 1), 0);
1694                 }
1695         } else {
1696                 uint32_t reg;
1697                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1698                         vsi->user_param + (msix_vect - 1);
1699
1700                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1701                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1702         }
1703         I40E_WRITE_FLUSH(hw);
1704 }
1705
1706 static void
1707 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1708                        int base_queue, int nb_queue,
1709                        uint16_t itr_idx)
1710 {
1711         int i;
1712         uint32_t val;
1713         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1714         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1715
1716         /* Bind all RX queues to allocated MSIX interrupt */
1717         for (i = 0; i < nb_queue; i++) {
1718                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1719                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1720                         ((base_queue + i + 1) <<
1721                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1722                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1723                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1724
1725                 if (i == nb_queue - 1)
1726                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1727                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1728         }
1729
1730         /* Write first RX queue to Link list register as the head element */
1731         if (vsi->type != I40E_VSI_SRIOV) {
1732                 uint16_t interval =
1733                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1734                                                pf->support_multi_driver);
1735
1736                 if (msix_vect == I40E_MISC_VEC_ID) {
1737                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1738                                        (base_queue <<
1739                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1740                                        (0x0 <<
1741                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1742                         I40E_WRITE_REG(hw,
1743                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1744                                        interval);
1745                 } else {
1746                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1747                                        (base_queue <<
1748                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1749                                        (0x0 <<
1750                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1751                         I40E_WRITE_REG(hw,
1752                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1753                                                        msix_vect - 1),
1754                                        interval);
1755                 }
1756         } else {
1757                 uint32_t reg;
1758
1759                 if (msix_vect == I40E_MISC_VEC_ID) {
1760                         I40E_WRITE_REG(hw,
1761                                        I40E_VPINT_LNKLST0(vsi->user_param),
1762                                        (base_queue <<
1763                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1764                                        (0x0 <<
1765                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1766                 } else {
1767                         /* num_msix_vectors_vf needs to minus irq0 */
1768                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1769                                 vsi->user_param + (msix_vect - 1);
1770
1771                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1772                                        (base_queue <<
1773                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1774                                        (0x0 <<
1775                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1776                 }
1777         }
1778
1779         I40E_WRITE_FLUSH(hw);
1780 }
1781
1782 void
1783 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1784 {
1785         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1788         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1789         uint16_t msix_vect = vsi->msix_intr;
1790         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1791         uint16_t queue_idx = 0;
1792         int record = 0;
1793         int i;
1794
1795         for (i = 0; i < vsi->nb_qps; i++) {
1796                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1797                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1798         }
1799
1800         /* VF bind interrupt */
1801         if (vsi->type == I40E_VSI_SRIOV) {
1802                 __vsi_queues_bind_intr(vsi, msix_vect,
1803                                        vsi->base_queue, vsi->nb_qps,
1804                                        itr_idx);
1805                 return;
1806         }
1807
1808         /* PF & VMDq bind interrupt */
1809         if (rte_intr_dp_is_en(intr_handle)) {
1810                 if (vsi->type == I40E_VSI_MAIN) {
1811                         queue_idx = 0;
1812                         record = 1;
1813                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1814                         struct i40e_vsi *main_vsi =
1815                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1816                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1817                         record = 1;
1818                 }
1819         }
1820
1821         for (i = 0; i < vsi->nb_used_qps; i++) {
1822                 if (nb_msix <= 1) {
1823                         if (!rte_intr_allow_others(intr_handle))
1824                                 /* allow to share MISC_VEC_ID */
1825                                 msix_vect = I40E_MISC_VEC_ID;
1826
1827                         /* no enough msix_vect, map all to one */
1828                         __vsi_queues_bind_intr(vsi, msix_vect,
1829                                                vsi->base_queue + i,
1830                                                vsi->nb_used_qps - i,
1831                                                itr_idx);
1832                         for (; !!record && i < vsi->nb_used_qps; i++)
1833                                 intr_handle->intr_vec[queue_idx + i] =
1834                                         msix_vect;
1835                         break;
1836                 }
1837                 /* 1:1 queue/msix_vect mapping */
1838                 __vsi_queues_bind_intr(vsi, msix_vect,
1839                                        vsi->base_queue + i, 1,
1840                                        itr_idx);
1841                 if (!!record)
1842                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1843
1844                 msix_vect++;
1845                 nb_msix--;
1846         }
1847 }
1848
1849 static void
1850 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1851 {
1852         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1853         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1854         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1855         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1856         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1857         uint16_t msix_intr, i;
1858
1859         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1860                 for (i = 0; i < vsi->nb_msix; i++) {
1861                         msix_intr = vsi->msix_intr + i;
1862                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1863                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1864                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1865                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1866                 }
1867         else
1868                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1869                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1870                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1871                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1872
1873         I40E_WRITE_FLUSH(hw);
1874 }
1875
1876 static void
1877 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1878 {
1879         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1880         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1881         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1882         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1883         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1884         uint16_t msix_intr, i;
1885
1886         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1887                 for (i = 0; i < vsi->nb_msix; i++) {
1888                         msix_intr = vsi->msix_intr + i;
1889                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1890                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1891                 }
1892         else
1893                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1894                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1895
1896         I40E_WRITE_FLUSH(hw);
1897 }
1898
1899 static inline uint8_t
1900 i40e_parse_link_speeds(uint16_t link_speeds)
1901 {
1902         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1903
1904         if (link_speeds & ETH_LINK_SPEED_40G)
1905                 link_speed |= I40E_LINK_SPEED_40GB;
1906         if (link_speeds & ETH_LINK_SPEED_25G)
1907                 link_speed |= I40E_LINK_SPEED_25GB;
1908         if (link_speeds & ETH_LINK_SPEED_20G)
1909                 link_speed |= I40E_LINK_SPEED_20GB;
1910         if (link_speeds & ETH_LINK_SPEED_10G)
1911                 link_speed |= I40E_LINK_SPEED_10GB;
1912         if (link_speeds & ETH_LINK_SPEED_1G)
1913                 link_speed |= I40E_LINK_SPEED_1GB;
1914         if (link_speeds & ETH_LINK_SPEED_100M)
1915                 link_speed |= I40E_LINK_SPEED_100MB;
1916
1917         return link_speed;
1918 }
1919
1920 static int
1921 i40e_phy_conf_link(struct i40e_hw *hw,
1922                    uint8_t abilities,
1923                    uint8_t force_speed,
1924                    bool is_up)
1925 {
1926         enum i40e_status_code status;
1927         struct i40e_aq_get_phy_abilities_resp phy_ab;
1928         struct i40e_aq_set_phy_config phy_conf;
1929         enum i40e_aq_phy_type cnt;
1930         uint32_t phy_type_mask = 0;
1931
1932         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1933                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1934                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1935                         I40E_AQ_PHY_FLAG_LOW_POWER;
1936         const uint8_t advt = I40E_LINK_SPEED_40GB |
1937                         I40E_LINK_SPEED_25GB |
1938                         I40E_LINK_SPEED_10GB |
1939                         I40E_LINK_SPEED_1GB |
1940                         I40E_LINK_SPEED_100MB;
1941         int ret = -ENOTSUP;
1942
1943
1944         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1945                                               NULL);
1946         if (status)
1947                 return ret;
1948
1949         /* If link already up, no need to set up again */
1950         if (is_up && phy_ab.phy_type != 0)
1951                 return I40E_SUCCESS;
1952
1953         memset(&phy_conf, 0, sizeof(phy_conf));
1954
1955         /* bits 0-2 use the values from get_phy_abilities_resp */
1956         abilities &= ~mask;
1957         abilities |= phy_ab.abilities & mask;
1958
1959         /* update ablities and speed */
1960         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1961                 phy_conf.link_speed = advt;
1962         else
1963                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1964
1965         phy_conf.abilities = abilities;
1966
1967
1968
1969         /* To enable link, phy_type mask needs to include each type */
1970         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1971                 phy_type_mask |= 1 << cnt;
1972
1973         /* use get_phy_abilities_resp value for the rest */
1974         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1975         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1976                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1977                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1978         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1979         phy_conf.eee_capability = phy_ab.eee_capability;
1980         phy_conf.eeer = phy_ab.eeer_val;
1981         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1982
1983         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1984                     phy_ab.abilities, phy_ab.link_speed);
1985         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1986                     phy_conf.abilities, phy_conf.link_speed);
1987
1988         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1989         if (status)
1990                 return ret;
1991
1992         return I40E_SUCCESS;
1993 }
1994
1995 static int
1996 i40e_apply_link_speed(struct rte_eth_dev *dev)
1997 {
1998         uint8_t speed;
1999         uint8_t abilities = 0;
2000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         struct rte_eth_conf *conf = &dev->data->dev_conf;
2002
2003         speed = i40e_parse_link_speeds(conf->link_speeds);
2004         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2005         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2006                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2007         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2008
2009         return i40e_phy_conf_link(hw, abilities, speed, true);
2010 }
2011
2012 static int
2013 i40e_dev_start(struct rte_eth_dev *dev)
2014 {
2015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct i40e_vsi *main_vsi = pf->main_vsi;
2018         int ret, i;
2019         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2020         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2021         uint32_t intr_vector = 0;
2022         struct i40e_vsi *vsi;
2023
2024         hw->adapter_stopped = 0;
2025
2026         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2027                 PMD_INIT_LOG(ERR,
2028                 "Invalid link_speeds for port %u, autonegotiation disabled",
2029                               dev->data->port_id);
2030                 return -EINVAL;
2031         }
2032
2033         rte_intr_disable(intr_handle);
2034
2035         if ((rte_intr_cap_multiple(intr_handle) ||
2036              !RTE_ETH_DEV_SRIOV(dev).active) &&
2037             dev->data->dev_conf.intr_conf.rxq != 0) {
2038                 intr_vector = dev->data->nb_rx_queues;
2039                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2040                 if (ret)
2041                         return ret;
2042         }
2043
2044         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2045                 intr_handle->intr_vec =
2046                         rte_zmalloc("intr_vec",
2047                                     dev->data->nb_rx_queues * sizeof(int),
2048                                     0);
2049                 if (!intr_handle->intr_vec) {
2050                         PMD_INIT_LOG(ERR,
2051                                 "Failed to allocate %d rx_queues intr_vec",
2052                                 dev->data->nb_rx_queues);
2053                         return -ENOMEM;
2054                 }
2055         }
2056
2057         /* Initialize VSI */
2058         ret = i40e_dev_rxtx_init(pf);
2059         if (ret != I40E_SUCCESS) {
2060                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2061                 goto err_up;
2062         }
2063
2064         /* Map queues with MSIX interrupt */
2065         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2066                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2067         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2068         i40e_vsi_enable_queues_intr(main_vsi);
2069
2070         /* Map VMDQ VSI queues with MSIX interrupt */
2071         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2072                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2073                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2074                                           I40E_ITR_INDEX_DEFAULT);
2075                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2076         }
2077
2078         /* enable FDIR MSIX interrupt */
2079         if (pf->fdir.fdir_vsi) {
2080                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2081                                           I40E_ITR_INDEX_NONE);
2082                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2083         }
2084
2085         /* Enable all queues which have been configured */
2086         ret = i40e_dev_switch_queues(pf, TRUE);
2087         if (ret != I40E_SUCCESS) {
2088                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2089                 goto err_up;
2090         }
2091
2092         /* Enable receiving broadcast packets */
2093         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2094         if (ret != I40E_SUCCESS)
2095                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2096
2097         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2098                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2099                                                 true, NULL);
2100                 if (ret != I40E_SUCCESS)
2101                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2102         }
2103
2104         /* Enable the VLAN promiscuous mode. */
2105         if (pf->vfs) {
2106                 for (i = 0; i < pf->vf_num; i++) {
2107                         vsi = pf->vfs[i].vsi;
2108                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2109                                                      true, NULL);
2110                 }
2111         }
2112
2113         /* Enable mac loopback mode */
2114         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2115             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2116                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2117                 if (ret != I40E_SUCCESS) {
2118                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2119                         goto err_up;
2120                 }
2121         }
2122
2123         /* Apply link configure */
2124         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2125                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2126                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2127                                 ETH_LINK_SPEED_40G)) {
2128                 PMD_DRV_LOG(ERR, "Invalid link setting");
2129                 goto err_up;
2130         }
2131         ret = i40e_apply_link_speed(dev);
2132         if (I40E_SUCCESS != ret) {
2133                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2134                 goto err_up;
2135         }
2136
2137         if (!rte_intr_allow_others(intr_handle)) {
2138                 rte_intr_callback_unregister(intr_handle,
2139                                              i40e_dev_interrupt_handler,
2140                                              (void *)dev);
2141                 /* configure and enable device interrupt */
2142                 i40e_pf_config_irq0(hw, FALSE);
2143                 i40e_pf_enable_irq0(hw);
2144
2145                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2146                         PMD_INIT_LOG(INFO,
2147                                 "lsc won't enable because of no intr multiplex");
2148         } else {
2149                 ret = i40e_aq_set_phy_int_mask(hw,
2150                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2151                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2152                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2153                 if (ret != I40E_SUCCESS)
2154                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2155
2156                 /* Call get_link_info aq commond to enable/disable LSE */
2157                 i40e_dev_link_update(dev, 0);
2158         }
2159
2160         /* enable uio intr after callback register */
2161         rte_intr_enable(intr_handle);
2162
2163         i40e_filter_restore(pf);
2164
2165         if (pf->tm_conf.root && !pf->tm_conf.committed)
2166                 PMD_DRV_LOG(WARNING,
2167                             "please call hierarchy_commit() "
2168                             "before starting the port");
2169
2170         return I40E_SUCCESS;
2171
2172 err_up:
2173         i40e_dev_switch_queues(pf, FALSE);
2174         i40e_dev_clear_queues(dev);
2175
2176         return ret;
2177 }
2178
2179 static void
2180 i40e_dev_stop(struct rte_eth_dev *dev)
2181 {
2182         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2184         struct i40e_vsi *main_vsi = pf->main_vsi;
2185         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2186         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2187         int i;
2188
2189         if (hw->adapter_stopped == 1)
2190                 return;
2191         /* Disable all queues */
2192         i40e_dev_switch_queues(pf, FALSE);
2193
2194         /* un-map queues with interrupt registers */
2195         i40e_vsi_disable_queues_intr(main_vsi);
2196         i40e_vsi_queues_unbind_intr(main_vsi);
2197
2198         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2199                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2200                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2201         }
2202
2203         if (pf->fdir.fdir_vsi) {
2204                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2205                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2206         }
2207         /* Clear all queues and release memory */
2208         i40e_dev_clear_queues(dev);
2209
2210         /* Set link down */
2211         i40e_dev_set_link_down(dev);
2212
2213         if (!rte_intr_allow_others(intr_handle))
2214                 /* resume to the default handler */
2215                 rte_intr_callback_register(intr_handle,
2216                                            i40e_dev_interrupt_handler,
2217                                            (void *)dev);
2218
2219         /* Clean datapath event and queue/vec mapping */
2220         rte_intr_efd_disable(intr_handle);
2221         if (intr_handle->intr_vec) {
2222                 rte_free(intr_handle->intr_vec);
2223                 intr_handle->intr_vec = NULL;
2224         }
2225
2226         /* reset hierarchy commit */
2227         pf->tm_conf.committed = false;
2228
2229         hw->adapter_stopped = 1;
2230 }
2231
2232 static void
2233 i40e_dev_close(struct rte_eth_dev *dev)
2234 {
2235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2238         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2239         struct i40e_mirror_rule *p_mirror;
2240         uint32_t reg;
2241         int i;
2242         int ret;
2243
2244         PMD_INIT_FUNC_TRACE();
2245
2246         i40e_dev_stop(dev);
2247
2248         /* Remove all mirror rules */
2249         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2250                 ret = i40e_aq_del_mirror_rule(hw,
2251                                               pf->main_vsi->veb->seid,
2252                                               p_mirror->rule_type,
2253                                               p_mirror->entries,
2254                                               p_mirror->num_entries,
2255                                               p_mirror->id);
2256                 if (ret < 0)
2257                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2258                                     "status = %d, aq_err = %d.", ret,
2259                                     hw->aq.asq_last_status);
2260
2261                 /* remove mirror software resource anyway */
2262                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2263                 rte_free(p_mirror);
2264                 pf->nb_mirror_rule--;
2265         }
2266
2267         i40e_dev_free_queues(dev);
2268
2269         /* Disable interrupt */
2270         i40e_pf_disable_irq0(hw);
2271         rte_intr_disable(intr_handle);
2272
2273         /* shutdown and destroy the HMC */
2274         i40e_shutdown_lan_hmc(hw);
2275
2276         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2277                 i40e_vsi_release(pf->vmdq[i].vsi);
2278                 pf->vmdq[i].vsi = NULL;
2279         }
2280         rte_free(pf->vmdq);
2281         pf->vmdq = NULL;
2282
2283         /* release all the existing VSIs and VEBs */
2284         i40e_fdir_teardown(pf);
2285         i40e_vsi_release(pf->main_vsi);
2286
2287         /* shutdown the adminq */
2288         i40e_aq_queue_shutdown(hw, true);
2289         i40e_shutdown_adminq(hw);
2290
2291         i40e_res_pool_destroy(&pf->qp_pool);
2292         i40e_res_pool_destroy(&pf->msix_pool);
2293
2294         /* Disable flexible payload in global configuration */
2295         if (!pf->support_multi_driver)
2296                 i40e_flex_payload_reg_set_default(hw);
2297
2298         /* force a PF reset to clean anything leftover */
2299         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2300         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2301                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2302         I40E_WRITE_FLUSH(hw);
2303 }
2304
2305 /*
2306  * Reset PF device only to re-initialize resources in PMD layer
2307  */
2308 static int
2309 i40e_dev_reset(struct rte_eth_dev *dev)
2310 {
2311         int ret;
2312
2313         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2314          * its VF to make them align with it. The detailed notification
2315          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2316          * To avoid unexpected behavior in VF, currently reset of PF with
2317          * SR-IOV activation is not supported. It might be supported later.
2318          */
2319         if (dev->data->sriov.active)
2320                 return -ENOTSUP;
2321
2322         ret = eth_i40e_dev_uninit(dev);
2323         if (ret)
2324                 return ret;
2325
2326         ret = eth_i40e_dev_init(dev);
2327
2328         return ret;
2329 }
2330
2331 static void
2332 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2333 {
2334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2336         struct i40e_vsi *vsi = pf->main_vsi;
2337         int status;
2338
2339         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2340                                                      true, NULL, true);
2341         if (status != I40E_SUCCESS)
2342                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2343
2344         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2345                                                         TRUE, NULL);
2346         if (status != I40E_SUCCESS)
2347                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2348
2349 }
2350
2351 static void
2352 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2353 {
2354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2356         struct i40e_vsi *vsi = pf->main_vsi;
2357         int status;
2358
2359         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2360                                                      false, NULL, true);
2361         if (status != I40E_SUCCESS)
2362                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2363
2364         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2365                                                         false, NULL);
2366         if (status != I40E_SUCCESS)
2367                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2368 }
2369
2370 static void
2371 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2372 {
2373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2375         struct i40e_vsi *vsi = pf->main_vsi;
2376         int ret;
2377
2378         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2379         if (ret != I40E_SUCCESS)
2380                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2381 }
2382
2383 static void
2384 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2385 {
2386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct i40e_vsi *vsi = pf->main_vsi;
2389         int ret;
2390
2391         if (dev->data->promiscuous == 1)
2392                 return; /* must remain in all_multicast mode */
2393
2394         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2395                                 vsi->seid, FALSE, NULL);
2396         if (ret != I40E_SUCCESS)
2397                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2398 }
2399
2400 /*
2401  * Set device link up.
2402  */
2403 static int
2404 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2405 {
2406         /* re-apply link speed setting */
2407         return i40e_apply_link_speed(dev);
2408 }
2409
2410 /*
2411  * Set device link down.
2412  */
2413 static int
2414 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2415 {
2416         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2417         uint8_t abilities = 0;
2418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419
2420         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2421         return i40e_phy_conf_link(hw, abilities, speed, false);
2422 }
2423
2424 static __rte_always_inline void
2425 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2426 {
2427 /* Link status registers and values*/
2428 #define I40E_PRTMAC_LINKSTA             0x001E2420
2429 #define I40E_REG_LINK_UP                0x40000080
2430 #define I40E_PRTMAC_MACC                0x001E24E0
2431 #define I40E_REG_MACC_25GB              0x00020000
2432 #define I40E_REG_SPEED_MASK             0x38000000
2433 #define I40E_REG_SPEED_100MB            0x00000000
2434 #define I40E_REG_SPEED_1GB              0x08000000
2435 #define I40E_REG_SPEED_10GB             0x10000000
2436 #define I40E_REG_SPEED_20GB             0x20000000
2437 #define I40E_REG_SPEED_25_40GB          0x18000000
2438         uint32_t link_speed;
2439         uint32_t reg_val;
2440
2441         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2442         link_speed = reg_val & I40E_REG_SPEED_MASK;
2443         reg_val &= I40E_REG_LINK_UP;
2444         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2445
2446         if (unlikely(link->link_status != 0))
2447                 return;
2448
2449         /* Parse the link status */
2450         switch (link_speed) {
2451         case I40E_REG_SPEED_100MB:
2452                 link->link_speed = ETH_SPEED_NUM_100M;
2453                 break;
2454         case I40E_REG_SPEED_1GB:
2455                 link->link_speed = ETH_SPEED_NUM_1G;
2456                 break;
2457         case I40E_REG_SPEED_10GB:
2458                 link->link_speed = ETH_SPEED_NUM_10G;
2459                 break;
2460         case I40E_REG_SPEED_20GB:
2461                 link->link_speed = ETH_SPEED_NUM_20G;
2462                 break;
2463         case I40E_REG_SPEED_25_40GB:
2464                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2465
2466                 if (reg_val & I40E_REG_MACC_25GB)
2467                         link->link_speed = ETH_SPEED_NUM_25G;
2468                 else
2469                         link->link_speed = ETH_SPEED_NUM_40G;
2470
2471                 break;
2472         default:
2473                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2474                 break;
2475         }
2476 }
2477
2478 static __rte_always_inline void
2479 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2480         bool enable_lse)
2481 {
2482 #define CHECK_INTERVAL             100  /* 100ms */
2483 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2484         uint32_t rep_cnt = MAX_REPEAT_TIME;
2485         struct i40e_link_status link_status;
2486         int status;
2487
2488         memset(&link_status, 0, sizeof(link_status));
2489
2490         do {
2491                 memset(&link_status, 0, sizeof(link_status));
2492
2493                 /* Get link status information from hardware */
2494                 status = i40e_aq_get_link_info(hw, enable_lse,
2495                                                 &link_status, NULL);
2496                 if (unlikely(status != I40E_SUCCESS)) {
2497                         link->link_speed = ETH_SPEED_NUM_100M;
2498                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2499                         PMD_DRV_LOG(ERR, "Failed to get link info");
2500                         return;
2501                 }
2502
2503                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2504                 if (unlikely(link->link_status != 0))
2505                         return;
2506
2507                 rte_delay_ms(CHECK_INTERVAL);
2508         } while (--rep_cnt);
2509
2510         /* Parse the link status */
2511         switch (link_status.link_speed) {
2512         case I40E_LINK_SPEED_100MB:
2513                 link->link_speed = ETH_SPEED_NUM_100M;
2514                 break;
2515         case I40E_LINK_SPEED_1GB:
2516                 link->link_speed = ETH_SPEED_NUM_1G;
2517                 break;
2518         case I40E_LINK_SPEED_10GB:
2519                 link->link_speed = ETH_SPEED_NUM_10G;
2520                 break;
2521         case I40E_LINK_SPEED_20GB:
2522                 link->link_speed = ETH_SPEED_NUM_20G;
2523                 break;
2524         case I40E_LINK_SPEED_25GB:
2525                 link->link_speed = ETH_SPEED_NUM_25G;
2526                 break;
2527         case I40E_LINK_SPEED_40GB:
2528                 link->link_speed = ETH_SPEED_NUM_40G;
2529                 break;
2530         default:
2531                 link->link_speed = ETH_SPEED_NUM_100M;
2532                 break;
2533         }
2534 }
2535
2536 int
2537 i40e_dev_link_update(struct rte_eth_dev *dev,
2538                      int wait_to_complete)
2539 {
2540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541         struct rte_eth_link link;
2542         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2543         int ret;
2544
2545         memset(&link, 0, sizeof(link));
2546
2547         /* i40e uses full duplex only */
2548         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2549         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2550                         ETH_LINK_SPEED_FIXED);
2551
2552         if (!wait_to_complete)
2553                 update_link_no_wait(hw, &link);
2554         else
2555                 update_link_wait(hw, &link, enable_lse);
2556
2557         ret = rte_eth_linkstatus_set(dev, &link);
2558         i40e_notify_all_vfs_link_status(dev);
2559
2560         return ret;
2561 }
2562
2563 /* Get all the statistics of a VSI */
2564 void
2565 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2566 {
2567         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2568         struct i40e_eth_stats *nes = &vsi->eth_stats;
2569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2570         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2571
2572         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2573                             vsi->offset_loaded, &oes->rx_bytes,
2574                             &nes->rx_bytes);
2575         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2576                             vsi->offset_loaded, &oes->rx_unicast,
2577                             &nes->rx_unicast);
2578         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2579                             vsi->offset_loaded, &oes->rx_multicast,
2580                             &nes->rx_multicast);
2581         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2582                             vsi->offset_loaded, &oes->rx_broadcast,
2583                             &nes->rx_broadcast);
2584         /* exclude CRC bytes */
2585         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2586                 nes->rx_broadcast) * ETHER_CRC_LEN;
2587
2588         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2589                             &oes->rx_discards, &nes->rx_discards);
2590         /* GLV_REPC not supported */
2591         /* GLV_RMPC not supported */
2592         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2593                             &oes->rx_unknown_protocol,
2594                             &nes->rx_unknown_protocol);
2595         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2596                             vsi->offset_loaded, &oes->tx_bytes,
2597                             &nes->tx_bytes);
2598         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2599                             vsi->offset_loaded, &oes->tx_unicast,
2600                             &nes->tx_unicast);
2601         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2602                             vsi->offset_loaded, &oes->tx_multicast,
2603                             &nes->tx_multicast);
2604         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2605                             vsi->offset_loaded,  &oes->tx_broadcast,
2606                             &nes->tx_broadcast);
2607         /* GLV_TDPC not supported */
2608         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2609                             &oes->tx_errors, &nes->tx_errors);
2610         vsi->offset_loaded = true;
2611
2612         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2613                     vsi->vsi_id);
2614         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2615         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2616         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2617         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2618         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2619         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2620                     nes->rx_unknown_protocol);
2621         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2622         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2623         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2624         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2625         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2626         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2627         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2628                     vsi->vsi_id);
2629 }
2630
2631 static void
2632 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2633 {
2634         unsigned int i;
2635         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2636         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2637
2638         /* Get rx/tx bytes of internal transfer packets */
2639         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2640                         I40E_GLV_GORCL(hw->port),
2641                         pf->offset_loaded,
2642                         &pf->internal_stats_offset.rx_bytes,
2643                         &pf->internal_stats.rx_bytes);
2644
2645         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2646                         I40E_GLV_GOTCL(hw->port),
2647                         pf->offset_loaded,
2648                         &pf->internal_stats_offset.tx_bytes,
2649                         &pf->internal_stats.tx_bytes);
2650         /* Get total internal rx packet count */
2651         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2652                             I40E_GLV_UPRCL(hw->port),
2653                             pf->offset_loaded,
2654                             &pf->internal_stats_offset.rx_unicast,
2655                             &pf->internal_stats.rx_unicast);
2656         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2657                             I40E_GLV_MPRCL(hw->port),
2658                             pf->offset_loaded,
2659                             &pf->internal_stats_offset.rx_multicast,
2660                             &pf->internal_stats.rx_multicast);
2661         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2662                             I40E_GLV_BPRCL(hw->port),
2663                             pf->offset_loaded,
2664                             &pf->internal_stats_offset.rx_broadcast,
2665                             &pf->internal_stats.rx_broadcast);
2666         /* Get total internal tx packet count */
2667         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2668                             I40E_GLV_UPTCL(hw->port),
2669                             pf->offset_loaded,
2670                             &pf->internal_stats_offset.tx_unicast,
2671                             &pf->internal_stats.tx_unicast);
2672         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2673                             I40E_GLV_MPTCL(hw->port),
2674                             pf->offset_loaded,
2675                             &pf->internal_stats_offset.tx_multicast,
2676                             &pf->internal_stats.tx_multicast);
2677         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2678                             I40E_GLV_BPTCL(hw->port),
2679                             pf->offset_loaded,
2680                             &pf->internal_stats_offset.tx_broadcast,
2681                             &pf->internal_stats.tx_broadcast);
2682
2683         /* exclude CRC size */
2684         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2685                 pf->internal_stats.rx_multicast +
2686                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2687
2688         /* Get statistics of struct i40e_eth_stats */
2689         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2690                             I40E_GLPRT_GORCL(hw->port),
2691                             pf->offset_loaded, &os->eth.rx_bytes,
2692                             &ns->eth.rx_bytes);
2693         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2694                             I40E_GLPRT_UPRCL(hw->port),
2695                             pf->offset_loaded, &os->eth.rx_unicast,
2696                             &ns->eth.rx_unicast);
2697         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2698                             I40E_GLPRT_MPRCL(hw->port),
2699                             pf->offset_loaded, &os->eth.rx_multicast,
2700                             &ns->eth.rx_multicast);
2701         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2702                             I40E_GLPRT_BPRCL(hw->port),
2703                             pf->offset_loaded, &os->eth.rx_broadcast,
2704                             &ns->eth.rx_broadcast);
2705         /* Workaround: CRC size should not be included in byte statistics,
2706          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2707          */
2708         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2709                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2710
2711         /* exclude internal rx bytes
2712          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2713          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2714          * value.
2715          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2716          */
2717         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2718                 ns->eth.rx_bytes = 0;
2719         else
2720                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2721
2722         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2723                 ns->eth.rx_unicast = 0;
2724         else
2725                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2726
2727         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2728                 ns->eth.rx_multicast = 0;
2729         else
2730                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2731
2732         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2733                 ns->eth.rx_broadcast = 0;
2734         else
2735                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2736
2737         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2738                             pf->offset_loaded, &os->eth.rx_discards,
2739                             &ns->eth.rx_discards);
2740         /* GLPRT_REPC not supported */
2741         /* GLPRT_RMPC not supported */
2742         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2743                             pf->offset_loaded,
2744                             &os->eth.rx_unknown_protocol,
2745                             &ns->eth.rx_unknown_protocol);
2746         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2747                             I40E_GLPRT_GOTCL(hw->port),
2748                             pf->offset_loaded, &os->eth.tx_bytes,
2749                             &ns->eth.tx_bytes);
2750         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2751                             I40E_GLPRT_UPTCL(hw->port),
2752                             pf->offset_loaded, &os->eth.tx_unicast,
2753                             &ns->eth.tx_unicast);
2754         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2755                             I40E_GLPRT_MPTCL(hw->port),
2756                             pf->offset_loaded, &os->eth.tx_multicast,
2757                             &ns->eth.tx_multicast);
2758         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2759                             I40E_GLPRT_BPTCL(hw->port),
2760                             pf->offset_loaded, &os->eth.tx_broadcast,
2761                             &ns->eth.tx_broadcast);
2762         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2763                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2764
2765         /* exclude internal tx bytes
2766          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2767          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2768          * value.
2769          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2770          */
2771         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2772                 ns->eth.tx_bytes = 0;
2773         else
2774                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2775
2776         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2777                 ns->eth.tx_unicast = 0;
2778         else
2779                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2780
2781         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2782                 ns->eth.tx_multicast = 0;
2783         else
2784                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2785
2786         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2787                 ns->eth.tx_broadcast = 0;
2788         else
2789                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2790
2791         /* GLPRT_TEPC not supported */
2792
2793         /* additional port specific stats */
2794         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2795                             pf->offset_loaded, &os->tx_dropped_link_down,
2796                             &ns->tx_dropped_link_down);
2797         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2798                             pf->offset_loaded, &os->crc_errors,
2799                             &ns->crc_errors);
2800         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2801                             pf->offset_loaded, &os->illegal_bytes,
2802                             &ns->illegal_bytes);
2803         /* GLPRT_ERRBC not supported */
2804         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2805                             pf->offset_loaded, &os->mac_local_faults,
2806                             &ns->mac_local_faults);
2807         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2808                             pf->offset_loaded, &os->mac_remote_faults,
2809                             &ns->mac_remote_faults);
2810         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2811                             pf->offset_loaded, &os->rx_length_errors,
2812                             &ns->rx_length_errors);
2813         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2814                             pf->offset_loaded, &os->link_xon_rx,
2815                             &ns->link_xon_rx);
2816         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2817                             pf->offset_loaded, &os->link_xoff_rx,
2818                             &ns->link_xoff_rx);
2819         for (i = 0; i < 8; i++) {
2820                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2821                                     pf->offset_loaded,
2822                                     &os->priority_xon_rx[i],
2823                                     &ns->priority_xon_rx[i]);
2824                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2825                                     pf->offset_loaded,
2826                                     &os->priority_xoff_rx[i],
2827                                     &ns->priority_xoff_rx[i]);
2828         }
2829         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2830                             pf->offset_loaded, &os->link_xon_tx,
2831                             &ns->link_xon_tx);
2832         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2833                             pf->offset_loaded, &os->link_xoff_tx,
2834                             &ns->link_xoff_tx);
2835         for (i = 0; i < 8; i++) {
2836                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2837                                     pf->offset_loaded,
2838                                     &os->priority_xon_tx[i],
2839                                     &ns->priority_xon_tx[i]);
2840                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2841                                     pf->offset_loaded,
2842                                     &os->priority_xoff_tx[i],
2843                                     &ns->priority_xoff_tx[i]);
2844                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2845                                     pf->offset_loaded,
2846                                     &os->priority_xon_2_xoff[i],
2847                                     &ns->priority_xon_2_xoff[i]);
2848         }
2849         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2850                             I40E_GLPRT_PRC64L(hw->port),
2851                             pf->offset_loaded, &os->rx_size_64,
2852                             &ns->rx_size_64);
2853         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2854                             I40E_GLPRT_PRC127L(hw->port),
2855                             pf->offset_loaded, &os->rx_size_127,
2856                             &ns->rx_size_127);
2857         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2858                             I40E_GLPRT_PRC255L(hw->port),
2859                             pf->offset_loaded, &os->rx_size_255,
2860                             &ns->rx_size_255);
2861         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2862                             I40E_GLPRT_PRC511L(hw->port),
2863                             pf->offset_loaded, &os->rx_size_511,
2864                             &ns->rx_size_511);
2865         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2866                             I40E_GLPRT_PRC1023L(hw->port),
2867                             pf->offset_loaded, &os->rx_size_1023,
2868                             &ns->rx_size_1023);
2869         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2870                             I40E_GLPRT_PRC1522L(hw->port),
2871                             pf->offset_loaded, &os->rx_size_1522,
2872                             &ns->rx_size_1522);
2873         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2874                             I40E_GLPRT_PRC9522L(hw->port),
2875                             pf->offset_loaded, &os->rx_size_big,
2876                             &ns->rx_size_big);
2877         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2878                             pf->offset_loaded, &os->rx_undersize,
2879                             &ns->rx_undersize);
2880         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2881                             pf->offset_loaded, &os->rx_fragments,
2882                             &ns->rx_fragments);
2883         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2884                             pf->offset_loaded, &os->rx_oversize,
2885                             &ns->rx_oversize);
2886         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2887                             pf->offset_loaded, &os->rx_jabber,
2888                             &ns->rx_jabber);
2889         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2890                             I40E_GLPRT_PTC64L(hw->port),
2891                             pf->offset_loaded, &os->tx_size_64,
2892                             &ns->tx_size_64);
2893         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2894                             I40E_GLPRT_PTC127L(hw->port),
2895                             pf->offset_loaded, &os->tx_size_127,
2896                             &ns->tx_size_127);
2897         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2898                             I40E_GLPRT_PTC255L(hw->port),
2899                             pf->offset_loaded, &os->tx_size_255,
2900                             &ns->tx_size_255);
2901         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2902                             I40E_GLPRT_PTC511L(hw->port),
2903                             pf->offset_loaded, &os->tx_size_511,
2904                             &ns->tx_size_511);
2905         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2906                             I40E_GLPRT_PTC1023L(hw->port),
2907                             pf->offset_loaded, &os->tx_size_1023,
2908                             &ns->tx_size_1023);
2909         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2910                             I40E_GLPRT_PTC1522L(hw->port),
2911                             pf->offset_loaded, &os->tx_size_1522,
2912                             &ns->tx_size_1522);
2913         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2914                             I40E_GLPRT_PTC9522L(hw->port),
2915                             pf->offset_loaded, &os->tx_size_big,
2916                             &ns->tx_size_big);
2917         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2918                            pf->offset_loaded,
2919                            &os->fd_sb_match, &ns->fd_sb_match);
2920         /* GLPRT_MSPDC not supported */
2921         /* GLPRT_XEC not supported */
2922
2923         pf->offset_loaded = true;
2924
2925         if (pf->main_vsi)
2926                 i40e_update_vsi_stats(pf->main_vsi);
2927 }
2928
2929 /* Get all statistics of a port */
2930 static int
2931 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2932 {
2933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2936         unsigned i;
2937
2938         /* call read registers - updates values, now write them to struct */
2939         i40e_read_stats_registers(pf, hw);
2940
2941         stats->ipackets = ns->eth.rx_unicast +
2942                         ns->eth.rx_multicast +
2943                         ns->eth.rx_broadcast -
2944                         ns->eth.rx_discards -
2945                         pf->main_vsi->eth_stats.rx_discards;
2946         stats->opackets = ns->eth.tx_unicast +
2947                         ns->eth.tx_multicast +
2948                         ns->eth.tx_broadcast;
2949         stats->ibytes   = ns->eth.rx_bytes;
2950         stats->obytes   = ns->eth.tx_bytes;
2951         stats->oerrors  = ns->eth.tx_errors +
2952                         pf->main_vsi->eth_stats.tx_errors;
2953
2954         /* Rx Errors */
2955         stats->imissed  = ns->eth.rx_discards +
2956                         pf->main_vsi->eth_stats.rx_discards;
2957         stats->ierrors  = ns->crc_errors +
2958                         ns->rx_length_errors + ns->rx_undersize +
2959                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2960
2961         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2962         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2963         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2964         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2965         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2966         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2967         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2968                     ns->eth.rx_unknown_protocol);
2969         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2970         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2971         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2972         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2973         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2974         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2975
2976         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2977                     ns->tx_dropped_link_down);
2978         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2979         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2980                     ns->illegal_bytes);
2981         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2982         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2983                     ns->mac_local_faults);
2984         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2985                     ns->mac_remote_faults);
2986         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2987                     ns->rx_length_errors);
2988         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2989         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2990         for (i = 0; i < 8; i++) {
2991                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2992                                 i, ns->priority_xon_rx[i]);
2993                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2994                                 i, ns->priority_xoff_rx[i]);
2995         }
2996         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2997         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2998         for (i = 0; i < 8; i++) {
2999                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3000                                 i, ns->priority_xon_tx[i]);
3001                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3002                                 i, ns->priority_xoff_tx[i]);
3003                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3004                                 i, ns->priority_xon_2_xoff[i]);
3005         }
3006         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3007         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3008         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3009         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3010         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3011         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3012         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3013         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3014         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3015         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3016         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3017         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3018         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3019         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3020         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3021         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3022         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3023         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3024         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3025                         ns->mac_short_packet_dropped);
3026         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3027                     ns->checksum_error);
3028         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3029         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3030         return 0;
3031 }
3032
3033 /* Reset the statistics */
3034 static void
3035 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3036 {
3037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3039
3040         /* Mark PF and VSI stats to update the offset, aka "reset" */
3041         pf->offset_loaded = false;
3042         if (pf->main_vsi)
3043                 pf->main_vsi->offset_loaded = false;
3044
3045         /* read the stats, reading current register values into offset */
3046         i40e_read_stats_registers(pf, hw);
3047 }
3048
3049 static uint32_t
3050 i40e_xstats_calc_num(void)
3051 {
3052         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3053                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3054                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3055 }
3056
3057 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3058                                      struct rte_eth_xstat_name *xstats_names,
3059                                      __rte_unused unsigned limit)
3060 {
3061         unsigned count = 0;
3062         unsigned i, prio;
3063
3064         if (xstats_names == NULL)
3065                 return i40e_xstats_calc_num();
3066
3067         /* Note: limit checked in rte_eth_xstats_names() */
3068
3069         /* Get stats from i40e_eth_stats struct */
3070         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3071                 snprintf(xstats_names[count].name,
3072                          sizeof(xstats_names[count].name),
3073                          "%s", rte_i40e_stats_strings[i].name);
3074                 count++;
3075         }
3076
3077         /* Get individiual stats from i40e_hw_port struct */
3078         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3079                 snprintf(xstats_names[count].name,
3080                         sizeof(xstats_names[count].name),
3081                          "%s", rte_i40e_hw_port_strings[i].name);
3082                 count++;
3083         }
3084
3085         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3086                 for (prio = 0; prio < 8; prio++) {
3087                         snprintf(xstats_names[count].name,
3088                                  sizeof(xstats_names[count].name),
3089                                  "rx_priority%u_%s", prio,
3090                                  rte_i40e_rxq_prio_strings[i].name);
3091                         count++;
3092                 }
3093         }
3094
3095         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3096                 for (prio = 0; prio < 8; prio++) {
3097                         snprintf(xstats_names[count].name,
3098                                  sizeof(xstats_names[count].name),
3099                                  "tx_priority%u_%s", prio,
3100                                  rte_i40e_txq_prio_strings[i].name);
3101                         count++;
3102                 }
3103         }
3104         return count;
3105 }
3106
3107 static int
3108 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3109                     unsigned n)
3110 {
3111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         unsigned i, count, prio;
3114         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3115
3116         count = i40e_xstats_calc_num();
3117         if (n < count)
3118                 return count;
3119
3120         i40e_read_stats_registers(pf, hw);
3121
3122         if (xstats == NULL)
3123                 return 0;
3124
3125         count = 0;
3126
3127         /* Get stats from i40e_eth_stats struct */
3128         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3129                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3130                         rte_i40e_stats_strings[i].offset);
3131                 xstats[count].id = count;
3132                 count++;
3133         }
3134
3135         /* Get individiual stats from i40e_hw_port struct */
3136         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3137                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3138                         rte_i40e_hw_port_strings[i].offset);
3139                 xstats[count].id = count;
3140                 count++;
3141         }
3142
3143         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3144                 for (prio = 0; prio < 8; prio++) {
3145                         xstats[count].value =
3146                                 *(uint64_t *)(((char *)hw_stats) +
3147                                 rte_i40e_rxq_prio_strings[i].offset +
3148                                 (sizeof(uint64_t) * prio));
3149                         xstats[count].id = count;
3150                         count++;
3151                 }
3152         }
3153
3154         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3155                 for (prio = 0; prio < 8; prio++) {
3156                         xstats[count].value =
3157                                 *(uint64_t *)(((char *)hw_stats) +
3158                                 rte_i40e_txq_prio_strings[i].offset +
3159                                 (sizeof(uint64_t) * prio));
3160                         xstats[count].id = count;
3161                         count++;
3162                 }
3163         }
3164
3165         return count;
3166 }
3167
3168 static int
3169 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3170                                  __rte_unused uint16_t queue_id,
3171                                  __rte_unused uint8_t stat_idx,
3172                                  __rte_unused uint8_t is_rx)
3173 {
3174         PMD_INIT_FUNC_TRACE();
3175
3176         return -ENOSYS;
3177 }
3178
3179 static int
3180 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3181 {
3182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         u32 full_ver;
3184         u8 ver, patch;
3185         u16 build;
3186         int ret;
3187
3188         full_ver = hw->nvm.oem_ver;
3189         ver = (u8)(full_ver >> 24);
3190         build = (u16)((full_ver >> 8) & 0xffff);
3191         patch = (u8)(full_ver & 0xff);
3192
3193         ret = snprintf(fw_version, fw_size,
3194                  "%d.%d%d 0x%08x %d.%d.%d",
3195                  ((hw->nvm.version >> 12) & 0xf),
3196                  ((hw->nvm.version >> 4) & 0xff),
3197                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3198                  ver, build, patch);
3199
3200         ret += 1; /* add the size of '\0' */
3201         if (fw_size < (u32)ret)
3202                 return ret;
3203         else
3204                 return 0;
3205 }
3206
3207 static void
3208 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3209 {
3210         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3212         struct i40e_vsi *vsi = pf->main_vsi;
3213         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3214
3215         dev_info->pci_dev = pci_dev;
3216         dev_info->max_rx_queues = vsi->nb_qps;
3217         dev_info->max_tx_queues = vsi->nb_qps;
3218         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3219         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3220         dev_info->max_mac_addrs = vsi->max_macaddrs;
3221         dev_info->max_vfs = pci_dev->max_vfs;
3222         dev_info->rx_offload_capa =
3223                 DEV_RX_OFFLOAD_VLAN_STRIP |
3224                 DEV_RX_OFFLOAD_QINQ_STRIP |
3225                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3226                 DEV_RX_OFFLOAD_UDP_CKSUM |
3227                 DEV_RX_OFFLOAD_TCP_CKSUM |
3228                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3229                 DEV_RX_OFFLOAD_CRC_STRIP;
3230         dev_info->tx_offload_capa =
3231                 DEV_TX_OFFLOAD_VLAN_INSERT |
3232                 DEV_TX_OFFLOAD_QINQ_INSERT |
3233                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3234                 DEV_TX_OFFLOAD_UDP_CKSUM |
3235                 DEV_TX_OFFLOAD_TCP_CKSUM |
3236                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3237                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3238                 DEV_TX_OFFLOAD_TCP_TSO |
3239                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3240                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3241                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3242                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3243         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3244                                                 sizeof(uint32_t);
3245         dev_info->reta_size = pf->hash_lut_size;
3246         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3247
3248         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3249                 .rx_thresh = {
3250                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3251                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3252                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3253                 },
3254                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3255                 .rx_drop_en = 0,
3256         };
3257
3258         dev_info->default_txconf = (struct rte_eth_txconf) {
3259                 .tx_thresh = {
3260                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3261                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3262                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3263                 },
3264                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3265                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3266                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3267                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3268         };
3269
3270         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3271                 .nb_max = I40E_MAX_RING_DESC,
3272                 .nb_min = I40E_MIN_RING_DESC,
3273                 .nb_align = I40E_ALIGN_RING_DESC,
3274         };
3275
3276         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3277                 .nb_max = I40E_MAX_RING_DESC,
3278                 .nb_min = I40E_MIN_RING_DESC,
3279                 .nb_align = I40E_ALIGN_RING_DESC,
3280                 .nb_seg_max = I40E_TX_MAX_SEG,
3281                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3282         };
3283
3284         if (pf->flags & I40E_FLAG_VMDQ) {
3285                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3286                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3287                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3288                                                 pf->max_nb_vmdq_vsi;
3289                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3290                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3291                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3292         }
3293
3294         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3295                 /* For XL710 */
3296                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3297         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3298                 /* For XXV710 */
3299                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3300         else
3301                 /* For X710 */
3302                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3303 }
3304
3305 static int
3306 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3307 {
3308         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3309         struct i40e_vsi *vsi = pf->main_vsi;
3310         PMD_INIT_FUNC_TRACE();
3311
3312         if (on)
3313                 return i40e_vsi_add_vlan(vsi, vlan_id);
3314         else
3315                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3316 }
3317
3318 static int
3319 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3320                                 enum rte_vlan_type vlan_type,
3321                                 uint16_t tpid, int qinq)
3322 {
3323         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324         uint64_t reg_r = 0;
3325         uint64_t reg_w = 0;
3326         uint16_t reg_id = 3;
3327         int ret;
3328
3329         if (qinq) {
3330                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3331                         reg_id = 2;
3332         }
3333
3334         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3335                                           &reg_r, NULL);
3336         if (ret != I40E_SUCCESS) {
3337                 PMD_DRV_LOG(ERR,
3338                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3339                            reg_id);
3340                 return -EIO;
3341         }
3342         PMD_DRV_LOG(DEBUG,
3343                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3344                     reg_id, reg_r);
3345
3346         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3347         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3348         if (reg_r == reg_w) {
3349                 PMD_DRV_LOG(DEBUG, "No need to write");
3350                 return 0;
3351         }
3352
3353         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3354                                            reg_w, NULL);
3355         if (ret != I40E_SUCCESS) {
3356                 PMD_DRV_LOG(ERR,
3357                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3358                             reg_id);
3359                 return -EIO;
3360         }
3361         PMD_DRV_LOG(DEBUG,
3362                     "Global register 0x%08x is changed with value 0x%08x",
3363                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3364
3365         return 0;
3366 }
3367
3368 static int
3369 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3370                    enum rte_vlan_type vlan_type,
3371                    uint16_t tpid)
3372 {
3373         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3375         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3376         int ret = 0;
3377
3378         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3379              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3380             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3381                 PMD_DRV_LOG(ERR,
3382                             "Unsupported vlan type.");
3383                 return -EINVAL;
3384         }
3385
3386         if (pf->support_multi_driver) {
3387                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3388                 return -ENOTSUP;
3389         }
3390
3391         /* 802.1ad frames ability is added in NVM API 1.7*/
3392         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3393                 if (qinq) {
3394                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3395                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3396                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3397                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3398                 } else {
3399                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3400                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3401                 }
3402                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3403                 if (ret != I40E_SUCCESS) {
3404                         PMD_DRV_LOG(ERR,
3405                                     "Set switch config failed aq_err: %d",
3406                                     hw->aq.asq_last_status);
3407                         ret = -EIO;
3408                 }
3409         } else
3410                 /* If NVM API < 1.7, keep the register setting */
3411                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3412                                                       tpid, qinq);
3413         i40e_global_cfg_warning(I40E_WARNING_TPID);
3414
3415         return ret;
3416 }
3417
3418 static int
3419 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3420 {
3421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3422         struct i40e_vsi *vsi = pf->main_vsi;
3423
3424         if (mask & ETH_VLAN_FILTER_MASK) {
3425                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3426                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3427                 else
3428                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3429         }
3430
3431         if (mask & ETH_VLAN_STRIP_MASK) {
3432                 /* Enable or disable VLAN stripping */
3433                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3434                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3435                 else
3436                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3437         }
3438
3439         if (mask & ETH_VLAN_EXTEND_MASK) {
3440                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3441                         i40e_vsi_config_double_vlan(vsi, TRUE);
3442                         /* Set global registers with default ethertype. */
3443                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3444                                            ETHER_TYPE_VLAN);
3445                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3446                                            ETHER_TYPE_VLAN);
3447                 }
3448                 else
3449                         i40e_vsi_config_double_vlan(vsi, FALSE);
3450         }
3451
3452         return 0;
3453 }
3454
3455 static void
3456 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3457                           __rte_unused uint16_t queue,
3458                           __rte_unused int on)
3459 {
3460         PMD_INIT_FUNC_TRACE();
3461 }
3462
3463 static int
3464 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3465 {
3466         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467         struct i40e_vsi *vsi = pf->main_vsi;
3468         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3469         struct i40e_vsi_vlan_pvid_info info;
3470
3471         memset(&info, 0, sizeof(info));
3472         info.on = on;
3473         if (info.on)
3474                 info.config.pvid = pvid;
3475         else {
3476                 info.config.reject.tagged =
3477                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3478                 info.config.reject.untagged =
3479                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3480         }
3481
3482         return i40e_vsi_vlan_pvid_set(vsi, &info);
3483 }
3484
3485 static int
3486 i40e_dev_led_on(struct rte_eth_dev *dev)
3487 {
3488         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489         uint32_t mode = i40e_led_get(hw);
3490
3491         if (mode == 0)
3492                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3493
3494         return 0;
3495 }
3496
3497 static int
3498 i40e_dev_led_off(struct rte_eth_dev *dev)
3499 {
3500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3501         uint32_t mode = i40e_led_get(hw);
3502
3503         if (mode != 0)
3504                 i40e_led_set(hw, 0, false);
3505
3506         return 0;
3507 }
3508
3509 static int
3510 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3511 {
3512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3514
3515         fc_conf->pause_time = pf->fc_conf.pause_time;
3516
3517         /* read out from register, in case they are modified by other port */
3518         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3519                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3520         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3521                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3522
3523         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3524         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3525
3526          /* Return current mode according to actual setting*/
3527         switch (hw->fc.current_mode) {
3528         case I40E_FC_FULL:
3529                 fc_conf->mode = RTE_FC_FULL;
3530                 break;
3531         case I40E_FC_TX_PAUSE:
3532                 fc_conf->mode = RTE_FC_TX_PAUSE;
3533                 break;
3534         case I40E_FC_RX_PAUSE:
3535                 fc_conf->mode = RTE_FC_RX_PAUSE;
3536                 break;
3537         case I40E_FC_NONE:
3538         default:
3539                 fc_conf->mode = RTE_FC_NONE;
3540         };
3541
3542         return 0;
3543 }
3544
3545 static int
3546 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3547 {
3548         uint32_t mflcn_reg, fctrl_reg, reg;
3549         uint32_t max_high_water;
3550         uint8_t i, aq_failure;
3551         int err;
3552         struct i40e_hw *hw;
3553         struct i40e_pf *pf;
3554         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3555                 [RTE_FC_NONE] = I40E_FC_NONE,
3556                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3557                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3558                 [RTE_FC_FULL] = I40E_FC_FULL
3559         };
3560
3561         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3562
3563         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3564         if ((fc_conf->high_water > max_high_water) ||
3565                         (fc_conf->high_water < fc_conf->low_water)) {
3566                 PMD_INIT_LOG(ERR,
3567                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3568                         max_high_water);
3569                 return -EINVAL;
3570         }
3571
3572         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3575
3576         pf->fc_conf.pause_time = fc_conf->pause_time;
3577         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3578         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3579
3580         PMD_INIT_FUNC_TRACE();
3581
3582         /* All the link flow control related enable/disable register
3583          * configuration is handle by the F/W
3584          */
3585         err = i40e_set_fc(hw, &aq_failure, true);
3586         if (err < 0)
3587                 return -ENOSYS;
3588
3589         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3590                 /* Configure flow control refresh threshold,
3591                  * the value for stat_tx_pause_refresh_timer[8]
3592                  * is used for global pause operation.
3593                  */
3594
3595                 I40E_WRITE_REG(hw,
3596                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3597                                pf->fc_conf.pause_time);
3598
3599                 /* configure the timer value included in transmitted pause
3600                  * frame,
3601                  * the value for stat_tx_pause_quanta[8] is used for global
3602                  * pause operation
3603                  */
3604                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3605                                pf->fc_conf.pause_time);
3606
3607                 fctrl_reg = I40E_READ_REG(hw,
3608                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3609
3610                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3611                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3612                 else
3613                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3614
3615                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3616                                fctrl_reg);
3617         } else {
3618                 /* Configure pause time (2 TCs per register) */
3619                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3620                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3621                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3622
3623                 /* Configure flow control refresh threshold value */
3624                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3625                                pf->fc_conf.pause_time / 2);
3626
3627                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3628
3629                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3630                  *depending on configuration
3631                  */
3632                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3633                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3634                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3635                 } else {
3636                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3637                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3638                 }
3639
3640                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3641         }
3642
3643         if (!pf->support_multi_driver) {
3644                 /* config water marker both based on the packets and bytes */
3645                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3646                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3647                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3648                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3649                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3650                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3651                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3652                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3653                                   << I40E_KILOSHIFT);
3654                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3655                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3656                                    << I40E_KILOSHIFT);
3657                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3658         } else {
3659                 PMD_DRV_LOG(ERR,
3660                             "Water marker configuration is not supported.");
3661         }
3662
3663         I40E_WRITE_FLUSH(hw);
3664
3665         return 0;
3666 }
3667
3668 static int
3669 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3670                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3671 {
3672         PMD_INIT_FUNC_TRACE();
3673
3674         return -ENOSYS;
3675 }
3676
3677 /* Add a MAC address, and update filters */
3678 static int
3679 i40e_macaddr_add(struct rte_eth_dev *dev,
3680                  struct ether_addr *mac_addr,
3681                  __rte_unused uint32_t index,
3682                  uint32_t pool)
3683 {
3684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3685         struct i40e_mac_filter_info mac_filter;
3686         struct i40e_vsi *vsi;
3687         int ret;
3688
3689         /* If VMDQ not enabled or configured, return */
3690         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3691                           !pf->nb_cfg_vmdq_vsi)) {
3692                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3693                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3694                         pool);
3695                 return -ENOTSUP;
3696         }
3697
3698         if (pool > pf->nb_cfg_vmdq_vsi) {
3699                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3700                                 pool, pf->nb_cfg_vmdq_vsi);
3701                 return -EINVAL;
3702         }
3703
3704         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3705         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3706                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3707         else
3708                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3709
3710         if (pool == 0)
3711                 vsi = pf->main_vsi;
3712         else
3713                 vsi = pf->vmdq[pool - 1].vsi;
3714
3715         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3716         if (ret != I40E_SUCCESS) {
3717                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3718                 return -ENODEV;
3719         }
3720         return 0;
3721 }
3722
3723 /* Remove a MAC address, and update filters */
3724 static void
3725 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3726 {
3727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3728         struct i40e_vsi *vsi;
3729         struct rte_eth_dev_data *data = dev->data;
3730         struct ether_addr *macaddr;
3731         int ret;
3732         uint32_t i;
3733         uint64_t pool_sel;
3734
3735         macaddr = &(data->mac_addrs[index]);
3736
3737         pool_sel = dev->data->mac_pool_sel[index];
3738
3739         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3740                 if (pool_sel & (1ULL << i)) {
3741                         if (i == 0)
3742                                 vsi = pf->main_vsi;
3743                         else {
3744                                 /* No VMDQ pool enabled or configured */
3745                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3746                                         (i > pf->nb_cfg_vmdq_vsi)) {
3747                                         PMD_DRV_LOG(ERR,
3748                                                 "No VMDQ pool enabled/configured");
3749                                         return;
3750                                 }
3751                                 vsi = pf->vmdq[i - 1].vsi;
3752                         }
3753                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3754
3755                         if (ret) {
3756                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3757                                 return;
3758                         }
3759                 }
3760         }
3761 }
3762
3763 /* Set perfect match or hash match of MAC and VLAN for a VF */
3764 static int
3765 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3766                  struct rte_eth_mac_filter *filter,
3767                  bool add)
3768 {
3769         struct i40e_hw *hw;
3770         struct i40e_mac_filter_info mac_filter;
3771         struct ether_addr old_mac;
3772         struct ether_addr *new_mac;
3773         struct i40e_pf_vf *vf = NULL;
3774         uint16_t vf_id;
3775         int ret;
3776
3777         if (pf == NULL) {
3778                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3779                 return -EINVAL;
3780         }
3781         hw = I40E_PF_TO_HW(pf);
3782
3783         if (filter == NULL) {
3784                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3785                 return -EINVAL;
3786         }
3787
3788         new_mac = &filter->mac_addr;
3789
3790         if (is_zero_ether_addr(new_mac)) {
3791                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3792                 return -EINVAL;
3793         }
3794
3795         vf_id = filter->dst_id;
3796
3797         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3798                 PMD_DRV_LOG(ERR, "Invalid argument.");
3799                 return -EINVAL;
3800         }
3801         vf = &pf->vfs[vf_id];
3802
3803         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3804                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3805                 return -EINVAL;
3806         }
3807
3808         if (add) {
3809                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3810                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3811                                 ETHER_ADDR_LEN);
3812                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3813                                  ETHER_ADDR_LEN);
3814
3815                 mac_filter.filter_type = filter->filter_type;
3816                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3817                 if (ret != I40E_SUCCESS) {
3818                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3819                         return -1;
3820                 }
3821                 ether_addr_copy(new_mac, &pf->dev_addr);
3822         } else {
3823                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3824                                 ETHER_ADDR_LEN);
3825                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3826                 if (ret != I40E_SUCCESS) {
3827                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3828                         return -1;
3829                 }
3830
3831                 /* Clear device address as it has been removed */
3832                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3833                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3834         }
3835
3836         return 0;
3837 }
3838
3839 /* MAC filter handle */
3840 static int
3841 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3842                 void *arg)
3843 {
3844         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3845         struct rte_eth_mac_filter *filter;
3846         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3847         int ret = I40E_NOT_SUPPORTED;
3848
3849         filter = (struct rte_eth_mac_filter *)(arg);
3850
3851         switch (filter_op) {
3852         case RTE_ETH_FILTER_NOP:
3853                 ret = I40E_SUCCESS;
3854                 break;
3855         case RTE_ETH_FILTER_ADD:
3856                 i40e_pf_disable_irq0(hw);
3857                 if (filter->is_vf)
3858                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3859                 i40e_pf_enable_irq0(hw);
3860                 break;
3861         case RTE_ETH_FILTER_DELETE:
3862                 i40e_pf_disable_irq0(hw);
3863                 if (filter->is_vf)
3864                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3865                 i40e_pf_enable_irq0(hw);
3866                 break;
3867         default:
3868                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3869                 ret = I40E_ERR_PARAM;
3870                 break;
3871         }
3872
3873         return ret;
3874 }
3875
3876 static int
3877 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3878 {
3879         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3880         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3881         uint32_t reg;
3882         int ret;
3883
3884         if (!lut)
3885                 return -EINVAL;
3886
3887         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3888                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3889                                           lut, lut_size);
3890                 if (ret) {
3891                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3892                         return ret;
3893                 }
3894         } else {
3895                 uint32_t *lut_dw = (uint32_t *)lut;
3896                 uint16_t i, lut_size_dw = lut_size / 4;
3897
3898                 if (vsi->type == I40E_VSI_SRIOV) {
3899                         for (i = 0; i <= lut_size_dw; i++) {
3900                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3901                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3902                         }
3903                 } else {
3904                         for (i = 0; i < lut_size_dw; i++)
3905                                 lut_dw[i] = I40E_READ_REG(hw,
3906                                                           I40E_PFQF_HLUT(i));
3907                 }
3908         }
3909
3910         return 0;
3911 }
3912
3913 int
3914 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3915 {
3916         struct i40e_pf *pf;
3917         struct i40e_hw *hw;
3918         int ret;
3919
3920         if (!vsi || !lut)
3921                 return -EINVAL;
3922
3923         pf = I40E_VSI_TO_PF(vsi);
3924         hw = I40E_VSI_TO_HW(vsi);
3925
3926         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3927                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3928                                           lut, lut_size);
3929                 if (ret) {
3930                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3931                         return ret;
3932                 }
3933         } else {
3934                 uint32_t *lut_dw = (uint32_t *)lut;
3935                 uint16_t i, lut_size_dw = lut_size / 4;
3936
3937                 if (vsi->type == I40E_VSI_SRIOV) {
3938                         for (i = 0; i < lut_size_dw; i++)
3939                                 I40E_WRITE_REG(
3940                                         hw,
3941                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3942                                         lut_dw[i]);
3943                 } else {
3944                         for (i = 0; i < lut_size_dw; i++)
3945                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3946                                                lut_dw[i]);
3947                 }
3948                 I40E_WRITE_FLUSH(hw);
3949         }
3950
3951         return 0;
3952 }
3953
3954 static int
3955 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3956                          struct rte_eth_rss_reta_entry64 *reta_conf,
3957                          uint16_t reta_size)
3958 {
3959         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3960         uint16_t i, lut_size = pf->hash_lut_size;
3961         uint16_t idx, shift;
3962         uint8_t *lut;
3963         int ret;
3964
3965         if (reta_size != lut_size ||
3966                 reta_size > ETH_RSS_RETA_SIZE_512) {
3967                 PMD_DRV_LOG(ERR,
3968                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3969                         reta_size, lut_size);
3970                 return -EINVAL;
3971         }
3972
3973         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3974         if (!lut) {
3975                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3976                 return -ENOMEM;
3977         }
3978         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3979         if (ret)
3980                 goto out;
3981         for (i = 0; i < reta_size; i++) {
3982                 idx = i / RTE_RETA_GROUP_SIZE;
3983                 shift = i % RTE_RETA_GROUP_SIZE;
3984                 if (reta_conf[idx].mask & (1ULL << shift))
3985                         lut[i] = reta_conf[idx].reta[shift];
3986         }
3987         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3988
3989 out:
3990         rte_free(lut);
3991
3992         return ret;
3993 }
3994
3995 static int
3996 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3997                         struct rte_eth_rss_reta_entry64 *reta_conf,
3998                         uint16_t reta_size)
3999 {
4000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4001         uint16_t i, lut_size = pf->hash_lut_size;
4002         uint16_t idx, shift;
4003         uint8_t *lut;
4004         int ret;
4005
4006         if (reta_size != lut_size ||
4007                 reta_size > ETH_RSS_RETA_SIZE_512) {
4008                 PMD_DRV_LOG(ERR,
4009                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4010                         reta_size, lut_size);
4011                 return -EINVAL;
4012         }
4013
4014         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4015         if (!lut) {
4016                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4017                 return -ENOMEM;
4018         }
4019
4020         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4021         if (ret)
4022                 goto out;
4023         for (i = 0; i < reta_size; i++) {
4024                 idx = i / RTE_RETA_GROUP_SIZE;
4025                 shift = i % RTE_RETA_GROUP_SIZE;
4026                 if (reta_conf[idx].mask & (1ULL << shift))
4027                         reta_conf[idx].reta[shift] = lut[i];
4028         }
4029
4030 out:
4031         rte_free(lut);
4032
4033         return ret;
4034 }
4035
4036 /**
4037  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4038  * @hw:   pointer to the HW structure
4039  * @mem:  pointer to mem struct to fill out
4040  * @size: size of memory requested
4041  * @alignment: what to align the allocation to
4042  **/
4043 enum i40e_status_code
4044 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4045                         struct i40e_dma_mem *mem,
4046                         u64 size,
4047                         u32 alignment)
4048 {
4049         const struct rte_memzone *mz = NULL;
4050         char z_name[RTE_MEMZONE_NAMESIZE];
4051
4052         if (!mem)
4053                 return I40E_ERR_PARAM;
4054
4055         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4056         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4057                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4058         if (!mz)
4059                 return I40E_ERR_NO_MEMORY;
4060
4061         mem->size = size;
4062         mem->va = mz->addr;
4063         mem->pa = mz->iova;
4064         mem->zone = (const void *)mz;
4065         PMD_DRV_LOG(DEBUG,
4066                 "memzone %s allocated with physical address: %"PRIu64,
4067                 mz->name, mem->pa);
4068
4069         return I40E_SUCCESS;
4070 }
4071
4072 /**
4073  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4074  * @hw:   pointer to the HW structure
4075  * @mem:  ptr to mem struct to free
4076  **/
4077 enum i40e_status_code
4078 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4079                     struct i40e_dma_mem *mem)
4080 {
4081         if (!mem)
4082                 return I40E_ERR_PARAM;
4083
4084         PMD_DRV_LOG(DEBUG,
4085                 "memzone %s to be freed with physical address: %"PRIu64,
4086                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4087         rte_memzone_free((const struct rte_memzone *)mem->zone);
4088         mem->zone = NULL;
4089         mem->va = NULL;
4090         mem->pa = (u64)0;
4091
4092         return I40E_SUCCESS;
4093 }
4094
4095 /**
4096  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4097  * @hw:   pointer to the HW structure
4098  * @mem:  pointer to mem struct to fill out
4099  * @size: size of memory requested
4100  **/
4101 enum i40e_status_code
4102 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4103                          struct i40e_virt_mem *mem,
4104                          u32 size)
4105 {
4106         if (!mem)
4107                 return I40E_ERR_PARAM;
4108
4109         mem->size = size;
4110         mem->va = rte_zmalloc("i40e", size, 0);
4111
4112         if (mem->va)
4113                 return I40E_SUCCESS;
4114         else
4115                 return I40E_ERR_NO_MEMORY;
4116 }
4117
4118 /**
4119  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4120  * @hw:   pointer to the HW structure
4121  * @mem:  pointer to mem struct to free
4122  **/
4123 enum i40e_status_code
4124 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4125                      struct i40e_virt_mem *mem)
4126 {
4127         if (!mem)
4128                 return I40E_ERR_PARAM;
4129
4130         rte_free(mem->va);
4131         mem->va = NULL;
4132
4133         return I40E_SUCCESS;
4134 }
4135
4136 void
4137 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4138 {
4139         rte_spinlock_init(&sp->spinlock);
4140 }
4141
4142 void
4143 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4144 {
4145         rte_spinlock_lock(&sp->spinlock);
4146 }
4147
4148 void
4149 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4150 {
4151         rte_spinlock_unlock(&sp->spinlock);
4152 }
4153
4154 void
4155 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4156 {
4157         return;
4158 }
4159
4160 /**
4161  * Get the hardware capabilities, which will be parsed
4162  * and saved into struct i40e_hw.
4163  */
4164 static int
4165 i40e_get_cap(struct i40e_hw *hw)
4166 {
4167         struct i40e_aqc_list_capabilities_element_resp *buf;
4168         uint16_t len, size = 0;
4169         int ret;
4170
4171         /* Calculate a huge enough buff for saving response data temporarily */
4172         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4173                                                 I40E_MAX_CAP_ELE_NUM;
4174         buf = rte_zmalloc("i40e", len, 0);
4175         if (!buf) {
4176                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4177                 return I40E_ERR_NO_MEMORY;
4178         }
4179
4180         /* Get, parse the capabilities and save it to hw */
4181         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4182                         i40e_aqc_opc_list_func_capabilities, NULL);
4183         if (ret != I40E_SUCCESS)
4184                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4185
4186         /* Free the temporary buffer after being used */
4187         rte_free(buf);
4188
4189         return ret;
4190 }
4191
4192 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4193 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4194
4195 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4196                 const char *value,
4197                 void *opaque)
4198 {
4199         struct i40e_pf *pf;
4200         unsigned long num;
4201         char *end;
4202
4203         pf = (struct i40e_pf *)opaque;
4204         RTE_SET_USED(key);
4205
4206         errno = 0;
4207         num = strtoul(value, &end, 0);
4208         if (errno != 0 || end == value || *end != 0) {
4209                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4210                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4211                 return -(EINVAL);
4212         }
4213
4214         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4215                 pf->vf_nb_qp_max = (uint16_t)num;
4216         else
4217                 /* here return 0 to make next valid same argument work */
4218                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4219                             "power of 2 and equal or less than 16 !, Now it is "
4220                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4221
4222         return 0;
4223 }
4224
4225 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4226 {
4227         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4228         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4229         struct rte_kvargs *kvlist;
4230
4231         /* set default queue number per VF as 4 */
4232         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4233
4234         if (dev->device->devargs == NULL)
4235                 return 0;
4236
4237         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4238         if (kvlist == NULL)
4239                 return -(EINVAL);
4240
4241         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4242                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4243                             "the first invalid or last valid one is used !",
4244                             QUEUE_NUM_PER_VF_ARG);
4245
4246         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4247                            i40e_pf_parse_vf_queue_number_handler, pf);
4248
4249         rte_kvargs_free(kvlist);
4250
4251         return 0;
4252 }
4253
4254 static int
4255 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4256 {
4257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4259         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4260         uint16_t qp_count = 0, vsi_count = 0;
4261
4262         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4263                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4264                 return -EINVAL;
4265         }
4266
4267         i40e_pf_config_vf_rxq_number(dev);
4268
4269         /* Add the parameter init for LFC */
4270         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4271         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4272         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4273
4274         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4275         pf->max_num_vsi = hw->func_caps.num_vsis;
4276         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4277         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4278
4279         /* FDir queue/VSI allocation */
4280         pf->fdir_qp_offset = 0;
4281         if (hw->func_caps.fd) {
4282                 pf->flags |= I40E_FLAG_FDIR;
4283                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4284         } else {
4285                 pf->fdir_nb_qps = 0;
4286         }
4287         qp_count += pf->fdir_nb_qps;
4288         vsi_count += 1;
4289
4290         /* LAN queue/VSI allocation */
4291         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4292         if (!hw->func_caps.rss) {
4293                 pf->lan_nb_qps = 1;
4294         } else {
4295                 pf->flags |= I40E_FLAG_RSS;
4296                 if (hw->mac.type == I40E_MAC_X722)
4297                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4298                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4299         }
4300         qp_count += pf->lan_nb_qps;
4301         vsi_count += 1;
4302
4303         /* VF queue/VSI allocation */
4304         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4305         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4306                 pf->flags |= I40E_FLAG_SRIOV;
4307                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4308                 pf->vf_num = pci_dev->max_vfs;
4309                 PMD_DRV_LOG(DEBUG,
4310                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4311                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4312         } else {
4313                 pf->vf_nb_qps = 0;
4314                 pf->vf_num = 0;
4315         }
4316         qp_count += pf->vf_nb_qps * pf->vf_num;
4317         vsi_count += pf->vf_num;
4318
4319         /* VMDq queue/VSI allocation */
4320         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4321         pf->vmdq_nb_qps = 0;
4322         pf->max_nb_vmdq_vsi = 0;
4323         if (hw->func_caps.vmdq) {
4324                 if (qp_count < hw->func_caps.num_tx_qp &&
4325                         vsi_count < hw->func_caps.num_vsis) {
4326                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4327                                 qp_count) / pf->vmdq_nb_qp_max;
4328
4329                         /* Limit the maximum number of VMDq vsi to the maximum
4330                          * ethdev can support
4331                          */
4332                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4333                                 hw->func_caps.num_vsis - vsi_count);
4334                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4335                                 ETH_64_POOLS);
4336                         if (pf->max_nb_vmdq_vsi) {
4337                                 pf->flags |= I40E_FLAG_VMDQ;
4338                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4339                                 PMD_DRV_LOG(DEBUG,
4340                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4341                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4342                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4343                         } else {
4344                                 PMD_DRV_LOG(INFO,
4345                                         "No enough queues left for VMDq");
4346                         }
4347                 } else {
4348                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4349                 }
4350         }
4351         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4352         vsi_count += pf->max_nb_vmdq_vsi;
4353
4354         if (hw->func_caps.dcb)
4355                 pf->flags |= I40E_FLAG_DCB;
4356
4357         if (qp_count > hw->func_caps.num_tx_qp) {
4358                 PMD_DRV_LOG(ERR,
4359                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4360                         qp_count, hw->func_caps.num_tx_qp);
4361                 return -EINVAL;
4362         }
4363         if (vsi_count > hw->func_caps.num_vsis) {
4364                 PMD_DRV_LOG(ERR,
4365                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4366                         vsi_count, hw->func_caps.num_vsis);
4367                 return -EINVAL;
4368         }
4369
4370         return 0;
4371 }
4372
4373 static int
4374 i40e_pf_get_switch_config(struct i40e_pf *pf)
4375 {
4376         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4377         struct i40e_aqc_get_switch_config_resp *switch_config;
4378         struct i40e_aqc_switch_config_element_resp *element;
4379         uint16_t start_seid = 0, num_reported;
4380         int ret;
4381
4382         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4383                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4384         if (!switch_config) {
4385                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4386                 return -ENOMEM;
4387         }
4388
4389         /* Get the switch configurations */
4390         ret = i40e_aq_get_switch_config(hw, switch_config,
4391                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4392         if (ret != I40E_SUCCESS) {
4393                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4394                 goto fail;
4395         }
4396         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4397         if (num_reported != 1) { /* The number should be 1 */
4398                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4399                 goto fail;
4400         }
4401
4402         /* Parse the switch configuration elements */
4403         element = &(switch_config->element[0]);
4404         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4405                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4406                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4407         } else
4408                 PMD_DRV_LOG(INFO, "Unknown element type");
4409
4410 fail:
4411         rte_free(switch_config);
4412
4413         return ret;
4414 }
4415
4416 static int
4417 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4418                         uint32_t num)
4419 {
4420         struct pool_entry *entry;
4421
4422         if (pool == NULL || num == 0)
4423                 return -EINVAL;
4424
4425         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4426         if (entry == NULL) {
4427                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4428                 return -ENOMEM;
4429         }
4430
4431         /* queue heap initialize */
4432         pool->num_free = num;
4433         pool->num_alloc = 0;
4434         pool->base = base;
4435         LIST_INIT(&pool->alloc_list);
4436         LIST_INIT(&pool->free_list);
4437
4438         /* Initialize element  */
4439         entry->base = 0;
4440         entry->len = num;
4441
4442         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4443         return 0;
4444 }
4445
4446 static void
4447 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4448 {
4449         struct pool_entry *entry, *next_entry;
4450
4451         if (pool == NULL)
4452                 return;
4453
4454         for (entry = LIST_FIRST(&pool->alloc_list);
4455                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4456                         entry = next_entry) {
4457                 LIST_REMOVE(entry, next);
4458                 rte_free(entry);
4459         }
4460
4461         for (entry = LIST_FIRST(&pool->free_list);
4462                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4463                         entry = next_entry) {
4464                 LIST_REMOVE(entry, next);
4465                 rte_free(entry);
4466         }
4467
4468         pool->num_free = 0;
4469         pool->num_alloc = 0;
4470         pool->base = 0;
4471         LIST_INIT(&pool->alloc_list);
4472         LIST_INIT(&pool->free_list);
4473 }
4474
4475 static int
4476 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4477                        uint32_t base)
4478 {
4479         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4480         uint32_t pool_offset;
4481         int insert;
4482
4483         if (pool == NULL) {
4484                 PMD_DRV_LOG(ERR, "Invalid parameter");
4485                 return -EINVAL;
4486         }
4487
4488         pool_offset = base - pool->base;
4489         /* Lookup in alloc list */
4490         LIST_FOREACH(entry, &pool->alloc_list, next) {
4491                 if (entry->base == pool_offset) {
4492                         valid_entry = entry;
4493                         LIST_REMOVE(entry, next);
4494                         break;
4495                 }
4496         }
4497
4498         /* Not find, return */
4499         if (valid_entry == NULL) {
4500                 PMD_DRV_LOG(ERR, "Failed to find entry");
4501                 return -EINVAL;
4502         }
4503
4504         /**
4505          * Found it, move it to free list  and try to merge.
4506          * In order to make merge easier, always sort it by qbase.
4507          * Find adjacent prev and last entries.
4508          */
4509         prev = next = NULL;
4510         LIST_FOREACH(entry, &pool->free_list, next) {
4511                 if (entry->base > valid_entry->base) {
4512                         next = entry;
4513                         break;
4514                 }
4515                 prev = entry;
4516         }
4517
4518         insert = 0;
4519         /* Try to merge with next one*/
4520         if (next != NULL) {
4521                 /* Merge with next one */
4522                 if (valid_entry->base + valid_entry->len == next->base) {
4523                         next->base = valid_entry->base;
4524                         next->len += valid_entry->len;
4525                         rte_free(valid_entry);
4526                         valid_entry = next;
4527                         insert = 1;
4528                 }
4529         }
4530
4531         if (prev != NULL) {
4532                 /* Merge with previous one */
4533                 if (prev->base + prev->len == valid_entry->base) {
4534                         prev->len += valid_entry->len;
4535                         /* If it merge with next one, remove next node */
4536                         if (insert == 1) {
4537                                 LIST_REMOVE(valid_entry, next);
4538                                 rte_free(valid_entry);
4539                         } else {
4540                                 rte_free(valid_entry);
4541                                 insert = 1;
4542                         }
4543                 }
4544         }
4545
4546         /* Not find any entry to merge, insert */
4547         if (insert == 0) {
4548                 if (prev != NULL)
4549                         LIST_INSERT_AFTER(prev, valid_entry, next);
4550                 else if (next != NULL)
4551                         LIST_INSERT_BEFORE(next, valid_entry, next);
4552                 else /* It's empty list, insert to head */
4553                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4554         }
4555
4556         pool->num_free += valid_entry->len;
4557         pool->num_alloc -= valid_entry->len;
4558
4559         return 0;
4560 }
4561
4562 static int
4563 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4564                        uint16_t num)
4565 {
4566         struct pool_entry *entry, *valid_entry;
4567
4568         if (pool == NULL || num == 0) {
4569                 PMD_DRV_LOG(ERR, "Invalid parameter");
4570                 return -EINVAL;
4571         }
4572
4573         if (pool->num_free < num) {
4574                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4575                             num, pool->num_free);
4576                 return -ENOMEM;
4577         }
4578
4579         valid_entry = NULL;
4580         /* Lookup  in free list and find most fit one */
4581         LIST_FOREACH(entry, &pool->free_list, next) {
4582                 if (entry->len >= num) {
4583                         /* Find best one */
4584                         if (entry->len == num) {
4585                                 valid_entry = entry;
4586                                 break;
4587                         }
4588                         if (valid_entry == NULL || valid_entry->len > entry->len)
4589                                 valid_entry = entry;
4590                 }
4591         }
4592
4593         /* Not find one to satisfy the request, return */
4594         if (valid_entry == NULL) {
4595                 PMD_DRV_LOG(ERR, "No valid entry found");
4596                 return -ENOMEM;
4597         }
4598         /**
4599          * The entry have equal queue number as requested,
4600          * remove it from alloc_list.
4601          */
4602         if (valid_entry->len == num) {
4603                 LIST_REMOVE(valid_entry, next);
4604         } else {
4605                 /**
4606                  * The entry have more numbers than requested,
4607                  * create a new entry for alloc_list and minus its
4608                  * queue base and number in free_list.
4609                  */
4610                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4611                 if (entry == NULL) {
4612                         PMD_DRV_LOG(ERR,
4613                                 "Failed to allocate memory for resource pool");
4614                         return -ENOMEM;
4615                 }
4616                 entry->base = valid_entry->base;
4617                 entry->len = num;
4618                 valid_entry->base += num;
4619                 valid_entry->len -= num;
4620                 valid_entry = entry;
4621         }
4622
4623         /* Insert it into alloc list, not sorted */
4624         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4625
4626         pool->num_free -= valid_entry->len;
4627         pool->num_alloc += valid_entry->len;
4628
4629         return valid_entry->base + pool->base;
4630 }
4631
4632 /**
4633  * bitmap_is_subset - Check whether src2 is subset of src1
4634  **/
4635 static inline int
4636 bitmap_is_subset(uint8_t src1, uint8_t src2)
4637 {
4638         return !((src1 ^ src2) & src2);
4639 }
4640
4641 static enum i40e_status_code
4642 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4643 {
4644         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4645
4646         /* If DCB is not supported, only default TC is supported */
4647         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4648                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4649                 return I40E_NOT_SUPPORTED;
4650         }
4651
4652         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4653                 PMD_DRV_LOG(ERR,
4654                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4655                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4656                 return I40E_NOT_SUPPORTED;
4657         }
4658         return I40E_SUCCESS;
4659 }
4660
4661 int
4662 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4663                                 struct i40e_vsi_vlan_pvid_info *info)
4664 {
4665         struct i40e_hw *hw;
4666         struct i40e_vsi_context ctxt;
4667         uint8_t vlan_flags = 0;
4668         int ret;
4669
4670         if (vsi == NULL || info == NULL) {
4671                 PMD_DRV_LOG(ERR, "invalid parameters");
4672                 return I40E_ERR_PARAM;
4673         }
4674
4675         if (info->on) {
4676                 vsi->info.pvid = info->config.pvid;
4677                 /**
4678                  * If insert pvid is enabled, only tagged pkts are
4679                  * allowed to be sent out.
4680                  */
4681                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4682                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4683         } else {
4684                 vsi->info.pvid = 0;
4685                 if (info->config.reject.tagged == 0)
4686                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4687
4688                 if (info->config.reject.untagged == 0)
4689                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4690         }
4691         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4692                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4693         vsi->info.port_vlan_flags |= vlan_flags;
4694         vsi->info.valid_sections =
4695                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4696         memset(&ctxt, 0, sizeof(ctxt));
4697         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4698         ctxt.seid = vsi->seid;
4699
4700         hw = I40E_VSI_TO_HW(vsi);
4701         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4702         if (ret != I40E_SUCCESS)
4703                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4704
4705         return ret;
4706 }
4707
4708 static int
4709 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4710 {
4711         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4712         int i, ret;
4713         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4714
4715         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4716         if (ret != I40E_SUCCESS)
4717                 return ret;
4718
4719         if (!vsi->seid) {
4720                 PMD_DRV_LOG(ERR, "seid not valid");
4721                 return -EINVAL;
4722         }
4723
4724         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4725         tc_bw_data.tc_valid_bits = enabled_tcmap;
4726         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4727                 tc_bw_data.tc_bw_credits[i] =
4728                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4729
4730         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4731         if (ret != I40E_SUCCESS) {
4732                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4733                 return ret;
4734         }
4735
4736         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4737                                         sizeof(vsi->info.qs_handle));
4738         return I40E_SUCCESS;
4739 }
4740
4741 static enum i40e_status_code
4742 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4743                                  struct i40e_aqc_vsi_properties_data *info,
4744                                  uint8_t enabled_tcmap)
4745 {
4746         enum i40e_status_code ret;
4747         int i, total_tc = 0;
4748         uint16_t qpnum_per_tc, bsf, qp_idx;
4749
4750         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4751         if (ret != I40E_SUCCESS)
4752                 return ret;
4753
4754         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4755                 if (enabled_tcmap & (1 << i))
4756                         total_tc++;
4757         if (total_tc == 0)
4758                 total_tc = 1;
4759         vsi->enabled_tc = enabled_tcmap;
4760
4761         /* Number of queues per enabled TC */
4762         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4763         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4764         bsf = rte_bsf32(qpnum_per_tc);
4765
4766         /* Adjust the queue number to actual queues that can be applied */
4767         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4768                 vsi->nb_qps = qpnum_per_tc * total_tc;
4769
4770         /**
4771          * Configure TC and queue mapping parameters, for enabled TC,
4772          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4773          * default queue will serve it.
4774          */
4775         qp_idx = 0;
4776         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4777                 if (vsi->enabled_tc & (1 << i)) {
4778                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4779                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4780                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4781                         qp_idx += qpnum_per_tc;
4782                 } else
4783                         info->tc_mapping[i] = 0;
4784         }
4785
4786         /* Associate queue number with VSI */
4787         if (vsi->type == I40E_VSI_SRIOV) {
4788                 info->mapping_flags |=
4789                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4790                 for (i = 0; i < vsi->nb_qps; i++)
4791                         info->queue_mapping[i] =
4792                                 rte_cpu_to_le_16(vsi->base_queue + i);
4793         } else {
4794                 info->mapping_flags |=
4795                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4796                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4797         }
4798         info->valid_sections |=
4799                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4800
4801         return I40E_SUCCESS;
4802 }
4803
4804 static int
4805 i40e_veb_release(struct i40e_veb *veb)
4806 {
4807         struct i40e_vsi *vsi;
4808         struct i40e_hw *hw;
4809
4810         if (veb == NULL)
4811                 return -EINVAL;
4812
4813         if (!TAILQ_EMPTY(&veb->head)) {
4814                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4815                 return -EACCES;
4816         }
4817         /* associate_vsi field is NULL for floating VEB */
4818         if (veb->associate_vsi != NULL) {
4819                 vsi = veb->associate_vsi;
4820                 hw = I40E_VSI_TO_HW(vsi);
4821
4822                 vsi->uplink_seid = veb->uplink_seid;
4823                 vsi->veb = NULL;
4824         } else {
4825                 veb->associate_pf->main_vsi->floating_veb = NULL;
4826                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4827         }
4828
4829         i40e_aq_delete_element(hw, veb->seid, NULL);
4830         rte_free(veb);
4831         return I40E_SUCCESS;
4832 }
4833
4834 /* Setup a veb */
4835 static struct i40e_veb *
4836 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4837 {
4838         struct i40e_veb *veb;
4839         int ret;
4840         struct i40e_hw *hw;
4841
4842         if (pf == NULL) {
4843                 PMD_DRV_LOG(ERR,
4844                             "veb setup failed, associated PF shouldn't null");
4845                 return NULL;
4846         }
4847         hw = I40E_PF_TO_HW(pf);
4848
4849         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4850         if (!veb) {
4851                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4852                 goto fail;
4853         }
4854
4855         veb->associate_vsi = vsi;
4856         veb->associate_pf = pf;
4857         TAILQ_INIT(&veb->head);
4858         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4859
4860         /* create floating veb if vsi is NULL */
4861         if (vsi != NULL) {
4862                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4863                                       I40E_DEFAULT_TCMAP, false,
4864                                       &veb->seid, false, NULL);
4865         } else {
4866                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4867                                       true, &veb->seid, false, NULL);
4868         }
4869
4870         if (ret != I40E_SUCCESS) {
4871                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4872                             hw->aq.asq_last_status);
4873                 goto fail;
4874         }
4875         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4876
4877         /* get statistics index */
4878         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4879                                 &veb->stats_idx, NULL, NULL, NULL);
4880         if (ret != I40E_SUCCESS) {
4881                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4882                             hw->aq.asq_last_status);
4883                 goto fail;
4884         }
4885         /* Get VEB bandwidth, to be implemented */
4886         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4887         if (vsi)
4888                 vsi->uplink_seid = veb->seid;
4889
4890         return veb;
4891 fail:
4892         rte_free(veb);
4893         return NULL;
4894 }
4895
4896 int
4897 i40e_vsi_release(struct i40e_vsi *vsi)
4898 {
4899         struct i40e_pf *pf;
4900         struct i40e_hw *hw;
4901         struct i40e_vsi_list *vsi_list;
4902         void *temp;
4903         int ret;
4904         struct i40e_mac_filter *f;
4905         uint16_t user_param;
4906
4907         if (!vsi)
4908                 return I40E_SUCCESS;
4909
4910         if (!vsi->adapter)
4911                 return -EFAULT;
4912
4913         user_param = vsi->user_param;
4914
4915         pf = I40E_VSI_TO_PF(vsi);
4916         hw = I40E_VSI_TO_HW(vsi);
4917
4918         /* VSI has child to attach, release child first */
4919         if (vsi->veb) {
4920                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4921                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4922                                 return -1;
4923                 }
4924                 i40e_veb_release(vsi->veb);
4925         }
4926
4927         if (vsi->floating_veb) {
4928                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4929                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4930                                 return -1;
4931                 }
4932         }
4933
4934         /* Remove all macvlan filters of the VSI */
4935         i40e_vsi_remove_all_macvlan_filter(vsi);
4936         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4937                 rte_free(f);
4938
4939         if (vsi->type != I40E_VSI_MAIN &&
4940             ((vsi->type != I40E_VSI_SRIOV) ||
4941             !pf->floating_veb_list[user_param])) {
4942                 /* Remove vsi from parent's sibling list */
4943                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4944                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4945                         return I40E_ERR_PARAM;
4946                 }
4947                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4948                                 &vsi->sib_vsi_list, list);
4949
4950                 /* Remove all switch element of the VSI */
4951                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4952                 if (ret != I40E_SUCCESS)
4953                         PMD_DRV_LOG(ERR, "Failed to delete element");
4954         }
4955
4956         if ((vsi->type == I40E_VSI_SRIOV) &&
4957             pf->floating_veb_list[user_param]) {
4958                 /* Remove vsi from parent's sibling list */
4959                 if (vsi->parent_vsi == NULL ||
4960                     vsi->parent_vsi->floating_veb == NULL) {
4961                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4962                         return I40E_ERR_PARAM;
4963                 }
4964                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4965                              &vsi->sib_vsi_list, list);
4966
4967                 /* Remove all switch element of the VSI */
4968                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4969                 if (ret != I40E_SUCCESS)
4970                         PMD_DRV_LOG(ERR, "Failed to delete element");
4971         }
4972
4973         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4974
4975         if (vsi->type != I40E_VSI_SRIOV)
4976                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4977         rte_free(vsi);
4978
4979         return I40E_SUCCESS;
4980 }
4981
4982 static int
4983 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4984 {
4985         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4986         struct i40e_aqc_remove_macvlan_element_data def_filter;
4987         struct i40e_mac_filter_info filter;
4988         int ret;
4989
4990         if (vsi->type != I40E_VSI_MAIN)
4991                 return I40E_ERR_CONFIG;
4992         memset(&def_filter, 0, sizeof(def_filter));
4993         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4994                                         ETH_ADDR_LEN);
4995         def_filter.vlan_tag = 0;
4996         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4997                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4998         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4999         if (ret != I40E_SUCCESS) {
5000                 struct i40e_mac_filter *f;
5001                 struct ether_addr *mac;
5002
5003                 PMD_DRV_LOG(DEBUG,
5004                             "Cannot remove the default macvlan filter");
5005                 /* It needs to add the permanent mac into mac list */
5006                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5007                 if (f == NULL) {
5008                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5009                         return I40E_ERR_NO_MEMORY;
5010                 }
5011                 mac = &f->mac_info.mac_addr;
5012                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5013                                 ETH_ADDR_LEN);
5014                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5015                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5016                 vsi->mac_num++;
5017
5018                 return ret;
5019         }
5020         rte_memcpy(&filter.mac_addr,
5021                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5022         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5023         return i40e_vsi_add_mac(vsi, &filter);
5024 }
5025
5026 /*
5027  * i40e_vsi_get_bw_config - Query VSI BW Information
5028  * @vsi: the VSI to be queried
5029  *
5030  * Returns 0 on success, negative value on failure
5031  */
5032 static enum i40e_status_code
5033 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5034 {
5035         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5036         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5037         struct i40e_hw *hw = &vsi->adapter->hw;
5038         i40e_status ret;
5039         int i;
5040         uint32_t bw_max;
5041
5042         memset(&bw_config, 0, sizeof(bw_config));
5043         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5044         if (ret != I40E_SUCCESS) {
5045                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5046                             hw->aq.asq_last_status);
5047                 return ret;
5048         }
5049
5050         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5051         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5052                                         &ets_sla_config, NULL);
5053         if (ret != I40E_SUCCESS) {
5054                 PMD_DRV_LOG(ERR,
5055                         "VSI failed to get TC bandwdith configuration %u",
5056                         hw->aq.asq_last_status);
5057                 return ret;
5058         }
5059
5060         /* store and print out BW info */
5061         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5062         vsi->bw_info.bw_max = bw_config.max_bw;
5063         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5064         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5065         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5066                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5067                      I40E_16_BIT_WIDTH);
5068         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5069                 vsi->bw_info.bw_ets_share_credits[i] =
5070                                 ets_sla_config.share_credits[i];
5071                 vsi->bw_info.bw_ets_credits[i] =
5072                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5073                 /* 4 bits per TC, 4th bit is reserved */
5074                 vsi->bw_info.bw_ets_max[i] =
5075                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5076                                   RTE_LEN2MASK(3, uint8_t));
5077                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5078                             vsi->bw_info.bw_ets_share_credits[i]);
5079                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5080                             vsi->bw_info.bw_ets_credits[i]);
5081                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5082                             vsi->bw_info.bw_ets_max[i]);
5083         }
5084
5085         return I40E_SUCCESS;
5086 }
5087
5088 /* i40e_enable_pf_lb
5089  * @pf: pointer to the pf structure
5090  *
5091  * allow loopback on pf
5092  */
5093 static inline void
5094 i40e_enable_pf_lb(struct i40e_pf *pf)
5095 {
5096         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5097         struct i40e_vsi_context ctxt;
5098         int ret;
5099
5100         /* Use the FW API if FW >= v5.0 */
5101         if (hw->aq.fw_maj_ver < 5) {
5102                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5103                 return;
5104         }
5105
5106         memset(&ctxt, 0, sizeof(ctxt));
5107         ctxt.seid = pf->main_vsi_seid;
5108         ctxt.pf_num = hw->pf_id;
5109         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5110         if (ret) {
5111                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5112                             ret, hw->aq.asq_last_status);
5113                 return;
5114         }
5115         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5116         ctxt.info.valid_sections =
5117                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5118         ctxt.info.switch_id |=
5119                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5120
5121         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5122         if (ret)
5123                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5124                             hw->aq.asq_last_status);
5125 }
5126
5127 /* Setup a VSI */
5128 struct i40e_vsi *
5129 i40e_vsi_setup(struct i40e_pf *pf,
5130                enum i40e_vsi_type type,
5131                struct i40e_vsi *uplink_vsi,
5132                uint16_t user_param)
5133 {
5134         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5135         struct i40e_vsi *vsi;
5136         struct i40e_mac_filter_info filter;
5137         int ret;
5138         struct i40e_vsi_context ctxt;
5139         struct ether_addr broadcast =
5140                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5141
5142         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5143             uplink_vsi == NULL) {
5144                 PMD_DRV_LOG(ERR,
5145                         "VSI setup failed, VSI link shouldn't be NULL");
5146                 return NULL;
5147         }
5148
5149         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5150                 PMD_DRV_LOG(ERR,
5151                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5152                 return NULL;
5153         }
5154
5155         /* two situations
5156          * 1.type is not MAIN and uplink vsi is not NULL
5157          * If uplink vsi didn't setup VEB, create one first under veb field
5158          * 2.type is SRIOV and the uplink is NULL
5159          * If floating VEB is NULL, create one veb under floating veb field
5160          */
5161
5162         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5163             uplink_vsi->veb == NULL) {
5164                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5165
5166                 if (uplink_vsi->veb == NULL) {
5167                         PMD_DRV_LOG(ERR, "VEB setup failed");
5168                         return NULL;
5169                 }
5170                 /* set ALLOWLOOPBACk on pf, when veb is created */
5171                 i40e_enable_pf_lb(pf);
5172         }
5173
5174         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5175             pf->main_vsi->floating_veb == NULL) {
5176                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5177
5178                 if (pf->main_vsi->floating_veb == NULL) {
5179                         PMD_DRV_LOG(ERR, "VEB setup failed");
5180                         return NULL;
5181                 }
5182         }
5183
5184         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5185         if (!vsi) {
5186                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5187                 return NULL;
5188         }
5189         TAILQ_INIT(&vsi->mac_list);
5190         vsi->type = type;
5191         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5192         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5193         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5194         vsi->user_param = user_param;
5195         vsi->vlan_anti_spoof_on = 0;
5196         vsi->vlan_filter_on = 0;
5197         /* Allocate queues */
5198         switch (vsi->type) {
5199         case I40E_VSI_MAIN  :
5200                 vsi->nb_qps = pf->lan_nb_qps;
5201                 break;
5202         case I40E_VSI_SRIOV :
5203                 vsi->nb_qps = pf->vf_nb_qps;
5204                 break;
5205         case I40E_VSI_VMDQ2:
5206                 vsi->nb_qps = pf->vmdq_nb_qps;
5207                 break;
5208         case I40E_VSI_FDIR:
5209                 vsi->nb_qps = pf->fdir_nb_qps;
5210                 break;
5211         default:
5212                 goto fail_mem;
5213         }
5214         /*
5215          * The filter status descriptor is reported in rx queue 0,
5216          * while the tx queue for fdir filter programming has no
5217          * such constraints, can be non-zero queues.
5218          * To simplify it, choose FDIR vsi use queue 0 pair.
5219          * To make sure it will use queue 0 pair, queue allocation
5220          * need be done before this function is called
5221          */
5222         if (type != I40E_VSI_FDIR) {
5223                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5224                         if (ret < 0) {
5225                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5226                                                 vsi->seid, ret);
5227                                 goto fail_mem;
5228                         }
5229                         vsi->base_queue = ret;
5230         } else
5231                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5232
5233         /* VF has MSIX interrupt in VF range, don't allocate here */
5234         if (type == I40E_VSI_MAIN) {
5235                 if (pf->support_multi_driver) {
5236                         /* If support multi-driver, need to use INT0 instead of
5237                          * allocating from msix pool. The Msix pool is init from
5238                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5239                          * to 1 without calling i40e_res_pool_alloc.
5240                          */
5241                         vsi->msix_intr = 0;
5242                         vsi->nb_msix = 1;
5243                 } else {
5244                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5245                                                   RTE_MIN(vsi->nb_qps,
5246                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5247                         if (ret < 0) {
5248                                 PMD_DRV_LOG(ERR,
5249                                             "VSI MAIN %d get heap failed %d",
5250                                             vsi->seid, ret);
5251                                 goto fail_queue_alloc;
5252                         }
5253                         vsi->msix_intr = ret;
5254                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5255                                                RTE_MAX_RXTX_INTR_VEC_ID);
5256                 }
5257         } else if (type != I40E_VSI_SRIOV) {
5258                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5259                 if (ret < 0) {
5260                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5261                         goto fail_queue_alloc;
5262                 }
5263                 vsi->msix_intr = ret;
5264                 vsi->nb_msix = 1;
5265         } else {
5266                 vsi->msix_intr = 0;
5267                 vsi->nb_msix = 0;
5268         }
5269
5270         /* Add VSI */
5271         if (type == I40E_VSI_MAIN) {
5272                 /* For main VSI, no need to add since it's default one */
5273                 vsi->uplink_seid = pf->mac_seid;
5274                 vsi->seid = pf->main_vsi_seid;
5275                 /* Bind queues with specific MSIX interrupt */
5276                 /**
5277                  * Needs 2 interrupt at least, one for misc cause which will
5278                  * enabled from OS side, Another for queues binding the
5279                  * interrupt from device side only.
5280                  */
5281
5282                 /* Get default VSI parameters from hardware */
5283                 memset(&ctxt, 0, sizeof(ctxt));
5284                 ctxt.seid = vsi->seid;
5285                 ctxt.pf_num = hw->pf_id;
5286                 ctxt.uplink_seid = vsi->uplink_seid;
5287                 ctxt.vf_num = 0;
5288                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5289                 if (ret != I40E_SUCCESS) {
5290                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5291                         goto fail_msix_alloc;
5292                 }
5293                 rte_memcpy(&vsi->info, &ctxt.info,
5294                         sizeof(struct i40e_aqc_vsi_properties_data));
5295                 vsi->vsi_id = ctxt.vsi_number;
5296                 vsi->info.valid_sections = 0;
5297
5298                 /* Configure tc, enabled TC0 only */
5299                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5300                         I40E_SUCCESS) {
5301                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5302                         goto fail_msix_alloc;
5303                 }
5304
5305                 /* TC, queue mapping */
5306                 memset(&ctxt, 0, sizeof(ctxt));
5307                 vsi->info.valid_sections |=
5308                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5309                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5310                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5311                 rte_memcpy(&ctxt.info, &vsi->info,
5312                         sizeof(struct i40e_aqc_vsi_properties_data));
5313                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5314                                                 I40E_DEFAULT_TCMAP);
5315                 if (ret != I40E_SUCCESS) {
5316                         PMD_DRV_LOG(ERR,
5317                                 "Failed to configure TC queue mapping");
5318                         goto fail_msix_alloc;
5319                 }
5320                 ctxt.seid = vsi->seid;
5321                 ctxt.pf_num = hw->pf_id;
5322                 ctxt.uplink_seid = vsi->uplink_seid;
5323                 ctxt.vf_num = 0;
5324
5325                 /* Update VSI parameters */
5326                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5327                 if (ret != I40E_SUCCESS) {
5328                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5329                         goto fail_msix_alloc;
5330                 }
5331
5332                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5333                                                 sizeof(vsi->info.tc_mapping));
5334                 rte_memcpy(&vsi->info.queue_mapping,
5335                                 &ctxt.info.queue_mapping,
5336                         sizeof(vsi->info.queue_mapping));
5337                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5338                 vsi->info.valid_sections = 0;
5339
5340                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5341                                 ETH_ADDR_LEN);
5342
5343                 /**
5344                  * Updating default filter settings are necessary to prevent
5345                  * reception of tagged packets.
5346                  * Some old firmware configurations load a default macvlan
5347                  * filter which accepts both tagged and untagged packets.
5348                  * The updating is to use a normal filter instead if needed.
5349                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5350                  * The firmware with correct configurations load the default
5351                  * macvlan filter which is expected and cannot be removed.
5352                  */
5353                 i40e_update_default_filter_setting(vsi);
5354                 i40e_config_qinq(hw, vsi);
5355         } else if (type == I40E_VSI_SRIOV) {
5356                 memset(&ctxt, 0, sizeof(ctxt));
5357                 /**
5358                  * For other VSI, the uplink_seid equals to uplink VSI's
5359                  * uplink_seid since they share same VEB
5360                  */
5361                 if (uplink_vsi == NULL)
5362                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5363                 else
5364                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5365                 ctxt.pf_num = hw->pf_id;
5366                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5367                 ctxt.uplink_seid = vsi->uplink_seid;
5368                 ctxt.connection_type = 0x1;
5369                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5370
5371                 /* Use the VEB configuration if FW >= v5.0 */
5372                 if (hw->aq.fw_maj_ver >= 5) {
5373                         /* Configure switch ID */
5374                         ctxt.info.valid_sections |=
5375                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5376                         ctxt.info.switch_id =
5377                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5378                 }
5379
5380                 /* Configure port/vlan */
5381                 ctxt.info.valid_sections |=
5382                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5383                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5384                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5385                                                 hw->func_caps.enabled_tcmap);
5386                 if (ret != I40E_SUCCESS) {
5387                         PMD_DRV_LOG(ERR,
5388                                 "Failed to configure TC queue mapping");
5389                         goto fail_msix_alloc;
5390                 }
5391
5392                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5393                 ctxt.info.valid_sections |=
5394                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5395                 /**
5396                  * Since VSI is not created yet, only configure parameter,
5397                  * will add vsi below.
5398                  */
5399
5400                 i40e_config_qinq(hw, vsi);
5401         } else if (type == I40E_VSI_VMDQ2) {
5402                 memset(&ctxt, 0, sizeof(ctxt));
5403                 /*
5404                  * For other VSI, the uplink_seid equals to uplink VSI's
5405                  * uplink_seid since they share same VEB
5406                  */
5407                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5408                 ctxt.pf_num = hw->pf_id;
5409                 ctxt.vf_num = 0;
5410                 ctxt.uplink_seid = vsi->uplink_seid;
5411                 ctxt.connection_type = 0x1;
5412                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5413
5414                 ctxt.info.valid_sections |=
5415                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5416                 /* user_param carries flag to enable loop back */
5417                 if (user_param) {
5418                         ctxt.info.switch_id =
5419                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5420                         ctxt.info.switch_id |=
5421                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5422                 }
5423
5424                 /* Configure port/vlan */
5425                 ctxt.info.valid_sections |=
5426                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5427                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5428                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5429                                                 I40E_DEFAULT_TCMAP);
5430                 if (ret != I40E_SUCCESS) {
5431                         PMD_DRV_LOG(ERR,
5432                                 "Failed to configure TC queue mapping");
5433                         goto fail_msix_alloc;
5434                 }
5435                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5436                 ctxt.info.valid_sections |=
5437                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5438         } else if (type == I40E_VSI_FDIR) {
5439                 memset(&ctxt, 0, sizeof(ctxt));
5440                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5441                 ctxt.pf_num = hw->pf_id;
5442                 ctxt.vf_num = 0;
5443                 ctxt.uplink_seid = vsi->uplink_seid;
5444                 ctxt.connection_type = 0x1;     /* regular data port */
5445                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5446                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5447                                                 I40E_DEFAULT_TCMAP);
5448                 if (ret != I40E_SUCCESS) {
5449                         PMD_DRV_LOG(ERR,
5450                                 "Failed to configure TC queue mapping.");
5451                         goto fail_msix_alloc;
5452                 }
5453                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5454                 ctxt.info.valid_sections |=
5455                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5456         } else {
5457                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5458                 goto fail_msix_alloc;
5459         }
5460
5461         if (vsi->type != I40E_VSI_MAIN) {
5462                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5463                 if (ret != I40E_SUCCESS) {
5464                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5465                                     hw->aq.asq_last_status);
5466                         goto fail_msix_alloc;
5467                 }
5468                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5469                 vsi->info.valid_sections = 0;
5470                 vsi->seid = ctxt.seid;
5471                 vsi->vsi_id = ctxt.vsi_number;
5472                 vsi->sib_vsi_list.vsi = vsi;
5473                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5474                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5475                                           &vsi->sib_vsi_list, list);
5476                 } else {
5477                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5478                                           &vsi->sib_vsi_list, list);
5479                 }
5480         }
5481
5482         /* MAC/VLAN configuration */
5483         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5484         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5485
5486         ret = i40e_vsi_add_mac(vsi, &filter);
5487         if (ret != I40E_SUCCESS) {
5488                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5489                 goto fail_msix_alloc;
5490         }
5491
5492         /* Get VSI BW information */
5493         i40e_vsi_get_bw_config(vsi);
5494         return vsi;
5495 fail_msix_alloc:
5496         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5497 fail_queue_alloc:
5498         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5499 fail_mem:
5500         rte_free(vsi);
5501         return NULL;
5502 }
5503
5504 /* Configure vlan filter on or off */
5505 int
5506 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5507 {
5508         int i, num;
5509         struct i40e_mac_filter *f;
5510         void *temp;
5511         struct i40e_mac_filter_info *mac_filter;
5512         enum rte_mac_filter_type desired_filter;
5513         int ret = I40E_SUCCESS;
5514
5515         if (on) {
5516                 /* Filter to match MAC and VLAN */
5517                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5518         } else {
5519                 /* Filter to match only MAC */
5520                 desired_filter = RTE_MAC_PERFECT_MATCH;
5521         }
5522
5523         num = vsi->mac_num;
5524
5525         mac_filter = rte_zmalloc("mac_filter_info_data",
5526                                  num * sizeof(*mac_filter), 0);
5527         if (mac_filter == NULL) {
5528                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5529                 return I40E_ERR_NO_MEMORY;
5530         }
5531
5532         i = 0;
5533
5534         /* Remove all existing mac */
5535         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5536                 mac_filter[i] = f->mac_info;
5537                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5538                 if (ret) {
5539                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5540                                     on ? "enable" : "disable");
5541                         goto DONE;
5542                 }
5543                 i++;
5544         }
5545
5546         /* Override with new filter */
5547         for (i = 0; i < num; i++) {
5548                 mac_filter[i].filter_type = desired_filter;
5549                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5550                 if (ret) {
5551                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5552                                     on ? "enable" : "disable");
5553                         goto DONE;
5554                 }
5555         }
5556
5557 DONE:
5558         rte_free(mac_filter);
5559         return ret;
5560 }
5561
5562 /* Configure vlan stripping on or off */
5563 int
5564 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5565 {
5566         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5567         struct i40e_vsi_context ctxt;
5568         uint8_t vlan_flags;
5569         int ret = I40E_SUCCESS;
5570
5571         /* Check if it has been already on or off */
5572         if (vsi->info.valid_sections &
5573                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5574                 if (on) {
5575                         if ((vsi->info.port_vlan_flags &
5576                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5577                                 return 0; /* already on */
5578                 } else {
5579                         if ((vsi->info.port_vlan_flags &
5580                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5581                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5582                                 return 0; /* already off */
5583                 }
5584         }
5585
5586         if (on)
5587                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5588         else
5589                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5590         vsi->info.valid_sections =
5591                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5592         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5593         vsi->info.port_vlan_flags |= vlan_flags;
5594         ctxt.seid = vsi->seid;
5595         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5596         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5597         if (ret)
5598                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5599                             on ? "enable" : "disable");
5600
5601         return ret;
5602 }
5603
5604 static int
5605 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5606 {
5607         struct rte_eth_dev_data *data = dev->data;
5608         int ret;
5609         int mask = 0;
5610
5611         /* Apply vlan offload setting */
5612         mask = ETH_VLAN_STRIP_MASK |
5613                ETH_VLAN_FILTER_MASK |
5614                ETH_VLAN_EXTEND_MASK;
5615         ret = i40e_vlan_offload_set(dev, mask);
5616         if (ret) {
5617                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5618                 return ret;
5619         }
5620
5621         /* Apply pvid setting */
5622         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5623                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5624         if (ret)
5625                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5626
5627         return ret;
5628 }
5629
5630 static int
5631 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5632 {
5633         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5634
5635         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5636 }
5637
5638 static int
5639 i40e_update_flow_control(struct i40e_hw *hw)
5640 {
5641 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5642         struct i40e_link_status link_status;
5643         uint32_t rxfc = 0, txfc = 0, reg;
5644         uint8_t an_info;
5645         int ret;
5646
5647         memset(&link_status, 0, sizeof(link_status));
5648         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5649         if (ret != I40E_SUCCESS) {
5650                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5651                 goto write_reg; /* Disable flow control */
5652         }
5653
5654         an_info = hw->phy.link_info.an_info;
5655         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5656                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5657                 ret = I40E_ERR_NOT_READY;
5658                 goto write_reg; /* Disable flow control */
5659         }
5660         /**
5661          * If link auto negotiation is enabled, flow control needs to
5662          * be configured according to it
5663          */
5664         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5665         case I40E_LINK_PAUSE_RXTX:
5666                 rxfc = 1;
5667                 txfc = 1;
5668                 hw->fc.current_mode = I40E_FC_FULL;
5669                 break;
5670         case I40E_AQ_LINK_PAUSE_RX:
5671                 rxfc = 1;
5672                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5673                 break;
5674         case I40E_AQ_LINK_PAUSE_TX:
5675                 txfc = 1;
5676                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5677                 break;
5678         default:
5679                 hw->fc.current_mode = I40E_FC_NONE;
5680                 break;
5681         }
5682
5683 write_reg:
5684         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5685                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5686         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5687         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5688         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5689         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5690
5691         return ret;
5692 }
5693
5694 /* PF setup */
5695 static int
5696 i40e_pf_setup(struct i40e_pf *pf)
5697 {
5698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5699         struct i40e_filter_control_settings settings;
5700         struct i40e_vsi *vsi;
5701         int ret;
5702
5703         /* Clear all stats counters */
5704         pf->offset_loaded = FALSE;
5705         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5706         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5707         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5708         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5709
5710         ret = i40e_pf_get_switch_config(pf);
5711         if (ret != I40E_SUCCESS) {
5712                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5713                 return ret;
5714         }
5715         if (pf->flags & I40E_FLAG_FDIR) {
5716                 /* make queue allocated first, let FDIR use queue pair 0*/
5717                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5718                 if (ret != I40E_FDIR_QUEUE_ID) {
5719                         PMD_DRV_LOG(ERR,
5720                                 "queue allocation fails for FDIR: ret =%d",
5721                                 ret);
5722                         pf->flags &= ~I40E_FLAG_FDIR;
5723                 }
5724         }
5725         /*  main VSI setup */
5726         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5727         if (!vsi) {
5728                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5729                 return I40E_ERR_NOT_READY;
5730         }
5731         pf->main_vsi = vsi;
5732
5733         /* Configure filter control */
5734         memset(&settings, 0, sizeof(settings));
5735         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5736                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5737         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5738                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5739         else {
5740                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5741                         hw->func_caps.rss_table_size);
5742                 return I40E_ERR_PARAM;
5743         }
5744         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5745                 hw->func_caps.rss_table_size);
5746         pf->hash_lut_size = hw->func_caps.rss_table_size;
5747
5748         /* Enable ethtype and macvlan filters */
5749         settings.enable_ethtype = TRUE;
5750         settings.enable_macvlan = TRUE;
5751         ret = i40e_set_filter_control(hw, &settings);
5752         if (ret)
5753                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5754                                                                 ret);
5755
5756         /* Update flow control according to the auto negotiation */
5757         i40e_update_flow_control(hw);
5758
5759         return I40E_SUCCESS;
5760 }
5761
5762 int
5763 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5764 {
5765         uint32_t reg;
5766         uint16_t j;
5767
5768         /**
5769          * Set or clear TX Queue Disable flags,
5770          * which is required by hardware.
5771          */
5772         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5773         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5774
5775         /* Wait until the request is finished */
5776         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5777                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5778                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5779                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5780                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5781                                                         & 0x1))) {
5782                         break;
5783                 }
5784         }
5785         if (on) {
5786                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5787                         return I40E_SUCCESS; /* already on, skip next steps */
5788
5789                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5790                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5791         } else {
5792                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5793                         return I40E_SUCCESS; /* already off, skip next steps */
5794                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5795         }
5796         /* Write the register */
5797         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5798         /* Check the result */
5799         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5800                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5801                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5802                 if (on) {
5803                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5804                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5805                                 break;
5806                 } else {
5807                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5808                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5809                                 break;
5810                 }
5811         }
5812         /* Check if it is timeout */
5813         if (j >= I40E_CHK_Q_ENA_COUNT) {
5814                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5815                             (on ? "enable" : "disable"), q_idx);
5816                 return I40E_ERR_TIMEOUT;
5817         }
5818
5819         return I40E_SUCCESS;
5820 }
5821
5822 /* Swith on or off the tx queues */
5823 static int
5824 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5825 {
5826         struct rte_eth_dev_data *dev_data = pf->dev_data;
5827         struct i40e_tx_queue *txq;
5828         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5829         uint16_t i;
5830         int ret;
5831
5832         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5833                 txq = dev_data->tx_queues[i];
5834                 /* Don't operate the queue if not configured or
5835                  * if starting only per queue */
5836                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5837                         continue;
5838                 if (on)
5839                         ret = i40e_dev_tx_queue_start(dev, i);
5840                 else
5841                         ret = i40e_dev_tx_queue_stop(dev, i);
5842                 if ( ret != I40E_SUCCESS)
5843                         return ret;
5844         }
5845
5846         return I40E_SUCCESS;
5847 }
5848
5849 int
5850 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5851 {
5852         uint32_t reg;
5853         uint16_t j;
5854
5855         /* Wait until the request is finished */
5856         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5857                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5858                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5859                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5860                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5861                         break;
5862         }
5863
5864         if (on) {
5865                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5866                         return I40E_SUCCESS; /* Already on, skip next steps */
5867                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5868         } else {
5869                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5870                         return I40E_SUCCESS; /* Already off, skip next steps */
5871                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5872         }
5873
5874         /* Write the register */
5875         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5876         /* Check the result */
5877         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5878                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5879                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5880                 if (on) {
5881                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5882                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5883                                 break;
5884                 } else {
5885                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5886                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5887                                 break;
5888                 }
5889         }
5890
5891         /* Check if it is timeout */
5892         if (j >= I40E_CHK_Q_ENA_COUNT) {
5893                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5894                             (on ? "enable" : "disable"), q_idx);
5895                 return I40E_ERR_TIMEOUT;
5896         }
5897
5898         return I40E_SUCCESS;
5899 }
5900 /* Switch on or off the rx queues */
5901 static int
5902 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5903 {
5904         struct rte_eth_dev_data *dev_data = pf->dev_data;
5905         struct i40e_rx_queue *rxq;
5906         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5907         uint16_t i;
5908         int ret;
5909
5910         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5911                 rxq = dev_data->rx_queues[i];
5912                 /* Don't operate the queue if not configured or
5913                  * if starting only per queue */
5914                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5915                         continue;
5916                 if (on)
5917                         ret = i40e_dev_rx_queue_start(dev, i);
5918                 else
5919                         ret = i40e_dev_rx_queue_stop(dev, i);
5920                 if (ret != I40E_SUCCESS)
5921                         return ret;
5922         }
5923
5924         return I40E_SUCCESS;
5925 }
5926
5927 /* Switch on or off all the rx/tx queues */
5928 int
5929 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5930 {
5931         int ret;
5932
5933         if (on) {
5934                 /* enable rx queues before enabling tx queues */
5935                 ret = i40e_dev_switch_rx_queues(pf, on);
5936                 if (ret) {
5937                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5938                         return ret;
5939                 }
5940                 ret = i40e_dev_switch_tx_queues(pf, on);
5941         } else {
5942                 /* Stop tx queues before stopping rx queues */
5943                 ret = i40e_dev_switch_tx_queues(pf, on);
5944                 if (ret) {
5945                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5946                         return ret;
5947                 }
5948                 ret = i40e_dev_switch_rx_queues(pf, on);
5949         }
5950
5951         return ret;
5952 }
5953
5954 /* Initialize VSI for TX */
5955 static int
5956 i40e_dev_tx_init(struct i40e_pf *pf)
5957 {
5958         struct rte_eth_dev_data *data = pf->dev_data;
5959         uint16_t i;
5960         uint32_t ret = I40E_SUCCESS;
5961         struct i40e_tx_queue *txq;
5962
5963         for (i = 0; i < data->nb_tx_queues; i++) {
5964                 txq = data->tx_queues[i];
5965                 if (!txq || !txq->q_set)
5966                         continue;
5967                 ret = i40e_tx_queue_init(txq);
5968                 if (ret != I40E_SUCCESS)
5969                         break;
5970         }
5971         if (ret == I40E_SUCCESS)
5972                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5973                                      ->eth_dev);
5974
5975         return ret;
5976 }
5977
5978 /* Initialize VSI for RX */
5979 static int
5980 i40e_dev_rx_init(struct i40e_pf *pf)
5981 {
5982         struct rte_eth_dev_data *data = pf->dev_data;
5983         int ret = I40E_SUCCESS;
5984         uint16_t i;
5985         struct i40e_rx_queue *rxq;
5986
5987         i40e_pf_config_mq_rx(pf);
5988         for (i = 0; i < data->nb_rx_queues; i++) {
5989                 rxq = data->rx_queues[i];
5990                 if (!rxq || !rxq->q_set)
5991                         continue;
5992
5993                 ret = i40e_rx_queue_init(rxq);
5994                 if (ret != I40E_SUCCESS) {
5995                         PMD_DRV_LOG(ERR,
5996                                 "Failed to do RX queue initialization");
5997                         break;
5998                 }
5999         }
6000         if (ret == I40E_SUCCESS)
6001                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6002                                      ->eth_dev);
6003
6004         return ret;
6005 }
6006
6007 static int
6008 i40e_dev_rxtx_init(struct i40e_pf *pf)
6009 {
6010         int err;
6011
6012         err = i40e_dev_tx_init(pf);
6013         if (err) {
6014                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6015                 return err;
6016         }
6017         err = i40e_dev_rx_init(pf);
6018         if (err) {
6019                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6020                 return err;
6021         }
6022
6023         return err;
6024 }
6025
6026 static int
6027 i40e_vmdq_setup(struct rte_eth_dev *dev)
6028 {
6029         struct rte_eth_conf *conf = &dev->data->dev_conf;
6030         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6031         int i, err, conf_vsis, j, loop;
6032         struct i40e_vsi *vsi;
6033         struct i40e_vmdq_info *vmdq_info;
6034         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6035         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6036
6037         /*
6038          * Disable interrupt to avoid message from VF. Furthermore, it will
6039          * avoid race condition in VSI creation/destroy.
6040          */
6041         i40e_pf_disable_irq0(hw);
6042
6043         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6044                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6045                 return -ENOTSUP;
6046         }
6047
6048         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6049         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6050                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6051                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6052                         pf->max_nb_vmdq_vsi);
6053                 return -ENOTSUP;
6054         }
6055
6056         if (pf->vmdq != NULL) {
6057                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6058                 return 0;
6059         }
6060
6061         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6062                                 sizeof(*vmdq_info) * conf_vsis, 0);
6063
6064         if (pf->vmdq == NULL) {
6065                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6066                 return -ENOMEM;
6067         }
6068
6069         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6070
6071         /* Create VMDQ VSI */
6072         for (i = 0; i < conf_vsis; i++) {
6073                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6074                                 vmdq_conf->enable_loop_back);
6075                 if (vsi == NULL) {
6076                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6077                         err = -1;
6078                         goto err_vsi_setup;
6079                 }
6080                 vmdq_info = &pf->vmdq[i];
6081                 vmdq_info->pf = pf;
6082                 vmdq_info->vsi = vsi;
6083         }
6084         pf->nb_cfg_vmdq_vsi = conf_vsis;
6085
6086         /* Configure Vlan */
6087         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6088         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6089                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6090                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6091                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6092                                         vmdq_conf->pool_map[i].vlan_id, j);
6093
6094                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6095                                                 vmdq_conf->pool_map[i].vlan_id);
6096                                 if (err) {
6097                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6098                                         err = -1;
6099                                         goto err_vsi_setup;
6100                                 }
6101                         }
6102                 }
6103         }
6104
6105         i40e_pf_enable_irq0(hw);
6106
6107         return 0;
6108
6109 err_vsi_setup:
6110         for (i = 0; i < conf_vsis; i++)
6111                 if (pf->vmdq[i].vsi == NULL)
6112                         break;
6113                 else
6114                         i40e_vsi_release(pf->vmdq[i].vsi);
6115
6116         rte_free(pf->vmdq);
6117         pf->vmdq = NULL;
6118         i40e_pf_enable_irq0(hw);
6119         return err;
6120 }
6121
6122 static void
6123 i40e_stat_update_32(struct i40e_hw *hw,
6124                    uint32_t reg,
6125                    bool offset_loaded,
6126                    uint64_t *offset,
6127                    uint64_t *stat)
6128 {
6129         uint64_t new_data;
6130
6131         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6132         if (!offset_loaded)
6133                 *offset = new_data;
6134
6135         if (new_data >= *offset)
6136                 *stat = (uint64_t)(new_data - *offset);
6137         else
6138                 *stat = (uint64_t)((new_data +
6139                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6140 }
6141
6142 static void
6143 i40e_stat_update_48(struct i40e_hw *hw,
6144                    uint32_t hireg,
6145                    uint32_t loreg,
6146                    bool offset_loaded,
6147                    uint64_t *offset,
6148                    uint64_t *stat)
6149 {
6150         uint64_t new_data;
6151
6152         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6153         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6154                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6155
6156         if (!offset_loaded)
6157                 *offset = new_data;
6158
6159         if (new_data >= *offset)
6160                 *stat = new_data - *offset;
6161         else
6162                 *stat = (uint64_t)((new_data +
6163                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6164
6165         *stat &= I40E_48_BIT_MASK;
6166 }
6167
6168 /* Disable IRQ0 */
6169 void
6170 i40e_pf_disable_irq0(struct i40e_hw *hw)
6171 {
6172         /* Disable all interrupt types */
6173         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6174                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6175         I40E_WRITE_FLUSH(hw);
6176 }
6177
6178 /* Enable IRQ0 */
6179 void
6180 i40e_pf_enable_irq0(struct i40e_hw *hw)
6181 {
6182         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6183                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6184                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6185                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6186         I40E_WRITE_FLUSH(hw);
6187 }
6188
6189 static void
6190 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6191 {
6192         /* read pending request and disable first */
6193         i40e_pf_disable_irq0(hw);
6194         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6195         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6196                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6197
6198         if (no_queue)
6199                 /* Link no queues with irq0 */
6200                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6201                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6202 }
6203
6204 static void
6205 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6206 {
6207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6209         int i;
6210         uint16_t abs_vf_id;
6211         uint32_t index, offset, val;
6212
6213         if (!pf->vfs)
6214                 return;
6215         /**
6216          * Try to find which VF trigger a reset, use absolute VF id to access
6217          * since the reg is global register.
6218          */
6219         for (i = 0; i < pf->vf_num; i++) {
6220                 abs_vf_id = hw->func_caps.vf_base_id + i;
6221                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6222                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6223                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6224                 /* VFR event occurred */
6225                 if (val & (0x1 << offset)) {
6226                         int ret;
6227
6228                         /* Clear the event first */
6229                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6230                                                         (0x1 << offset));
6231                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6232                         /**
6233                          * Only notify a VF reset event occurred,
6234                          * don't trigger another SW reset
6235                          */
6236                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6237                         if (ret != I40E_SUCCESS)
6238                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6239                 }
6240         }
6241 }
6242
6243 static void
6244 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6245 {
6246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6247         int i;
6248
6249         for (i = 0; i < pf->vf_num; i++)
6250                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6251 }
6252
6253 static void
6254 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6255 {
6256         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6257         struct i40e_arq_event_info info;
6258         uint16_t pending, opcode;
6259         int ret;
6260
6261         info.buf_len = I40E_AQ_BUF_SZ;
6262         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6263         if (!info.msg_buf) {
6264                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6265                 return;
6266         }
6267
6268         pending = 1;
6269         while (pending) {
6270                 ret = i40e_clean_arq_element(hw, &info, &pending);
6271
6272                 if (ret != I40E_SUCCESS) {
6273                         PMD_DRV_LOG(INFO,
6274                                 "Failed to read msg from AdminQ, aq_err: %u",
6275                                 hw->aq.asq_last_status);
6276                         break;
6277                 }
6278                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6279
6280                 switch (opcode) {
6281                 case i40e_aqc_opc_send_msg_to_pf:
6282                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6283                         i40e_pf_host_handle_vf_msg(dev,
6284                                         rte_le_to_cpu_16(info.desc.retval),
6285                                         rte_le_to_cpu_32(info.desc.cookie_high),
6286                                         rte_le_to_cpu_32(info.desc.cookie_low),
6287                                         info.msg_buf,
6288                                         info.msg_len);
6289                         break;
6290                 case i40e_aqc_opc_get_link_status:
6291                         ret = i40e_dev_link_update(dev, 0);
6292                         if (!ret)
6293                                 _rte_eth_dev_callback_process(dev,
6294                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6295                         break;
6296                 default:
6297                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6298                                     opcode);
6299                         break;
6300                 }
6301         }
6302         rte_free(info.msg_buf);
6303 }
6304
6305 /**
6306  * Interrupt handler triggered by NIC  for handling
6307  * specific interrupt.
6308  *
6309  * @param handle
6310  *  Pointer to interrupt handle.
6311  * @param param
6312  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6313  *
6314  * @return
6315  *  void
6316  */
6317 static void
6318 i40e_dev_interrupt_handler(void *param)
6319 {
6320         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6321         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6322         uint32_t icr0;
6323
6324         /* Disable interrupt */
6325         i40e_pf_disable_irq0(hw);
6326
6327         /* read out interrupt causes */
6328         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6329
6330         /* No interrupt event indicated */
6331         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6332                 PMD_DRV_LOG(INFO, "No interrupt event");
6333                 goto done;
6334         }
6335         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6336                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6337         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6338                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6339         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6340                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6341         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6342                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6343         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6344                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6345         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6346                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6347         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6348                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6349
6350         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6351                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6352                 i40e_dev_handle_vfr_event(dev);
6353         }
6354         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6355                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6356                 i40e_dev_handle_aq_msg(dev);
6357         }
6358
6359 done:
6360         /* Enable interrupt */
6361         i40e_pf_enable_irq0(hw);
6362         rte_intr_enable(dev->intr_handle);
6363 }
6364
6365 int
6366 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6367                          struct i40e_macvlan_filter *filter,
6368                          int total)
6369 {
6370         int ele_num, ele_buff_size;
6371         int num, actual_num, i;
6372         uint16_t flags;
6373         int ret = I40E_SUCCESS;
6374         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6375         struct i40e_aqc_add_macvlan_element_data *req_list;
6376
6377         if (filter == NULL  || total == 0)
6378                 return I40E_ERR_PARAM;
6379         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6380         ele_buff_size = hw->aq.asq_buf_size;
6381
6382         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6383         if (req_list == NULL) {
6384                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6385                 return I40E_ERR_NO_MEMORY;
6386         }
6387
6388         num = 0;
6389         do {
6390                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6391                 memset(req_list, 0, ele_buff_size);
6392
6393                 for (i = 0; i < actual_num; i++) {
6394                         rte_memcpy(req_list[i].mac_addr,
6395                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6396                         req_list[i].vlan_tag =
6397                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6398
6399                         switch (filter[num + i].filter_type) {
6400                         case RTE_MAC_PERFECT_MATCH:
6401                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6402                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6403                                 break;
6404                         case RTE_MACVLAN_PERFECT_MATCH:
6405                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6406                                 break;
6407                         case RTE_MAC_HASH_MATCH:
6408                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6409                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6410                                 break;
6411                         case RTE_MACVLAN_HASH_MATCH:
6412                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6413                                 break;
6414                         default:
6415                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6416                                 ret = I40E_ERR_PARAM;
6417                                 goto DONE;
6418                         }
6419
6420                         req_list[i].queue_number = 0;
6421
6422                         req_list[i].flags = rte_cpu_to_le_16(flags);
6423                 }
6424
6425                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6426                                                 actual_num, NULL);
6427                 if (ret != I40E_SUCCESS) {
6428                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6429                         goto DONE;
6430                 }
6431                 num += actual_num;
6432         } while (num < total);
6433
6434 DONE:
6435         rte_free(req_list);
6436         return ret;
6437 }
6438
6439 int
6440 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6441                             struct i40e_macvlan_filter *filter,
6442                             int total)
6443 {
6444         int ele_num, ele_buff_size;
6445         int num, actual_num, i;
6446         uint16_t flags;
6447         int ret = I40E_SUCCESS;
6448         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6449         struct i40e_aqc_remove_macvlan_element_data *req_list;
6450
6451         if (filter == NULL  || total == 0)
6452                 return I40E_ERR_PARAM;
6453
6454         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6455         ele_buff_size = hw->aq.asq_buf_size;
6456
6457         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6458         if (req_list == NULL) {
6459                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6460                 return I40E_ERR_NO_MEMORY;
6461         }
6462
6463         num = 0;
6464         do {
6465                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6466                 memset(req_list, 0, ele_buff_size);
6467
6468                 for (i = 0; i < actual_num; i++) {
6469                         rte_memcpy(req_list[i].mac_addr,
6470                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6471                         req_list[i].vlan_tag =
6472                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6473
6474                         switch (filter[num + i].filter_type) {
6475                         case RTE_MAC_PERFECT_MATCH:
6476                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6477                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6478                                 break;
6479                         case RTE_MACVLAN_PERFECT_MATCH:
6480                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6481                                 break;
6482                         case RTE_MAC_HASH_MATCH:
6483                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6484                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6485                                 break;
6486                         case RTE_MACVLAN_HASH_MATCH:
6487                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6488                                 break;
6489                         default:
6490                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6491                                 ret = I40E_ERR_PARAM;
6492                                 goto DONE;
6493                         }
6494                         req_list[i].flags = rte_cpu_to_le_16(flags);
6495                 }
6496
6497                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6498                                                 actual_num, NULL);
6499                 if (ret != I40E_SUCCESS) {
6500                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6501                         goto DONE;
6502                 }
6503                 num += actual_num;
6504         } while (num < total);
6505
6506 DONE:
6507         rte_free(req_list);
6508         return ret;
6509 }
6510
6511 /* Find out specific MAC filter */
6512 static struct i40e_mac_filter *
6513 i40e_find_mac_filter(struct i40e_vsi *vsi,
6514                          struct ether_addr *macaddr)
6515 {
6516         struct i40e_mac_filter *f;
6517
6518         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6519                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6520                         return f;
6521         }
6522
6523         return NULL;
6524 }
6525
6526 static bool
6527 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6528                          uint16_t vlan_id)
6529 {
6530         uint32_t vid_idx, vid_bit;
6531
6532         if (vlan_id > ETH_VLAN_ID_MAX)
6533                 return 0;
6534
6535         vid_idx = I40E_VFTA_IDX(vlan_id);
6536         vid_bit = I40E_VFTA_BIT(vlan_id);
6537
6538         if (vsi->vfta[vid_idx] & vid_bit)
6539                 return 1;
6540         else
6541                 return 0;
6542 }
6543
6544 static void
6545 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6546                        uint16_t vlan_id, bool on)
6547 {
6548         uint32_t vid_idx, vid_bit;
6549
6550         vid_idx = I40E_VFTA_IDX(vlan_id);
6551         vid_bit = I40E_VFTA_BIT(vlan_id);
6552
6553         if (on)
6554                 vsi->vfta[vid_idx] |= vid_bit;
6555         else
6556                 vsi->vfta[vid_idx] &= ~vid_bit;
6557 }
6558
6559 void
6560 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6561                      uint16_t vlan_id, bool on)
6562 {
6563         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6564         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6565         int ret;
6566
6567         if (vlan_id > ETH_VLAN_ID_MAX)
6568                 return;
6569
6570         i40e_store_vlan_filter(vsi, vlan_id, on);
6571
6572         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6573                 return;
6574
6575         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6576
6577         if (on) {
6578                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6579                                        &vlan_data, 1, NULL);
6580                 if (ret != I40E_SUCCESS)
6581                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6582         } else {
6583                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6584                                           &vlan_data, 1, NULL);
6585                 if (ret != I40E_SUCCESS)
6586                         PMD_DRV_LOG(ERR,
6587                                     "Failed to remove vlan filter");
6588         }
6589 }
6590
6591 /**
6592  * Find all vlan options for specific mac addr,
6593  * return with actual vlan found.
6594  */
6595 int
6596 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6597                            struct i40e_macvlan_filter *mv_f,
6598                            int num, struct ether_addr *addr)
6599 {
6600         int i;
6601         uint32_t j, k;
6602
6603         /**
6604          * Not to use i40e_find_vlan_filter to decrease the loop time,
6605          * although the code looks complex.
6606           */
6607         if (num < vsi->vlan_num)
6608                 return I40E_ERR_PARAM;
6609
6610         i = 0;
6611         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6612                 if (vsi->vfta[j]) {
6613                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6614                                 if (vsi->vfta[j] & (1 << k)) {
6615                                         if (i > num - 1) {
6616                                                 PMD_DRV_LOG(ERR,
6617                                                         "vlan number doesn't match");
6618                                                 return I40E_ERR_PARAM;
6619                                         }
6620                                         rte_memcpy(&mv_f[i].macaddr,
6621                                                         addr, ETH_ADDR_LEN);
6622                                         mv_f[i].vlan_id =
6623                                                 j * I40E_UINT32_BIT_SIZE + k;
6624                                         i++;
6625                                 }
6626                         }
6627                 }
6628         }
6629         return I40E_SUCCESS;
6630 }
6631
6632 static inline int
6633 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6634                            struct i40e_macvlan_filter *mv_f,
6635                            int num,
6636                            uint16_t vlan)
6637 {
6638         int i = 0;
6639         struct i40e_mac_filter *f;
6640
6641         if (num < vsi->mac_num)
6642                 return I40E_ERR_PARAM;
6643
6644         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6645                 if (i > num - 1) {
6646                         PMD_DRV_LOG(ERR, "buffer number not match");
6647                         return I40E_ERR_PARAM;
6648                 }
6649                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6650                                 ETH_ADDR_LEN);
6651                 mv_f[i].vlan_id = vlan;
6652                 mv_f[i].filter_type = f->mac_info.filter_type;
6653                 i++;
6654         }
6655
6656         return I40E_SUCCESS;
6657 }
6658
6659 static int
6660 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6661 {
6662         int i, j, num;
6663         struct i40e_mac_filter *f;
6664         struct i40e_macvlan_filter *mv_f;
6665         int ret = I40E_SUCCESS;
6666
6667         if (vsi == NULL || vsi->mac_num == 0)
6668                 return I40E_ERR_PARAM;
6669
6670         /* Case that no vlan is set */
6671         if (vsi->vlan_num == 0)
6672                 num = vsi->mac_num;
6673         else
6674                 num = vsi->mac_num * vsi->vlan_num;
6675
6676         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6677         if (mv_f == NULL) {
6678                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6679                 return I40E_ERR_NO_MEMORY;
6680         }
6681
6682         i = 0;
6683         if (vsi->vlan_num == 0) {
6684                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6685                         rte_memcpy(&mv_f[i].macaddr,
6686                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6687                         mv_f[i].filter_type = f->mac_info.filter_type;
6688                         mv_f[i].vlan_id = 0;
6689                         i++;
6690                 }
6691         } else {
6692                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6693                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6694                                         vsi->vlan_num, &f->mac_info.mac_addr);
6695                         if (ret != I40E_SUCCESS)
6696                                 goto DONE;
6697                         for (j = i; j < i + vsi->vlan_num; j++)
6698                                 mv_f[j].filter_type = f->mac_info.filter_type;
6699                         i += vsi->vlan_num;
6700                 }
6701         }
6702
6703         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6704 DONE:
6705         rte_free(mv_f);
6706
6707         return ret;
6708 }
6709
6710 int
6711 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6712 {
6713         struct i40e_macvlan_filter *mv_f;
6714         int mac_num;
6715         int ret = I40E_SUCCESS;
6716
6717         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6718                 return I40E_ERR_PARAM;
6719
6720         /* If it's already set, just return */
6721         if (i40e_find_vlan_filter(vsi,vlan))
6722                 return I40E_SUCCESS;
6723
6724         mac_num = vsi->mac_num;
6725
6726         if (mac_num == 0) {
6727                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6728                 return I40E_ERR_PARAM;
6729         }
6730
6731         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6732
6733         if (mv_f == NULL) {
6734                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6735                 return I40E_ERR_NO_MEMORY;
6736         }
6737
6738         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6739
6740         if (ret != I40E_SUCCESS)
6741                 goto DONE;
6742
6743         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6744
6745         if (ret != I40E_SUCCESS)
6746                 goto DONE;
6747
6748         i40e_set_vlan_filter(vsi, vlan, 1);
6749
6750         vsi->vlan_num++;
6751         ret = I40E_SUCCESS;
6752 DONE:
6753         rte_free(mv_f);
6754         return ret;
6755 }
6756
6757 int
6758 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6759 {
6760         struct i40e_macvlan_filter *mv_f;
6761         int mac_num;
6762         int ret = I40E_SUCCESS;
6763
6764         /**
6765          * Vlan 0 is the generic filter for untagged packets
6766          * and can't be removed.
6767          */
6768         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6769                 return I40E_ERR_PARAM;
6770
6771         /* If can't find it, just return */
6772         if (!i40e_find_vlan_filter(vsi, vlan))
6773                 return I40E_ERR_PARAM;
6774
6775         mac_num = vsi->mac_num;
6776
6777         if (mac_num == 0) {
6778                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6779                 return I40E_ERR_PARAM;
6780         }
6781
6782         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6783
6784         if (mv_f == NULL) {
6785                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6786                 return I40E_ERR_NO_MEMORY;
6787         }
6788
6789         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6790
6791         if (ret != I40E_SUCCESS)
6792                 goto DONE;
6793
6794         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6795
6796         if (ret != I40E_SUCCESS)
6797                 goto DONE;
6798
6799         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6800         if (vsi->vlan_num == 1) {
6801                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6802                 if (ret != I40E_SUCCESS)
6803                         goto DONE;
6804
6805                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6806                 if (ret != I40E_SUCCESS)
6807                         goto DONE;
6808         }
6809
6810         i40e_set_vlan_filter(vsi, vlan, 0);
6811
6812         vsi->vlan_num--;
6813         ret = I40E_SUCCESS;
6814 DONE:
6815         rte_free(mv_f);
6816         return ret;
6817 }
6818
6819 int
6820 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6821 {
6822         struct i40e_mac_filter *f;
6823         struct i40e_macvlan_filter *mv_f;
6824         int i, vlan_num = 0;
6825         int ret = I40E_SUCCESS;
6826
6827         /* If it's add and we've config it, return */
6828         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6829         if (f != NULL)
6830                 return I40E_SUCCESS;
6831         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6832                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6833
6834                 /**
6835                  * If vlan_num is 0, that's the first time to add mac,
6836                  * set mask for vlan_id 0.
6837                  */
6838                 if (vsi->vlan_num == 0) {
6839                         i40e_set_vlan_filter(vsi, 0, 1);
6840                         vsi->vlan_num = 1;
6841                 }
6842                 vlan_num = vsi->vlan_num;
6843         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6844                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6845                 vlan_num = 1;
6846
6847         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6848         if (mv_f == NULL) {
6849                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6850                 return I40E_ERR_NO_MEMORY;
6851         }
6852
6853         for (i = 0; i < vlan_num; i++) {
6854                 mv_f[i].filter_type = mac_filter->filter_type;
6855                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6856                                 ETH_ADDR_LEN);
6857         }
6858
6859         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6860                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6861                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6862                                         &mac_filter->mac_addr);
6863                 if (ret != I40E_SUCCESS)
6864                         goto DONE;
6865         }
6866
6867         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6868         if (ret != I40E_SUCCESS)
6869                 goto DONE;
6870
6871         /* Add the mac addr into mac list */
6872         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6873         if (f == NULL) {
6874                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6875                 ret = I40E_ERR_NO_MEMORY;
6876                 goto DONE;
6877         }
6878         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6879                         ETH_ADDR_LEN);
6880         f->mac_info.filter_type = mac_filter->filter_type;
6881         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6882         vsi->mac_num++;
6883
6884         ret = I40E_SUCCESS;
6885 DONE:
6886         rte_free(mv_f);
6887
6888         return ret;
6889 }
6890
6891 int
6892 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6893 {
6894         struct i40e_mac_filter *f;
6895         struct i40e_macvlan_filter *mv_f;
6896         int i, vlan_num;
6897         enum rte_mac_filter_type filter_type;
6898         int ret = I40E_SUCCESS;
6899
6900         /* Can't find it, return an error */
6901         f = i40e_find_mac_filter(vsi, addr);
6902         if (f == NULL)
6903                 return I40E_ERR_PARAM;
6904
6905         vlan_num = vsi->vlan_num;
6906         filter_type = f->mac_info.filter_type;
6907         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6908                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6909                 if (vlan_num == 0) {
6910                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6911                         return I40E_ERR_PARAM;
6912                 }
6913         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6914                         filter_type == RTE_MAC_HASH_MATCH)
6915                 vlan_num = 1;
6916
6917         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6918         if (mv_f == NULL) {
6919                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6920                 return I40E_ERR_NO_MEMORY;
6921         }
6922
6923         for (i = 0; i < vlan_num; i++) {
6924                 mv_f[i].filter_type = filter_type;
6925                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6926                                 ETH_ADDR_LEN);
6927         }
6928         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6929                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6930                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6931                 if (ret != I40E_SUCCESS)
6932                         goto DONE;
6933         }
6934
6935         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6936         if (ret != I40E_SUCCESS)
6937                 goto DONE;
6938
6939         /* Remove the mac addr into mac list */
6940         TAILQ_REMOVE(&vsi->mac_list, f, next);
6941         rte_free(f);
6942         vsi->mac_num--;
6943
6944         ret = I40E_SUCCESS;
6945 DONE:
6946         rte_free(mv_f);
6947         return ret;
6948 }
6949
6950 /* Configure hash enable flags for RSS */
6951 uint64_t
6952 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6953 {
6954         uint64_t hena = 0;
6955         int i;
6956
6957         if (!flags)
6958                 return hena;
6959
6960         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6961                 if (flags & (1ULL << i))
6962                         hena |= adapter->pctypes_tbl[i];
6963         }
6964
6965         return hena;
6966 }
6967
6968 /* Parse the hash enable flags */
6969 uint64_t
6970 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6971 {
6972         uint64_t rss_hf = 0;
6973
6974         if (!flags)
6975                 return rss_hf;
6976         int i;
6977
6978         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6979                 if (flags & adapter->pctypes_tbl[i])
6980                         rss_hf |= (1ULL << i);
6981         }
6982         return rss_hf;
6983 }
6984
6985 /* Disable RSS */
6986 static void
6987 i40e_pf_disable_rss(struct i40e_pf *pf)
6988 {
6989         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6990
6991         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6992         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6993         I40E_WRITE_FLUSH(hw);
6994 }
6995
6996 int
6997 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6998 {
6999         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7000         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7001         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7002                            I40E_VFQF_HKEY_MAX_INDEX :
7003                            I40E_PFQF_HKEY_MAX_INDEX;
7004         int ret = 0;
7005
7006         if (!key || key_len == 0) {
7007                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7008                 return 0;
7009         } else if (key_len != (key_idx + 1) *
7010                 sizeof(uint32_t)) {
7011                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7012                 return -EINVAL;
7013         }
7014
7015         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7016                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7017                         (struct i40e_aqc_get_set_rss_key_data *)key;
7018
7019                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7020                 if (ret)
7021                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7022         } else {
7023                 uint32_t *hash_key = (uint32_t *)key;
7024                 uint16_t i;
7025
7026                 if (vsi->type == I40E_VSI_SRIOV) {
7027                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7028                                 I40E_WRITE_REG(
7029                                         hw,
7030                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7031                                         hash_key[i]);
7032
7033                 } else {
7034                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7035                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7036                                                hash_key[i]);
7037                 }
7038                 I40E_WRITE_FLUSH(hw);
7039         }
7040
7041         return ret;
7042 }
7043
7044 static int
7045 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7046 {
7047         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7048         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7049         uint32_t reg;
7050         int ret;
7051
7052         if (!key || !key_len)
7053                 return -EINVAL;
7054
7055         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7056                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7057                         (struct i40e_aqc_get_set_rss_key_data *)key);
7058                 if (ret) {
7059                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7060                         return ret;
7061                 }
7062         } else {
7063                 uint32_t *key_dw = (uint32_t *)key;
7064                 uint16_t i;
7065
7066                 if (vsi->type == I40E_VSI_SRIOV) {
7067                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7068                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7069                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7070                         }
7071                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7072                                    sizeof(uint32_t);
7073                 } else {
7074                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7075                                 reg = I40E_PFQF_HKEY(i);
7076                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7077                         }
7078                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7079                                    sizeof(uint32_t);
7080                 }
7081         }
7082         return 0;
7083 }
7084
7085 static int
7086 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7087 {
7088         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7089         uint64_t hena;
7090         int ret;
7091
7092         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7093                                rss_conf->rss_key_len);
7094         if (ret)
7095                 return ret;
7096
7097         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7098         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7099         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7100         I40E_WRITE_FLUSH(hw);
7101
7102         return 0;
7103 }
7104
7105 static int
7106 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7107                          struct rte_eth_rss_conf *rss_conf)
7108 {
7109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7112         uint64_t hena;
7113
7114         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7115         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7116
7117         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7118                 if (rss_hf != 0) /* Enable RSS */
7119                         return -EINVAL;
7120                 return 0; /* Nothing to do */
7121         }
7122         /* RSS enabled */
7123         if (rss_hf == 0) /* Disable RSS */
7124                 return -EINVAL;
7125
7126         return i40e_hw_rss_hash_set(pf, rss_conf);
7127 }
7128
7129 static int
7130 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7131                            struct rte_eth_rss_conf *rss_conf)
7132 {
7133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7135         uint64_t hena;
7136
7137         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7138                          &rss_conf->rss_key_len);
7139
7140         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7141         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7142         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7143
7144         return 0;
7145 }
7146
7147 static int
7148 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7149 {
7150         switch (filter_type) {
7151         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7152                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7153                 break;
7154         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7155                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7156                 break;
7157         case RTE_TUNNEL_FILTER_IMAC_TENID:
7158                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7159                 break;
7160         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7161                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7162                 break;
7163         case ETH_TUNNEL_FILTER_IMAC:
7164                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7165                 break;
7166         case ETH_TUNNEL_FILTER_OIP:
7167                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7168                 break;
7169         case ETH_TUNNEL_FILTER_IIP:
7170                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7171                 break;
7172         default:
7173                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7174                 return -EINVAL;
7175         }
7176
7177         return 0;
7178 }
7179
7180 /* Convert tunnel filter structure */
7181 static int
7182 i40e_tunnel_filter_convert(
7183         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7184         struct i40e_tunnel_filter *tunnel_filter)
7185 {
7186         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7187                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7188         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7189                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7190         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7191         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7192              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7193             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7194                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7195         else
7196                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7197         tunnel_filter->input.flags = cld_filter->element.flags;
7198         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7199         tunnel_filter->queue = cld_filter->element.queue_number;
7200         rte_memcpy(tunnel_filter->input.general_fields,
7201                    cld_filter->general_fields,
7202                    sizeof(cld_filter->general_fields));
7203
7204         return 0;
7205 }
7206
7207 /* Check if there exists the tunnel filter */
7208 struct i40e_tunnel_filter *
7209 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7210                              const struct i40e_tunnel_filter_input *input)
7211 {
7212         int ret;
7213
7214         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7215         if (ret < 0)
7216                 return NULL;
7217
7218         return tunnel_rule->hash_map[ret];
7219 }
7220
7221 /* Add a tunnel filter into the SW list */
7222 static int
7223 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7224                              struct i40e_tunnel_filter *tunnel_filter)
7225 {
7226         struct i40e_tunnel_rule *rule = &pf->tunnel;
7227         int ret;
7228
7229         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7230         if (ret < 0) {
7231                 PMD_DRV_LOG(ERR,
7232                             "Failed to insert tunnel filter to hash table %d!",
7233                             ret);
7234                 return ret;
7235         }
7236         rule->hash_map[ret] = tunnel_filter;
7237
7238         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7239
7240         return 0;
7241 }
7242
7243 /* Delete a tunnel filter from the SW list */
7244 int
7245 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7246                           struct i40e_tunnel_filter_input *input)
7247 {
7248         struct i40e_tunnel_rule *rule = &pf->tunnel;
7249         struct i40e_tunnel_filter *tunnel_filter;
7250         int ret;
7251
7252         ret = rte_hash_del_key(rule->hash_table, input);
7253         if (ret < 0) {
7254                 PMD_DRV_LOG(ERR,
7255                             "Failed to delete tunnel filter to hash table %d!",
7256                             ret);
7257                 return ret;
7258         }
7259         tunnel_filter = rule->hash_map[ret];
7260         rule->hash_map[ret] = NULL;
7261
7262         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7263         rte_free(tunnel_filter);
7264
7265         return 0;
7266 }
7267
7268 int
7269 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7270                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7271                         uint8_t add)
7272 {
7273         uint16_t ip_type;
7274         uint32_t ipv4_addr, ipv4_addr_le;
7275         uint8_t i, tun_type = 0;
7276         /* internal varialbe to convert ipv6 byte order */
7277         uint32_t convert_ipv6[4];
7278         int val, ret = 0;
7279         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7280         struct i40e_vsi *vsi = pf->main_vsi;
7281         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7282         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7283         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7284         struct i40e_tunnel_filter *tunnel, *node;
7285         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7286
7287         cld_filter = rte_zmalloc("tunnel_filter",
7288                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7289         0);
7290
7291         if (NULL == cld_filter) {
7292                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7293                 return -ENOMEM;
7294         }
7295         pfilter = cld_filter;
7296
7297         ether_addr_copy(&tunnel_filter->outer_mac,
7298                         (struct ether_addr *)&pfilter->element.outer_mac);
7299         ether_addr_copy(&tunnel_filter->inner_mac,
7300                         (struct ether_addr *)&pfilter->element.inner_mac);
7301
7302         pfilter->element.inner_vlan =
7303                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7304         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7305                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7306                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7307                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7308                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7309                                 &ipv4_addr_le,
7310                                 sizeof(pfilter->element.ipaddr.v4.data));
7311         } else {
7312                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7313                 for (i = 0; i < 4; i++) {
7314                         convert_ipv6[i] =
7315                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7316                 }
7317                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7318                            &convert_ipv6,
7319                            sizeof(pfilter->element.ipaddr.v6.data));
7320         }
7321
7322         /* check tunneled type */
7323         switch (tunnel_filter->tunnel_type) {
7324         case RTE_TUNNEL_TYPE_VXLAN:
7325                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7326                 break;
7327         case RTE_TUNNEL_TYPE_NVGRE:
7328                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7329                 break;
7330         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7331                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7332                 break;
7333         default:
7334                 /* Other tunnel types is not supported. */
7335                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7336                 rte_free(cld_filter);
7337                 return -EINVAL;
7338         }
7339
7340         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7341                                        &pfilter->element.flags);
7342         if (val < 0) {
7343                 rte_free(cld_filter);
7344                 return -EINVAL;
7345         }
7346
7347         pfilter->element.flags |= rte_cpu_to_le_16(
7348                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7349                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7350         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7351         pfilter->element.queue_number =
7352                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7353
7354         /* Check if there is the filter in SW list */
7355         memset(&check_filter, 0, sizeof(check_filter));
7356         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7357         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7358         if (add && node) {
7359                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7360                 rte_free(cld_filter);
7361                 return -EINVAL;
7362         }
7363
7364         if (!add && !node) {
7365                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7366                 rte_free(cld_filter);
7367                 return -EINVAL;
7368         }
7369
7370         if (add) {
7371                 ret = i40e_aq_add_cloud_filters(hw,
7372                                         vsi->seid, &cld_filter->element, 1);
7373                 if (ret < 0) {
7374                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7375                         rte_free(cld_filter);
7376                         return -ENOTSUP;
7377                 }
7378                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7379                 if (tunnel == NULL) {
7380                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7381                         rte_free(cld_filter);
7382                         return -ENOMEM;
7383                 }
7384
7385                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7386                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7387                 if (ret < 0)
7388                         rte_free(tunnel);
7389         } else {
7390                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7391                                                    &cld_filter->element, 1);
7392                 if (ret < 0) {
7393                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7394                         rte_free(cld_filter);
7395                         return -ENOTSUP;
7396                 }
7397                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7398         }
7399
7400         rte_free(cld_filter);
7401         return ret;
7402 }
7403
7404 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7405 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7406 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7407 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7408 #define I40E_TR_GRE_KEY_MASK                    0x400
7409 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7410 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7411
7412 static enum
7413 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7414 {
7415         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7416         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7418         enum i40e_status_code status = I40E_SUCCESS;
7419
7420         if (pf->support_multi_driver) {
7421                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7422                 return I40E_NOT_SUPPORTED;
7423         }
7424
7425         memset(&filter_replace, 0,
7426                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7427         memset(&filter_replace_buf, 0,
7428                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7429
7430         /* create L1 filter */
7431         filter_replace.old_filter_type =
7432                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7433         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7434         filter_replace.tr_bit = 0;
7435
7436         /* Prepare the buffer, 3 entries */
7437         filter_replace_buf.data[0] =
7438                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7439         filter_replace_buf.data[0] |=
7440                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7441         filter_replace_buf.data[2] = 0xFF;
7442         filter_replace_buf.data[3] = 0xFF;
7443         filter_replace_buf.data[4] =
7444                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7445         filter_replace_buf.data[4] |=
7446                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7447         filter_replace_buf.data[7] = 0xF0;
7448         filter_replace_buf.data[8]
7449                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7450         filter_replace_buf.data[8] |=
7451                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7452         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7453                 I40E_TR_GENEVE_KEY_MASK |
7454                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7455         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7456                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7457                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7458
7459         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7460                                                &filter_replace_buf);
7461         if (!status) {
7462                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7463                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7464                             "cloud l1 type is changed from 0x%x to 0x%x",
7465                             filter_replace.old_filter_type,
7466                             filter_replace.new_filter_type);
7467         }
7468         return status;
7469 }
7470
7471 static enum
7472 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7473 {
7474         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7475         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7476         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7477         enum i40e_status_code status = I40E_SUCCESS;
7478
7479         if (pf->support_multi_driver) {
7480                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7481                 return I40E_NOT_SUPPORTED;
7482         }
7483
7484         /* For MPLSoUDP */
7485         memset(&filter_replace, 0,
7486                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7487         memset(&filter_replace_buf, 0,
7488                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7489         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7490                 I40E_AQC_MIRROR_CLOUD_FILTER;
7491         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7492         filter_replace.new_filter_type =
7493                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7494         /* Prepare the buffer, 2 entries */
7495         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7496         filter_replace_buf.data[0] |=
7497                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7498         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7499         filter_replace_buf.data[4] |=
7500                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7501         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7502                                                &filter_replace_buf);
7503         if (status < 0)
7504                 return status;
7505         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7506                     "cloud filter type is changed from 0x%x to 0x%x",
7507                     filter_replace.old_filter_type,
7508                     filter_replace.new_filter_type);
7509
7510         /* For MPLSoGRE */
7511         memset(&filter_replace, 0,
7512                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7513         memset(&filter_replace_buf, 0,
7514                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7515
7516         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7517                 I40E_AQC_MIRROR_CLOUD_FILTER;
7518         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7519         filter_replace.new_filter_type =
7520                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7521         /* Prepare the buffer, 2 entries */
7522         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7523         filter_replace_buf.data[0] |=
7524                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7525         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7526         filter_replace_buf.data[4] |=
7527                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7528
7529         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7530                                                &filter_replace_buf);
7531         if (!status) {
7532                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7533                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7534                             "cloud filter type is changed from 0x%x to 0x%x",
7535                             filter_replace.old_filter_type,
7536                             filter_replace.new_filter_type);
7537         }
7538         return status;
7539 }
7540
7541 static enum i40e_status_code
7542 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7543 {
7544         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7545         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7546         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7547         enum i40e_status_code status = I40E_SUCCESS;
7548
7549         if (pf->support_multi_driver) {
7550                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7551                 return I40E_NOT_SUPPORTED;
7552         }
7553
7554         /* For GTP-C */
7555         memset(&filter_replace, 0,
7556                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7557         memset(&filter_replace_buf, 0,
7558                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7559         /* create L1 filter */
7560         filter_replace.old_filter_type =
7561                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7562         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7563         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7564                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7565         /* Prepare the buffer, 2 entries */
7566         filter_replace_buf.data[0] =
7567                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7568         filter_replace_buf.data[0] |=
7569                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7570         filter_replace_buf.data[2] = 0xFF;
7571         filter_replace_buf.data[3] = 0xFF;
7572         filter_replace_buf.data[4] =
7573                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7574         filter_replace_buf.data[4] |=
7575                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7576         filter_replace_buf.data[6] = 0xFF;
7577         filter_replace_buf.data[7] = 0xFF;
7578         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7579                                                &filter_replace_buf);
7580         if (status < 0)
7581                 return status;
7582         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7583                     "cloud l1 type is changed from 0x%x to 0x%x",
7584                     filter_replace.old_filter_type,
7585                     filter_replace.new_filter_type);
7586
7587         /* for GTP-U */
7588         memset(&filter_replace, 0,
7589                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7590         memset(&filter_replace_buf, 0,
7591                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7592         /* create L1 filter */
7593         filter_replace.old_filter_type =
7594                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7595         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7596         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7597                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7598         /* Prepare the buffer, 2 entries */
7599         filter_replace_buf.data[0] =
7600                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7601         filter_replace_buf.data[0] |=
7602                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7603         filter_replace_buf.data[2] = 0xFF;
7604         filter_replace_buf.data[3] = 0xFF;
7605         filter_replace_buf.data[4] =
7606                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7607         filter_replace_buf.data[4] |=
7608                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7609         filter_replace_buf.data[6] = 0xFF;
7610         filter_replace_buf.data[7] = 0xFF;
7611
7612         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7613                                                &filter_replace_buf);
7614         if (!status) {
7615                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7616                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7617                             "cloud l1 type is changed from 0x%x to 0x%x",
7618                             filter_replace.old_filter_type,
7619                             filter_replace.new_filter_type);
7620         }
7621         return status;
7622 }
7623
7624 static enum
7625 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7626 {
7627         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7628         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7629         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7630         enum i40e_status_code status = I40E_SUCCESS;
7631
7632         if (pf->support_multi_driver) {
7633                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7634                 return I40E_NOT_SUPPORTED;
7635         }
7636
7637         /* for GTP-C */
7638         memset(&filter_replace, 0,
7639                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7640         memset(&filter_replace_buf, 0,
7641                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7642         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7643         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7644         filter_replace.new_filter_type =
7645                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7646         /* Prepare the buffer, 2 entries */
7647         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7648         filter_replace_buf.data[0] |=
7649                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7650         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7651         filter_replace_buf.data[4] |=
7652                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7653         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7654                                                &filter_replace_buf);
7655         if (status < 0)
7656                 return status;
7657         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7658                     "cloud filter type is changed from 0x%x to 0x%x",
7659                     filter_replace.old_filter_type,
7660                     filter_replace.new_filter_type);
7661
7662         /* for GTP-U */
7663         memset(&filter_replace, 0,
7664                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7665         memset(&filter_replace_buf, 0,
7666                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7667         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7668         filter_replace.old_filter_type =
7669                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7670         filter_replace.new_filter_type =
7671                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7672         /* Prepare the buffer, 2 entries */
7673         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7674         filter_replace_buf.data[0] |=
7675                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7676         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7677         filter_replace_buf.data[4] |=
7678                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7679
7680         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7681                                                &filter_replace_buf);
7682         if (!status) {
7683                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7684                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7685                             "cloud filter type is changed from 0x%x to 0x%x",
7686                             filter_replace.old_filter_type,
7687                             filter_replace.new_filter_type);
7688         }
7689         return status;
7690 }
7691
7692 int
7693 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7694                       struct i40e_tunnel_filter_conf *tunnel_filter,
7695                       uint8_t add)
7696 {
7697         uint16_t ip_type;
7698         uint32_t ipv4_addr, ipv4_addr_le;
7699         uint8_t i, tun_type = 0;
7700         /* internal variable to convert ipv6 byte order */
7701         uint32_t convert_ipv6[4];
7702         int val, ret = 0;
7703         struct i40e_pf_vf *vf = NULL;
7704         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7705         struct i40e_vsi *vsi;
7706         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7707         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7708         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7709         struct i40e_tunnel_filter *tunnel, *node;
7710         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7711         uint32_t teid_le;
7712         bool big_buffer = 0;
7713
7714         cld_filter = rte_zmalloc("tunnel_filter",
7715                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7716                          0);
7717
7718         if (cld_filter == NULL) {
7719                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7720                 return -ENOMEM;
7721         }
7722         pfilter = cld_filter;
7723
7724         ether_addr_copy(&tunnel_filter->outer_mac,
7725                         (struct ether_addr *)&pfilter->element.outer_mac);
7726         ether_addr_copy(&tunnel_filter->inner_mac,
7727                         (struct ether_addr *)&pfilter->element.inner_mac);
7728
7729         pfilter->element.inner_vlan =
7730                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7731         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7732                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7733                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7734                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7735                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7736                                 &ipv4_addr_le,
7737                                 sizeof(pfilter->element.ipaddr.v4.data));
7738         } else {
7739                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7740                 for (i = 0; i < 4; i++) {
7741                         convert_ipv6[i] =
7742                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7743                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7744                 }
7745                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7746                            &convert_ipv6,
7747                            sizeof(pfilter->element.ipaddr.v6.data));
7748         }
7749
7750         /* check tunneled type */
7751         switch (tunnel_filter->tunnel_type) {
7752         case I40E_TUNNEL_TYPE_VXLAN:
7753                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7754                 break;
7755         case I40E_TUNNEL_TYPE_NVGRE:
7756                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7757                 break;
7758         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7759                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7760                 break;
7761         case I40E_TUNNEL_TYPE_MPLSoUDP:
7762                 if (!pf->mpls_replace_flag) {
7763                         i40e_replace_mpls_l1_filter(pf);
7764                         i40e_replace_mpls_cloud_filter(pf);
7765                         pf->mpls_replace_flag = 1;
7766                 }
7767                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7768                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7769                         teid_le >> 4;
7770                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7771                         (teid_le & 0xF) << 12;
7772                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7773                         0x40;
7774                 big_buffer = 1;
7775                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7776                 break;
7777         case I40E_TUNNEL_TYPE_MPLSoGRE:
7778                 if (!pf->mpls_replace_flag) {
7779                         i40e_replace_mpls_l1_filter(pf);
7780                         i40e_replace_mpls_cloud_filter(pf);
7781                         pf->mpls_replace_flag = 1;
7782                 }
7783                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7784                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7785                         teid_le >> 4;
7786                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7787                         (teid_le & 0xF) << 12;
7788                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7789                         0x0;
7790                 big_buffer = 1;
7791                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7792                 break;
7793         case I40E_TUNNEL_TYPE_GTPC:
7794                 if (!pf->gtp_replace_flag) {
7795                         i40e_replace_gtp_l1_filter(pf);
7796                         i40e_replace_gtp_cloud_filter(pf);
7797                         pf->gtp_replace_flag = 1;
7798                 }
7799                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7800                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7801                         (teid_le >> 16) & 0xFFFF;
7802                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7803                         teid_le & 0xFFFF;
7804                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7805                         0x0;
7806                 big_buffer = 1;
7807                 break;
7808         case I40E_TUNNEL_TYPE_GTPU:
7809                 if (!pf->gtp_replace_flag) {
7810                         i40e_replace_gtp_l1_filter(pf);
7811                         i40e_replace_gtp_cloud_filter(pf);
7812                         pf->gtp_replace_flag = 1;
7813                 }
7814                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7815                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7816                         (teid_le >> 16) & 0xFFFF;
7817                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7818                         teid_le & 0xFFFF;
7819                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7820                         0x0;
7821                 big_buffer = 1;
7822                 break;
7823         case I40E_TUNNEL_TYPE_QINQ:
7824                 if (!pf->qinq_replace_flag) {
7825                         ret = i40e_cloud_filter_qinq_create(pf);
7826                         if (ret < 0)
7827                                 PMD_DRV_LOG(DEBUG,
7828                                             "QinQ tunnel filter already created.");
7829                         pf->qinq_replace_flag = 1;
7830                 }
7831                 /*      Add in the General fields the values of
7832                  *      the Outer and Inner VLAN
7833                  *      Big Buffer should be set, see changes in
7834                  *      i40e_aq_add_cloud_filters
7835                  */
7836                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7837                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7838                 big_buffer = 1;
7839                 break;
7840         default:
7841                 /* Other tunnel types is not supported. */
7842                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7843                 rte_free(cld_filter);
7844                 return -EINVAL;
7845         }
7846
7847         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7848                 pfilter->element.flags =
7849                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7850         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7851                 pfilter->element.flags =
7852                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7853         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7854                 pfilter->element.flags =
7855                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7856         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7857                 pfilter->element.flags =
7858                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7859         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7860                 pfilter->element.flags |=
7861                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7862         else {
7863                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7864                                                 &pfilter->element.flags);
7865                 if (val < 0) {
7866                         rte_free(cld_filter);
7867                         return -EINVAL;
7868                 }
7869         }
7870
7871         pfilter->element.flags |= rte_cpu_to_le_16(
7872                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7873                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7874         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7875         pfilter->element.queue_number =
7876                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7877
7878         if (!tunnel_filter->is_to_vf)
7879                 vsi = pf->main_vsi;
7880         else {
7881                 if (tunnel_filter->vf_id >= pf->vf_num) {
7882                         PMD_DRV_LOG(ERR, "Invalid argument.");
7883                         rte_free(cld_filter);
7884                         return -EINVAL;
7885                 }
7886                 vf = &pf->vfs[tunnel_filter->vf_id];
7887                 vsi = vf->vsi;
7888         }
7889
7890         /* Check if there is the filter in SW list */
7891         memset(&check_filter, 0, sizeof(check_filter));
7892         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7893         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7894         check_filter.vf_id = tunnel_filter->vf_id;
7895         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7896         if (add && node) {
7897                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7898                 rte_free(cld_filter);
7899                 return -EINVAL;
7900         }
7901
7902         if (!add && !node) {
7903                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7904                 rte_free(cld_filter);
7905                 return -EINVAL;
7906         }
7907
7908         if (add) {
7909                 if (big_buffer)
7910                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7911                                                    vsi->seid, cld_filter, 1);
7912                 else
7913                         ret = i40e_aq_add_cloud_filters(hw,
7914                                         vsi->seid, &cld_filter->element, 1);
7915                 if (ret < 0) {
7916                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7917                         rte_free(cld_filter);
7918                         return -ENOTSUP;
7919                 }
7920                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7921                 if (tunnel == NULL) {
7922                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7923                         rte_free(cld_filter);
7924                         return -ENOMEM;
7925                 }
7926
7927                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7928                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7929                 if (ret < 0)
7930                         rte_free(tunnel);
7931         } else {
7932                 if (big_buffer)
7933                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7934                                 hw, vsi->seid, cld_filter, 1);
7935                 else
7936                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7937                                                    &cld_filter->element, 1);
7938                 if (ret < 0) {
7939                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7940                         rte_free(cld_filter);
7941                         return -ENOTSUP;
7942                 }
7943                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7944         }
7945
7946         rte_free(cld_filter);
7947         return ret;
7948 }
7949
7950 static int
7951 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7952 {
7953         uint8_t i;
7954
7955         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7956                 if (pf->vxlan_ports[i] == port)
7957                         return i;
7958         }
7959
7960         return -1;
7961 }
7962
7963 static int
7964 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7965 {
7966         int  idx, ret;
7967         uint8_t filter_idx;
7968         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7969
7970         idx = i40e_get_vxlan_port_idx(pf, port);
7971
7972         /* Check if port already exists */
7973         if (idx >= 0) {
7974                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7975                 return -EINVAL;
7976         }
7977
7978         /* Now check if there is space to add the new port */
7979         idx = i40e_get_vxlan_port_idx(pf, 0);
7980         if (idx < 0) {
7981                 PMD_DRV_LOG(ERR,
7982                         "Maximum number of UDP ports reached, not adding port %d",
7983                         port);
7984                 return -ENOSPC;
7985         }
7986
7987         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7988                                         &filter_idx, NULL);
7989         if (ret < 0) {
7990                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7991                 return -1;
7992         }
7993
7994         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7995                          port,  filter_idx);
7996
7997         /* New port: add it and mark its index in the bitmap */
7998         pf->vxlan_ports[idx] = port;
7999         pf->vxlan_bitmap |= (1 << idx);
8000
8001         if (!(pf->flags & I40E_FLAG_VXLAN))
8002                 pf->flags |= I40E_FLAG_VXLAN;
8003
8004         return 0;
8005 }
8006
8007 static int
8008 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8009 {
8010         int idx;
8011         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8012
8013         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8014                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8015                 return -EINVAL;
8016         }
8017
8018         idx = i40e_get_vxlan_port_idx(pf, port);
8019
8020         if (idx < 0) {
8021                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8022                 return -EINVAL;
8023         }
8024
8025         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8026                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8027                 return -1;
8028         }
8029
8030         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8031                         port, idx);
8032
8033         pf->vxlan_ports[idx] = 0;
8034         pf->vxlan_bitmap &= ~(1 << idx);
8035
8036         if (!pf->vxlan_bitmap)
8037                 pf->flags &= ~I40E_FLAG_VXLAN;
8038
8039         return 0;
8040 }
8041
8042 /* Add UDP tunneling port */
8043 static int
8044 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8045                              struct rte_eth_udp_tunnel *udp_tunnel)
8046 {
8047         int ret = 0;
8048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8049
8050         if (udp_tunnel == NULL)
8051                 return -EINVAL;
8052
8053         switch (udp_tunnel->prot_type) {
8054         case RTE_TUNNEL_TYPE_VXLAN:
8055                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8056                 break;
8057
8058         case RTE_TUNNEL_TYPE_GENEVE:
8059         case RTE_TUNNEL_TYPE_TEREDO:
8060                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8061                 ret = -1;
8062                 break;
8063
8064         default:
8065                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8066                 ret = -1;
8067                 break;
8068         }
8069
8070         return ret;
8071 }
8072
8073 /* Remove UDP tunneling port */
8074 static int
8075 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8076                              struct rte_eth_udp_tunnel *udp_tunnel)
8077 {
8078         int ret = 0;
8079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8080
8081         if (udp_tunnel == NULL)
8082                 return -EINVAL;
8083
8084         switch (udp_tunnel->prot_type) {
8085         case RTE_TUNNEL_TYPE_VXLAN:
8086                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8087                 break;
8088         case RTE_TUNNEL_TYPE_GENEVE:
8089         case RTE_TUNNEL_TYPE_TEREDO:
8090                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8091                 ret = -1;
8092                 break;
8093         default:
8094                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8095                 ret = -1;
8096                 break;
8097         }
8098
8099         return ret;
8100 }
8101
8102 /* Calculate the maximum number of contiguous PF queues that are configured */
8103 static int
8104 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8105 {
8106         struct rte_eth_dev_data *data = pf->dev_data;
8107         int i, num;
8108         struct i40e_rx_queue *rxq;
8109
8110         num = 0;
8111         for (i = 0; i < pf->lan_nb_qps; i++) {
8112                 rxq = data->rx_queues[i];
8113                 if (rxq && rxq->q_set)
8114                         num++;
8115                 else
8116                         break;
8117         }
8118
8119         return num;
8120 }
8121
8122 /* Configure RSS */
8123 static int
8124 i40e_pf_config_rss(struct i40e_pf *pf)
8125 {
8126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8127         struct rte_eth_rss_conf rss_conf;
8128         uint32_t i, lut = 0;
8129         uint16_t j, num;
8130
8131         /*
8132          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8133          * It's necessary to calculate the actual PF queues that are configured.
8134          */
8135         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8136                 num = i40e_pf_calc_configured_queues_num(pf);
8137         else
8138                 num = pf->dev_data->nb_rx_queues;
8139
8140         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8141         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8142                         num);
8143
8144         if (num == 0) {
8145                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8146                 return -ENOTSUP;
8147         }
8148
8149         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8150                 if (j == num)
8151                         j = 0;
8152                 lut = (lut << 8) | (j & ((0x1 <<
8153                         hw->func_caps.rss_table_entry_width) - 1));
8154                 if ((i & 3) == 3)
8155                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8156         }
8157
8158         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8159         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8160                 i40e_pf_disable_rss(pf);
8161                 return 0;
8162         }
8163         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8164                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8165                 /* Random default keys */
8166                 static uint32_t rss_key_default[] = {0x6b793944,
8167                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8168                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8169                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8170
8171                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8172                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8173                                                         sizeof(uint32_t);
8174         }
8175
8176         return i40e_hw_rss_hash_set(pf, &rss_conf);
8177 }
8178
8179 static int
8180 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8181                                struct rte_eth_tunnel_filter_conf *filter)
8182 {
8183         if (pf == NULL || filter == NULL) {
8184                 PMD_DRV_LOG(ERR, "Invalid parameter");
8185                 return -EINVAL;
8186         }
8187
8188         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8189                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8190                 return -EINVAL;
8191         }
8192
8193         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8194                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8195                 return -EINVAL;
8196         }
8197
8198         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8199                 (is_zero_ether_addr(&filter->outer_mac))) {
8200                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8201                 return -EINVAL;
8202         }
8203
8204         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8205                 (is_zero_ether_addr(&filter->inner_mac))) {
8206                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8207                 return -EINVAL;
8208         }
8209
8210         return 0;
8211 }
8212
8213 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8214 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8215 static int
8216 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8217 {
8218         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8219         uint32_t val, reg;
8220         int ret = -EINVAL;
8221
8222         if (pf->support_multi_driver) {
8223                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8224                 return -ENOTSUP;
8225         }
8226
8227         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8228         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8229
8230         if (len == 3) {
8231                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8232         } else if (len == 4) {
8233                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8234         } else {
8235                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8236                 return ret;
8237         }
8238
8239         if (reg != val) {
8240                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8241                                                    reg, NULL);
8242                 if (ret != 0)
8243                         return ret;
8244                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8245                             "with value 0x%08x",
8246                             I40E_GL_PRS_FVBM(2), reg);
8247                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8248         } else {
8249                 ret = 0;
8250         }
8251         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8252                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8253
8254         return ret;
8255 }
8256
8257 static int
8258 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8259 {
8260         int ret = -EINVAL;
8261
8262         if (!hw || !cfg)
8263                 return -EINVAL;
8264
8265         switch (cfg->cfg_type) {
8266         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8267                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8268                 break;
8269         default:
8270                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8271                 break;
8272         }
8273
8274         return ret;
8275 }
8276
8277 static int
8278 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8279                                enum rte_filter_op filter_op,
8280                                void *arg)
8281 {
8282         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8283         int ret = I40E_ERR_PARAM;
8284
8285         switch (filter_op) {
8286         case RTE_ETH_FILTER_SET:
8287                 ret = i40e_dev_global_config_set(hw,
8288                         (struct rte_eth_global_cfg *)arg);
8289                 break;
8290         default:
8291                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8292                 break;
8293         }
8294
8295         return ret;
8296 }
8297
8298 static int
8299 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8300                           enum rte_filter_op filter_op,
8301                           void *arg)
8302 {
8303         struct rte_eth_tunnel_filter_conf *filter;
8304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8305         int ret = I40E_SUCCESS;
8306
8307         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8308
8309         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8310                 return I40E_ERR_PARAM;
8311
8312         switch (filter_op) {
8313         case RTE_ETH_FILTER_NOP:
8314                 if (!(pf->flags & I40E_FLAG_VXLAN))
8315                         ret = I40E_NOT_SUPPORTED;
8316                 break;
8317         case RTE_ETH_FILTER_ADD:
8318                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8319                 break;
8320         case RTE_ETH_FILTER_DELETE:
8321                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8322                 break;
8323         default:
8324                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8325                 ret = I40E_ERR_PARAM;
8326                 break;
8327         }
8328
8329         return ret;
8330 }
8331
8332 static int
8333 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8334 {
8335         int ret = 0;
8336         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8337
8338         /* RSS setup */
8339         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8340                 ret = i40e_pf_config_rss(pf);
8341         else
8342                 i40e_pf_disable_rss(pf);
8343
8344         return ret;
8345 }
8346
8347 /* Get the symmetric hash enable configurations per port */
8348 static void
8349 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8350 {
8351         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8352
8353         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8354 }
8355
8356 /* Set the symmetric hash enable configurations per port */
8357 static void
8358 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8359 {
8360         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8361
8362         if (enable > 0) {
8363                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8364                         PMD_DRV_LOG(INFO,
8365                                 "Symmetric hash has already been enabled");
8366                         return;
8367                 }
8368                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8369         } else {
8370                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8371                         PMD_DRV_LOG(INFO,
8372                                 "Symmetric hash has already been disabled");
8373                         return;
8374                 }
8375                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8376         }
8377         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8378         I40E_WRITE_FLUSH(hw);
8379 }
8380
8381 /*
8382  * Get global configurations of hash function type and symmetric hash enable
8383  * per flow type (pctype). Note that global configuration means it affects all
8384  * the ports on the same NIC.
8385  */
8386 static int
8387 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8388                                    struct rte_eth_hash_global_conf *g_cfg)
8389 {
8390         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8391         uint32_t reg;
8392         uint16_t i, j;
8393
8394         memset(g_cfg, 0, sizeof(*g_cfg));
8395         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8396         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8397                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8398         else
8399                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8400         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8401                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8402
8403         /*
8404          * As i40e supports less than 64 flow types, only first 64 bits need to
8405          * be checked.
8406          */
8407         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8408                 g_cfg->valid_bit_mask[i] = 0ULL;
8409                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8410         }
8411
8412         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8413
8414         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8415                 if (!adapter->pctypes_tbl[i])
8416                         continue;
8417                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8418                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8419                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8420                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8421                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8422                                         g_cfg->sym_hash_enable_mask[0] |=
8423                                                                 (1ULL << i);
8424                                 }
8425                         }
8426                 }
8427         }
8428
8429         return 0;
8430 }
8431
8432 static int
8433 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8434                               const struct rte_eth_hash_global_conf *g_cfg)
8435 {
8436         uint32_t i;
8437         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8438
8439         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8440                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8441                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8442                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8443                                                 g_cfg->hash_func);
8444                 return -EINVAL;
8445         }
8446
8447         /*
8448          * As i40e supports less than 64 flow types, only first 64 bits need to
8449          * be checked.
8450          */
8451         mask0 = g_cfg->valid_bit_mask[0];
8452         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8453                 if (i == 0) {
8454                         /* Check if any unsupported flow type configured */
8455                         if ((mask0 | i40e_mask) ^ i40e_mask)
8456                                 goto mask_err;
8457                 } else {
8458                         if (g_cfg->valid_bit_mask[i])
8459                                 goto mask_err;
8460                 }
8461         }
8462
8463         return 0;
8464
8465 mask_err:
8466         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8467
8468         return -EINVAL;
8469 }
8470
8471 /*
8472  * Set global configurations of hash function type and symmetric hash enable
8473  * per flow type (pctype). Note any modifying global configuration will affect
8474  * all the ports on the same NIC.
8475  */
8476 static int
8477 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8478                                    struct rte_eth_hash_global_conf *g_cfg)
8479 {
8480         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8481         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8482         int ret;
8483         uint16_t i, j;
8484         uint32_t reg;
8485         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8486
8487         if (pf->support_multi_driver) {
8488                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8489                 return -ENOTSUP;
8490         }
8491
8492         /* Check the input parameters */
8493         ret = i40e_hash_global_config_check(adapter, g_cfg);
8494         if (ret < 0)
8495                 return ret;
8496
8497         /*
8498          * As i40e supports less than 64 flow types, only first 64 bits need to
8499          * be configured.
8500          */
8501         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8502                 if (mask0 & (1UL << i)) {
8503                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8504                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8505
8506                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8507                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8508                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8509                                         i40e_write_global_rx_ctl(hw,
8510                                                           I40E_GLQF_HSYM(j),
8511                                                           reg);
8512                         }
8513                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8514                 }
8515         }
8516
8517         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8518         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8519                 /* Toeplitz */
8520                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8521                         PMD_DRV_LOG(DEBUG,
8522                                 "Hash function already set to Toeplitz");
8523                         goto out;
8524                 }
8525                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8526         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8527                 /* Simple XOR */
8528                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8529                         PMD_DRV_LOG(DEBUG,
8530                                 "Hash function already set to Simple XOR");
8531                         goto out;
8532                 }
8533                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8534         } else
8535                 /* Use the default, and keep it as it is */
8536                 goto out;
8537
8538         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8539         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8540
8541 out:
8542         I40E_WRITE_FLUSH(hw);
8543
8544         return 0;
8545 }
8546
8547 /**
8548  * Valid input sets for hash and flow director filters per PCTYPE
8549  */
8550 static uint64_t
8551 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8552                 enum rte_filter_type filter)
8553 {
8554         uint64_t valid;
8555
8556         static const uint64_t valid_hash_inset_table[] = {
8557                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8558                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8559                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8560                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8561                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8562                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8563                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8564                         I40E_INSET_FLEX_PAYLOAD,
8565                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8569                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8570                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8571                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8572                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8573                         I40E_INSET_FLEX_PAYLOAD,
8574                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8578                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8579                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8580                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8581                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8582                         I40E_INSET_FLEX_PAYLOAD,
8583                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8584                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8585                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8586                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8587                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8588                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8589                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8590                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8591                         I40E_INSET_FLEX_PAYLOAD,
8592                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8596                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8597                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8598                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8599                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8600                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8601                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8605                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8606                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8607                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8608                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8609                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8610                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8611                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8612                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8613                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8614                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8615                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8616                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8618                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8619                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8620                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8621                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8622                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8623                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8624                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8625                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8626                         I40E_INSET_FLEX_PAYLOAD,
8627                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8628                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8629                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8630                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8631                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8632                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8633                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8634                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8635                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8636                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8637                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8638                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8639                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8640                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8641                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8642                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8643                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8644                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8645                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8646                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8647                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8648                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8649                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8650                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8651                         I40E_INSET_FLEX_PAYLOAD,
8652                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8653                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8654                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8655                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8656                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8657                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8658                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8659                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8660                         I40E_INSET_FLEX_PAYLOAD,
8661                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8662                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8663                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8664                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8665                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8666                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8667                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8668                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8669                         I40E_INSET_FLEX_PAYLOAD,
8670                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8671                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8672                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8673                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8674                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8675                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8676                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8677                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8678                         I40E_INSET_FLEX_PAYLOAD,
8679                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8680                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8681                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8682                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8683                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8684                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8685                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8686                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8687                         I40E_INSET_FLEX_PAYLOAD,
8688                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8689                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8690                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8691                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8692                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8693                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8694                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8695                         I40E_INSET_FLEX_PAYLOAD,
8696                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8697                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8698                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8699                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8700                         I40E_INSET_FLEX_PAYLOAD,
8701         };
8702
8703         /**
8704          * Flow director supports only fields defined in
8705          * union rte_eth_fdir_flow.
8706          */
8707         static const uint64_t valid_fdir_inset_table[] = {
8708                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8709                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8710                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8711                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8712                 I40E_INSET_IPV4_TTL,
8713                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8714                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8715                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8716                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8717                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8718                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8719                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8720                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8721                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8722                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8723                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8724                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8725                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8726                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8727                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8728                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8729                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8730                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8731                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8732                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8733                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8734                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8735                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8736                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8737                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8738                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8739                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8740                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8741                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8742                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8743                 I40E_INSET_SCTP_VT,
8744                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8745                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8746                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8747                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8748                 I40E_INSET_IPV4_TTL,
8749                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8750                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8751                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8752                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8753                 I40E_INSET_IPV6_HOP_LIMIT,
8754                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8755                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8756                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8757                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8758                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8759                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8760                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8761                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8762                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8763                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8764                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8765                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8766                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8767                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8768                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8769                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8770                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8771                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8772                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8773                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8774                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8775                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8776                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8777                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8778                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8779                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8780                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8781                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8782                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8783                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8784                 I40E_INSET_SCTP_VT,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8786                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8787                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8788                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8789                 I40E_INSET_IPV6_HOP_LIMIT,
8790                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8791                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8792                 I40E_INSET_LAST_ETHER_TYPE,
8793         };
8794
8795         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8796                 return 0;
8797         if (filter == RTE_ETH_FILTER_HASH)
8798                 valid = valid_hash_inset_table[pctype];
8799         else
8800                 valid = valid_fdir_inset_table[pctype];
8801
8802         return valid;
8803 }
8804
8805 /**
8806  * Validate if the input set is allowed for a specific PCTYPE
8807  */
8808 int
8809 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8810                 enum rte_filter_type filter, uint64_t inset)
8811 {
8812         uint64_t valid;
8813
8814         valid = i40e_get_valid_input_set(pctype, filter);
8815         if (inset & (~valid))
8816                 return -EINVAL;
8817
8818         return 0;
8819 }
8820
8821 /* default input set fields combination per pctype */
8822 uint64_t
8823 i40e_get_default_input_set(uint16_t pctype)
8824 {
8825         static const uint64_t default_inset_table[] = {
8826                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8827                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8828                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8829                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8830                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8831                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8832                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8833                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8834                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8835                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8836                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8837                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8838                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8839                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8840                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8841                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8842                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8843                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8844                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8845                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8846                         I40E_INSET_SCTP_VT,
8847                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8848                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8849                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8850                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8851                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8852                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8853                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8854                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8855                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8856                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8857                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8858                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8859                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8860                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8861                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8862                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8863                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8864                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8865                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8866                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8867                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8868                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8869                         I40E_INSET_SCTP_VT,
8870                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8871                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8872                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8873                         I40E_INSET_LAST_ETHER_TYPE,
8874         };
8875
8876         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8877                 return 0;
8878
8879         return default_inset_table[pctype];
8880 }
8881
8882 /**
8883  * Parse the input set from index to logical bit masks
8884  */
8885 static int
8886 i40e_parse_input_set(uint64_t *inset,
8887                      enum i40e_filter_pctype pctype,
8888                      enum rte_eth_input_set_field *field,
8889                      uint16_t size)
8890 {
8891         uint16_t i, j;
8892         int ret = -EINVAL;
8893
8894         static const struct {
8895                 enum rte_eth_input_set_field field;
8896                 uint64_t inset;
8897         } inset_convert_table[] = {
8898                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8899                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8900                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8901                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8902                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8903                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8904                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8905                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8906                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8907                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8908                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8909                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8910                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8911                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8912                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8913                         I40E_INSET_IPV6_NEXT_HDR},
8914                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8915                         I40E_INSET_IPV6_HOP_LIMIT},
8916                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8917                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8918                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8919                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8920                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8921                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8922                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8923                         I40E_INSET_SCTP_VT},
8924                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8925                         I40E_INSET_TUNNEL_DMAC},
8926                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8927                         I40E_INSET_VLAN_TUNNEL},
8928                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8929                         I40E_INSET_TUNNEL_ID},
8930                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8931                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8932                         I40E_INSET_FLEX_PAYLOAD_W1},
8933                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8934                         I40E_INSET_FLEX_PAYLOAD_W2},
8935                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8936                         I40E_INSET_FLEX_PAYLOAD_W3},
8937                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8938                         I40E_INSET_FLEX_PAYLOAD_W4},
8939                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8940                         I40E_INSET_FLEX_PAYLOAD_W5},
8941                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8942                         I40E_INSET_FLEX_PAYLOAD_W6},
8943                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8944                         I40E_INSET_FLEX_PAYLOAD_W7},
8945                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8946                         I40E_INSET_FLEX_PAYLOAD_W8},
8947         };
8948
8949         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8950                 return ret;
8951
8952         /* Only one item allowed for default or all */
8953         if (size == 1) {
8954                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8955                         *inset = i40e_get_default_input_set(pctype);
8956                         return 0;
8957                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8958                         *inset = I40E_INSET_NONE;
8959                         return 0;
8960                 }
8961         }
8962
8963         for (i = 0, *inset = 0; i < size; i++) {
8964                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8965                         if (field[i] == inset_convert_table[j].field) {
8966                                 *inset |= inset_convert_table[j].inset;
8967                                 break;
8968                         }
8969                 }
8970
8971                 /* It contains unsupported input set, return immediately */
8972                 if (j == RTE_DIM(inset_convert_table))
8973                         return ret;
8974         }
8975
8976         return 0;
8977 }
8978
8979 /**
8980  * Translate the input set from bit masks to register aware bit masks
8981  * and vice versa
8982  */
8983 uint64_t
8984 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8985 {
8986         uint64_t val = 0;
8987         uint16_t i;
8988
8989         struct inset_map {
8990                 uint64_t inset;
8991                 uint64_t inset_reg;
8992         };
8993
8994         static const struct inset_map inset_map_common[] = {
8995                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8996                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8997                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8998                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8999                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9000                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9001                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9002                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9003                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9004                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9005                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9006                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9007                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9008                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9009                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9010                 {I40E_INSET_TUNNEL_DMAC,
9011                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9012                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9013                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9014                 {I40E_INSET_TUNNEL_SRC_PORT,
9015                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9016                 {I40E_INSET_TUNNEL_DST_PORT,
9017                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9018                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9019                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9020                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9021                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9022                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9023                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9024                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9025                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9026                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9027         };
9028
9029     /* some different registers map in x722*/
9030         static const struct inset_map inset_map_diff_x722[] = {
9031                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9032                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9033                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9034                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9035         };
9036
9037         static const struct inset_map inset_map_diff_not_x722[] = {
9038                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9039                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9040                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9041                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9042         };
9043
9044         if (input == 0)
9045                 return val;
9046
9047         /* Translate input set to register aware inset */
9048         if (type == I40E_MAC_X722) {
9049                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9050                         if (input & inset_map_diff_x722[i].inset)
9051                                 val |= inset_map_diff_x722[i].inset_reg;
9052                 }
9053         } else {
9054                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9055                         if (input & inset_map_diff_not_x722[i].inset)
9056                                 val |= inset_map_diff_not_x722[i].inset_reg;
9057                 }
9058         }
9059
9060         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9061                 if (input & inset_map_common[i].inset)
9062                         val |= inset_map_common[i].inset_reg;
9063         }
9064
9065         return val;
9066 }
9067
9068 int
9069 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9070 {
9071         uint8_t i, idx = 0;
9072         uint64_t inset_need_mask = inset;
9073
9074         static const struct {
9075                 uint64_t inset;
9076                 uint32_t mask;
9077         } inset_mask_map[] = {
9078                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9079                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9080                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9081                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9082                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9083                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9084                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9085                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9086         };
9087
9088         if (!inset || !mask || !nb_elem)
9089                 return 0;
9090
9091         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9092                 /* Clear the inset bit, if no MASK is required,
9093                  * for example proto + ttl
9094                  */
9095                 if ((inset & inset_mask_map[i].inset) ==
9096                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9097                         inset_need_mask &= ~inset_mask_map[i].inset;
9098                 if (!inset_need_mask)
9099                         return 0;
9100         }
9101         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9102                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9103                     inset_mask_map[i].inset) {
9104                         if (idx >= nb_elem) {
9105                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9106                                 return -EINVAL;
9107                         }
9108                         mask[idx] = inset_mask_map[i].mask;
9109                         idx++;
9110                 }
9111         }
9112
9113         return idx;
9114 }
9115
9116 void
9117 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9118 {
9119         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9120
9121         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9122         if (reg != val)
9123                 i40e_write_rx_ctl(hw, addr, val);
9124         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9125                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9126 }
9127
9128 void
9129 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9130 {
9131         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9132
9133         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9134         if (reg != val)
9135                 i40e_write_global_rx_ctl(hw, addr, val);
9136         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9137                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9138 }
9139
9140 static void
9141 i40e_filter_input_set_init(struct i40e_pf *pf)
9142 {
9143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9144         enum i40e_filter_pctype pctype;
9145         uint64_t input_set, inset_reg;
9146         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9147         int num, i;
9148         uint16_t flow_type;
9149
9150         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9151              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9152                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9153
9154                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9155                         continue;
9156
9157                 input_set = i40e_get_default_input_set(pctype);
9158
9159                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9160                                                    I40E_INSET_MASK_NUM_REG);
9161                 if (num < 0)
9162                         return;
9163                 if (pf->support_multi_driver && num > 0) {
9164                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9165                         return;
9166                 }
9167                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9168                                         input_set);
9169
9170                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9171                                       (uint32_t)(inset_reg & UINT32_MAX));
9172                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9173                                      (uint32_t)((inset_reg >>
9174                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9175                 if (!pf->support_multi_driver) {
9176                         i40e_check_write_global_reg(hw,
9177                                             I40E_GLQF_HASH_INSET(0, pctype),
9178                                             (uint32_t)(inset_reg & UINT32_MAX));
9179                         i40e_check_write_global_reg(hw,
9180                                              I40E_GLQF_HASH_INSET(1, pctype),
9181                                              (uint32_t)((inset_reg >>
9182                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9183
9184                         for (i = 0; i < num; i++) {
9185                                 i40e_check_write_global_reg(hw,
9186                                                     I40E_GLQF_FD_MSK(i, pctype),
9187                                                     mask_reg[i]);
9188                                 i40e_check_write_global_reg(hw,
9189                                                   I40E_GLQF_HASH_MSK(i, pctype),
9190                                                   mask_reg[i]);
9191                         }
9192                         /*clear unused mask registers of the pctype */
9193                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9194                                 i40e_check_write_global_reg(hw,
9195                                                     I40E_GLQF_FD_MSK(i, pctype),
9196                                                     0);
9197                                 i40e_check_write_global_reg(hw,
9198                                                   I40E_GLQF_HASH_MSK(i, pctype),
9199                                                   0);
9200                         }
9201                 } else {
9202                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9203                 }
9204                 I40E_WRITE_FLUSH(hw);
9205
9206                 /* store the default input set */
9207                 if (!pf->support_multi_driver)
9208                         pf->hash_input_set[pctype] = input_set;
9209                 pf->fdir.input_set[pctype] = input_set;
9210         }
9211
9212         if (!pf->support_multi_driver) {
9213                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9214                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9215                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9216         }
9217 }
9218
9219 int
9220 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9221                          struct rte_eth_input_set_conf *conf)
9222 {
9223         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9224         enum i40e_filter_pctype pctype;
9225         uint64_t input_set, inset_reg = 0;
9226         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9227         int ret, i, num;
9228
9229         if (!conf) {
9230                 PMD_DRV_LOG(ERR, "Invalid pointer");
9231                 return -EFAULT;
9232         }
9233         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9234             conf->op != RTE_ETH_INPUT_SET_ADD) {
9235                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9236                 return -EINVAL;
9237         }
9238
9239         if (pf->support_multi_driver) {
9240                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9241                 return -ENOTSUP;
9242         }
9243
9244         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9245         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9246                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9247                 return -EINVAL;
9248         }
9249
9250         if (hw->mac.type == I40E_MAC_X722) {
9251                 /* get translated pctype value in fd pctype register */
9252                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9253                         I40E_GLQF_FD_PCTYPES((int)pctype));
9254         }
9255
9256         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9257                                    conf->inset_size);
9258         if (ret) {
9259                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9260                 return -EINVAL;
9261         }
9262
9263         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9264                 /* get inset value in register */
9265                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9266                 inset_reg <<= I40E_32_BIT_WIDTH;
9267                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9268                 input_set |= pf->hash_input_set[pctype];
9269         }
9270         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9271                                            I40E_INSET_MASK_NUM_REG);
9272         if (num < 0)
9273                 return -EINVAL;
9274
9275         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9276
9277         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9278                                     (uint32_t)(inset_reg & UINT32_MAX));
9279         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9280                                     (uint32_t)((inset_reg >>
9281                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9282         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9283
9284         for (i = 0; i < num; i++)
9285                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9286                                             mask_reg[i]);
9287         /*clear unused mask registers of the pctype */
9288         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9289                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9290                                             0);
9291         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9292         I40E_WRITE_FLUSH(hw);
9293
9294         pf->hash_input_set[pctype] = input_set;
9295         return 0;
9296 }
9297
9298 int
9299 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9300                          struct rte_eth_input_set_conf *conf)
9301 {
9302         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9303         enum i40e_filter_pctype pctype;
9304         uint64_t input_set, inset_reg = 0;
9305         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9306         int ret, i, num;
9307
9308         if (!hw || !conf) {
9309                 PMD_DRV_LOG(ERR, "Invalid pointer");
9310                 return -EFAULT;
9311         }
9312         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9313             conf->op != RTE_ETH_INPUT_SET_ADD) {
9314                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9315                 return -EINVAL;
9316         }
9317
9318         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9319
9320         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9321                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9322                 return -EINVAL;
9323         }
9324
9325         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9326                                    conf->inset_size);
9327         if (ret) {
9328                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9329                 return -EINVAL;
9330         }
9331
9332         /* get inset value in register */
9333         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9334         inset_reg <<= I40E_32_BIT_WIDTH;
9335         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9336
9337         /* Can not change the inset reg for flex payload for fdir,
9338          * it is done by writing I40E_PRTQF_FD_FLXINSET
9339          * in i40e_set_flex_mask_on_pctype.
9340          */
9341         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9342                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9343         else
9344                 input_set |= pf->fdir.input_set[pctype];
9345         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9346                                            I40E_INSET_MASK_NUM_REG);
9347         if (num < 0)
9348                 return -EINVAL;
9349         if (pf->support_multi_driver && num > 0) {
9350                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9351                 return -ENOTSUP;
9352         }
9353
9354         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9355
9356         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9357                               (uint32_t)(inset_reg & UINT32_MAX));
9358         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9359                              (uint32_t)((inset_reg >>
9360                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9361
9362         if (!pf->support_multi_driver) {
9363                 for (i = 0; i < num; i++)
9364                         i40e_check_write_global_reg(hw,
9365                                                     I40E_GLQF_FD_MSK(i, pctype),
9366                                                     mask_reg[i]);
9367                 /*clear unused mask registers of the pctype */
9368                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9369                         i40e_check_write_global_reg(hw,
9370                                                     I40E_GLQF_FD_MSK(i, pctype),
9371                                                     0);
9372                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9373         } else {
9374                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9375         }
9376         I40E_WRITE_FLUSH(hw);
9377
9378         pf->fdir.input_set[pctype] = input_set;
9379         return 0;
9380 }
9381
9382 static int
9383 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9384 {
9385         int ret = 0;
9386
9387         if (!hw || !info) {
9388                 PMD_DRV_LOG(ERR, "Invalid pointer");
9389                 return -EFAULT;
9390         }
9391
9392         switch (info->info_type) {
9393         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9394                 i40e_get_symmetric_hash_enable_per_port(hw,
9395                                         &(info->info.enable));
9396                 break;
9397         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9398                 ret = i40e_get_hash_filter_global_config(hw,
9399                                 &(info->info.global_conf));
9400                 break;
9401         default:
9402                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9403                                                         info->info_type);
9404                 ret = -EINVAL;
9405                 break;
9406         }
9407
9408         return ret;
9409 }
9410
9411 static int
9412 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9413 {
9414         int ret = 0;
9415
9416         if (!hw || !info) {
9417                 PMD_DRV_LOG(ERR, "Invalid pointer");
9418                 return -EFAULT;
9419         }
9420
9421         switch (info->info_type) {
9422         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9423                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9424                 break;
9425         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9426                 ret = i40e_set_hash_filter_global_config(hw,
9427                                 &(info->info.global_conf));
9428                 break;
9429         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9430                 ret = i40e_hash_filter_inset_select(hw,
9431                                                &(info->info.input_set_conf));
9432                 break;
9433
9434         default:
9435                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9436                                                         info->info_type);
9437                 ret = -EINVAL;
9438                 break;
9439         }
9440
9441         return ret;
9442 }
9443
9444 /* Operations for hash function */
9445 static int
9446 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9447                       enum rte_filter_op filter_op,
9448                       void *arg)
9449 {
9450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9451         int ret = 0;
9452
9453         switch (filter_op) {
9454         case RTE_ETH_FILTER_NOP:
9455                 break;
9456         case RTE_ETH_FILTER_GET:
9457                 ret = i40e_hash_filter_get(hw,
9458                         (struct rte_eth_hash_filter_info *)arg);
9459                 break;
9460         case RTE_ETH_FILTER_SET:
9461                 ret = i40e_hash_filter_set(hw,
9462                         (struct rte_eth_hash_filter_info *)arg);
9463                 break;
9464         default:
9465                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9466                                                                 filter_op);
9467                 ret = -ENOTSUP;
9468                 break;
9469         }
9470
9471         return ret;
9472 }
9473
9474 /* Convert ethertype filter structure */
9475 static int
9476 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9477                               struct i40e_ethertype_filter *filter)
9478 {
9479         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9480         filter->input.ether_type = input->ether_type;
9481         filter->flags = input->flags;
9482         filter->queue = input->queue;
9483
9484         return 0;
9485 }
9486
9487 /* Check if there exists the ehtertype filter */
9488 struct i40e_ethertype_filter *
9489 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9490                                 const struct i40e_ethertype_filter_input *input)
9491 {
9492         int ret;
9493
9494         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9495         if (ret < 0)
9496                 return NULL;
9497
9498         return ethertype_rule->hash_map[ret];
9499 }
9500
9501 /* Add ethertype filter in SW list */
9502 static int
9503 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9504                                 struct i40e_ethertype_filter *filter)
9505 {
9506         struct i40e_ethertype_rule *rule = &pf->ethertype;
9507         int ret;
9508
9509         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9510         if (ret < 0) {
9511                 PMD_DRV_LOG(ERR,
9512                             "Failed to insert ethertype filter"
9513                             " to hash table %d!",
9514                             ret);
9515                 return ret;
9516         }
9517         rule->hash_map[ret] = filter;
9518
9519         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9520
9521         return 0;
9522 }
9523
9524 /* Delete ethertype filter in SW list */
9525 int
9526 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9527                              struct i40e_ethertype_filter_input *input)
9528 {
9529         struct i40e_ethertype_rule *rule = &pf->ethertype;
9530         struct i40e_ethertype_filter *filter;
9531         int ret;
9532
9533         ret = rte_hash_del_key(rule->hash_table, input);
9534         if (ret < 0) {
9535                 PMD_DRV_LOG(ERR,
9536                             "Failed to delete ethertype filter"
9537                             " to hash table %d!",
9538                             ret);
9539                 return ret;
9540         }
9541         filter = rule->hash_map[ret];
9542         rule->hash_map[ret] = NULL;
9543
9544         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9545         rte_free(filter);
9546
9547         return 0;
9548 }
9549
9550 /*
9551  * Configure ethertype filter, which can director packet by filtering
9552  * with mac address and ether_type or only ether_type
9553  */
9554 int
9555 i40e_ethertype_filter_set(struct i40e_pf *pf,
9556                         struct rte_eth_ethertype_filter *filter,
9557                         bool add)
9558 {
9559         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9560         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9561         struct i40e_ethertype_filter *ethertype_filter, *node;
9562         struct i40e_ethertype_filter check_filter;
9563         struct i40e_control_filter_stats stats;
9564         uint16_t flags = 0;
9565         int ret;
9566
9567         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9568                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9569                 return -EINVAL;
9570         }
9571         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9572                 filter->ether_type == ETHER_TYPE_IPv6) {
9573                 PMD_DRV_LOG(ERR,
9574                         "unsupported ether_type(0x%04x) in control packet filter.",
9575                         filter->ether_type);
9576                 return -EINVAL;
9577         }
9578         if (filter->ether_type == ETHER_TYPE_VLAN)
9579                 PMD_DRV_LOG(WARNING,
9580                         "filter vlan ether_type in first tag is not supported.");
9581
9582         /* Check if there is the filter in SW list */
9583         memset(&check_filter, 0, sizeof(check_filter));
9584         i40e_ethertype_filter_convert(filter, &check_filter);
9585         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9586                                                &check_filter.input);
9587         if (add && node) {
9588                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9589                 return -EINVAL;
9590         }
9591
9592         if (!add && !node) {
9593                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9594                 return -EINVAL;
9595         }
9596
9597         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9598                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9599         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9600                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9601         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9602
9603         memset(&stats, 0, sizeof(stats));
9604         ret = i40e_aq_add_rem_control_packet_filter(hw,
9605                         filter->mac_addr.addr_bytes,
9606                         filter->ether_type, flags,
9607                         pf->main_vsi->seid,
9608                         filter->queue, add, &stats, NULL);
9609
9610         PMD_DRV_LOG(INFO,
9611                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9612                 ret, stats.mac_etype_used, stats.etype_used,
9613                 stats.mac_etype_free, stats.etype_free);
9614         if (ret < 0)
9615                 return -ENOSYS;
9616
9617         /* Add or delete a filter in SW list */
9618         if (add) {
9619                 ethertype_filter = rte_zmalloc("ethertype_filter",
9620                                        sizeof(*ethertype_filter), 0);
9621                 if (ethertype_filter == NULL) {
9622                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9623                         return -ENOMEM;
9624                 }
9625
9626                 rte_memcpy(ethertype_filter, &check_filter,
9627                            sizeof(check_filter));
9628                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9629                 if (ret < 0)
9630                         rte_free(ethertype_filter);
9631         } else {
9632                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9633         }
9634
9635         return ret;
9636 }
9637
9638 /*
9639  * Handle operations for ethertype filter.
9640  */
9641 static int
9642 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9643                                 enum rte_filter_op filter_op,
9644                                 void *arg)
9645 {
9646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9647         int ret = 0;
9648
9649         if (filter_op == RTE_ETH_FILTER_NOP)
9650                 return ret;
9651
9652         if (arg == NULL) {
9653                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9654                             filter_op);
9655                 return -EINVAL;
9656         }
9657
9658         switch (filter_op) {
9659         case RTE_ETH_FILTER_ADD:
9660                 ret = i40e_ethertype_filter_set(pf,
9661                         (struct rte_eth_ethertype_filter *)arg,
9662                         TRUE);
9663                 break;
9664         case RTE_ETH_FILTER_DELETE:
9665                 ret = i40e_ethertype_filter_set(pf,
9666                         (struct rte_eth_ethertype_filter *)arg,
9667                         FALSE);
9668                 break;
9669         default:
9670                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9671                 ret = -ENOSYS;
9672                 break;
9673         }
9674         return ret;
9675 }
9676
9677 static int
9678 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9679                      enum rte_filter_type filter_type,
9680                      enum rte_filter_op filter_op,
9681                      void *arg)
9682 {
9683         int ret = 0;
9684
9685         if (dev == NULL)
9686                 return -EINVAL;
9687
9688         switch (filter_type) {
9689         case RTE_ETH_FILTER_NONE:
9690                 /* For global configuration */
9691                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9692                 break;
9693         case RTE_ETH_FILTER_HASH:
9694                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9695                 break;
9696         case RTE_ETH_FILTER_MACVLAN:
9697                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9698                 break;
9699         case RTE_ETH_FILTER_ETHERTYPE:
9700                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9701                 break;
9702         case RTE_ETH_FILTER_TUNNEL:
9703                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9704                 break;
9705         case RTE_ETH_FILTER_FDIR:
9706                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9707                 break;
9708         case RTE_ETH_FILTER_GENERIC:
9709                 if (filter_op != RTE_ETH_FILTER_GET)
9710                         return -EINVAL;
9711                 *(const void **)arg = &i40e_flow_ops;
9712                 break;
9713         default:
9714                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9715                                                         filter_type);
9716                 ret = -EINVAL;
9717                 break;
9718         }
9719
9720         return ret;
9721 }
9722
9723 /*
9724  * Check and enable Extended Tag.
9725  * Enabling Extended Tag is important for 40G performance.
9726  */
9727 static void
9728 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9729 {
9730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9731         uint32_t buf = 0;
9732         int ret;
9733
9734         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9735                                       PCI_DEV_CAP_REG);
9736         if (ret < 0) {
9737                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9738                             PCI_DEV_CAP_REG);
9739                 return;
9740         }
9741         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9742                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9743                 return;
9744         }
9745
9746         buf = 0;
9747         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9748                                       PCI_DEV_CTRL_REG);
9749         if (ret < 0) {
9750                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9751                             PCI_DEV_CTRL_REG);
9752                 return;
9753         }
9754         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9755                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9756                 return;
9757         }
9758         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9759         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9760                                        PCI_DEV_CTRL_REG);
9761         if (ret < 0) {
9762                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9763                             PCI_DEV_CTRL_REG);
9764                 return;
9765         }
9766 }
9767
9768 /*
9769  * As some registers wouldn't be reset unless a global hardware reset,
9770  * hardware initialization is needed to put those registers into an
9771  * expected initial state.
9772  */
9773 static void
9774 i40e_hw_init(struct rte_eth_dev *dev)
9775 {
9776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9777
9778         i40e_enable_extended_tag(dev);
9779
9780         /* clear the PF Queue Filter control register */
9781         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9782
9783         /* Disable symmetric hash per port */
9784         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9785 }
9786
9787 /*
9788  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9789  * however this function will return only one highest pctype index,
9790  * which is not quite correct. This is known problem of i40e driver
9791  * and needs to be fixed later.
9792  */
9793 enum i40e_filter_pctype
9794 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9795 {
9796         int i;
9797         uint64_t pctype_mask;
9798
9799         if (flow_type < I40E_FLOW_TYPE_MAX) {
9800                 pctype_mask = adapter->pctypes_tbl[flow_type];
9801                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9802                         if (pctype_mask & (1ULL << i))
9803                                 return (enum i40e_filter_pctype)i;
9804                 }
9805         }
9806         return I40E_FILTER_PCTYPE_INVALID;
9807 }
9808
9809 uint16_t
9810 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9811                         enum i40e_filter_pctype pctype)
9812 {
9813         uint16_t flowtype;
9814         uint64_t pctype_mask = 1ULL << pctype;
9815
9816         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9817              flowtype++) {
9818                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9819                         return flowtype;
9820         }
9821
9822         return RTE_ETH_FLOW_UNKNOWN;
9823 }
9824
9825 /*
9826  * On X710, performance number is far from the expectation on recent firmware
9827  * versions; on XL710, performance number is also far from the expectation on
9828  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9829  * mode is enabled and port MAC address is equal to the packet destination MAC
9830  * address. The fix for this issue may not be integrated in the following
9831  * firmware version. So the workaround in software driver is needed. It needs
9832  * to modify the initial values of 3 internal only registers for both X710 and
9833  * XL710. Note that the values for X710 or XL710 could be different, and the
9834  * workaround can be removed when it is fixed in firmware in the future.
9835  */
9836
9837 /* For both X710 and XL710 */
9838 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9839 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9840 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9841
9842 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9843 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9844
9845 /* For X722 */
9846 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9847 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9848
9849 /* For X710 */
9850 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9851 /* For XL710 */
9852 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9853 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9854
9855 static int
9856 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9857 {
9858         enum i40e_status_code status;
9859         struct i40e_aq_get_phy_abilities_resp phy_ab;
9860         int ret = -ENOTSUP;
9861         int retries = 0;
9862
9863         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9864                                               NULL);
9865
9866         while (status) {
9867                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9868                         status);
9869                 retries++;
9870                 rte_delay_us(100000);
9871                 if  (retries < 5)
9872                         status = i40e_aq_get_phy_capabilities(hw, false,
9873                                         true, &phy_ab, NULL);
9874                 else
9875                         return ret;
9876         }
9877         return 0;
9878 }
9879
9880 static void
9881 i40e_configure_registers(struct i40e_hw *hw)
9882 {
9883         static struct {
9884                 uint32_t addr;
9885                 uint64_t val;
9886         } reg_table[] = {
9887                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9888                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9889                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9890         };
9891         uint64_t reg;
9892         uint32_t i;
9893         int ret;
9894
9895         for (i = 0; i < RTE_DIM(reg_table); i++) {
9896                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9897                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9898                                 reg_table[i].val =
9899                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9900                         else /* For X710/XL710/XXV710 */
9901                                 if (hw->aq.fw_maj_ver < 6)
9902                                         reg_table[i].val =
9903                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9904                                 else
9905                                         reg_table[i].val =
9906                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9907                 }
9908
9909                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9910                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9911                                 reg_table[i].val =
9912                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9913                         else /* For X710/XL710/XXV710 */
9914                                 reg_table[i].val =
9915                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9916                 }
9917
9918                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9919                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9920                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9921                                 reg_table[i].val =
9922                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9923                         else /* For X710 */
9924                                 reg_table[i].val =
9925                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9926                 }
9927
9928                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9929                                                         &reg, NULL);
9930                 if (ret < 0) {
9931                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9932                                                         reg_table[i].addr);
9933                         break;
9934                 }
9935                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9936                                                 reg_table[i].addr, reg);
9937                 if (reg == reg_table[i].val)
9938                         continue;
9939
9940                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9941                                                 reg_table[i].val, NULL);
9942                 if (ret < 0) {
9943                         PMD_DRV_LOG(ERR,
9944                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9945                                 reg_table[i].val, reg_table[i].addr);
9946                         break;
9947                 }
9948                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9949                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9950         }
9951 }
9952
9953 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9954 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9955 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9956 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9957 static int
9958 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9959 {
9960         uint32_t reg;
9961         int ret;
9962
9963         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9964                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9965                 return -EINVAL;
9966         }
9967
9968         /* Configure for double VLAN RX stripping */
9969         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9970         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9971                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9972                 ret = i40e_aq_debug_write_register(hw,
9973                                                    I40E_VSI_TSR(vsi->vsi_id),
9974                                                    reg, NULL);
9975                 if (ret < 0) {
9976                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9977                                     vsi->vsi_id);
9978                         return I40E_ERR_CONFIG;
9979                 }
9980         }
9981
9982         /* Configure for double VLAN TX insertion */
9983         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9984         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9985                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9986                 ret = i40e_aq_debug_write_register(hw,
9987                                                    I40E_VSI_L2TAGSTXVALID(
9988                                                    vsi->vsi_id), reg, NULL);
9989                 if (ret < 0) {
9990                         PMD_DRV_LOG(ERR,
9991                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9992                                 vsi->vsi_id);
9993                         return I40E_ERR_CONFIG;
9994                 }
9995         }
9996
9997         return 0;
9998 }
9999
10000 /**
10001  * i40e_aq_add_mirror_rule
10002  * @hw: pointer to the hardware structure
10003  * @seid: VEB seid to add mirror rule to
10004  * @dst_id: destination vsi seid
10005  * @entries: Buffer which contains the entities to be mirrored
10006  * @count: number of entities contained in the buffer
10007  * @rule_id:the rule_id of the rule to be added
10008  *
10009  * Add a mirror rule for a given veb.
10010  *
10011  **/
10012 static enum i40e_status_code
10013 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10014                         uint16_t seid, uint16_t dst_id,
10015                         uint16_t rule_type, uint16_t *entries,
10016                         uint16_t count, uint16_t *rule_id)
10017 {
10018         struct i40e_aq_desc desc;
10019         struct i40e_aqc_add_delete_mirror_rule cmd;
10020         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10021                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10022                 &desc.params.raw;
10023         uint16_t buff_len;
10024         enum i40e_status_code status;
10025
10026         i40e_fill_default_direct_cmd_desc(&desc,
10027                                           i40e_aqc_opc_add_mirror_rule);
10028         memset(&cmd, 0, sizeof(cmd));
10029
10030         buff_len = sizeof(uint16_t) * count;
10031         desc.datalen = rte_cpu_to_le_16(buff_len);
10032         if (buff_len > 0)
10033                 desc.flags |= rte_cpu_to_le_16(
10034                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10035         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10036                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10037         cmd.num_entries = rte_cpu_to_le_16(count);
10038         cmd.seid = rte_cpu_to_le_16(seid);
10039         cmd.destination = rte_cpu_to_le_16(dst_id);
10040
10041         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10042         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10043         PMD_DRV_LOG(INFO,
10044                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10045                 hw->aq.asq_last_status, resp->rule_id,
10046                 resp->mirror_rules_used, resp->mirror_rules_free);
10047         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10048
10049         return status;
10050 }
10051
10052 /**
10053  * i40e_aq_del_mirror_rule
10054  * @hw: pointer to the hardware structure
10055  * @seid: VEB seid to add mirror rule to
10056  * @entries: Buffer which contains the entities to be mirrored
10057  * @count: number of entities contained in the buffer
10058  * @rule_id:the rule_id of the rule to be delete
10059  *
10060  * Delete a mirror rule for a given veb.
10061  *
10062  **/
10063 static enum i40e_status_code
10064 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10065                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10066                 uint16_t count, uint16_t rule_id)
10067 {
10068         struct i40e_aq_desc desc;
10069         struct i40e_aqc_add_delete_mirror_rule cmd;
10070         uint16_t buff_len = 0;
10071         enum i40e_status_code status;
10072         void *buff = NULL;
10073
10074         i40e_fill_default_direct_cmd_desc(&desc,
10075                                           i40e_aqc_opc_delete_mirror_rule);
10076         memset(&cmd, 0, sizeof(cmd));
10077         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10078                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10079                                                           I40E_AQ_FLAG_RD));
10080                 cmd.num_entries = count;
10081                 buff_len = sizeof(uint16_t) * count;
10082                 desc.datalen = rte_cpu_to_le_16(buff_len);
10083                 buff = (void *)entries;
10084         } else
10085                 /* rule id is filled in destination field for deleting mirror rule */
10086                 cmd.destination = rte_cpu_to_le_16(rule_id);
10087
10088         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10089                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10090         cmd.seid = rte_cpu_to_le_16(seid);
10091
10092         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10093         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10094
10095         return status;
10096 }
10097
10098 /**
10099  * i40e_mirror_rule_set
10100  * @dev: pointer to the hardware structure
10101  * @mirror_conf: mirror rule info
10102  * @sw_id: mirror rule's sw_id
10103  * @on: enable/disable
10104  *
10105  * set a mirror rule.
10106  *
10107  **/
10108 static int
10109 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10110                         struct rte_eth_mirror_conf *mirror_conf,
10111                         uint8_t sw_id, uint8_t on)
10112 {
10113         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10115         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10116         struct i40e_mirror_rule *parent = NULL;
10117         uint16_t seid, dst_seid, rule_id;
10118         uint16_t i, j = 0;
10119         int ret;
10120
10121         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10122
10123         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10124                 PMD_DRV_LOG(ERR,
10125                         "mirror rule can not be configured without veb or vfs.");
10126                 return -ENOSYS;
10127         }
10128         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10129                 PMD_DRV_LOG(ERR, "mirror table is full.");
10130                 return -ENOSPC;
10131         }
10132         if (mirror_conf->dst_pool > pf->vf_num) {
10133                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10134                                  mirror_conf->dst_pool);
10135                 return -EINVAL;
10136         }
10137
10138         seid = pf->main_vsi->veb->seid;
10139
10140         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10141                 if (sw_id <= it->index) {
10142                         mirr_rule = it;
10143                         break;
10144                 }
10145                 parent = it;
10146         }
10147         if (mirr_rule && sw_id == mirr_rule->index) {
10148                 if (on) {
10149                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10150                         return -EEXIST;
10151                 } else {
10152                         ret = i40e_aq_del_mirror_rule(hw, seid,
10153                                         mirr_rule->rule_type,
10154                                         mirr_rule->entries,
10155                                         mirr_rule->num_entries, mirr_rule->id);
10156                         if (ret < 0) {
10157                                 PMD_DRV_LOG(ERR,
10158                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10159                                         ret, hw->aq.asq_last_status);
10160                                 return -ENOSYS;
10161                         }
10162                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10163                         rte_free(mirr_rule);
10164                         pf->nb_mirror_rule--;
10165                         return 0;
10166                 }
10167         } else if (!on) {
10168                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10169                 return -ENOENT;
10170         }
10171
10172         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10173                                 sizeof(struct i40e_mirror_rule) , 0);
10174         if (!mirr_rule) {
10175                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10176                 return I40E_ERR_NO_MEMORY;
10177         }
10178         switch (mirror_conf->rule_type) {
10179         case ETH_MIRROR_VLAN:
10180                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10181                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10182                                 mirr_rule->entries[j] =
10183                                         mirror_conf->vlan.vlan_id[i];
10184                                 j++;
10185                         }
10186                 }
10187                 if (j == 0) {
10188                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10189                         rte_free(mirr_rule);
10190                         return -EINVAL;
10191                 }
10192                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10193                 break;
10194         case ETH_MIRROR_VIRTUAL_POOL_UP:
10195         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10196                 /* check if the specified pool bit is out of range */
10197                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10198                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10199                         rte_free(mirr_rule);
10200                         return -EINVAL;
10201                 }
10202                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10203                         if (mirror_conf->pool_mask & (1ULL << i)) {
10204                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10205                                 j++;
10206                         }
10207                 }
10208                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10209                         /* add pf vsi to entries */
10210                         mirr_rule->entries[j] = pf->main_vsi_seid;
10211                         j++;
10212                 }
10213                 if (j == 0) {
10214                         PMD_DRV_LOG(ERR, "pool is not specified.");
10215                         rte_free(mirr_rule);
10216                         return -EINVAL;
10217                 }
10218                 /* egress and ingress in aq commands means from switch but not port */
10219                 mirr_rule->rule_type =
10220                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10221                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10222                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10223                 break;
10224         case ETH_MIRROR_UPLINK_PORT:
10225                 /* egress and ingress in aq commands means from switch but not port*/
10226                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10227                 break;
10228         case ETH_MIRROR_DOWNLINK_PORT:
10229                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10230                 break;
10231         default:
10232                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10233                         mirror_conf->rule_type);
10234                 rte_free(mirr_rule);
10235                 return -EINVAL;
10236         }
10237
10238         /* If the dst_pool is equal to vf_num, consider it as PF */
10239         if (mirror_conf->dst_pool == pf->vf_num)
10240                 dst_seid = pf->main_vsi_seid;
10241         else
10242                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10243
10244         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10245                                       mirr_rule->rule_type, mirr_rule->entries,
10246                                       j, &rule_id);
10247         if (ret < 0) {
10248                 PMD_DRV_LOG(ERR,
10249                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10250                         ret, hw->aq.asq_last_status);
10251                 rte_free(mirr_rule);
10252                 return -ENOSYS;
10253         }
10254
10255         mirr_rule->index = sw_id;
10256         mirr_rule->num_entries = j;
10257         mirr_rule->id = rule_id;
10258         mirr_rule->dst_vsi_seid = dst_seid;
10259
10260         if (parent)
10261                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10262         else
10263                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10264
10265         pf->nb_mirror_rule++;
10266         return 0;
10267 }
10268
10269 /**
10270  * i40e_mirror_rule_reset
10271  * @dev: pointer to the device
10272  * @sw_id: mirror rule's sw_id
10273  *
10274  * reset a mirror rule.
10275  *
10276  **/
10277 static int
10278 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10279 {
10280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10282         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10283         uint16_t seid;
10284         int ret;
10285
10286         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10287
10288         seid = pf->main_vsi->veb->seid;
10289
10290         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10291                 if (sw_id == it->index) {
10292                         mirr_rule = it;
10293                         break;
10294                 }
10295         }
10296         if (mirr_rule) {
10297                 ret = i40e_aq_del_mirror_rule(hw, seid,
10298                                 mirr_rule->rule_type,
10299                                 mirr_rule->entries,
10300                                 mirr_rule->num_entries, mirr_rule->id);
10301                 if (ret < 0) {
10302                         PMD_DRV_LOG(ERR,
10303                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10304                                 ret, hw->aq.asq_last_status);
10305                         return -ENOSYS;
10306                 }
10307                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10308                 rte_free(mirr_rule);
10309                 pf->nb_mirror_rule--;
10310         } else {
10311                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10312                 return -ENOENT;
10313         }
10314         return 0;
10315 }
10316
10317 static uint64_t
10318 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10319 {
10320         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10321         uint64_t systim_cycles;
10322
10323         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10324         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10325                         << 32;
10326
10327         return systim_cycles;
10328 }
10329
10330 static uint64_t
10331 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10332 {
10333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10334         uint64_t rx_tstamp;
10335
10336         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10337         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10338                         << 32;
10339
10340         return rx_tstamp;
10341 }
10342
10343 static uint64_t
10344 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10345 {
10346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10347         uint64_t tx_tstamp;
10348
10349         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10350         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10351                         << 32;
10352
10353         return tx_tstamp;
10354 }
10355
10356 static void
10357 i40e_start_timecounters(struct rte_eth_dev *dev)
10358 {
10359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10360         struct i40e_adapter *adapter =
10361                         (struct i40e_adapter *)dev->data->dev_private;
10362         struct rte_eth_link link;
10363         uint32_t tsync_inc_l;
10364         uint32_t tsync_inc_h;
10365
10366         /* Get current link speed. */
10367         i40e_dev_link_update(dev, 1);
10368         rte_eth_linkstatus_get(dev, &link);
10369
10370         switch (link.link_speed) {
10371         case ETH_SPEED_NUM_40G:
10372                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10373                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10374                 break;
10375         case ETH_SPEED_NUM_10G:
10376                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10377                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10378                 break;
10379         case ETH_SPEED_NUM_1G:
10380                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10381                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10382                 break;
10383         default:
10384                 tsync_inc_l = 0x0;
10385                 tsync_inc_h = 0x0;
10386         }
10387
10388         /* Set the timesync increment value. */
10389         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10390         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10391
10392         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10393         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10394         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10395
10396         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10397         adapter->systime_tc.cc_shift = 0;
10398         adapter->systime_tc.nsec_mask = 0;
10399
10400         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10401         adapter->rx_tstamp_tc.cc_shift = 0;
10402         adapter->rx_tstamp_tc.nsec_mask = 0;
10403
10404         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10405         adapter->tx_tstamp_tc.cc_shift = 0;
10406         adapter->tx_tstamp_tc.nsec_mask = 0;
10407 }
10408
10409 static int
10410 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10411 {
10412         struct i40e_adapter *adapter =
10413                         (struct i40e_adapter *)dev->data->dev_private;
10414
10415         adapter->systime_tc.nsec += delta;
10416         adapter->rx_tstamp_tc.nsec += delta;
10417         adapter->tx_tstamp_tc.nsec += delta;
10418
10419         return 0;
10420 }
10421
10422 static int
10423 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10424 {
10425         uint64_t ns;
10426         struct i40e_adapter *adapter =
10427                         (struct i40e_adapter *)dev->data->dev_private;
10428
10429         ns = rte_timespec_to_ns(ts);
10430
10431         /* Set the timecounters to a new value. */
10432         adapter->systime_tc.nsec = ns;
10433         adapter->rx_tstamp_tc.nsec = ns;
10434         adapter->tx_tstamp_tc.nsec = ns;
10435
10436         return 0;
10437 }
10438
10439 static int
10440 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10441 {
10442         uint64_t ns, systime_cycles;
10443         struct i40e_adapter *adapter =
10444                         (struct i40e_adapter *)dev->data->dev_private;
10445
10446         systime_cycles = i40e_read_systime_cyclecounter(dev);
10447         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10448         *ts = rte_ns_to_timespec(ns);
10449
10450         return 0;
10451 }
10452
10453 static int
10454 i40e_timesync_enable(struct rte_eth_dev *dev)
10455 {
10456         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10457         uint32_t tsync_ctl_l;
10458         uint32_t tsync_ctl_h;
10459
10460         /* Stop the timesync system time. */
10461         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10462         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10463         /* Reset the timesync system time value. */
10464         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10465         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10466
10467         i40e_start_timecounters(dev);
10468
10469         /* Clear timesync registers. */
10470         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10471         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10472         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10473         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10474         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10475         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10476
10477         /* Enable timestamping of PTP packets. */
10478         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10479         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10480
10481         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10482         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10483         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10484
10485         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10486         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10487
10488         return 0;
10489 }
10490
10491 static int
10492 i40e_timesync_disable(struct rte_eth_dev *dev)
10493 {
10494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10495         uint32_t tsync_ctl_l;
10496         uint32_t tsync_ctl_h;
10497
10498         /* Disable timestamping of transmitted PTP packets. */
10499         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10500         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10501
10502         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10503         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10504
10505         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10506         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10507
10508         /* Reset the timesync increment value. */
10509         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10510         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10511
10512         return 0;
10513 }
10514
10515 static int
10516 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10517                                 struct timespec *timestamp, uint32_t flags)
10518 {
10519         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10520         struct i40e_adapter *adapter =
10521                 (struct i40e_adapter *)dev->data->dev_private;
10522
10523         uint32_t sync_status;
10524         uint32_t index = flags & 0x03;
10525         uint64_t rx_tstamp_cycles;
10526         uint64_t ns;
10527
10528         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10529         if ((sync_status & (1 << index)) == 0)
10530                 return -EINVAL;
10531
10532         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10533         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10534         *timestamp = rte_ns_to_timespec(ns);
10535
10536         return 0;
10537 }
10538
10539 static int
10540 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10541                                 struct timespec *timestamp)
10542 {
10543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10544         struct i40e_adapter *adapter =
10545                 (struct i40e_adapter *)dev->data->dev_private;
10546
10547         uint32_t sync_status;
10548         uint64_t tx_tstamp_cycles;
10549         uint64_t ns;
10550
10551         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10552         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10553                 return -EINVAL;
10554
10555         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10556         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10557         *timestamp = rte_ns_to_timespec(ns);
10558
10559         return 0;
10560 }
10561
10562 /*
10563  * i40e_parse_dcb_configure - parse dcb configure from user
10564  * @dev: the device being configured
10565  * @dcb_cfg: pointer of the result of parse
10566  * @*tc_map: bit map of enabled traffic classes
10567  *
10568  * Returns 0 on success, negative value on failure
10569  */
10570 static int
10571 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10572                          struct i40e_dcbx_config *dcb_cfg,
10573                          uint8_t *tc_map)
10574 {
10575         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10576         uint8_t i, tc_bw, bw_lf;
10577
10578         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10579
10580         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10581         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10582                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10583                 return -EINVAL;
10584         }
10585
10586         /* assume each tc has the same bw */
10587         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10588         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10589                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10590         /* to ensure the sum of tcbw is equal to 100 */
10591         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10592         for (i = 0; i < bw_lf; i++)
10593                 dcb_cfg->etscfg.tcbwtable[i]++;
10594
10595         /* assume each tc has the same Transmission Selection Algorithm */
10596         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10597                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10598
10599         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10600                 dcb_cfg->etscfg.prioritytable[i] =
10601                                 dcb_rx_conf->dcb_tc[i];
10602
10603         /* FW needs one App to configure HW */
10604         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10605         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10606         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10607         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10608
10609         if (dcb_rx_conf->nb_tcs == 0)
10610                 *tc_map = 1; /* tc0 only */
10611         else
10612                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10613
10614         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10615                 dcb_cfg->pfc.willing = 0;
10616                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10617                 dcb_cfg->pfc.pfcenable = *tc_map;
10618         }
10619         return 0;
10620 }
10621
10622
10623 static enum i40e_status_code
10624 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10625                               struct i40e_aqc_vsi_properties_data *info,
10626                               uint8_t enabled_tcmap)
10627 {
10628         enum i40e_status_code ret;
10629         int i, total_tc = 0;
10630         uint16_t qpnum_per_tc, bsf, qp_idx;
10631         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10632         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10633         uint16_t used_queues;
10634
10635         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10636         if (ret != I40E_SUCCESS)
10637                 return ret;
10638
10639         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10640                 if (enabled_tcmap & (1 << i))
10641                         total_tc++;
10642         }
10643         if (total_tc == 0)
10644                 total_tc = 1;
10645         vsi->enabled_tc = enabled_tcmap;
10646
10647         /* different VSI has different queues assigned */
10648         if (vsi->type == I40E_VSI_MAIN)
10649                 used_queues = dev_data->nb_rx_queues -
10650                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10651         else if (vsi->type == I40E_VSI_VMDQ2)
10652                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10653         else {
10654                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10655                 return I40E_ERR_NO_AVAILABLE_VSI;
10656         }
10657
10658         qpnum_per_tc = used_queues / total_tc;
10659         /* Number of queues per enabled TC */
10660         if (qpnum_per_tc == 0) {
10661                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10662                 return I40E_ERR_INVALID_QP_ID;
10663         }
10664         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10665                                 I40E_MAX_Q_PER_TC);
10666         bsf = rte_bsf32(qpnum_per_tc);
10667
10668         /**
10669          * Configure TC and queue mapping parameters, for enabled TC,
10670          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10671          * default queue will serve it.
10672          */
10673         qp_idx = 0;
10674         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10675                 if (vsi->enabled_tc & (1 << i)) {
10676                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10677                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10678                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10679                         qp_idx += qpnum_per_tc;
10680                 } else
10681                         info->tc_mapping[i] = 0;
10682         }
10683
10684         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10685         if (vsi->type == I40E_VSI_SRIOV) {
10686                 info->mapping_flags |=
10687                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10688                 for (i = 0; i < vsi->nb_qps; i++)
10689                         info->queue_mapping[i] =
10690                                 rte_cpu_to_le_16(vsi->base_queue + i);
10691         } else {
10692                 info->mapping_flags |=
10693                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10694                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10695         }
10696         info->valid_sections |=
10697                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10698
10699         return I40E_SUCCESS;
10700 }
10701
10702 /*
10703  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10704  * @veb: VEB to be configured
10705  * @tc_map: enabled TC bitmap
10706  *
10707  * Returns 0 on success, negative value on failure
10708  */
10709 static enum i40e_status_code
10710 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10711 {
10712         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10713         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10714         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10715         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10716         enum i40e_status_code ret = I40E_SUCCESS;
10717         int i;
10718         uint32_t bw_max;
10719
10720         /* Check if enabled_tc is same as existing or new TCs */
10721         if (veb->enabled_tc == tc_map)
10722                 return ret;
10723
10724         /* configure tc bandwidth */
10725         memset(&veb_bw, 0, sizeof(veb_bw));
10726         veb_bw.tc_valid_bits = tc_map;
10727         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10728         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10729                 if (tc_map & BIT_ULL(i))
10730                         veb_bw.tc_bw_share_credits[i] = 1;
10731         }
10732         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10733                                                    &veb_bw, NULL);
10734         if (ret) {
10735                 PMD_INIT_LOG(ERR,
10736                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10737                         hw->aq.asq_last_status);
10738                 return ret;
10739         }
10740
10741         memset(&ets_query, 0, sizeof(ets_query));
10742         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10743                                                    &ets_query, NULL);
10744         if (ret != I40E_SUCCESS) {
10745                 PMD_DRV_LOG(ERR,
10746                         "Failed to get switch_comp ETS configuration %u",
10747                         hw->aq.asq_last_status);
10748                 return ret;
10749         }
10750         memset(&bw_query, 0, sizeof(bw_query));
10751         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10752                                                   &bw_query, NULL);
10753         if (ret != I40E_SUCCESS) {
10754                 PMD_DRV_LOG(ERR,
10755                         "Failed to get switch_comp bandwidth configuration %u",
10756                         hw->aq.asq_last_status);
10757                 return ret;
10758         }
10759
10760         /* store and print out BW info */
10761         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10762         veb->bw_info.bw_max = ets_query.tc_bw_max;
10763         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10764         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10765         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10766                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10767                      I40E_16_BIT_WIDTH);
10768         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10769                 veb->bw_info.bw_ets_share_credits[i] =
10770                                 bw_query.tc_bw_share_credits[i];
10771                 veb->bw_info.bw_ets_credits[i] =
10772                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10773                 /* 4 bits per TC, 4th bit is reserved */
10774                 veb->bw_info.bw_ets_max[i] =
10775                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10776                                   RTE_LEN2MASK(3, uint8_t));
10777                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10778                             veb->bw_info.bw_ets_share_credits[i]);
10779                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10780                             veb->bw_info.bw_ets_credits[i]);
10781                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10782                             veb->bw_info.bw_ets_max[i]);
10783         }
10784
10785         veb->enabled_tc = tc_map;
10786
10787         return ret;
10788 }
10789
10790
10791 /*
10792  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10793  * @vsi: VSI to be configured
10794  * @tc_map: enabled TC bitmap
10795  *
10796  * Returns 0 on success, negative value on failure
10797  */
10798 static enum i40e_status_code
10799 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10800 {
10801         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10802         struct i40e_vsi_context ctxt;
10803         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10804         enum i40e_status_code ret = I40E_SUCCESS;
10805         int i;
10806
10807         /* Check if enabled_tc is same as existing or new TCs */
10808         if (vsi->enabled_tc == tc_map)
10809                 return ret;
10810
10811         /* configure tc bandwidth */
10812         memset(&bw_data, 0, sizeof(bw_data));
10813         bw_data.tc_valid_bits = tc_map;
10814         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10815         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10816                 if (tc_map & BIT_ULL(i))
10817                         bw_data.tc_bw_credits[i] = 1;
10818         }
10819         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10820         if (ret) {
10821                 PMD_INIT_LOG(ERR,
10822                         "AQ command Config VSI BW allocation per TC failed = %d",
10823                         hw->aq.asq_last_status);
10824                 goto out;
10825         }
10826         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10827                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10828
10829         /* Update Queue Pairs Mapping for currently enabled UPs */
10830         ctxt.seid = vsi->seid;
10831         ctxt.pf_num = hw->pf_id;
10832         ctxt.vf_num = 0;
10833         ctxt.uplink_seid = vsi->uplink_seid;
10834         ctxt.info = vsi->info;
10835         i40e_get_cap(hw);
10836         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10837         if (ret)
10838                 goto out;
10839
10840         /* Update the VSI after updating the VSI queue-mapping information */
10841         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10842         if (ret) {
10843                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10844                         hw->aq.asq_last_status);
10845                 goto out;
10846         }
10847         /* update the local VSI info with updated queue map */
10848         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10849                                         sizeof(vsi->info.tc_mapping));
10850         rte_memcpy(&vsi->info.queue_mapping,
10851                         &ctxt.info.queue_mapping,
10852                 sizeof(vsi->info.queue_mapping));
10853         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10854         vsi->info.valid_sections = 0;
10855
10856         /* query and update current VSI BW information */
10857         ret = i40e_vsi_get_bw_config(vsi);
10858         if (ret) {
10859                 PMD_INIT_LOG(ERR,
10860                          "Failed updating vsi bw info, err %s aq_err %s",
10861                          i40e_stat_str(hw, ret),
10862                          i40e_aq_str(hw, hw->aq.asq_last_status));
10863                 goto out;
10864         }
10865
10866         vsi->enabled_tc = tc_map;
10867
10868 out:
10869         return ret;
10870 }
10871
10872 /*
10873  * i40e_dcb_hw_configure - program the dcb setting to hw
10874  * @pf: pf the configuration is taken on
10875  * @new_cfg: new configuration
10876  * @tc_map: enabled TC bitmap
10877  *
10878  * Returns 0 on success, negative value on failure
10879  */
10880 static enum i40e_status_code
10881 i40e_dcb_hw_configure(struct i40e_pf *pf,
10882                       struct i40e_dcbx_config *new_cfg,
10883                       uint8_t tc_map)
10884 {
10885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10886         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10887         struct i40e_vsi *main_vsi = pf->main_vsi;
10888         struct i40e_vsi_list *vsi_list;
10889         enum i40e_status_code ret;
10890         int i;
10891         uint32_t val;
10892
10893         /* Use the FW API if FW > v4.4*/
10894         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10895               (hw->aq.fw_maj_ver >= 5))) {
10896                 PMD_INIT_LOG(ERR,
10897                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10898                 return I40E_ERR_FIRMWARE_API_VERSION;
10899         }
10900
10901         /* Check if need reconfiguration */
10902         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10903                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10904                 return I40E_SUCCESS;
10905         }
10906
10907         /* Copy the new config to the current config */
10908         *old_cfg = *new_cfg;
10909         old_cfg->etsrec = old_cfg->etscfg;
10910         ret = i40e_set_dcb_config(hw);
10911         if (ret) {
10912                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10913                          i40e_stat_str(hw, ret),
10914                          i40e_aq_str(hw, hw->aq.asq_last_status));
10915                 return ret;
10916         }
10917         /* set receive Arbiter to RR mode and ETS scheme by default */
10918         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10919                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10920                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10921                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10922                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10923                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10924                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10925                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10926                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10927                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10928                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10929                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10930                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10931         }
10932         /* get local mib to check whether it is configured correctly */
10933         /* IEEE mode */
10934         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10935         /* Get Local DCB Config */
10936         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10937                                      &hw->local_dcbx_config);
10938
10939         /* if Veb is created, need to update TC of it at first */
10940         if (main_vsi->veb) {
10941                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10942                 if (ret)
10943                         PMD_INIT_LOG(WARNING,
10944                                  "Failed configuring TC for VEB seid=%d",
10945                                  main_vsi->veb->seid);
10946         }
10947         /* Update each VSI */
10948         i40e_vsi_config_tc(main_vsi, tc_map);
10949         if (main_vsi->veb) {
10950                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10951                         /* Beside main VSI and VMDQ VSIs, only enable default
10952                          * TC for other VSIs
10953                          */
10954                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10955                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10956                                                          tc_map);
10957                         else
10958                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10959                                                          I40E_DEFAULT_TCMAP);
10960                         if (ret)
10961                                 PMD_INIT_LOG(WARNING,
10962                                         "Failed configuring TC for VSI seid=%d",
10963                                         vsi_list->vsi->seid);
10964                         /* continue */
10965                 }
10966         }
10967         return I40E_SUCCESS;
10968 }
10969
10970 /*
10971  * i40e_dcb_init_configure - initial dcb config
10972  * @dev: device being configured
10973  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10974  *
10975  * Returns 0 on success, negative value on failure
10976  */
10977 int
10978 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10979 {
10980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10982         int i, ret = 0;
10983
10984         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10985                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10986                 return -ENOTSUP;
10987         }
10988
10989         /* DCB initialization:
10990          * Update DCB configuration from the Firmware and configure
10991          * LLDP MIB change event.
10992          */
10993         if (sw_dcb == TRUE) {
10994                 ret = i40e_init_dcb(hw);
10995                 /* If lldp agent is stopped, the return value from
10996                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10997                  * adminq status. Otherwise, it should return success.
10998                  */
10999                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11000                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11001                         memset(&hw->local_dcbx_config, 0,
11002                                 sizeof(struct i40e_dcbx_config));
11003                         /* set dcb default configuration */
11004                         hw->local_dcbx_config.etscfg.willing = 0;
11005                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11006                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11007                         hw->local_dcbx_config.etscfg.tsatable[0] =
11008                                                 I40E_IEEE_TSA_ETS;
11009                         /* all UPs mapping to TC0 */
11010                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11011                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11012                         hw->local_dcbx_config.etsrec =
11013                                 hw->local_dcbx_config.etscfg;
11014                         hw->local_dcbx_config.pfc.willing = 0;
11015                         hw->local_dcbx_config.pfc.pfccap =
11016                                                 I40E_MAX_TRAFFIC_CLASS;
11017                         /* FW needs one App to configure HW */
11018                         hw->local_dcbx_config.numapps = 1;
11019                         hw->local_dcbx_config.app[0].selector =
11020                                                 I40E_APP_SEL_ETHTYPE;
11021                         hw->local_dcbx_config.app[0].priority = 3;
11022                         hw->local_dcbx_config.app[0].protocolid =
11023                                                 I40E_APP_PROTOID_FCOE;
11024                         ret = i40e_set_dcb_config(hw);
11025                         if (ret) {
11026                                 PMD_INIT_LOG(ERR,
11027                                         "default dcb config fails. err = %d, aq_err = %d.",
11028                                         ret, hw->aq.asq_last_status);
11029                                 return -ENOSYS;
11030                         }
11031                 } else {
11032                         PMD_INIT_LOG(ERR,
11033                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11034                                 ret, hw->aq.asq_last_status);
11035                         return -ENOTSUP;
11036                 }
11037         } else {
11038                 ret = i40e_aq_start_lldp(hw, NULL);
11039                 if (ret != I40E_SUCCESS)
11040                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11041
11042                 ret = i40e_init_dcb(hw);
11043                 if (!ret) {
11044                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11045                                 PMD_INIT_LOG(ERR,
11046                                         "HW doesn't support DCBX offload.");
11047                                 return -ENOTSUP;
11048                         }
11049                 } else {
11050                         PMD_INIT_LOG(ERR,
11051                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11052                                 ret, hw->aq.asq_last_status);
11053                         return -ENOTSUP;
11054                 }
11055         }
11056         return 0;
11057 }
11058
11059 /*
11060  * i40e_dcb_setup - setup dcb related config
11061  * @dev: device being configured
11062  *
11063  * Returns 0 on success, negative value on failure
11064  */
11065 static int
11066 i40e_dcb_setup(struct rte_eth_dev *dev)
11067 {
11068         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11069         struct i40e_dcbx_config dcb_cfg;
11070         uint8_t tc_map = 0;
11071         int ret = 0;
11072
11073         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11074                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11075                 return -ENOTSUP;
11076         }
11077
11078         if (pf->vf_num != 0)
11079                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11080
11081         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11082         if (ret) {
11083                 PMD_INIT_LOG(ERR, "invalid dcb config");
11084                 return -EINVAL;
11085         }
11086         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11087         if (ret) {
11088                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11089                 return -ENOSYS;
11090         }
11091
11092         return 0;
11093 }
11094
11095 static int
11096 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11097                       struct rte_eth_dcb_info *dcb_info)
11098 {
11099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11101         struct i40e_vsi *vsi = pf->main_vsi;
11102         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11103         uint16_t bsf, tc_mapping;
11104         int i, j = 0;
11105
11106         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11107                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11108         else
11109                 dcb_info->nb_tcs = 1;
11110         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11111                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11112         for (i = 0; i < dcb_info->nb_tcs; i++)
11113                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11114
11115         /* get queue mapping if vmdq is disabled */
11116         if (!pf->nb_cfg_vmdq_vsi) {
11117                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11118                         if (!(vsi->enabled_tc & (1 << i)))
11119                                 continue;
11120                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11121                         dcb_info->tc_queue.tc_rxq[j][i].base =
11122                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11123                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11124                         dcb_info->tc_queue.tc_txq[j][i].base =
11125                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11126                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11127                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11128                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11129                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11130                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11131                 }
11132                 return 0;
11133         }
11134
11135         /* get queue mapping if vmdq is enabled */
11136         do {
11137                 vsi = pf->vmdq[j].vsi;
11138                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11139                         if (!(vsi->enabled_tc & (1 << i)))
11140                                 continue;
11141                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11142                         dcb_info->tc_queue.tc_rxq[j][i].base =
11143                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11144                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11145                         dcb_info->tc_queue.tc_txq[j][i].base =
11146                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11147                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11148                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11149                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11150                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11151                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11152                 }
11153                 j++;
11154         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11155         return 0;
11156 }
11157
11158 static int
11159 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11160 {
11161         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11162         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11164         uint16_t msix_intr;
11165
11166         msix_intr = intr_handle->intr_vec[queue_id];
11167         if (msix_intr == I40E_MISC_VEC_ID)
11168                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11169                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11170                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11171                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11172         else
11173                 I40E_WRITE_REG(hw,
11174                                I40E_PFINT_DYN_CTLN(msix_intr -
11175                                                    I40E_RX_VEC_START),
11176                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11177                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11178                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11179
11180         I40E_WRITE_FLUSH(hw);
11181         rte_intr_enable(&pci_dev->intr_handle);
11182
11183         return 0;
11184 }
11185
11186 static int
11187 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11188 {
11189         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11190         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11192         uint16_t msix_intr;
11193
11194         msix_intr = intr_handle->intr_vec[queue_id];
11195         if (msix_intr == I40E_MISC_VEC_ID)
11196                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11197                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11198         else
11199                 I40E_WRITE_REG(hw,
11200                                I40E_PFINT_DYN_CTLN(msix_intr -
11201                                                    I40E_RX_VEC_START),
11202                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11203         I40E_WRITE_FLUSH(hw);
11204
11205         return 0;
11206 }
11207
11208 static int i40e_get_regs(struct rte_eth_dev *dev,
11209                          struct rte_dev_reg_info *regs)
11210 {
11211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11212         uint32_t *ptr_data = regs->data;
11213         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11214         const struct i40e_reg_info *reg_info;
11215
11216         if (ptr_data == NULL) {
11217                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11218                 regs->width = sizeof(uint32_t);
11219                 return 0;
11220         }
11221
11222         /* The first few registers have to be read using AQ operations */
11223         reg_idx = 0;
11224         while (i40e_regs_adminq[reg_idx].name) {
11225                 reg_info = &i40e_regs_adminq[reg_idx++];
11226                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11227                         for (arr_idx2 = 0;
11228                                         arr_idx2 <= reg_info->count2;
11229                                         arr_idx2++) {
11230                                 reg_offset = arr_idx * reg_info->stride1 +
11231                                         arr_idx2 * reg_info->stride2;
11232                                 reg_offset += reg_info->base_addr;
11233                                 ptr_data[reg_offset >> 2] =
11234                                         i40e_read_rx_ctl(hw, reg_offset);
11235                         }
11236         }
11237
11238         /* The remaining registers can be read using primitives */
11239         reg_idx = 0;
11240         while (i40e_regs_others[reg_idx].name) {
11241                 reg_info = &i40e_regs_others[reg_idx++];
11242                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11243                         for (arr_idx2 = 0;
11244                                         arr_idx2 <= reg_info->count2;
11245                                         arr_idx2++) {
11246                                 reg_offset = arr_idx * reg_info->stride1 +
11247                                         arr_idx2 * reg_info->stride2;
11248                                 reg_offset += reg_info->base_addr;
11249                                 ptr_data[reg_offset >> 2] =
11250                                         I40E_READ_REG(hw, reg_offset);
11251                         }
11252         }
11253
11254         return 0;
11255 }
11256
11257 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11258 {
11259         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11260
11261         /* Convert word count to byte count */
11262         return hw->nvm.sr_size << 1;
11263 }
11264
11265 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11266                            struct rte_dev_eeprom_info *eeprom)
11267 {
11268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11269         uint16_t *data = eeprom->data;
11270         uint16_t offset, length, cnt_words;
11271         int ret_code;
11272
11273         offset = eeprom->offset >> 1;
11274         length = eeprom->length >> 1;
11275         cnt_words = length;
11276
11277         if (offset > hw->nvm.sr_size ||
11278                 offset + length > hw->nvm.sr_size) {
11279                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11280                 return -EINVAL;
11281         }
11282
11283         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11284
11285         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11286         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11287                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11288                 return -EIO;
11289         }
11290
11291         return 0;
11292 }
11293
11294 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11295                                       struct ether_addr *mac_addr)
11296 {
11297         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11299         struct i40e_vsi *vsi = pf->main_vsi;
11300         struct i40e_mac_filter_info mac_filter;
11301         struct i40e_mac_filter *f;
11302         int ret;
11303
11304         if (!is_valid_assigned_ether_addr(mac_addr)) {
11305                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11306                 return;
11307         }
11308
11309         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11310                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11311                         break;
11312         }
11313
11314         if (f == NULL) {
11315                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11316                 return;
11317         }
11318
11319         mac_filter = f->mac_info;
11320         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11321         if (ret != I40E_SUCCESS) {
11322                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11323                 return;
11324         }
11325         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11326         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11327         if (ret != I40E_SUCCESS) {
11328                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11329                 return;
11330         }
11331         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11332
11333         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11334                                   mac_addr->addr_bytes, NULL);
11335 }
11336
11337 static int
11338 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11339 {
11340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11341         struct rte_eth_dev_data *dev_data = pf->dev_data;
11342         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11343         int ret = 0;
11344
11345         /* check if mtu is within the allowed range */
11346         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11347                 return -EINVAL;
11348
11349         /* mtu setting is forbidden if port is start */
11350         if (dev_data->dev_started) {
11351                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11352                             dev_data->port_id);
11353                 return -EBUSY;
11354         }
11355
11356         if (frame_size > ETHER_MAX_LEN)
11357                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11358         else
11359                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11360
11361         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11362
11363         return ret;
11364 }
11365
11366 /* Restore ethertype filter */
11367 static void
11368 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11369 {
11370         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11371         struct i40e_ethertype_filter_list
11372                 *ethertype_list = &pf->ethertype.ethertype_list;
11373         struct i40e_ethertype_filter *f;
11374         struct i40e_control_filter_stats stats;
11375         uint16_t flags;
11376
11377         TAILQ_FOREACH(f, ethertype_list, rules) {
11378                 flags = 0;
11379                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11380                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11381                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11382                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11383                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11384
11385                 memset(&stats, 0, sizeof(stats));
11386                 i40e_aq_add_rem_control_packet_filter(hw,
11387                                             f->input.mac_addr.addr_bytes,
11388                                             f->input.ether_type,
11389                                             flags, pf->main_vsi->seid,
11390                                             f->queue, 1, &stats, NULL);
11391         }
11392         PMD_DRV_LOG(INFO, "Ethertype filter:"
11393                     " mac_etype_used = %u, etype_used = %u,"
11394                     " mac_etype_free = %u, etype_free = %u",
11395                     stats.mac_etype_used, stats.etype_used,
11396                     stats.mac_etype_free, stats.etype_free);
11397 }
11398
11399 /* Restore tunnel filter */
11400 static void
11401 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11402 {
11403         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11404         struct i40e_vsi *vsi;
11405         struct i40e_pf_vf *vf;
11406         struct i40e_tunnel_filter_list
11407                 *tunnel_list = &pf->tunnel.tunnel_list;
11408         struct i40e_tunnel_filter *f;
11409         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11410         bool big_buffer = 0;
11411
11412         TAILQ_FOREACH(f, tunnel_list, rules) {
11413                 if (!f->is_to_vf)
11414                         vsi = pf->main_vsi;
11415                 else {
11416                         vf = &pf->vfs[f->vf_id];
11417                         vsi = vf->vsi;
11418                 }
11419                 memset(&cld_filter, 0, sizeof(cld_filter));
11420                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11421                         (struct ether_addr *)&cld_filter.element.outer_mac);
11422                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11423                         (struct ether_addr *)&cld_filter.element.inner_mac);
11424                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11425                 cld_filter.element.flags = f->input.flags;
11426                 cld_filter.element.tenant_id = f->input.tenant_id;
11427                 cld_filter.element.queue_number = f->queue;
11428                 rte_memcpy(cld_filter.general_fields,
11429                            f->input.general_fields,
11430                            sizeof(f->input.general_fields));
11431
11432                 if (((f->input.flags &
11433                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11434                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11435                     ((f->input.flags &
11436                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11437                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11438                     ((f->input.flags &
11439                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11440                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11441                         big_buffer = 1;
11442
11443                 if (big_buffer)
11444                         i40e_aq_add_cloud_filters_big_buffer(hw,
11445                                              vsi->seid, &cld_filter, 1);
11446                 else
11447                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11448                                                   &cld_filter.element, 1);
11449         }
11450 }
11451
11452 /* Restore rss filter */
11453 static inline void
11454 i40e_rss_filter_restore(struct i40e_pf *pf)
11455 {
11456         struct i40e_rte_flow_rss_conf *conf =
11457                                         &pf->rss_info;
11458         if (conf->num)
11459                 i40e_config_rss_filter(pf, conf, TRUE);
11460 }
11461
11462 static void
11463 i40e_filter_restore(struct i40e_pf *pf)
11464 {
11465         i40e_ethertype_filter_restore(pf);
11466         i40e_tunnel_filter_restore(pf);
11467         i40e_fdir_filter_restore(pf);
11468         i40e_rss_filter_restore(pf);
11469 }
11470
11471 static bool
11472 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11473 {
11474         if (strcmp(dev->device->driver->name, drv->driver.name))
11475                 return false;
11476
11477         return true;
11478 }
11479
11480 bool
11481 is_i40e_supported(struct rte_eth_dev *dev)
11482 {
11483         return is_device_supported(dev, &rte_i40e_pmd);
11484 }
11485
11486 struct i40e_customized_pctype*
11487 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11488 {
11489         int i;
11490
11491         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11492                 if (pf->customized_pctype[i].index == index)
11493                         return &pf->customized_pctype[i];
11494         }
11495         return NULL;
11496 }
11497
11498 static int
11499 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11500                               uint32_t pkg_size, uint32_t proto_num,
11501                               struct rte_pmd_i40e_proto_info *proto)
11502 {
11503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11504         uint32_t pctype_num;
11505         struct rte_pmd_i40e_ptype_info *pctype;
11506         uint32_t buff_size;
11507         struct i40e_customized_pctype *new_pctype = NULL;
11508         uint8_t proto_id;
11509         uint8_t pctype_value;
11510         char name[64];
11511         uint32_t i, j, n;
11512         int ret;
11513
11514         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11515                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11516                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11517         if (ret) {
11518                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11519                 return -1;
11520         }
11521         if (!pctype_num) {
11522                 PMD_DRV_LOG(INFO, "No new pctype added");
11523                 return -1;
11524         }
11525
11526         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11527         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11528         if (!pctype) {
11529                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11530                 return -1;
11531         }
11532         /* get information about new pctype list */
11533         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11534                                         (uint8_t *)pctype, buff_size,
11535                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11536         if (ret) {
11537                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11538                 rte_free(pctype);
11539                 return -1;
11540         }
11541
11542         /* Update customized pctype. */
11543         for (i = 0; i < pctype_num; i++) {
11544                 pctype_value = pctype[i].ptype_id;
11545                 memset(name, 0, sizeof(name));
11546                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11547                         proto_id = pctype[i].protocols[j];
11548                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11549                                 continue;
11550                         for (n = 0; n < proto_num; n++) {
11551                                 if (proto[n].proto_id != proto_id)
11552                                         continue;
11553                                 strcat(name, proto[n].name);
11554                                 strcat(name, "_");
11555                                 break;
11556                         }
11557                 }
11558                 name[strlen(name) - 1] = '\0';
11559                 if (!strcmp(name, "GTPC"))
11560                         new_pctype =
11561                                 i40e_find_customized_pctype(pf,
11562                                                       I40E_CUSTOMIZED_GTPC);
11563                 else if (!strcmp(name, "GTPU_IPV4"))
11564                         new_pctype =
11565                                 i40e_find_customized_pctype(pf,
11566                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11567                 else if (!strcmp(name, "GTPU_IPV6"))
11568                         new_pctype =
11569                                 i40e_find_customized_pctype(pf,
11570                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11571                 else if (!strcmp(name, "GTPU"))
11572                         new_pctype =
11573                                 i40e_find_customized_pctype(pf,
11574                                                       I40E_CUSTOMIZED_GTPU);
11575                 if (new_pctype) {
11576                         new_pctype->pctype = pctype_value;
11577                         new_pctype->valid = true;
11578                 }
11579         }
11580
11581         rte_free(pctype);
11582         return 0;
11583 }
11584
11585 static int
11586 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11587                                uint32_t pkg_size, uint32_t proto_num,
11588                                struct rte_pmd_i40e_proto_info *proto)
11589 {
11590         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11591         uint16_t port_id = dev->data->port_id;
11592         uint32_t ptype_num;
11593         struct rte_pmd_i40e_ptype_info *ptype;
11594         uint32_t buff_size;
11595         uint8_t proto_id;
11596         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11597         uint32_t i, j, n;
11598         bool in_tunnel;
11599         int ret;
11600
11601         /* get information about new ptype num */
11602         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11603                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11604                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11605         if (ret) {
11606                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11607                 return ret;
11608         }
11609         if (!ptype_num) {
11610                 PMD_DRV_LOG(INFO, "No new ptype added");
11611                 return -1;
11612         }
11613
11614         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11615         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11616         if (!ptype) {
11617                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11618                 return -1;
11619         }
11620
11621         /* get information about new ptype list */
11622         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11623                                         (uint8_t *)ptype, buff_size,
11624                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11625         if (ret) {
11626                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11627                 rte_free(ptype);
11628                 return ret;
11629         }
11630
11631         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11632         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11633         if (!ptype_mapping) {
11634                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11635                 rte_free(ptype);
11636                 return -1;
11637         }
11638
11639         /* Update ptype mapping table. */
11640         for (i = 0; i < ptype_num; i++) {
11641                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11642                 ptype_mapping[i].sw_ptype = 0;
11643                 in_tunnel = false;
11644                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11645                         proto_id = ptype[i].protocols[j];
11646                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11647                                 continue;
11648                         for (n = 0; n < proto_num; n++) {
11649                                 if (proto[n].proto_id != proto_id)
11650                                         continue;
11651                                 memset(name, 0, sizeof(name));
11652                                 strcpy(name, proto[n].name);
11653                                 if (!strncasecmp(name, "PPPOE", 5))
11654                                         ptype_mapping[i].sw_ptype |=
11655                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11656                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11657                                          !in_tunnel) {
11658                                         ptype_mapping[i].sw_ptype |=
11659                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11660                                         ptype_mapping[i].sw_ptype |=
11661                                                 RTE_PTYPE_L4_FRAG;
11662                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11663                                            in_tunnel) {
11664                                         ptype_mapping[i].sw_ptype |=
11665                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11666                                         ptype_mapping[i].sw_ptype |=
11667                                                 RTE_PTYPE_INNER_L4_FRAG;
11668                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11669                                         ptype_mapping[i].sw_ptype |=
11670                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11671                                         in_tunnel = true;
11672                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11673                                            !in_tunnel)
11674                                         ptype_mapping[i].sw_ptype |=
11675                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11676                                 else if (!strncasecmp(name, "IPV4", 4) &&
11677                                          in_tunnel)
11678                                         ptype_mapping[i].sw_ptype |=
11679                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11680                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11681                                          !in_tunnel) {
11682                                         ptype_mapping[i].sw_ptype |=
11683                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11684                                         ptype_mapping[i].sw_ptype |=
11685                                                 RTE_PTYPE_L4_FRAG;
11686                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11687                                            in_tunnel) {
11688                                         ptype_mapping[i].sw_ptype |=
11689                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11690                                         ptype_mapping[i].sw_ptype |=
11691                                                 RTE_PTYPE_INNER_L4_FRAG;
11692                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11693                                         ptype_mapping[i].sw_ptype |=
11694                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11695                                         in_tunnel = true;
11696                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11697                                            !in_tunnel)
11698                                         ptype_mapping[i].sw_ptype |=
11699                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11700                                 else if (!strncasecmp(name, "IPV6", 4) &&
11701                                          in_tunnel)
11702                                         ptype_mapping[i].sw_ptype |=
11703                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11704                                 else if (!strncasecmp(name, "UDP", 3) &&
11705                                          !in_tunnel)
11706                                         ptype_mapping[i].sw_ptype |=
11707                                                 RTE_PTYPE_L4_UDP;
11708                                 else if (!strncasecmp(name, "UDP", 3) &&
11709                                          in_tunnel)
11710                                         ptype_mapping[i].sw_ptype |=
11711                                                 RTE_PTYPE_INNER_L4_UDP;
11712                                 else if (!strncasecmp(name, "TCP", 3) &&
11713                                          !in_tunnel)
11714                                         ptype_mapping[i].sw_ptype |=
11715                                                 RTE_PTYPE_L4_TCP;
11716                                 else if (!strncasecmp(name, "TCP", 3) &&
11717                                          in_tunnel)
11718                                         ptype_mapping[i].sw_ptype |=
11719                                                 RTE_PTYPE_INNER_L4_TCP;
11720                                 else if (!strncasecmp(name, "SCTP", 4) &&
11721                                          !in_tunnel)
11722                                         ptype_mapping[i].sw_ptype |=
11723                                                 RTE_PTYPE_L4_SCTP;
11724                                 else if (!strncasecmp(name, "SCTP", 4) &&
11725                                          in_tunnel)
11726                                         ptype_mapping[i].sw_ptype |=
11727                                                 RTE_PTYPE_INNER_L4_SCTP;
11728                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11729                                           !strncasecmp(name, "ICMPV6", 6)) &&
11730                                          !in_tunnel)
11731                                         ptype_mapping[i].sw_ptype |=
11732                                                 RTE_PTYPE_L4_ICMP;
11733                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11734                                           !strncasecmp(name, "ICMPV6", 6)) &&
11735                                          in_tunnel)
11736                                         ptype_mapping[i].sw_ptype |=
11737                                                 RTE_PTYPE_INNER_L4_ICMP;
11738                                 else if (!strncasecmp(name, "GTPC", 4)) {
11739                                         ptype_mapping[i].sw_ptype |=
11740                                                 RTE_PTYPE_TUNNEL_GTPC;
11741                                         in_tunnel = true;
11742                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11743                                         ptype_mapping[i].sw_ptype |=
11744                                                 RTE_PTYPE_TUNNEL_GTPU;
11745                                         in_tunnel = true;
11746                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11747                                         ptype_mapping[i].sw_ptype |=
11748                                                 RTE_PTYPE_TUNNEL_GRENAT;
11749                                         in_tunnel = true;
11750                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11751                                         ptype_mapping[i].sw_ptype |=
11752                                                 RTE_PTYPE_TUNNEL_L2TP;
11753                                         in_tunnel = true;
11754                                 }
11755
11756                                 break;
11757                         }
11758                 }
11759         }
11760
11761         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11762                                                 ptype_num, 0);
11763         if (ret)
11764                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11765
11766         rte_free(ptype_mapping);
11767         rte_free(ptype);
11768         return ret;
11769 }
11770
11771 void
11772 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11773                               uint32_t pkg_size)
11774 {
11775         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11776         uint32_t proto_num;
11777         struct rte_pmd_i40e_proto_info *proto;
11778         uint32_t buff_size;
11779         uint32_t i;
11780         int ret;
11781
11782         /* get information about protocol number */
11783         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11784                                        (uint8_t *)&proto_num, sizeof(proto_num),
11785                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11786         if (ret) {
11787                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11788                 return;
11789         }
11790         if (!proto_num) {
11791                 PMD_DRV_LOG(INFO, "No new protocol added");
11792                 return;
11793         }
11794
11795         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11796         proto = rte_zmalloc("new_proto", buff_size, 0);
11797         if (!proto) {
11798                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11799                 return;
11800         }
11801
11802         /* get information about protocol list */
11803         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11804                                         (uint8_t *)proto, buff_size,
11805                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11806         if (ret) {
11807                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11808                 rte_free(proto);
11809                 return;
11810         }
11811
11812         /* Check if GTP is supported. */
11813         for (i = 0; i < proto_num; i++) {
11814                 if (!strncmp(proto[i].name, "GTP", 3)) {
11815                         pf->gtp_support = true;
11816                         break;
11817                 }
11818         }
11819
11820         /* Update customized pctype info */
11821         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11822                                             proto_num, proto);
11823         if (ret)
11824                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11825
11826         /* Update customized ptype info */
11827         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11828                                            proto_num, proto);
11829         if (ret)
11830                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11831
11832         rte_free(proto);
11833 }
11834
11835 /* Create a QinQ cloud filter
11836  *
11837  * The Fortville NIC has limited resources for tunnel filters,
11838  * so we can only reuse existing filters.
11839  *
11840  * In step 1 we define which Field Vector fields can be used for
11841  * filter types.
11842  * As we do not have the inner tag defined as a field,
11843  * we have to define it first, by reusing one of L1 entries.
11844  *
11845  * In step 2 we are replacing one of existing filter types with
11846  * a new one for QinQ.
11847  * As we reusing L1 and replacing L2, some of the default filter
11848  * types will disappear,which depends on L1 and L2 entries we reuse.
11849  *
11850  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11851  *
11852  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11853  *              later when we define the cloud filter.
11854  *      a.      Valid_flags.replace_cloud = 0
11855  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11856  *      c.      New_filter = 0x10
11857  *      d.      TR bit = 0xff (optional, not used here)
11858  *      e.      Buffer – 2 entries:
11859  *              i.      Byte 0 = 8 (outer vlan FV index).
11860  *                      Byte 1 = 0 (rsv)
11861  *                      Byte 2-3 = 0x0fff
11862  *              ii.     Byte 0 = 37 (inner vlan FV index).
11863  *                      Byte 1 =0 (rsv)
11864  *                      Byte 2-3 = 0x0fff
11865  *
11866  * Step 2:
11867  * 2.   Create cloud filter using two L1 filters entries: stag and
11868  *              new filter(outer vlan+ inner vlan)
11869  *      a.      Valid_flags.replace_cloud = 1
11870  *      b.      Old_filter = 1 (instead of outer IP)
11871  *      c.      New_filter = 0x10
11872  *      d.      Buffer – 2 entries:
11873  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11874  *                      Byte 1-3 = 0 (rsv)
11875  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11876  *                      Byte 9-11 = 0 (rsv)
11877  */
11878 static int
11879 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11880 {
11881         int ret = -ENOTSUP;
11882         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11883         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11884         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11885
11886         if (pf->support_multi_driver) {
11887                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11888                 return ret;
11889         }
11890
11891         /* Init */
11892         memset(&filter_replace, 0,
11893                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11894         memset(&filter_replace_buf, 0,
11895                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11896
11897         /* create L1 filter */
11898         filter_replace.old_filter_type =
11899                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11900         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11901         filter_replace.tr_bit = 0;
11902
11903         /* Prepare the buffer, 2 entries */
11904         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11905         filter_replace_buf.data[0] |=
11906                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11907         /* Field Vector 12b mask */
11908         filter_replace_buf.data[2] = 0xff;
11909         filter_replace_buf.data[3] = 0x0f;
11910         filter_replace_buf.data[4] =
11911                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11912         filter_replace_buf.data[4] |=
11913                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11914         /* Field Vector 12b mask */
11915         filter_replace_buf.data[6] = 0xff;
11916         filter_replace_buf.data[7] = 0x0f;
11917         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11918                         &filter_replace_buf);
11919         if (ret != I40E_SUCCESS)
11920                 return ret;
11921         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11922                     "cloud l1 type is changed from 0x%x to 0x%x",
11923                     filter_replace.old_filter_type,
11924                     filter_replace.new_filter_type);
11925
11926         /* Apply the second L2 cloud filter */
11927         memset(&filter_replace, 0,
11928                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11929         memset(&filter_replace_buf, 0,
11930                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11931
11932         /* create L2 filter, input for L2 filter will be L1 filter  */
11933         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11934         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11935         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11936
11937         /* Prepare the buffer, 2 entries */
11938         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11939         filter_replace_buf.data[0] |=
11940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11941         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11942         filter_replace_buf.data[4] |=
11943                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11944         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11945                         &filter_replace_buf);
11946         if (!ret) {
11947                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11948                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11949                             "cloud filter type is changed from 0x%x to 0x%x",
11950                             filter_replace.old_filter_type,
11951                             filter_replace.new_filter_type);
11952         }
11953         return ret;
11954 }
11955
11956 int
11957 i40e_config_rss_filter(struct i40e_pf *pf,
11958                 struct i40e_rte_flow_rss_conf *conf, bool add)
11959 {
11960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11961         uint32_t i, lut = 0;
11962         uint16_t j, num;
11963         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11964         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11965
11966         if (!add) {
11967                 if (memcmp(conf, rss_info,
11968                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11969                         i40e_pf_disable_rss(pf);
11970                         memset(rss_info, 0,
11971                                 sizeof(struct i40e_rte_flow_rss_conf));
11972                         return 0;
11973                 }
11974                 return -EINVAL;
11975         }
11976
11977         if (rss_info->num)
11978                 return -EINVAL;
11979
11980         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11981          * It's necessary to calculate the actual PF queues that are configured.
11982          */
11983         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11984                 num = i40e_pf_calc_configured_queues_num(pf);
11985         else
11986                 num = pf->dev_data->nb_rx_queues;
11987
11988         num = RTE_MIN(num, conf->num);
11989         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11990                         num);
11991
11992         if (num == 0) {
11993                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11994                 return -ENOTSUP;
11995         }
11996
11997         /* Fill in redirection table */
11998         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11999                 if (j == num)
12000                         j = 0;
12001                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
12002                         hw->func_caps.rss_table_entry_width) - 1));
12003                 if ((i & 3) == 3)
12004                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12005         }
12006
12007         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12008                 i40e_pf_disable_rss(pf);
12009                 return 0;
12010         }
12011         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12012                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12013                 /* Random default keys */
12014                 static uint32_t rss_key_default[] = {0x6b793944,
12015                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12016                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12017                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12018
12019                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12020                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12021                                                         sizeof(uint32_t);
12022         }
12023
12024         i40e_hw_rss_hash_set(pf, &rss_conf);
12025
12026         rte_memcpy(rss_info,
12027                 conf, sizeof(struct i40e_rte_flow_rss_conf));
12028
12029         return 0;
12030 }
12031
12032 RTE_INIT(i40e_init_log);
12033 static void
12034 i40e_init_log(void)
12035 {
12036         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12037         if (i40e_logtype_init >= 0)
12038                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12039         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12040         if (i40e_logtype_driver >= 0)
12041                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12042 }
12043
12044 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12045                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12046                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");