drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 260                                struct rte_eth_stats *stats);
 261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 262                                struct rte_eth_xstat *xstats, unsigned n);
 263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 264                                      struct rte_eth_xstat_name *xstats_names,
 265                                      unsigned limit);
 266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 268                                             uint16_t queue_id,
 269                                             uint8_t stat_idx,
 270                                             uint8_t is_rx);
 271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 272                                 char *fw_version, size_t fw_size);
 273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 274                               struct rte_eth_dev_info *dev_info);
 275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 276                                 uint16_t vlan_id,
 277                                 int on);
 278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 279                               enum rte_vlan_type vlan_type,
 280                               uint16_t tpid);
 281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 283                                       uint16_t queue,
 284                                       int on);
 285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 289                               struct rte_eth_fc_conf *fc_conf);
 290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 291                               struct rte_eth_fc_conf *fc_conf);
 292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 293                                        struct rte_eth_pfc_conf *pfc_conf);
 294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 295                             struct ether_addr *mac_addr,
 296                             uint32_t index,
 297                             uint32_t pool);
 298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 300                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 301                                     uint16_t reta_size);
 302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 303                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 304                                    uint16_t reta_size);
 305
 306 static int i40e_get_cap(struct i40e_hw *hw);
 307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 308 static int i40e_pf_setup(struct i40e_pf *pf);
 309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 314                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 315 static void i40e_stat_update_48(struct i40e_hw *hw,
 316                                uint32_t hireg,
 317                                uint32_t loreg,
 318                                bool offset_loaded,
 319                                uint64_t *offset,
 320                                uint64_t *stat);
 321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 322 static void i40e_dev_interrupt_handler(void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              uint16_t vlan);
 340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 342                                     struct rte_eth_rss_conf *rss_conf);
 343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 344                                       struct rte_eth_rss_conf *rss_conf);
 345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 346                                         struct rte_eth_udp_tunnel *udp_tunnel);
 347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 348                                         struct rte_eth_udp_tunnel *udp_tunnel);
 349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 351                                 enum rte_filter_op filter_op,
 352                                 void *arg);
 353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 354                                 enum rte_filter_type filter_type,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 358                                   struct rte_eth_dcb_info *dcb_info);
 359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 360 static void i40e_configure_registers(struct i40e_hw *hw);
 361 static void i40e_hw_init(struct rte_eth_dev *dev);
 362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 364                         struct rte_eth_mirror_conf *mirror_conf,
 365                         uint8_t sw_id, uint8_t on);
 366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 367
 368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 371                                            struct timespec *timestamp,
 372                                            uint32_t flags);
 373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 374                                            struct timespec *timestamp);
 375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 376
 377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 378
 379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 380                                    struct timespec *timestamp);
 381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 382                                     const struct timespec *timestamp);
 383
 384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 385                                          uint16_t queue_id);
 386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 387                                           uint16_t queue_id);
 388
 389 static int i40e_get_regs(struct rte_eth_dev *dev,
 390                          struct rte_dev_reg_info *regs);
 391
 392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 393
 394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 395                            struct rte_dev_eeprom_info *eeprom);
 396
 397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 398                                       struct ether_addr *mac_addr);
 399
 400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 401
 402 static int i40e_ethertype_filter_convert(
 403         const struct rte_eth_ethertype_filter *input,
 404         struct i40e_ethertype_filter *filter);
 405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 406                                    struct i40e_ethertype_filter *filter);
 407
 408 static int i40e_tunnel_filter_convert(
 409         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 410         struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 412                                 struct i40e_tunnel_filter *tunnel_filter);
 413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 414
 415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 417 static void i40e_filter_restore(struct i40e_pf *pf);
 418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 419
 420 int i40e_logtype_init;
 421 int i40e_logtype_driver;
 422
 423 static const struct rte_pci_id pci_id_i40e_map[] = {
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 453         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 454         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 455         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 456         .dev_set_link_up              = i40e_dev_set_link_up,
 457         .dev_set_link_down            = i40e_dev_set_link_down,
 458         .link_update                  = i40e_dev_link_update,
 459         .stats_get                    = i40e_dev_stats_get,
 460         .xstats_get                   = i40e_dev_xstats_get,
 461         .xstats_get_names             = i40e_dev_xstats_get_names,
 462         .stats_reset                  = i40e_dev_stats_reset,
 463         .xstats_reset                 = i40e_dev_stats_reset,
 464         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .rx_queue_count               = i40e_dev_rx_queue_count,
 482         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 483         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 484         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 485         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 486         .tx_queue_release             = i40e_dev_tx_queue_release,
 487         .dev_led_on                   = i40e_dev_led_on,
 488         .dev_led_off                  = i40e_dev_led_off,
 489         .flow_ctrl_get                = i40e_flow_ctrl_get,
 490         .flow_ctrl_set                = i40e_flow_ctrl_set,
 491         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 492         .mac_addr_add                 = i40e_macaddr_add,
 493         .mac_addr_remove              = i40e_macaddr_remove,
 494         .reta_update                  = i40e_dev_rss_reta_update,
 495         .reta_query                   = i40e_dev_rss_reta_query,
 496         .rss_hash_update              = i40e_dev_rss_hash_update,
 497         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 498         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 499         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 500         .filter_ctrl                  = i40e_dev_filter_ctrl,
 501         .rxq_info_get                 = i40e_rxq_info_get,
 502         .txq_info_get                 = i40e_txq_info_get,
 503         .mirror_rule_set              = i40e_mirror_rule_set,
 504         .mirror_rule_reset            = i40e_mirror_rule_reset,
 505         .timesync_enable              = i40e_timesync_enable,
 506         .timesync_disable             = i40e_timesync_disable,
 507         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 508         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 509         .get_dcb_info                 = i40e_dev_get_dcb_info,
 510         .timesync_adjust_time         = i40e_timesync_adjust_time,
 511         .timesync_read_time           = i40e_timesync_read_time,
 512         .timesync_write_time          = i40e_timesync_write_time,
 513         .get_reg                      = i40e_get_regs,
 514         .get_eeprom_length            = i40e_get_eeprom_length,
 515         .get_eeprom                   = i40e_get_eeprom,
 516         .mac_addr_set                 = i40e_set_default_mac_addr,
 517         .mtu_set                      = i40e_dev_mtu_set,
 518         .tm_ops_get                   = i40e_tm_ops_get,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         unsigned offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 535         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 536         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 537         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 538 };
 539
 540 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 541                 sizeof(rte_i40e_stats_strings[0]))
 542
 543 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 544         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 545                 tx_dropped_link_down)},
 546         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 547         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 548                 illegal_bytes)},
 549         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 550         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_local_faults)},
 552         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_remote_faults)},
 554         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 555                 rx_length_errors)},
 556         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 557         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 558         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 559         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 560         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 561         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_127)},
 563         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_255)},
 565         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_511)},
 567         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1023)},
 569         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1522)},
 571         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_big)},
 573         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_undersize)},
 575         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_oversize)},
 577         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 578                 mac_short_packet_dropped)},
 579         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_fragments)},
 581         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 582         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 583         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_127)},
 585         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_255)},
 587         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_511)},
 589         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1023)},
 591         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1522)},
 593         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_big)},
 595         {"rx_flow_director_atr_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 597         {"rx_flow_director_sb_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 599         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_status)},
 601         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_status)},
 603         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 tx_lpi_count)},
 605         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 rx_lpi_count)},
 607 };
 608
 609 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 610                 sizeof(rte_i40e_hw_port_strings[0]))
 611
 612 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 613         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xon_rx)},
 615         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xoff_rx)},
 617 };
 618
 619 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 620                 sizeof(rte_i40e_rxq_prio_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_tx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_tx)},
 627         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xon_2_xoff)},
 629 };
 630
 631 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 632                 sizeof(rte_i40e_txq_prio_strings[0]))
 633
 634 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         return rte_eth_dev_pci_generic_probe(pci_dev,
 638                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 639 }
 640
 641 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 642 {
 643         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 644 }
 645
 646 static struct rte_pci_driver rte_i40e_pmd = {
 647         .id_table = pci_id_i40e_map,
 648         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 649         .probe = eth_i40e_pci_probe,
 650         .remove = eth_i40e_pci_remove,
 651 };
 652
 653 static inline int
 654 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 655                                      struct rte_eth_link *link)
 656 {
 657         struct rte_eth_link *dst = link;
 658         struct rte_eth_link *src = &(dev->data->dev_link);
 659
 660         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 661                                         *(uint64_t *)src) == 0)
 662                 return -1;
 663
 664         return 0;
 665 }
 666
 667 static inline int
 668 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 669                                       struct rte_eth_link *link)
 670 {
 671         struct rte_eth_link *dst = &(dev->data->dev_link);
 672         struct rte_eth_link *src = link;
 673
 674         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 675                                         *(uint64_t *)src) == 0)
 676                 return -1;
 677
 678         return 0;
 679 }
 680
 681 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 682 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 683 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 684
 685 #ifndef I40E_GLQF_ORT
 686 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 687 #endif
 688 #ifndef I40E_GLQF_PIT
 689 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 690 #endif
 691 #ifndef I40E_GLQF_L3_MAP
 692 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 693 #endif
 694
 695 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 696 {
 697         /*
 698          * Initialize registers for flexible payload, which should be set by NVM.
 699          * This should be removed from code once it is fixed in NVM.
 700          */
 701         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 702         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 711         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 712         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 713
 714         /* Initialize registers for parsing packet type of QinQ */
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 716         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 717 }
 718
 719 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 720
 721 /*
 722  * Add a ethertype filter to drop all flow control frames transmitted
 723  * from VSIs.
 724 */
 725 static void
 726 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 727 {
 728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 729         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 730                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 731                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 732         int ret;
 733
 734         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 735                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 736                                 pf->main_vsi_seid, 0,
 737                                 TRUE, NULL, NULL);
 738         if (ret)
 739                 PMD_INIT_LOG(ERR,
 740                         "Failed to add filter to drop flow control frames from VSIs.");
 741 }
 742
 743 static int
 744 floating_veb_list_handler(__rte_unused const char *key,
 745                           const char *floating_veb_value,
 746                           void *opaque)
 747 {
 748         int idx = 0;
 749         unsigned int count = 0;
 750         char *end = NULL;
 751         int min, max;
 752         bool *vf_floating_veb = opaque;
 753
 754         while (isblank(*floating_veb_value))
 755                 floating_veb_value++;
 756
 757         /* Reset floating VEB configuration for VFs */
 758         for (idx = 0; idx < I40E_MAX_VF; idx++)
 759                 vf_floating_veb[idx] = false;
 760
 761         min = I40E_MAX_VF;
 762         do {
 763                 while (isblank(*floating_veb_value))
 764                         floating_veb_value++;
 765                 if (*floating_veb_value == '\0')
 766                         return -1;
 767                 errno = 0;
 768                 idx = strtoul(floating_veb_value, &end, 10);
 769                 if (errno || end == NULL)
 770                         return -1;
 771                 while (isblank(*end))
 772                         end++;
 773                 if (*end == '-') {
 774                         min = idx;
 775                 } else if ((*end == ';') || (*end == '\0')) {
 776                         max = idx;
 777                         if (min == I40E_MAX_VF)
 778                                 min = idx;
 779                         if (max >= I40E_MAX_VF)
 780                                 max = I40E_MAX_VF - 1;
 781                         for (idx = min; idx <= max; idx++) {
 782                                 vf_floating_veb[idx] = true;
 783                                 count++;
 784                         }
 785                         min = I40E_MAX_VF;
 786                 } else {
 787                         return -1;
 788                 }
 789                 floating_veb_value = end + 1;
 790         } while (*end != '\0');
 791
 792         if (count == 0)
 793                 return -1;
 794
 795         return 0;
 796 }
 797
 798 static void
 799 config_vf_floating_veb(struct rte_devargs *devargs,
 800                        uint16_t floating_veb,
 801                        bool *vf_floating_veb)
 802 {
 803         struct rte_kvargs *kvlist;
 804         int i;
 805         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 806
 807         if (!floating_veb)
 808                 return;
 809         /* All the VFs attach to the floating VEB by default
 810          * when the floating VEB is enabled.
 811          */
 812         for (i = 0; i < I40E_MAX_VF; i++)
 813                 vf_floating_veb[i] = true;
 814
 815         if (devargs == NULL)
 816                 return;
 817
 818         kvlist = rte_kvargs_parse(devargs->args, NULL);
 819         if (kvlist == NULL)
 820                 return;
 821
 822         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 823                 rte_kvargs_free(kvlist);
 824                 return;
 825         }
 826         /* When the floating_veb_list parameter exists, all the VFs
 827          * will attach to the legacy VEB firstly, then configure VFs
 828          * to the floating VEB according to the floating_veb_list.
 829          */
 830         if (rte_kvargs_process(kvlist, floating_veb_list,
 831                                floating_veb_list_handler,
 832                                vf_floating_veb) < 0) {
 833                 rte_kvargs_free(kvlist);
 834                 return;
 835         }
 836         rte_kvargs_free(kvlist);
 837 }
 838
 839 static int
 840 i40e_check_floating_handler(__rte_unused const char *key,
 841                             const char *value,
 842                             __rte_unused void *opaque)
 843 {
 844         if (strcmp(value, "1"))
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static int
 851 is_floating_veb_supported(struct rte_devargs *devargs)
 852 {
 853         struct rte_kvargs *kvlist;
 854         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 855
 856         if (devargs == NULL)
 857                 return 0;
 858
 859         kvlist = rte_kvargs_parse(devargs->args, NULL);
 860         if (kvlist == NULL)
 861                 return 0;
 862
 863         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         /* Floating VEB is enabled when there's key-value:
 868          * enable_floating_veb=1
 869          */
 870         if (rte_kvargs_process(kvlist, floating_veb_key,
 871                                i40e_check_floating_handler, NULL) < 0) {
 872                 rte_kvargs_free(kvlist);
 873                 return 0;
 874         }
 875         rte_kvargs_free(kvlist);
 876
 877         return 1;
 878 }
 879
 880 static void
 881 config_floating_veb(struct rte_eth_dev *dev)
 882 {
 883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 886
 887         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 888
 889         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 890                 pf->floating_veb =
 891                         is_floating_veb_supported(pci_dev->device.devargs);
 892                 config_vf_floating_veb(pci_dev->device.devargs,
 893                                        pf->floating_veb,
 894                                        pf->floating_veb_list);
 895         } else {
 896                 pf->floating_veb = false;
 897         }
 898 }
 899
 900 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 901 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 902
 903 static int
 904 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 905 {
 906         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 907         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 908         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 909         int ret;
 910
 911         struct rte_hash_parameters ethertype_hash_params = {
 912                 .name = ethertype_hash_name,
 913                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 914                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 915                 .hash_func = rte_hash_crc,
 916                 .hash_func_init_val = 0,
 917                 .socket_id = rte_socket_id(),
 918         };
 919
 920         /* Initialize ethertype filter rule list and hash */
 921         TAILQ_INIT(&ethertype_rule->ethertype_list);
 922         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 923                  "ethertype_%s", dev->device->name);
 924         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 925         if (!ethertype_rule->hash_table) {
 926                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 927                 return -EINVAL;
 928         }
 929         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 930                                        sizeof(struct i40e_ethertype_filter *) *
 931                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 932                                        0);
 933         if (!ethertype_rule->hash_map) {
 934                 PMD_INIT_LOG(ERR,
 935                              "Failed to allocate memory for ethertype hash map!");
 936                 ret = -ENOMEM;
 937                 goto err_ethertype_hash_map_alloc;
 938         }
 939
 940         return 0;
 941
 942 err_ethertype_hash_map_alloc:
 943         rte_hash_free(ethertype_rule->hash_table);
 944
 945         return ret;
 946 }
 947
 948 static int
 949 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 950 {
 951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 952         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 953         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 954         int ret;
 955
 956         struct rte_hash_parameters tunnel_hash_params = {
 957                 .name = tunnel_hash_name,
 958                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 959                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 960                 .hash_func = rte_hash_crc,
 961                 .hash_func_init_val = 0,
 962                 .socket_id = rte_socket_id(),
 963         };
 964
 965         /* Initialize tunnel filter rule list and hash */
 966         TAILQ_INIT(&tunnel_rule->tunnel_list);
 967         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 968                  "tunnel_%s", dev->device->name);
 969         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 970         if (!tunnel_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 972                 return -EINVAL;
 973         }
 974         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 975                                     sizeof(struct i40e_tunnel_filter *) *
 976                                     I40E_MAX_TUNNEL_FILTER_NUM,
 977                                     0);
 978         if (!tunnel_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for tunnel hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_tunnel_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_tunnel_hash_map_alloc:
 988         rte_hash_free(tunnel_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_fdir_info *fdir_info = &pf->fdir;
 998         char fdir_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters fdir_hash_params = {
1002                 .name = fdir_hash_name,
1003                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1004                 .key_len = sizeof(struct rte_eth_fdir_input),
1005                 .hash_func = rte_hash_crc,
1006                 .hash_func_init_val = 0,
1007                 .socket_id = rte_socket_id(),
1008         };
1009
1010         /* Initialize flow director filter rule list and hash */
1011         TAILQ_INIT(&fdir_info->fdir_list);
1012         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1013                  "fdir_%s", dev->device->name);
1014         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1015         if (!fdir_info->hash_table) {
1016                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1017                 return -EINVAL;
1018         }
1019         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1020                                           sizeof(struct i40e_fdir_filter *) *
1021                                           I40E_MAX_FDIR_FILTER_NUM,
1022                                           0);
1023         if (!fdir_info->hash_map) {
1024                 PMD_INIT_LOG(ERR,
1025                              "Failed to allocate memory for fdir hash map!");
1026                 ret = -ENOMEM;
1027                 goto err_fdir_hash_map_alloc;
1028         }
1029         return 0;
1030
1031 err_fdir_hash_map_alloc:
1032         rte_hash_free(fdir_info->hash_table);
1033
1034         return ret;
1035 }
1036
1037 static int
1038 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 {
1040         struct rte_pci_device *pci_dev;
1041         struct rte_intr_handle *intr_handle;
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1044         struct i40e_vsi *vsi;
1045         int ret;
1046         uint32_t len;
1047         uint8_t aq_fail = 0;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         dev->dev_ops = &i40e_eth_dev_ops;
1052         dev->rx_pkt_burst = i40e_recv_pkts;
1053         dev->tx_pkt_burst = i40e_xmit_pkts;
1054         dev->tx_pkt_prepare = i40e_prep_pkts;
1055
1056         /* for secondary processes, we don't initialise any further as primary
1057          * has already done this work. Only check we don't need a different
1058          * RX function */
1059         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1060                 i40e_set_rx_function(dev);
1061                 i40e_set_tx_function(dev);
1062                 return 0;
1063         }
1064         i40e_set_default_ptype_table(dev);
1065         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1066         intr_handle = &pci_dev->intr_handle;
1067
1068         rte_eth_copy_pci_info(dev, pci_dev);
1069         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070
1071         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         pf->adapter->eth_dev = dev;
1073         pf->dev_data = dev->data;
1074
1075         hw->back = I40E_PF_TO_ADAPTER(pf);
1076         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1077         if (!hw->hw_addr) {
1078                 PMD_INIT_LOG(ERR,
1079                         "Hardware is not available, as address is NULL");
1080                 return -ENODEV;
1081         }
1082
1083         hw->vendor_id = pci_dev->id.vendor_id;
1084         hw->device_id = pci_dev->id.device_id;
1085         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1086         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1087         hw->bus.device = pci_dev->addr.devid;
1088         hw->bus.func = pci_dev->addr.function;
1089         hw->adapter_stopped = 0;
1090
1091         /* Make sure all is clean before doing PF reset */
1092         i40e_clear_hw(hw);
1093
1094         /* Initialize the hardware */
1095         i40e_hw_init(dev);
1096
1097         /* Reset here to make sure all is clean for each PF */
1098         ret = i40e_pf_reset(hw);
1099         if (ret) {
1100                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1101                 return ret;
1102         }
1103
1104         /* Initialize the shared code (base driver) */
1105         ret = i40e_init_shared_code(hw);
1106         if (ret) {
1107                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1108                 return ret;
1109         }
1110
1111         /*
1112          * To work around the NVM issue, initialize registers
1113          * for flexible payload and packet type of QinQ by
1114          * software. It should be removed once issues are fixed
1115          * in NVM.
1116          */
1117         i40e_GLQF_reg_init(hw);
1118
1119         /* Initialize the input set for filters (hash and fd) to default value */
1120         i40e_filter_input_set_init(pf);
1121
1122         /* Initialize the parameters for adminq */
1123         i40e_init_adminq_parameter(hw);
1124         ret = i40e_init_adminq(hw);
1125         if (ret != I40E_SUCCESS) {
1126                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1127                 return -EIO;
1128         }
1129         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1130                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1131                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1132                      ((hw->nvm.version >> 12) & 0xf),
1133                      ((hw->nvm.version >> 4) & 0xff),
1134                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135
1136         /* initialise the L3_MAP register */
1137         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1138                                    0x00000028,  NULL);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141
1142         /* Need the special FW version to support floating VEB */
1143         config_floating_veb(dev);
1144         /* Clear PXE mode */
1145         i40e_clear_pxe_mode(hw);
1146         i40e_dev_sync_phy_type(hw);
1147
1148         /*
1149          * On X710, performance number is far from the expectation on recent
1150          * firmware versions. The fix for this issue may not be integrated in
1151          * the following firmware version. So the workaround in software driver
1152          * is needed. It needs to modify the initial values of 3 internal only
1153          * registers. Note that the workaround can be removed when it is fixed
1154          * in firmware in the future.
1155          */
1156         i40e_configure_registers(hw);
1157
1158         /* Get hw capabilities */
1159         ret = i40e_get_cap(hw);
1160         if (ret != I40E_SUCCESS) {
1161                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1162                 goto err_get_capabilities;
1163         }
1164
1165         /* Initialize parameters for PF */
1166         ret = i40e_pf_parameter_init(dev);
1167         if (ret != 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1169                 goto err_parameter_init;
1170         }
1171
1172         /* Initialize the queue management */
1173         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1176                 goto err_qp_pool_init;
1177         }
1178         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1179                                 hw->func_caps.num_msix_vectors - 1);
1180         if (ret < 0) {
1181                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1182                 goto err_msix_pool_init;
1183         }
1184
1185         /* Initialize lan hmc */
1186         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1187                                 hw->func_caps.num_rx_qp, 0, 0);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1190                 goto err_init_lan_hmc;
1191         }
1192
1193         /* Configure lan hmc */
1194         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1197                 goto err_configure_lan_hmc;
1198         }
1199
1200         /* Get and check the mac address */
1201         i40e_get_mac_addr(hw, hw->mac.addr);
1202         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "mac address is not valid");
1204                 ret = -EIO;
1205                 goto err_get_mac_addr;
1206         }
1207         /* Copy the permanent MAC address */
1208         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1209                         (struct ether_addr *) hw->mac.perm_addr);
1210
1211         /* Disable flow control */
1212         hw->fc.requested_mode = I40E_FC_NONE;
1213         i40e_set_fc(hw, &aq_fail, TRUE);
1214
1215         /* Set the global registers with default ether type value */
1216         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1217         if (ret != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR,
1219                         "Failed to set the default outer VLAN ether type");
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* PF setup, which includes VSI setup */
1224         ret = i40e_pf_setup(pf);
1225         if (ret) {
1226                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1227                 goto err_setup_pf_switch;
1228         }
1229
1230         /* reset all stats of the device, including pf and main vsi */
1231         i40e_dev_stats_reset(dev);
1232
1233         vsi = pf->main_vsi;
1234
1235         /* Disable double vlan by default */
1236         i40e_vsi_config_double_vlan(vsi, FALSE);
1237
1238         /* Disable S-TAG identification when floating_veb is disabled */
1239         if (!pf->floating_veb) {
1240                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1241                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1242                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1243                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244                 }
1245         }
1246
1247         if (!vsi->max_macaddrs)
1248                 len = ETHER_ADDR_LEN;
1249         else
1250                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1251
1252         /* Should be after VSI initialized */
1253         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1254         if (!dev->data->mac_addrs) {
1255                 PMD_INIT_LOG(ERR,
1256                         "Failed to allocated memory for storing mac address");
1257                 goto err_mac_alloc;
1258         }
1259         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1260                                         &dev->data->mac_addrs[0]);
1261
1262         /* Init dcb to sw mode by default */
1263         ret = i40e_dcb_init_configure(dev, TRUE);
1264         if (ret != I40E_SUCCESS) {
1265                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1266                 pf->flags &= ~I40E_FLAG_DCB;
1267         }
1268         /* Update HW struct after DCB configuration */
1269         i40e_get_cap(hw);
1270
1271         /* initialize pf host driver to setup SRIOV resource if applicable */
1272         i40e_pf_host_init(dev);
1273
1274         /* register callback func to eal lib */
1275         rte_intr_callback_register(intr_handle,
1276                                    i40e_dev_interrupt_handler, dev);
1277
1278         /* configure and enable device interrupt */
1279         i40e_pf_config_irq0(hw, TRUE);
1280         i40e_pf_enable_irq0(hw);
1281
1282         /* enable uio intr after callback register */
1283         rte_intr_enable(intr_handle);
1284         /*
1285          * Add an ethertype filter to drop all flow control frames transmitted
1286          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287          * frames to wire.
1288          */
1289         i40e_add_tx_flow_control_drop_filter(pf);
1290
1291         /* Set the max frame size to 0x2600 by default,
1292          * in case other drivers changed the default value.
1293          */
1294         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1295
1296         /* initialize mirror rule list */
1297         TAILQ_INIT(&pf->mirror_list);
1298
1299         /* initialize Traffic Manager configuration */
1300         i40e_tm_conf_init(dev);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         return 0;
1313
1314 err_init_fdir_filter_list:
1315         rte_free(pf->tunnel.hash_table);
1316         rte_free(pf->tunnel.hash_map);
1317 err_init_tunnel_filter_list:
1318         rte_free(pf->ethertype.hash_table);
1319         rte_free(pf->ethertype.hash_map);
1320 err_init_ethtype_filter_list:
1321         rte_free(dev->data->mac_addrs);
1322 err_mac_alloc:
1323         i40e_vsi_release(pf->main_vsi);
1324 err_setup_pf_switch:
1325 err_get_mac_addr:
1326 err_configure_lan_hmc:
1327         (void)i40e_shutdown_lan_hmc(hw);
1328 err_init_lan_hmc:
1329         i40e_res_pool_destroy(&pf->msix_pool);
1330 err_msix_pool_init:
1331         i40e_res_pool_destroy(&pf->qp_pool);
1332 err_qp_pool_init:
1333 err_parameter_init:
1334 err_get_capabilities:
1335         (void)i40e_shutdown_adminq(hw);
1336
1337         return ret;
1338 }
1339
1340 static void
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1342 {
1343         struct i40e_ethertype_filter *p_ethertype;
1344         struct i40e_ethertype_rule *ethertype_rule;
1345
1346         ethertype_rule = &pf->ethertype;
1347         /* Remove all ethertype filter rules and hash */
1348         if (ethertype_rule->hash_map)
1349                 rte_free(ethertype_rule->hash_map);
1350         if (ethertype_rule->hash_table)
1351                 rte_hash_free(ethertype_rule->hash_table);
1352
1353         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1354                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1355                              p_ethertype, rules);
1356                 rte_free(p_ethertype);
1357         }
1358 }
1359
1360 static void
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1362 {
1363         struct i40e_tunnel_filter *p_tunnel;
1364         struct i40e_tunnel_rule *tunnel_rule;
1365
1366         tunnel_rule = &pf->tunnel;
1367         /* Remove all tunnel director rules and hash */
1368         if (tunnel_rule->hash_map)
1369                 rte_free(tunnel_rule->hash_map);
1370         if (tunnel_rule->hash_table)
1371                 rte_hash_free(tunnel_rule->hash_table);
1372
1373         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1375                 rte_free(p_tunnel);
1376         }
1377 }
1378
1379 static void
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1381 {
1382         struct i40e_fdir_filter *p_fdir;
1383         struct i40e_fdir_info *fdir_info;
1384
1385         fdir_info = &pf->fdir;
1386         /* Remove all flow director rules and hash */
1387         if (fdir_info->hash_map)
1388                 rte_free(fdir_info->hash_map);
1389         if (fdir_info->hash_table)
1390                 rte_hash_free(fdir_info->hash_table);
1391
1392         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1394                 rte_free(p_fdir);
1395         }
1396 }
1397
1398 static int
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1400 {
1401         struct i40e_pf *pf;
1402         struct rte_pci_device *pci_dev;
1403         struct rte_intr_handle *intr_handle;
1404         struct i40e_hw *hw;
1405         struct i40e_filter_control_settings settings;
1406         struct rte_flow *p_flow;
1407         int ret;
1408         uint8_t aq_fail = 0;
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1413                 return 0;
1414
1415         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1418         intr_handle = &pci_dev->intr_handle;
1419
1420         if (hw->adapter_stopped == 0)
1421                 i40e_dev_close(dev);
1422
1423         dev->dev_ops = NULL;
1424         dev->rx_pkt_burst = NULL;
1425         dev->tx_pkt_burst = NULL;
1426
1427         /* Clear PXE mode */
1428         i40e_clear_pxe_mode(hw);
1429
1430         /* Unconfigure filter control */
1431         memset(&settings, 0, sizeof(settings));
1432         ret = i40e_set_filter_control(hw, &settings);
1433         if (ret)
1434                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1435                                         ret);
1436
1437         /* Disable flow control */
1438         hw->fc.requested_mode = I40E_FC_NONE;
1439         i40e_set_fc(hw, &aq_fail, TRUE);
1440
1441         /* uninitialize pf host driver */
1442         i40e_pf_host_uninit(dev);
1443
1444         rte_free(dev->data->mac_addrs);
1445         dev->data->mac_addrs = NULL;
1446
1447         /* disable uio intr before callback unregister */
1448         rte_intr_disable(intr_handle);
1449
1450         /* register callback func to eal lib */
1451         rte_intr_callback_unregister(intr_handle,
1452                                      i40e_dev_interrupt_handler, dev);
1453
1454         i40e_rm_ethtype_filter_list(pf);
1455         i40e_rm_tunnel_filter_list(pf);
1456         i40e_rm_fdir_filter_list(pf);
1457
1458         /* Remove all flows */
1459         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1461                 rte_free(p_flow);
1462         }
1463
1464         /* Remove all Traffic Manager configuration */
1465         i40e_tm_conf_uninit(dev);
1466
1467         return 0;
1468 }
1469
1470 static int
1471 i40e_dev_configure(struct rte_eth_dev *dev)
1472 {
1473         struct i40e_adapter *ad =
1474                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1475         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1477         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1478         int i, ret;
1479
1480         ret = i40e_dev_sync_phy_type(hw);
1481         if (ret)
1482                 return ret;
1483
1484         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1485          * bulk allocation or vector Rx preconditions we will reset it.
1486          */
1487         ad->rx_bulk_alloc_allowed = true;
1488         ad->rx_vec_allowed = true;
1489         ad->tx_simple_allowed = true;
1490         ad->tx_vec_allowed = true;
1491
1492         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1493                 ret = i40e_fdir_setup(pf);
1494                 if (ret != I40E_SUCCESS) {
1495                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1496                         return -ENOTSUP;
1497                 }
1498                 ret = i40e_fdir_configure(dev);
1499                 if (ret < 0) {
1500                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1501                         goto err;
1502                 }
1503         } else
1504                 i40e_fdir_teardown(pf);
1505
1506         ret = i40e_dev_init_vlan(dev);
1507         if (ret < 0)
1508                 goto err;
1509
1510         /* VMDQ setup.
1511          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1512          *  RSS setting have different requirements.
1513          *  General PMD driver call sequence are NIC init, configure,
1514          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1515          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1516          *  applicable. So, VMDQ setting has to be done before
1517          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1518          *  For RSS setting, it will try to calculate actual configured RX queue
1519          *  number, which will be available after rx_queue_setup(). dev_start()
1520          *  function is good to place RSS setup.
1521          */
1522         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1523                 ret = i40e_vmdq_setup(dev);
1524                 if (ret)
1525                         goto err;
1526         }
1527
1528         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1529                 ret = i40e_dcb_setup(dev);
1530                 if (ret) {
1531                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1532                         goto err_dcb;
1533                 }
1534         }
1535
1536         TAILQ_INIT(&pf->flow_list);
1537
1538         return 0;
1539
1540 err_dcb:
1541         /* need to release vmdq resource if exists */
1542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1543                 i40e_vsi_release(pf->vmdq[i].vsi);
1544                 pf->vmdq[i].vsi = NULL;
1545         }
1546         rte_free(pf->vmdq);
1547         pf->vmdq = NULL;
1548 err:
1549         /* need to release fdir resource if exists */
1550         i40e_fdir_teardown(pf);
1551         return ret;
1552 }
1553
1554 void
1555 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1556 {
1557         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1558         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1559         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1561         uint16_t msix_vect = vsi->msix_intr;
1562         uint16_t i;
1563
1564         for (i = 0; i < vsi->nb_qps; i++) {
1565                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1566                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1567                 rte_wmb();
1568         }
1569
1570         if (vsi->type != I40E_VSI_SRIOV) {
1571                 if (!rte_intr_allow_others(intr_handle)) {
1572                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1573                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1574                         I40E_WRITE_REG(hw,
1575                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1576                                        0);
1577                 } else {
1578                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1579                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1580                         I40E_WRITE_REG(hw,
1581                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1582                                                        msix_vect - 1), 0);
1583                 }
1584         } else {
1585                 uint32_t reg;
1586                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1587                         vsi->user_param + (msix_vect - 1);
1588
1589                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1590                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1591         }
1592         I40E_WRITE_FLUSH(hw);
1593 }
1594
1595 static void
1596 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1597                        int base_queue, int nb_queue)
1598 {
1599         int i;
1600         uint32_t val;
1601         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1602
1603         /* Bind all RX queues to allocated MSIX interrupt */
1604         for (i = 0; i < nb_queue; i++) {
1605                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1606                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1607                         ((base_queue + i + 1) <<
1608                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1609                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1610                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1611
1612                 if (i == nb_queue - 1)
1613                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1614                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1615         }
1616
1617         /* Write first RX queue to Link list register as the head element */
1618         if (vsi->type != I40E_VSI_SRIOV) {
1619                 uint16_t interval =
1620                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1621
1622                 if (msix_vect == I40E_MISC_VEC_ID) {
1623                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1624                                        (base_queue <<
1625                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1628                         I40E_WRITE_REG(hw,
1629                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1630                                        interval);
1631                 } else {
1632                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1633                                        (base_queue <<
1634                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1635                                        (0x0 <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1637                         I40E_WRITE_REG(hw,
1638                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1639                                                        msix_vect - 1),
1640                                        interval);
1641                 }
1642         } else {
1643                 uint32_t reg;
1644
1645                 if (msix_vect == I40E_MISC_VEC_ID) {
1646                         I40E_WRITE_REG(hw,
1647                                        I40E_VPINT_LNKLST0(vsi->user_param),
1648                                        (base_queue <<
1649                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1652                 } else {
1653                         /* num_msix_vectors_vf needs to minus irq0 */
1654                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1655                                 vsi->user_param + (msix_vect - 1);
1656
1657                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1658                                        (base_queue <<
1659                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660                                        (0x0 <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662                 }
1663         }
1664
1665         I40E_WRITE_FLUSH(hw);
1666 }
1667
1668 void
1669 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1670 {
1671         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1674         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1675         uint16_t msix_vect = vsi->msix_intr;
1676         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1677         uint16_t queue_idx = 0;
1678         int record = 0;
1679         uint32_t val;
1680         int i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685         }
1686
1687         /* INTENA flag is not auto-cleared for interrupt */
1688         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1689         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1690                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1691                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1692         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1693
1694         /* VF bind interrupt */
1695         if (vsi->type == I40E_VSI_SRIOV) {
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue, vsi->nb_qps);
1698                 return;
1699         }
1700
1701         /* PF & VMDq bind interrupt */
1702         if (rte_intr_dp_is_en(intr_handle)) {
1703                 if (vsi->type == I40E_VSI_MAIN) {
1704                         queue_idx = 0;
1705                         record = 1;
1706                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1707                         struct i40e_vsi *main_vsi =
1708                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1709                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1710                         record = 1;
1711                 }
1712         }
1713
1714         for (i = 0; i < vsi->nb_used_qps; i++) {
1715                 if (nb_msix <= 1) {
1716                         if (!rte_intr_allow_others(intr_handle))
1717                                 /* allow to share MISC_VEC_ID */
1718                                 msix_vect = I40E_MISC_VEC_ID;
1719
1720                         /* no enough msix_vect, map all to one */
1721                         __vsi_queues_bind_intr(vsi, msix_vect,
1722                                                vsi->base_queue + i,
1723                                                vsi->nb_used_qps - i);
1724                         for (; !!record && i < vsi->nb_used_qps; i++)
1725                                 intr_handle->intr_vec[queue_idx + i] =
1726                                         msix_vect;
1727                         break;
1728                 }
1729                 /* 1:1 queue/msix_vect mapping */
1730                 __vsi_queues_bind_intr(vsi, msix_vect,
1731                                        vsi->base_queue + i, 1);
1732                 if (!!record)
1733                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1734
1735                 msix_vect++;
1736                 nb_msix--;
1737         }
1738 }
1739
1740 static void
1741 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1742 {
1743         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1744         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1745         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1747         uint16_t interval = i40e_calc_itr_interval(\
1748                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1749         uint16_t msix_intr, i;
1750
1751         if (rte_intr_allow_others(intr_handle))
1752                 for (i = 0; i < vsi->nb_msix; i++) {
1753                         msix_intr = vsi->msix_intr + i;
1754                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1755                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1756                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1757                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1758                                 (interval <<
1759                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1760                 }
1761         else
1762                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1763                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1764                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1765                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1766                                (interval <<
1767                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1768
1769         I40E_WRITE_FLUSH(hw);
1770 }
1771
1772 static void
1773 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1774 {
1775         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1776         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1777         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1778         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779         uint16_t msix_intr, i;
1780
1781         if (rte_intr_allow_others(intr_handle))
1782                 for (i = 0; i < vsi->nb_msix; i++) {
1783                         msix_intr = vsi->msix_intr + i;
1784                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1785                                        0);
1786                 }
1787         else
1788                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1789
1790         I40E_WRITE_FLUSH(hw);
1791 }
1792
1793 static inline uint8_t
1794 i40e_parse_link_speeds(uint16_t link_speeds)
1795 {
1796         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1797
1798         if (link_speeds & ETH_LINK_SPEED_40G)
1799                 link_speed |= I40E_LINK_SPEED_40GB;
1800         if (link_speeds & ETH_LINK_SPEED_25G)
1801                 link_speed |= I40E_LINK_SPEED_25GB;
1802         if (link_speeds & ETH_LINK_SPEED_20G)
1803                 link_speed |= I40E_LINK_SPEED_20GB;
1804         if (link_speeds & ETH_LINK_SPEED_10G)
1805                 link_speed |= I40E_LINK_SPEED_10GB;
1806         if (link_speeds & ETH_LINK_SPEED_1G)
1807                 link_speed |= I40E_LINK_SPEED_1GB;
1808         if (link_speeds & ETH_LINK_SPEED_100M)
1809                 link_speed |= I40E_LINK_SPEED_100MB;
1810
1811         return link_speed;
1812 }
1813
1814 static int
1815 i40e_phy_conf_link(struct i40e_hw *hw,
1816                    uint8_t abilities,
1817                    uint8_t force_speed)
1818 {
1819         enum i40e_status_code status;
1820         struct i40e_aq_get_phy_abilities_resp phy_ab;
1821         struct i40e_aq_set_phy_config phy_conf;
1822         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1823                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1824                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1825                         I40E_AQ_PHY_FLAG_LOW_POWER;
1826         const uint8_t advt = I40E_LINK_SPEED_40GB |
1827                         I40E_LINK_SPEED_25GB |
1828                         I40E_LINK_SPEED_10GB |
1829                         I40E_LINK_SPEED_1GB |
1830                         I40E_LINK_SPEED_100MB;
1831         int ret = -ENOTSUP;
1832
1833
1834         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1835                                               NULL);
1836         if (status)
1837                 return ret;
1838
1839         memset(&phy_conf, 0, sizeof(phy_conf));
1840
1841         /* bits 0-2 use the values from get_phy_abilities_resp */
1842         abilities &= ~mask;
1843         abilities |= phy_ab.abilities & mask;
1844
1845         /* update ablities and speed */
1846         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1847                 phy_conf.link_speed = advt;
1848         else
1849                 phy_conf.link_speed = force_speed;
1850
1851         phy_conf.abilities = abilities;
1852
1853         /* use get_phy_abilities_resp value for the rest */
1854         phy_conf.phy_type = phy_ab.phy_type;
1855         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1856         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1857         phy_conf.eee_capability = phy_ab.eee_capability;
1858         phy_conf.eeer = phy_ab.eeer_val;
1859         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1860
1861         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1862                     phy_ab.abilities, phy_ab.link_speed);
1863         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1864                     phy_conf.abilities, phy_conf.link_speed);
1865
1866         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1867         if (status)
1868                 return ret;
1869
1870         return I40E_SUCCESS;
1871 }
1872
1873 static int
1874 i40e_apply_link_speed(struct rte_eth_dev *dev)
1875 {
1876         uint8_t speed;
1877         uint8_t abilities = 0;
1878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1879         struct rte_eth_conf *conf = &dev->data->dev_conf;
1880
1881         speed = i40e_parse_link_speeds(conf->link_speeds);
1882         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1883         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1884                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1886
1887         /* Skip changing speed on 40G interfaces, FW does not support */
1888         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1889                 speed =  I40E_LINK_SPEED_UNKNOWN;
1890                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1891         }
1892
1893         return i40e_phy_conf_link(hw, abilities, speed);
1894 }
1895
1896 static int
1897 i40e_dev_start(struct rte_eth_dev *dev)
1898 {
1899         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct i40e_vsi *main_vsi = pf->main_vsi;
1902         int ret, i;
1903         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1904         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1905         uint32_t intr_vector = 0;
1906         struct i40e_vsi *vsi;
1907
1908         hw->adapter_stopped = 0;
1909
1910         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1911                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1912                              dev->data->port_id);
1913                 return -EINVAL;
1914         }
1915
1916         rte_intr_disable(intr_handle);
1917
1918         if ((rte_intr_cap_multiple(intr_handle) ||
1919              !RTE_ETH_DEV_SRIOV(dev).active) &&
1920             dev->data->dev_conf.intr_conf.rxq != 0) {
1921                 intr_vector = dev->data->nb_rx_queues;
1922                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1923                 if (ret)
1924                         return ret;
1925         }
1926
1927         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1928                 intr_handle->intr_vec =
1929                         rte_zmalloc("intr_vec",
1930                                     dev->data->nb_rx_queues * sizeof(int),
1931                                     0);
1932                 if (!intr_handle->intr_vec) {
1933                         PMD_INIT_LOG(ERR,
1934                                 "Failed to allocate %d rx_queues intr_vec",
1935                                 dev->data->nb_rx_queues);
1936                         return -ENOMEM;
1937                 }
1938         }
1939
1940         /* Initialize VSI */
1941         ret = i40e_dev_rxtx_init(pf);
1942         if (ret != I40E_SUCCESS) {
1943                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1944                 goto err_up;
1945         }
1946
1947         /* Map queues with MSIX interrupt */
1948         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1949                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1950         i40e_vsi_queues_bind_intr(main_vsi);
1951         i40e_vsi_enable_queues_intr(main_vsi);
1952
1953         /* Map VMDQ VSI queues with MSIX interrupt */
1954         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1956                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1957                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1958         }
1959
1960         /* enable FDIR MSIX interrupt */
1961         if (pf->fdir.fdir_vsi) {
1962                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1963                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1964         }
1965
1966         /* Enable all queues which have been configured */
1967         ret = i40e_dev_switch_queues(pf, TRUE);
1968         if (ret != I40E_SUCCESS) {
1969                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1970                 goto err_up;
1971         }
1972
1973         /* Enable receiving broadcast packets */
1974         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1975         if (ret != I40E_SUCCESS)
1976                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977
1978         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1979                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1980                                                 true, NULL);
1981                 if (ret != I40E_SUCCESS)
1982                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1983         }
1984
1985         /* Enable the VLAN promiscuous mode. */
1986         if (pf->vfs) {
1987                 for (i = 0; i < pf->vf_num; i++) {
1988                         vsi = pf->vfs[i].vsi;
1989                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1990                                                      true, NULL);
1991                 }
1992         }
1993
1994         /* Apply link configure */
1995         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1996                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1997                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1998                                 ETH_LINK_SPEED_40G)) {
1999                 PMD_DRV_LOG(ERR, "Invalid link setting");
2000                 goto err_up;
2001         }
2002         ret = i40e_apply_link_speed(dev);
2003         if (I40E_SUCCESS != ret) {
2004                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2005                 goto err_up;
2006         }
2007
2008         if (!rte_intr_allow_others(intr_handle)) {
2009                 rte_intr_callback_unregister(intr_handle,
2010                                              i40e_dev_interrupt_handler,
2011                                              (void *)dev);
2012                 /* configure and enable device interrupt */
2013                 i40e_pf_config_irq0(hw, FALSE);
2014                 i40e_pf_enable_irq0(hw);
2015
2016                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2017                         PMD_INIT_LOG(INFO,
2018                                 "lsc won't enable because of no intr multiplex");
2019         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2020                 ret = i40e_aq_set_phy_int_mask(hw,
2021                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2022                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2023                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2024                 if (ret != I40E_SUCCESS)
2025                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2026
2027                 /* Call get_link_info aq commond to enable LSE */
2028                 i40e_dev_link_update(dev, 0);
2029         }
2030
2031         /* enable uio intr after callback register */
2032         rte_intr_enable(intr_handle);
2033
2034         i40e_filter_restore(pf);
2035
2036         return I40E_SUCCESS;
2037
2038 err_up:
2039         i40e_dev_switch_queues(pf, FALSE);
2040         i40e_dev_clear_queues(dev);
2041
2042         return ret;
2043 }
2044
2045 static void
2046 i40e_dev_stop(struct rte_eth_dev *dev)
2047 {
2048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2049         struct i40e_vsi *main_vsi = pf->main_vsi;
2050         struct i40e_mirror_rule *p_mirror;
2051         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2053         int i;
2054
2055         /* Disable all queues */
2056         i40e_dev_switch_queues(pf, FALSE);
2057
2058         /* un-map queues with interrupt registers */
2059         i40e_vsi_disable_queues_intr(main_vsi);
2060         i40e_vsi_queues_unbind_intr(main_vsi);
2061
2062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2063                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2064                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2065         }
2066
2067         if (pf->fdir.fdir_vsi) {
2068                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2069                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2070         }
2071         /* Clear all queues and release memory */
2072         i40e_dev_clear_queues(dev);
2073
2074         /* Set link down */
2075         i40e_dev_set_link_down(dev);
2076
2077         /* Remove all mirror rules */
2078         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2079                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2080                 rte_free(p_mirror);
2081         }
2082         pf->nb_mirror_rule = 0;
2083
2084         if (!rte_intr_allow_others(intr_handle))
2085                 /* resume to the default handler */
2086                 rte_intr_callback_register(intr_handle,
2087                                            i40e_dev_interrupt_handler,
2088                                            (void *)dev);
2089
2090         /* Clean datapath event and queue/vec mapping */
2091         rte_intr_efd_disable(intr_handle);
2092         if (intr_handle->intr_vec) {
2093                 rte_free(intr_handle->intr_vec);
2094                 intr_handle->intr_vec = NULL;
2095         }
2096 }
2097
2098 static void
2099 i40e_dev_close(struct rte_eth_dev *dev)
2100 {
2101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2104         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2105         uint32_t reg;
2106         int i;
2107
2108         PMD_INIT_FUNC_TRACE();
2109
2110         i40e_dev_stop(dev);
2111         hw->adapter_stopped = 1;
2112         i40e_dev_free_queues(dev);
2113
2114         /* Disable interrupt */
2115         i40e_pf_disable_irq0(hw);
2116         rte_intr_disable(intr_handle);
2117
2118         /* shutdown and destroy the HMC */
2119         i40e_shutdown_lan_hmc(hw);
2120
2121         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2122                 i40e_vsi_release(pf->vmdq[i].vsi);
2123                 pf->vmdq[i].vsi = NULL;
2124         }
2125         rte_free(pf->vmdq);
2126         pf->vmdq = NULL;
2127
2128         /* release all the existing VSIs and VEBs */
2129         i40e_fdir_teardown(pf);
2130         i40e_vsi_release(pf->main_vsi);
2131
2132         /* shutdown the adminq */
2133         i40e_aq_queue_shutdown(hw, true);
2134         i40e_shutdown_adminq(hw);
2135
2136         i40e_res_pool_destroy(&pf->qp_pool);
2137         i40e_res_pool_destroy(&pf->msix_pool);
2138
2139         /* force a PF reset to clean anything leftover */
2140         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2141         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2142                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2143         I40E_WRITE_FLUSH(hw);
2144 }
2145
2146 static void
2147 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2148 {
2149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2151         struct i40e_vsi *vsi = pf->main_vsi;
2152         int status;
2153
2154         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2155                                                      true, NULL, true);
2156         if (status != I40E_SUCCESS)
2157                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2158
2159         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2160                                                         TRUE, NULL);
2161         if (status != I40E_SUCCESS)
2162                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2163
2164 }
2165
2166 static void
2167 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2168 {
2169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2171         struct i40e_vsi *vsi = pf->main_vsi;
2172         int status;
2173
2174         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2175                                                      false, NULL, true);
2176         if (status != I40E_SUCCESS)
2177                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2178
2179         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2180                                                         false, NULL);
2181         if (status != I40E_SUCCESS)
2182                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2183 }
2184
2185 static void
2186 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2187 {
2188         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         struct i40e_vsi *vsi = pf->main_vsi;
2191         int ret;
2192
2193         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2194         if (ret != I40E_SUCCESS)
2195                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2196 }
2197
2198 static void
2199 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2200 {
2201         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2202         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2203         struct i40e_vsi *vsi = pf->main_vsi;
2204         int ret;
2205
2206         if (dev->data->promiscuous == 1)
2207                 return; /* must remain in all_multicast mode */
2208
2209         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2210                                 vsi->seid, FALSE, NULL);
2211         if (ret != I40E_SUCCESS)
2212                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2213 }
2214
2215 /*
2216  * Set device link up.
2217  */
2218 static int
2219 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2220 {
2221         /* re-apply link speed setting */
2222         return i40e_apply_link_speed(dev);
2223 }
2224
2225 /*
2226  * Set device link down.
2227  */
2228 static int
2229 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2230 {
2231         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2232         uint8_t abilities = 0;
2233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2234
2235         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2236         return i40e_phy_conf_link(hw, abilities, speed);
2237 }
2238
2239 int
2240 i40e_dev_link_update(struct rte_eth_dev *dev,
2241                      int wait_to_complete)
2242 {
2243 #define CHECK_INTERVAL 100  /* 100ms */
2244 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2245         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         struct i40e_link_status link_status;
2247         struct rte_eth_link link, old;
2248         int status;
2249         unsigned rep_cnt = MAX_REPEAT_TIME;
2250         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2251
2252         memset(&link, 0, sizeof(link));
2253         memset(&old, 0, sizeof(old));
2254         memset(&link_status, 0, sizeof(link_status));
2255         rte_i40e_dev_atomic_read_link_status(dev, &old);
2256
2257         do {
2258                 /* Get link status information from hardware */
2259                 status = i40e_aq_get_link_info(hw, enable_lse,
2260                                                 &link_status, NULL);
2261                 if (status != I40E_SUCCESS) {
2262                         link.link_speed = ETH_SPEED_NUM_100M;
2263                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2264                         PMD_DRV_LOG(ERR, "Failed to get link info");
2265                         goto out;
2266                 }
2267
2268                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2269                 if (!wait_to_complete || link.link_status)
2270                         break;
2271
2272                 rte_delay_ms(CHECK_INTERVAL);
2273         } while (--rep_cnt);
2274
2275         if (!link.link_status)
2276                 goto out;
2277
2278         /* i40e uses full duplex only */
2279         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2280
2281         /* Parse the link status */
2282         switch (link_status.link_speed) {
2283         case I40E_LINK_SPEED_100MB:
2284                 link.link_speed = ETH_SPEED_NUM_100M;
2285                 break;
2286         case I40E_LINK_SPEED_1GB:
2287                 link.link_speed = ETH_SPEED_NUM_1G;
2288                 break;
2289         case I40E_LINK_SPEED_10GB:
2290                 link.link_speed = ETH_SPEED_NUM_10G;
2291                 break;
2292         case I40E_LINK_SPEED_20GB:
2293                 link.link_speed = ETH_SPEED_NUM_20G;
2294                 break;
2295         case I40E_LINK_SPEED_25GB:
2296                 link.link_speed = ETH_SPEED_NUM_25G;
2297                 break;
2298         case I40E_LINK_SPEED_40GB:
2299                 link.link_speed = ETH_SPEED_NUM_40G;
2300                 break;
2301         default:
2302                 link.link_speed = ETH_SPEED_NUM_100M;
2303                 break;
2304         }
2305
2306         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2307                         ETH_LINK_SPEED_FIXED);
2308
2309 out:
2310         rte_i40e_dev_atomic_write_link_status(dev, &link);
2311         if (link.link_status == old.link_status)
2312                 return -1;
2313
2314         i40e_notify_all_vfs_link_status(dev);
2315
2316         return 0;
2317 }
2318
2319 /* Get all the statistics of a VSI */
2320 void
2321 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2322 {
2323         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2324         struct i40e_eth_stats *nes = &vsi->eth_stats;
2325         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2326         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2327
2328         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2329                             vsi->offset_loaded, &oes->rx_bytes,
2330                             &nes->rx_bytes);
2331         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2332                             vsi->offset_loaded, &oes->rx_unicast,
2333                             &nes->rx_unicast);
2334         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2335                             vsi->offset_loaded, &oes->rx_multicast,
2336                             &nes->rx_multicast);
2337         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2338                             vsi->offset_loaded, &oes->rx_broadcast,
2339                             &nes->rx_broadcast);
2340         /* exclude CRC bytes */
2341         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2342                 nes->rx_broadcast) * ETHER_CRC_LEN;
2343
2344         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2345                             &oes->rx_discards, &nes->rx_discards);
2346         /* GLV_REPC not supported */
2347         /* GLV_RMPC not supported */
2348         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2349                             &oes->rx_unknown_protocol,
2350                             &nes->rx_unknown_protocol);
2351         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2352                             vsi->offset_loaded, &oes->tx_bytes,
2353                             &nes->tx_bytes);
2354         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2355                             vsi->offset_loaded, &oes->tx_unicast,
2356                             &nes->tx_unicast);
2357         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2358                             vsi->offset_loaded, &oes->tx_multicast,
2359                             &nes->tx_multicast);
2360         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2361                             vsi->offset_loaded,  &oes->tx_broadcast,
2362                             &nes->tx_broadcast);
2363         /* exclude CRC bytes */
2364         nes->tx_bytes -= (nes->tx_unicast + nes->tx_multicast +
2365                 nes->tx_broadcast) * ETHER_CRC_LEN;
2366         /* GLV_TDPC not supported */
2367         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2368                             &oes->tx_errors, &nes->tx_errors);
2369         vsi->offset_loaded = true;
2370
2371         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2372                     vsi->vsi_id);
2373         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2374         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2375         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2376         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2377         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2378         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2379                     nes->rx_unknown_protocol);
2380         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2381         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2382         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2383         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2384         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2385         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2386         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2387                     vsi->vsi_id);
2388 }
2389
2390 static void
2391 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2392 {
2393         unsigned int i;
2394         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2395         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2396
2397         /* Get rx/tx bytes of internal transfer packets */
2398         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2399                         I40E_GLV_GORCL(hw->port),
2400                         pf->offset_loaded,
2401                         &pf->internal_stats_offset.rx_bytes,
2402                         &pf->internal_stats.rx_bytes);
2403
2404         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2405                         I40E_GLV_GOTCL(hw->port),
2406                         pf->offset_loaded,
2407                         &pf->internal_stats_offset.tx_bytes,
2408                         &pf->internal_stats.tx_bytes);
2409         /* Get total internal rx packet count */
2410         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2411                             I40E_GLV_UPRCL(hw->port),
2412                             pf->offset_loaded,
2413                             &pf->internal_stats_offset.rx_unicast,
2414                             &pf->internal_stats.rx_unicast);
2415         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2416                             I40E_GLV_MPRCL(hw->port),
2417                             pf->offset_loaded,
2418                             &pf->internal_stats_offset.rx_multicast,
2419                             &pf->internal_stats.rx_multicast);
2420         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2421                             I40E_GLV_BPRCL(hw->port),
2422                             pf->offset_loaded,
2423                             &pf->internal_stats_offset.rx_broadcast,
2424                             &pf->internal_stats.rx_broadcast);
2425
2426         /* exclude CRC size */
2427         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2428                 pf->internal_stats.rx_multicast +
2429                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2430
2431         /* Get statistics of struct i40e_eth_stats */
2432         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2433                             I40E_GLPRT_GORCL(hw->port),
2434                             pf->offset_loaded, &os->eth.rx_bytes,
2435                             &ns->eth.rx_bytes);
2436         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2437                             I40E_GLPRT_UPRCL(hw->port),
2438                             pf->offset_loaded, &os->eth.rx_unicast,
2439                             &ns->eth.rx_unicast);
2440         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2441                             I40E_GLPRT_MPRCL(hw->port),
2442                             pf->offset_loaded, &os->eth.rx_multicast,
2443                             &ns->eth.rx_multicast);
2444         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2445                             I40E_GLPRT_BPRCL(hw->port),
2446                             pf->offset_loaded, &os->eth.rx_broadcast,
2447                             &ns->eth.rx_broadcast);
2448         /* Workaround: CRC size should not be included in byte statistics,
2449          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2450          */
2451         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2452                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2453
2454         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2455          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2456          * value.
2457          */
2458         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2459                 ns->eth.rx_bytes = 0;
2460         /* exlude internal rx bytes */
2461         else
2462                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2463
2464         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2465                             pf->offset_loaded, &os->eth.rx_discards,
2466                             &ns->eth.rx_discards);
2467         /* GLPRT_REPC not supported */
2468         /* GLPRT_RMPC not supported */
2469         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2470                             pf->offset_loaded,
2471                             &os->eth.rx_unknown_protocol,
2472                             &ns->eth.rx_unknown_protocol);
2473         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2474                             I40E_GLPRT_GOTCL(hw->port),
2475                             pf->offset_loaded, &os->eth.tx_bytes,
2476                             &ns->eth.tx_bytes);
2477         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2478                             I40E_GLPRT_UPTCL(hw->port),
2479                             pf->offset_loaded, &os->eth.tx_unicast,
2480                             &ns->eth.tx_unicast);
2481         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2482                             I40E_GLPRT_MPTCL(hw->port),
2483                             pf->offset_loaded, &os->eth.tx_multicast,
2484                             &ns->eth.tx_multicast);
2485         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2486                             I40E_GLPRT_BPTCL(hw->port),
2487                             pf->offset_loaded, &os->eth.tx_broadcast,
2488                             &ns->eth.tx_broadcast);
2489         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2490                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2491
2492         /* exclude internal tx bytes */
2493         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2494                 ns->eth.tx_bytes = 0;
2495         else
2496                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2497
2498         /* GLPRT_TEPC not supported */
2499
2500         /* additional port specific stats */
2501         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2502                             pf->offset_loaded, &os->tx_dropped_link_down,
2503                             &ns->tx_dropped_link_down);
2504         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2505                             pf->offset_loaded, &os->crc_errors,
2506                             &ns->crc_errors);
2507         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2508                             pf->offset_loaded, &os->illegal_bytes,
2509                             &ns->illegal_bytes);
2510         /* GLPRT_ERRBC not supported */
2511         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2512                             pf->offset_loaded, &os->mac_local_faults,
2513                             &ns->mac_local_faults);
2514         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2515                             pf->offset_loaded, &os->mac_remote_faults,
2516                             &ns->mac_remote_faults);
2517         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2518                             pf->offset_loaded, &os->rx_length_errors,
2519                             &ns->rx_length_errors);
2520         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2521                             pf->offset_loaded, &os->link_xon_rx,
2522                             &ns->link_xon_rx);
2523         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2524                             pf->offset_loaded, &os->link_xoff_rx,
2525                             &ns->link_xoff_rx);
2526         for (i = 0; i < 8; i++) {
2527                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2528                                     pf->offset_loaded,
2529                                     &os->priority_xon_rx[i],
2530                                     &ns->priority_xon_rx[i]);
2531                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2532                                     pf->offset_loaded,
2533                                     &os->priority_xoff_rx[i],
2534                                     &ns->priority_xoff_rx[i]);
2535         }
2536         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2537                             pf->offset_loaded, &os->link_xon_tx,
2538                             &ns->link_xon_tx);
2539         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2540                             pf->offset_loaded, &os->link_xoff_tx,
2541                             &ns->link_xoff_tx);
2542         for (i = 0; i < 8; i++) {
2543                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2544                                     pf->offset_loaded,
2545                                     &os->priority_xon_tx[i],
2546                                     &ns->priority_xon_tx[i]);
2547                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2548                                     pf->offset_loaded,
2549                                     &os->priority_xoff_tx[i],
2550                                     &ns->priority_xoff_tx[i]);
2551                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2552                                     pf->offset_loaded,
2553                                     &os->priority_xon_2_xoff[i],
2554                                     &ns->priority_xon_2_xoff[i]);
2555         }
2556         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2557                             I40E_GLPRT_PRC64L(hw->port),
2558                             pf->offset_loaded, &os->rx_size_64,
2559                             &ns->rx_size_64);
2560         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2561                             I40E_GLPRT_PRC127L(hw->port),
2562                             pf->offset_loaded, &os->rx_size_127,
2563                             &ns->rx_size_127);
2564         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2565                             I40E_GLPRT_PRC255L(hw->port),
2566                             pf->offset_loaded, &os->rx_size_255,
2567                             &ns->rx_size_255);
2568         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2569                             I40E_GLPRT_PRC511L(hw->port),
2570                             pf->offset_loaded, &os->rx_size_511,
2571                             &ns->rx_size_511);
2572         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2573                             I40E_GLPRT_PRC1023L(hw->port),
2574                             pf->offset_loaded, &os->rx_size_1023,
2575                             &ns->rx_size_1023);
2576         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2577                             I40E_GLPRT_PRC1522L(hw->port),
2578                             pf->offset_loaded, &os->rx_size_1522,
2579                             &ns->rx_size_1522);
2580         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2581                             I40E_GLPRT_PRC9522L(hw->port),
2582                             pf->offset_loaded, &os->rx_size_big,
2583                             &ns->rx_size_big);
2584         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2585                             pf->offset_loaded, &os->rx_undersize,
2586                             &ns->rx_undersize);
2587         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2588                             pf->offset_loaded, &os->rx_fragments,
2589                             &ns->rx_fragments);
2590         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2591                             pf->offset_loaded, &os->rx_oversize,
2592                             &ns->rx_oversize);
2593         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2594                             pf->offset_loaded, &os->rx_jabber,
2595                             &ns->rx_jabber);
2596         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2597                             I40E_GLPRT_PTC64L(hw->port),
2598                             pf->offset_loaded, &os->tx_size_64,
2599                             &ns->tx_size_64);
2600         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2601                             I40E_GLPRT_PTC127L(hw->port),
2602                             pf->offset_loaded, &os->tx_size_127,
2603                             &ns->tx_size_127);
2604         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2605                             I40E_GLPRT_PTC255L(hw->port),
2606                             pf->offset_loaded, &os->tx_size_255,
2607                             &ns->tx_size_255);
2608         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2609                             I40E_GLPRT_PTC511L(hw->port),
2610                             pf->offset_loaded, &os->tx_size_511,
2611                             &ns->tx_size_511);
2612         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2613                             I40E_GLPRT_PTC1023L(hw->port),
2614                             pf->offset_loaded, &os->tx_size_1023,
2615                             &ns->tx_size_1023);
2616         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2617                             I40E_GLPRT_PTC1522L(hw->port),
2618                             pf->offset_loaded, &os->tx_size_1522,
2619                             &ns->tx_size_1522);
2620         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2621                             I40E_GLPRT_PTC9522L(hw->port),
2622                             pf->offset_loaded, &os->tx_size_big,
2623                             &ns->tx_size_big);
2624         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2625                            pf->offset_loaded,
2626                            &os->fd_sb_match, &ns->fd_sb_match);
2627         /* GLPRT_MSPDC not supported */
2628         /* GLPRT_XEC not supported */
2629
2630         pf->offset_loaded = true;
2631
2632         if (pf->main_vsi)
2633                 i40e_update_vsi_stats(pf->main_vsi);
2634 }
2635
2636 /* Get all statistics of a port */
2637 static void
2638 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2639 {
2640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2642         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2643         unsigned i;
2644
2645         /* call read registers - updates values, now write them to struct */
2646         i40e_read_stats_registers(pf, hw);
2647
2648         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2649                         pf->main_vsi->eth_stats.rx_multicast +
2650                         pf->main_vsi->eth_stats.rx_broadcast -
2651                         pf->main_vsi->eth_stats.rx_discards;
2652         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2653                         pf->main_vsi->eth_stats.tx_multicast +
2654                         pf->main_vsi->eth_stats.tx_broadcast;
2655         stats->ibytes   = ns->eth.rx_bytes;
2656         stats->obytes   = ns->eth.tx_bytes;
2657         stats->oerrors  = ns->eth.tx_errors +
2658                         pf->main_vsi->eth_stats.tx_errors;
2659
2660         /* Rx Errors */
2661         stats->imissed  = ns->eth.rx_discards +
2662                         pf->main_vsi->eth_stats.rx_discards;
2663         stats->ierrors  = ns->crc_errors +
2664                         ns->rx_length_errors + ns->rx_undersize +
2665                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2666
2667         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2668         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2669         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2670         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2671         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2672         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2673         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2674                     ns->eth.rx_unknown_protocol);
2675         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2676         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2677         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2678         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2679         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2680         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2681
2682         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2683                     ns->tx_dropped_link_down);
2684         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2685         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2686                     ns->illegal_bytes);
2687         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2688         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2689                     ns->mac_local_faults);
2690         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2691                     ns->mac_remote_faults);
2692         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2693                     ns->rx_length_errors);
2694         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2695         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2696         for (i = 0; i < 8; i++) {
2697                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2698                                 i, ns->priority_xon_rx[i]);
2699                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2700                                 i, ns->priority_xoff_rx[i]);
2701         }
2702         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2703         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2704         for (i = 0; i < 8; i++) {
2705                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2706                                 i, ns->priority_xon_tx[i]);
2707                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2708                                 i, ns->priority_xoff_tx[i]);
2709                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2710                                 i, ns->priority_xon_2_xoff[i]);
2711         }
2712         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2713         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2714         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2715         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2716         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2717         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2718         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2719         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2720         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2721         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2722         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2723         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2724         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2725         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2726         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2727         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2728         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2729         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2730         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2731                         ns->mac_short_packet_dropped);
2732         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2733                     ns->checksum_error);
2734         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2735         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2736 }
2737
2738 /* Reset the statistics */
2739 static void
2740 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2741 {
2742         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744
2745         /* Mark PF and VSI stats to update the offset, aka "reset" */
2746         pf->offset_loaded = false;
2747         if (pf->main_vsi)
2748                 pf->main_vsi->offset_loaded = false;
2749
2750         /* read the stats, reading current register values into offset */
2751         i40e_read_stats_registers(pf, hw);
2752 }
2753
2754 static uint32_t
2755 i40e_xstats_calc_num(void)
2756 {
2757         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2758                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2759                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2760 }
2761
2762 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2763                                      struct rte_eth_xstat_name *xstats_names,
2764                                      __rte_unused unsigned limit)
2765 {
2766         unsigned count = 0;
2767         unsigned i, prio;
2768
2769         if (xstats_names == NULL)
2770                 return i40e_xstats_calc_num();
2771
2772         /* Note: limit checked in rte_eth_xstats_names() */
2773
2774         /* Get stats from i40e_eth_stats struct */
2775         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2776                 snprintf(xstats_names[count].name,
2777                          sizeof(xstats_names[count].name),
2778                          "%s", rte_i40e_stats_strings[i].name);
2779                 count++;
2780         }
2781
2782         /* Get individiual stats from i40e_hw_port struct */
2783         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2784                 snprintf(xstats_names[count].name,
2785                         sizeof(xstats_names[count].name),
2786                          "%s", rte_i40e_hw_port_strings[i].name);
2787                 count++;
2788         }
2789
2790         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2791                 for (prio = 0; prio < 8; prio++) {
2792                         snprintf(xstats_names[count].name,
2793                                  sizeof(xstats_names[count].name),
2794                                  "rx_priority%u_%s", prio,
2795                                  rte_i40e_rxq_prio_strings[i].name);
2796                         count++;
2797                 }
2798         }
2799
2800         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2801                 for (prio = 0; prio < 8; prio++) {
2802                         snprintf(xstats_names[count].name,
2803                                  sizeof(xstats_names[count].name),
2804                                  "tx_priority%u_%s", prio,
2805                                  rte_i40e_txq_prio_strings[i].name);
2806                         count++;
2807                 }
2808         }
2809         return count;
2810 }
2811
2812 static int
2813 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2814                     unsigned n)
2815 {
2816         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2818         unsigned i, count, prio;
2819         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2820
2821         count = i40e_xstats_calc_num();
2822         if (n < count)
2823                 return count;
2824
2825         i40e_read_stats_registers(pf, hw);
2826
2827         if (xstats == NULL)
2828                 return 0;
2829
2830         count = 0;
2831
2832         /* Get stats from i40e_eth_stats struct */
2833         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2834                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2835                         rte_i40e_stats_strings[i].offset);
2836                 xstats[count].id = count;
2837                 count++;
2838         }
2839
2840         /* Get individiual stats from i40e_hw_port struct */
2841         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2842                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2843                         rte_i40e_hw_port_strings[i].offset);
2844                 xstats[count].id = count;
2845                 count++;
2846         }
2847
2848         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2849                 for (prio = 0; prio < 8; prio++) {
2850                         xstats[count].value =
2851                                 *(uint64_t *)(((char *)hw_stats) +
2852                                 rte_i40e_rxq_prio_strings[i].offset +
2853                                 (sizeof(uint64_t) * prio));
2854                         xstats[count].id = count;
2855                         count++;
2856                 }
2857         }
2858
2859         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2860                 for (prio = 0; prio < 8; prio++) {
2861                         xstats[count].value =
2862                                 *(uint64_t *)(((char *)hw_stats) +
2863                                 rte_i40e_txq_prio_strings[i].offset +
2864                                 (sizeof(uint64_t) * prio));
2865                         xstats[count].id = count;
2866                         count++;
2867                 }
2868         }
2869
2870         return count;
2871 }
2872
2873 static int
2874 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2875                                  __rte_unused uint16_t queue_id,
2876                                  __rte_unused uint8_t stat_idx,
2877                                  __rte_unused uint8_t is_rx)
2878 {
2879         PMD_INIT_FUNC_TRACE();
2880
2881         return -ENOSYS;
2882 }
2883
2884 static int
2885 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2886 {
2887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888         u32 full_ver;
2889         u8 ver, patch;
2890         u16 build;
2891         int ret;
2892
2893         full_ver = hw->nvm.oem_ver;
2894         ver = (u8)(full_ver >> 24);
2895         build = (u16)((full_ver >> 8) & 0xffff);
2896         patch = (u8)(full_ver & 0xff);
2897
2898         ret = snprintf(fw_version, fw_size,
2899                  "%d.%d%d 0x%08x %d.%d.%d",
2900                  ((hw->nvm.version >> 12) & 0xf),
2901                  ((hw->nvm.version >> 4) & 0xff),
2902                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2903                  ver, build, patch);
2904
2905         ret += 1; /* add the size of '\0' */
2906         if (fw_size < (u32)ret)
2907                 return ret;
2908         else
2909                 return 0;
2910 }
2911
2912 static void
2913 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2914 {
2915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2917         struct i40e_vsi *vsi = pf->main_vsi;
2918         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2919
2920         dev_info->pci_dev = pci_dev;
2921         dev_info->max_rx_queues = vsi->nb_qps;
2922         dev_info->max_tx_queues = vsi->nb_qps;
2923         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2924         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2925         dev_info->max_mac_addrs = vsi->max_macaddrs;
2926         dev_info->max_vfs = pci_dev->max_vfs;
2927         dev_info->rx_offload_capa =
2928                 DEV_RX_OFFLOAD_VLAN_STRIP |
2929                 DEV_RX_OFFLOAD_QINQ_STRIP |
2930                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2931                 DEV_RX_OFFLOAD_UDP_CKSUM |
2932                 DEV_RX_OFFLOAD_TCP_CKSUM;
2933         dev_info->tx_offload_capa =
2934                 DEV_TX_OFFLOAD_VLAN_INSERT |
2935                 DEV_TX_OFFLOAD_QINQ_INSERT |
2936                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2937                 DEV_TX_OFFLOAD_UDP_CKSUM |
2938                 DEV_TX_OFFLOAD_TCP_CKSUM |
2939                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2940                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2941                 DEV_TX_OFFLOAD_TCP_TSO |
2942                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2943                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2944                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2945                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2946         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2947                                                 sizeof(uint32_t);
2948         dev_info->reta_size = pf->hash_lut_size;
2949         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2950
2951         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2952                 .rx_thresh = {
2953                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2954                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2955                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2956                 },
2957                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2958                 .rx_drop_en = 0,
2959         };
2960
2961         dev_info->default_txconf = (struct rte_eth_txconf) {
2962                 .tx_thresh = {
2963                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2964                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2965                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2966                 },
2967                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2968                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2969                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2970                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2971         };
2972
2973         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2974                 .nb_max = I40E_MAX_RING_DESC,
2975                 .nb_min = I40E_MIN_RING_DESC,
2976                 .nb_align = I40E_ALIGN_RING_DESC,
2977         };
2978
2979         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2980                 .nb_max = I40E_MAX_RING_DESC,
2981                 .nb_min = I40E_MIN_RING_DESC,
2982                 .nb_align = I40E_ALIGN_RING_DESC,
2983                 .nb_seg_max = I40E_TX_MAX_SEG,
2984                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2985         };
2986
2987         if (pf->flags & I40E_FLAG_VMDQ) {
2988                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2989                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2990                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2991                                                 pf->max_nb_vmdq_vsi;
2992                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2993                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2994                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2995         }
2996
2997         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2998                 /* For XL710 */
2999                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3000         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3001                 /* For XXV710 */
3002                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3003         else
3004                 /* For X710 */
3005                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3006 }
3007
3008 static int
3009 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3010 {
3011         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3012         struct i40e_vsi *vsi = pf->main_vsi;
3013         PMD_INIT_FUNC_TRACE();
3014
3015         if (on)
3016                 return i40e_vsi_add_vlan(vsi, vlan_id);
3017         else
3018                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3019 }
3020
3021 static int
3022 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3023                                 enum rte_vlan_type vlan_type,
3024                                 uint16_t tpid, int qinq)
3025 {
3026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3027         uint64_t reg_r = 0;
3028         uint64_t reg_w = 0;
3029         uint16_t reg_id = 3;
3030         int ret;
3031
3032         if (qinq) {
3033                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3034                         reg_id = 2;
3035         }
3036
3037         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3038                                           &reg_r, NULL);
3039         if (ret != I40E_SUCCESS) {
3040                 PMD_DRV_LOG(ERR,
3041                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3042                            reg_id);
3043                 return -EIO;
3044         }
3045         PMD_DRV_LOG(DEBUG,
3046                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3047                     reg_id, reg_r);
3048
3049         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3050         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3051         if (reg_r == reg_w) {
3052                 PMD_DRV_LOG(DEBUG, "No need to write");
3053                 return 0;
3054         }
3055
3056         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3057                                            reg_w, NULL);
3058         if (ret != I40E_SUCCESS) {
3059                 PMD_DRV_LOG(ERR,
3060                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3061                             reg_id);
3062                 return -EIO;
3063         }
3064         PMD_DRV_LOG(DEBUG,
3065                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3066                     reg_w, reg_id);
3067
3068         return 0;
3069 }
3070
3071 static int
3072 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3073                    enum rte_vlan_type vlan_type,
3074                    uint16_t tpid)
3075 {
3076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3077         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3078         int ret = 0;
3079
3080         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3081              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3082             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3083                 PMD_DRV_LOG(ERR,
3084                             "Unsupported vlan type.");
3085                 return -EINVAL;
3086         }
3087         /* 802.1ad frames ability is added in NVM API 1.7*/
3088         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3089                 if (qinq) {
3090                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3091                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3092                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3093                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3094                 } else {
3095                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3096                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3097                 }
3098                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3099                 if (ret != I40E_SUCCESS) {
3100                         PMD_DRV_LOG(ERR,
3101                                     "Set switch config failed aq_err: %d",
3102                                     hw->aq.asq_last_status);
3103                         ret = -EIO;
3104                 }
3105         } else
3106                 /* If NVM API < 1.7, keep the register setting */
3107                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3108                                                       tpid, qinq);
3109
3110         return ret;
3111 }
3112
3113 static void
3114 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3115 {
3116         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3117         struct i40e_vsi *vsi = pf->main_vsi;
3118
3119         if (mask & ETH_VLAN_FILTER_MASK) {
3120                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3121                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3122                 else
3123                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3124         }
3125
3126         if (mask & ETH_VLAN_STRIP_MASK) {
3127                 /* Enable or disable VLAN stripping */
3128                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3129                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3130                 else
3131                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3132         }
3133
3134         if (mask & ETH_VLAN_EXTEND_MASK) {
3135                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3136                         i40e_vsi_config_double_vlan(vsi, TRUE);
3137                         /* Set global registers with default ethertype. */
3138                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3139                                            ETHER_TYPE_VLAN);
3140                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3141                                            ETHER_TYPE_VLAN);
3142                 }
3143                 else
3144                         i40e_vsi_config_double_vlan(vsi, FALSE);
3145         }
3146 }
3147
3148 static void
3149 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3150                           __rte_unused uint16_t queue,
3151                           __rte_unused int on)
3152 {
3153         PMD_INIT_FUNC_TRACE();
3154 }
3155
3156 static int
3157 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3158 {
3159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3160         struct i40e_vsi *vsi = pf->main_vsi;
3161         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3162         struct i40e_vsi_vlan_pvid_info info;
3163
3164         memset(&info, 0, sizeof(info));
3165         info.on = on;
3166         if (info.on)
3167                 info.config.pvid = pvid;
3168         else {
3169                 info.config.reject.tagged =
3170                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3171                 info.config.reject.untagged =
3172                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3173         }
3174
3175         return i40e_vsi_vlan_pvid_set(vsi, &info);
3176 }
3177
3178 static int
3179 i40e_dev_led_on(struct rte_eth_dev *dev)
3180 {
3181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182         uint32_t mode = i40e_led_get(hw);
3183
3184         if (mode == 0)
3185                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3186
3187         return 0;
3188 }
3189
3190 static int
3191 i40e_dev_led_off(struct rte_eth_dev *dev)
3192 {
3193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3194         uint32_t mode = i40e_led_get(hw);
3195
3196         if (mode != 0)
3197                 i40e_led_set(hw, 0, false);
3198
3199         return 0;
3200 }
3201
3202 static int
3203 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3204 {
3205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3207
3208         fc_conf->pause_time = pf->fc_conf.pause_time;
3209         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3210         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3211
3212          /* Return current mode according to actual setting*/
3213         switch (hw->fc.current_mode) {
3214         case I40E_FC_FULL:
3215                 fc_conf->mode = RTE_FC_FULL;
3216                 break;
3217         case I40E_FC_TX_PAUSE:
3218                 fc_conf->mode = RTE_FC_TX_PAUSE;
3219                 break;
3220         case I40E_FC_RX_PAUSE:
3221                 fc_conf->mode = RTE_FC_RX_PAUSE;
3222                 break;
3223         case I40E_FC_NONE:
3224         default:
3225                 fc_conf->mode = RTE_FC_NONE;
3226         };
3227
3228         return 0;
3229 }
3230
3231 static int
3232 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3233 {
3234         uint32_t mflcn_reg, fctrl_reg, reg;
3235         uint32_t max_high_water;
3236         uint8_t i, aq_failure;
3237         int err;
3238         struct i40e_hw *hw;
3239         struct i40e_pf *pf;
3240         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3241                 [RTE_FC_NONE] = I40E_FC_NONE,
3242                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3243                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3244                 [RTE_FC_FULL] = I40E_FC_FULL
3245         };
3246
3247         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3248
3249         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3250         if ((fc_conf->high_water > max_high_water) ||
3251                         (fc_conf->high_water < fc_conf->low_water)) {
3252                 PMD_INIT_LOG(ERR,
3253                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3254                         max_high_water);
3255                 return -EINVAL;
3256         }
3257
3258         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3261
3262         pf->fc_conf.pause_time = fc_conf->pause_time;
3263         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3264         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3265
3266         PMD_INIT_FUNC_TRACE();
3267
3268         /* All the link flow control related enable/disable register
3269          * configuration is handle by the F/W
3270          */
3271         err = i40e_set_fc(hw, &aq_failure, true);
3272         if (err < 0)
3273                 return -ENOSYS;
3274
3275         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3276                 /* Configure flow control refresh threshold,
3277                  * the value for stat_tx_pause_refresh_timer[8]
3278                  * is used for global pause operation.
3279                  */
3280
3281                 I40E_WRITE_REG(hw,
3282                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3283                                pf->fc_conf.pause_time);
3284
3285                 /* configure the timer value included in transmitted pause
3286                  * frame,
3287                  * the value for stat_tx_pause_quanta[8] is used for global
3288                  * pause operation
3289                  */
3290                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3291                                pf->fc_conf.pause_time);
3292
3293                 fctrl_reg = I40E_READ_REG(hw,
3294                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3295
3296                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3297                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3298                 else
3299                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3300
3301                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3302                                fctrl_reg);
3303         } else {
3304                 /* Configure pause time (2 TCs per register) */
3305                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3306                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3307                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3308
3309                 /* Configure flow control refresh threshold value */
3310                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3311                                pf->fc_conf.pause_time / 2);
3312
3313                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3314
3315                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3316                  *depending on configuration
3317                  */
3318                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3319                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3320                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3321                 } else {
3322                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3323                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3324                 }
3325
3326                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3327         }
3328
3329         /* config the water marker both based on the packets and bytes */
3330         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3331                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3332                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3333         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3334                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3335                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3336         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3337                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3338                        << I40E_KILOSHIFT);
3339         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3340                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3341                        << I40E_KILOSHIFT);
3342
3343         I40E_WRITE_FLUSH(hw);
3344
3345         return 0;
3346 }
3347
3348 static int
3349 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3350                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3351 {
3352         PMD_INIT_FUNC_TRACE();
3353
3354         return -ENOSYS;
3355 }
3356
3357 /* Add a MAC address, and update filters */
3358 static int
3359 i40e_macaddr_add(struct rte_eth_dev *dev,
3360                  struct ether_addr *mac_addr,
3361                  __rte_unused uint32_t index,
3362                  uint32_t pool)
3363 {
3364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3365         struct i40e_mac_filter_info mac_filter;
3366         struct i40e_vsi *vsi;
3367         int ret;
3368
3369         /* If VMDQ not enabled or configured, return */
3370         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3371                           !pf->nb_cfg_vmdq_vsi)) {
3372                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3373                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3374                         pool);
3375                 return -ENOTSUP;
3376         }
3377
3378         if (pool > pf->nb_cfg_vmdq_vsi) {
3379                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3380                                 pool, pf->nb_cfg_vmdq_vsi);
3381                 return -EINVAL;
3382         }
3383
3384         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3385         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3386                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3387         else
3388                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3389
3390         if (pool == 0)
3391                 vsi = pf->main_vsi;
3392         else
3393                 vsi = pf->vmdq[pool - 1].vsi;
3394
3395         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3396         if (ret != I40E_SUCCESS) {
3397                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3398                 return -ENODEV;
3399         }
3400         return 0;
3401 }
3402
3403 /* Remove a MAC address, and update filters */
3404 static void
3405 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3406 {
3407         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3408         struct i40e_vsi *vsi;
3409         struct rte_eth_dev_data *data = dev->data;
3410         struct ether_addr *macaddr;
3411         int ret;
3412         uint32_t i;
3413         uint64_t pool_sel;
3414
3415         macaddr = &(data->mac_addrs[index]);
3416
3417         pool_sel = dev->data->mac_pool_sel[index];
3418
3419         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3420                 if (pool_sel & (1ULL << i)) {
3421                         if (i == 0)
3422                                 vsi = pf->main_vsi;
3423                         else {
3424                                 /* No VMDQ pool enabled or configured */
3425                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3426                                         (i > pf->nb_cfg_vmdq_vsi)) {
3427                                         PMD_DRV_LOG(ERR,
3428                                                 "No VMDQ pool enabled/configured");
3429                                         return;
3430                                 }
3431                                 vsi = pf->vmdq[i - 1].vsi;
3432                         }
3433                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3434
3435                         if (ret) {
3436                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3437                                 return;
3438                         }
3439                 }
3440         }
3441 }
3442
3443 /* Set perfect match or hash match of MAC and VLAN for a VF */
3444 static int
3445 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3446                  struct rte_eth_mac_filter *filter,
3447                  bool add)
3448 {
3449         struct i40e_hw *hw;
3450         struct i40e_mac_filter_info mac_filter;
3451         struct ether_addr old_mac;
3452         struct ether_addr *new_mac;
3453         struct i40e_pf_vf *vf = NULL;
3454         uint16_t vf_id;
3455         int ret;
3456
3457         if (pf == NULL) {
3458                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3459                 return -EINVAL;
3460         }
3461         hw = I40E_PF_TO_HW(pf);
3462
3463         if (filter == NULL) {
3464                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3465                 return -EINVAL;
3466         }
3467
3468         new_mac = &filter->mac_addr;
3469
3470         if (is_zero_ether_addr(new_mac)) {
3471                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3472                 return -EINVAL;
3473         }
3474
3475         vf_id = filter->dst_id;
3476
3477         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3478                 PMD_DRV_LOG(ERR, "Invalid argument.");
3479                 return -EINVAL;
3480         }
3481         vf = &pf->vfs[vf_id];
3482
3483         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3484                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3485                 return -EINVAL;
3486         }
3487
3488         if (add) {
3489                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3490                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3491                                 ETHER_ADDR_LEN);
3492                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3493                                  ETHER_ADDR_LEN);
3494
3495                 mac_filter.filter_type = filter->filter_type;
3496                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3497                 if (ret != I40E_SUCCESS) {
3498                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3499                         return -1;
3500                 }
3501                 ether_addr_copy(new_mac, &pf->dev_addr);
3502         } else {
3503                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3504                                 ETHER_ADDR_LEN);
3505                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3506                 if (ret != I40E_SUCCESS) {
3507                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3508                         return -1;
3509                 }
3510
3511                 /* Clear device address as it has been removed */
3512                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3513                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3514         }
3515
3516         return 0;
3517 }
3518
3519 /* MAC filter handle */
3520 static int
3521 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3522                 void *arg)
3523 {
3524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3525         struct rte_eth_mac_filter *filter;
3526         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3527         int ret = I40E_NOT_SUPPORTED;
3528
3529         filter = (struct rte_eth_mac_filter *)(arg);
3530
3531         switch (filter_op) {
3532         case RTE_ETH_FILTER_NOP:
3533                 ret = I40E_SUCCESS;
3534                 break;
3535         case RTE_ETH_FILTER_ADD:
3536                 i40e_pf_disable_irq0(hw);
3537                 if (filter->is_vf)
3538                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3539                 i40e_pf_enable_irq0(hw);
3540                 break;
3541         case RTE_ETH_FILTER_DELETE:
3542                 i40e_pf_disable_irq0(hw);
3543                 if (filter->is_vf)
3544                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3545                 i40e_pf_enable_irq0(hw);
3546                 break;
3547         default:
3548                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3549                 ret = I40E_ERR_PARAM;
3550                 break;
3551         }
3552
3553         return ret;
3554 }
3555
3556 static int
3557 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3558 {
3559         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3560         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3561         int ret;
3562
3563         if (!lut)
3564                 return -EINVAL;
3565
3566         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3567                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3568                                           lut, lut_size);
3569                 if (ret) {
3570                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3571                         return ret;
3572                 }
3573         } else {
3574                 uint32_t *lut_dw = (uint32_t *)lut;
3575                 uint16_t i, lut_size_dw = lut_size / 4;
3576
3577                 for (i = 0; i < lut_size_dw; i++)
3578                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3579         }
3580
3581         return 0;
3582 }
3583
3584 static int
3585 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3586 {
3587         struct i40e_pf *pf;
3588         struct i40e_hw *hw;
3589         int ret;
3590
3591         if (!vsi || !lut)
3592                 return -EINVAL;
3593
3594         pf = I40E_VSI_TO_PF(vsi);
3595         hw = I40E_VSI_TO_HW(vsi);
3596
3597         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3598                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3599                                           lut, lut_size);
3600                 if (ret) {
3601                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3602                         return ret;
3603                 }
3604         } else {
3605                 uint32_t *lut_dw = (uint32_t *)lut;
3606                 uint16_t i, lut_size_dw = lut_size / 4;
3607
3608                 for (i = 0; i < lut_size_dw; i++)
3609                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3610                 I40E_WRITE_FLUSH(hw);
3611         }
3612
3613         return 0;
3614 }
3615
3616 static int
3617 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3618                          struct rte_eth_rss_reta_entry64 *reta_conf,
3619                          uint16_t reta_size)
3620 {
3621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3622         uint16_t i, lut_size = pf->hash_lut_size;
3623         uint16_t idx, shift;
3624         uint8_t *lut;
3625         int ret;
3626
3627         if (reta_size != lut_size ||
3628                 reta_size > ETH_RSS_RETA_SIZE_512) {
3629                 PMD_DRV_LOG(ERR,
3630                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3631                         reta_size, lut_size);
3632                 return -EINVAL;
3633         }
3634
3635         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3636         if (!lut) {
3637                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3638                 return -ENOMEM;
3639         }
3640         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3641         if (ret)
3642                 goto out;
3643         for (i = 0; i < reta_size; i++) {
3644                 idx = i / RTE_RETA_GROUP_SIZE;
3645                 shift = i % RTE_RETA_GROUP_SIZE;
3646                 if (reta_conf[idx].mask & (1ULL << shift))
3647                         lut[i] = reta_conf[idx].reta[shift];
3648         }
3649         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3650
3651 out:
3652         rte_free(lut);
3653
3654         return ret;
3655 }
3656
3657 static int
3658 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3659                         struct rte_eth_rss_reta_entry64 *reta_conf,
3660                         uint16_t reta_size)
3661 {
3662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3663         uint16_t i, lut_size = pf->hash_lut_size;
3664         uint16_t idx, shift;
3665         uint8_t *lut;
3666         int ret;
3667
3668         if (reta_size != lut_size ||
3669                 reta_size > ETH_RSS_RETA_SIZE_512) {
3670                 PMD_DRV_LOG(ERR,
3671                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3672                         reta_size, lut_size);
3673                 return -EINVAL;
3674         }
3675
3676         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3677         if (!lut) {
3678                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3679                 return -ENOMEM;
3680         }
3681
3682         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3683         if (ret)
3684                 goto out;
3685         for (i = 0; i < reta_size; i++) {
3686                 idx = i / RTE_RETA_GROUP_SIZE;
3687                 shift = i % RTE_RETA_GROUP_SIZE;
3688                 if (reta_conf[idx].mask & (1ULL << shift))
3689                         reta_conf[idx].reta[shift] = lut[i];
3690         }
3691
3692 out:
3693         rte_free(lut);
3694
3695         return ret;
3696 }
3697
3698 /**
3699  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3700  * @hw:   pointer to the HW structure
3701  * @mem:  pointer to mem struct to fill out
3702  * @size: size of memory requested
3703  * @alignment: what to align the allocation to
3704  **/
3705 enum i40e_status_code
3706 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3707                         struct i40e_dma_mem *mem,
3708                         u64 size,
3709                         u32 alignment)
3710 {
3711         const struct rte_memzone *mz = NULL;
3712         char z_name[RTE_MEMZONE_NAMESIZE];
3713
3714         if (!mem)
3715                 return I40E_ERR_PARAM;
3716
3717         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3718         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3719                                          alignment, RTE_PGSIZE_2M);
3720         if (!mz)
3721                 return I40E_ERR_NO_MEMORY;
3722
3723         mem->size = size;
3724         mem->va = mz->addr;
3725         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3726         mem->zone = (const void *)mz;
3727         PMD_DRV_LOG(DEBUG,
3728                 "memzone %s allocated with physical address: %"PRIu64,
3729                 mz->name, mem->pa);
3730
3731         return I40E_SUCCESS;
3732 }
3733
3734 /**
3735  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3736  * @hw:   pointer to the HW structure
3737  * @mem:  ptr to mem struct to free
3738  **/
3739 enum i40e_status_code
3740 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3741                     struct i40e_dma_mem *mem)
3742 {
3743         if (!mem)
3744                 return I40E_ERR_PARAM;
3745
3746         PMD_DRV_LOG(DEBUG,
3747                 "memzone %s to be freed with physical address: %"PRIu64,
3748                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3749         rte_memzone_free((const struct rte_memzone *)mem->zone);
3750         mem->zone = NULL;
3751         mem->va = NULL;
3752         mem->pa = (u64)0;
3753
3754         return I40E_SUCCESS;
3755 }
3756
3757 /**
3758  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3759  * @hw:   pointer to the HW structure
3760  * @mem:  pointer to mem struct to fill out
3761  * @size: size of memory requested
3762  **/
3763 enum i40e_status_code
3764 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3765                          struct i40e_virt_mem *mem,
3766                          u32 size)
3767 {
3768         if (!mem)
3769                 return I40E_ERR_PARAM;
3770
3771         mem->size = size;
3772         mem->va = rte_zmalloc("i40e", size, 0);
3773
3774         if (mem->va)
3775                 return I40E_SUCCESS;
3776         else
3777                 return I40E_ERR_NO_MEMORY;
3778 }
3779
3780 /**
3781  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3782  * @hw:   pointer to the HW structure
3783  * @mem:  pointer to mem struct to free
3784  **/
3785 enum i40e_status_code
3786 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3787                      struct i40e_virt_mem *mem)
3788 {
3789         if (!mem)
3790                 return I40E_ERR_PARAM;
3791
3792         rte_free(mem->va);
3793         mem->va = NULL;
3794
3795         return I40E_SUCCESS;
3796 }
3797
3798 void
3799 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3800 {
3801         rte_spinlock_init(&sp->spinlock);
3802 }
3803
3804 void
3805 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3806 {
3807         rte_spinlock_lock(&sp->spinlock);
3808 }
3809
3810 void
3811 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3812 {
3813         rte_spinlock_unlock(&sp->spinlock);
3814 }
3815
3816 void
3817 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3818 {
3819         return;
3820 }
3821
3822 /**
3823  * Get the hardware capabilities, which will be parsed
3824  * and saved into struct i40e_hw.
3825  */
3826 static int
3827 i40e_get_cap(struct i40e_hw *hw)
3828 {
3829         struct i40e_aqc_list_capabilities_element_resp *buf;
3830         uint16_t len, size = 0;
3831         int ret;
3832
3833         /* Calculate a huge enough buff for saving response data temporarily */
3834         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3835                                                 I40E_MAX_CAP_ELE_NUM;
3836         buf = rte_zmalloc("i40e", len, 0);
3837         if (!buf) {
3838                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3839                 return I40E_ERR_NO_MEMORY;
3840         }
3841
3842         /* Get, parse the capabilities and save it to hw */
3843         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3844                         i40e_aqc_opc_list_func_capabilities, NULL);
3845         if (ret != I40E_SUCCESS)
3846                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3847
3848         /* Free the temporary buffer after being used */
3849         rte_free(buf);
3850
3851         return ret;
3852 }
3853
3854 static int
3855 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3856 {
3857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3858         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3859         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3860         uint16_t qp_count = 0, vsi_count = 0;
3861
3862         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3863                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3864                 return -EINVAL;
3865         }
3866         /* Add the parameter init for LFC */
3867         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3868         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3869         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3870
3871         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3872         pf->max_num_vsi = hw->func_caps.num_vsis;
3873         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3874         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3875         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3876
3877         /* FDir queue/VSI allocation */
3878         pf->fdir_qp_offset = 0;
3879         if (hw->func_caps.fd) {
3880                 pf->flags |= I40E_FLAG_FDIR;
3881                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3882         } else {
3883                 pf->fdir_nb_qps = 0;
3884         }
3885         qp_count += pf->fdir_nb_qps;
3886         vsi_count += 1;
3887
3888         /* LAN queue/VSI allocation */
3889         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3890         if (!hw->func_caps.rss) {
3891                 pf->lan_nb_qps = 1;
3892         } else {
3893                 pf->flags |= I40E_FLAG_RSS;
3894                 if (hw->mac.type == I40E_MAC_X722)
3895                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3896                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3897         }
3898         qp_count += pf->lan_nb_qps;
3899         vsi_count += 1;
3900
3901         /* VF queue/VSI allocation */
3902         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3903         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3904                 pf->flags |= I40E_FLAG_SRIOV;
3905                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3906                 pf->vf_num = pci_dev->max_vfs;
3907                 PMD_DRV_LOG(DEBUG,
3908                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3909                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3910         } else {
3911                 pf->vf_nb_qps = 0;
3912                 pf->vf_num = 0;
3913         }
3914         qp_count += pf->vf_nb_qps * pf->vf_num;
3915         vsi_count += pf->vf_num;
3916
3917         /* VMDq queue/VSI allocation */
3918         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3919         pf->vmdq_nb_qps = 0;
3920         pf->max_nb_vmdq_vsi = 0;
3921         if (hw->func_caps.vmdq) {
3922                 if (qp_count < hw->func_caps.num_tx_qp &&
3923                         vsi_count < hw->func_caps.num_vsis) {
3924                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3925                                 qp_count) / pf->vmdq_nb_qp_max;
3926
3927                         /* Limit the maximum number of VMDq vsi to the maximum
3928                          * ethdev can support
3929                          */
3930                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3931                                 hw->func_caps.num_vsis - vsi_count);
3932                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3933                                 ETH_64_POOLS);
3934                         if (pf->max_nb_vmdq_vsi) {
3935                                 pf->flags |= I40E_FLAG_VMDQ;
3936                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3937                                 PMD_DRV_LOG(DEBUG,
3938                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3939                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3940                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3941                         } else {
3942                                 PMD_DRV_LOG(INFO,
3943                                         "No enough queues left for VMDq");
3944                         }
3945                 } else {
3946                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3947                 }
3948         }
3949         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3950         vsi_count += pf->max_nb_vmdq_vsi;
3951
3952         if (hw->func_caps.dcb)
3953                 pf->flags |= I40E_FLAG_DCB;
3954
3955         if (qp_count > hw->func_caps.num_tx_qp) {
3956                 PMD_DRV_LOG(ERR,
3957                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3958                         qp_count, hw->func_caps.num_tx_qp);
3959                 return -EINVAL;
3960         }
3961         if (vsi_count > hw->func_caps.num_vsis) {
3962                 PMD_DRV_LOG(ERR,
3963                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3964                         vsi_count, hw->func_caps.num_vsis);
3965                 return -EINVAL;
3966         }
3967
3968         return 0;
3969 }
3970
3971 static int
3972 i40e_pf_get_switch_config(struct i40e_pf *pf)
3973 {
3974         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3975         struct i40e_aqc_get_switch_config_resp *switch_config;
3976         struct i40e_aqc_switch_config_element_resp *element;
3977         uint16_t start_seid = 0, num_reported;
3978         int ret;
3979
3980         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3981                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3982         if (!switch_config) {
3983                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3984                 return -ENOMEM;
3985         }
3986
3987         /* Get the switch configurations */
3988         ret = i40e_aq_get_switch_config(hw, switch_config,
3989                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3990         if (ret != I40E_SUCCESS) {
3991                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3992                 goto fail;
3993         }
3994         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3995         if (num_reported != 1) { /* The number should be 1 */
3996                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3997                 goto fail;
3998         }
3999
4000         /* Parse the switch configuration elements */
4001         element = &(switch_config->element[0]);
4002         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4003                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4004                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4005         } else
4006                 PMD_DRV_LOG(INFO, "Unknown element type");
4007
4008 fail:
4009         rte_free(switch_config);
4010
4011         return ret;
4012 }
4013
4014 static int
4015 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4016                         uint32_t num)
4017 {
4018         struct pool_entry *entry;
4019
4020         if (pool == NULL || num == 0)
4021                 return -EINVAL;
4022
4023         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4024         if (entry == NULL) {
4025                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4026                 return -ENOMEM;
4027         }
4028
4029         /* queue heap initialize */
4030         pool->num_free = num;
4031         pool->num_alloc = 0;
4032         pool->base = base;
4033         LIST_INIT(&pool->alloc_list);
4034         LIST_INIT(&pool->free_list);
4035
4036         /* Initialize element  */
4037         entry->base = 0;
4038         entry->len = num;
4039
4040         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4041         return 0;
4042 }
4043
4044 static void
4045 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4046 {
4047         struct pool_entry *entry, *next_entry;
4048
4049         if (pool == NULL)
4050                 return;
4051
4052         for (entry = LIST_FIRST(&pool->alloc_list);
4053                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4054                         entry = next_entry) {
4055                 LIST_REMOVE(entry, next);
4056                 rte_free(entry);
4057         }
4058
4059         for (entry = LIST_FIRST(&pool->free_list);
4060                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4061                         entry = next_entry) {
4062                 LIST_REMOVE(entry, next);
4063                 rte_free(entry);
4064         }
4065
4066         pool->num_free = 0;
4067         pool->num_alloc = 0;
4068         pool->base = 0;
4069         LIST_INIT(&pool->alloc_list);
4070         LIST_INIT(&pool->free_list);
4071 }
4072
4073 static int
4074 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4075                        uint32_t base)
4076 {
4077         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4078         uint32_t pool_offset;
4079         int insert;
4080
4081         if (pool == NULL) {
4082                 PMD_DRV_LOG(ERR, "Invalid parameter");
4083                 return -EINVAL;
4084         }
4085
4086         pool_offset = base - pool->base;
4087         /* Lookup in alloc list */
4088         LIST_FOREACH(entry, &pool->alloc_list, next) {
4089                 if (entry->base == pool_offset) {
4090                         valid_entry = entry;
4091                         LIST_REMOVE(entry, next);
4092                         break;
4093                 }
4094         }
4095
4096         /* Not find, return */
4097         if (valid_entry == NULL) {
4098                 PMD_DRV_LOG(ERR, "Failed to find entry");
4099                 return -EINVAL;
4100         }
4101
4102         /**
4103          * Found it, move it to free list  and try to merge.
4104          * In order to make merge easier, always sort it by qbase.
4105          * Find adjacent prev and last entries.
4106          */
4107         prev = next = NULL;
4108         LIST_FOREACH(entry, &pool->free_list, next) {
4109                 if (entry->base > valid_entry->base) {
4110                         next = entry;
4111                         break;
4112                 }
4113                 prev = entry;
4114         }
4115
4116         insert = 0;
4117         /* Try to merge with next one*/
4118         if (next != NULL) {
4119                 /* Merge with next one */
4120                 if (valid_entry->base + valid_entry->len == next->base) {
4121                         next->base = valid_entry->base;
4122                         next->len += valid_entry->len;
4123                         rte_free(valid_entry);
4124                         valid_entry = next;
4125                         insert = 1;
4126                 }
4127         }
4128
4129         if (prev != NULL) {
4130                 /* Merge with previous one */
4131                 if (prev->base + prev->len == valid_entry->base) {
4132                         prev->len += valid_entry->len;
4133                         /* If it merge with next one, remove next node */
4134                         if (insert == 1) {
4135                                 LIST_REMOVE(valid_entry, next);
4136                                 rte_free(valid_entry);
4137                         } else {
4138                                 rte_free(valid_entry);
4139                                 insert = 1;
4140                         }
4141                 }
4142         }
4143
4144         /* Not find any entry to merge, insert */
4145         if (insert == 0) {
4146                 if (prev != NULL)
4147                         LIST_INSERT_AFTER(prev, valid_entry, next);
4148                 else if (next != NULL)
4149                         LIST_INSERT_BEFORE(next, valid_entry, next);
4150                 else /* It's empty list, insert to head */
4151                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4152         }
4153
4154         pool->num_free += valid_entry->len;
4155         pool->num_alloc -= valid_entry->len;
4156
4157         return 0;
4158 }
4159
4160 static int
4161 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4162                        uint16_t num)
4163 {
4164         struct pool_entry *entry, *valid_entry;
4165
4166         if (pool == NULL || num == 0) {
4167                 PMD_DRV_LOG(ERR, "Invalid parameter");
4168                 return -EINVAL;
4169         }
4170
4171         if (pool->num_free < num) {
4172                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4173                             num, pool->num_free);
4174                 return -ENOMEM;
4175         }
4176
4177         valid_entry = NULL;
4178         /* Lookup  in free list and find most fit one */
4179         LIST_FOREACH(entry, &pool->free_list, next) {
4180                 if (entry->len >= num) {
4181                         /* Find best one */
4182                         if (entry->len == num) {
4183                                 valid_entry = entry;
4184                                 break;
4185                         }
4186                         if (valid_entry == NULL || valid_entry->len > entry->len)
4187                                 valid_entry = entry;
4188                 }
4189         }
4190
4191         /* Not find one to satisfy the request, return */
4192         if (valid_entry == NULL) {
4193                 PMD_DRV_LOG(ERR, "No valid entry found");
4194                 return -ENOMEM;
4195         }
4196         /**
4197          * The entry have equal queue number as requested,
4198          * remove it from alloc_list.
4199          */
4200         if (valid_entry->len == num) {
4201                 LIST_REMOVE(valid_entry, next);
4202         } else {
4203                 /**
4204                  * The entry have more numbers than requested,
4205                  * create a new entry for alloc_list and minus its
4206                  * queue base and number in free_list.
4207                  */
4208                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4209                 if (entry == NULL) {
4210                         PMD_DRV_LOG(ERR,
4211                                 "Failed to allocate memory for resource pool");
4212                         return -ENOMEM;
4213                 }
4214                 entry->base = valid_entry->base;
4215                 entry->len = num;
4216                 valid_entry->base += num;
4217                 valid_entry->len -= num;
4218                 valid_entry = entry;
4219         }
4220
4221         /* Insert it into alloc list, not sorted */
4222         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4223
4224         pool->num_free -= valid_entry->len;
4225         pool->num_alloc += valid_entry->len;
4226
4227         return valid_entry->base + pool->base;
4228 }
4229
4230 /**
4231  * bitmap_is_subset - Check whether src2 is subset of src1
4232  **/
4233 static inline int
4234 bitmap_is_subset(uint8_t src1, uint8_t src2)
4235 {
4236         return !((src1 ^ src2) & src2);
4237 }
4238
4239 static enum i40e_status_code
4240 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4241 {
4242         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4243
4244         /* If DCB is not supported, only default TC is supported */
4245         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4246                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4247                 return I40E_NOT_SUPPORTED;
4248         }
4249
4250         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4251                 PMD_DRV_LOG(ERR,
4252                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4253                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4254                 return I40E_NOT_SUPPORTED;
4255         }
4256         return I40E_SUCCESS;
4257 }
4258
4259 int
4260 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4261                                 struct i40e_vsi_vlan_pvid_info *info)
4262 {
4263         struct i40e_hw *hw;
4264         struct i40e_vsi_context ctxt;
4265         uint8_t vlan_flags = 0;
4266         int ret;
4267
4268         if (vsi == NULL || info == NULL) {
4269                 PMD_DRV_LOG(ERR, "invalid parameters");
4270                 return I40E_ERR_PARAM;
4271         }
4272
4273         if (info->on) {
4274                 vsi->info.pvid = info->config.pvid;
4275                 /**
4276                  * If insert pvid is enabled, only tagged pkts are
4277                  * allowed to be sent out.
4278                  */
4279                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4280                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4281         } else {
4282                 vsi->info.pvid = 0;
4283                 if (info->config.reject.tagged == 0)
4284                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4285
4286                 if (info->config.reject.untagged == 0)
4287                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4288         }
4289         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4290                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4291         vsi->info.port_vlan_flags |= vlan_flags;
4292         vsi->info.valid_sections =
4293                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4294         memset(&ctxt, 0, sizeof(ctxt));
4295         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4296         ctxt.seid = vsi->seid;
4297
4298         hw = I40E_VSI_TO_HW(vsi);
4299         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4300         if (ret != I40E_SUCCESS)
4301                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4302
4303         return ret;
4304 }
4305
4306 static int
4307 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4308 {
4309         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4310         int i, ret;
4311         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4312
4313         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4314         if (ret != I40E_SUCCESS)
4315                 return ret;
4316
4317         if (!vsi->seid) {
4318                 PMD_DRV_LOG(ERR, "seid not valid");
4319                 return -EINVAL;
4320         }
4321
4322         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4323         tc_bw_data.tc_valid_bits = enabled_tcmap;
4324         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4325                 tc_bw_data.tc_bw_credits[i] =
4326                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4327
4328         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4329         if (ret != I40E_SUCCESS) {
4330                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4331                 return ret;
4332         }
4333
4334         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4335                                         sizeof(vsi->info.qs_handle));
4336         return I40E_SUCCESS;
4337 }
4338
4339 static enum i40e_status_code
4340 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4341                                  struct i40e_aqc_vsi_properties_data *info,
4342                                  uint8_t enabled_tcmap)
4343 {
4344         enum i40e_status_code ret;
4345         int i, total_tc = 0;
4346         uint16_t qpnum_per_tc, bsf, qp_idx;
4347
4348         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4349         if (ret != I40E_SUCCESS)
4350                 return ret;
4351
4352         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4353                 if (enabled_tcmap & (1 << i))
4354                         total_tc++;
4355         if (total_tc == 0)
4356                 total_tc = 1;
4357         vsi->enabled_tc = enabled_tcmap;
4358
4359         /* Number of queues per enabled TC */
4360         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4361         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4362         bsf = rte_bsf32(qpnum_per_tc);
4363
4364         /* Adjust the queue number to actual queues that can be applied */
4365         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4366                 vsi->nb_qps = qpnum_per_tc * total_tc;
4367
4368         /**
4369          * Configure TC and queue mapping parameters, for enabled TC,
4370          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4371          * default queue will serve it.
4372          */
4373         qp_idx = 0;
4374         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4375                 if (vsi->enabled_tc & (1 << i)) {
4376                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4377                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4378                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4379                         qp_idx += qpnum_per_tc;
4380                 } else
4381                         info->tc_mapping[i] = 0;
4382         }
4383
4384         /* Associate queue number with VSI */
4385         if (vsi->type == I40E_VSI_SRIOV) {
4386                 info->mapping_flags |=
4387                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4388                 for (i = 0; i < vsi->nb_qps; i++)
4389                         info->queue_mapping[i] =
4390                                 rte_cpu_to_le_16(vsi->base_queue + i);
4391         } else {
4392                 info->mapping_flags |=
4393                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4394                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4395         }
4396         info->valid_sections |=
4397                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4398
4399         return I40E_SUCCESS;
4400 }
4401
4402 static int
4403 i40e_veb_release(struct i40e_veb *veb)
4404 {
4405         struct i40e_vsi *vsi;
4406         struct i40e_hw *hw;
4407
4408         if (veb == NULL)
4409                 return -EINVAL;
4410
4411         if (!TAILQ_EMPTY(&veb->head)) {
4412                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4413                 return -EACCES;
4414         }
4415         /* associate_vsi field is NULL for floating VEB */
4416         if (veb->associate_vsi != NULL) {
4417                 vsi = veb->associate_vsi;
4418                 hw = I40E_VSI_TO_HW(vsi);
4419
4420                 vsi->uplink_seid = veb->uplink_seid;
4421                 vsi->veb = NULL;
4422         } else {
4423                 veb->associate_pf->main_vsi->floating_veb = NULL;
4424                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4425         }
4426
4427         i40e_aq_delete_element(hw, veb->seid, NULL);
4428         rte_free(veb);
4429         return I40E_SUCCESS;
4430 }
4431
4432 /* Setup a veb */
4433 static struct i40e_veb *
4434 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4435 {
4436         struct i40e_veb *veb;
4437         int ret;
4438         struct i40e_hw *hw;
4439
4440         if (pf == NULL) {
4441                 PMD_DRV_LOG(ERR,
4442                             "veb setup failed, associated PF shouldn't null");
4443                 return NULL;
4444         }
4445         hw = I40E_PF_TO_HW(pf);
4446
4447         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4448         if (!veb) {
4449                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4450                 goto fail;
4451         }
4452
4453         veb->associate_vsi = vsi;
4454         veb->associate_pf = pf;
4455         TAILQ_INIT(&veb->head);
4456         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4457
4458         /* create floating veb if vsi is NULL */
4459         if (vsi != NULL) {
4460                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4461                                       I40E_DEFAULT_TCMAP, false,
4462                                       &veb->seid, false, NULL);
4463         } else {
4464                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4465                                       true, &veb->seid, false, NULL);
4466         }
4467
4468         if (ret != I40E_SUCCESS) {
4469                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4470                             hw->aq.asq_last_status);
4471                 goto fail;
4472         }
4473         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4474
4475         /* get statistics index */
4476         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4477                                 &veb->stats_idx, NULL, NULL, NULL);
4478         if (ret != I40E_SUCCESS) {
4479                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4480                             hw->aq.asq_last_status);
4481                 goto fail;
4482         }
4483         /* Get VEB bandwidth, to be implemented */
4484         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4485         if (vsi)
4486                 vsi->uplink_seid = veb->seid;
4487
4488         return veb;
4489 fail:
4490         rte_free(veb);
4491         return NULL;
4492 }
4493
4494 int
4495 i40e_vsi_release(struct i40e_vsi *vsi)
4496 {
4497         struct i40e_pf *pf;
4498         struct i40e_hw *hw;
4499         struct i40e_vsi_list *vsi_list;
4500         void *temp;
4501         int ret;
4502         struct i40e_mac_filter *f;
4503         uint16_t user_param;
4504
4505         if (!vsi)
4506                 return I40E_SUCCESS;
4507
4508         if (!vsi->adapter)
4509                 return -EFAULT;
4510
4511         user_param = vsi->user_param;
4512
4513         pf = I40E_VSI_TO_PF(vsi);
4514         hw = I40E_VSI_TO_HW(vsi);
4515
4516         /* VSI has child to attach, release child first */
4517         if (vsi->veb) {
4518                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4519                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4520                                 return -1;
4521                 }
4522                 i40e_veb_release(vsi->veb);
4523         }
4524
4525         if (vsi->floating_veb) {
4526                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4527                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4528                                 return -1;
4529                 }
4530         }
4531
4532         /* Remove all macvlan filters of the VSI */
4533         i40e_vsi_remove_all_macvlan_filter(vsi);
4534         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4535                 rte_free(f);
4536
4537         if (vsi->type != I40E_VSI_MAIN &&
4538             ((vsi->type != I40E_VSI_SRIOV) ||
4539             !pf->floating_veb_list[user_param])) {
4540                 /* Remove vsi from parent's sibling list */
4541                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4542                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4543                         return I40E_ERR_PARAM;
4544                 }
4545                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4546                                 &vsi->sib_vsi_list, list);
4547
4548                 /* Remove all switch element of the VSI */
4549                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4550                 if (ret != I40E_SUCCESS)
4551                         PMD_DRV_LOG(ERR, "Failed to delete element");
4552         }
4553
4554         if ((vsi->type == I40E_VSI_SRIOV) &&
4555             pf->floating_veb_list[user_param]) {
4556                 /* Remove vsi from parent's sibling list */
4557                 if (vsi->parent_vsi == NULL ||
4558                     vsi->parent_vsi->floating_veb == NULL) {
4559                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4560                         return I40E_ERR_PARAM;
4561                 }
4562                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4563                              &vsi->sib_vsi_list, list);
4564
4565                 /* Remove all switch element of the VSI */
4566                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4567                 if (ret != I40E_SUCCESS)
4568                         PMD_DRV_LOG(ERR, "Failed to delete element");
4569         }
4570
4571         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4572
4573         if (vsi->type != I40E_VSI_SRIOV)
4574                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4575         rte_free(vsi);
4576
4577         return I40E_SUCCESS;
4578 }
4579
4580 static int
4581 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4582 {
4583         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4584         struct i40e_aqc_remove_macvlan_element_data def_filter;
4585         struct i40e_mac_filter_info filter;
4586         int ret;
4587
4588         if (vsi->type != I40E_VSI_MAIN)
4589                 return I40E_ERR_CONFIG;
4590         memset(&def_filter, 0, sizeof(def_filter));
4591         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4592                                         ETH_ADDR_LEN);
4593         def_filter.vlan_tag = 0;
4594         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4595                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4596         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4597         if (ret != I40E_SUCCESS) {
4598                 struct i40e_mac_filter *f;
4599                 struct ether_addr *mac;
4600
4601                 PMD_DRV_LOG(DEBUG,
4602                             "Cannot remove the default macvlan filter");
4603                 /* It needs to add the permanent mac into mac list */
4604                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4605                 if (f == NULL) {
4606                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4607                         return I40E_ERR_NO_MEMORY;
4608                 }
4609                 mac = &f->mac_info.mac_addr;
4610                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4611                                 ETH_ADDR_LEN);
4612                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4613                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4614                 vsi->mac_num++;
4615
4616                 return ret;
4617         }
4618         (void)rte_memcpy(&filter.mac_addr,
4619                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4620         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4621         return i40e_vsi_add_mac(vsi, &filter);
4622 }
4623
4624 /*
4625  * i40e_vsi_get_bw_config - Query VSI BW Information
4626  * @vsi: the VSI to be queried
4627  *
4628  * Returns 0 on success, negative value on failure
4629  */
4630 static enum i40e_status_code
4631 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4632 {
4633         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4634         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4635         struct i40e_hw *hw = &vsi->adapter->hw;
4636         i40e_status ret;
4637         int i;
4638         uint32_t bw_max;
4639
4640         memset(&bw_config, 0, sizeof(bw_config));
4641         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4642         if (ret != I40E_SUCCESS) {
4643                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4644                             hw->aq.asq_last_status);
4645                 return ret;
4646         }
4647
4648         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4649         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4650                                         &ets_sla_config, NULL);
4651         if (ret != I40E_SUCCESS) {
4652                 PMD_DRV_LOG(ERR,
4653                         "VSI failed to get TC bandwdith configuration %u",
4654                         hw->aq.asq_last_status);
4655                 return ret;
4656         }
4657
4658         /* store and print out BW info */
4659         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4660         vsi->bw_info.bw_max = bw_config.max_bw;
4661         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4662         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4663         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4664                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4665                      I40E_16_BIT_WIDTH);
4666         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4667                 vsi->bw_info.bw_ets_share_credits[i] =
4668                                 ets_sla_config.share_credits[i];
4669                 vsi->bw_info.bw_ets_credits[i] =
4670                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4671                 /* 4 bits per TC, 4th bit is reserved */
4672                 vsi->bw_info.bw_ets_max[i] =
4673                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4674                                   RTE_LEN2MASK(3, uint8_t));
4675                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4676                             vsi->bw_info.bw_ets_share_credits[i]);
4677                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4678                             vsi->bw_info.bw_ets_credits[i]);
4679                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4680                             vsi->bw_info.bw_ets_max[i]);
4681         }
4682
4683         return I40E_SUCCESS;
4684 }
4685
4686 /* i40e_enable_pf_lb
4687  * @pf: pointer to the pf structure
4688  *
4689  * allow loopback on pf
4690  */
4691 static inline void
4692 i40e_enable_pf_lb(struct i40e_pf *pf)
4693 {
4694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4695         struct i40e_vsi_context ctxt;
4696         int ret;
4697
4698         /* Use the FW API if FW >= v5.0 */
4699         if (hw->aq.fw_maj_ver < 5) {
4700                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4701                 return;
4702         }
4703
4704         memset(&ctxt, 0, sizeof(ctxt));
4705         ctxt.seid = pf->main_vsi_seid;
4706         ctxt.pf_num = hw->pf_id;
4707         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4708         if (ret) {
4709                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4710                             ret, hw->aq.asq_last_status);
4711                 return;
4712         }
4713         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4714         ctxt.info.valid_sections =
4715                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4716         ctxt.info.switch_id |=
4717                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4718
4719         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4720         if (ret)
4721                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4722                             hw->aq.asq_last_status);
4723 }
4724
4725 /* Setup a VSI */
4726 struct i40e_vsi *
4727 i40e_vsi_setup(struct i40e_pf *pf,
4728                enum i40e_vsi_type type,
4729                struct i40e_vsi *uplink_vsi,
4730                uint16_t user_param)
4731 {
4732         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4733         struct i40e_vsi *vsi;
4734         struct i40e_mac_filter_info filter;
4735         int ret;
4736         struct i40e_vsi_context ctxt;
4737         struct ether_addr broadcast =
4738                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4739
4740         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4741             uplink_vsi == NULL) {
4742                 PMD_DRV_LOG(ERR,
4743                         "VSI setup failed, VSI link shouldn't be NULL");
4744                 return NULL;
4745         }
4746
4747         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4748                 PMD_DRV_LOG(ERR,
4749                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4750                 return NULL;
4751         }
4752
4753         /* two situations
4754          * 1.type is not MAIN and uplink vsi is not NULL
4755          * If uplink vsi didn't setup VEB, create one first under veb field
4756          * 2.type is SRIOV and the uplink is NULL
4757          * If floating VEB is NULL, create one veb under floating veb field
4758          */
4759
4760         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4761             uplink_vsi->veb == NULL) {
4762                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4763
4764                 if (uplink_vsi->veb == NULL) {
4765                         PMD_DRV_LOG(ERR, "VEB setup failed");
4766                         return NULL;
4767                 }
4768                 /* set ALLOWLOOPBACk on pf, when veb is created */
4769                 i40e_enable_pf_lb(pf);
4770         }
4771
4772         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4773             pf->main_vsi->floating_veb == NULL) {
4774                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4775
4776                 if (pf->main_vsi->floating_veb == NULL) {
4777                         PMD_DRV_LOG(ERR, "VEB setup failed");
4778                         return NULL;
4779                 }
4780         }
4781
4782         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4783         if (!vsi) {
4784                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4785                 return NULL;
4786         }
4787         TAILQ_INIT(&vsi->mac_list);
4788         vsi->type = type;
4789         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4790         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4791         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4792         vsi->user_param = user_param;
4793         vsi->vlan_anti_spoof_on = 0;
4794         vsi->vlan_filter_on = 0;
4795         /* Allocate queues */
4796         switch (vsi->type) {
4797         case I40E_VSI_MAIN  :
4798                 vsi->nb_qps = pf->lan_nb_qps;
4799                 break;
4800         case I40E_VSI_SRIOV :
4801                 vsi->nb_qps = pf->vf_nb_qps;
4802                 break;
4803         case I40E_VSI_VMDQ2:
4804                 vsi->nb_qps = pf->vmdq_nb_qps;
4805                 break;
4806         case I40E_VSI_FDIR:
4807                 vsi->nb_qps = pf->fdir_nb_qps;
4808                 break;
4809         default:
4810                 goto fail_mem;
4811         }
4812         /*
4813          * The filter status descriptor is reported in rx queue 0,
4814          * while the tx queue for fdir filter programming has no
4815          * such constraints, can be non-zero queues.
4816          * To simplify it, choose FDIR vsi use queue 0 pair.
4817          * To make sure it will use queue 0 pair, queue allocation
4818          * need be done before this function is called
4819          */
4820         if (type != I40E_VSI_FDIR) {
4821                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4822                         if (ret < 0) {
4823                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4824                                                 vsi->seid, ret);
4825                                 goto fail_mem;
4826                         }
4827                         vsi->base_queue = ret;
4828         } else
4829                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4830
4831         /* VF has MSIX interrupt in VF range, don't allocate here */
4832         if (type == I40E_VSI_MAIN) {
4833                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4834                                           RTE_MIN(vsi->nb_qps,
4835                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4836                 if (ret < 0) {
4837                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4838                                     vsi->seid, ret);
4839                         goto fail_queue_alloc;
4840                 }
4841                 vsi->msix_intr = ret;
4842                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4843         } else if (type != I40E_VSI_SRIOV) {
4844                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4845                 if (ret < 0) {
4846                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4847                         goto fail_queue_alloc;
4848                 }
4849                 vsi->msix_intr = ret;
4850                 vsi->nb_msix = 1;
4851         } else {
4852                 vsi->msix_intr = 0;
4853                 vsi->nb_msix = 0;
4854         }
4855
4856         /* Add VSI */
4857         if (type == I40E_VSI_MAIN) {
4858                 /* For main VSI, no need to add since it's default one */
4859                 vsi->uplink_seid = pf->mac_seid;
4860                 vsi->seid = pf->main_vsi_seid;
4861                 /* Bind queues with specific MSIX interrupt */
4862                 /**
4863                  * Needs 2 interrupt at least, one for misc cause which will
4864                  * enabled from OS side, Another for queues binding the
4865                  * interrupt from device side only.
4866                  */
4867
4868                 /* Get default VSI parameters from hardware */
4869                 memset(&ctxt, 0, sizeof(ctxt));
4870                 ctxt.seid = vsi->seid;
4871                 ctxt.pf_num = hw->pf_id;
4872                 ctxt.uplink_seid = vsi->uplink_seid;
4873                 ctxt.vf_num = 0;
4874                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4875                 if (ret != I40E_SUCCESS) {
4876                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4877                         goto fail_msix_alloc;
4878                 }
4879                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4880                         sizeof(struct i40e_aqc_vsi_properties_data));
4881                 vsi->vsi_id = ctxt.vsi_number;
4882                 vsi->info.valid_sections = 0;
4883
4884                 /* Configure tc, enabled TC0 only */
4885                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4886                         I40E_SUCCESS) {
4887                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4888                         goto fail_msix_alloc;
4889                 }
4890
4891                 /* TC, queue mapping */
4892                 memset(&ctxt, 0, sizeof(ctxt));
4893                 vsi->info.valid_sections |=
4894                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4895                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4896                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4897                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4898                         sizeof(struct i40e_aqc_vsi_properties_data));
4899                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4900                                                 I40E_DEFAULT_TCMAP);
4901                 if (ret != I40E_SUCCESS) {
4902                         PMD_DRV_LOG(ERR,
4903                                 "Failed to configure TC queue mapping");
4904                         goto fail_msix_alloc;
4905                 }
4906                 ctxt.seid = vsi->seid;
4907                 ctxt.pf_num = hw->pf_id;
4908                 ctxt.uplink_seid = vsi->uplink_seid;
4909                 ctxt.vf_num = 0;
4910
4911                 /* Update VSI parameters */
4912                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4913                 if (ret != I40E_SUCCESS) {
4914                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4915                         goto fail_msix_alloc;
4916                 }
4917
4918                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4919                                                 sizeof(vsi->info.tc_mapping));
4920                 (void)rte_memcpy(&vsi->info.queue_mapping,
4921                                 &ctxt.info.queue_mapping,
4922                         sizeof(vsi->info.queue_mapping));
4923                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4924                 vsi->info.valid_sections = 0;
4925
4926                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4927                                 ETH_ADDR_LEN);
4928
4929                 /**
4930                  * Updating default filter settings are necessary to prevent
4931                  * reception of tagged packets.
4932                  * Some old firmware configurations load a default macvlan
4933                  * filter which accepts both tagged and untagged packets.
4934                  * The updating is to use a normal filter instead if needed.
4935                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4936                  * The firmware with correct configurations load the default
4937                  * macvlan filter which is expected and cannot be removed.
4938                  */
4939                 i40e_update_default_filter_setting(vsi);
4940                 i40e_config_qinq(hw, vsi);
4941         } else if (type == I40E_VSI_SRIOV) {
4942                 memset(&ctxt, 0, sizeof(ctxt));
4943                 /**
4944                  * For other VSI, the uplink_seid equals to uplink VSI's
4945                  * uplink_seid since they share same VEB
4946                  */
4947                 if (uplink_vsi == NULL)
4948                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4949                 else
4950                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4951                 ctxt.pf_num = hw->pf_id;
4952                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4953                 ctxt.uplink_seid = vsi->uplink_seid;
4954                 ctxt.connection_type = 0x1;
4955                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4956
4957                 /* Use the VEB configuration if FW >= v5.0 */
4958                 if (hw->aq.fw_maj_ver >= 5) {
4959                         /* Configure switch ID */
4960                         ctxt.info.valid_sections |=
4961                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4962                         ctxt.info.switch_id =
4963                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4964                 }
4965
4966                 /* Configure port/vlan */
4967                 ctxt.info.valid_sections |=
4968                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4969                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4970                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4971                                                 hw->func_caps.enabled_tcmap);
4972                 if (ret != I40E_SUCCESS) {
4973                         PMD_DRV_LOG(ERR,
4974                                 "Failed to configure TC queue mapping");
4975                         goto fail_msix_alloc;
4976                 }
4977
4978                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4979                 ctxt.info.valid_sections |=
4980                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4981                 /**
4982                  * Since VSI is not created yet, only configure parameter,
4983                  * will add vsi below.
4984                  */
4985
4986                 i40e_config_qinq(hw, vsi);
4987         } else if (type == I40E_VSI_VMDQ2) {
4988                 memset(&ctxt, 0, sizeof(ctxt));
4989                 /*
4990                  * For other VSI, the uplink_seid equals to uplink VSI's
4991                  * uplink_seid since they share same VEB
4992                  */
4993                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4994                 ctxt.pf_num = hw->pf_id;
4995                 ctxt.vf_num = 0;
4996                 ctxt.uplink_seid = vsi->uplink_seid;
4997                 ctxt.connection_type = 0x1;
4998                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4999
5000                 ctxt.info.valid_sections |=
5001                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5002                 /* user_param carries flag to enable loop back */
5003                 if (user_param) {
5004                         ctxt.info.switch_id =
5005                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5006                         ctxt.info.switch_id |=
5007                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5008                 }
5009
5010                 /* Configure port/vlan */
5011                 ctxt.info.valid_sections |=
5012                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5013                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5014                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5015                                                 I40E_DEFAULT_TCMAP);
5016                 if (ret != I40E_SUCCESS) {
5017                         PMD_DRV_LOG(ERR,
5018                                 "Failed to configure TC queue mapping");
5019                         goto fail_msix_alloc;
5020                 }
5021                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5022                 ctxt.info.valid_sections |=
5023                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5024         } else if (type == I40E_VSI_FDIR) {
5025                 memset(&ctxt, 0, sizeof(ctxt));
5026                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5027                 ctxt.pf_num = hw->pf_id;
5028                 ctxt.vf_num = 0;
5029                 ctxt.uplink_seid = vsi->uplink_seid;
5030                 ctxt.connection_type = 0x1;     /* regular data port */
5031                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5032                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5033                                                 I40E_DEFAULT_TCMAP);
5034                 if (ret != I40E_SUCCESS) {
5035                         PMD_DRV_LOG(ERR,
5036                                 "Failed to configure TC queue mapping.");
5037                         goto fail_msix_alloc;
5038                 }
5039                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5040                 ctxt.info.valid_sections |=
5041                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5042         } else {
5043                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5044                 goto fail_msix_alloc;
5045         }
5046
5047         if (vsi->type != I40E_VSI_MAIN) {
5048                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5049                 if (ret != I40E_SUCCESS) {
5050                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5051                                     hw->aq.asq_last_status);
5052                         goto fail_msix_alloc;
5053                 }
5054                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5055                 vsi->info.valid_sections = 0;
5056                 vsi->seid = ctxt.seid;
5057                 vsi->vsi_id = ctxt.vsi_number;
5058                 vsi->sib_vsi_list.vsi = vsi;
5059                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5060                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5061                                           &vsi->sib_vsi_list, list);
5062                 } else {
5063                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5064                                           &vsi->sib_vsi_list, list);
5065                 }
5066         }
5067
5068         /* MAC/VLAN configuration */
5069         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5070         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5071
5072         ret = i40e_vsi_add_mac(vsi, &filter);
5073         if (ret != I40E_SUCCESS) {
5074                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5075                 goto fail_msix_alloc;
5076         }
5077
5078         /* Get VSI BW information */
5079         i40e_vsi_get_bw_config(vsi);
5080         return vsi;
5081 fail_msix_alloc:
5082         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5083 fail_queue_alloc:
5084         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5085 fail_mem:
5086         rte_free(vsi);
5087         return NULL;
5088 }
5089
5090 /* Configure vlan filter on or off */
5091 int
5092 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5093 {
5094         int i, num;
5095         struct i40e_mac_filter *f;
5096         void *temp;
5097         struct i40e_mac_filter_info *mac_filter;
5098         enum rte_mac_filter_type desired_filter;
5099         int ret = I40E_SUCCESS;
5100
5101         if (on) {
5102                 /* Filter to match MAC and VLAN */
5103                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5104         } else {
5105                 /* Filter to match only MAC */
5106                 desired_filter = RTE_MAC_PERFECT_MATCH;
5107         }
5108
5109         num = vsi->mac_num;
5110
5111         mac_filter = rte_zmalloc("mac_filter_info_data",
5112                                  num * sizeof(*mac_filter), 0);
5113         if (mac_filter == NULL) {
5114                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5115                 return I40E_ERR_NO_MEMORY;
5116         }
5117
5118         i = 0;
5119
5120         /* Remove all existing mac */
5121         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5122                 mac_filter[i] = f->mac_info;
5123                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5124                 if (ret) {
5125                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5126                                     on ? "enable" : "disable");
5127                         goto DONE;
5128                 }
5129                 i++;
5130         }
5131
5132         /* Override with new filter */
5133         for (i = 0; i < num; i++) {
5134                 mac_filter[i].filter_type = desired_filter;
5135                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5136                 if (ret) {
5137                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5138                                     on ? "enable" : "disable");
5139                         goto DONE;
5140                 }
5141         }
5142
5143 DONE:
5144         rte_free(mac_filter);
5145         return ret;
5146 }
5147
5148 /* Configure vlan stripping on or off */
5149 int
5150 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5151 {
5152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5153         struct i40e_vsi_context ctxt;
5154         uint8_t vlan_flags;
5155         int ret = I40E_SUCCESS;
5156
5157         /* Check if it has been already on or off */
5158         if (vsi->info.valid_sections &
5159                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5160                 if (on) {
5161                         if ((vsi->info.port_vlan_flags &
5162                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5163                                 return 0; /* already on */
5164                 } else {
5165                         if ((vsi->info.port_vlan_flags &
5166                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5167                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5168                                 return 0; /* already off */
5169                 }
5170         }
5171
5172         if (on)
5173                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5174         else
5175                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5176         vsi->info.valid_sections =
5177                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5178         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5179         vsi->info.port_vlan_flags |= vlan_flags;
5180         ctxt.seid = vsi->seid;
5181         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5182         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5183         if (ret)
5184                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5185                             on ? "enable" : "disable");
5186
5187         return ret;
5188 }
5189
5190 static int
5191 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5192 {
5193         struct rte_eth_dev_data *data = dev->data;
5194         int ret;
5195         int mask = 0;
5196
5197         /* Apply vlan offload setting */
5198         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5199         i40e_vlan_offload_set(dev, mask);
5200
5201         /* Apply double-vlan setting, not implemented yet */
5202
5203         /* Apply pvid setting */
5204         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5205                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5206         if (ret)
5207                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5208
5209         return ret;
5210 }
5211
5212 static int
5213 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5214 {
5215         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5216
5217         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5218 }
5219
5220 static int
5221 i40e_update_flow_control(struct i40e_hw *hw)
5222 {
5223 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5224         struct i40e_link_status link_status;
5225         uint32_t rxfc = 0, txfc = 0, reg;
5226         uint8_t an_info;
5227         int ret;
5228
5229         memset(&link_status, 0, sizeof(link_status));
5230         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5231         if (ret != I40E_SUCCESS) {
5232                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5233                 goto write_reg; /* Disable flow control */
5234         }
5235
5236         an_info = hw->phy.link_info.an_info;
5237         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5238                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5239                 ret = I40E_ERR_NOT_READY;
5240                 goto write_reg; /* Disable flow control */
5241         }
5242         /**
5243          * If link auto negotiation is enabled, flow control needs to
5244          * be configured according to it
5245          */
5246         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5247         case I40E_LINK_PAUSE_RXTX:
5248                 rxfc = 1;
5249                 txfc = 1;
5250                 hw->fc.current_mode = I40E_FC_FULL;
5251                 break;
5252         case I40E_AQ_LINK_PAUSE_RX:
5253                 rxfc = 1;
5254                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5255                 break;
5256         case I40E_AQ_LINK_PAUSE_TX:
5257                 txfc = 1;
5258                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5259                 break;
5260         default:
5261                 hw->fc.current_mode = I40E_FC_NONE;
5262                 break;
5263         }
5264
5265 write_reg:
5266         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5267                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5268         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5269         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5270         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5271         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5272
5273         return ret;
5274 }
5275
5276 /* PF setup */
5277 static int
5278 i40e_pf_setup(struct i40e_pf *pf)
5279 {
5280         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5281         struct i40e_filter_control_settings settings;
5282         struct i40e_vsi *vsi;
5283         int ret;
5284
5285         /* Clear all stats counters */
5286         pf->offset_loaded = FALSE;
5287         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5288         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5289         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5290         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5291
5292         ret = i40e_pf_get_switch_config(pf);
5293         if (ret != I40E_SUCCESS) {
5294                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5295                 return ret;
5296         }
5297         if (pf->flags & I40E_FLAG_FDIR) {
5298                 /* make queue allocated first, let FDIR use queue pair 0*/
5299                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5300                 if (ret != I40E_FDIR_QUEUE_ID) {
5301                         PMD_DRV_LOG(ERR,
5302                                 "queue allocation fails for FDIR: ret =%d",
5303                                 ret);
5304                         pf->flags &= ~I40E_FLAG_FDIR;
5305                 }
5306         }
5307         /*  main VSI setup */
5308         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5309         if (!vsi) {
5310                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5311                 return I40E_ERR_NOT_READY;
5312         }
5313         pf->main_vsi = vsi;
5314
5315         /* Configure filter control */
5316         memset(&settings, 0, sizeof(settings));
5317         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5318                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5319         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5320                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5321         else {
5322                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5323                         hw->func_caps.rss_table_size);
5324                 return I40E_ERR_PARAM;
5325         }
5326         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5327                 hw->func_caps.rss_table_size);
5328         pf->hash_lut_size = hw->func_caps.rss_table_size;
5329
5330         /* Enable ethtype and macvlan filters */
5331         settings.enable_ethtype = TRUE;
5332         settings.enable_macvlan = TRUE;
5333         ret = i40e_set_filter_control(hw, &settings);
5334         if (ret)
5335                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5336                                                                 ret);
5337
5338         /* Update flow control according to the auto negotiation */
5339         i40e_update_flow_control(hw);
5340
5341         return I40E_SUCCESS;
5342 }
5343
5344 int
5345 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5346 {
5347         uint32_t reg;
5348         uint16_t j;
5349
5350         /**
5351          * Set or clear TX Queue Disable flags,
5352          * which is required by hardware.
5353          */
5354         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5355         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5356
5357         /* Wait until the request is finished */
5358         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5359                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5360                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5361                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5362                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5363                                                         & 0x1))) {
5364                         break;
5365                 }
5366         }
5367         if (on) {
5368                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5369                         return I40E_SUCCESS; /* already on, skip next steps */
5370
5371                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5372                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5373         } else {
5374                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5375                         return I40E_SUCCESS; /* already off, skip next steps */
5376                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5377         }
5378         /* Write the register */
5379         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5380         /* Check the result */
5381         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5382                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5383                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5384                 if (on) {
5385                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5386                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5387                                 break;
5388                 } else {
5389                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5390                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5391                                 break;
5392                 }
5393         }
5394         /* Check if it is timeout */
5395         if (j >= I40E_CHK_Q_ENA_COUNT) {
5396                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5397                             (on ? "enable" : "disable"), q_idx);
5398                 return I40E_ERR_TIMEOUT;
5399         }
5400
5401         return I40E_SUCCESS;
5402 }
5403
5404 /* Swith on or off the tx queues */
5405 static int
5406 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5407 {
5408         struct rte_eth_dev_data *dev_data = pf->dev_data;
5409         struct i40e_tx_queue *txq;
5410         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5411         uint16_t i;
5412         int ret;
5413
5414         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5415                 txq = dev_data->tx_queues[i];
5416                 /* Don't operate the queue if not configured or
5417                  * if starting only per queue */
5418                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5419                         continue;
5420                 if (on)
5421                         ret = i40e_dev_tx_queue_start(dev, i);
5422                 else
5423                         ret = i40e_dev_tx_queue_stop(dev, i);
5424                 if ( ret != I40E_SUCCESS)
5425                         return ret;
5426         }
5427
5428         return I40E_SUCCESS;
5429 }
5430
5431 int
5432 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5433 {
5434         uint32_t reg;
5435         uint16_t j;
5436
5437         /* Wait until the request is finished */
5438         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5439                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5440                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5441                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5442                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5443                         break;
5444         }
5445
5446         if (on) {
5447                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5448                         return I40E_SUCCESS; /* Already on, skip next steps */
5449                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5450         } else {
5451                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5452                         return I40E_SUCCESS; /* Already off, skip next steps */
5453                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5454         }
5455
5456         /* Write the register */
5457         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5458         /* Check the result */
5459         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5460                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5461                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5462                 if (on) {
5463                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5464                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5465                                 break;
5466                 } else {
5467                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5468                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5469                                 break;
5470                 }
5471         }
5472
5473         /* Check if it is timeout */
5474         if (j >= I40E_CHK_Q_ENA_COUNT) {
5475                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5476                             (on ? "enable" : "disable"), q_idx);
5477                 return I40E_ERR_TIMEOUT;
5478         }
5479
5480         return I40E_SUCCESS;
5481 }
5482 /* Switch on or off the rx queues */
5483 static int
5484 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5485 {
5486         struct rte_eth_dev_data *dev_data = pf->dev_data;
5487         struct i40e_rx_queue *rxq;
5488         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5489         uint16_t i;
5490         int ret;
5491
5492         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5493                 rxq = dev_data->rx_queues[i];
5494                 /* Don't operate the queue if not configured or
5495                  * if starting only per queue */
5496                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5497                         continue;
5498                 if (on)
5499                         ret = i40e_dev_rx_queue_start(dev, i);
5500                 else
5501                         ret = i40e_dev_rx_queue_stop(dev, i);
5502                 if (ret != I40E_SUCCESS)
5503                         return ret;
5504         }
5505
5506         return I40E_SUCCESS;
5507 }
5508
5509 /* Switch on or off all the rx/tx queues */
5510 int
5511 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5512 {
5513         int ret;
5514
5515         if (on) {
5516                 /* enable rx queues before enabling tx queues */
5517                 ret = i40e_dev_switch_rx_queues(pf, on);
5518                 if (ret) {
5519                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5520                         return ret;
5521                 }
5522                 ret = i40e_dev_switch_tx_queues(pf, on);
5523         } else {
5524                 /* Stop tx queues before stopping rx queues */
5525                 ret = i40e_dev_switch_tx_queues(pf, on);
5526                 if (ret) {
5527                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5528                         return ret;
5529                 }
5530                 ret = i40e_dev_switch_rx_queues(pf, on);
5531         }
5532
5533         return ret;
5534 }
5535
5536 /* Initialize VSI for TX */
5537 static int
5538 i40e_dev_tx_init(struct i40e_pf *pf)
5539 {
5540         struct rte_eth_dev_data *data = pf->dev_data;
5541         uint16_t i;
5542         uint32_t ret = I40E_SUCCESS;
5543         struct i40e_tx_queue *txq;
5544
5545         for (i = 0; i < data->nb_tx_queues; i++) {
5546                 txq = data->tx_queues[i];
5547                 if (!txq || !txq->q_set)
5548                         continue;
5549                 ret = i40e_tx_queue_init(txq);
5550                 if (ret != I40E_SUCCESS)
5551                         break;
5552         }
5553         if (ret == I40E_SUCCESS)
5554                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5555                                      ->eth_dev);
5556
5557         return ret;
5558 }
5559
5560 /* Initialize VSI for RX */
5561 static int
5562 i40e_dev_rx_init(struct i40e_pf *pf)
5563 {
5564         struct rte_eth_dev_data *data = pf->dev_data;
5565         int ret = I40E_SUCCESS;
5566         uint16_t i;
5567         struct i40e_rx_queue *rxq;
5568
5569         i40e_pf_config_mq_rx(pf);
5570         for (i = 0; i < data->nb_rx_queues; i++) {
5571                 rxq = data->rx_queues[i];
5572                 if (!rxq || !rxq->q_set)
5573                         continue;
5574
5575                 ret = i40e_rx_queue_init(rxq);
5576                 if (ret != I40E_SUCCESS) {
5577                         PMD_DRV_LOG(ERR,
5578                                 "Failed to do RX queue initialization");
5579                         break;
5580                 }
5581         }
5582         if (ret == I40E_SUCCESS)
5583                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5584                                      ->eth_dev);
5585
5586         return ret;
5587 }
5588
5589 static int
5590 i40e_dev_rxtx_init(struct i40e_pf *pf)
5591 {
5592         int err;
5593
5594         err = i40e_dev_tx_init(pf);
5595         if (err) {
5596                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5597                 return err;
5598         }
5599         err = i40e_dev_rx_init(pf);
5600         if (err) {
5601                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5602                 return err;
5603         }
5604
5605         return err;
5606 }
5607
5608 static int
5609 i40e_vmdq_setup(struct rte_eth_dev *dev)
5610 {
5611         struct rte_eth_conf *conf = &dev->data->dev_conf;
5612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5613         int i, err, conf_vsis, j, loop;
5614         struct i40e_vsi *vsi;
5615         struct i40e_vmdq_info *vmdq_info;
5616         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5617         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5618
5619         /*
5620          * Disable interrupt to avoid message from VF. Furthermore, it will
5621          * avoid race condition in VSI creation/destroy.
5622          */
5623         i40e_pf_disable_irq0(hw);
5624
5625         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5626                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5627                 return -ENOTSUP;
5628         }
5629
5630         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5631         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5632                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5633                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5634                         pf->max_nb_vmdq_vsi);
5635                 return -ENOTSUP;
5636         }
5637
5638         if (pf->vmdq != NULL) {
5639                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5640                 return 0;
5641         }
5642
5643         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5644                                 sizeof(*vmdq_info) * conf_vsis, 0);
5645
5646         if (pf->vmdq == NULL) {
5647                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5648                 return -ENOMEM;
5649         }
5650
5651         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5652
5653         /* Create VMDQ VSI */
5654         for (i = 0; i < conf_vsis; i++) {
5655                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5656                                 vmdq_conf->enable_loop_back);
5657                 if (vsi == NULL) {
5658                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5659                         err = -1;
5660                         goto err_vsi_setup;
5661                 }
5662                 vmdq_info = &pf->vmdq[i];
5663                 vmdq_info->pf = pf;
5664                 vmdq_info->vsi = vsi;
5665         }
5666         pf->nb_cfg_vmdq_vsi = conf_vsis;
5667
5668         /* Configure Vlan */
5669         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5670         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5671                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5672                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5673                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5674                                         vmdq_conf->pool_map[i].vlan_id, j);
5675
5676                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5677                                                 vmdq_conf->pool_map[i].vlan_id);
5678                                 if (err) {
5679                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5680                                         err = -1;
5681                                         goto err_vsi_setup;
5682                                 }
5683                         }
5684                 }
5685         }
5686
5687         i40e_pf_enable_irq0(hw);
5688
5689         return 0;
5690
5691 err_vsi_setup:
5692         for (i = 0; i < conf_vsis; i++)
5693                 if (pf->vmdq[i].vsi == NULL)
5694                         break;
5695                 else
5696                         i40e_vsi_release(pf->vmdq[i].vsi);
5697
5698         rte_free(pf->vmdq);
5699         pf->vmdq = NULL;
5700         i40e_pf_enable_irq0(hw);
5701         return err;
5702 }
5703
5704 static void
5705 i40e_stat_update_32(struct i40e_hw *hw,
5706                    uint32_t reg,
5707                    bool offset_loaded,
5708                    uint64_t *offset,
5709                    uint64_t *stat)
5710 {
5711         uint64_t new_data;
5712
5713         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5714         if (!offset_loaded)
5715                 *offset = new_data;
5716
5717         if (new_data >= *offset)
5718                 *stat = (uint64_t)(new_data - *offset);
5719         else
5720                 *stat = (uint64_t)((new_data +
5721                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5722 }
5723
5724 static void
5725 i40e_stat_update_48(struct i40e_hw *hw,
5726                    uint32_t hireg,
5727                    uint32_t loreg,
5728                    bool offset_loaded,
5729                    uint64_t *offset,
5730                    uint64_t *stat)
5731 {
5732         uint64_t new_data;
5733
5734         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5735         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5736                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5737
5738         if (!offset_loaded)
5739                 *offset = new_data;
5740
5741         if (new_data >= *offset)
5742                 *stat = new_data - *offset;
5743         else
5744                 *stat = (uint64_t)((new_data +
5745                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5746
5747         *stat &= I40E_48_BIT_MASK;
5748 }
5749
5750 /* Disable IRQ0 */
5751 void
5752 i40e_pf_disable_irq0(struct i40e_hw *hw)
5753 {
5754         /* Disable all interrupt types */
5755         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5756         I40E_WRITE_FLUSH(hw);
5757 }
5758
5759 /* Enable IRQ0 */
5760 void
5761 i40e_pf_enable_irq0(struct i40e_hw *hw)
5762 {
5763         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5764                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5765                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5766                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5767         I40E_WRITE_FLUSH(hw);
5768 }
5769
5770 static void
5771 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5772 {
5773         /* read pending request and disable first */
5774         i40e_pf_disable_irq0(hw);
5775         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5776         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5777                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5778
5779         if (no_queue)
5780                 /* Link no queues with irq0 */
5781                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5782                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5783 }
5784
5785 static void
5786 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5787 {
5788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5790         int i;
5791         uint16_t abs_vf_id;
5792         uint32_t index, offset, val;
5793
5794         if (!pf->vfs)
5795                 return;
5796         /**
5797          * Try to find which VF trigger a reset, use absolute VF id to access
5798          * since the reg is global register.
5799          */
5800         for (i = 0; i < pf->vf_num; i++) {
5801                 abs_vf_id = hw->func_caps.vf_base_id + i;
5802                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5803                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5804                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5805                 /* VFR event occurred */
5806                 if (val & (0x1 << offset)) {
5807                         int ret;
5808
5809                         /* Clear the event first */
5810                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5811                                                         (0x1 << offset));
5812                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5813                         /**
5814                          * Only notify a VF reset event occurred,
5815                          * don't trigger another SW reset
5816                          */
5817                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5818                         if (ret != I40E_SUCCESS)
5819                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5820                 }
5821         }
5822 }
5823
5824 static void
5825 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5826 {
5827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5828         int i;
5829
5830         for (i = 0; i < pf->vf_num; i++)
5831                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5832 }
5833
5834 static void
5835 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5836 {
5837         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5838         struct i40e_arq_event_info info;
5839         uint16_t pending, opcode;
5840         int ret;
5841
5842         info.buf_len = I40E_AQ_BUF_SZ;
5843         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5844         if (!info.msg_buf) {
5845                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5846                 return;
5847         }
5848
5849         pending = 1;
5850         while (pending) {
5851                 ret = i40e_clean_arq_element(hw, &info, &pending);
5852
5853                 if (ret != I40E_SUCCESS) {
5854                         PMD_DRV_LOG(INFO,
5855                                 "Failed to read msg from AdminQ, aq_err: %u",
5856                                 hw->aq.asq_last_status);
5857                         break;
5858                 }
5859                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5860
5861                 switch (opcode) {
5862                 case i40e_aqc_opc_send_msg_to_pf:
5863                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5864                         i40e_pf_host_handle_vf_msg(dev,
5865                                         rte_le_to_cpu_16(info.desc.retval),
5866                                         rte_le_to_cpu_32(info.desc.cookie_high),
5867                                         rte_le_to_cpu_32(info.desc.cookie_low),
5868                                         info.msg_buf,
5869                                         info.msg_len);
5870                         break;
5871                 case i40e_aqc_opc_get_link_status:
5872                         ret = i40e_dev_link_update(dev, 0);
5873                         if (!ret)
5874                                 _rte_eth_dev_callback_process(dev,
5875                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5876                         break;
5877                 default:
5878                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5879                                     opcode);
5880                         break;
5881                 }
5882         }
5883         rte_free(info.msg_buf);
5884 }
5885
5886 /**
5887  * Interrupt handler triggered by NIC  for handling
5888  * specific interrupt.
5889  *
5890  * @param handle
5891  *  Pointer to interrupt handle.
5892  * @param param
5893  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5894  *
5895  * @return
5896  *  void
5897  */
5898 static void
5899 i40e_dev_interrupt_handler(void *param)
5900 {
5901         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5903         uint32_t icr0;
5904
5905         /* Disable interrupt */
5906         i40e_pf_disable_irq0(hw);
5907
5908         /* read out interrupt causes */
5909         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5910
5911         /* No interrupt event indicated */
5912         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5913                 PMD_DRV_LOG(INFO, "No interrupt event");
5914                 goto done;
5915         }
5916         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5917                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5918         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5919                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5920         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5921                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5922         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5923                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5924         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5925                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5926         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5927                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5928         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5929                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5930
5931         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5932                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5933                 i40e_dev_handle_vfr_event(dev);
5934         }
5935         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5936                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5937                 i40e_dev_handle_aq_msg(dev);
5938         }
5939
5940 done:
5941         /* Enable interrupt */
5942         i40e_pf_enable_irq0(hw);
5943         rte_intr_enable(dev->intr_handle);
5944 }
5945
5946 int
5947 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5948                          struct i40e_macvlan_filter *filter,
5949                          int total)
5950 {
5951         int ele_num, ele_buff_size;
5952         int num, actual_num, i;
5953         uint16_t flags;
5954         int ret = I40E_SUCCESS;
5955         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5956         struct i40e_aqc_add_macvlan_element_data *req_list;
5957
5958         if (filter == NULL  || total == 0)
5959                 return I40E_ERR_PARAM;
5960         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5961         ele_buff_size = hw->aq.asq_buf_size;
5962
5963         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5964         if (req_list == NULL) {
5965                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5966                 return I40E_ERR_NO_MEMORY;
5967         }
5968
5969         num = 0;
5970         do {
5971                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5972                 memset(req_list, 0, ele_buff_size);
5973
5974                 for (i = 0; i < actual_num; i++) {
5975                         (void)rte_memcpy(req_list[i].mac_addr,
5976                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5977                         req_list[i].vlan_tag =
5978                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5979
5980                         switch (filter[num + i].filter_type) {
5981                         case RTE_MAC_PERFECT_MATCH:
5982                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5983                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5984                                 break;
5985                         case RTE_MACVLAN_PERFECT_MATCH:
5986                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5987                                 break;
5988                         case RTE_MAC_HASH_MATCH:
5989                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5990                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5991                                 break;
5992                         case RTE_MACVLAN_HASH_MATCH:
5993                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5994                                 break;
5995                         default:
5996                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5997                                 ret = I40E_ERR_PARAM;
5998                                 goto DONE;
5999                         }
6000
6001                         req_list[i].queue_number = 0;
6002
6003                         req_list[i].flags = rte_cpu_to_le_16(flags);
6004                 }
6005
6006                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6007                                                 actual_num, NULL);
6008                 if (ret != I40E_SUCCESS) {
6009                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6010                         goto DONE;
6011                 }
6012                 num += actual_num;
6013         } while (num < total);
6014
6015 DONE:
6016         rte_free(req_list);
6017         return ret;
6018 }
6019
6020 int
6021 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6022                             struct i40e_macvlan_filter *filter,
6023                             int total)
6024 {
6025         int ele_num, ele_buff_size;
6026         int num, actual_num, i;
6027         uint16_t flags;
6028         int ret = I40E_SUCCESS;
6029         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6030         struct i40e_aqc_remove_macvlan_element_data *req_list;
6031
6032         if (filter == NULL  || total == 0)
6033                 return I40E_ERR_PARAM;
6034
6035         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6036         ele_buff_size = hw->aq.asq_buf_size;
6037
6038         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6039         if (req_list == NULL) {
6040                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6041                 return I40E_ERR_NO_MEMORY;
6042         }
6043
6044         num = 0;
6045         do {
6046                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6047                 memset(req_list, 0, ele_buff_size);
6048
6049                 for (i = 0; i < actual_num; i++) {
6050                         (void)rte_memcpy(req_list[i].mac_addr,
6051                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6052                         req_list[i].vlan_tag =
6053                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6054
6055                         switch (filter[num + i].filter_type) {
6056                         case RTE_MAC_PERFECT_MATCH:
6057                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6058                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6059                                 break;
6060                         case RTE_MACVLAN_PERFECT_MATCH:
6061                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6062                                 break;
6063                         case RTE_MAC_HASH_MATCH:
6064                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6065                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6066                                 break;
6067                         case RTE_MACVLAN_HASH_MATCH:
6068                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6069                                 break;
6070                         default:
6071                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6072                                 ret = I40E_ERR_PARAM;
6073                                 goto DONE;
6074                         }
6075                         req_list[i].flags = rte_cpu_to_le_16(flags);
6076                 }
6077
6078                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6079                                                 actual_num, NULL);
6080                 if (ret != I40E_SUCCESS) {
6081                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6082                         goto DONE;
6083                 }
6084                 num += actual_num;
6085         } while (num < total);
6086
6087 DONE:
6088         rte_free(req_list);
6089         return ret;
6090 }
6091
6092 /* Find out specific MAC filter */
6093 static struct i40e_mac_filter *
6094 i40e_find_mac_filter(struct i40e_vsi *vsi,
6095                          struct ether_addr *macaddr)
6096 {
6097         struct i40e_mac_filter *f;
6098
6099         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6100                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6101                         return f;
6102         }
6103
6104         return NULL;
6105 }
6106
6107 static bool
6108 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6109                          uint16_t vlan_id)
6110 {
6111         uint32_t vid_idx, vid_bit;
6112
6113         if (vlan_id > ETH_VLAN_ID_MAX)
6114                 return 0;
6115
6116         vid_idx = I40E_VFTA_IDX(vlan_id);
6117         vid_bit = I40E_VFTA_BIT(vlan_id);
6118
6119         if (vsi->vfta[vid_idx] & vid_bit)
6120                 return 1;
6121         else
6122                 return 0;
6123 }
6124
6125 static void
6126 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6127                        uint16_t vlan_id, bool on)
6128 {
6129         uint32_t vid_idx, vid_bit;
6130
6131         vid_idx = I40E_VFTA_IDX(vlan_id);
6132         vid_bit = I40E_VFTA_BIT(vlan_id);
6133
6134         if (on)
6135                 vsi->vfta[vid_idx] |= vid_bit;
6136         else
6137                 vsi->vfta[vid_idx] &= ~vid_bit;
6138 }
6139
6140 void
6141 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6142                      uint16_t vlan_id, bool on)
6143 {
6144         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6145         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6146         int ret;
6147
6148         if (vlan_id > ETH_VLAN_ID_MAX)
6149                 return;
6150
6151         i40e_store_vlan_filter(vsi, vlan_id, on);
6152
6153         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6154                 return;
6155
6156         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6157
6158         if (on) {
6159                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6160                                        &vlan_data, 1, NULL);
6161                 if (ret != I40E_SUCCESS)
6162                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6163         } else {
6164                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6165                                           &vlan_data, 1, NULL);
6166                 if (ret != I40E_SUCCESS)
6167                         PMD_DRV_LOG(ERR,
6168                                     "Failed to remove vlan filter");
6169         }
6170 }
6171
6172 /**
6173  * Find all vlan options for specific mac addr,
6174  * return with actual vlan found.
6175  */
6176 int
6177 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6178                            struct i40e_macvlan_filter *mv_f,
6179                            int num, struct ether_addr *addr)
6180 {
6181         int i;
6182         uint32_t j, k;
6183
6184         /**
6185          * Not to use i40e_find_vlan_filter to decrease the loop time,
6186          * although the code looks complex.
6187           */
6188         if (num < vsi->vlan_num)
6189                 return I40E_ERR_PARAM;
6190
6191         i = 0;
6192         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6193                 if (vsi->vfta[j]) {
6194                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6195                                 if (vsi->vfta[j] & (1 << k)) {
6196                                         if (i > num - 1) {
6197                                                 PMD_DRV_LOG(ERR,
6198                                                         "vlan number doesn't match");
6199                                                 return I40E_ERR_PARAM;
6200                                         }
6201                                         (void)rte_memcpy(&mv_f[i].macaddr,
6202                                                         addr, ETH_ADDR_LEN);
6203                                         mv_f[i].vlan_id =
6204                                                 j * I40E_UINT32_BIT_SIZE + k;
6205                                         i++;
6206                                 }
6207                         }
6208                 }
6209         }
6210         return I40E_SUCCESS;
6211 }
6212
6213 static inline int
6214 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6215                            struct i40e_macvlan_filter *mv_f,
6216                            int num,
6217                            uint16_t vlan)
6218 {
6219         int i = 0;
6220         struct i40e_mac_filter *f;
6221
6222         if (num < vsi->mac_num)
6223                 return I40E_ERR_PARAM;
6224
6225         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6226                 if (i > num - 1) {
6227                         PMD_DRV_LOG(ERR, "buffer number not match");
6228                         return I40E_ERR_PARAM;
6229                 }
6230                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6231                                 ETH_ADDR_LEN);
6232                 mv_f[i].vlan_id = vlan;
6233                 mv_f[i].filter_type = f->mac_info.filter_type;
6234                 i++;
6235         }
6236
6237         return I40E_SUCCESS;
6238 }
6239
6240 static int
6241 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6242 {
6243         int i, j, num;
6244         struct i40e_mac_filter *f;
6245         struct i40e_macvlan_filter *mv_f;
6246         int ret = I40E_SUCCESS;
6247
6248         if (vsi == NULL || vsi->mac_num == 0)
6249                 return I40E_ERR_PARAM;
6250
6251         /* Case that no vlan is set */
6252         if (vsi->vlan_num == 0)
6253                 num = vsi->mac_num;
6254         else
6255                 num = vsi->mac_num * vsi->vlan_num;
6256
6257         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6258         if (mv_f == NULL) {
6259                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6260                 return I40E_ERR_NO_MEMORY;
6261         }
6262
6263         i = 0;
6264         if (vsi->vlan_num == 0) {
6265                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6266                         (void)rte_memcpy(&mv_f[i].macaddr,
6267                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6268                         mv_f[i].filter_type = f->mac_info.filter_type;
6269                         mv_f[i].vlan_id = 0;
6270                         i++;
6271                 }
6272         } else {
6273                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6274                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6275                                         vsi->vlan_num, &f->mac_info.mac_addr);
6276                         if (ret != I40E_SUCCESS)
6277                                 goto DONE;
6278                         for (j = i; j < i + vsi->vlan_num; j++)
6279                                 mv_f[j].filter_type = f->mac_info.filter_type;
6280                         i += vsi->vlan_num;
6281                 }
6282         }
6283
6284         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6285 DONE:
6286         rte_free(mv_f);
6287
6288         return ret;
6289 }
6290
6291 int
6292 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6293 {
6294         struct i40e_macvlan_filter *mv_f;
6295         int mac_num;
6296         int ret = I40E_SUCCESS;
6297
6298         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6299                 return I40E_ERR_PARAM;
6300
6301         /* If it's already set, just return */
6302         if (i40e_find_vlan_filter(vsi,vlan))
6303                 return I40E_SUCCESS;
6304
6305         mac_num = vsi->mac_num;
6306
6307         if (mac_num == 0) {
6308                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6309                 return I40E_ERR_PARAM;
6310         }
6311
6312         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6313
6314         if (mv_f == NULL) {
6315                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6316                 return I40E_ERR_NO_MEMORY;
6317         }
6318
6319         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6320
6321         if (ret != I40E_SUCCESS)
6322                 goto DONE;
6323
6324         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6325
6326         if (ret != I40E_SUCCESS)
6327                 goto DONE;
6328
6329         i40e_set_vlan_filter(vsi, vlan, 1);
6330
6331         vsi->vlan_num++;
6332         ret = I40E_SUCCESS;
6333 DONE:
6334         rte_free(mv_f);
6335         return ret;
6336 }
6337
6338 int
6339 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6340 {
6341         struct i40e_macvlan_filter *mv_f;
6342         int mac_num;
6343         int ret = I40E_SUCCESS;
6344
6345         /**
6346          * Vlan 0 is the generic filter for untagged packets
6347          * and can't be removed.
6348          */
6349         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6350                 return I40E_ERR_PARAM;
6351
6352         /* If can't find it, just return */
6353         if (!i40e_find_vlan_filter(vsi, vlan))
6354                 return I40E_ERR_PARAM;
6355
6356         mac_num = vsi->mac_num;
6357
6358         if (mac_num == 0) {
6359                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6360                 return I40E_ERR_PARAM;
6361         }
6362
6363         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6364
6365         if (mv_f == NULL) {
6366                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6367                 return I40E_ERR_NO_MEMORY;
6368         }
6369
6370         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6371
6372         if (ret != I40E_SUCCESS)
6373                 goto DONE;
6374
6375         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6376
6377         if (ret != I40E_SUCCESS)
6378                 goto DONE;
6379
6380         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6381         if (vsi->vlan_num == 1) {
6382                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6383                 if (ret != I40E_SUCCESS)
6384                         goto DONE;
6385
6386                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6387                 if (ret != I40E_SUCCESS)
6388                         goto DONE;
6389         }
6390
6391         i40e_set_vlan_filter(vsi, vlan, 0);
6392
6393         vsi->vlan_num--;
6394         ret = I40E_SUCCESS;
6395 DONE:
6396         rte_free(mv_f);
6397         return ret;
6398 }
6399
6400 int
6401 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6402 {
6403         struct i40e_mac_filter *f;
6404         struct i40e_macvlan_filter *mv_f;
6405         int i, vlan_num = 0;
6406         int ret = I40E_SUCCESS;
6407
6408         /* If it's add and we've config it, return */
6409         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6410         if (f != NULL)
6411                 return I40E_SUCCESS;
6412         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6413                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6414
6415                 /**
6416                  * If vlan_num is 0, that's the first time to add mac,
6417                  * set mask for vlan_id 0.
6418                  */
6419                 if (vsi->vlan_num == 0) {
6420                         i40e_set_vlan_filter(vsi, 0, 1);
6421                         vsi->vlan_num = 1;
6422                 }
6423                 vlan_num = vsi->vlan_num;
6424         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6425                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6426                 vlan_num = 1;
6427
6428         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6429         if (mv_f == NULL) {
6430                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6431                 return I40E_ERR_NO_MEMORY;
6432         }
6433
6434         for (i = 0; i < vlan_num; i++) {
6435                 mv_f[i].filter_type = mac_filter->filter_type;
6436                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6437                                 ETH_ADDR_LEN);
6438         }
6439
6440         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6441                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6442                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6443                                         &mac_filter->mac_addr);
6444                 if (ret != I40E_SUCCESS)
6445                         goto DONE;
6446         }
6447
6448         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6449         if (ret != I40E_SUCCESS)
6450                 goto DONE;
6451
6452         /* Add the mac addr into mac list */
6453         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6454         if (f == NULL) {
6455                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6456                 ret = I40E_ERR_NO_MEMORY;
6457                 goto DONE;
6458         }
6459         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6460                         ETH_ADDR_LEN);
6461         f->mac_info.filter_type = mac_filter->filter_type;
6462         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6463         vsi->mac_num++;
6464
6465         ret = I40E_SUCCESS;
6466 DONE:
6467         rte_free(mv_f);
6468
6469         return ret;
6470 }
6471
6472 int
6473 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6474 {
6475         struct i40e_mac_filter *f;
6476         struct i40e_macvlan_filter *mv_f;
6477         int i, vlan_num;
6478         enum rte_mac_filter_type filter_type;
6479         int ret = I40E_SUCCESS;
6480
6481         /* Can't find it, return an error */
6482         f = i40e_find_mac_filter(vsi, addr);
6483         if (f == NULL)
6484                 return I40E_ERR_PARAM;
6485
6486         vlan_num = vsi->vlan_num;
6487         filter_type = f->mac_info.filter_type;
6488         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6489                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6490                 if (vlan_num == 0) {
6491                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6492                         return I40E_ERR_PARAM;
6493                 }
6494         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6495                         filter_type == RTE_MAC_HASH_MATCH)
6496                 vlan_num = 1;
6497
6498         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6499         if (mv_f == NULL) {
6500                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6501                 return I40E_ERR_NO_MEMORY;
6502         }
6503
6504         for (i = 0; i < vlan_num; i++) {
6505                 mv_f[i].filter_type = filter_type;
6506                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6507                                 ETH_ADDR_LEN);
6508         }
6509         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6510                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6511                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6512                 if (ret != I40E_SUCCESS)
6513                         goto DONE;
6514         }
6515
6516         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6517         if (ret != I40E_SUCCESS)
6518                 goto DONE;
6519
6520         /* Remove the mac addr into mac list */
6521         TAILQ_REMOVE(&vsi->mac_list, f, next);
6522         rte_free(f);
6523         vsi->mac_num--;
6524
6525         ret = I40E_SUCCESS;
6526 DONE:
6527         rte_free(mv_f);
6528         return ret;
6529 }
6530
6531 /* Configure hash enable flags for RSS */
6532 uint64_t
6533 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6534 {
6535         uint64_t hena = 0;
6536
6537         if (!flags)
6538                 return hena;
6539
6540         if (flags & ETH_RSS_FRAG_IPV4)
6541                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6542         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6543                 if (type == I40E_MAC_X722) {
6544                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6545                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6546                 } else
6547                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6548         }
6549         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6550                 if (type == I40E_MAC_X722) {
6551                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6552                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6553                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6554                 } else
6555                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6556         }
6557         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6558                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6559         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6560                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6561         if (flags & ETH_RSS_FRAG_IPV6)
6562                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6563         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6564                 if (type == I40E_MAC_X722) {
6565                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6566                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6567                 } else
6568                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6569         }
6570         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6571                 if (type == I40E_MAC_X722) {
6572                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6573                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6574                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6575                 } else
6576                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6577         }
6578         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6580         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6581                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6582         if (flags & ETH_RSS_L2_PAYLOAD)
6583                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6584
6585         return hena;
6586 }
6587
6588 /* Parse the hash enable flags */
6589 uint64_t
6590 i40e_parse_hena(uint64_t flags)
6591 {
6592         uint64_t rss_hf = 0;
6593
6594         if (!flags)
6595                 return rss_hf;
6596         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6597                 rss_hf |= ETH_RSS_FRAG_IPV4;
6598         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6599                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6600         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6601                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6602         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6603                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6604         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6605                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6607                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6608         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6609                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6611                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6612         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6613                 rss_hf |= ETH_RSS_FRAG_IPV6;
6614         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6615                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6617                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6619                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6620         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6621                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6623                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6624         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6625                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6626         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6627                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6628         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6629                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6630
6631         return rss_hf;
6632 }
6633
6634 /* Disable RSS */
6635 static void
6636 i40e_pf_disable_rss(struct i40e_pf *pf)
6637 {
6638         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6639         uint64_t hena;
6640
6641         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6642         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6643         if (hw->mac.type == I40E_MAC_X722)
6644                 hena &= ~I40E_RSS_HENA_ALL_X722;
6645         else
6646                 hena &= ~I40E_RSS_HENA_ALL;
6647         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6648         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6649         I40E_WRITE_FLUSH(hw);
6650 }
6651
6652 static int
6653 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6654 {
6655         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6656         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6657         int ret = 0;
6658
6659         if (!key || key_len == 0) {
6660                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6661                 return 0;
6662         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6663                 sizeof(uint32_t)) {
6664                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6665                 return -EINVAL;
6666         }
6667
6668         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6669                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6670                         (struct i40e_aqc_get_set_rss_key_data *)key;
6671
6672                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6673                 if (ret)
6674                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6675         } else {
6676                 uint32_t *hash_key = (uint32_t *)key;
6677                 uint16_t i;
6678
6679                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6680                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6681                 I40E_WRITE_FLUSH(hw);
6682         }
6683
6684         return ret;
6685 }
6686
6687 static int
6688 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6689 {
6690         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6691         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6692         int ret;
6693
6694         if (!key || !key_len)
6695                 return -EINVAL;
6696
6697         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6698                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6699                         (struct i40e_aqc_get_set_rss_key_data *)key);
6700                 if (ret) {
6701                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6702                         return ret;
6703                 }
6704         } else {
6705                 uint32_t *key_dw = (uint32_t *)key;
6706                 uint16_t i;
6707
6708                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6709                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6710         }
6711         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6712
6713         return 0;
6714 }
6715
6716 static int
6717 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6718 {
6719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6720         uint64_t rss_hf;
6721         uint64_t hena;
6722         int ret;
6723
6724         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6725                                rss_conf->rss_key_len);
6726         if (ret)
6727                 return ret;
6728
6729         rss_hf = rss_conf->rss_hf;
6730         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6731         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6732         if (hw->mac.type == I40E_MAC_X722)
6733                 hena &= ~I40E_RSS_HENA_ALL_X722;
6734         else
6735                 hena &= ~I40E_RSS_HENA_ALL;
6736         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6737         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6738         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6739         I40E_WRITE_FLUSH(hw);
6740
6741         return 0;
6742 }
6743
6744 static int
6745 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6746                          struct rte_eth_rss_conf *rss_conf)
6747 {
6748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6751         uint64_t hena;
6752
6753         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6754         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6755         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6756                  ? I40E_RSS_HENA_ALL_X722
6757                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6758                 if (rss_hf != 0) /* Enable RSS */
6759                         return -EINVAL;
6760                 return 0; /* Nothing to do */
6761         }
6762         /* RSS enabled */
6763         if (rss_hf == 0) /* Disable RSS */
6764                 return -EINVAL;
6765
6766         return i40e_hw_rss_hash_set(pf, rss_conf);
6767 }
6768
6769 static int
6770 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6771                            struct rte_eth_rss_conf *rss_conf)
6772 {
6773         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6774         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6775         uint64_t hena;
6776
6777         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6778                          &rss_conf->rss_key_len);
6779
6780         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6781         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6782         rss_conf->rss_hf = i40e_parse_hena(hena);
6783
6784         return 0;
6785 }
6786
6787 static int
6788 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6789 {
6790         switch (filter_type) {
6791         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6792                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6793                 break;
6794         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6795                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6796                 break;
6797         case RTE_TUNNEL_FILTER_IMAC_TENID:
6798                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6799                 break;
6800         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6801                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6802                 break;
6803         case ETH_TUNNEL_FILTER_IMAC:
6804                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6805                 break;
6806         case ETH_TUNNEL_FILTER_OIP:
6807                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6808                 break;
6809         case ETH_TUNNEL_FILTER_IIP:
6810                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6811                 break;
6812         default:
6813                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6814                 return -EINVAL;
6815         }
6816
6817         return 0;
6818 }
6819
6820 /* Convert tunnel filter structure */
6821 static int
6822 i40e_tunnel_filter_convert(
6823         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6824         struct i40e_tunnel_filter *tunnel_filter)
6825 {
6826         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6827                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6828         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6829                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6830         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6831         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6832              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6833             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6834                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6835         else
6836                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6837         tunnel_filter->input.flags = cld_filter->element.flags;
6838         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6839         tunnel_filter->queue = cld_filter->element.queue_number;
6840         rte_memcpy(tunnel_filter->input.general_fields,
6841                    cld_filter->general_fields,
6842                    sizeof(cld_filter->general_fields));
6843
6844         return 0;
6845 }
6846
6847 /* Check if there exists the tunnel filter */
6848 struct i40e_tunnel_filter *
6849 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6850                              const struct i40e_tunnel_filter_input *input)
6851 {
6852         int ret;
6853
6854         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6855         if (ret < 0)
6856                 return NULL;
6857
6858         return tunnel_rule->hash_map[ret];
6859 }
6860
6861 /* Add a tunnel filter into the SW list */
6862 static int
6863 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6864                              struct i40e_tunnel_filter *tunnel_filter)
6865 {
6866         struct i40e_tunnel_rule *rule = &pf->tunnel;
6867         int ret;
6868
6869         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6870         if (ret < 0) {
6871                 PMD_DRV_LOG(ERR,
6872                             "Failed to insert tunnel filter to hash table %d!",
6873                             ret);
6874                 return ret;
6875         }
6876         rule->hash_map[ret] = tunnel_filter;
6877
6878         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6879
6880         return 0;
6881 }
6882
6883 /* Delete a tunnel filter from the SW list */
6884 int
6885 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6886                           struct i40e_tunnel_filter_input *input)
6887 {
6888         struct i40e_tunnel_rule *rule = &pf->tunnel;
6889         struct i40e_tunnel_filter *tunnel_filter;
6890         int ret;
6891
6892         ret = rte_hash_del_key(rule->hash_table, input);
6893         if (ret < 0) {
6894                 PMD_DRV_LOG(ERR,
6895                             "Failed to delete tunnel filter to hash table %d!",
6896                             ret);
6897                 return ret;
6898         }
6899         tunnel_filter = rule->hash_map[ret];
6900         rule->hash_map[ret] = NULL;
6901
6902         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6903         rte_free(tunnel_filter);
6904
6905         return 0;
6906 }
6907
6908 int
6909 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6910                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6911                         uint8_t add)
6912 {
6913         uint16_t ip_type;
6914         uint32_t ipv4_addr;
6915         uint8_t i, tun_type = 0;
6916         /* internal varialbe to convert ipv6 byte order */
6917         uint32_t convert_ipv6[4];
6918         int val, ret = 0;
6919         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6920         struct i40e_vsi *vsi = pf->main_vsi;
6921         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6922         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6923         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6924         struct i40e_tunnel_filter *tunnel, *node;
6925         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6926
6927         cld_filter = rte_zmalloc("tunnel_filter",
6928                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6929         0);
6930
6931         if (NULL == cld_filter) {
6932                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6933                 return -ENOMEM;
6934         }
6935         pfilter = cld_filter;
6936
6937         ether_addr_copy(&tunnel_filter->outer_mac,
6938                         (struct ether_addr *)&pfilter->element.outer_mac);
6939         ether_addr_copy(&tunnel_filter->inner_mac,
6940                         (struct ether_addr *)&pfilter->element.inner_mac);
6941
6942         pfilter->element.inner_vlan =
6943                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6944         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6945                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6946                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6947                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6948                                 &rte_cpu_to_le_32(ipv4_addr),
6949                                 sizeof(pfilter->element.ipaddr.v4.data));
6950         } else {
6951                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6952                 for (i = 0; i < 4; i++) {
6953                         convert_ipv6[i] =
6954                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6955                 }
6956                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6957                            &convert_ipv6,
6958                            sizeof(pfilter->element.ipaddr.v6.data));
6959         }
6960
6961         /* check tunneled type */
6962         switch (tunnel_filter->tunnel_type) {
6963         case RTE_TUNNEL_TYPE_VXLAN:
6964                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6965                 break;
6966         case RTE_TUNNEL_TYPE_NVGRE:
6967                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6968                 break;
6969         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6970                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6971                 break;
6972         default:
6973                 /* Other tunnel types is not supported. */
6974                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6975                 rte_free(cld_filter);
6976                 return -EINVAL;
6977         }
6978
6979         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6980                                        &pfilter->element.flags);
6981         if (val < 0) {
6982                 rte_free(cld_filter);
6983                 return -EINVAL;
6984         }
6985
6986         pfilter->element.flags |= rte_cpu_to_le_16(
6987                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6988                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6989         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6990         pfilter->element.queue_number =
6991                 rte_cpu_to_le_16(tunnel_filter->queue_id);
6992
6993         /* Check if there is the filter in SW list */
6994         memset(&check_filter, 0, sizeof(check_filter));
6995         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6996         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6997         if (add && node) {
6998                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6999                 return -EINVAL;
7000         }
7001
7002         if (!add && !node) {
7003                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7004                 return -EINVAL;
7005         }
7006
7007         if (add) {
7008                 ret = i40e_aq_add_cloud_filters(hw,
7009                                         vsi->seid, &cld_filter->element, 1);
7010                 if (ret < 0) {
7011                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7012                         return -ENOTSUP;
7013                 }
7014                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7015                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7016                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7017         } else {
7018                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7019                                                    &cld_filter->element, 1);
7020                 if (ret < 0) {
7021                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7022                         return -ENOTSUP;
7023                 }
7024                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7025         }
7026
7027         rte_free(cld_filter);
7028         return ret;
7029 }
7030
7031 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7032 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7033 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7034 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7035 #define I40E_TR_GRE_KEY_MASK                    0x400
7036 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7037 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7038
7039 static enum
7040 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7041 {
7042         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7043         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7045         enum i40e_status_code status = I40E_SUCCESS;
7046
7047         memset(&filter_replace, 0,
7048                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7049         memset(&filter_replace_buf, 0,
7050                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7051
7052         /* create L1 filter */
7053         filter_replace.old_filter_type =
7054                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7055         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7056         filter_replace.tr_bit = 0;
7057
7058         /* Prepare the buffer, 3 entries */
7059         filter_replace_buf.data[0] =
7060                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7061         filter_replace_buf.data[0] |=
7062                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7063         filter_replace_buf.data[2] = 0xFF;
7064         filter_replace_buf.data[3] = 0xFF;
7065         filter_replace_buf.data[4] =
7066                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7067         filter_replace_buf.data[4] |=
7068                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7069         filter_replace_buf.data[7] = 0xF0;
7070         filter_replace_buf.data[8]
7071                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7072         filter_replace_buf.data[8] |=
7073                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7074         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7075                 I40E_TR_GENEVE_KEY_MASK |
7076                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7077         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7078                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7079                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7080
7081         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7082                                                &filter_replace_buf);
7083         return status;
7084 }
7085
7086 static enum
7087 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7088 {
7089         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7090         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7091         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7092         enum i40e_status_code status = I40E_SUCCESS;
7093
7094         /* For MPLSoUDP */
7095         memset(&filter_replace, 0,
7096                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7097         memset(&filter_replace_buf, 0,
7098                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7099         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7100                 I40E_AQC_MIRROR_CLOUD_FILTER;
7101         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7102         filter_replace.new_filter_type =
7103                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7104         /* Prepare the buffer, 2 entries */
7105         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7106         filter_replace_buf.data[0] |=
7107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7108         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7109         filter_replace_buf.data[4] |=
7110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7111         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7112                                                &filter_replace_buf);
7113         if (status < 0)
7114                 return status;
7115
7116         /* For MPLSoGRE */
7117         memset(&filter_replace, 0,
7118                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7119         memset(&filter_replace_buf, 0,
7120                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7121
7122         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7123                 I40E_AQC_MIRROR_CLOUD_FILTER;
7124         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7125         filter_replace.new_filter_type =
7126                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7127         /* Prepare the buffer, 2 entries */
7128         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7129         filter_replace_buf.data[0] |=
7130                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7131         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7132         filter_replace_buf.data[4] |=
7133                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7134
7135         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7136                                                &filter_replace_buf);
7137         return status;
7138 }
7139
7140 int
7141 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7142                       struct i40e_tunnel_filter_conf *tunnel_filter,
7143                       uint8_t add)
7144 {
7145         uint16_t ip_type;
7146         uint32_t ipv4_addr;
7147         uint8_t i, tun_type = 0;
7148         /* internal variable to convert ipv6 byte order */
7149         uint32_t convert_ipv6[4];
7150         int val, ret = 0;
7151         struct i40e_pf_vf *vf = NULL;
7152         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7153         struct i40e_vsi *vsi;
7154         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7155         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7156         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7157         struct i40e_tunnel_filter *tunnel, *node;
7158         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7159         uint32_t teid_le;
7160         bool big_buffer = 0;
7161
7162         cld_filter = rte_zmalloc("tunnel_filter",
7163                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7164                          0);
7165
7166         if (cld_filter == NULL) {
7167                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7168                 return -ENOMEM;
7169         }
7170         pfilter = cld_filter;
7171
7172         ether_addr_copy(&tunnel_filter->outer_mac,
7173                         (struct ether_addr *)&pfilter->element.outer_mac);
7174         ether_addr_copy(&tunnel_filter->inner_mac,
7175                         (struct ether_addr *)&pfilter->element.inner_mac);
7176
7177         pfilter->element.inner_vlan =
7178                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7179         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7180                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7181                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7182                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7183                                 &rte_cpu_to_le_32(ipv4_addr),
7184                                 sizeof(pfilter->element.ipaddr.v4.data));
7185         } else {
7186                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7187                 for (i = 0; i < 4; i++) {
7188                         convert_ipv6[i] =
7189                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7190                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7191                 }
7192                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7193                            &convert_ipv6,
7194                            sizeof(pfilter->element.ipaddr.v6.data));
7195         }
7196
7197         /* check tunneled type */
7198         switch (tunnel_filter->tunnel_type) {
7199         case I40E_TUNNEL_TYPE_VXLAN:
7200                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7201                 break;
7202         case I40E_TUNNEL_TYPE_NVGRE:
7203                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7204                 break;
7205         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7206                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7207                 break;
7208         case I40E_TUNNEL_TYPE_MPLSoUDP:
7209                 if (!pf->mpls_replace_flag) {
7210                         i40e_replace_mpls_l1_filter(pf);
7211                         i40e_replace_mpls_cloud_filter(pf);
7212                         pf->mpls_replace_flag = 1;
7213                 }
7214                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7215                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7216                         teid_le >> 4;
7217                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7218                         (teid_le & 0xF) << 12;
7219                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7220                         0x40;
7221                 big_buffer = 1;
7222                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7223                 break;
7224         case I40E_TUNNEL_TYPE_MPLSoGRE:
7225                 if (!pf->mpls_replace_flag) {
7226                         i40e_replace_mpls_l1_filter(pf);
7227                         i40e_replace_mpls_cloud_filter(pf);
7228                         pf->mpls_replace_flag = 1;
7229                 }
7230                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7231                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7232                         teid_le >> 4;
7233                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7234                         (teid_le & 0xF) << 12;
7235                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7236                         0x0;
7237                 big_buffer = 1;
7238                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7239                 break;
7240         case I40E_TUNNEL_TYPE_QINQ:
7241                 if (!pf->qinq_replace_flag) {
7242                         ret = i40e_cloud_filter_qinq_create(pf);
7243                         if (ret < 0)
7244                                 PMD_DRV_LOG(DEBUG,
7245                                             "QinQ tunnel filter already created.");
7246                         pf->qinq_replace_flag = 1;
7247                 }
7248                 /*      Add in the General fields the values of
7249                  *      the Outer and Inner VLAN
7250                  *      Big Buffer should be set, see changes in
7251                  *      i40e_aq_add_cloud_filters
7252                  */
7253                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7254                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7255                 big_buffer = 1;
7256                 break;
7257         default:
7258                 /* Other tunnel types is not supported. */
7259                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7260                 rte_free(cld_filter);
7261                 return -EINVAL;
7262         }
7263
7264         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7265                 pfilter->element.flags =
7266                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7267         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7268                 pfilter->element.flags =
7269                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7270         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7271                 pfilter->element.flags |=
7272                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7273         else {
7274                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7275                                                 &pfilter->element.flags);
7276                 if (val < 0) {
7277                         rte_free(cld_filter);
7278                         return -EINVAL;
7279                 }
7280         }
7281
7282         pfilter->element.flags |= rte_cpu_to_le_16(
7283                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7284                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7285         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7286         pfilter->element.queue_number =
7287                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7288
7289         if (!tunnel_filter->is_to_vf)
7290                 vsi = pf->main_vsi;
7291         else {
7292                 if (tunnel_filter->vf_id >= pf->vf_num) {
7293                         PMD_DRV_LOG(ERR, "Invalid argument.");
7294                         return -EINVAL;
7295                 }
7296                 vf = &pf->vfs[tunnel_filter->vf_id];
7297                 vsi = vf->vsi;
7298         }
7299
7300         /* Check if there is the filter in SW list */
7301         memset(&check_filter, 0, sizeof(check_filter));
7302         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7303         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7304         check_filter.vf_id = tunnel_filter->vf_id;
7305         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7306         if (add && node) {
7307                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7308                 return -EINVAL;
7309         }
7310
7311         if (!add && !node) {
7312                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7313                 return -EINVAL;
7314         }
7315
7316         if (add) {
7317                 if (big_buffer)
7318                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7319                                                    vsi->seid, cld_filter, 1);
7320                 else
7321                         ret = i40e_aq_add_cloud_filters(hw,
7322                                         vsi->seid, &cld_filter->element, 1);
7323                 if (ret < 0) {
7324                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7325                         return -ENOTSUP;
7326                 }
7327                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7328                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7329                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7330         } else {
7331                 if (big_buffer)
7332                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7333                                 hw, vsi->seid, cld_filter, 1);
7334                 else
7335                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7336                                                    &cld_filter->element, 1);
7337                 if (ret < 0) {
7338                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7339                         return -ENOTSUP;
7340                 }
7341                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7342         }
7343
7344         rte_free(cld_filter);
7345         return ret;
7346 }
7347
7348 static int
7349 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7350 {
7351         uint8_t i;
7352
7353         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7354                 if (pf->vxlan_ports[i] == port)
7355                         return i;
7356         }
7357
7358         return -1;
7359 }
7360
7361 static int
7362 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7363 {
7364         int  idx, ret;
7365         uint8_t filter_idx;
7366         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7367
7368         idx = i40e_get_vxlan_port_idx(pf, port);
7369
7370         /* Check if port already exists */
7371         if (idx >= 0) {
7372                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7373                 return -EINVAL;
7374         }
7375
7376         /* Now check if there is space to add the new port */
7377         idx = i40e_get_vxlan_port_idx(pf, 0);
7378         if (idx < 0) {
7379                 PMD_DRV_LOG(ERR,
7380                         "Maximum number of UDP ports reached, not adding port %d",
7381                         port);
7382                 return -ENOSPC;
7383         }
7384
7385         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7386                                         &filter_idx, NULL);
7387         if (ret < 0) {
7388                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7389                 return -1;
7390         }
7391
7392         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7393                          port,  filter_idx);
7394
7395         /* New port: add it and mark its index in the bitmap */
7396         pf->vxlan_ports[idx] = port;
7397         pf->vxlan_bitmap |= (1 << idx);
7398
7399         if (!(pf->flags & I40E_FLAG_VXLAN))
7400                 pf->flags |= I40E_FLAG_VXLAN;
7401
7402         return 0;
7403 }
7404
7405 static int
7406 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7407 {
7408         int idx;
7409         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7410
7411         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7412                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7413                 return -EINVAL;
7414         }
7415
7416         idx = i40e_get_vxlan_port_idx(pf, port);
7417
7418         if (idx < 0) {
7419                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7420                 return -EINVAL;
7421         }
7422
7423         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7424                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7425                 return -1;
7426         }
7427
7428         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7429                         port, idx);
7430
7431         pf->vxlan_ports[idx] = 0;
7432         pf->vxlan_bitmap &= ~(1 << idx);
7433
7434         if (!pf->vxlan_bitmap)
7435                 pf->flags &= ~I40E_FLAG_VXLAN;
7436
7437         return 0;
7438 }
7439
7440 /* Add UDP tunneling port */
7441 static int
7442 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7443                              struct rte_eth_udp_tunnel *udp_tunnel)
7444 {
7445         int ret = 0;
7446         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7447
7448         if (udp_tunnel == NULL)
7449                 return -EINVAL;
7450
7451         switch (udp_tunnel->prot_type) {
7452         case RTE_TUNNEL_TYPE_VXLAN:
7453                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7454                 break;
7455
7456         case RTE_TUNNEL_TYPE_GENEVE:
7457         case RTE_TUNNEL_TYPE_TEREDO:
7458                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7459                 ret = -1;
7460                 break;
7461
7462         default:
7463                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7464                 ret = -1;
7465                 break;
7466         }
7467
7468         return ret;
7469 }
7470
7471 /* Remove UDP tunneling port */
7472 static int
7473 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7474                              struct rte_eth_udp_tunnel *udp_tunnel)
7475 {
7476         int ret = 0;
7477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7478
7479         if (udp_tunnel == NULL)
7480                 return -EINVAL;
7481
7482         switch (udp_tunnel->prot_type) {
7483         case RTE_TUNNEL_TYPE_VXLAN:
7484                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7485                 break;
7486         case RTE_TUNNEL_TYPE_GENEVE:
7487         case RTE_TUNNEL_TYPE_TEREDO:
7488                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7489                 ret = -1;
7490                 break;
7491         default:
7492                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7493                 ret = -1;
7494                 break;
7495         }
7496
7497         return ret;
7498 }
7499
7500 /* Calculate the maximum number of contiguous PF queues that are configured */
7501 static int
7502 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7503 {
7504         struct rte_eth_dev_data *data = pf->dev_data;
7505         int i, num;
7506         struct i40e_rx_queue *rxq;
7507
7508         num = 0;
7509         for (i = 0; i < pf->lan_nb_qps; i++) {
7510                 rxq = data->rx_queues[i];
7511                 if (rxq && rxq->q_set)
7512                         num++;
7513                 else
7514                         break;
7515         }
7516
7517         return num;
7518 }
7519
7520 /* Configure RSS */
7521 static int
7522 i40e_pf_config_rss(struct i40e_pf *pf)
7523 {
7524         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7525         struct rte_eth_rss_conf rss_conf;
7526         uint32_t i, lut = 0;
7527         uint16_t j, num;
7528
7529         /*
7530          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7531          * It's necessary to calculate the actual PF queues that are configured.
7532          */
7533         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7534                 num = i40e_pf_calc_configured_queues_num(pf);
7535         else
7536                 num = pf->dev_data->nb_rx_queues;
7537
7538         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7539         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7540                         num);
7541
7542         if (num == 0) {
7543                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7544                 return -ENOTSUP;
7545         }
7546
7547         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7548                 if (j == num)
7549                         j = 0;
7550                 lut = (lut << 8) | (j & ((0x1 <<
7551                         hw->func_caps.rss_table_entry_width) - 1));
7552                 if ((i & 3) == 3)
7553                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7554         }
7555
7556         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7557         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7558                 i40e_pf_disable_rss(pf);
7559                 return 0;
7560         }
7561         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7562                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7563                 /* Random default keys */
7564                 static uint32_t rss_key_default[] = {0x6b793944,
7565                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7566                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7567                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7568
7569                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7570                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7571                                                         sizeof(uint32_t);
7572         }
7573
7574         return i40e_hw_rss_hash_set(pf, &rss_conf);
7575 }
7576
7577 static int
7578 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7579                                struct rte_eth_tunnel_filter_conf *filter)
7580 {
7581         if (pf == NULL || filter == NULL) {
7582                 PMD_DRV_LOG(ERR, "Invalid parameter");
7583                 return -EINVAL;
7584         }
7585
7586         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7587                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7588                 return -EINVAL;
7589         }
7590
7591         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7592                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7593                 return -EINVAL;
7594         }
7595
7596         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7597                 (is_zero_ether_addr(&filter->outer_mac))) {
7598                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7599                 return -EINVAL;
7600         }
7601
7602         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7603                 (is_zero_ether_addr(&filter->inner_mac))) {
7604                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7605                 return -EINVAL;
7606         }
7607
7608         return 0;
7609 }
7610
7611 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7612 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7613 static int
7614 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7615 {
7616         uint32_t val, reg;
7617         int ret = -EINVAL;
7618
7619         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7620         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7621
7622         if (len == 3) {
7623                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7624         } else if (len == 4) {
7625                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7626         } else {
7627                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7628                 return ret;
7629         }
7630
7631         if (reg != val) {
7632                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7633                                                    reg, NULL);
7634                 if (ret != 0)
7635                         return ret;
7636         } else {
7637                 ret = 0;
7638         }
7639         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7640                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7641
7642         return ret;
7643 }
7644
7645 static int
7646 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7647 {
7648         int ret = -EINVAL;
7649
7650         if (!hw || !cfg)
7651                 return -EINVAL;
7652
7653         switch (cfg->cfg_type) {
7654         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7655                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7656                 break;
7657         default:
7658                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7659                 break;
7660         }
7661
7662         return ret;
7663 }
7664
7665 static int
7666 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7667                                enum rte_filter_op filter_op,
7668                                void *arg)
7669 {
7670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7671         int ret = I40E_ERR_PARAM;
7672
7673         switch (filter_op) {
7674         case RTE_ETH_FILTER_SET:
7675                 ret = i40e_dev_global_config_set(hw,
7676                         (struct rte_eth_global_cfg *)arg);
7677                 break;
7678         default:
7679                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7680                 break;
7681         }
7682
7683         return ret;
7684 }
7685
7686 static int
7687 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7688                           enum rte_filter_op filter_op,
7689                           void *arg)
7690 {
7691         struct rte_eth_tunnel_filter_conf *filter;
7692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7693         int ret = I40E_SUCCESS;
7694
7695         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7696
7697         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7698                 return I40E_ERR_PARAM;
7699
7700         switch (filter_op) {
7701         case RTE_ETH_FILTER_NOP:
7702                 if (!(pf->flags & I40E_FLAG_VXLAN))
7703                         ret = I40E_NOT_SUPPORTED;
7704                 break;
7705         case RTE_ETH_FILTER_ADD:
7706                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7707                 break;
7708         case RTE_ETH_FILTER_DELETE:
7709                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7710                 break;
7711         default:
7712                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7713                 ret = I40E_ERR_PARAM;
7714                 break;
7715         }
7716
7717         return ret;
7718 }
7719
7720 static int
7721 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7722 {
7723         int ret = 0;
7724         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7725
7726         /* RSS setup */
7727         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7728                 ret = i40e_pf_config_rss(pf);
7729         else
7730                 i40e_pf_disable_rss(pf);
7731
7732         return ret;
7733 }
7734
7735 /* Get the symmetric hash enable configurations per port */
7736 static void
7737 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7738 {
7739         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7740
7741         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7742 }
7743
7744 /* Set the symmetric hash enable configurations per port */
7745 static void
7746 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7747 {
7748         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7749
7750         if (enable > 0) {
7751                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7752                         PMD_DRV_LOG(INFO,
7753                                 "Symmetric hash has already been enabled");
7754                         return;
7755                 }
7756                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7757         } else {
7758                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7759                         PMD_DRV_LOG(INFO,
7760                                 "Symmetric hash has already been disabled");
7761                         return;
7762                 }
7763                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7764         }
7765         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7766         I40E_WRITE_FLUSH(hw);
7767 }
7768
7769 /*
7770  * Get global configurations of hash function type and symmetric hash enable
7771  * per flow type (pctype). Note that global configuration means it affects all
7772  * the ports on the same NIC.
7773  */
7774 static int
7775 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7776                                    struct rte_eth_hash_global_conf *g_cfg)
7777 {
7778         uint32_t reg, mask = I40E_FLOW_TYPES;
7779         uint16_t i;
7780         enum i40e_filter_pctype pctype;
7781
7782         memset(g_cfg, 0, sizeof(*g_cfg));
7783         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7784         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7785                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7786         else
7787                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7788         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7789                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7790
7791         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7792                 if (!(mask & (1UL << i)))
7793                         continue;
7794                 mask &= ~(1UL << i);
7795                 /* Bit set indicats the coresponding flow type is supported */
7796                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7797                 /* if flowtype is invalid, continue */
7798                 if (!I40E_VALID_FLOW(i))
7799                         continue;
7800                 pctype = i40e_flowtype_to_pctype(i);
7801                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7802                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7803                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7804         }
7805
7806         return 0;
7807 }
7808
7809 static int
7810 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7811 {
7812         uint32_t i;
7813         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7814
7815         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7816                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7817                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7818                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7819                                                 g_cfg->hash_func);
7820                 return -EINVAL;
7821         }
7822
7823         /*
7824          * As i40e supports less than 32 flow types, only first 32 bits need to
7825          * be checked.
7826          */
7827         mask0 = g_cfg->valid_bit_mask[0];
7828         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7829                 if (i == 0) {
7830                         /* Check if any unsupported flow type configured */
7831                         if ((mask0 | i40e_mask) ^ i40e_mask)
7832                                 goto mask_err;
7833                 } else {
7834                         if (g_cfg->valid_bit_mask[i])
7835                                 goto mask_err;
7836                 }
7837         }
7838
7839         return 0;
7840
7841 mask_err:
7842         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7843
7844         return -EINVAL;
7845 }
7846
7847 /*
7848  * Set global configurations of hash function type and symmetric hash enable
7849  * per flow type (pctype). Note any modifying global configuration will affect
7850  * all the ports on the same NIC.
7851  */
7852 static int
7853 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7854                                    struct rte_eth_hash_global_conf *g_cfg)
7855 {
7856         int ret;
7857         uint16_t i;
7858         uint32_t reg;
7859         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7860         enum i40e_filter_pctype pctype;
7861
7862         /* Check the input parameters */
7863         ret = i40e_hash_global_config_check(g_cfg);
7864         if (ret < 0)
7865                 return ret;
7866
7867         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7868                 if (!(mask0 & (1UL << i)))
7869                         continue;
7870                 mask0 &= ~(1UL << i);
7871                 /* if flowtype is invalid, continue */
7872                 if (!I40E_VALID_FLOW(i))
7873                         continue;
7874                 pctype = i40e_flowtype_to_pctype(i);
7875                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7876                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7877                 if (hw->mac.type == I40E_MAC_X722) {
7878                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7879                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7880                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7881                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7882                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7883                                   reg);
7884                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7885                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7886                                   reg);
7887                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7888                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7889                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7890                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7891                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7892                                   reg);
7893                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7894                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7895                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7896                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7897                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7898                                   reg);
7899                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7900                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7901                                   reg);
7902                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7903                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7904                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7905                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7906                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7907                                   reg);
7908                         } else {
7909                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7910                                   reg);
7911                         }
7912                 } else {
7913                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7914                 }
7915         }
7916
7917         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7918         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7919                 /* Toeplitz */
7920                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7921                         PMD_DRV_LOG(DEBUG,
7922                                 "Hash function already set to Toeplitz");
7923                         goto out;
7924                 }
7925                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7926         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7927                 /* Simple XOR */
7928                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7929                         PMD_DRV_LOG(DEBUG,
7930                                 "Hash function already set to Simple XOR");
7931                         goto out;
7932                 }
7933                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7934         } else
7935                 /* Use the default, and keep it as it is */
7936                 goto out;
7937
7938         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7939
7940 out:
7941         I40E_WRITE_FLUSH(hw);
7942
7943         return 0;
7944 }
7945
7946 /**
7947  * Valid input sets for hash and flow director filters per PCTYPE
7948  */
7949 static uint64_t
7950 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7951                 enum rte_filter_type filter)
7952 {
7953         uint64_t valid;
7954
7955         static const uint64_t valid_hash_inset_table[] = {
7956                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7957                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7958                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7959                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7960                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7961                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7962                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7963                         I40E_INSET_FLEX_PAYLOAD,
7964                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7965                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7966                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7967                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7968                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7969                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7970                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7971                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7972                         I40E_INSET_FLEX_PAYLOAD,
7973                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7974                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7975                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7976                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7977                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7978                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7979                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7980                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7981                         I40E_INSET_FLEX_PAYLOAD,
7982                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7983                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7984                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7985                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7986                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7987                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7988                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7989                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7990                         I40E_INSET_FLEX_PAYLOAD,
7991                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7992                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7993                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7994                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7995                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7996                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7997                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7998                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7999                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8000                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8001                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8002                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8003                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8004                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8005                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8006                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8007                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8008                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8009                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8010                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8011                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8012                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8013                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8014                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8015                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8016                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8017                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8018                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8019                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8020                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8022                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025                         I40E_INSET_FLEX_PAYLOAD,
8026                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8027                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8028                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8029                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8030                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8031                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8032                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8033                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8034                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8035                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8036                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8038                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8039                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8040                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8041                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8042                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8046                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8047                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8048                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8049                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8050                         I40E_INSET_FLEX_PAYLOAD,
8051                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8052                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8053                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8055                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8056                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8057                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8058                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8059                         I40E_INSET_FLEX_PAYLOAD,
8060                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8064                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8065                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8066                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8067                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8068                         I40E_INSET_FLEX_PAYLOAD,
8069                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8073                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8074                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8075                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8076                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8077                         I40E_INSET_FLEX_PAYLOAD,
8078                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8082                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8083                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8084                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8085                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8086                         I40E_INSET_FLEX_PAYLOAD,
8087                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8091                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8092                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8093                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8094                         I40E_INSET_FLEX_PAYLOAD,
8095                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8096                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8097                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8098                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8099                         I40E_INSET_FLEX_PAYLOAD,
8100         };
8101
8102         /**
8103          * Flow director supports only fields defined in
8104          * union rte_eth_fdir_flow.
8105          */
8106         static const uint64_t valid_fdir_inset_table[] = {
8107                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8108                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8109                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8110                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8111                 I40E_INSET_IPV4_TTL,
8112                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8113                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8114                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8115                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8116                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8117                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8118                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8119                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8120                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8121                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8122                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8123                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8124                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8125                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8126                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8127                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8128                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8130                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8131                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8132                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8134                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8135                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8136                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8137                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8138                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8139                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8141                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8142                 I40E_INSET_SCTP_VT,
8143                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8147                 I40E_INSET_IPV4_TTL,
8148                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8150                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8151                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8152                 I40E_INSET_IPV6_HOP_LIMIT,
8153                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8155                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8156                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8157                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8158                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8159                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8160                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8161                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8162                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8163                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8164                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8165                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8167                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8168                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8169                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8170                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8171                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8172                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8173                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8174                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8175                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8176                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8177                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8178                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8179                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8181                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8182                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8183                 I40E_INSET_SCTP_VT,
8184                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8185                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8186                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8187                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8188                 I40E_INSET_IPV6_HOP_LIMIT,
8189                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191                 I40E_INSET_LAST_ETHER_TYPE,
8192         };
8193
8194         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8195                 return 0;
8196         if (filter == RTE_ETH_FILTER_HASH)
8197                 valid = valid_hash_inset_table[pctype];
8198         else
8199                 valid = valid_fdir_inset_table[pctype];
8200
8201         return valid;
8202 }
8203
8204 /**
8205  * Validate if the input set is allowed for a specific PCTYPE
8206  */
8207 int
8208 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8209                 enum rte_filter_type filter, uint64_t inset)
8210 {
8211         uint64_t valid;
8212
8213         valid = i40e_get_valid_input_set(pctype, filter);
8214         if (inset & (~valid))
8215                 return -EINVAL;
8216
8217         return 0;
8218 }
8219
8220 /* default input set fields combination per pctype */
8221 uint64_t
8222 i40e_get_default_input_set(uint16_t pctype)
8223 {
8224         static const uint64_t default_inset_table[] = {
8225                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8226                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8227                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8228                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8229                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8230                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8231                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8232                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8233                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8234                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8235                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8236                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8237                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8240                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8241                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8242                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8243                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8244                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8245                         I40E_INSET_SCTP_VT,
8246                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8247                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8248                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8249                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8250                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8251                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8252                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8253                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8254                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8255                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8256                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8257                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8258                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8259                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8260                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8261                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8262                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8263                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8264                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8265                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8266                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8267                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8268                         I40E_INSET_SCTP_VT,
8269                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8270                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8271                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8272                         I40E_INSET_LAST_ETHER_TYPE,
8273         };
8274
8275         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8276                 return 0;
8277
8278         return default_inset_table[pctype];
8279 }
8280
8281 /**
8282  * Parse the input set from index to logical bit masks
8283  */
8284 static int
8285 i40e_parse_input_set(uint64_t *inset,
8286                      enum i40e_filter_pctype pctype,
8287                      enum rte_eth_input_set_field *field,
8288                      uint16_t size)
8289 {
8290         uint16_t i, j;
8291         int ret = -EINVAL;
8292
8293         static const struct {
8294                 enum rte_eth_input_set_field field;
8295                 uint64_t inset;
8296         } inset_convert_table[] = {
8297                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8298                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8299                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8300                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8301                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8302                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8303                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8304                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8305                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8306                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8307                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8308                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8309                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8310                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8311                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8312                         I40E_INSET_IPV6_NEXT_HDR},
8313                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8314                         I40E_INSET_IPV6_HOP_LIMIT},
8315                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8316                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8317                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8318                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8319                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8320                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8321                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8322                         I40E_INSET_SCTP_VT},
8323                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8324                         I40E_INSET_TUNNEL_DMAC},
8325                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8326                         I40E_INSET_VLAN_TUNNEL},
8327                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8328                         I40E_INSET_TUNNEL_ID},
8329                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8330                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8331                         I40E_INSET_FLEX_PAYLOAD_W1},
8332                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8333                         I40E_INSET_FLEX_PAYLOAD_W2},
8334                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8335                         I40E_INSET_FLEX_PAYLOAD_W3},
8336                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8337                         I40E_INSET_FLEX_PAYLOAD_W4},
8338                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8339                         I40E_INSET_FLEX_PAYLOAD_W5},
8340                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8341                         I40E_INSET_FLEX_PAYLOAD_W6},
8342                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8343                         I40E_INSET_FLEX_PAYLOAD_W7},
8344                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8345                         I40E_INSET_FLEX_PAYLOAD_W8},
8346         };
8347
8348         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8349                 return ret;
8350
8351         /* Only one item allowed for default or all */
8352         if (size == 1) {
8353                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8354                         *inset = i40e_get_default_input_set(pctype);
8355                         return 0;
8356                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8357                         *inset = I40E_INSET_NONE;
8358                         return 0;
8359                 }
8360         }
8361
8362         for (i = 0, *inset = 0; i < size; i++) {
8363                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8364                         if (field[i] == inset_convert_table[j].field) {
8365                                 *inset |= inset_convert_table[j].inset;
8366                                 break;
8367                         }
8368                 }
8369
8370                 /* It contains unsupported input set, return immediately */
8371                 if (j == RTE_DIM(inset_convert_table))
8372                         return ret;
8373         }
8374
8375         return 0;
8376 }
8377
8378 /**
8379  * Translate the input set from bit masks to register aware bit masks
8380  * and vice versa
8381  */
8382 uint64_t
8383 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8384 {
8385         uint64_t val = 0;
8386         uint16_t i;
8387
8388         struct inset_map {
8389                 uint64_t inset;
8390                 uint64_t inset_reg;
8391         };
8392
8393         static const struct inset_map inset_map_common[] = {
8394                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8395                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8396                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8397                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8398                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8399                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8400                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8401                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8402                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8403                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8404                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8405                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8406                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8407                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8408                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8409                 {I40E_INSET_TUNNEL_DMAC,
8410                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8411                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8412                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8413                 {I40E_INSET_TUNNEL_SRC_PORT,
8414                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8415                 {I40E_INSET_TUNNEL_DST_PORT,
8416                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8417                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8418                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8419                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8420                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8421                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8422                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8423                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8424                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8425                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8426         };
8427
8428     /* some different registers map in x722*/
8429         static const struct inset_map inset_map_diff_x722[] = {
8430                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8431                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8432                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8433                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8434         };
8435
8436         static const struct inset_map inset_map_diff_not_x722[] = {
8437                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8438                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8439                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8440                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8441         };
8442
8443         if (input == 0)
8444                 return val;
8445
8446         /* Translate input set to register aware inset */
8447         if (type == I40E_MAC_X722) {
8448                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8449                         if (input & inset_map_diff_x722[i].inset)
8450                                 val |= inset_map_diff_x722[i].inset_reg;
8451                 }
8452         } else {
8453                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8454                         if (input & inset_map_diff_not_x722[i].inset)
8455                                 val |= inset_map_diff_not_x722[i].inset_reg;
8456                 }
8457         }
8458
8459         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8460                 if (input & inset_map_common[i].inset)
8461                         val |= inset_map_common[i].inset_reg;
8462         }
8463
8464         return val;
8465 }
8466
8467 int
8468 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8469 {
8470         uint8_t i, idx = 0;
8471         uint64_t inset_need_mask = inset;
8472
8473         static const struct {
8474                 uint64_t inset;
8475                 uint32_t mask;
8476         } inset_mask_map[] = {
8477                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8478                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8479                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8480                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8481                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8482                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8483                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8484                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8485         };
8486
8487         if (!inset || !mask || !nb_elem)
8488                 return 0;
8489
8490         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8491                 /* Clear the inset bit, if no MASK is required,
8492                  * for example proto + ttl
8493                  */
8494                 if ((inset & inset_mask_map[i].inset) ==
8495                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8496                         inset_need_mask &= ~inset_mask_map[i].inset;
8497                 if (!inset_need_mask)
8498                         return 0;
8499         }
8500         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8501                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8502                     inset_mask_map[i].inset) {
8503                         if (idx >= nb_elem) {
8504                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8505                                 return -EINVAL;
8506                         }
8507                         mask[idx] = inset_mask_map[i].mask;
8508                         idx++;
8509                 }
8510         }
8511
8512         return idx;
8513 }
8514
8515 void
8516 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8517 {
8518         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8519
8520         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8521         if (reg != val)
8522                 i40e_write_rx_ctl(hw, addr, val);
8523         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8524                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8525 }
8526
8527 static void
8528 i40e_filter_input_set_init(struct i40e_pf *pf)
8529 {
8530         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8531         enum i40e_filter_pctype pctype;
8532         uint64_t input_set, inset_reg;
8533         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8534         int num, i;
8535
8536         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8537              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8538                 if (hw->mac.type == I40E_MAC_X722) {
8539                         if (!I40E_VALID_PCTYPE_X722(pctype))
8540                                 continue;
8541                 } else {
8542                         if (!I40E_VALID_PCTYPE(pctype))
8543                                 continue;
8544                 }
8545
8546                 input_set = i40e_get_default_input_set(pctype);
8547
8548                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8549                                                    I40E_INSET_MASK_NUM_REG);
8550                 if (num < 0)
8551                         return;
8552                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8553                                         input_set);
8554
8555                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8556                                       (uint32_t)(inset_reg & UINT32_MAX));
8557                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8558                                      (uint32_t)((inset_reg >>
8559                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8560                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8561                                       (uint32_t)(inset_reg & UINT32_MAX));
8562                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8563                                      (uint32_t)((inset_reg >>
8564                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8565
8566                 for (i = 0; i < num; i++) {
8567                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8568                                              mask_reg[i]);
8569                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8570                                              mask_reg[i]);
8571                 }
8572                 /*clear unused mask registers of the pctype */
8573                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8574                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8575                                              0);
8576                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8577                                              0);
8578                 }
8579                 I40E_WRITE_FLUSH(hw);
8580
8581                 /* store the default input set */
8582                 pf->hash_input_set[pctype] = input_set;
8583                 pf->fdir.input_set[pctype] = input_set;
8584         }
8585 }
8586
8587 int
8588 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8589                          struct rte_eth_input_set_conf *conf)
8590 {
8591         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8592         enum i40e_filter_pctype pctype;
8593         uint64_t input_set, inset_reg = 0;
8594         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8595         int ret, i, num;
8596
8597         if (!conf) {
8598                 PMD_DRV_LOG(ERR, "Invalid pointer");
8599                 return -EFAULT;
8600         }
8601         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8602             conf->op != RTE_ETH_INPUT_SET_ADD) {
8603                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8604                 return -EINVAL;
8605         }
8606
8607         if (!I40E_VALID_FLOW(conf->flow_type)) {
8608                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8609                 return -EINVAL;
8610         }
8611
8612         if (hw->mac.type == I40E_MAC_X722) {
8613                 /* get translated pctype value in fd pctype register */
8614                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8615                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8616                         conf->flow_type)));
8617         } else
8618                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8619
8620         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8621                                    conf->inset_size);
8622         if (ret) {
8623                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8624                 return -EINVAL;
8625         }
8626         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8627                                     input_set) != 0) {
8628                 PMD_DRV_LOG(ERR, "Invalid input set");
8629                 return -EINVAL;
8630         }
8631         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8632                 /* get inset value in register */
8633                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8634                 inset_reg <<= I40E_32_BIT_WIDTH;
8635                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8636                 input_set |= pf->hash_input_set[pctype];
8637         }
8638         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8639                                            I40E_INSET_MASK_NUM_REG);
8640         if (num < 0)
8641                 return -EINVAL;
8642
8643         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8644
8645         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8646                               (uint32_t)(inset_reg & UINT32_MAX));
8647         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8648                              (uint32_t)((inset_reg >>
8649                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8650
8651         for (i = 0; i < num; i++)
8652                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8653                                      mask_reg[i]);
8654         /*clear unused mask registers of the pctype */
8655         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8656                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8657                                      0);
8658         I40E_WRITE_FLUSH(hw);
8659
8660         pf->hash_input_set[pctype] = input_set;
8661         return 0;
8662 }
8663
8664 int
8665 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8666                          struct rte_eth_input_set_conf *conf)
8667 {
8668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8669         enum i40e_filter_pctype pctype;
8670         uint64_t input_set, inset_reg = 0;
8671         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8672         int ret, i, num;
8673
8674         if (!hw || !conf) {
8675                 PMD_DRV_LOG(ERR, "Invalid pointer");
8676                 return -EFAULT;
8677         }
8678         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8679             conf->op != RTE_ETH_INPUT_SET_ADD) {
8680                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8681                 return -EINVAL;
8682         }
8683
8684         if (!I40E_VALID_FLOW(conf->flow_type)) {
8685                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8686                 return -EINVAL;
8687         }
8688
8689         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8690
8691         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8692                                    conf->inset_size);
8693         if (ret) {
8694                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8695                 return -EINVAL;
8696         }
8697         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8698                                     input_set) != 0) {
8699                 PMD_DRV_LOG(ERR, "Invalid input set");
8700                 return -EINVAL;
8701         }
8702
8703         /* get inset value in register */
8704         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8705         inset_reg <<= I40E_32_BIT_WIDTH;
8706         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8707
8708         /* Can not change the inset reg for flex payload for fdir,
8709          * it is done by writing I40E_PRTQF_FD_FLXINSET
8710          * in i40e_set_flex_mask_on_pctype.
8711          */
8712         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8713                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8714         else
8715                 input_set |= pf->fdir.input_set[pctype];
8716         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8717                                            I40E_INSET_MASK_NUM_REG);
8718         if (num < 0)
8719                 return -EINVAL;
8720
8721         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8722
8723         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8724                               (uint32_t)(inset_reg & UINT32_MAX));
8725         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8726                              (uint32_t)((inset_reg >>
8727                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8728
8729         for (i = 0; i < num; i++)
8730                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8731                                      mask_reg[i]);
8732         /*clear unused mask registers of the pctype */
8733         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8734                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8735                                      0);
8736         I40E_WRITE_FLUSH(hw);
8737
8738         pf->fdir.input_set[pctype] = input_set;
8739         return 0;
8740 }
8741
8742 static int
8743 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8744 {
8745         int ret = 0;
8746
8747         if (!hw || !info) {
8748                 PMD_DRV_LOG(ERR, "Invalid pointer");
8749                 return -EFAULT;
8750         }
8751
8752         switch (info->info_type) {
8753         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8754                 i40e_get_symmetric_hash_enable_per_port(hw,
8755                                         &(info->info.enable));
8756                 break;
8757         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8758                 ret = i40e_get_hash_filter_global_config(hw,
8759                                 &(info->info.global_conf));
8760                 break;
8761         default:
8762                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8763                                                         info->info_type);
8764                 ret = -EINVAL;
8765                 break;
8766         }
8767
8768         return ret;
8769 }
8770
8771 static int
8772 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8773 {
8774         int ret = 0;
8775
8776         if (!hw || !info) {
8777                 PMD_DRV_LOG(ERR, "Invalid pointer");
8778                 return -EFAULT;
8779         }
8780
8781         switch (info->info_type) {
8782         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8783                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8784                 break;
8785         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8786                 ret = i40e_set_hash_filter_global_config(hw,
8787                                 &(info->info.global_conf));
8788                 break;
8789         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8790                 ret = i40e_hash_filter_inset_select(hw,
8791                                                &(info->info.input_set_conf));
8792                 break;
8793
8794         default:
8795                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8796                                                         info->info_type);
8797                 ret = -EINVAL;
8798                 break;
8799         }
8800
8801         return ret;
8802 }
8803
8804 /* Operations for hash function */
8805 static int
8806 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8807                       enum rte_filter_op filter_op,
8808                       void *arg)
8809 {
8810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8811         int ret = 0;
8812
8813         switch (filter_op) {
8814         case RTE_ETH_FILTER_NOP:
8815                 break;
8816         case RTE_ETH_FILTER_GET:
8817                 ret = i40e_hash_filter_get(hw,
8818                         (struct rte_eth_hash_filter_info *)arg);
8819                 break;
8820         case RTE_ETH_FILTER_SET:
8821                 ret = i40e_hash_filter_set(hw,
8822                         (struct rte_eth_hash_filter_info *)arg);
8823                 break;
8824         default:
8825                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8826                                                                 filter_op);
8827                 ret = -ENOTSUP;
8828                 break;
8829         }
8830
8831         return ret;
8832 }
8833
8834 /* Convert ethertype filter structure */
8835 static int
8836 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8837                               struct i40e_ethertype_filter *filter)
8838 {
8839         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8840         filter->input.ether_type = input->ether_type;
8841         filter->flags = input->flags;
8842         filter->queue = input->queue;
8843
8844         return 0;
8845 }
8846
8847 /* Check if there exists the ehtertype filter */
8848 struct i40e_ethertype_filter *
8849 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8850                                 const struct i40e_ethertype_filter_input *input)
8851 {
8852         int ret;
8853
8854         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8855         if (ret < 0)
8856                 return NULL;
8857
8858         return ethertype_rule->hash_map[ret];
8859 }
8860
8861 /* Add ethertype filter in SW list */
8862 static int
8863 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8864                                 struct i40e_ethertype_filter *filter)
8865 {
8866         struct i40e_ethertype_rule *rule = &pf->ethertype;
8867         int ret;
8868
8869         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8870         if (ret < 0) {
8871                 PMD_DRV_LOG(ERR,
8872                             "Failed to insert ethertype filter"
8873                             " to hash table %d!",
8874                             ret);
8875                 return ret;
8876         }
8877         rule->hash_map[ret] = filter;
8878
8879         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8880
8881         return 0;
8882 }
8883
8884 /* Delete ethertype filter in SW list */
8885 int
8886 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8887                              struct i40e_ethertype_filter_input *input)
8888 {
8889         struct i40e_ethertype_rule *rule = &pf->ethertype;
8890         struct i40e_ethertype_filter *filter;
8891         int ret;
8892
8893         ret = rte_hash_del_key(rule->hash_table, input);
8894         if (ret < 0) {
8895                 PMD_DRV_LOG(ERR,
8896                             "Failed to delete ethertype filter"
8897                             " to hash table %d!",
8898                             ret);
8899                 return ret;
8900         }
8901         filter = rule->hash_map[ret];
8902         rule->hash_map[ret] = NULL;
8903
8904         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8905         rte_free(filter);
8906
8907         return 0;
8908 }
8909
8910 /*
8911  * Configure ethertype filter, which can director packet by filtering
8912  * with mac address and ether_type or only ether_type
8913  */
8914 int
8915 i40e_ethertype_filter_set(struct i40e_pf *pf,
8916                         struct rte_eth_ethertype_filter *filter,
8917                         bool add)
8918 {
8919         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8920         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8921         struct i40e_ethertype_filter *ethertype_filter, *node;
8922         struct i40e_ethertype_filter check_filter;
8923         struct i40e_control_filter_stats stats;
8924         uint16_t flags = 0;
8925         int ret;
8926
8927         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8928                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8929                 return -EINVAL;
8930         }
8931         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8932                 filter->ether_type == ETHER_TYPE_IPv6) {
8933                 PMD_DRV_LOG(ERR,
8934                         "unsupported ether_type(0x%04x) in control packet filter.",
8935                         filter->ether_type);
8936                 return -EINVAL;
8937         }
8938         if (filter->ether_type == ETHER_TYPE_VLAN)
8939                 PMD_DRV_LOG(WARNING,
8940                         "filter vlan ether_type in first tag is not supported.");
8941
8942         /* Check if there is the filter in SW list */
8943         memset(&check_filter, 0, sizeof(check_filter));
8944         i40e_ethertype_filter_convert(filter, &check_filter);
8945         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8946                                                &check_filter.input);
8947         if (add && node) {
8948                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8949                 return -EINVAL;
8950         }
8951
8952         if (!add && !node) {
8953                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8954                 return -EINVAL;
8955         }
8956
8957         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8958                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8959         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8960                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8961         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8962
8963         memset(&stats, 0, sizeof(stats));
8964         ret = i40e_aq_add_rem_control_packet_filter(hw,
8965                         filter->mac_addr.addr_bytes,
8966                         filter->ether_type, flags,
8967                         pf->main_vsi->seid,
8968                         filter->queue, add, &stats, NULL);
8969
8970         PMD_DRV_LOG(INFO,
8971                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8972                 ret, stats.mac_etype_used, stats.etype_used,
8973                 stats.mac_etype_free, stats.etype_free);
8974         if (ret < 0)
8975                 return -ENOSYS;
8976
8977         /* Add or delete a filter in SW list */
8978         if (add) {
8979                 ethertype_filter = rte_zmalloc("ethertype_filter",
8980                                        sizeof(*ethertype_filter), 0);
8981                 rte_memcpy(ethertype_filter, &check_filter,
8982                            sizeof(check_filter));
8983                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8984         } else {
8985                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8986         }
8987
8988         return ret;
8989 }
8990
8991 /*
8992  * Handle operations for ethertype filter.
8993  */
8994 static int
8995 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8996                                 enum rte_filter_op filter_op,
8997                                 void *arg)
8998 {
8999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9000         int ret = 0;
9001
9002         if (filter_op == RTE_ETH_FILTER_NOP)
9003                 return ret;
9004
9005         if (arg == NULL) {
9006                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9007                             filter_op);
9008                 return -EINVAL;
9009         }
9010
9011         switch (filter_op) {
9012         case RTE_ETH_FILTER_ADD:
9013                 ret = i40e_ethertype_filter_set(pf,
9014                         (struct rte_eth_ethertype_filter *)arg,
9015                         TRUE);
9016                 break;
9017         case RTE_ETH_FILTER_DELETE:
9018                 ret = i40e_ethertype_filter_set(pf,
9019                         (struct rte_eth_ethertype_filter *)arg,
9020                         FALSE);
9021                 break;
9022         default:
9023                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9024                 ret = -ENOSYS;
9025                 break;
9026         }
9027         return ret;
9028 }
9029
9030 static int
9031 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9032                      enum rte_filter_type filter_type,
9033                      enum rte_filter_op filter_op,
9034                      void *arg)
9035 {
9036         int ret = 0;
9037
9038         if (dev == NULL)
9039                 return -EINVAL;
9040
9041         switch (filter_type) {
9042         case RTE_ETH_FILTER_NONE:
9043                 /* For global configuration */
9044                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9045                 break;
9046         case RTE_ETH_FILTER_HASH:
9047                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9048                 break;
9049         case RTE_ETH_FILTER_MACVLAN:
9050                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9051                 break;
9052         case RTE_ETH_FILTER_ETHERTYPE:
9053                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9054                 break;
9055         case RTE_ETH_FILTER_TUNNEL:
9056                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9057                 break;
9058         case RTE_ETH_FILTER_FDIR:
9059                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9060                 break;
9061         case RTE_ETH_FILTER_GENERIC:
9062                 if (filter_op != RTE_ETH_FILTER_GET)
9063                         return -EINVAL;
9064                 *(const void **)arg = &i40e_flow_ops;
9065                 break;
9066         default:
9067                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9068                                                         filter_type);
9069                 ret = -EINVAL;
9070                 break;
9071         }
9072
9073         return ret;
9074 }
9075
9076 /*
9077  * Check and enable Extended Tag.
9078  * Enabling Extended Tag is important for 40G performance.
9079  */
9080 static void
9081 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9082 {
9083         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9084         uint32_t buf = 0;
9085         int ret;
9086
9087         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9088                                       PCI_DEV_CAP_REG);
9089         if (ret < 0) {
9090                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9091                             PCI_DEV_CAP_REG);
9092                 return;
9093         }
9094         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9095                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9096                 return;
9097         }
9098
9099         buf = 0;
9100         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9101                                       PCI_DEV_CTRL_REG);
9102         if (ret < 0) {
9103                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9104                             PCI_DEV_CTRL_REG);
9105                 return;
9106         }
9107         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9108                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9109                 return;
9110         }
9111         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9112         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9113                                        PCI_DEV_CTRL_REG);
9114         if (ret < 0) {
9115                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9116                             PCI_DEV_CTRL_REG);
9117                 return;
9118         }
9119 }
9120
9121 /*
9122  * As some registers wouldn't be reset unless a global hardware reset,
9123  * hardware initialization is needed to put those registers into an
9124  * expected initial state.
9125  */
9126 static void
9127 i40e_hw_init(struct rte_eth_dev *dev)
9128 {
9129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9130
9131         i40e_enable_extended_tag(dev);
9132
9133         /* clear the PF Queue Filter control register */
9134         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9135
9136         /* Disable symmetric hash per port */
9137         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9138 }
9139
9140 enum i40e_filter_pctype
9141 i40e_flowtype_to_pctype(uint16_t flow_type)
9142 {
9143         static const enum i40e_filter_pctype pctype_table[] = {
9144                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9145                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9146                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9147                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9148                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9149                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9150                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9151                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9152                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9153                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9154                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9155                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9156                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9157                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9158                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9159                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9160                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9161                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9162                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9163         };
9164
9165         return pctype_table[flow_type];
9166 }
9167
9168 uint16_t
9169 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9170 {
9171         static const uint16_t flowtype_table[] = {
9172                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9173                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9174                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9175                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9176                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9177                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9178                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9179                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9180                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9181                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9182                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9183                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9184                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9185                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9186                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9187                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9189                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9190                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9191                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9192                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9193                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9194                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9195                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9196                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9197                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9198                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9199                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9201                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9202                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9203         };
9204
9205         return flowtype_table[pctype];
9206 }
9207
9208 /*
9209  * On X710, performance number is far from the expectation on recent firmware
9210  * versions; on XL710, performance number is also far from the expectation on
9211  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9212  * mode is enabled and port MAC address is equal to the packet destination MAC
9213  * address. The fix for this issue may not be integrated in the following
9214  * firmware version. So the workaround in software driver is needed. It needs
9215  * to modify the initial values of 3 internal only registers for both X710 and
9216  * XL710. Note that the values for X710 or XL710 could be different, and the
9217  * workaround can be removed when it is fixed in firmware in the future.
9218  */
9219
9220 /* For both X710 and XL710 */
9221 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9222 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
9223
9224 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9225 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9226
9227 /* For X722 */
9228 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9229 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9230
9231 /* For X710 */
9232 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9233 /* For XL710 */
9234 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9235 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9236
9237 static int
9238 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9239 {
9240         enum i40e_status_code status;
9241         struct i40e_aq_get_phy_abilities_resp phy_ab;
9242         int ret = -ENOTSUP;
9243
9244         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9245                                               NULL);
9246
9247         if (status) {
9248                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9249                         status);
9250                 return ret;
9251         }
9252
9253         return 0;
9254 }
9255
9256 static void
9257 i40e_configure_registers(struct i40e_hw *hw)
9258 {
9259         static struct {
9260                 uint32_t addr;
9261                 uint64_t val;
9262         } reg_table[] = {
9263                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9264                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9265                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9266         };
9267         uint64_t reg;
9268         uint32_t i;
9269         int ret;
9270
9271         for (i = 0; i < RTE_DIM(reg_table); i++) {
9272                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9273                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9274                                 reg_table[i].val =
9275                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9276                         else /* For X710/XL710/XXV710 */
9277                                 reg_table[i].val =
9278                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9279                 }
9280
9281                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9282                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9283                                 reg_table[i].val =
9284                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9285                         else /* For X710/XL710/XXV710 */
9286                                 reg_table[i].val =
9287                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9288                 }
9289
9290                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9291                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9292                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9293                                 reg_table[i].val =
9294                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9295                         else /* For X710 */
9296                                 reg_table[i].val =
9297                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9298                 }
9299
9300                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9301                                                         &reg, NULL);
9302                 if (ret < 0) {
9303                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9304                                                         reg_table[i].addr);
9305                         break;
9306                 }
9307                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9308                                                 reg_table[i].addr, reg);
9309                 if (reg == reg_table[i].val)
9310                         continue;
9311
9312                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9313                                                 reg_table[i].val, NULL);
9314                 if (ret < 0) {
9315                         PMD_DRV_LOG(ERR,
9316                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9317                                 reg_table[i].val, reg_table[i].addr);
9318                         break;
9319                 }
9320                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9321                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9322         }
9323 }
9324
9325 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9326 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9327 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9328 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9329 static int
9330 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9331 {
9332         uint32_t reg;
9333         int ret;
9334
9335         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9336                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9337                 return -EINVAL;
9338         }
9339
9340         /* Configure for double VLAN RX stripping */
9341         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9342         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9343                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9344                 ret = i40e_aq_debug_write_register(hw,
9345                                                    I40E_VSI_TSR(vsi->vsi_id),
9346                                                    reg, NULL);
9347                 if (ret < 0) {
9348                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9349                                     vsi->vsi_id);
9350                         return I40E_ERR_CONFIG;
9351                 }
9352         }
9353
9354         /* Configure for double VLAN TX insertion */
9355         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9356         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9357                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9358                 ret = i40e_aq_debug_write_register(hw,
9359                                                    I40E_VSI_L2TAGSTXVALID(
9360                                                    vsi->vsi_id), reg, NULL);
9361                 if (ret < 0) {
9362                         PMD_DRV_LOG(ERR,
9363                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9364                                 vsi->vsi_id);
9365                         return I40E_ERR_CONFIG;
9366                 }
9367         }
9368
9369         return 0;
9370 }
9371
9372 /**
9373  * i40e_aq_add_mirror_rule
9374  * @hw: pointer to the hardware structure
9375  * @seid: VEB seid to add mirror rule to
9376  * @dst_id: destination vsi seid
9377  * @entries: Buffer which contains the entities to be mirrored
9378  * @count: number of entities contained in the buffer
9379  * @rule_id:the rule_id of the rule to be added
9380  *
9381  * Add a mirror rule for a given veb.
9382  *
9383  **/
9384 static enum i40e_status_code
9385 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9386                         uint16_t seid, uint16_t dst_id,
9387                         uint16_t rule_type, uint16_t *entries,
9388                         uint16_t count, uint16_t *rule_id)
9389 {
9390         struct i40e_aq_desc desc;
9391         struct i40e_aqc_add_delete_mirror_rule cmd;
9392         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9393                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9394                 &desc.params.raw;
9395         uint16_t buff_len;
9396         enum i40e_status_code status;
9397
9398         i40e_fill_default_direct_cmd_desc(&desc,
9399                                           i40e_aqc_opc_add_mirror_rule);
9400         memset(&cmd, 0, sizeof(cmd));
9401
9402         buff_len = sizeof(uint16_t) * count;
9403         desc.datalen = rte_cpu_to_le_16(buff_len);
9404         if (buff_len > 0)
9405                 desc.flags |= rte_cpu_to_le_16(
9406                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9407         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9408                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9409         cmd.num_entries = rte_cpu_to_le_16(count);
9410         cmd.seid = rte_cpu_to_le_16(seid);
9411         cmd.destination = rte_cpu_to_le_16(dst_id);
9412
9413         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9414         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9415         PMD_DRV_LOG(INFO,
9416                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9417                 hw->aq.asq_last_status, resp->rule_id,
9418                 resp->mirror_rules_used, resp->mirror_rules_free);
9419         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9420
9421         return status;
9422 }
9423
9424 /**
9425  * i40e_aq_del_mirror_rule
9426  * @hw: pointer to the hardware structure
9427  * @seid: VEB seid to add mirror rule to
9428  * @entries: Buffer which contains the entities to be mirrored
9429  * @count: number of entities contained in the buffer
9430  * @rule_id:the rule_id of the rule to be delete
9431  *
9432  * Delete a mirror rule for a given veb.
9433  *
9434  **/
9435 static enum i40e_status_code
9436 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9437                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9438                 uint16_t count, uint16_t rule_id)
9439 {
9440         struct i40e_aq_desc desc;
9441         struct i40e_aqc_add_delete_mirror_rule cmd;
9442         uint16_t buff_len = 0;
9443         enum i40e_status_code status;
9444         void *buff = NULL;
9445
9446         i40e_fill_default_direct_cmd_desc(&desc,
9447                                           i40e_aqc_opc_delete_mirror_rule);
9448         memset(&cmd, 0, sizeof(cmd));
9449         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9450                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9451                                                           I40E_AQ_FLAG_RD));
9452                 cmd.num_entries = count;
9453                 buff_len = sizeof(uint16_t) * count;
9454                 desc.datalen = rte_cpu_to_le_16(buff_len);
9455                 buff = (void *)entries;
9456         } else
9457                 /* rule id is filled in destination field for deleting mirror rule */
9458                 cmd.destination = rte_cpu_to_le_16(rule_id);
9459
9460         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9461                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9462         cmd.seid = rte_cpu_to_le_16(seid);
9463
9464         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9465         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9466
9467         return status;
9468 }
9469
9470 /**
9471  * i40e_mirror_rule_set
9472  * @dev: pointer to the hardware structure
9473  * @mirror_conf: mirror rule info
9474  * @sw_id: mirror rule's sw_id
9475  * @on: enable/disable
9476  *
9477  * set a mirror rule.
9478  *
9479  **/
9480 static int
9481 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9482                         struct rte_eth_mirror_conf *mirror_conf,
9483                         uint8_t sw_id, uint8_t on)
9484 {
9485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9487         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9488         struct i40e_mirror_rule *parent = NULL;
9489         uint16_t seid, dst_seid, rule_id;
9490         uint16_t i, j = 0;
9491         int ret;
9492
9493         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9494
9495         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9496                 PMD_DRV_LOG(ERR,
9497                         "mirror rule can not be configured without veb or vfs.");
9498                 return -ENOSYS;
9499         }
9500         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9501                 PMD_DRV_LOG(ERR, "mirror table is full.");
9502                 return -ENOSPC;
9503         }
9504         if (mirror_conf->dst_pool > pf->vf_num) {
9505                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9506                                  mirror_conf->dst_pool);
9507                 return -EINVAL;
9508         }
9509
9510         seid = pf->main_vsi->veb->seid;
9511
9512         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9513                 if (sw_id <= it->index) {
9514                         mirr_rule = it;
9515                         break;
9516                 }
9517                 parent = it;
9518         }
9519         if (mirr_rule && sw_id == mirr_rule->index) {
9520                 if (on) {
9521                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9522                         return -EEXIST;
9523                 } else {
9524                         ret = i40e_aq_del_mirror_rule(hw, seid,
9525                                         mirr_rule->rule_type,
9526                                         mirr_rule->entries,
9527                                         mirr_rule->num_entries, mirr_rule->id);
9528                         if (ret < 0) {
9529                                 PMD_DRV_LOG(ERR,
9530                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9531                                         ret, hw->aq.asq_last_status);
9532                                 return -ENOSYS;
9533                         }
9534                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9535                         rte_free(mirr_rule);
9536                         pf->nb_mirror_rule--;
9537                         return 0;
9538                 }
9539         } else if (!on) {
9540                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9541                 return -ENOENT;
9542         }
9543
9544         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9545                                 sizeof(struct i40e_mirror_rule) , 0);
9546         if (!mirr_rule) {
9547                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9548                 return I40E_ERR_NO_MEMORY;
9549         }
9550         switch (mirror_conf->rule_type) {
9551         case ETH_MIRROR_VLAN:
9552                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9553                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9554                                 mirr_rule->entries[j] =
9555                                         mirror_conf->vlan.vlan_id[i];
9556                                 j++;
9557                         }
9558                 }
9559                 if (j == 0) {
9560                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9561                         rte_free(mirr_rule);
9562                         return -EINVAL;
9563                 }
9564                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9565                 break;
9566         case ETH_MIRROR_VIRTUAL_POOL_UP:
9567         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9568                 /* check if the specified pool bit is out of range */
9569                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9570                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9571                         rte_free(mirr_rule);
9572                         return -EINVAL;
9573                 }
9574                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9575                         if (mirror_conf->pool_mask & (1ULL << i)) {
9576                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9577                                 j++;
9578                         }
9579                 }
9580                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9581                         /* add pf vsi to entries */
9582                         mirr_rule->entries[j] = pf->main_vsi_seid;
9583                         j++;
9584                 }
9585                 if (j == 0) {
9586                         PMD_DRV_LOG(ERR, "pool is not specified.");
9587                         rte_free(mirr_rule);
9588                         return -EINVAL;
9589                 }
9590                 /* egress and ingress in aq commands means from switch but not port */
9591                 mirr_rule->rule_type =
9592                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9593                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9594                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9595                 break;
9596         case ETH_MIRROR_UPLINK_PORT:
9597                 /* egress and ingress in aq commands means from switch but not port*/
9598                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9599                 break;
9600         case ETH_MIRROR_DOWNLINK_PORT:
9601                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9602                 break;
9603         default:
9604                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9605                         mirror_conf->rule_type);
9606                 rte_free(mirr_rule);
9607                 return -EINVAL;
9608         }
9609
9610         /* If the dst_pool is equal to vf_num, consider it as PF */
9611         if (mirror_conf->dst_pool == pf->vf_num)
9612                 dst_seid = pf->main_vsi_seid;
9613         else
9614                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9615
9616         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9617                                       mirr_rule->rule_type, mirr_rule->entries,
9618                                       j, &rule_id);
9619         if (ret < 0) {
9620                 PMD_DRV_LOG(ERR,
9621                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9622                         ret, hw->aq.asq_last_status);
9623                 rte_free(mirr_rule);
9624                 return -ENOSYS;
9625         }
9626
9627         mirr_rule->index = sw_id;
9628         mirr_rule->num_entries = j;
9629         mirr_rule->id = rule_id;
9630         mirr_rule->dst_vsi_seid = dst_seid;
9631
9632         if (parent)
9633                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9634         else
9635                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9636
9637         pf->nb_mirror_rule++;
9638         return 0;
9639 }
9640
9641 /**
9642  * i40e_mirror_rule_reset
9643  * @dev: pointer to the device
9644  * @sw_id: mirror rule's sw_id
9645  *
9646  * reset a mirror rule.
9647  *
9648  **/
9649 static int
9650 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9651 {
9652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9654         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9655         uint16_t seid;
9656         int ret;
9657
9658         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9659
9660         seid = pf->main_vsi->veb->seid;
9661
9662         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9663                 if (sw_id == it->index) {
9664                         mirr_rule = it;
9665                         break;
9666                 }
9667         }
9668         if (mirr_rule) {
9669                 ret = i40e_aq_del_mirror_rule(hw, seid,
9670                                 mirr_rule->rule_type,
9671                                 mirr_rule->entries,
9672                                 mirr_rule->num_entries, mirr_rule->id);
9673                 if (ret < 0) {
9674                         PMD_DRV_LOG(ERR,
9675                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9676                                 ret, hw->aq.asq_last_status);
9677                         return -ENOSYS;
9678                 }
9679                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9680                 rte_free(mirr_rule);
9681                 pf->nb_mirror_rule--;
9682         } else {
9683                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9684                 return -ENOENT;
9685         }
9686         return 0;
9687 }
9688
9689 static uint64_t
9690 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9691 {
9692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9693         uint64_t systim_cycles;
9694
9695         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9696         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9697                         << 32;
9698
9699         return systim_cycles;
9700 }
9701
9702 static uint64_t
9703 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9704 {
9705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9706         uint64_t rx_tstamp;
9707
9708         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9709         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9710                         << 32;
9711
9712         return rx_tstamp;
9713 }
9714
9715 static uint64_t
9716 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9717 {
9718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9719         uint64_t tx_tstamp;
9720
9721         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9722         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9723                         << 32;
9724
9725         return tx_tstamp;
9726 }
9727
9728 static void
9729 i40e_start_timecounters(struct rte_eth_dev *dev)
9730 {
9731         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9732         struct i40e_adapter *adapter =
9733                         (struct i40e_adapter *)dev->data->dev_private;
9734         struct rte_eth_link link;
9735         uint32_t tsync_inc_l;
9736         uint32_t tsync_inc_h;
9737
9738         /* Get current link speed. */
9739         memset(&link, 0, sizeof(link));
9740         i40e_dev_link_update(dev, 1);
9741         rte_i40e_dev_atomic_read_link_status(dev, &link);
9742
9743         switch (link.link_speed) {
9744         case ETH_SPEED_NUM_40G:
9745                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9746                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9747                 break;
9748         case ETH_SPEED_NUM_10G:
9749                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9750                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9751                 break;
9752         case ETH_SPEED_NUM_1G:
9753                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9754                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9755                 break;
9756         default:
9757                 tsync_inc_l = 0x0;
9758                 tsync_inc_h = 0x0;
9759         }
9760
9761         /* Set the timesync increment value. */
9762         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9763         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9764
9765         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9766         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9767         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9768
9769         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9770         adapter->systime_tc.cc_shift = 0;
9771         adapter->systime_tc.nsec_mask = 0;
9772
9773         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9774         adapter->rx_tstamp_tc.cc_shift = 0;
9775         adapter->rx_tstamp_tc.nsec_mask = 0;
9776
9777         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9778         adapter->tx_tstamp_tc.cc_shift = 0;
9779         adapter->tx_tstamp_tc.nsec_mask = 0;
9780 }
9781
9782 static int
9783 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9784 {
9785         struct i40e_adapter *adapter =
9786                         (struct i40e_adapter *)dev->data->dev_private;
9787
9788         adapter->systime_tc.nsec += delta;
9789         adapter->rx_tstamp_tc.nsec += delta;
9790         adapter->tx_tstamp_tc.nsec += delta;
9791
9792         return 0;
9793 }
9794
9795 static int
9796 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9797 {
9798         uint64_t ns;
9799         struct i40e_adapter *adapter =
9800                         (struct i40e_adapter *)dev->data->dev_private;
9801
9802         ns = rte_timespec_to_ns(ts);
9803
9804         /* Set the timecounters to a new value. */
9805         adapter->systime_tc.nsec = ns;
9806         adapter->rx_tstamp_tc.nsec = ns;
9807         adapter->tx_tstamp_tc.nsec = ns;
9808
9809         return 0;
9810 }
9811
9812 static int
9813 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9814 {
9815         uint64_t ns, systime_cycles;
9816         struct i40e_adapter *adapter =
9817                         (struct i40e_adapter *)dev->data->dev_private;
9818
9819         systime_cycles = i40e_read_systime_cyclecounter(dev);
9820         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9821         *ts = rte_ns_to_timespec(ns);
9822
9823         return 0;
9824 }
9825
9826 static int
9827 i40e_timesync_enable(struct rte_eth_dev *dev)
9828 {
9829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9830         uint32_t tsync_ctl_l;
9831         uint32_t tsync_ctl_h;
9832
9833         /* Stop the timesync system time. */
9834         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9835         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9836         /* Reset the timesync system time value. */
9837         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9838         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9839
9840         i40e_start_timecounters(dev);
9841
9842         /* Clear timesync registers. */
9843         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9844         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9845         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9846         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9847         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9848         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9849
9850         /* Enable timestamping of PTP packets. */
9851         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9852         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9853
9854         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9855         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9856         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9857
9858         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9859         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9860
9861         return 0;
9862 }
9863
9864 static int
9865 i40e_timesync_disable(struct rte_eth_dev *dev)
9866 {
9867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9868         uint32_t tsync_ctl_l;
9869         uint32_t tsync_ctl_h;
9870
9871         /* Disable timestamping of transmitted PTP packets. */
9872         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9873         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9874
9875         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9876         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9877
9878         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9879         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9880
9881         /* Reset the timesync increment value. */
9882         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9883         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9884
9885         return 0;
9886 }
9887
9888 static int
9889 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9890                                 struct timespec *timestamp, uint32_t flags)
9891 {
9892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9893         struct i40e_adapter *adapter =
9894                 (struct i40e_adapter *)dev->data->dev_private;
9895
9896         uint32_t sync_status;
9897         uint32_t index = flags & 0x03;
9898         uint64_t rx_tstamp_cycles;
9899         uint64_t ns;
9900
9901         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9902         if ((sync_status & (1 << index)) == 0)
9903                 return -EINVAL;
9904
9905         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9906         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9907         *timestamp = rte_ns_to_timespec(ns);
9908
9909         return 0;
9910 }
9911
9912 static int
9913 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9914                                 struct timespec *timestamp)
9915 {
9916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9917         struct i40e_adapter *adapter =
9918                 (struct i40e_adapter *)dev->data->dev_private;
9919
9920         uint32_t sync_status;
9921         uint64_t tx_tstamp_cycles;
9922         uint64_t ns;
9923
9924         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9925         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9926                 return -EINVAL;
9927
9928         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9929         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9930         *timestamp = rte_ns_to_timespec(ns);
9931
9932         return 0;
9933 }
9934
9935 /*
9936  * i40e_parse_dcb_configure - parse dcb configure from user
9937  * @dev: the device being configured
9938  * @dcb_cfg: pointer of the result of parse
9939  * @*tc_map: bit map of enabled traffic classes
9940  *
9941  * Returns 0 on success, negative value on failure
9942  */
9943 static int
9944 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9945                          struct i40e_dcbx_config *dcb_cfg,
9946                          uint8_t *tc_map)
9947 {
9948         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9949         uint8_t i, tc_bw, bw_lf;
9950
9951         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9952
9953         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9954         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9955                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9956                 return -EINVAL;
9957         }
9958
9959         /* assume each tc has the same bw */
9960         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9961         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9962                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9963         /* to ensure the sum of tcbw is equal to 100 */
9964         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9965         for (i = 0; i < bw_lf; i++)
9966                 dcb_cfg->etscfg.tcbwtable[i]++;
9967
9968         /* assume each tc has the same Transmission Selection Algorithm */
9969         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9970                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9971
9972         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9973                 dcb_cfg->etscfg.prioritytable[i] =
9974                                 dcb_rx_conf->dcb_tc[i];
9975
9976         /* FW needs one App to configure HW */
9977         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9978         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9979         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9980         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9981
9982         if (dcb_rx_conf->nb_tcs == 0)
9983                 *tc_map = 1; /* tc0 only */
9984         else
9985                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9986
9987         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9988                 dcb_cfg->pfc.willing = 0;
9989                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9990                 dcb_cfg->pfc.pfcenable = *tc_map;
9991         }
9992         return 0;
9993 }
9994
9995
9996 static enum i40e_status_code
9997 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9998                               struct i40e_aqc_vsi_properties_data *info,
9999                               uint8_t enabled_tcmap)
10000 {
10001         enum i40e_status_code ret;
10002         int i, total_tc = 0;
10003         uint16_t qpnum_per_tc, bsf, qp_idx;
10004         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10005         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10006         uint16_t used_queues;
10007
10008         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10009         if (ret != I40E_SUCCESS)
10010                 return ret;
10011
10012         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10013                 if (enabled_tcmap & (1 << i))
10014                         total_tc++;
10015         }
10016         if (total_tc == 0)
10017                 total_tc = 1;
10018         vsi->enabled_tc = enabled_tcmap;
10019
10020         /* different VSI has different queues assigned */
10021         if (vsi->type == I40E_VSI_MAIN)
10022                 used_queues = dev_data->nb_rx_queues -
10023                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10024         else if (vsi->type == I40E_VSI_VMDQ2)
10025                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10026         else {
10027                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10028                 return I40E_ERR_NO_AVAILABLE_VSI;
10029         }
10030
10031         qpnum_per_tc = used_queues / total_tc;
10032         /* Number of queues per enabled TC */
10033         if (qpnum_per_tc == 0) {
10034                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10035                 return I40E_ERR_INVALID_QP_ID;
10036         }
10037         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10038                                 I40E_MAX_Q_PER_TC);
10039         bsf = rte_bsf32(qpnum_per_tc);
10040
10041         /**
10042          * Configure TC and queue mapping parameters, for enabled TC,
10043          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10044          * default queue will serve it.
10045          */
10046         qp_idx = 0;
10047         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10048                 if (vsi->enabled_tc & (1 << i)) {
10049                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10050                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10051                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10052                         qp_idx += qpnum_per_tc;
10053                 } else
10054                         info->tc_mapping[i] = 0;
10055         }
10056
10057         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10058         if (vsi->type == I40E_VSI_SRIOV) {
10059                 info->mapping_flags |=
10060                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10061                 for (i = 0; i < vsi->nb_qps; i++)
10062                         info->queue_mapping[i] =
10063                                 rte_cpu_to_le_16(vsi->base_queue + i);
10064         } else {
10065                 info->mapping_flags |=
10066                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10067                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10068         }
10069         info->valid_sections |=
10070                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10071
10072         return I40E_SUCCESS;
10073 }
10074
10075 /*
10076  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10077  * @veb: VEB to be configured
10078  * @tc_map: enabled TC bitmap
10079  *
10080  * Returns 0 on success, negative value on failure
10081  */
10082 static enum i40e_status_code
10083 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10084 {
10085         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10086         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10087         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10088         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10089         enum i40e_status_code ret = I40E_SUCCESS;
10090         int i;
10091         uint32_t bw_max;
10092
10093         /* Check if enabled_tc is same as existing or new TCs */
10094         if (veb->enabled_tc == tc_map)
10095                 return ret;
10096
10097         /* configure tc bandwidth */
10098         memset(&veb_bw, 0, sizeof(veb_bw));
10099         veb_bw.tc_valid_bits = tc_map;
10100         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10101         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10102                 if (tc_map & BIT_ULL(i))
10103                         veb_bw.tc_bw_share_credits[i] = 1;
10104         }
10105         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10106                                                    &veb_bw, NULL);
10107         if (ret) {
10108                 PMD_INIT_LOG(ERR,
10109                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10110                         hw->aq.asq_last_status);
10111                 return ret;
10112         }
10113
10114         memset(&ets_query, 0, sizeof(ets_query));
10115         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10116                                                    &ets_query, NULL);
10117         if (ret != I40E_SUCCESS) {
10118                 PMD_DRV_LOG(ERR,
10119                         "Failed to get switch_comp ETS configuration %u",
10120                         hw->aq.asq_last_status);
10121                 return ret;
10122         }
10123         memset(&bw_query, 0, sizeof(bw_query));
10124         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10125                                                   &bw_query, NULL);
10126         if (ret != I40E_SUCCESS) {
10127                 PMD_DRV_LOG(ERR,
10128                         "Failed to get switch_comp bandwidth configuration %u",
10129                         hw->aq.asq_last_status);
10130                 return ret;
10131         }
10132
10133         /* store and print out BW info */
10134         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10135         veb->bw_info.bw_max = ets_query.tc_bw_max;
10136         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10137         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10138         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10139                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10140                      I40E_16_BIT_WIDTH);
10141         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10142                 veb->bw_info.bw_ets_share_credits[i] =
10143                                 bw_query.tc_bw_share_credits[i];
10144                 veb->bw_info.bw_ets_credits[i] =
10145                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10146                 /* 4 bits per TC, 4th bit is reserved */
10147                 veb->bw_info.bw_ets_max[i] =
10148                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10149                                   RTE_LEN2MASK(3, uint8_t));
10150                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10151                             veb->bw_info.bw_ets_share_credits[i]);
10152                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10153                             veb->bw_info.bw_ets_credits[i]);
10154                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10155                             veb->bw_info.bw_ets_max[i]);
10156         }
10157
10158         veb->enabled_tc = tc_map;
10159
10160         return ret;
10161 }
10162
10163
10164 /*
10165  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10166  * @vsi: VSI to be configured
10167  * @tc_map: enabled TC bitmap
10168  *
10169  * Returns 0 on success, negative value on failure
10170  */
10171 static enum i40e_status_code
10172 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10173 {
10174         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10175         struct i40e_vsi_context ctxt;
10176         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10177         enum i40e_status_code ret = I40E_SUCCESS;
10178         int i;
10179
10180         /* Check if enabled_tc is same as existing or new TCs */
10181         if (vsi->enabled_tc == tc_map)
10182                 return ret;
10183
10184         /* configure tc bandwidth */
10185         memset(&bw_data, 0, sizeof(bw_data));
10186         bw_data.tc_valid_bits = tc_map;
10187         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10188         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10189                 if (tc_map & BIT_ULL(i))
10190                         bw_data.tc_bw_credits[i] = 1;
10191         }
10192         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10193         if (ret) {
10194                 PMD_INIT_LOG(ERR,
10195                         "AQ command Config VSI BW allocation per TC failed = %d",
10196                         hw->aq.asq_last_status);
10197                 goto out;
10198         }
10199         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10200                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10201
10202         /* Update Queue Pairs Mapping for currently enabled UPs */
10203         ctxt.seid = vsi->seid;
10204         ctxt.pf_num = hw->pf_id;
10205         ctxt.vf_num = 0;
10206         ctxt.uplink_seid = vsi->uplink_seid;
10207         ctxt.info = vsi->info;
10208         i40e_get_cap(hw);
10209         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10210         if (ret)
10211                 goto out;
10212
10213         /* Update the VSI after updating the VSI queue-mapping information */
10214         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10215         if (ret) {
10216                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10217                         hw->aq.asq_last_status);
10218                 goto out;
10219         }
10220         /* update the local VSI info with updated queue map */
10221         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10222                                         sizeof(vsi->info.tc_mapping));
10223         (void)rte_memcpy(&vsi->info.queue_mapping,
10224                         &ctxt.info.queue_mapping,
10225                 sizeof(vsi->info.queue_mapping));
10226         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10227         vsi->info.valid_sections = 0;
10228
10229         /* query and update current VSI BW information */
10230         ret = i40e_vsi_get_bw_config(vsi);
10231         if (ret) {
10232                 PMD_INIT_LOG(ERR,
10233                          "Failed updating vsi bw info, err %s aq_err %s",
10234                          i40e_stat_str(hw, ret),
10235                          i40e_aq_str(hw, hw->aq.asq_last_status));
10236                 goto out;
10237         }
10238
10239         vsi->enabled_tc = tc_map;
10240
10241 out:
10242         return ret;
10243 }
10244
10245 /*
10246  * i40e_dcb_hw_configure - program the dcb setting to hw
10247  * @pf: pf the configuration is taken on
10248  * @new_cfg: new configuration
10249  * @tc_map: enabled TC bitmap
10250  *
10251  * Returns 0 on success, negative value on failure
10252  */
10253 static enum i40e_status_code
10254 i40e_dcb_hw_configure(struct i40e_pf *pf,
10255                       struct i40e_dcbx_config *new_cfg,
10256                       uint8_t tc_map)
10257 {
10258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10259         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10260         struct i40e_vsi *main_vsi = pf->main_vsi;
10261         struct i40e_vsi_list *vsi_list;
10262         enum i40e_status_code ret;
10263         int i;
10264         uint32_t val;
10265
10266         /* Use the FW API if FW > v4.4*/
10267         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10268               (hw->aq.fw_maj_ver >= 5))) {
10269                 PMD_INIT_LOG(ERR,
10270                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10271                 return I40E_ERR_FIRMWARE_API_VERSION;
10272         }
10273
10274         /* Check if need reconfiguration */
10275         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10276                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10277                 return I40E_SUCCESS;
10278         }
10279
10280         /* Copy the new config to the current config */
10281         *old_cfg = *new_cfg;
10282         old_cfg->etsrec = old_cfg->etscfg;
10283         ret = i40e_set_dcb_config(hw);
10284         if (ret) {
10285                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10286                          i40e_stat_str(hw, ret),
10287                          i40e_aq_str(hw, hw->aq.asq_last_status));
10288                 return ret;
10289         }
10290         /* set receive Arbiter to RR mode and ETS scheme by default */
10291         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10292                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10293                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10294                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10295                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10296                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10297                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10298                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10299                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10300                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10301                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10302                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10303                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10304         }
10305         /* get local mib to check whether it is configured correctly */
10306         /* IEEE mode */
10307         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10308         /* Get Local DCB Config */
10309         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10310                                      &hw->local_dcbx_config);
10311
10312         /* if Veb is created, need to update TC of it at first */
10313         if (main_vsi->veb) {
10314                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10315                 if (ret)
10316                         PMD_INIT_LOG(WARNING,
10317                                  "Failed configuring TC for VEB seid=%d",
10318                                  main_vsi->veb->seid);
10319         }
10320         /* Update each VSI */
10321         i40e_vsi_config_tc(main_vsi, tc_map);
10322         if (main_vsi->veb) {
10323                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10324                         /* Beside main VSI and VMDQ VSIs, only enable default
10325                          * TC for other VSIs
10326                          */
10327                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10328                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10329                                                          tc_map);
10330                         else
10331                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10332                                                          I40E_DEFAULT_TCMAP);
10333                         if (ret)
10334                                 PMD_INIT_LOG(WARNING,
10335                                         "Failed configuring TC for VSI seid=%d",
10336                                         vsi_list->vsi->seid);
10337                         /* continue */
10338                 }
10339         }
10340         return I40E_SUCCESS;
10341 }
10342
10343 /*
10344  * i40e_dcb_init_configure - initial dcb config
10345  * @dev: device being configured
10346  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10347  *
10348  * Returns 0 on success, negative value on failure
10349  */
10350 static int
10351 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10352 {
10353         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10355         int i, ret = 0;
10356
10357         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10358                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10359                 return -ENOTSUP;
10360         }
10361
10362         /* DCB initialization:
10363          * Update DCB configuration from the Firmware and configure
10364          * LLDP MIB change event.
10365          */
10366         if (sw_dcb == TRUE) {
10367                 ret = i40e_init_dcb(hw);
10368                 /* If lldp agent is stopped, the return value from
10369                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10370                  * adminq status. Otherwise, it should return success.
10371                  */
10372                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10373                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10374                         memset(&hw->local_dcbx_config, 0,
10375                                 sizeof(struct i40e_dcbx_config));
10376                         /* set dcb default configuration */
10377                         hw->local_dcbx_config.etscfg.willing = 0;
10378                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10379                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10380                         hw->local_dcbx_config.etscfg.tsatable[0] =
10381                                                 I40E_IEEE_TSA_ETS;
10382                         /* all UPs mapping to TC0 */
10383                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10384                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10385                         hw->local_dcbx_config.etsrec =
10386                                 hw->local_dcbx_config.etscfg;
10387                         hw->local_dcbx_config.pfc.willing = 0;
10388                         hw->local_dcbx_config.pfc.pfccap =
10389                                                 I40E_MAX_TRAFFIC_CLASS;
10390                         /* FW needs one App to configure HW */
10391                         hw->local_dcbx_config.numapps = 1;
10392                         hw->local_dcbx_config.app[0].selector =
10393                                                 I40E_APP_SEL_ETHTYPE;
10394                         hw->local_dcbx_config.app[0].priority = 3;
10395                         hw->local_dcbx_config.app[0].protocolid =
10396                                                 I40E_APP_PROTOID_FCOE;
10397                         ret = i40e_set_dcb_config(hw);
10398                         if (ret) {
10399                                 PMD_INIT_LOG(ERR,
10400                                         "default dcb config fails. err = %d, aq_err = %d.",
10401                                         ret, hw->aq.asq_last_status);
10402                                 return -ENOSYS;
10403                         }
10404                 } else {
10405                         PMD_INIT_LOG(ERR,
10406                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10407                                 ret, hw->aq.asq_last_status);
10408                         return -ENOTSUP;
10409                 }
10410         } else {
10411                 ret = i40e_aq_start_lldp(hw, NULL);
10412                 if (ret != I40E_SUCCESS)
10413                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10414
10415                 ret = i40e_init_dcb(hw);
10416                 if (!ret) {
10417                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10418                                 PMD_INIT_LOG(ERR,
10419                                         "HW doesn't support DCBX offload.");
10420                                 return -ENOTSUP;
10421                         }
10422                 } else {
10423                         PMD_INIT_LOG(ERR,
10424                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10425                                 ret, hw->aq.asq_last_status);
10426                         return -ENOTSUP;
10427                 }
10428         }
10429         return 0;
10430 }
10431
10432 /*
10433  * i40e_dcb_setup - setup dcb related config
10434  * @dev: device being configured
10435  *
10436  * Returns 0 on success, negative value on failure
10437  */
10438 static int
10439 i40e_dcb_setup(struct rte_eth_dev *dev)
10440 {
10441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10442         struct i40e_dcbx_config dcb_cfg;
10443         uint8_t tc_map = 0;
10444         int ret = 0;
10445
10446         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10447                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10448                 return -ENOTSUP;
10449         }
10450
10451         if (pf->vf_num != 0)
10452                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10453
10454         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10455         if (ret) {
10456                 PMD_INIT_LOG(ERR, "invalid dcb config");
10457                 return -EINVAL;
10458         }
10459         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10460         if (ret) {
10461                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10462                 return -ENOSYS;
10463         }
10464
10465         return 0;
10466 }
10467
10468 static int
10469 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10470                       struct rte_eth_dcb_info *dcb_info)
10471 {
10472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10474         struct i40e_vsi *vsi = pf->main_vsi;
10475         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10476         uint16_t bsf, tc_mapping;
10477         int i, j = 0;
10478
10479         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10480                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10481         else
10482                 dcb_info->nb_tcs = 1;
10483         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10484                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10485         for (i = 0; i < dcb_info->nb_tcs; i++)
10486                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10487
10488         /* get queue mapping if vmdq is disabled */
10489         if (!pf->nb_cfg_vmdq_vsi) {
10490                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10491                         if (!(vsi->enabled_tc & (1 << i)))
10492                                 continue;
10493                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10494                         dcb_info->tc_queue.tc_rxq[j][i].base =
10495                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10496                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10497                         dcb_info->tc_queue.tc_txq[j][i].base =
10498                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10499                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10500                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10501                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10502                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10503                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10504                 }
10505                 return 0;
10506         }
10507
10508         /* get queue mapping if vmdq is enabled */
10509         do {
10510                 vsi = pf->vmdq[j].vsi;
10511                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10512                         if (!(vsi->enabled_tc & (1 << i)))
10513                                 continue;
10514                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10515                         dcb_info->tc_queue.tc_rxq[j][i].base =
10516                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10517                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10518                         dcb_info->tc_queue.tc_txq[j][i].base =
10519                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10520                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10521                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10522                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10523                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10524                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10525                 }
10526                 j++;
10527         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10528         return 0;
10529 }
10530
10531 static int
10532 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10533 {
10534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10536         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10537         uint16_t interval =
10538                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10539         uint16_t msix_intr;
10540
10541         msix_intr = intr_handle->intr_vec[queue_id];
10542         if (msix_intr == I40E_MISC_VEC_ID)
10543                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10544                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10545                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10546                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10547                                (interval <<
10548                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10549         else
10550                 I40E_WRITE_REG(hw,
10551                                I40E_PFINT_DYN_CTLN(msix_intr -
10552                                                    I40E_RX_VEC_START),
10553                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10554                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10555                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10556                                (interval <<
10557                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10558
10559         I40E_WRITE_FLUSH(hw);
10560         rte_intr_enable(&pci_dev->intr_handle);
10561
10562         return 0;
10563 }
10564
10565 static int
10566 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10567 {
10568         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10570         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10571         uint16_t msix_intr;
10572
10573         msix_intr = intr_handle->intr_vec[queue_id];
10574         if (msix_intr == I40E_MISC_VEC_ID)
10575                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10576         else
10577                 I40E_WRITE_REG(hw,
10578                                I40E_PFINT_DYN_CTLN(msix_intr -
10579                                                    I40E_RX_VEC_START),
10580                                0);
10581         I40E_WRITE_FLUSH(hw);
10582
10583         return 0;
10584 }
10585
10586 static int i40e_get_regs(struct rte_eth_dev *dev,
10587                          struct rte_dev_reg_info *regs)
10588 {
10589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10590         uint32_t *ptr_data = regs->data;
10591         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10592         const struct i40e_reg_info *reg_info;
10593
10594         if (ptr_data == NULL) {
10595                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10596                 regs->width = sizeof(uint32_t);
10597                 return 0;
10598         }
10599
10600         /* The first few registers have to be read using AQ operations */
10601         reg_idx = 0;
10602         while (i40e_regs_adminq[reg_idx].name) {
10603                 reg_info = &i40e_regs_adminq[reg_idx++];
10604                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10605                         for (arr_idx2 = 0;
10606                                         arr_idx2 <= reg_info->count2;
10607                                         arr_idx2++) {
10608                                 reg_offset = arr_idx * reg_info->stride1 +
10609                                         arr_idx2 * reg_info->stride2;
10610                                 reg_offset += reg_info->base_addr;
10611                                 ptr_data[reg_offset >> 2] =
10612                                         i40e_read_rx_ctl(hw, reg_offset);
10613                         }
10614         }
10615
10616         /* The remaining registers can be read using primitives */
10617         reg_idx = 0;
10618         while (i40e_regs_others[reg_idx].name) {
10619                 reg_info = &i40e_regs_others[reg_idx++];
10620                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10621                         for (arr_idx2 = 0;
10622                                         arr_idx2 <= reg_info->count2;
10623                                         arr_idx2++) {
10624                                 reg_offset = arr_idx * reg_info->stride1 +
10625                                         arr_idx2 * reg_info->stride2;
10626                                 reg_offset += reg_info->base_addr;
10627                                 ptr_data[reg_offset >> 2] =
10628                                         I40E_READ_REG(hw, reg_offset);
10629                         }
10630         }
10631
10632         return 0;
10633 }
10634
10635 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10636 {
10637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10638
10639         /* Convert word count to byte count */
10640         return hw->nvm.sr_size << 1;
10641 }
10642
10643 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10644                            struct rte_dev_eeprom_info *eeprom)
10645 {
10646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10647         uint16_t *data = eeprom->data;
10648         uint16_t offset, length, cnt_words;
10649         int ret_code;
10650
10651         offset = eeprom->offset >> 1;
10652         length = eeprom->length >> 1;
10653         cnt_words = length;
10654
10655         if (offset > hw->nvm.sr_size ||
10656                 offset + length > hw->nvm.sr_size) {
10657                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10658                 return -EINVAL;
10659         }
10660
10661         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10662
10663         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10664         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10665                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10666                 return -EIO;
10667         }
10668
10669         return 0;
10670 }
10671
10672 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10673                                       struct ether_addr *mac_addr)
10674 {
10675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10676
10677         if (!is_valid_assigned_ether_addr(mac_addr)) {
10678                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10679                 return;
10680         }
10681
10682         /* Flags: 0x3 updates port address */
10683         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10684 }
10685
10686 static int
10687 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10688 {
10689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10690         struct rte_eth_dev_data *dev_data = pf->dev_data;
10691         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10692         int ret = 0;
10693
10694         /* check if mtu is within the allowed range */
10695         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10696                 return -EINVAL;
10697
10698         /* mtu setting is forbidden if port is start */
10699         if (dev_data->dev_started) {
10700                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10701                             dev_data->port_id);
10702                 return -EBUSY;
10703         }
10704
10705         if (frame_size > ETHER_MAX_LEN)
10706                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10707         else
10708                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10709
10710         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10711
10712         return ret;
10713 }
10714
10715 /* Restore ethertype filter */
10716 static void
10717 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10718 {
10719         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10720         struct i40e_ethertype_filter_list
10721                 *ethertype_list = &pf->ethertype.ethertype_list;
10722         struct i40e_ethertype_filter *f;
10723         struct i40e_control_filter_stats stats;
10724         uint16_t flags;
10725
10726         TAILQ_FOREACH(f, ethertype_list, rules) {
10727                 flags = 0;
10728                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10729                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10730                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10731                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10732                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10733
10734                 memset(&stats, 0, sizeof(stats));
10735                 i40e_aq_add_rem_control_packet_filter(hw,
10736                                             f->input.mac_addr.addr_bytes,
10737                                             f->input.ether_type,
10738                                             flags, pf->main_vsi->seid,
10739                                             f->queue, 1, &stats, NULL);
10740         }
10741         PMD_DRV_LOG(INFO, "Ethertype filter:"
10742                     " mac_etype_used = %u, etype_used = %u,"
10743                     " mac_etype_free = %u, etype_free = %u",
10744                     stats.mac_etype_used, stats.etype_used,
10745                     stats.mac_etype_free, stats.etype_free);
10746 }
10747
10748 /* Restore tunnel filter */
10749 static void
10750 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10751 {
10752         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10753         struct i40e_vsi *vsi;
10754         struct i40e_pf_vf *vf;
10755         struct i40e_tunnel_filter_list
10756                 *tunnel_list = &pf->tunnel.tunnel_list;
10757         struct i40e_tunnel_filter *f;
10758         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10759         bool big_buffer = 0;
10760
10761         TAILQ_FOREACH(f, tunnel_list, rules) {
10762                 if (!f->is_to_vf)
10763                         vsi = pf->main_vsi;
10764                 else {
10765                         vf = &pf->vfs[f->vf_id];
10766                         vsi = vf->vsi;
10767                 }
10768                 memset(&cld_filter, 0, sizeof(cld_filter));
10769                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10770                         (struct ether_addr *)&cld_filter.element.outer_mac);
10771                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10772                         (struct ether_addr *)&cld_filter.element.inner_mac);
10773                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10774                 cld_filter.element.flags = f->input.flags;
10775                 cld_filter.element.tenant_id = f->input.tenant_id;
10776                 cld_filter.element.queue_number = f->queue;
10777                 rte_memcpy(cld_filter.general_fields,
10778                            f->input.general_fields,
10779                            sizeof(f->input.general_fields));
10780
10781                 if (((f->input.flags &
10782                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10783                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10784                     ((f->input.flags &
10785                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10786                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10787                     ((f->input.flags &
10788                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10789                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10790                         big_buffer = 1;
10791
10792                 if (big_buffer)
10793                         i40e_aq_add_cloud_filters_big_buffer(hw,
10794                                              vsi->seid, &cld_filter, 1);
10795                 else
10796                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10797                                                   &cld_filter.element, 1);
10798         }
10799 }
10800
10801 static void
10802 i40e_filter_restore(struct i40e_pf *pf)
10803 {
10804         i40e_ethertype_filter_restore(pf);
10805         i40e_tunnel_filter_restore(pf);
10806         i40e_fdir_filter_restore(pf);
10807 }
10808
10809 static bool
10810 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10811 {
10812         if (strcmp(dev->device->driver->name, drv->driver.name))
10813                 return false;
10814
10815         return true;
10816 }
10817
10818 bool
10819 is_i40e_supported(struct rte_eth_dev *dev)
10820 {
10821         return is_device_supported(dev, &rte_i40e_pmd);
10822 }
10823
10824 /* Create a QinQ cloud filter
10825  *
10826  * The Fortville NIC has limited resources for tunnel filters,
10827  * so we can only reuse existing filters.
10828  *
10829  * In step 1 we define which Field Vector fields can be used for
10830  * filter types.
10831  * As we do not have the inner tag defined as a field,
10832  * we have to define it first, by reusing one of L1 entries.
10833  *
10834  * In step 2 we are replacing one of existing filter types with
10835  * a new one for QinQ.
10836  * As we reusing L1 and replacing L2, some of the default filter
10837  * types will disappear,which depends on L1 and L2 entries we reuse.
10838  *
10839  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10840  *
10841  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10842  *              later when we define the cloud filter.
10843  *      a.      Valid_flags.replace_cloud = 0
10844  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10845  *      c.      New_filter = 0x10
10846  *      d.      TR bit = 0xff (optional, not used here)
10847  *      e.      Buffer – 2 entries:
10848  *              i.      Byte 0 = 8 (outer vlan FV index).
10849  *                      Byte 1 = 0 (rsv)
10850  *                      Byte 2-3 = 0x0fff
10851  *              ii.     Byte 0 = 37 (inner vlan FV index).
10852  *                      Byte 1 =0 (rsv)
10853  *                      Byte 2-3 = 0x0fff
10854  *
10855  * Step 2:
10856  * 2.   Create cloud filter using two L1 filters entries: stag and
10857  *              new filter(outer vlan+ inner vlan)
10858  *      a.      Valid_flags.replace_cloud = 1
10859  *      b.      Old_filter = 1 (instead of outer IP)
10860  *      c.      New_filter = 0x10
10861  *      d.      Buffer – 2 entries:
10862  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10863  *                      Byte 1-3 = 0 (rsv)
10864  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10865  *                      Byte 9-11 = 0 (rsv)
10866  */
10867 static int
10868 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10869 {
10870         int ret = -ENOTSUP;
10871         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10872         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10873         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10874
10875         /* Init */
10876         memset(&filter_replace, 0,
10877                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10878         memset(&filter_replace_buf, 0,
10879                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10880
10881         /* create L1 filter */
10882         filter_replace.old_filter_type =
10883                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10884         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10885         filter_replace.tr_bit = 0;
10886
10887         /* Prepare the buffer, 2 entries */
10888         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10889         filter_replace_buf.data[0] |=
10890                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10891         /* Field Vector 12b mask */
10892         filter_replace_buf.data[2] = 0xff;
10893         filter_replace_buf.data[3] = 0x0f;
10894         filter_replace_buf.data[4] =
10895                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10896         filter_replace_buf.data[4] |=
10897                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10898         /* Field Vector 12b mask */
10899         filter_replace_buf.data[6] = 0xff;
10900         filter_replace_buf.data[7] = 0x0f;
10901         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10902                         &filter_replace_buf);
10903         if (ret != I40E_SUCCESS)
10904                 return ret;
10905
10906         /* Apply the second L2 cloud filter */
10907         memset(&filter_replace, 0,
10908                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10909         memset(&filter_replace_buf, 0,
10910                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10911
10912         /* create L2 filter, input for L2 filter will be L1 filter  */
10913         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10914         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10915         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10916
10917         /* Prepare the buffer, 2 entries */
10918         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10919         filter_replace_buf.data[0] |=
10920                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10921         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10922         filter_replace_buf.data[4] |=
10923                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10924         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10925                         &filter_replace_buf);
10926         return ret;
10927 }
10928
10929 RTE_INIT(i40e_init_log);
10930 static void
10931 i40e_init_log(void)
10932 {
10933         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10934         if (i40e_logtype_init >= 0)
10935                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10936         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10937         if (i40e_logtype_driver >= 0)
10938                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10939 }