drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "base/i40e_diag.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 374                                       struct ether_addr *mac_addr);
 375
 376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 377
 378 static int i40e_ethertype_filter_convert(
 379         const struct rte_eth_ethertype_filter *input,
 380         struct i40e_ethertype_filter *filter);
 381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 382                                    struct i40e_ethertype_filter *filter);
 383
 384 static int i40e_tunnel_filter_convert(
 385         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 386         struct i40e_tunnel_filter *tunnel_filter);
 387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 388                                 struct i40e_tunnel_filter *tunnel_filter);
 389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 390
 391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 393 static void i40e_filter_restore(struct i40e_pf *pf);
 394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 395
 396 int i40e_logtype_init;
 397 int i40e_logtype_driver;
 398
 399 static const struct rte_pci_id pci_id_i40e_map[] = {
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 420         { .vendor_id = 0, /* sentinel */ },
 421 };
 422
 423 static const struct eth_dev_ops i40e_eth_dev_ops = {
 424         .dev_configure                = i40e_dev_configure,
 425         .dev_start                    = i40e_dev_start,
 426         .dev_stop                     = i40e_dev_stop,
 427         .dev_close                    = i40e_dev_close,
 428         .dev_reset                    = i40e_dev_reset,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .xstats_get_names             = i40e_dev_xstats_get_names,
 439         .stats_reset                  = i40e_dev_stats_reset,
 440         .xstats_reset                 = i40e_dev_stats_reset,
 441         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 442         .fw_version_get               = i40e_fw_version_get,
 443         .dev_infos_get                = i40e_dev_info_get,
 444         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 445         .vlan_filter_set              = i40e_vlan_filter_set,
 446         .vlan_tpid_set                = i40e_vlan_tpid_set,
 447         .vlan_offload_set             = i40e_vlan_offload_set,
 448         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 449         .vlan_pvid_set                = i40e_vlan_pvid_set,
 450         .rx_queue_start               = i40e_dev_rx_queue_start,
 451         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 452         .tx_queue_start               = i40e_dev_tx_queue_start,
 453         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 454         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 455         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 456         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 457         .rx_queue_release             = i40e_dev_rx_queue_release,
 458         .rx_queue_count               = i40e_dev_rx_queue_count,
 459         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 460         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 461         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 462         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 463         .tx_queue_release             = i40e_dev_tx_queue_release,
 464         .dev_led_on                   = i40e_dev_led_on,
 465         .dev_led_off                  = i40e_dev_led_off,
 466         .flow_ctrl_get                = i40e_flow_ctrl_get,
 467         .flow_ctrl_set                = i40e_flow_ctrl_set,
 468         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 469         .mac_addr_add                 = i40e_macaddr_add,
 470         .mac_addr_remove              = i40e_macaddr_remove,
 471         .reta_update                  = i40e_dev_rss_reta_update,
 472         .reta_query                   = i40e_dev_rss_reta_query,
 473         .rss_hash_update              = i40e_dev_rss_hash_update,
 474         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 475         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 476         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 477         .filter_ctrl                  = i40e_dev_filter_ctrl,
 478         .rxq_info_get                 = i40e_rxq_info_get,
 479         .txq_info_get                 = i40e_txq_info_get,
 480         .mirror_rule_set              = i40e_mirror_rule_set,
 481         .mirror_rule_reset            = i40e_mirror_rule_reset,
 482         .timesync_enable              = i40e_timesync_enable,
 483         .timesync_disable             = i40e_timesync_disable,
 484         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 485         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 486         .get_dcb_info                 = i40e_dev_get_dcb_info,
 487         .timesync_adjust_time         = i40e_timesync_adjust_time,
 488         .timesync_read_time           = i40e_timesync_read_time,
 489         .timesync_write_time          = i40e_timesync_write_time,
 490         .get_reg                      = i40e_get_regs,
 491         .get_eeprom_length            = i40e_get_eeprom_length,
 492         .get_eeprom                   = i40e_get_eeprom,
 493         .mac_addr_set                 = i40e_set_default_mac_addr,
 494         .mtu_set                      = i40e_dev_mtu_set,
 495         .tm_ops_get                   = i40e_tm_ops_get,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 612         struct rte_pci_device *pci_dev)
 613 {
 614         return rte_eth_dev_pci_generic_probe(pci_dev,
 615                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 616 }
 617
 618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 619 {
 620         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 621 }
 622
 623 static struct rte_pci_driver rte_i40e_pmd = {
 624         .id_table = pci_id_i40e_map,
 625         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 626                      RTE_PCI_DRV_IOVA_AS_VA,
 627         .probe = eth_i40e_pci_probe,
 628         .remove = eth_i40e_pci_remove,
 629 };
 630
 631 static inline int
 632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 633                                      struct rte_eth_link *link)
 634 {
 635         struct rte_eth_link *dst = link;
 636         struct rte_eth_link *src = &(dev->data->dev_link);
 637
 638         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 639                                         *(uint64_t *)src) == 0)
 640                 return -1;
 641
 642         return 0;
 643 }
 644
 645 static inline int
 646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 647                                       struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = &(dev->data->dev_link);
 650         struct rte_eth_link *src = link;
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 660 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 661 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 662
 663 #ifndef I40E_GLQF_ORT
 664 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 665 #endif
 666 #ifndef I40E_GLQF_PIT
 667 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_L3_MAP
 670 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 674 {
 675         /*
 676          * Initialize registers for parsing packet type of QinQ
 677          * This should be removed from code once proper
 678          * configuration API is added to avoid configuration conflicts
 679          * between ports of the same device.
 680          */
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 682         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 683 }
 684
 685 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 686
 687 /*
 688  * Add a ethertype filter to drop all flow control frames transmitted
 689  * from VSIs.
 690 */
 691 static void
 692 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 693 {
 694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 695         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 696                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 697                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 698         int ret;
 699
 700         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 701                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 702                                 pf->main_vsi_seid, 0,
 703                                 TRUE, NULL, NULL);
 704         if (ret)
 705                 PMD_INIT_LOG(ERR,
 706                         "Failed to add filter to drop flow control frames from VSIs.");
 707 }
 708
 709 static int
 710 floating_veb_list_handler(__rte_unused const char *key,
 711                           const char *floating_veb_value,
 712                           void *opaque)
 713 {
 714         int idx = 0;
 715         unsigned int count = 0;
 716         char *end = NULL;
 717         int min, max;
 718         bool *vf_floating_veb = opaque;
 719
 720         while (isblank(*floating_veb_value))
 721                 floating_veb_value++;
 722
 723         /* Reset floating VEB configuration for VFs */
 724         for (idx = 0; idx < I40E_MAX_VF; idx++)
 725                 vf_floating_veb[idx] = false;
 726
 727         min = I40E_MAX_VF;
 728         do {
 729                 while (isblank(*floating_veb_value))
 730                         floating_veb_value++;
 731                 if (*floating_veb_value == '\0')
 732                         return -1;
 733                 errno = 0;
 734                 idx = strtoul(floating_veb_value, &end, 10);
 735                 if (errno || end == NULL)
 736                         return -1;
 737                 while (isblank(*end))
 738                         end++;
 739                 if (*end == '-') {
 740                         min = idx;
 741                 } else if ((*end == ';') || (*end == '\0')) {
 742                         max = idx;
 743                         if (min == I40E_MAX_VF)
 744                                 min = idx;
 745                         if (max >= I40E_MAX_VF)
 746                                 max = I40E_MAX_VF - 1;
 747                         for (idx = min; idx <= max; idx++) {
 748                                 vf_floating_veb[idx] = true;
 749                                 count++;
 750                         }
 751                         min = I40E_MAX_VF;
 752                 } else {
 753                         return -1;
 754                 }
 755                 floating_veb_value = end + 1;
 756         } while (*end != '\0');
 757
 758         if (count == 0)
 759                 return -1;
 760
 761         return 0;
 762 }
 763
 764 static void
 765 config_vf_floating_veb(struct rte_devargs *devargs,
 766                        uint16_t floating_veb,
 767                        bool *vf_floating_veb)
 768 {
 769         struct rte_kvargs *kvlist;
 770         int i;
 771         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 772
 773         if (!floating_veb)
 774                 return;
 775         /* All the VFs attach to the floating VEB by default
 776          * when the floating VEB is enabled.
 777          */
 778         for (i = 0; i < I40E_MAX_VF; i++)
 779                 vf_floating_veb[i] = true;
 780
 781         if (devargs == NULL)
 782                 return;
 783
 784         kvlist = rte_kvargs_parse(devargs->args, NULL);
 785         if (kvlist == NULL)
 786                 return;
 787
 788         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 789                 rte_kvargs_free(kvlist);
 790                 return;
 791         }
 792         /* When the floating_veb_list parameter exists, all the VFs
 793          * will attach to the legacy VEB firstly, then configure VFs
 794          * to the floating VEB according to the floating_veb_list.
 795          */
 796         if (rte_kvargs_process(kvlist, floating_veb_list,
 797                                floating_veb_list_handler,
 798                                vf_floating_veb) < 0) {
 799                 rte_kvargs_free(kvlist);
 800                 return;
 801         }
 802         rte_kvargs_free(kvlist);
 803 }
 804
 805 static int
 806 i40e_check_floating_handler(__rte_unused const char *key,
 807                             const char *value,
 808                             __rte_unused void *opaque)
 809 {
 810         if (strcmp(value, "1"))
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static int
 817 is_floating_veb_supported(struct rte_devargs *devargs)
 818 {
 819         struct rte_kvargs *kvlist;
 820         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 821
 822         if (devargs == NULL)
 823                 return 0;
 824
 825         kvlist = rte_kvargs_parse(devargs->args, NULL);
 826         if (kvlist == NULL)
 827                 return 0;
 828
 829         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 830                 rte_kvargs_free(kvlist);
 831                 return 0;
 832         }
 833         /* Floating VEB is enabled when there's key-value:
 834          * enable_floating_veb=1
 835          */
 836         if (rte_kvargs_process(kvlist, floating_veb_key,
 837                                i40e_check_floating_handler, NULL) < 0) {
 838                 rte_kvargs_free(kvlist);
 839                 return 0;
 840         }
 841         rte_kvargs_free(kvlist);
 842
 843         return 1;
 844 }
 845
 846 static void
 847 config_floating_veb(struct rte_eth_dev *dev)
 848 {
 849         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 851         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 852
 853         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 854
 855         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 856                 pf->floating_veb =
 857                         is_floating_veb_supported(pci_dev->device.devargs);
 858                 config_vf_floating_veb(pci_dev->device.devargs,
 859                                        pf->floating_veb,
 860                                        pf->floating_veb_list);
 861         } else {
 862                 pf->floating_veb = false;
 863         }
 864 }
 865
 866 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 867 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 868
 869 static int
 870 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 871 {
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 874         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 875         int ret;
 876
 877         struct rte_hash_parameters ethertype_hash_params = {
 878                 .name = ethertype_hash_name,
 879                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 880                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 881                 .hash_func = rte_hash_crc,
 882                 .hash_func_init_val = 0,
 883                 .socket_id = rte_socket_id(),
 884         };
 885
 886         /* Initialize ethertype filter rule list and hash */
 887         TAILQ_INIT(&ethertype_rule->ethertype_list);
 888         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 889                  "ethertype_%s", dev->device->name);
 890         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 891         if (!ethertype_rule->hash_table) {
 892                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 893                 return -EINVAL;
 894         }
 895         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 896                                        sizeof(struct i40e_ethertype_filter *) *
 897                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 898                                        0);
 899         if (!ethertype_rule->hash_map) {
 900                 PMD_INIT_LOG(ERR,
 901                              "Failed to allocate memory for ethertype hash map!");
 902                 ret = -ENOMEM;
 903                 goto err_ethertype_hash_map_alloc;
 904         }
 905
 906         return 0;
 907
 908 err_ethertype_hash_map_alloc:
 909         rte_hash_free(ethertype_rule->hash_table);
 910
 911         return ret;
 912 }
 913
 914 static int
 915 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 916 {
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 919         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 920         int ret;
 921
 922         struct rte_hash_parameters tunnel_hash_params = {
 923                 .name = tunnel_hash_name,
 924                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 925                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 926                 .hash_func = rte_hash_crc,
 927                 .hash_func_init_val = 0,
 928                 .socket_id = rte_socket_id(),
 929         };
 930
 931         /* Initialize tunnel filter rule list and hash */
 932         TAILQ_INIT(&tunnel_rule->tunnel_list);
 933         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 934                  "tunnel_%s", dev->device->name);
 935         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 936         if (!tunnel_rule->hash_table) {
 937                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 938                 return -EINVAL;
 939         }
 940         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 941                                     sizeof(struct i40e_tunnel_filter *) *
 942                                     I40E_MAX_TUNNEL_FILTER_NUM,
 943                                     0);
 944         if (!tunnel_rule->hash_map) {
 945                 PMD_INIT_LOG(ERR,
 946                              "Failed to allocate memory for tunnel hash map!");
 947                 ret = -ENOMEM;
 948                 goto err_tunnel_hash_map_alloc;
 949         }
 950
 951         return 0;
 952
 953 err_tunnel_hash_map_alloc:
 954         rte_hash_free(tunnel_rule->hash_table);
 955
 956         return ret;
 957 }
 958
 959 static int
 960 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 961 {
 962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 963         struct i40e_fdir_info *fdir_info = &pf->fdir;
 964         char fdir_hash_name[RTE_HASH_NAMESIZE];
 965         int ret;
 966
 967         struct rte_hash_parameters fdir_hash_params = {
 968                 .name = fdir_hash_name,
 969                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 970                 .key_len = sizeof(struct i40e_fdir_input),
 971                 .hash_func = rte_hash_crc,
 972                 .hash_func_init_val = 0,
 973                 .socket_id = rte_socket_id(),
 974         };
 975
 976         /* Initialize flow director filter rule list and hash */
 977         TAILQ_INIT(&fdir_info->fdir_list);
 978         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 979                  "fdir_%s", dev->device->name);
 980         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 981         if (!fdir_info->hash_table) {
 982                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 983                 return -EINVAL;
 984         }
 985         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 986                                           sizeof(struct i40e_fdir_filter *) *
 987                                           I40E_MAX_FDIR_FILTER_NUM,
 988                                           0);
 989         if (!fdir_info->hash_map) {
 990                 PMD_INIT_LOG(ERR,
 991                              "Failed to allocate memory for fdir hash map!");
 992                 ret = -ENOMEM;
 993                 goto err_fdir_hash_map_alloc;
 994         }
 995         return 0;
 996
 997 err_fdir_hash_map_alloc:
 998         rte_hash_free(fdir_info->hash_table);
 999
1000         return ret;
1001 }
1002
1003 static void
1004 i40e_init_customized_info(struct i40e_pf *pf)
1005 {
1006         int i;
1007
1008         /* Initialize customized pctype */
1009         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1010                 pf->customized_pctype[i].index = i;
1011                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1012                 pf->customized_pctype[i].valid = false;
1013         }
1014
1015         pf->gtp_support = false;
1016 }
1017
1018 void
1019 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1020 {
1021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct i40e_queue_regions *info = &pf->queue_region;
1024         uint16_t i;
1025
1026         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1027                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1028
1029         memset(info, 0, sizeof(struct i40e_queue_regions));
1030 }
1031
1032 static int
1033 eth_i40e_dev_init(struct rte_eth_dev *dev)
1034 {
1035         struct rte_pci_device *pci_dev;
1036         struct rte_intr_handle *intr_handle;
1037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct i40e_vsi *vsi;
1040         int ret;
1041         uint32_t len;
1042         uint8_t aq_fail = 0;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         dev->dev_ops = &i40e_eth_dev_ops;
1047         dev->rx_pkt_burst = i40e_recv_pkts;
1048         dev->tx_pkt_burst = i40e_xmit_pkts;
1049         dev->tx_pkt_prepare = i40e_prep_pkts;
1050
1051         /* for secondary processes, we don't initialise any further as primary
1052          * has already done this work. Only check we don't need a different
1053          * RX function */
1054         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1055                 i40e_set_rx_function(dev);
1056                 i40e_set_tx_function(dev);
1057                 return 0;
1058         }
1059         i40e_set_default_ptype_table(dev);
1060         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1061         intr_handle = &pci_dev->intr_handle;
1062
1063         rte_eth_copy_pci_info(dev, pci_dev);
1064
1065         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066         pf->adapter->eth_dev = dev;
1067         pf->dev_data = dev->data;
1068
1069         hw->back = I40E_PF_TO_ADAPTER(pf);
1070         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1071         if (!hw->hw_addr) {
1072                 PMD_INIT_LOG(ERR,
1073                         "Hardware is not available, as address is NULL");
1074                 return -ENODEV;
1075         }
1076
1077         hw->vendor_id = pci_dev->id.vendor_id;
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081         hw->bus.device = pci_dev->addr.devid;
1082         hw->bus.func = pci_dev->addr.function;
1083         hw->adapter_stopped = 0;
1084
1085         /* Make sure all is clean before doing PF reset */
1086         i40e_clear_hw(hw);
1087
1088         /* Initialize the hardware */
1089         i40e_hw_init(dev);
1090
1091         /* Reset here to make sure all is clean for each PF */
1092         ret = i40e_pf_reset(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1095                 return ret;
1096         }
1097
1098         /* Initialize the shared code (base driver) */
1099         ret = i40e_init_shared_code(hw);
1100         if (ret) {
1101                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1102                 return ret;
1103         }
1104
1105         i40e_set_default_pctype_table(dev);
1106
1107         /*
1108          * To work around the NVM issue, initialize registers
1109          * for packet type of QinQ by software.
1110          * It should be removed once issues are fixed in NVM.
1111          */
1112         i40e_GLQF_reg_init(hw);
1113
1114         /* Initialize the input set for filters (hash and fd) to default value */
1115         i40e_filter_input_set_init(pf);
1116
1117         /* Initialize the parameters for adminq */
1118         i40e_init_adminq_parameter(hw);
1119         ret = i40e_init_adminq(hw);
1120         if (ret != I40E_SUCCESS) {
1121                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1122                 return -EIO;
1123         }
1124         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1125                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1126                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1127                      ((hw->nvm.version >> 12) & 0xf),
1128                      ((hw->nvm.version >> 4) & 0xff),
1129                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1130
1131         /* initialise the L3_MAP register */
1132         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1133                                    0x00000028,  NULL);
1134         if (ret)
1135                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1136
1137         /* Need the special FW version to support floating VEB */
1138         config_floating_veb(dev);
1139         /* Clear PXE mode */
1140         i40e_clear_pxe_mode(hw);
1141         i40e_dev_sync_phy_type(hw);
1142
1143         /*
1144          * On X710, performance number is far from the expectation on recent
1145          * firmware versions. The fix for this issue may not be integrated in
1146          * the following firmware version. So the workaround in software driver
1147          * is needed. It needs to modify the initial values of 3 internal only
1148          * registers. Note that the workaround can be removed when it is fixed
1149          * in firmware in the future.
1150          */
1151         i40e_configure_registers(hw);
1152
1153         /* Get hw capabilities */
1154         ret = i40e_get_cap(hw);
1155         if (ret != I40E_SUCCESS) {
1156                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1157                 goto err_get_capabilities;
1158         }
1159
1160         /* Initialize parameters for PF */
1161         ret = i40e_pf_parameter_init(dev);
1162         if (ret != 0) {
1163                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1164                 goto err_parameter_init;
1165         }
1166
1167         /* Initialize the queue management */
1168         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1169         if (ret < 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1171                 goto err_qp_pool_init;
1172         }
1173         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1174                                 hw->func_caps.num_msix_vectors - 1);
1175         if (ret < 0) {
1176                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1177                 goto err_msix_pool_init;
1178         }
1179
1180         /* Initialize lan hmc */
1181         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1182                                 hw->func_caps.num_rx_qp, 0, 0);
1183         if (ret != I40E_SUCCESS) {
1184                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1185                 goto err_init_lan_hmc;
1186         }
1187
1188         /* Configure lan hmc */
1189         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1192                 goto err_configure_lan_hmc;
1193         }
1194
1195         /* Get and check the mac address */
1196         i40e_get_mac_addr(hw, hw->mac.addr);
1197         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "mac address is not valid");
1199                 ret = -EIO;
1200                 goto err_get_mac_addr;
1201         }
1202         /* Copy the permanent MAC address */
1203         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1204                         (struct ether_addr *) hw->mac.perm_addr);
1205
1206         /* Disable flow control */
1207         hw->fc.requested_mode = I40E_FC_NONE;
1208         i40e_set_fc(hw, &aq_fail, TRUE);
1209
1210         /* Set the global registers with default ether type value */
1211         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1212         if (ret != I40E_SUCCESS) {
1213                 PMD_INIT_LOG(ERR,
1214                         "Failed to set the default outer VLAN ether type");
1215                 goto err_setup_pf_switch;
1216         }
1217
1218         /* PF setup, which includes VSI setup */
1219         ret = i40e_pf_setup(pf);
1220         if (ret) {
1221                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* reset all stats of the device, including pf and main vsi */
1226         i40e_dev_stats_reset(dev);
1227
1228         vsi = pf->main_vsi;
1229
1230         /* Disable double vlan by default */
1231         i40e_vsi_config_double_vlan(vsi, FALSE);
1232
1233         /* Disable S-TAG identification when floating_veb is disabled */
1234         if (!pf->floating_veb) {
1235                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1236                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1237                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1238                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1239                 }
1240         }
1241
1242         if (!vsi->max_macaddrs)
1243                 len = ETHER_ADDR_LEN;
1244         else
1245                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1246
1247         /* Should be after VSI initialized */
1248         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1249         if (!dev->data->mac_addrs) {
1250                 PMD_INIT_LOG(ERR,
1251                         "Failed to allocated memory for storing mac address");
1252                 goto err_mac_alloc;
1253         }
1254         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1255                                         &dev->data->mac_addrs[0]);
1256
1257         /* Init dcb to sw mode by default */
1258         ret = i40e_dcb_init_configure(dev, TRUE);
1259         if (ret != I40E_SUCCESS) {
1260                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1261                 pf->flags &= ~I40E_FLAG_DCB;
1262         }
1263         /* Update HW struct after DCB configuration */
1264         i40e_get_cap(hw);
1265
1266         /* initialize pf host driver to setup SRIOV resource if applicable */
1267         i40e_pf_host_init(dev);
1268
1269         /* register callback func to eal lib */
1270         rte_intr_callback_register(intr_handle,
1271                                    i40e_dev_interrupt_handler, dev);
1272
1273         /* configure and enable device interrupt */
1274         i40e_pf_config_irq0(hw, TRUE);
1275         i40e_pf_enable_irq0(hw);
1276
1277         /* enable uio intr after callback register */
1278         rte_intr_enable(intr_handle);
1279
1280         /* By default disable flexible payload in global configuration */
1281         i40e_flex_payload_reg_set_default(hw);
1282
1283         /*
1284          * Add an ethertype filter to drop all flow control frames transmitted
1285          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1286          * frames to wire.
1287          */
1288         i40e_add_tx_flow_control_drop_filter(pf);
1289
1290         /* Set the max frame size to 0x2600 by default,
1291          * in case other drivers changed the default value.
1292          */
1293         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1294
1295         /* initialize mirror rule list */
1296         TAILQ_INIT(&pf->mirror_list);
1297
1298         /* initialize Traffic Manager configuration */
1299         i40e_tm_conf_init(dev);
1300
1301         /* Initialize customized information */
1302         i40e_init_customized_info(pf);
1303
1304         ret = i40e_init_ethtype_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_ethtype_filter_list;
1307         ret = i40e_init_tunnel_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_tunnel_filter_list;
1310         ret = i40e_init_fdir_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_fdir_filter_list;
1313
1314         /* initialize queue region configuration */
1315         i40e_init_queue_region_conf(dev);
1316
1317         /* initialize rss configuration from rte_flow */
1318         memset(&pf->rss_info, 0,
1319                 sizeof(struct i40e_rte_flow_rss_conf));
1320
1321         return 0;
1322
1323 err_init_fdir_filter_list:
1324         rte_free(pf->tunnel.hash_table);
1325         rte_free(pf->tunnel.hash_map);
1326 err_init_tunnel_filter_list:
1327         rte_free(pf->ethertype.hash_table);
1328         rte_free(pf->ethertype.hash_map);
1329 err_init_ethtype_filter_list:
1330         rte_free(dev->data->mac_addrs);
1331 err_mac_alloc:
1332         i40e_vsi_release(pf->main_vsi);
1333 err_setup_pf_switch:
1334 err_get_mac_addr:
1335 err_configure_lan_hmc:
1336         (void)i40e_shutdown_lan_hmc(hw);
1337 err_init_lan_hmc:
1338         i40e_res_pool_destroy(&pf->msix_pool);
1339 err_msix_pool_init:
1340         i40e_res_pool_destroy(&pf->qp_pool);
1341 err_qp_pool_init:
1342 err_parameter_init:
1343 err_get_capabilities:
1344         (void)i40e_shutdown_adminq(hw);
1345
1346         return ret;
1347 }
1348
1349 static void
1350 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1351 {
1352         struct i40e_ethertype_filter *p_ethertype;
1353         struct i40e_ethertype_rule *ethertype_rule;
1354
1355         ethertype_rule = &pf->ethertype;
1356         /* Remove all ethertype filter rules and hash */
1357         if (ethertype_rule->hash_map)
1358                 rte_free(ethertype_rule->hash_map);
1359         if (ethertype_rule->hash_table)
1360                 rte_hash_free(ethertype_rule->hash_table);
1361
1362         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1363                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1364                              p_ethertype, rules);
1365                 rte_free(p_ethertype);
1366         }
1367 }
1368
1369 static void
1370 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1371 {
1372         struct i40e_tunnel_filter *p_tunnel;
1373         struct i40e_tunnel_rule *tunnel_rule;
1374
1375         tunnel_rule = &pf->tunnel;
1376         /* Remove all tunnel director rules and hash */
1377         if (tunnel_rule->hash_map)
1378                 rte_free(tunnel_rule->hash_map);
1379         if (tunnel_rule->hash_table)
1380                 rte_hash_free(tunnel_rule->hash_table);
1381
1382         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1383                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1384                 rte_free(p_tunnel);
1385         }
1386 }
1387
1388 static void
1389 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1390 {
1391         struct i40e_fdir_filter *p_fdir;
1392         struct i40e_fdir_info *fdir_info;
1393
1394         fdir_info = &pf->fdir;
1395         /* Remove all flow director rules and hash */
1396         if (fdir_info->hash_map)
1397                 rte_free(fdir_info->hash_map);
1398         if (fdir_info->hash_table)
1399                 rte_hash_free(fdir_info->hash_table);
1400
1401         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1402                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1403                 rte_free(p_fdir);
1404         }
1405 }
1406
1407 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1408 {
1409         /*
1410          * Disable by default flexible payload
1411          * for corresponding L2/L3/L4 layers.
1412          */
1413         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1414         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1415         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1416 }
1417
1418 static int
1419 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1420 {
1421         struct i40e_pf *pf;
1422         struct rte_pci_device *pci_dev;
1423         struct rte_intr_handle *intr_handle;
1424         struct i40e_hw *hw;
1425         struct i40e_filter_control_settings settings;
1426         struct rte_flow *p_flow;
1427         int ret;
1428         uint8_t aq_fail = 0;
1429
1430         PMD_INIT_FUNC_TRACE();
1431
1432         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1433                 return 0;
1434
1435         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1436         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1437         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1438         intr_handle = &pci_dev->intr_handle;
1439
1440         if (hw->adapter_stopped == 0)
1441                 i40e_dev_close(dev);
1442
1443         dev->dev_ops = NULL;
1444         dev->rx_pkt_burst = NULL;
1445         dev->tx_pkt_burst = NULL;
1446
1447         /* Clear PXE mode */
1448         i40e_clear_pxe_mode(hw);
1449
1450         /* Unconfigure filter control */
1451         memset(&settings, 0, sizeof(settings));
1452         ret = i40e_set_filter_control(hw, &settings);
1453         if (ret)
1454                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1455                                         ret);
1456
1457         /* Disable flow control */
1458         hw->fc.requested_mode = I40E_FC_NONE;
1459         i40e_set_fc(hw, &aq_fail, TRUE);
1460
1461         /* uninitialize pf host driver */
1462         i40e_pf_host_uninit(dev);
1463
1464         rte_free(dev->data->mac_addrs);
1465         dev->data->mac_addrs = NULL;
1466
1467         /* disable uio intr before callback unregister */
1468         rte_intr_disable(intr_handle);
1469
1470         /* register callback func to eal lib */
1471         rte_intr_callback_unregister(intr_handle,
1472                                      i40e_dev_interrupt_handler, dev);
1473
1474         i40e_rm_ethtype_filter_list(pf);
1475         i40e_rm_tunnel_filter_list(pf);
1476         i40e_rm_fdir_filter_list(pf);
1477
1478         /* Remove all flows */
1479         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1480                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1481                 rte_free(p_flow);
1482         }
1483
1484         /* Remove all Traffic Manager configuration */
1485         i40e_tm_conf_uninit(dev);
1486
1487         return 0;
1488 }
1489
1490 static int
1491 i40e_dev_configure(struct rte_eth_dev *dev)
1492 {
1493         struct i40e_adapter *ad =
1494                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1497         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1498         int i, ret;
1499
1500         ret = i40e_dev_sync_phy_type(hw);
1501         if (ret)
1502                 return ret;
1503
1504         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1505          * bulk allocation or vector Rx preconditions we will reset it.
1506          */
1507         ad->rx_bulk_alloc_allowed = true;
1508         ad->rx_vec_allowed = true;
1509         ad->tx_simple_allowed = true;
1510         ad->tx_vec_allowed = true;
1511
1512         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1513                 ret = i40e_fdir_setup(pf);
1514                 if (ret != I40E_SUCCESS) {
1515                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1516                         return -ENOTSUP;
1517                 }
1518                 ret = i40e_fdir_configure(dev);
1519                 if (ret < 0) {
1520                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1521                         goto err;
1522                 }
1523         } else
1524                 i40e_fdir_teardown(pf);
1525
1526         ret = i40e_dev_init_vlan(dev);
1527         if (ret < 0)
1528                 goto err;
1529
1530         /* VMDQ setup.
1531          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1532          *  RSS setting have different requirements.
1533          *  General PMD driver call sequence are NIC init, configure,
1534          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1535          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1536          *  applicable. So, VMDQ setting has to be done before
1537          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1538          *  For RSS setting, it will try to calculate actual configured RX queue
1539          *  number, which will be available after rx_queue_setup(). dev_start()
1540          *  function is good to place RSS setup.
1541          */
1542         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1543                 ret = i40e_vmdq_setup(dev);
1544                 if (ret)
1545                         goto err;
1546         }
1547
1548         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1549                 ret = i40e_dcb_setup(dev);
1550                 if (ret) {
1551                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1552                         goto err_dcb;
1553                 }
1554         }
1555
1556         TAILQ_INIT(&pf->flow_list);
1557
1558         return 0;
1559
1560 err_dcb:
1561         /* need to release vmdq resource if exists */
1562         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1563                 i40e_vsi_release(pf->vmdq[i].vsi);
1564                 pf->vmdq[i].vsi = NULL;
1565         }
1566         rte_free(pf->vmdq);
1567         pf->vmdq = NULL;
1568 err:
1569         /* need to release fdir resource if exists */
1570         i40e_fdir_teardown(pf);
1571         return ret;
1572 }
1573
1574 void
1575 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1576 {
1577         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1580         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1581         uint16_t msix_vect = vsi->msix_intr;
1582         uint16_t i;
1583
1584         for (i = 0; i < vsi->nb_qps; i++) {
1585                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1586                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1587                 rte_wmb();
1588         }
1589
1590         if (vsi->type != I40E_VSI_SRIOV) {
1591                 if (!rte_intr_allow_others(intr_handle)) {
1592                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1593                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596                                        0);
1597                 } else {
1598                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1599                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1600                         I40E_WRITE_REG(hw,
1601                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1602                                                        msix_vect - 1), 0);
1603                 }
1604         } else {
1605                 uint32_t reg;
1606                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1607                         vsi->user_param + (msix_vect - 1);
1608
1609                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1610                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1611         }
1612         I40E_WRITE_FLUSH(hw);
1613 }
1614
1615 static void
1616 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1617                        int base_queue, int nb_queue,
1618                        uint16_t itr_idx)
1619 {
1620         int i;
1621         uint32_t val;
1622         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1623
1624         /* Bind all RX queues to allocated MSIX interrupt */
1625         for (i = 0; i < nb_queue; i++) {
1626                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1627                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1628                         ((base_queue + i + 1) <<
1629                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1630                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1631                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1632
1633                 if (i == nb_queue - 1)
1634                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1635                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1636         }
1637
1638         /* Write first RX queue to Link list register as the head element */
1639         if (vsi->type != I40E_VSI_SRIOV) {
1640                 uint16_t interval =
1641                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1642
1643                 if (msix_vect == I40E_MISC_VEC_ID) {
1644                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1645                                        (base_queue <<
1646                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1647                                        (0x0 <<
1648                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1649                         I40E_WRITE_REG(hw,
1650                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1651                                        interval);
1652                 } else {
1653                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1654                                        (base_queue <<
1655                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1656                                        (0x0 <<
1657                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1658                         I40E_WRITE_REG(hw,
1659                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1660                                                        msix_vect - 1),
1661                                        interval);
1662                 }
1663         } else {
1664                 uint32_t reg;
1665
1666                 if (msix_vect == I40E_MISC_VEC_ID) {
1667                         I40E_WRITE_REG(hw,
1668                                        I40E_VPINT_LNKLST0(vsi->user_param),
1669                                        (base_queue <<
1670                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1671                                        (0x0 <<
1672                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1673                 } else {
1674                         /* num_msix_vectors_vf needs to minus irq0 */
1675                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1676                                 vsi->user_param + (msix_vect - 1);
1677
1678                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1679                                        (base_queue <<
1680                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1681                                        (0x0 <<
1682                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1683                 }
1684         }
1685
1686         I40E_WRITE_FLUSH(hw);
1687 }
1688
1689 void
1690 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1691 {
1692         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1693         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1694         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1695         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1696         uint16_t msix_vect = vsi->msix_intr;
1697         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1698         uint16_t queue_idx = 0;
1699         int record = 0;
1700         uint32_t val;
1701         int i;
1702
1703         for (i = 0; i < vsi->nb_qps; i++) {
1704                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1705                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1706         }
1707
1708         /* INTENA flag is not auto-cleared for interrupt */
1709         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1710         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1711                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1712                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1713         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1714
1715         /* VF bind interrupt */
1716         if (vsi->type == I40E_VSI_SRIOV) {
1717                 __vsi_queues_bind_intr(vsi, msix_vect,
1718                                        vsi->base_queue, vsi->nb_qps,
1719                                        itr_idx);
1720                 return;
1721         }
1722
1723         /* PF & VMDq bind interrupt */
1724         if (rte_intr_dp_is_en(intr_handle)) {
1725                 if (vsi->type == I40E_VSI_MAIN) {
1726                         queue_idx = 0;
1727                         record = 1;
1728                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1729                         struct i40e_vsi *main_vsi =
1730                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1731                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1732                         record = 1;
1733                 }
1734         }
1735
1736         for (i = 0; i < vsi->nb_used_qps; i++) {
1737                 if (nb_msix <= 1) {
1738                         if (!rte_intr_allow_others(intr_handle))
1739                                 /* allow to share MISC_VEC_ID */
1740                                 msix_vect = I40E_MISC_VEC_ID;
1741
1742                         /* no enough msix_vect, map all to one */
1743                         __vsi_queues_bind_intr(vsi, msix_vect,
1744                                                vsi->base_queue + i,
1745                                                vsi->nb_used_qps - i,
1746                                                itr_idx);
1747                         for (; !!record && i < vsi->nb_used_qps; i++)
1748                                 intr_handle->intr_vec[queue_idx + i] =
1749                                         msix_vect;
1750                         break;
1751                 }
1752                 /* 1:1 queue/msix_vect mapping */
1753                 __vsi_queues_bind_intr(vsi, msix_vect,
1754                                        vsi->base_queue + i, 1,
1755                                        itr_idx);
1756                 if (!!record)
1757                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1758
1759                 msix_vect++;
1760                 nb_msix--;
1761         }
1762 }
1763
1764 static void
1765 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1766 {
1767         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1769         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771         uint16_t interval = i40e_calc_itr_interval(\
1772                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1773         uint16_t msix_intr, i;
1774
1775         if (rte_intr_allow_others(intr_handle))
1776                 for (i = 0; i < vsi->nb_msix; i++) {
1777                         msix_intr = vsi->msix_intr + i;
1778                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1779                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1780                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1781                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1782                                 (interval <<
1783                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1784                 }
1785         else
1786                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1787                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1788                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1789                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1790                                (interval <<
1791                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1792
1793         I40E_WRITE_FLUSH(hw);
1794 }
1795
1796 static void
1797 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1798 {
1799         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1800         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1801         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1802         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1803         uint16_t msix_intr, i;
1804
1805         if (rte_intr_allow_others(intr_handle))
1806                 for (i = 0; i < vsi->nb_msix; i++) {
1807                         msix_intr = vsi->msix_intr + i;
1808                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1809                                        0);
1810                 }
1811         else
1812                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1813
1814         I40E_WRITE_FLUSH(hw);
1815 }
1816
1817 static inline uint8_t
1818 i40e_parse_link_speeds(uint16_t link_speeds)
1819 {
1820         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1821
1822         if (link_speeds & ETH_LINK_SPEED_40G)
1823                 link_speed |= I40E_LINK_SPEED_40GB;
1824         if (link_speeds & ETH_LINK_SPEED_25G)
1825                 link_speed |= I40E_LINK_SPEED_25GB;
1826         if (link_speeds & ETH_LINK_SPEED_20G)
1827                 link_speed |= I40E_LINK_SPEED_20GB;
1828         if (link_speeds & ETH_LINK_SPEED_10G)
1829                 link_speed |= I40E_LINK_SPEED_10GB;
1830         if (link_speeds & ETH_LINK_SPEED_1G)
1831                 link_speed |= I40E_LINK_SPEED_1GB;
1832         if (link_speeds & ETH_LINK_SPEED_100M)
1833                 link_speed |= I40E_LINK_SPEED_100MB;
1834
1835         return link_speed;
1836 }
1837
1838 static int
1839 i40e_phy_conf_link(struct i40e_hw *hw,
1840                    uint8_t abilities,
1841                    uint8_t force_speed,
1842                    bool is_up)
1843 {
1844         enum i40e_status_code status;
1845         struct i40e_aq_get_phy_abilities_resp phy_ab;
1846         struct i40e_aq_set_phy_config phy_conf;
1847         enum i40e_aq_phy_type cnt;
1848         uint32_t phy_type_mask = 0;
1849
1850         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1851                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1852                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1853                         I40E_AQ_PHY_FLAG_LOW_POWER;
1854         const uint8_t advt = I40E_LINK_SPEED_40GB |
1855                         I40E_LINK_SPEED_25GB |
1856                         I40E_LINK_SPEED_10GB |
1857                         I40E_LINK_SPEED_1GB |
1858                         I40E_LINK_SPEED_100MB;
1859         int ret = -ENOTSUP;
1860
1861
1862         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1863                                               NULL);
1864         if (status)
1865                 return ret;
1866
1867         /* If link already up, no need to set up again */
1868         if (is_up && phy_ab.phy_type != 0)
1869                 return I40E_SUCCESS;
1870
1871         memset(&phy_conf, 0, sizeof(phy_conf));
1872
1873         /* bits 0-2 use the values from get_phy_abilities_resp */
1874         abilities &= ~mask;
1875         abilities |= phy_ab.abilities & mask;
1876
1877         /* update ablities and speed */
1878         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1879                 phy_conf.link_speed = advt;
1880         else
1881                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1882
1883         phy_conf.abilities = abilities;
1884
1885
1886
1887         /* To enable link, phy_type mask needs to include each type */
1888         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1889                 phy_type_mask |= 1 << cnt;
1890
1891         /* use get_phy_abilities_resp value for the rest */
1892         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1893         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1894                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1895                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1896         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1897         phy_conf.eee_capability = phy_ab.eee_capability;
1898         phy_conf.eeer = phy_ab.eeer_val;
1899         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1900
1901         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1902                     phy_ab.abilities, phy_ab.link_speed);
1903         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1904                     phy_conf.abilities, phy_conf.link_speed);
1905
1906         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1907         if (status)
1908                 return ret;
1909
1910         return I40E_SUCCESS;
1911 }
1912
1913 static int
1914 i40e_apply_link_speed(struct rte_eth_dev *dev)
1915 {
1916         uint8_t speed;
1917         uint8_t abilities = 0;
1918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1919         struct rte_eth_conf *conf = &dev->data->dev_conf;
1920
1921         speed = i40e_parse_link_speeds(conf->link_speeds);
1922         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1923         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1924                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1925         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1926
1927         return i40e_phy_conf_link(hw, abilities, speed, true);
1928 }
1929
1930 static int
1931 i40e_dev_start(struct rte_eth_dev *dev)
1932 {
1933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         struct i40e_vsi *main_vsi = pf->main_vsi;
1936         int ret, i;
1937         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1938         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1939         uint32_t intr_vector = 0;
1940         struct i40e_vsi *vsi;
1941
1942         hw->adapter_stopped = 0;
1943
1944         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1945                 PMD_INIT_LOG(ERR,
1946                 "Invalid link_speeds for port %u, autonegotiation disabled",
1947                               dev->data->port_id);
1948                 return -EINVAL;
1949         }
1950
1951         rte_intr_disable(intr_handle);
1952
1953         if ((rte_intr_cap_multiple(intr_handle) ||
1954              !RTE_ETH_DEV_SRIOV(dev).active) &&
1955             dev->data->dev_conf.intr_conf.rxq != 0) {
1956                 intr_vector = dev->data->nb_rx_queues;
1957                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1958                 if (ret)
1959                         return ret;
1960         }
1961
1962         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1963                 intr_handle->intr_vec =
1964                         rte_zmalloc("intr_vec",
1965                                     dev->data->nb_rx_queues * sizeof(int),
1966                                     0);
1967                 if (!intr_handle->intr_vec) {
1968                         PMD_INIT_LOG(ERR,
1969                                 "Failed to allocate %d rx_queues intr_vec",
1970                                 dev->data->nb_rx_queues);
1971                         return -ENOMEM;
1972                 }
1973         }
1974
1975         /* Initialize VSI */
1976         ret = i40e_dev_rxtx_init(pf);
1977         if (ret != I40E_SUCCESS) {
1978                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1979                 goto err_up;
1980         }
1981
1982         /* Map queues with MSIX interrupt */
1983         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1984                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1985         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1986         i40e_vsi_enable_queues_intr(main_vsi);
1987
1988         /* Map VMDQ VSI queues with MSIX interrupt */
1989         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1990                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1991                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1992                                           I40E_ITR_INDEX_DEFAULT);
1993                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1994         }
1995
1996         /* enable FDIR MSIX interrupt */
1997         if (pf->fdir.fdir_vsi) {
1998                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1999                                           I40E_ITR_INDEX_NONE);
2000                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2001         }
2002
2003         /* Enable all queues which have been configured */
2004         ret = i40e_dev_switch_queues(pf, TRUE);
2005
2006         if (ret != I40E_SUCCESS) {
2007                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2008                 goto err_up;
2009         }
2010
2011         /* Enable receiving broadcast packets */
2012         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2013         if (ret != I40E_SUCCESS)
2014                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2015
2016         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2018                                                 true, NULL);
2019                 if (ret != I40E_SUCCESS)
2020                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2021         }
2022
2023         /* Enable the VLAN promiscuous mode. */
2024         if (pf->vfs) {
2025                 for (i = 0; i < pf->vf_num; i++) {
2026                         vsi = pf->vfs[i].vsi;
2027                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2028                                                      true, NULL);
2029                 }
2030         }
2031
2032         /* Enable mac loopback mode */
2033         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2034             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2035                 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2036                 if (ret != I40E_SUCCESS) {
2037                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2038                         goto err_up;
2039                 }
2040         }
2041
2042         /* Apply link configure */
2043         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2044                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2045                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2046                                 ETH_LINK_SPEED_40G)) {
2047                 PMD_DRV_LOG(ERR, "Invalid link setting");
2048                 goto err_up;
2049         }
2050         ret = i40e_apply_link_speed(dev);
2051         if (I40E_SUCCESS != ret) {
2052                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2053                 goto err_up;
2054         }
2055
2056         if (!rte_intr_allow_others(intr_handle)) {
2057                 rte_intr_callback_unregister(intr_handle,
2058                                              i40e_dev_interrupt_handler,
2059                                              (void *)dev);
2060                 /* configure and enable device interrupt */
2061                 i40e_pf_config_irq0(hw, FALSE);
2062                 i40e_pf_enable_irq0(hw);
2063
2064                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2065                         PMD_INIT_LOG(INFO,
2066                                 "lsc won't enable because of no intr multiplex");
2067         } else {
2068                 ret = i40e_aq_set_phy_int_mask(hw,
2069                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2070                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2071                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2072                 if (ret != I40E_SUCCESS)
2073                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2074
2075                 /* Call get_link_info aq commond to enable/disable LSE */
2076                 i40e_dev_link_update(dev, 0);
2077         }
2078
2079         /* enable uio intr after callback register */
2080         rte_intr_enable(intr_handle);
2081
2082         i40e_filter_restore(pf);
2083
2084         if (pf->tm_conf.root && !pf->tm_conf.committed)
2085                 PMD_DRV_LOG(WARNING,
2086                             "please call hierarchy_commit() "
2087                             "before starting the port");
2088
2089         return I40E_SUCCESS;
2090
2091 err_up:
2092         i40e_dev_switch_queues(pf, FALSE);
2093         i40e_dev_clear_queues(dev);
2094
2095         return ret;
2096 }
2097
2098 static void
2099 i40e_dev_stop(struct rte_eth_dev *dev)
2100 {
2101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2102         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2103         struct i40e_vsi *main_vsi = pf->main_vsi;
2104         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2105         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2106         int i;
2107
2108         if (hw->adapter_stopped == 1)
2109                 return;
2110         /* Disable all queues */
2111         i40e_dev_switch_queues(pf, FALSE);
2112
2113         /* un-map queues with interrupt registers */
2114         i40e_vsi_disable_queues_intr(main_vsi);
2115         i40e_vsi_queues_unbind_intr(main_vsi);
2116
2117         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2118                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2119                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2120         }
2121
2122         if (pf->fdir.fdir_vsi) {
2123                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2124                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2125         }
2126         /* Clear all queues and release memory */
2127         i40e_dev_clear_queues(dev);
2128
2129         /* Set link down */
2130         i40e_dev_set_link_down(dev);
2131
2132         if (!rte_intr_allow_others(intr_handle))
2133                 /* resume to the default handler */
2134                 rte_intr_callback_register(intr_handle,
2135                                            i40e_dev_interrupt_handler,
2136                                            (void *)dev);
2137
2138         /* Clean datapath event and queue/vec mapping */
2139         rte_intr_efd_disable(intr_handle);
2140         if (intr_handle->intr_vec) {
2141                 rte_free(intr_handle->intr_vec);
2142                 intr_handle->intr_vec = NULL;
2143         }
2144
2145         /* reset hierarchy commit */
2146         pf->tm_conf.committed = false;
2147
2148         hw->adapter_stopped = 1;
2149 }
2150
2151 static void
2152 i40e_dev_close(struct rte_eth_dev *dev)
2153 {
2154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2157         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2158         struct i40e_mirror_rule *p_mirror;
2159         uint32_t reg;
2160         int i;
2161         int ret;
2162
2163         PMD_INIT_FUNC_TRACE();
2164
2165         i40e_dev_stop(dev);
2166
2167         /* Remove all mirror rules */
2168         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2169                 ret = i40e_aq_del_mirror_rule(hw,
2170                                               pf->main_vsi->veb->seid,
2171                                               p_mirror->rule_type,
2172                                               p_mirror->entries,
2173                                               p_mirror->num_entries,
2174                                               p_mirror->id);
2175                 if (ret < 0)
2176                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2177                                     "status = %d, aq_err = %d.", ret,
2178                                     hw->aq.asq_last_status);
2179
2180                 /* remove mirror software resource anyway */
2181                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2182                 rte_free(p_mirror);
2183                 pf->nb_mirror_rule--;
2184         }
2185
2186         i40e_dev_free_queues(dev);
2187
2188         /* Disable interrupt */
2189         i40e_pf_disable_irq0(hw);
2190         rte_intr_disable(intr_handle);
2191
2192         /* shutdown and destroy the HMC */
2193         i40e_shutdown_lan_hmc(hw);
2194
2195         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2196                 i40e_vsi_release(pf->vmdq[i].vsi);
2197                 pf->vmdq[i].vsi = NULL;
2198         }
2199         rte_free(pf->vmdq);
2200         pf->vmdq = NULL;
2201
2202         /* release all the existing VSIs and VEBs */
2203         i40e_fdir_teardown(pf);
2204         i40e_vsi_release(pf->main_vsi);
2205
2206         /* shutdown the adminq */
2207         i40e_aq_queue_shutdown(hw, true);
2208         i40e_shutdown_adminq(hw);
2209
2210         i40e_res_pool_destroy(&pf->qp_pool);
2211         i40e_res_pool_destroy(&pf->msix_pool);
2212
2213         /* Disable flexible payload in global configuration */
2214         i40e_flex_payload_reg_set_default(hw);
2215
2216         /* force a PF reset to clean anything leftover */
2217         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2218         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2219                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2220         I40E_WRITE_FLUSH(hw);
2221 }
2222
2223 /*
2224  * Reset PF device only to re-initialize resources in PMD layer
2225  */
2226 static int
2227 i40e_dev_reset(struct rte_eth_dev *dev)
2228 {
2229         int ret;
2230
2231         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2232          * its VF to make them align with it. The detailed notification
2233          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2234          * To avoid unexpected behavior in VF, currently reset of PF with
2235          * SR-IOV activation is not supported. It might be supported later.
2236          */
2237         if (dev->data->sriov.active)
2238                 return -ENOTSUP;
2239
2240         ret = eth_i40e_dev_uninit(dev);
2241         if (ret)
2242                 return ret;
2243
2244         ret = eth_i40e_dev_init(dev);
2245
2246         return ret;
2247 }
2248
2249 static void
2250 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2251 {
2252         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2253         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2254         struct i40e_vsi *vsi = pf->main_vsi;
2255         int status;
2256
2257         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2258                                                      true, NULL, true);
2259         if (status != I40E_SUCCESS)
2260                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2261
2262         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2263                                                         TRUE, NULL);
2264         if (status != I40E_SUCCESS)
2265                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2266
2267 }
2268
2269 static void
2270 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2271 {
2272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2274         struct i40e_vsi *vsi = pf->main_vsi;
2275         int status;
2276
2277         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2278                                                      false, NULL, true);
2279         if (status != I40E_SUCCESS)
2280                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2281
2282         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2283                                                         false, NULL);
2284         if (status != I40E_SUCCESS)
2285                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2286 }
2287
2288 static void
2289 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2290 {
2291         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2293         struct i40e_vsi *vsi = pf->main_vsi;
2294         int ret;
2295
2296         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2297         if (ret != I40E_SUCCESS)
2298                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2299 }
2300
2301 static void
2302 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2303 {
2304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306         struct i40e_vsi *vsi = pf->main_vsi;
2307         int ret;
2308
2309         if (dev->data->promiscuous == 1)
2310                 return; /* must remain in all_multicast mode */
2311
2312         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2313                                 vsi->seid, FALSE, NULL);
2314         if (ret != I40E_SUCCESS)
2315                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2316 }
2317
2318 /*
2319  * Set device link up.
2320  */
2321 static int
2322 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2323 {
2324         /* re-apply link speed setting */
2325         return i40e_apply_link_speed(dev);
2326 }
2327
2328 /*
2329  * Set device link down.
2330  */
2331 static int
2332 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2333 {
2334         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2335         uint8_t abilities = 0;
2336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337
2338         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2339         return i40e_phy_conf_link(hw, abilities, speed, false);
2340 }
2341
2342 int
2343 i40e_dev_link_update(struct rte_eth_dev *dev,
2344                      int wait_to_complete)
2345 {
2346 #define CHECK_INTERVAL 100  /* 100ms */
2347 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2349         struct i40e_link_status link_status;
2350         struct rte_eth_link link, old;
2351         int status;
2352         unsigned rep_cnt = MAX_REPEAT_TIME;
2353         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2354
2355         memset(&link, 0, sizeof(link));
2356         memset(&old, 0, sizeof(old));
2357         memset(&link_status, 0, sizeof(link_status));
2358         rte_i40e_dev_atomic_read_link_status(dev, &old);
2359
2360         do {
2361                 /* Get link status information from hardware */
2362                 status = i40e_aq_get_link_info(hw, enable_lse,
2363                                                 &link_status, NULL);
2364                 if (status != I40E_SUCCESS) {
2365                         link.link_speed = ETH_SPEED_NUM_100M;
2366                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2367                         PMD_DRV_LOG(ERR, "Failed to get link info");
2368                         goto out;
2369                 }
2370
2371                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2372                 if (!wait_to_complete || link.link_status)
2373                         break;
2374
2375                 rte_delay_ms(CHECK_INTERVAL);
2376         } while (--rep_cnt);
2377
2378         if (!link.link_status)
2379                 goto out;
2380
2381         /* i40e uses full duplex only */
2382         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2383
2384         /* Parse the link status */
2385         switch (link_status.link_speed) {
2386         case I40E_LINK_SPEED_100MB:
2387                 link.link_speed = ETH_SPEED_NUM_100M;
2388                 break;
2389         case I40E_LINK_SPEED_1GB:
2390                 link.link_speed = ETH_SPEED_NUM_1G;
2391                 break;
2392         case I40E_LINK_SPEED_10GB:
2393                 link.link_speed = ETH_SPEED_NUM_10G;
2394                 break;
2395         case I40E_LINK_SPEED_20GB:
2396                 link.link_speed = ETH_SPEED_NUM_20G;
2397                 break;
2398         case I40E_LINK_SPEED_25GB:
2399                 link.link_speed = ETH_SPEED_NUM_25G;
2400                 break;
2401         case I40E_LINK_SPEED_40GB:
2402                 link.link_speed = ETH_SPEED_NUM_40G;
2403                 break;
2404         default:
2405                 link.link_speed = ETH_SPEED_NUM_100M;
2406                 break;
2407         }
2408
2409         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2410                         ETH_LINK_SPEED_FIXED);
2411
2412 out:
2413         rte_i40e_dev_atomic_write_link_status(dev, &link);
2414         if (link.link_status == old.link_status)
2415                 return -1;
2416
2417         i40e_notify_all_vfs_link_status(dev);
2418
2419         return 0;
2420 }
2421
2422 /* Get all the statistics of a VSI */
2423 void
2424 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2425 {
2426         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2427         struct i40e_eth_stats *nes = &vsi->eth_stats;
2428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2429         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2430
2431         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2432                             vsi->offset_loaded, &oes->rx_bytes,
2433                             &nes->rx_bytes);
2434         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2435                             vsi->offset_loaded, &oes->rx_unicast,
2436                             &nes->rx_unicast);
2437         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2438                             vsi->offset_loaded, &oes->rx_multicast,
2439                             &nes->rx_multicast);
2440         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2441                             vsi->offset_loaded, &oes->rx_broadcast,
2442                             &nes->rx_broadcast);
2443         /* exclude CRC bytes */
2444         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2445                 nes->rx_broadcast) * ETHER_CRC_LEN;
2446
2447         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2448                             &oes->rx_discards, &nes->rx_discards);
2449         /* GLV_REPC not supported */
2450         /* GLV_RMPC not supported */
2451         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2452                             &oes->rx_unknown_protocol,
2453                             &nes->rx_unknown_protocol);
2454         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2455                             vsi->offset_loaded, &oes->tx_bytes,
2456                             &nes->tx_bytes);
2457         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2458                             vsi->offset_loaded, &oes->tx_unicast,
2459                             &nes->tx_unicast);
2460         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2461                             vsi->offset_loaded, &oes->tx_multicast,
2462                             &nes->tx_multicast);
2463         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2464                             vsi->offset_loaded,  &oes->tx_broadcast,
2465                             &nes->tx_broadcast);
2466         /* GLV_TDPC not supported */
2467         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2468                             &oes->tx_errors, &nes->tx_errors);
2469         vsi->offset_loaded = true;
2470
2471         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2472                     vsi->vsi_id);
2473         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2474         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2475         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2476         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2477         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2478         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2479                     nes->rx_unknown_protocol);
2480         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2481         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2482         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2483         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2484         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2485         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2486         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2487                     vsi->vsi_id);
2488 }
2489
2490 static void
2491 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2492 {
2493         unsigned int i;
2494         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2495         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2496
2497         /* Get rx/tx bytes of internal transfer packets */
2498         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2499                         I40E_GLV_GORCL(hw->port),
2500                         pf->offset_loaded,
2501                         &pf->internal_stats_offset.rx_bytes,
2502                         &pf->internal_stats.rx_bytes);
2503
2504         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2505                         I40E_GLV_GOTCL(hw->port),
2506                         pf->offset_loaded,
2507                         &pf->internal_stats_offset.tx_bytes,
2508                         &pf->internal_stats.tx_bytes);
2509         /* Get total internal rx packet count */
2510         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2511                             I40E_GLV_UPRCL(hw->port),
2512                             pf->offset_loaded,
2513                             &pf->internal_stats_offset.rx_unicast,
2514                             &pf->internal_stats.rx_unicast);
2515         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2516                             I40E_GLV_MPRCL(hw->port),
2517                             pf->offset_loaded,
2518                             &pf->internal_stats_offset.rx_multicast,
2519                             &pf->internal_stats.rx_multicast);
2520         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2521                             I40E_GLV_BPRCL(hw->port),
2522                             pf->offset_loaded,
2523                             &pf->internal_stats_offset.rx_broadcast,
2524                             &pf->internal_stats.rx_broadcast);
2525         /* Get total internal tx packet count */
2526         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2527                             I40E_GLV_UPTCL(hw->port),
2528                             pf->offset_loaded,
2529                             &pf->internal_stats_offset.tx_unicast,
2530                             &pf->internal_stats.tx_unicast);
2531         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2532                             I40E_GLV_MPTCL(hw->port),
2533                             pf->offset_loaded,
2534                             &pf->internal_stats_offset.tx_multicast,
2535                             &pf->internal_stats.tx_multicast);
2536         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2537                             I40E_GLV_BPTCL(hw->port),
2538                             pf->offset_loaded,
2539                             &pf->internal_stats_offset.tx_broadcast,
2540                             &pf->internal_stats.tx_broadcast);
2541
2542         /* exclude CRC size */
2543         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2544                 pf->internal_stats.rx_multicast +
2545                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2546
2547         /* Get statistics of struct i40e_eth_stats */
2548         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2549                             I40E_GLPRT_GORCL(hw->port),
2550                             pf->offset_loaded, &os->eth.rx_bytes,
2551                             &ns->eth.rx_bytes);
2552         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2553                             I40E_GLPRT_UPRCL(hw->port),
2554                             pf->offset_loaded, &os->eth.rx_unicast,
2555                             &ns->eth.rx_unicast);
2556         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2557                             I40E_GLPRT_MPRCL(hw->port),
2558                             pf->offset_loaded, &os->eth.rx_multicast,
2559                             &ns->eth.rx_multicast);
2560         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2561                             I40E_GLPRT_BPRCL(hw->port),
2562                             pf->offset_loaded, &os->eth.rx_broadcast,
2563                             &ns->eth.rx_broadcast);
2564         /* Workaround: CRC size should not be included in byte statistics,
2565          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2566          */
2567         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2568                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2569
2570         /* exclude internal rx bytes
2571          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2572          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2573          * value.
2574          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2575          */
2576         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2577                 ns->eth.rx_bytes = 0;
2578         else
2579                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2580
2581         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2582                 ns->eth.rx_unicast = 0;
2583         else
2584                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2585
2586         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2587                 ns->eth.rx_multicast = 0;
2588         else
2589                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2590
2591         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2592                 ns->eth.rx_broadcast = 0;
2593         else
2594                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2595
2596         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2597                             pf->offset_loaded, &os->eth.rx_discards,
2598                             &ns->eth.rx_discards);
2599         /* GLPRT_REPC not supported */
2600         /* GLPRT_RMPC not supported */
2601         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2602                             pf->offset_loaded,
2603                             &os->eth.rx_unknown_protocol,
2604                             &ns->eth.rx_unknown_protocol);
2605         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2606                             I40E_GLPRT_GOTCL(hw->port),
2607                             pf->offset_loaded, &os->eth.tx_bytes,
2608                             &ns->eth.tx_bytes);
2609         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2610                             I40E_GLPRT_UPTCL(hw->port),
2611                             pf->offset_loaded, &os->eth.tx_unicast,
2612                             &ns->eth.tx_unicast);
2613         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2614                             I40E_GLPRT_MPTCL(hw->port),
2615                             pf->offset_loaded, &os->eth.tx_multicast,
2616                             &ns->eth.tx_multicast);
2617         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2618                             I40E_GLPRT_BPTCL(hw->port),
2619                             pf->offset_loaded, &os->eth.tx_broadcast,
2620                             &ns->eth.tx_broadcast);
2621         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2622                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2623
2624         /* exclude internal tx bytes
2625          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2626          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2627          * value.
2628          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2629          */
2630         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2631                 ns->eth.tx_bytes = 0;
2632         else
2633                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2634
2635         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2636                 ns->eth.tx_unicast = 0;
2637         else
2638                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2639
2640         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2641                 ns->eth.tx_multicast = 0;
2642         else
2643                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2644
2645         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2646                 ns->eth.tx_broadcast = 0;
2647         else
2648                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2649
2650         /* GLPRT_TEPC not supported */
2651
2652         /* additional port specific stats */
2653         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2654                             pf->offset_loaded, &os->tx_dropped_link_down,
2655                             &ns->tx_dropped_link_down);
2656         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2657                             pf->offset_loaded, &os->crc_errors,
2658                             &ns->crc_errors);
2659         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2660                             pf->offset_loaded, &os->illegal_bytes,
2661                             &ns->illegal_bytes);
2662         /* GLPRT_ERRBC not supported */
2663         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2664                             pf->offset_loaded, &os->mac_local_faults,
2665                             &ns->mac_local_faults);
2666         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2667                             pf->offset_loaded, &os->mac_remote_faults,
2668                             &ns->mac_remote_faults);
2669         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2670                             pf->offset_loaded, &os->rx_length_errors,
2671                             &ns->rx_length_errors);
2672         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2673                             pf->offset_loaded, &os->link_xon_rx,
2674                             &ns->link_xon_rx);
2675         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2676                             pf->offset_loaded, &os->link_xoff_rx,
2677                             &ns->link_xoff_rx);
2678         for (i = 0; i < 8; i++) {
2679                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2680                                     pf->offset_loaded,
2681                                     &os->priority_xon_rx[i],
2682                                     &ns->priority_xon_rx[i]);
2683                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2684                                     pf->offset_loaded,
2685                                     &os->priority_xoff_rx[i],
2686                                     &ns->priority_xoff_rx[i]);
2687         }
2688         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2689                             pf->offset_loaded, &os->link_xon_tx,
2690                             &ns->link_xon_tx);
2691         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2692                             pf->offset_loaded, &os->link_xoff_tx,
2693                             &ns->link_xoff_tx);
2694         for (i = 0; i < 8; i++) {
2695                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2696                                     pf->offset_loaded,
2697                                     &os->priority_xon_tx[i],
2698                                     &ns->priority_xon_tx[i]);
2699                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2700                                     pf->offset_loaded,
2701                                     &os->priority_xoff_tx[i],
2702                                     &ns->priority_xoff_tx[i]);
2703                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2704                                     pf->offset_loaded,
2705                                     &os->priority_xon_2_xoff[i],
2706                                     &ns->priority_xon_2_xoff[i]);
2707         }
2708         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2709                             I40E_GLPRT_PRC64L(hw->port),
2710                             pf->offset_loaded, &os->rx_size_64,
2711                             &ns->rx_size_64);
2712         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2713                             I40E_GLPRT_PRC127L(hw->port),
2714                             pf->offset_loaded, &os->rx_size_127,
2715                             &ns->rx_size_127);
2716         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2717                             I40E_GLPRT_PRC255L(hw->port),
2718                             pf->offset_loaded, &os->rx_size_255,
2719                             &ns->rx_size_255);
2720         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2721                             I40E_GLPRT_PRC511L(hw->port),
2722                             pf->offset_loaded, &os->rx_size_511,
2723                             &ns->rx_size_511);
2724         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2725                             I40E_GLPRT_PRC1023L(hw->port),
2726                             pf->offset_loaded, &os->rx_size_1023,
2727                             &ns->rx_size_1023);
2728         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2729                             I40E_GLPRT_PRC1522L(hw->port),
2730                             pf->offset_loaded, &os->rx_size_1522,
2731                             &ns->rx_size_1522);
2732         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2733                             I40E_GLPRT_PRC9522L(hw->port),
2734                             pf->offset_loaded, &os->rx_size_big,
2735                             &ns->rx_size_big);
2736         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2737                             pf->offset_loaded, &os->rx_undersize,
2738                             &ns->rx_undersize);
2739         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2740                             pf->offset_loaded, &os->rx_fragments,
2741                             &ns->rx_fragments);
2742         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2743                             pf->offset_loaded, &os->rx_oversize,
2744                             &ns->rx_oversize);
2745         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2746                             pf->offset_loaded, &os->rx_jabber,
2747                             &ns->rx_jabber);
2748         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2749                             I40E_GLPRT_PTC64L(hw->port),
2750                             pf->offset_loaded, &os->tx_size_64,
2751                             &ns->tx_size_64);
2752         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2753                             I40E_GLPRT_PTC127L(hw->port),
2754                             pf->offset_loaded, &os->tx_size_127,
2755                             &ns->tx_size_127);
2756         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2757                             I40E_GLPRT_PTC255L(hw->port),
2758                             pf->offset_loaded, &os->tx_size_255,
2759                             &ns->tx_size_255);
2760         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2761                             I40E_GLPRT_PTC511L(hw->port),
2762                             pf->offset_loaded, &os->tx_size_511,
2763                             &ns->tx_size_511);
2764         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2765                             I40E_GLPRT_PTC1023L(hw->port),
2766                             pf->offset_loaded, &os->tx_size_1023,
2767                             &ns->tx_size_1023);
2768         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2769                             I40E_GLPRT_PTC1522L(hw->port),
2770                             pf->offset_loaded, &os->tx_size_1522,
2771                             &ns->tx_size_1522);
2772         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2773                             I40E_GLPRT_PTC9522L(hw->port),
2774                             pf->offset_loaded, &os->tx_size_big,
2775                             &ns->tx_size_big);
2776         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2777                            pf->offset_loaded,
2778                            &os->fd_sb_match, &ns->fd_sb_match);
2779         /* GLPRT_MSPDC not supported */
2780         /* GLPRT_XEC not supported */
2781
2782         pf->offset_loaded = true;
2783
2784         if (pf->main_vsi)
2785                 i40e_update_vsi_stats(pf->main_vsi);
2786 }
2787
2788 /* Get all statistics of a port */
2789 static int
2790 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2791 {
2792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2793         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2794         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2795         unsigned i;
2796
2797         /* call read registers - updates values, now write them to struct */
2798         i40e_read_stats_registers(pf, hw);
2799
2800         stats->ipackets = ns->eth.rx_unicast +
2801                         ns->eth.rx_multicast +
2802                         ns->eth.rx_broadcast -
2803                         ns->eth.rx_discards -
2804                         pf->main_vsi->eth_stats.rx_discards;
2805         stats->opackets = ns->eth.tx_unicast +
2806                         ns->eth.tx_multicast +
2807                         ns->eth.tx_broadcast;
2808         stats->ibytes   = ns->eth.rx_bytes;
2809         stats->obytes   = ns->eth.tx_bytes;
2810         stats->oerrors  = ns->eth.tx_errors +
2811                         pf->main_vsi->eth_stats.tx_errors;
2812
2813         /* Rx Errors */
2814         stats->imissed  = ns->eth.rx_discards +
2815                         pf->main_vsi->eth_stats.rx_discards;
2816         stats->ierrors  = ns->crc_errors +
2817                         ns->rx_length_errors + ns->rx_undersize +
2818                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2819
2820         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2821         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2822         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2823         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2824         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2825         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2826         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2827                     ns->eth.rx_unknown_protocol);
2828         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2829         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2830         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2831         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2832         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2833         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2834
2835         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2836                     ns->tx_dropped_link_down);
2837         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2838         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2839                     ns->illegal_bytes);
2840         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2841         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2842                     ns->mac_local_faults);
2843         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2844                     ns->mac_remote_faults);
2845         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2846                     ns->rx_length_errors);
2847         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2848         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2849         for (i = 0; i < 8; i++) {
2850                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2851                                 i, ns->priority_xon_rx[i]);
2852                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2853                                 i, ns->priority_xoff_rx[i]);
2854         }
2855         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2856         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2857         for (i = 0; i < 8; i++) {
2858                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2859                                 i, ns->priority_xon_tx[i]);
2860                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2861                                 i, ns->priority_xoff_tx[i]);
2862                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2863                                 i, ns->priority_xon_2_xoff[i]);
2864         }
2865         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2866         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2867         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2868         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2869         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2870         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2871         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2872         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2873         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2874         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2875         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2876         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2877         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2878         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2879         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2880         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2881         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2882         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2883         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2884                         ns->mac_short_packet_dropped);
2885         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2886                     ns->checksum_error);
2887         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2888         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2889         return 0;
2890 }
2891
2892 /* Reset the statistics */
2893 static void
2894 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2895 {
2896         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898
2899         /* Mark PF and VSI stats to update the offset, aka "reset" */
2900         pf->offset_loaded = false;
2901         if (pf->main_vsi)
2902                 pf->main_vsi->offset_loaded = false;
2903
2904         /* read the stats, reading current register values into offset */
2905         i40e_read_stats_registers(pf, hw);
2906 }
2907
2908 static uint32_t
2909 i40e_xstats_calc_num(void)
2910 {
2911         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2912                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2913                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2914 }
2915
2916 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2917                                      struct rte_eth_xstat_name *xstats_names,
2918                                      __rte_unused unsigned limit)
2919 {
2920         unsigned count = 0;
2921         unsigned i, prio;
2922
2923         if (xstats_names == NULL)
2924                 return i40e_xstats_calc_num();
2925
2926         /* Note: limit checked in rte_eth_xstats_names() */
2927
2928         /* Get stats from i40e_eth_stats struct */
2929         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2930                 snprintf(xstats_names[count].name,
2931                          sizeof(xstats_names[count].name),
2932                          "%s", rte_i40e_stats_strings[i].name);
2933                 count++;
2934         }
2935
2936         /* Get individiual stats from i40e_hw_port struct */
2937         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2938                 snprintf(xstats_names[count].name,
2939                         sizeof(xstats_names[count].name),
2940                          "%s", rte_i40e_hw_port_strings[i].name);
2941                 count++;
2942         }
2943
2944         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2945                 for (prio = 0; prio < 8; prio++) {
2946                         snprintf(xstats_names[count].name,
2947                                  sizeof(xstats_names[count].name),
2948                                  "rx_priority%u_%s", prio,
2949                                  rte_i40e_rxq_prio_strings[i].name);
2950                         count++;
2951                 }
2952         }
2953
2954         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2955                 for (prio = 0; prio < 8; prio++) {
2956                         snprintf(xstats_names[count].name,
2957                                  sizeof(xstats_names[count].name),
2958                                  "tx_priority%u_%s", prio,
2959                                  rte_i40e_txq_prio_strings[i].name);
2960                         count++;
2961                 }
2962         }
2963         return count;
2964 }
2965
2966 static int
2967 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2968                     unsigned n)
2969 {
2970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         unsigned i, count, prio;
2973         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2974
2975         count = i40e_xstats_calc_num();
2976         if (n < count)
2977                 return count;
2978
2979         i40e_read_stats_registers(pf, hw);
2980
2981         if (xstats == NULL)
2982                 return 0;
2983
2984         count = 0;
2985
2986         /* Get stats from i40e_eth_stats struct */
2987         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2988                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2989                         rte_i40e_stats_strings[i].offset);
2990                 xstats[count].id = count;
2991                 count++;
2992         }
2993
2994         /* Get individiual stats from i40e_hw_port struct */
2995         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2996                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2997                         rte_i40e_hw_port_strings[i].offset);
2998                 xstats[count].id = count;
2999                 count++;
3000         }
3001
3002         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3003                 for (prio = 0; prio < 8; prio++) {
3004                         xstats[count].value =
3005                                 *(uint64_t *)(((char *)hw_stats) +
3006                                 rte_i40e_rxq_prio_strings[i].offset +
3007                                 (sizeof(uint64_t) * prio));
3008                         xstats[count].id = count;
3009                         count++;
3010                 }
3011         }
3012
3013         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3014                 for (prio = 0; prio < 8; prio++) {
3015                         xstats[count].value =
3016                                 *(uint64_t *)(((char *)hw_stats) +
3017                                 rte_i40e_txq_prio_strings[i].offset +
3018                                 (sizeof(uint64_t) * prio));
3019                         xstats[count].id = count;
3020                         count++;
3021                 }
3022         }
3023
3024         return count;
3025 }
3026
3027 static int
3028 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3029                                  __rte_unused uint16_t queue_id,
3030                                  __rte_unused uint8_t stat_idx,
3031                                  __rte_unused uint8_t is_rx)
3032 {
3033         PMD_INIT_FUNC_TRACE();
3034
3035         return -ENOSYS;
3036 }
3037
3038 static int
3039 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3040 {
3041         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3042         u32 full_ver;
3043         u8 ver, patch;
3044         u16 build;
3045         int ret;
3046
3047         full_ver = hw->nvm.oem_ver;
3048         ver = (u8)(full_ver >> 24);
3049         build = (u16)((full_ver >> 8) & 0xffff);
3050         patch = (u8)(full_ver & 0xff);
3051
3052         ret = snprintf(fw_version, fw_size,
3053                  "%d.%d%d 0x%08x %d.%d.%d",
3054                  ((hw->nvm.version >> 12) & 0xf),
3055                  ((hw->nvm.version >> 4) & 0xff),
3056                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3057                  ver, build, patch);
3058
3059         ret += 1; /* add the size of '\0' */
3060         if (fw_size < (u32)ret)
3061                 return ret;
3062         else
3063                 return 0;
3064 }
3065
3066 static void
3067 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3068 {
3069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3070         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3071         struct i40e_vsi *vsi = pf->main_vsi;
3072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3073
3074         dev_info->pci_dev = pci_dev;
3075         dev_info->max_rx_queues = vsi->nb_qps;
3076         dev_info->max_tx_queues = vsi->nb_qps;
3077         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3078         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3079         dev_info->max_mac_addrs = vsi->max_macaddrs;
3080         dev_info->max_vfs = pci_dev->max_vfs;
3081         dev_info->rx_offload_capa =
3082                 DEV_RX_OFFLOAD_VLAN_STRIP |
3083                 DEV_RX_OFFLOAD_QINQ_STRIP |
3084                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3085                 DEV_RX_OFFLOAD_UDP_CKSUM |
3086                 DEV_RX_OFFLOAD_TCP_CKSUM |
3087                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3088                 DEV_RX_OFFLOAD_CRC_STRIP;
3089         dev_info->tx_offload_capa =
3090                 DEV_TX_OFFLOAD_VLAN_INSERT |
3091                 DEV_TX_OFFLOAD_QINQ_INSERT |
3092                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3093                 DEV_TX_OFFLOAD_UDP_CKSUM |
3094                 DEV_TX_OFFLOAD_TCP_CKSUM |
3095                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3096                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3097                 DEV_TX_OFFLOAD_TCP_TSO |
3098                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3099                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3100                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3101                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3102         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3103                                                 sizeof(uint32_t);
3104         dev_info->reta_size = pf->hash_lut_size;
3105         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3106
3107         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3108                 .rx_thresh = {
3109                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3110                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3111                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3112                 },
3113                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3114                 .rx_drop_en = 0,
3115         };
3116
3117         dev_info->default_txconf = (struct rte_eth_txconf) {
3118                 .tx_thresh = {
3119                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3120                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3121                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3122                 },
3123                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3124                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3125                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3126                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3127         };
3128
3129         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3130                 .nb_max = I40E_MAX_RING_DESC,
3131                 .nb_min = I40E_MIN_RING_DESC,
3132                 .nb_align = I40E_ALIGN_RING_DESC,
3133         };
3134
3135         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3136                 .nb_max = I40E_MAX_RING_DESC,
3137                 .nb_min = I40E_MIN_RING_DESC,
3138                 .nb_align = I40E_ALIGN_RING_DESC,
3139                 .nb_seg_max = I40E_TX_MAX_SEG,
3140                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3141         };
3142
3143         if (pf->flags & I40E_FLAG_VMDQ) {
3144                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3145                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3146                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3147                                                 pf->max_nb_vmdq_vsi;
3148                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3149                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3150                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3151         }
3152
3153         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3154                 /* For XL710 */
3155                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3156         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3157                 /* For XXV710 */
3158                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3159         else
3160                 /* For X710 */
3161                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3162 }
3163
3164 static int
3165 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3166 {
3167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168         struct i40e_vsi *vsi = pf->main_vsi;
3169         PMD_INIT_FUNC_TRACE();
3170
3171         if (on)
3172                 return i40e_vsi_add_vlan(vsi, vlan_id);
3173         else
3174                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3175 }
3176
3177 static int
3178 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3179                                 enum rte_vlan_type vlan_type,
3180                                 uint16_t tpid, int qinq)
3181 {
3182         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3183         uint64_t reg_r = 0;
3184         uint64_t reg_w = 0;
3185         uint16_t reg_id = 3;
3186         int ret;
3187
3188         if (qinq) {
3189                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3190                         reg_id = 2;
3191         }
3192
3193         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3194                                           &reg_r, NULL);
3195         if (ret != I40E_SUCCESS) {
3196                 PMD_DRV_LOG(ERR,
3197                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3198                            reg_id);
3199                 return -EIO;
3200         }
3201         PMD_DRV_LOG(DEBUG,
3202                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3203                     reg_id, reg_r);
3204
3205         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3206         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3207         if (reg_r == reg_w) {
3208                 PMD_DRV_LOG(DEBUG, "No need to write");
3209                 return 0;
3210         }
3211
3212         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3213                                            reg_w, NULL);
3214         if (ret != I40E_SUCCESS) {
3215                 PMD_DRV_LOG(ERR,
3216                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3217                             reg_id);
3218                 return -EIO;
3219         }
3220         PMD_DRV_LOG(DEBUG,
3221                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3222                     reg_w, reg_id);
3223
3224         return 0;
3225 }
3226
3227 static int
3228 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3229                    enum rte_vlan_type vlan_type,
3230                    uint16_t tpid)
3231 {
3232         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3233         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3234         int ret = 0;
3235
3236         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3237              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3238             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3239                 PMD_DRV_LOG(ERR,
3240                             "Unsupported vlan type.");
3241                 return -EINVAL;
3242         }
3243         /* 802.1ad frames ability is added in NVM API 1.7*/
3244         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3245                 if (qinq) {
3246                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3247                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3248                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3249                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3250                 } else {
3251                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3252                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3253                 }
3254                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3255                 if (ret != I40E_SUCCESS) {
3256                         PMD_DRV_LOG(ERR,
3257                                     "Set switch config failed aq_err: %d",
3258                                     hw->aq.asq_last_status);
3259                         ret = -EIO;
3260                 }
3261         } else
3262                 /* If NVM API < 1.7, keep the register setting */
3263                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3264                                                       tpid, qinq);
3265
3266         return ret;
3267 }
3268
3269 static int
3270 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3271 {
3272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273         struct i40e_vsi *vsi = pf->main_vsi;
3274
3275         if (mask & ETH_VLAN_FILTER_MASK) {
3276                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3277                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3278                 else
3279                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3280         }
3281
3282         if (mask & ETH_VLAN_STRIP_MASK) {
3283                 /* Enable or disable VLAN stripping */
3284                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3285                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3286                 else
3287                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3288         }
3289
3290         if (mask & ETH_VLAN_EXTEND_MASK) {
3291                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3292                         i40e_vsi_config_double_vlan(vsi, TRUE);
3293                         /* Set global registers with default ethertype. */
3294                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3295                                            ETHER_TYPE_VLAN);
3296                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3297                                            ETHER_TYPE_VLAN);
3298                 }
3299                 else
3300                         i40e_vsi_config_double_vlan(vsi, FALSE);
3301         }
3302
3303         return 0;
3304 }
3305
3306 static void
3307 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3308                           __rte_unused uint16_t queue,
3309                           __rte_unused int on)
3310 {
3311         PMD_INIT_FUNC_TRACE();
3312 }
3313
3314 static int
3315 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3316 {
3317         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318         struct i40e_vsi *vsi = pf->main_vsi;
3319         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3320         struct i40e_vsi_vlan_pvid_info info;
3321
3322         memset(&info, 0, sizeof(info));
3323         info.on = on;
3324         if (info.on)
3325                 info.config.pvid = pvid;
3326         else {
3327                 info.config.reject.tagged =
3328                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3329                 info.config.reject.untagged =
3330                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3331         }
3332
3333         return i40e_vsi_vlan_pvid_set(vsi, &info);
3334 }
3335
3336 static int
3337 i40e_dev_led_on(struct rte_eth_dev *dev)
3338 {
3339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340         uint32_t mode = i40e_led_get(hw);
3341
3342         if (mode == 0)
3343                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3344
3345         return 0;
3346 }
3347
3348 static int
3349 i40e_dev_led_off(struct rte_eth_dev *dev)
3350 {
3351         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3352         uint32_t mode = i40e_led_get(hw);
3353
3354         if (mode != 0)
3355                 i40e_led_set(hw, 0, false);
3356
3357         return 0;
3358 }
3359
3360 static int
3361 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3362 {
3363         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3365
3366         fc_conf->pause_time = pf->fc_conf.pause_time;
3367
3368         /* read out from register, in case they are modified by other port */
3369         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3370                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3371         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3372                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3373
3374         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3375         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3376
3377          /* Return current mode according to actual setting*/
3378         switch (hw->fc.current_mode) {
3379         case I40E_FC_FULL:
3380                 fc_conf->mode = RTE_FC_FULL;
3381                 break;
3382         case I40E_FC_TX_PAUSE:
3383                 fc_conf->mode = RTE_FC_TX_PAUSE;
3384                 break;
3385         case I40E_FC_RX_PAUSE:
3386                 fc_conf->mode = RTE_FC_RX_PAUSE;
3387                 break;
3388         case I40E_FC_NONE:
3389         default:
3390                 fc_conf->mode = RTE_FC_NONE;
3391         };
3392
3393         return 0;
3394 }
3395
3396 static int
3397 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3398 {
3399         uint32_t mflcn_reg, fctrl_reg, reg;
3400         uint32_t max_high_water;
3401         uint8_t i, aq_failure;
3402         int err;
3403         struct i40e_hw *hw;
3404         struct i40e_pf *pf;
3405         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3406                 [RTE_FC_NONE] = I40E_FC_NONE,
3407                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3408                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3409                 [RTE_FC_FULL] = I40E_FC_FULL
3410         };
3411
3412         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3413
3414         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3415         if ((fc_conf->high_water > max_high_water) ||
3416                         (fc_conf->high_water < fc_conf->low_water)) {
3417                 PMD_INIT_LOG(ERR,
3418                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3419                         max_high_water);
3420                 return -EINVAL;
3421         }
3422
3423         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3425         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3426
3427         pf->fc_conf.pause_time = fc_conf->pause_time;
3428         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3429         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3430
3431         PMD_INIT_FUNC_TRACE();
3432
3433         /* All the link flow control related enable/disable register
3434          * configuration is handle by the F/W
3435          */
3436         err = i40e_set_fc(hw, &aq_failure, true);
3437         if (err < 0)
3438                 return -ENOSYS;
3439
3440         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3441                 /* Configure flow control refresh threshold,
3442                  * the value for stat_tx_pause_refresh_timer[8]
3443                  * is used for global pause operation.
3444                  */
3445
3446                 I40E_WRITE_REG(hw,
3447                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3448                                pf->fc_conf.pause_time);
3449
3450                 /* configure the timer value included in transmitted pause
3451                  * frame,
3452                  * the value for stat_tx_pause_quanta[8] is used for global
3453                  * pause operation
3454                  */
3455                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3456                                pf->fc_conf.pause_time);
3457
3458                 fctrl_reg = I40E_READ_REG(hw,
3459                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3460
3461                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3462                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3463                 else
3464                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3465
3466                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3467                                fctrl_reg);
3468         } else {
3469                 /* Configure pause time (2 TCs per register) */
3470                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3471                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3472                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3473
3474                 /* Configure flow control refresh threshold value */
3475                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3476                                pf->fc_conf.pause_time / 2);
3477
3478                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3479
3480                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3481                  *depending on configuration
3482                  */
3483                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3484                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3485                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3486                 } else {
3487                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3488                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3489                 }
3490
3491                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3492         }
3493
3494         /* config the water marker both based on the packets and bytes */
3495         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3496                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3497                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3498         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3499                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3500                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3501         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3502                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3503                        << I40E_KILOSHIFT);
3504         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3505                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3506                        << I40E_KILOSHIFT);
3507
3508         I40E_WRITE_FLUSH(hw);
3509
3510         return 0;
3511 }
3512
3513 static int
3514 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3515                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3516 {
3517         PMD_INIT_FUNC_TRACE();
3518
3519         return -ENOSYS;
3520 }
3521
3522 /* Add a MAC address, and update filters */
3523 static int
3524 i40e_macaddr_add(struct rte_eth_dev *dev,
3525                  struct ether_addr *mac_addr,
3526                  __rte_unused uint32_t index,
3527                  uint32_t pool)
3528 {
3529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530         struct i40e_mac_filter_info mac_filter;
3531         struct i40e_vsi *vsi;
3532         int ret;
3533
3534         /* If VMDQ not enabled or configured, return */
3535         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3536                           !pf->nb_cfg_vmdq_vsi)) {
3537                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3538                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3539                         pool);
3540                 return -ENOTSUP;
3541         }
3542
3543         if (pool > pf->nb_cfg_vmdq_vsi) {
3544                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3545                                 pool, pf->nb_cfg_vmdq_vsi);
3546                 return -EINVAL;
3547         }
3548
3549         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3550         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3551                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3552         else
3553                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3554
3555         if (pool == 0)
3556                 vsi = pf->main_vsi;
3557         else
3558                 vsi = pf->vmdq[pool - 1].vsi;
3559
3560         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3561         if (ret != I40E_SUCCESS) {
3562                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3563                 return -ENODEV;
3564         }
3565         return 0;
3566 }
3567
3568 /* Remove a MAC address, and update filters */
3569 static void
3570 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3571 {
3572         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3573         struct i40e_vsi *vsi;
3574         struct rte_eth_dev_data *data = dev->data;
3575         struct ether_addr *macaddr;
3576         int ret;
3577         uint32_t i;
3578         uint64_t pool_sel;
3579
3580         macaddr = &(data->mac_addrs[index]);
3581
3582         pool_sel = dev->data->mac_pool_sel[index];
3583
3584         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3585                 if (pool_sel & (1ULL << i)) {
3586                         if (i == 0)
3587                                 vsi = pf->main_vsi;
3588                         else {
3589                                 /* No VMDQ pool enabled or configured */
3590                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3591                                         (i > pf->nb_cfg_vmdq_vsi)) {
3592                                         PMD_DRV_LOG(ERR,
3593                                                 "No VMDQ pool enabled/configured");
3594                                         return;
3595                                 }
3596                                 vsi = pf->vmdq[i - 1].vsi;
3597                         }
3598                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3599
3600                         if (ret) {
3601                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3602                                 return;
3603                         }
3604                 }
3605         }
3606 }
3607
3608 /* Set perfect match or hash match of MAC and VLAN for a VF */
3609 static int
3610 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3611                  struct rte_eth_mac_filter *filter,
3612                  bool add)
3613 {
3614         struct i40e_hw *hw;
3615         struct i40e_mac_filter_info mac_filter;
3616         struct ether_addr old_mac;
3617         struct ether_addr *new_mac;
3618         struct i40e_pf_vf *vf = NULL;
3619         uint16_t vf_id;
3620         int ret;
3621
3622         if (pf == NULL) {
3623                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3624                 return -EINVAL;
3625         }
3626         hw = I40E_PF_TO_HW(pf);
3627
3628         if (filter == NULL) {
3629                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3630                 return -EINVAL;
3631         }
3632
3633         new_mac = &filter->mac_addr;
3634
3635         if (is_zero_ether_addr(new_mac)) {
3636                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3637                 return -EINVAL;
3638         }
3639
3640         vf_id = filter->dst_id;
3641
3642         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3643                 PMD_DRV_LOG(ERR, "Invalid argument.");
3644                 return -EINVAL;
3645         }
3646         vf = &pf->vfs[vf_id];
3647
3648         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3649                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3650                 return -EINVAL;
3651         }
3652
3653         if (add) {
3654                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3655                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3656                                 ETHER_ADDR_LEN);
3657                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3658                                  ETHER_ADDR_LEN);
3659
3660                 mac_filter.filter_type = filter->filter_type;
3661                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3662                 if (ret != I40E_SUCCESS) {
3663                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3664                         return -1;
3665                 }
3666                 ether_addr_copy(new_mac, &pf->dev_addr);
3667         } else {
3668                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3669                                 ETHER_ADDR_LEN);
3670                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3671                 if (ret != I40E_SUCCESS) {
3672                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3673                         return -1;
3674                 }
3675
3676                 /* Clear device address as it has been removed */
3677                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3678                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3679         }
3680
3681         return 0;
3682 }
3683
3684 /* MAC filter handle */
3685 static int
3686 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3687                 void *arg)
3688 {
3689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3690         struct rte_eth_mac_filter *filter;
3691         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3692         int ret = I40E_NOT_SUPPORTED;
3693
3694         filter = (struct rte_eth_mac_filter *)(arg);
3695
3696         switch (filter_op) {
3697         case RTE_ETH_FILTER_NOP:
3698                 ret = I40E_SUCCESS;
3699                 break;
3700         case RTE_ETH_FILTER_ADD:
3701                 i40e_pf_disable_irq0(hw);
3702                 if (filter->is_vf)
3703                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3704                 i40e_pf_enable_irq0(hw);
3705                 break;
3706         case RTE_ETH_FILTER_DELETE:
3707                 i40e_pf_disable_irq0(hw);
3708                 if (filter->is_vf)
3709                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3710                 i40e_pf_enable_irq0(hw);
3711                 break;
3712         default:
3713                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3714                 ret = I40E_ERR_PARAM;
3715                 break;
3716         }
3717
3718         return ret;
3719 }
3720
3721 static int
3722 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3723 {
3724         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3725         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3726         uint32_t reg;
3727         int ret;
3728
3729         if (!lut)
3730                 return -EINVAL;
3731
3732         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3733                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3734                                           lut, lut_size);
3735                 if (ret) {
3736                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3737                         return ret;
3738                 }
3739         } else {
3740                 uint32_t *lut_dw = (uint32_t *)lut;
3741                 uint16_t i, lut_size_dw = lut_size / 4;
3742
3743                 if (vsi->type == I40E_VSI_SRIOV) {
3744                         for (i = 0; i <= lut_size_dw; i++) {
3745                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3746                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3747                         }
3748                 } else {
3749                         for (i = 0; i < lut_size_dw; i++)
3750                                 lut_dw[i] = I40E_READ_REG(hw,
3751                                                           I40E_PFQF_HLUT(i));
3752                 }
3753         }
3754
3755         return 0;
3756 }
3757
3758 int
3759 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3760 {
3761         struct i40e_pf *pf;
3762         struct i40e_hw *hw;
3763         int ret;
3764
3765         if (!vsi || !lut)
3766                 return -EINVAL;
3767
3768         pf = I40E_VSI_TO_PF(vsi);
3769         hw = I40E_VSI_TO_HW(vsi);
3770
3771         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3772                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3773                                           lut, lut_size);
3774                 if (ret) {
3775                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3776                         return ret;
3777                 }
3778         } else {
3779                 uint32_t *lut_dw = (uint32_t *)lut;
3780                 uint16_t i, lut_size_dw = lut_size / 4;
3781
3782                 if (vsi->type == I40E_VSI_SRIOV) {
3783                         for (i = 0; i < lut_size_dw; i++)
3784                                 I40E_WRITE_REG(
3785                                         hw,
3786                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3787                                         lut_dw[i]);
3788                 } else {
3789                         for (i = 0; i < lut_size_dw; i++)
3790                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3791                                                lut_dw[i]);
3792                 }
3793                 I40E_WRITE_FLUSH(hw);
3794         }
3795
3796         return 0;
3797 }
3798
3799 static int
3800 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3801                          struct rte_eth_rss_reta_entry64 *reta_conf,
3802                          uint16_t reta_size)
3803 {
3804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3805         uint16_t i, lut_size = pf->hash_lut_size;
3806         uint16_t idx, shift;
3807         uint8_t *lut;
3808         int ret;
3809
3810         if (reta_size != lut_size ||
3811                 reta_size > ETH_RSS_RETA_SIZE_512) {
3812                 PMD_DRV_LOG(ERR,
3813                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3814                         reta_size, lut_size);
3815                 return -EINVAL;
3816         }
3817
3818         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3819         if (!lut) {
3820                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3821                 return -ENOMEM;
3822         }
3823         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3824         if (ret)
3825                 goto out;
3826         for (i = 0; i < reta_size; i++) {
3827                 idx = i / RTE_RETA_GROUP_SIZE;
3828                 shift = i % RTE_RETA_GROUP_SIZE;
3829                 if (reta_conf[idx].mask & (1ULL << shift))
3830                         lut[i] = reta_conf[idx].reta[shift];
3831         }
3832         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3833
3834 out:
3835         rte_free(lut);
3836
3837         return ret;
3838 }
3839
3840 static int
3841 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3842                         struct rte_eth_rss_reta_entry64 *reta_conf,
3843                         uint16_t reta_size)
3844 {
3845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846         uint16_t i, lut_size = pf->hash_lut_size;
3847         uint16_t idx, shift;
3848         uint8_t *lut;
3849         int ret;
3850
3851         if (reta_size != lut_size ||
3852                 reta_size > ETH_RSS_RETA_SIZE_512) {
3853                 PMD_DRV_LOG(ERR,
3854                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3855                         reta_size, lut_size);
3856                 return -EINVAL;
3857         }
3858
3859         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3860         if (!lut) {
3861                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3862                 return -ENOMEM;
3863         }
3864
3865         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3866         if (ret)
3867                 goto out;
3868         for (i = 0; i < reta_size; i++) {
3869                 idx = i / RTE_RETA_GROUP_SIZE;
3870                 shift = i % RTE_RETA_GROUP_SIZE;
3871                 if (reta_conf[idx].mask & (1ULL << shift))
3872                         reta_conf[idx].reta[shift] = lut[i];
3873         }
3874
3875 out:
3876         rte_free(lut);
3877
3878         return ret;
3879 }
3880
3881 /**
3882  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3883  * @hw:   pointer to the HW structure
3884  * @mem:  pointer to mem struct to fill out
3885  * @size: size of memory requested
3886  * @alignment: what to align the allocation to
3887  **/
3888 enum i40e_status_code
3889 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3890                         struct i40e_dma_mem *mem,
3891                         u64 size,
3892                         u32 alignment)
3893 {
3894         const struct rte_memzone *mz = NULL;
3895         char z_name[RTE_MEMZONE_NAMESIZE];
3896
3897         if (!mem)
3898                 return I40E_ERR_PARAM;
3899
3900         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3901         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3902                                          alignment, RTE_PGSIZE_2M);
3903         if (!mz)
3904                 return I40E_ERR_NO_MEMORY;
3905
3906         mem->size = size;
3907         mem->va = mz->addr;
3908         mem->pa = mz->iova;
3909         mem->zone = (const void *)mz;
3910         PMD_DRV_LOG(DEBUG,
3911                 "memzone %s allocated with physical address: %"PRIu64,
3912                 mz->name, mem->pa);
3913
3914         return I40E_SUCCESS;
3915 }
3916
3917 /**
3918  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3919  * @hw:   pointer to the HW structure
3920  * @mem:  ptr to mem struct to free
3921  **/
3922 enum i40e_status_code
3923 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3924                     struct i40e_dma_mem *mem)
3925 {
3926         if (!mem)
3927                 return I40E_ERR_PARAM;
3928
3929         PMD_DRV_LOG(DEBUG,
3930                 "memzone %s to be freed with physical address: %"PRIu64,
3931                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3932         rte_memzone_free((const struct rte_memzone *)mem->zone);
3933         mem->zone = NULL;
3934         mem->va = NULL;
3935         mem->pa = (u64)0;
3936
3937         return I40E_SUCCESS;
3938 }
3939
3940 /**
3941  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3942  * @hw:   pointer to the HW structure
3943  * @mem:  pointer to mem struct to fill out
3944  * @size: size of memory requested
3945  **/
3946 enum i40e_status_code
3947 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3948                          struct i40e_virt_mem *mem,
3949                          u32 size)
3950 {
3951         if (!mem)
3952                 return I40E_ERR_PARAM;
3953
3954         mem->size = size;
3955         mem->va = rte_zmalloc("i40e", size, 0);
3956
3957         if (mem->va)
3958                 return I40E_SUCCESS;
3959         else
3960                 return I40E_ERR_NO_MEMORY;
3961 }
3962
3963 /**
3964  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3965  * @hw:   pointer to the HW structure
3966  * @mem:  pointer to mem struct to free
3967  **/
3968 enum i40e_status_code
3969 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3970                      struct i40e_virt_mem *mem)
3971 {
3972         if (!mem)
3973                 return I40E_ERR_PARAM;
3974
3975         rte_free(mem->va);
3976         mem->va = NULL;
3977
3978         return I40E_SUCCESS;
3979 }
3980
3981 void
3982 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3983 {
3984         rte_spinlock_init(&sp->spinlock);
3985 }
3986
3987 void
3988 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3989 {
3990         rte_spinlock_lock(&sp->spinlock);
3991 }
3992
3993 void
3994 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3995 {
3996         rte_spinlock_unlock(&sp->spinlock);
3997 }
3998
3999 void
4000 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4001 {
4002         return;
4003 }
4004
4005 /**
4006  * Get the hardware capabilities, which will be parsed
4007  * and saved into struct i40e_hw.
4008  */
4009 static int
4010 i40e_get_cap(struct i40e_hw *hw)
4011 {
4012         struct i40e_aqc_list_capabilities_element_resp *buf;
4013         uint16_t len, size = 0;
4014         int ret;
4015
4016         /* Calculate a huge enough buff for saving response data temporarily */
4017         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4018                                                 I40E_MAX_CAP_ELE_NUM;
4019         buf = rte_zmalloc("i40e", len, 0);
4020         if (!buf) {
4021                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4022                 return I40E_ERR_NO_MEMORY;
4023         }
4024
4025         /* Get, parse the capabilities and save it to hw */
4026         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4027                         i40e_aqc_opc_list_func_capabilities, NULL);
4028         if (ret != I40E_SUCCESS)
4029                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4030
4031         /* Free the temporary buffer after being used */
4032         rte_free(buf);
4033
4034         return ret;
4035 }
4036
4037 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4038 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4039 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4040
4041 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4042                 const char *value,
4043                 void *opaque)
4044 {
4045         struct i40e_pf *pf;
4046         unsigned long num;
4047         char *end;
4048
4049         pf = (struct i40e_pf *)opaque;
4050         RTE_SET_USED(key);
4051
4052         errno = 0;
4053         num = strtoul(value, &end, 0);
4054         if (errno != 0 || end == value || *end != 0) {
4055                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4056                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4057                 return -(EINVAL);
4058         }
4059
4060         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4061                 pf->vf_nb_qp_max = (uint16_t)num;
4062         else
4063                 /* here return 0 to make next valid same argument work */
4064                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4065                             "power of 2 and equal or less than 16 !, Now it is "
4066                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4067
4068         return 0;
4069 }
4070
4071 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4072 {
4073         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4074         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4075         struct rte_kvargs *kvlist;
4076
4077         /* set default queue number per VF as 4 */
4078         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4079
4080         if (dev->device->devargs == NULL)
4081                 return 0;
4082
4083         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4084         if (kvlist == NULL)
4085                 return -(EINVAL);
4086
4087         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4088                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4089                             "the first invalid or last valid one is used !",
4090                             QUEUE_NUM_PER_VF_ARG);
4091
4092         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4093                            i40e_pf_parse_vf_queue_number_handler, pf);
4094
4095         rte_kvargs_free(kvlist);
4096
4097         return 0;
4098 }
4099
4100 static int
4101 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4102 {
4103         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4104         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4106         uint16_t qp_count = 0, vsi_count = 0;
4107
4108         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4109                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4110                 return -EINVAL;
4111         }
4112
4113         i40e_pf_config_vf_rxq_number(dev);
4114
4115         /* Add the parameter init for LFC */
4116         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4117         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4118         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4119
4120         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4121         pf->max_num_vsi = hw->func_caps.num_vsis;
4122         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4123         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4124
4125         /* FDir queue/VSI allocation */
4126         pf->fdir_qp_offset = 0;
4127         if (hw->func_caps.fd) {
4128                 pf->flags |= I40E_FLAG_FDIR;
4129                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4130         } else {
4131                 pf->fdir_nb_qps = 0;
4132         }
4133         qp_count += pf->fdir_nb_qps;
4134         vsi_count += 1;
4135
4136         /* LAN queue/VSI allocation */
4137         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4138         if (!hw->func_caps.rss) {
4139                 pf->lan_nb_qps = 1;
4140         } else {
4141                 pf->flags |= I40E_FLAG_RSS;
4142                 if (hw->mac.type == I40E_MAC_X722)
4143                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4144                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4145         }
4146         qp_count += pf->lan_nb_qps;
4147         vsi_count += 1;
4148
4149         /* VF queue/VSI allocation */
4150         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4151         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4152                 pf->flags |= I40E_FLAG_SRIOV;
4153                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4154                 pf->vf_num = pci_dev->max_vfs;
4155                 PMD_DRV_LOG(DEBUG,
4156                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4157                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4158         } else {
4159                 pf->vf_nb_qps = 0;
4160                 pf->vf_num = 0;
4161         }
4162         qp_count += pf->vf_nb_qps * pf->vf_num;
4163         vsi_count += pf->vf_num;
4164
4165         /* VMDq queue/VSI allocation */
4166         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4167         pf->vmdq_nb_qps = 0;
4168         pf->max_nb_vmdq_vsi = 0;
4169         if (hw->func_caps.vmdq) {
4170                 if (qp_count < hw->func_caps.num_tx_qp &&
4171                         vsi_count < hw->func_caps.num_vsis) {
4172                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4173                                 qp_count) / pf->vmdq_nb_qp_max;
4174
4175                         /* Limit the maximum number of VMDq vsi to the maximum
4176                          * ethdev can support
4177                          */
4178                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4179                                 hw->func_caps.num_vsis - vsi_count);
4180                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4181                                 ETH_64_POOLS);
4182                         if (pf->max_nb_vmdq_vsi) {
4183                                 pf->flags |= I40E_FLAG_VMDQ;
4184                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4185                                 PMD_DRV_LOG(DEBUG,
4186                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4187                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4188                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4189                         } else {
4190                                 PMD_DRV_LOG(INFO,
4191                                         "No enough queues left for VMDq");
4192                         }
4193                 } else {
4194                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4195                 }
4196         }
4197         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4198         vsi_count += pf->max_nb_vmdq_vsi;
4199
4200         if (hw->func_caps.dcb)
4201                 pf->flags |= I40E_FLAG_DCB;
4202
4203         if (qp_count > hw->func_caps.num_tx_qp) {
4204                 PMD_DRV_LOG(ERR,
4205                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4206                         qp_count, hw->func_caps.num_tx_qp);
4207                 return -EINVAL;
4208         }
4209         if (vsi_count > hw->func_caps.num_vsis) {
4210                 PMD_DRV_LOG(ERR,
4211                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4212                         vsi_count, hw->func_caps.num_vsis);
4213                 return -EINVAL;
4214         }
4215
4216         return 0;
4217 }
4218
4219 static int
4220 i40e_pf_get_switch_config(struct i40e_pf *pf)
4221 {
4222         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4223         struct i40e_aqc_get_switch_config_resp *switch_config;
4224         struct i40e_aqc_switch_config_element_resp *element;
4225         uint16_t start_seid = 0, num_reported;
4226         int ret;
4227
4228         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4229                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4230         if (!switch_config) {
4231                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4232                 return -ENOMEM;
4233         }
4234
4235         /* Get the switch configurations */
4236         ret = i40e_aq_get_switch_config(hw, switch_config,
4237                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4238         if (ret != I40E_SUCCESS) {
4239                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4240                 goto fail;
4241         }
4242         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4243         if (num_reported != 1) { /* The number should be 1 */
4244                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4245                 goto fail;
4246         }
4247
4248         /* Parse the switch configuration elements */
4249         element = &(switch_config->element[0]);
4250         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4251                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4252                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4253         } else
4254                 PMD_DRV_LOG(INFO, "Unknown element type");
4255
4256 fail:
4257         rte_free(switch_config);
4258
4259         return ret;
4260 }
4261
4262 static int
4263 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4264                         uint32_t num)
4265 {
4266         struct pool_entry *entry;
4267
4268         if (pool == NULL || num == 0)
4269                 return -EINVAL;
4270
4271         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4272         if (entry == NULL) {
4273                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4274                 return -ENOMEM;
4275         }
4276
4277         /* queue heap initialize */
4278         pool->num_free = num;
4279         pool->num_alloc = 0;
4280         pool->base = base;
4281         LIST_INIT(&pool->alloc_list);
4282         LIST_INIT(&pool->free_list);
4283
4284         /* Initialize element  */
4285         entry->base = 0;
4286         entry->len = num;
4287
4288         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4289         return 0;
4290 }
4291
4292 static void
4293 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4294 {
4295         struct pool_entry *entry, *next_entry;
4296
4297         if (pool == NULL)
4298                 return;
4299
4300         for (entry = LIST_FIRST(&pool->alloc_list);
4301                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4302                         entry = next_entry) {
4303                 LIST_REMOVE(entry, next);
4304                 rte_free(entry);
4305         }
4306
4307         for (entry = LIST_FIRST(&pool->free_list);
4308                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4309                         entry = next_entry) {
4310                 LIST_REMOVE(entry, next);
4311                 rte_free(entry);
4312         }
4313
4314         pool->num_free = 0;
4315         pool->num_alloc = 0;
4316         pool->base = 0;
4317         LIST_INIT(&pool->alloc_list);
4318         LIST_INIT(&pool->free_list);
4319 }
4320
4321 static int
4322 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4323                        uint32_t base)
4324 {
4325         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4326         uint32_t pool_offset;
4327         int insert;
4328
4329         if (pool == NULL) {
4330                 PMD_DRV_LOG(ERR, "Invalid parameter");
4331                 return -EINVAL;
4332         }
4333
4334         pool_offset = base - pool->base;
4335         /* Lookup in alloc list */
4336         LIST_FOREACH(entry, &pool->alloc_list, next) {
4337                 if (entry->base == pool_offset) {
4338                         valid_entry = entry;
4339                         LIST_REMOVE(entry, next);
4340                         break;
4341                 }
4342         }
4343
4344         /* Not find, return */
4345         if (valid_entry == NULL) {
4346                 PMD_DRV_LOG(ERR, "Failed to find entry");
4347                 return -EINVAL;
4348         }
4349
4350         /**
4351          * Found it, move it to free list  and try to merge.
4352          * In order to make merge easier, always sort it by qbase.
4353          * Find adjacent prev and last entries.
4354          */
4355         prev = next = NULL;
4356         LIST_FOREACH(entry, &pool->free_list, next) {
4357                 if (entry->base > valid_entry->base) {
4358                         next = entry;
4359                         break;
4360                 }
4361                 prev = entry;
4362         }
4363
4364         insert = 0;
4365         /* Try to merge with next one*/
4366         if (next != NULL) {
4367                 /* Merge with next one */
4368                 if (valid_entry->base + valid_entry->len == next->base) {
4369                         next->base = valid_entry->base;
4370                         next->len += valid_entry->len;
4371                         rte_free(valid_entry);
4372                         valid_entry = next;
4373                         insert = 1;
4374                 }
4375         }
4376
4377         if (prev != NULL) {
4378                 /* Merge with previous one */
4379                 if (prev->base + prev->len == valid_entry->base) {
4380                         prev->len += valid_entry->len;
4381                         /* If it merge with next one, remove next node */
4382                         if (insert == 1) {
4383                                 LIST_REMOVE(valid_entry, next);
4384                                 rte_free(valid_entry);
4385                         } else {
4386                                 rte_free(valid_entry);
4387                                 insert = 1;
4388                         }
4389                 }
4390         }
4391
4392         /* Not find any entry to merge, insert */
4393         if (insert == 0) {
4394                 if (prev != NULL)
4395                         LIST_INSERT_AFTER(prev, valid_entry, next);
4396                 else if (next != NULL)
4397                         LIST_INSERT_BEFORE(next, valid_entry, next);
4398                 else /* It's empty list, insert to head */
4399                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4400         }
4401
4402         pool->num_free += valid_entry->len;
4403         pool->num_alloc -= valid_entry->len;
4404
4405         return 0;
4406 }
4407
4408 static int
4409 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4410                        uint16_t num)
4411 {
4412         struct pool_entry *entry, *valid_entry;
4413
4414         if (pool == NULL || num == 0) {
4415                 PMD_DRV_LOG(ERR, "Invalid parameter");
4416                 return -EINVAL;
4417         }
4418
4419         if (pool->num_free < num) {
4420                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4421                             num, pool->num_free);
4422                 return -ENOMEM;
4423         }
4424
4425         valid_entry = NULL;
4426         /* Lookup  in free list and find most fit one */
4427         LIST_FOREACH(entry, &pool->free_list, next) {
4428                 if (entry->len >= num) {
4429                         /* Find best one */
4430                         if (entry->len == num) {
4431                                 valid_entry = entry;
4432                                 break;
4433                         }
4434                         if (valid_entry == NULL || valid_entry->len > entry->len)
4435                                 valid_entry = entry;
4436                 }
4437         }
4438
4439         /* Not find one to satisfy the request, return */
4440         if (valid_entry == NULL) {
4441                 PMD_DRV_LOG(ERR, "No valid entry found");
4442                 return -ENOMEM;
4443         }
4444         /**
4445          * The entry have equal queue number as requested,
4446          * remove it from alloc_list.
4447          */
4448         if (valid_entry->len == num) {
4449                 LIST_REMOVE(valid_entry, next);
4450         } else {
4451                 /**
4452                  * The entry have more numbers than requested,
4453                  * create a new entry for alloc_list and minus its
4454                  * queue base and number in free_list.
4455                  */
4456                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4457                 if (entry == NULL) {
4458                         PMD_DRV_LOG(ERR,
4459                                 "Failed to allocate memory for resource pool");
4460                         return -ENOMEM;
4461                 }
4462                 entry->base = valid_entry->base;
4463                 entry->len = num;
4464                 valid_entry->base += num;
4465                 valid_entry->len -= num;
4466                 valid_entry = entry;
4467         }
4468
4469         /* Insert it into alloc list, not sorted */
4470         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4471
4472         pool->num_free -= valid_entry->len;
4473         pool->num_alloc += valid_entry->len;
4474
4475         return valid_entry->base + pool->base;
4476 }
4477
4478 /**
4479  * bitmap_is_subset - Check whether src2 is subset of src1
4480  **/
4481 static inline int
4482 bitmap_is_subset(uint8_t src1, uint8_t src2)
4483 {
4484         return !((src1 ^ src2) & src2);
4485 }
4486
4487 static enum i40e_status_code
4488 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4489 {
4490         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4491
4492         /* If DCB is not supported, only default TC is supported */
4493         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4494                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4495                 return I40E_NOT_SUPPORTED;
4496         }
4497
4498         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4499                 PMD_DRV_LOG(ERR,
4500                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4501                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4502                 return I40E_NOT_SUPPORTED;
4503         }
4504         return I40E_SUCCESS;
4505 }
4506
4507 int
4508 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4509                                 struct i40e_vsi_vlan_pvid_info *info)
4510 {
4511         struct i40e_hw *hw;
4512         struct i40e_vsi_context ctxt;
4513         uint8_t vlan_flags = 0;
4514         int ret;
4515
4516         if (vsi == NULL || info == NULL) {
4517                 PMD_DRV_LOG(ERR, "invalid parameters");
4518                 return I40E_ERR_PARAM;
4519         }
4520
4521         if (info->on) {
4522                 vsi->info.pvid = info->config.pvid;
4523                 /**
4524                  * If insert pvid is enabled, only tagged pkts are
4525                  * allowed to be sent out.
4526                  */
4527                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4528                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4529         } else {
4530                 vsi->info.pvid = 0;
4531                 if (info->config.reject.tagged == 0)
4532                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4533
4534                 if (info->config.reject.untagged == 0)
4535                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4536         }
4537         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4538                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4539         vsi->info.port_vlan_flags |= vlan_flags;
4540         vsi->info.valid_sections =
4541                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4542         memset(&ctxt, 0, sizeof(ctxt));
4543         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4544         ctxt.seid = vsi->seid;
4545
4546         hw = I40E_VSI_TO_HW(vsi);
4547         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4548         if (ret != I40E_SUCCESS)
4549                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4550
4551         return ret;
4552 }
4553
4554 static int
4555 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4556 {
4557         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4558         int i, ret;
4559         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4560
4561         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4562         if (ret != I40E_SUCCESS)
4563                 return ret;
4564
4565         if (!vsi->seid) {
4566                 PMD_DRV_LOG(ERR, "seid not valid");
4567                 return -EINVAL;
4568         }
4569
4570         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4571         tc_bw_data.tc_valid_bits = enabled_tcmap;
4572         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4573                 tc_bw_data.tc_bw_credits[i] =
4574                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4575
4576         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4577         if (ret != I40E_SUCCESS) {
4578                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4579                 return ret;
4580         }
4581
4582         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4583                                         sizeof(vsi->info.qs_handle));
4584         return I40E_SUCCESS;
4585 }
4586
4587 static enum i40e_status_code
4588 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4589                                  struct i40e_aqc_vsi_properties_data *info,
4590                                  uint8_t enabled_tcmap)
4591 {
4592         enum i40e_status_code ret;
4593         int i, total_tc = 0;
4594         uint16_t qpnum_per_tc, bsf, qp_idx;
4595
4596         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4597         if (ret != I40E_SUCCESS)
4598                 return ret;
4599
4600         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4601                 if (enabled_tcmap & (1 << i))
4602                         total_tc++;
4603         if (total_tc == 0)
4604                 total_tc = 1;
4605         vsi->enabled_tc = enabled_tcmap;
4606
4607         /* Number of queues per enabled TC */
4608         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4609         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4610         bsf = rte_bsf32(qpnum_per_tc);
4611
4612         /* Adjust the queue number to actual queues that can be applied */
4613         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4614                 vsi->nb_qps = qpnum_per_tc * total_tc;
4615
4616         /**
4617          * Configure TC and queue mapping parameters, for enabled TC,
4618          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4619          * default queue will serve it.
4620          */
4621         qp_idx = 0;
4622         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4623                 if (vsi->enabled_tc & (1 << i)) {
4624                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4625                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4626                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4627                         qp_idx += qpnum_per_tc;
4628                 } else
4629                         info->tc_mapping[i] = 0;
4630         }
4631
4632         /* Associate queue number with VSI */
4633         if (vsi->type == I40E_VSI_SRIOV) {
4634                 info->mapping_flags |=
4635                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4636                 for (i = 0; i < vsi->nb_qps; i++)
4637                         info->queue_mapping[i] =
4638                                 rte_cpu_to_le_16(vsi->base_queue + i);
4639         } else {
4640                 info->mapping_flags |=
4641                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4642                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4643         }
4644         info->valid_sections |=
4645                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4646
4647         return I40E_SUCCESS;
4648 }
4649
4650 static int
4651 i40e_veb_release(struct i40e_veb *veb)
4652 {
4653         struct i40e_vsi *vsi;
4654         struct i40e_hw *hw;
4655
4656         if (veb == NULL)
4657                 return -EINVAL;
4658
4659         if (!TAILQ_EMPTY(&veb->head)) {
4660                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4661                 return -EACCES;
4662         }
4663         /* associate_vsi field is NULL for floating VEB */
4664         if (veb->associate_vsi != NULL) {
4665                 vsi = veb->associate_vsi;
4666                 hw = I40E_VSI_TO_HW(vsi);
4667
4668                 vsi->uplink_seid = veb->uplink_seid;
4669                 vsi->veb = NULL;
4670         } else {
4671                 veb->associate_pf->main_vsi->floating_veb = NULL;
4672                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4673         }
4674
4675         i40e_aq_delete_element(hw, veb->seid, NULL);
4676         rte_free(veb);
4677         return I40E_SUCCESS;
4678 }
4679
4680 /* Setup a veb */
4681 static struct i40e_veb *
4682 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4683 {
4684         struct i40e_veb *veb;
4685         int ret;
4686         struct i40e_hw *hw;
4687
4688         if (pf == NULL) {
4689                 PMD_DRV_LOG(ERR,
4690                             "veb setup failed, associated PF shouldn't null");
4691                 return NULL;
4692         }
4693         hw = I40E_PF_TO_HW(pf);
4694
4695         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4696         if (!veb) {
4697                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4698                 goto fail;
4699         }
4700
4701         veb->associate_vsi = vsi;
4702         veb->associate_pf = pf;
4703         TAILQ_INIT(&veb->head);
4704         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4705
4706         /* create floating veb if vsi is NULL */
4707         if (vsi != NULL) {
4708                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4709                                       I40E_DEFAULT_TCMAP, false,
4710                                       &veb->seid, false, NULL);
4711         } else {
4712                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4713                                       true, &veb->seid, false, NULL);
4714         }
4715
4716         if (ret != I40E_SUCCESS) {
4717                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4718                             hw->aq.asq_last_status);
4719                 goto fail;
4720         }
4721         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4722
4723         /* get statistics index */
4724         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4725                                 &veb->stats_idx, NULL, NULL, NULL);
4726         if (ret != I40E_SUCCESS) {
4727                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4728                             hw->aq.asq_last_status);
4729                 goto fail;
4730         }
4731         /* Get VEB bandwidth, to be implemented */
4732         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4733         if (vsi)
4734                 vsi->uplink_seid = veb->seid;
4735
4736         return veb;
4737 fail:
4738         rte_free(veb);
4739         return NULL;
4740 }
4741
4742 int
4743 i40e_vsi_release(struct i40e_vsi *vsi)
4744 {
4745         struct i40e_pf *pf;
4746         struct i40e_hw *hw;
4747         struct i40e_vsi_list *vsi_list;
4748         void *temp;
4749         int ret;
4750         struct i40e_mac_filter *f;
4751         uint16_t user_param;
4752
4753         if (!vsi)
4754                 return I40E_SUCCESS;
4755
4756         if (!vsi->adapter)
4757                 return -EFAULT;
4758
4759         user_param = vsi->user_param;
4760
4761         pf = I40E_VSI_TO_PF(vsi);
4762         hw = I40E_VSI_TO_HW(vsi);
4763
4764         /* VSI has child to attach, release child first */
4765         if (vsi->veb) {
4766                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4767                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4768                                 return -1;
4769                 }
4770                 i40e_veb_release(vsi->veb);
4771         }
4772
4773         if (vsi->floating_veb) {
4774                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4775                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4776                                 return -1;
4777                 }
4778         }
4779
4780         /* Remove all macvlan filters of the VSI */
4781         i40e_vsi_remove_all_macvlan_filter(vsi);
4782         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4783                 rte_free(f);
4784
4785         if (vsi->type != I40E_VSI_MAIN &&
4786             ((vsi->type != I40E_VSI_SRIOV) ||
4787             !pf->floating_veb_list[user_param])) {
4788                 /* Remove vsi from parent's sibling list */
4789                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4790                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4791                         return I40E_ERR_PARAM;
4792                 }
4793                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4794                                 &vsi->sib_vsi_list, list);
4795
4796                 /* Remove all switch element of the VSI */
4797                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4798                 if (ret != I40E_SUCCESS)
4799                         PMD_DRV_LOG(ERR, "Failed to delete element");
4800         }
4801
4802         if ((vsi->type == I40E_VSI_SRIOV) &&
4803             pf->floating_veb_list[user_param]) {
4804                 /* Remove vsi from parent's sibling list */
4805                 if (vsi->parent_vsi == NULL ||
4806                     vsi->parent_vsi->floating_veb == NULL) {
4807                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4808                         return I40E_ERR_PARAM;
4809                 }
4810                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4811                              &vsi->sib_vsi_list, list);
4812
4813                 /* Remove all switch element of the VSI */
4814                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4815                 if (ret != I40E_SUCCESS)
4816                         PMD_DRV_LOG(ERR, "Failed to delete element");
4817         }
4818
4819         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4820
4821         if (vsi->type != I40E_VSI_SRIOV)
4822                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4823         rte_free(vsi);
4824
4825         return I40E_SUCCESS;
4826 }
4827
4828 static int
4829 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4830 {
4831         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4832         struct i40e_aqc_remove_macvlan_element_data def_filter;
4833         struct i40e_mac_filter_info filter;
4834         int ret;
4835
4836         if (vsi->type != I40E_VSI_MAIN)
4837                 return I40E_ERR_CONFIG;
4838         memset(&def_filter, 0, sizeof(def_filter));
4839         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4840                                         ETH_ADDR_LEN);
4841         def_filter.vlan_tag = 0;
4842         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4843                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4844         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4845         if (ret != I40E_SUCCESS) {
4846                 struct i40e_mac_filter *f;
4847                 struct ether_addr *mac;
4848
4849                 PMD_DRV_LOG(DEBUG,
4850                             "Cannot remove the default macvlan filter");
4851                 /* It needs to add the permanent mac into mac list */
4852                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4853                 if (f == NULL) {
4854                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4855                         return I40E_ERR_NO_MEMORY;
4856                 }
4857                 mac = &f->mac_info.mac_addr;
4858                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4859                                 ETH_ADDR_LEN);
4860                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4861                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4862                 vsi->mac_num++;
4863
4864                 return ret;
4865         }
4866         rte_memcpy(&filter.mac_addr,
4867                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4868         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4869         return i40e_vsi_add_mac(vsi, &filter);
4870 }
4871
4872 /*
4873  * i40e_vsi_get_bw_config - Query VSI BW Information
4874  * @vsi: the VSI to be queried
4875  *
4876  * Returns 0 on success, negative value on failure
4877  */
4878 static enum i40e_status_code
4879 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4880 {
4881         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4882         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4883         struct i40e_hw *hw = &vsi->adapter->hw;
4884         i40e_status ret;
4885         int i;
4886         uint32_t bw_max;
4887
4888         memset(&bw_config, 0, sizeof(bw_config));
4889         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4890         if (ret != I40E_SUCCESS) {
4891                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4892                             hw->aq.asq_last_status);
4893                 return ret;
4894         }
4895
4896         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4897         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4898                                         &ets_sla_config, NULL);
4899         if (ret != I40E_SUCCESS) {
4900                 PMD_DRV_LOG(ERR,
4901                         "VSI failed to get TC bandwdith configuration %u",
4902                         hw->aq.asq_last_status);
4903                 return ret;
4904         }
4905
4906         /* store and print out BW info */
4907         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4908         vsi->bw_info.bw_max = bw_config.max_bw;
4909         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4910         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4911         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4912                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4913                      I40E_16_BIT_WIDTH);
4914         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4915                 vsi->bw_info.bw_ets_share_credits[i] =
4916                                 ets_sla_config.share_credits[i];
4917                 vsi->bw_info.bw_ets_credits[i] =
4918                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4919                 /* 4 bits per TC, 4th bit is reserved */
4920                 vsi->bw_info.bw_ets_max[i] =
4921                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4922                                   RTE_LEN2MASK(3, uint8_t));
4923                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4924                             vsi->bw_info.bw_ets_share_credits[i]);
4925                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4926                             vsi->bw_info.bw_ets_credits[i]);
4927                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4928                             vsi->bw_info.bw_ets_max[i]);
4929         }
4930
4931         return I40E_SUCCESS;
4932 }
4933
4934 /* i40e_enable_pf_lb
4935  * @pf: pointer to the pf structure
4936  *
4937  * allow loopback on pf
4938  */
4939 static inline void
4940 i40e_enable_pf_lb(struct i40e_pf *pf)
4941 {
4942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4943         struct i40e_vsi_context ctxt;
4944         int ret;
4945
4946         /* Use the FW API if FW >= v5.0 */
4947         if (hw->aq.fw_maj_ver < 5) {
4948                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4949                 return;
4950         }
4951
4952         memset(&ctxt, 0, sizeof(ctxt));
4953         ctxt.seid = pf->main_vsi_seid;
4954         ctxt.pf_num = hw->pf_id;
4955         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4956         if (ret) {
4957                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4958                             ret, hw->aq.asq_last_status);
4959                 return;
4960         }
4961         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4962         ctxt.info.valid_sections =
4963                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4964         ctxt.info.switch_id |=
4965                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4966
4967         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4968         if (ret)
4969                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4970                             hw->aq.asq_last_status);
4971 }
4972
4973 /* Setup a VSI */
4974 struct i40e_vsi *
4975 i40e_vsi_setup(struct i40e_pf *pf,
4976                enum i40e_vsi_type type,
4977                struct i40e_vsi *uplink_vsi,
4978                uint16_t user_param)
4979 {
4980         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4981         struct i40e_vsi *vsi;
4982         struct i40e_mac_filter_info filter;
4983         int ret;
4984         struct i40e_vsi_context ctxt;
4985         struct ether_addr broadcast =
4986                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4987
4988         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4989             uplink_vsi == NULL) {
4990                 PMD_DRV_LOG(ERR,
4991                         "VSI setup failed, VSI link shouldn't be NULL");
4992                 return NULL;
4993         }
4994
4995         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4996                 PMD_DRV_LOG(ERR,
4997                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4998                 return NULL;
4999         }
5000
5001         /* two situations
5002          * 1.type is not MAIN and uplink vsi is not NULL
5003          * If uplink vsi didn't setup VEB, create one first under veb field
5004          * 2.type is SRIOV and the uplink is NULL
5005          * If floating VEB is NULL, create one veb under floating veb field
5006          */
5007
5008         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5009             uplink_vsi->veb == NULL) {
5010                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5011
5012                 if (uplink_vsi->veb == NULL) {
5013                         PMD_DRV_LOG(ERR, "VEB setup failed");
5014                         return NULL;
5015                 }
5016                 /* set ALLOWLOOPBACk on pf, when veb is created */
5017                 i40e_enable_pf_lb(pf);
5018         }
5019
5020         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5021             pf->main_vsi->floating_veb == NULL) {
5022                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5023
5024                 if (pf->main_vsi->floating_veb == NULL) {
5025                         PMD_DRV_LOG(ERR, "VEB setup failed");
5026                         return NULL;
5027                 }
5028         }
5029
5030         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5031         if (!vsi) {
5032                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5033                 return NULL;
5034         }
5035         TAILQ_INIT(&vsi->mac_list);
5036         vsi->type = type;
5037         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5038         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5039         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5040         vsi->user_param = user_param;
5041         vsi->vlan_anti_spoof_on = 0;
5042         vsi->vlan_filter_on = 0;
5043         /* Allocate queues */
5044         switch (vsi->type) {
5045         case I40E_VSI_MAIN  :
5046                 vsi->nb_qps = pf->lan_nb_qps;
5047                 break;
5048         case I40E_VSI_SRIOV :
5049                 vsi->nb_qps = pf->vf_nb_qps;
5050                 break;
5051         case I40E_VSI_VMDQ2:
5052                 vsi->nb_qps = pf->vmdq_nb_qps;
5053                 break;
5054         case I40E_VSI_FDIR:
5055                 vsi->nb_qps = pf->fdir_nb_qps;
5056                 break;
5057         default:
5058                 goto fail_mem;
5059         }
5060         /*
5061          * The filter status descriptor is reported in rx queue 0,
5062          * while the tx queue for fdir filter programming has no
5063          * such constraints, can be non-zero queues.
5064          * To simplify it, choose FDIR vsi use queue 0 pair.
5065          * To make sure it will use queue 0 pair, queue allocation
5066          * need be done before this function is called
5067          */
5068         if (type != I40E_VSI_FDIR) {
5069                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5070                         if (ret < 0) {
5071                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5072                                                 vsi->seid, ret);
5073                                 goto fail_mem;
5074                         }
5075                         vsi->base_queue = ret;
5076         } else
5077                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5078
5079         /* VF has MSIX interrupt in VF range, don't allocate here */
5080         if (type == I40E_VSI_MAIN) {
5081                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5082                                           RTE_MIN(vsi->nb_qps,
5083                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5084                 if (ret < 0) {
5085                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5086                                     vsi->seid, ret);
5087                         goto fail_queue_alloc;
5088                 }
5089                 vsi->msix_intr = ret;
5090                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5091         } else if (type != I40E_VSI_SRIOV) {
5092                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5093                 if (ret < 0) {
5094                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5095                         goto fail_queue_alloc;
5096                 }
5097                 vsi->msix_intr = ret;
5098                 vsi->nb_msix = 1;
5099         } else {
5100                 vsi->msix_intr = 0;
5101                 vsi->nb_msix = 0;
5102         }
5103
5104         /* Add VSI */
5105         if (type == I40E_VSI_MAIN) {
5106                 /* For main VSI, no need to add since it's default one */
5107                 vsi->uplink_seid = pf->mac_seid;
5108                 vsi->seid = pf->main_vsi_seid;
5109                 /* Bind queues with specific MSIX interrupt */
5110                 /**
5111                  * Needs 2 interrupt at least, one for misc cause which will
5112                  * enabled from OS side, Another for queues binding the
5113                  * interrupt from device side only.
5114                  */
5115
5116                 /* Get default VSI parameters from hardware */
5117                 memset(&ctxt, 0, sizeof(ctxt));
5118                 ctxt.seid = vsi->seid;
5119                 ctxt.pf_num = hw->pf_id;
5120                 ctxt.uplink_seid = vsi->uplink_seid;
5121                 ctxt.vf_num = 0;
5122                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5123                 if (ret != I40E_SUCCESS) {
5124                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5125                         goto fail_msix_alloc;
5126                 }
5127                 rte_memcpy(&vsi->info, &ctxt.info,
5128                         sizeof(struct i40e_aqc_vsi_properties_data));
5129                 vsi->vsi_id = ctxt.vsi_number;
5130                 vsi->info.valid_sections = 0;
5131
5132                 /* Configure tc, enabled TC0 only */
5133                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5134                         I40E_SUCCESS) {
5135                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5136                         goto fail_msix_alloc;
5137                 }
5138
5139                 /* TC, queue mapping */
5140                 memset(&ctxt, 0, sizeof(ctxt));
5141                 vsi->info.valid_sections |=
5142                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5143                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5144                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5145                 rte_memcpy(&ctxt.info, &vsi->info,
5146                         sizeof(struct i40e_aqc_vsi_properties_data));
5147                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5148                                                 I40E_DEFAULT_TCMAP);
5149                 if (ret != I40E_SUCCESS) {
5150                         PMD_DRV_LOG(ERR,
5151                                 "Failed to configure TC queue mapping");
5152                         goto fail_msix_alloc;
5153                 }
5154                 ctxt.seid = vsi->seid;
5155                 ctxt.pf_num = hw->pf_id;
5156                 ctxt.uplink_seid = vsi->uplink_seid;
5157                 ctxt.vf_num = 0;
5158
5159                 /* Update VSI parameters */
5160                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5161                 if (ret != I40E_SUCCESS) {
5162                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5163                         goto fail_msix_alloc;
5164                 }
5165
5166                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5167                                                 sizeof(vsi->info.tc_mapping));
5168                 rte_memcpy(&vsi->info.queue_mapping,
5169                                 &ctxt.info.queue_mapping,
5170                         sizeof(vsi->info.queue_mapping));
5171                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5172                 vsi->info.valid_sections = 0;
5173
5174                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5175                                 ETH_ADDR_LEN);
5176
5177                 /**
5178                  * Updating default filter settings are necessary to prevent
5179                  * reception of tagged packets.
5180                  * Some old firmware configurations load a default macvlan
5181                  * filter which accepts both tagged and untagged packets.
5182                  * The updating is to use a normal filter instead if needed.
5183                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5184                  * The firmware with correct configurations load the default
5185                  * macvlan filter which is expected and cannot be removed.
5186                  */
5187                 i40e_update_default_filter_setting(vsi);
5188                 i40e_config_qinq(hw, vsi);
5189         } else if (type == I40E_VSI_SRIOV) {
5190                 memset(&ctxt, 0, sizeof(ctxt));
5191                 /**
5192                  * For other VSI, the uplink_seid equals to uplink VSI's
5193                  * uplink_seid since they share same VEB
5194                  */
5195                 if (uplink_vsi == NULL)
5196                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5197                 else
5198                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5199                 ctxt.pf_num = hw->pf_id;
5200                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5201                 ctxt.uplink_seid = vsi->uplink_seid;
5202                 ctxt.connection_type = 0x1;
5203                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5204
5205                 /* Use the VEB configuration if FW >= v5.0 */
5206                 if (hw->aq.fw_maj_ver >= 5) {
5207                         /* Configure switch ID */
5208                         ctxt.info.valid_sections |=
5209                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5210                         ctxt.info.switch_id =
5211                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5212                 }
5213
5214                 /* Configure port/vlan */
5215                 ctxt.info.valid_sections |=
5216                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5217                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5218                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5219                                                 hw->func_caps.enabled_tcmap);
5220                 if (ret != I40E_SUCCESS) {
5221                         PMD_DRV_LOG(ERR,
5222                                 "Failed to configure TC queue mapping");
5223                         goto fail_msix_alloc;
5224                 }
5225
5226                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5227                 ctxt.info.valid_sections |=
5228                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5229                 /**
5230                  * Since VSI is not created yet, only configure parameter,
5231                  * will add vsi below.
5232                  */
5233
5234                 i40e_config_qinq(hw, vsi);
5235         } else if (type == I40E_VSI_VMDQ2) {
5236                 memset(&ctxt, 0, sizeof(ctxt));
5237                 /*
5238                  * For other VSI, the uplink_seid equals to uplink VSI's
5239                  * uplink_seid since they share same VEB
5240                  */
5241                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5242                 ctxt.pf_num = hw->pf_id;
5243                 ctxt.vf_num = 0;
5244                 ctxt.uplink_seid = vsi->uplink_seid;
5245                 ctxt.connection_type = 0x1;
5246                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5247
5248                 ctxt.info.valid_sections |=
5249                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5250                 /* user_param carries flag to enable loop back */
5251                 if (user_param) {
5252                         ctxt.info.switch_id =
5253                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5254                         ctxt.info.switch_id |=
5255                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5256                 }
5257
5258                 /* Configure port/vlan */
5259                 ctxt.info.valid_sections |=
5260                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5261                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5262                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5263                                                 I40E_DEFAULT_TCMAP);
5264                 if (ret != I40E_SUCCESS) {
5265                         PMD_DRV_LOG(ERR,
5266                                 "Failed to configure TC queue mapping");
5267                         goto fail_msix_alloc;
5268                 }
5269                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5270                 ctxt.info.valid_sections |=
5271                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5272         } else if (type == I40E_VSI_FDIR) {
5273                 memset(&ctxt, 0, sizeof(ctxt));
5274                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5275                 ctxt.pf_num = hw->pf_id;
5276                 ctxt.vf_num = 0;
5277                 ctxt.uplink_seid = vsi->uplink_seid;
5278                 ctxt.connection_type = 0x1;     /* regular data port */
5279                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5280                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5281                                                 I40E_DEFAULT_TCMAP);
5282                 if (ret != I40E_SUCCESS) {
5283                         PMD_DRV_LOG(ERR,
5284                                 "Failed to configure TC queue mapping.");
5285                         goto fail_msix_alloc;
5286                 }
5287                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5288                 ctxt.info.valid_sections |=
5289                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5290         } else {
5291                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5292                 goto fail_msix_alloc;
5293         }
5294
5295         if (vsi->type != I40E_VSI_MAIN) {
5296                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5297                 if (ret != I40E_SUCCESS) {
5298                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5299                                     hw->aq.asq_last_status);
5300                         goto fail_msix_alloc;
5301                 }
5302                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5303                 vsi->info.valid_sections = 0;
5304                 vsi->seid = ctxt.seid;
5305                 vsi->vsi_id = ctxt.vsi_number;
5306                 vsi->sib_vsi_list.vsi = vsi;
5307                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5308                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5309                                           &vsi->sib_vsi_list, list);
5310                 } else {
5311                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5312                                           &vsi->sib_vsi_list, list);
5313                 }
5314         }
5315
5316         /* MAC/VLAN configuration */
5317         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5318         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5319
5320         ret = i40e_vsi_add_mac(vsi, &filter);
5321         if (ret != I40E_SUCCESS) {
5322                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5323                 goto fail_msix_alloc;
5324         }
5325
5326         /* Get VSI BW information */
5327         i40e_vsi_get_bw_config(vsi);
5328         return vsi;
5329 fail_msix_alloc:
5330         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5331 fail_queue_alloc:
5332         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5333 fail_mem:
5334         rte_free(vsi);
5335         return NULL;
5336 }
5337
5338 /* Configure vlan filter on or off */
5339 int
5340 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5341 {
5342         int i, num;
5343         struct i40e_mac_filter *f;
5344         void *temp;
5345         struct i40e_mac_filter_info *mac_filter;
5346         enum rte_mac_filter_type desired_filter;
5347         int ret = I40E_SUCCESS;
5348
5349         if (on) {
5350                 /* Filter to match MAC and VLAN */
5351                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5352         } else {
5353                 /* Filter to match only MAC */
5354                 desired_filter = RTE_MAC_PERFECT_MATCH;
5355         }
5356
5357         num = vsi->mac_num;
5358
5359         mac_filter = rte_zmalloc("mac_filter_info_data",
5360                                  num * sizeof(*mac_filter), 0);
5361         if (mac_filter == NULL) {
5362                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5363                 return I40E_ERR_NO_MEMORY;
5364         }
5365
5366         i = 0;
5367
5368         /* Remove all existing mac */
5369         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5370                 mac_filter[i] = f->mac_info;
5371                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5372                 if (ret) {
5373                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5374                                     on ? "enable" : "disable");
5375                         goto DONE;
5376                 }
5377                 i++;
5378         }
5379
5380         /* Override with new filter */
5381         for (i = 0; i < num; i++) {
5382                 mac_filter[i].filter_type = desired_filter;
5383                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5384                 if (ret) {
5385                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5386                                     on ? "enable" : "disable");
5387                         goto DONE;
5388                 }
5389         }
5390
5391 DONE:
5392         rte_free(mac_filter);
5393         return ret;
5394 }
5395
5396 /* Configure vlan stripping on or off */
5397 int
5398 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5399 {
5400         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5401         struct i40e_vsi_context ctxt;
5402         uint8_t vlan_flags;
5403         int ret = I40E_SUCCESS;
5404
5405         /* Check if it has been already on or off */
5406         if (vsi->info.valid_sections &
5407                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5408                 if (on) {
5409                         if ((vsi->info.port_vlan_flags &
5410                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5411                                 return 0; /* already on */
5412                 } else {
5413                         if ((vsi->info.port_vlan_flags &
5414                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5415                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5416                                 return 0; /* already off */
5417                 }
5418         }
5419
5420         if (on)
5421                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5422         else
5423                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5424         vsi->info.valid_sections =
5425                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5426         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5427         vsi->info.port_vlan_flags |= vlan_flags;
5428         ctxt.seid = vsi->seid;
5429         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5430         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5431         if (ret)
5432                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5433                             on ? "enable" : "disable");
5434
5435         return ret;
5436 }
5437
5438 static int
5439 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5440 {
5441         struct rte_eth_dev_data *data = dev->data;
5442         int ret;
5443         int mask = 0;
5444
5445         /* Apply vlan offload setting */
5446         mask = ETH_VLAN_STRIP_MASK |
5447                ETH_VLAN_FILTER_MASK |
5448                ETH_VLAN_EXTEND_MASK;
5449         ret = i40e_vlan_offload_set(dev, mask);
5450         if (ret) {
5451                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5452                 return ret;
5453         }
5454
5455         /* Apply pvid setting */
5456         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5457                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5458         if (ret)
5459                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5460
5461         return ret;
5462 }
5463
5464 static int
5465 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5466 {
5467         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5468
5469         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5470 }
5471
5472 static int
5473 i40e_update_flow_control(struct i40e_hw *hw)
5474 {
5475 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5476         struct i40e_link_status link_status;
5477         uint32_t rxfc = 0, txfc = 0, reg;
5478         uint8_t an_info;
5479         int ret;
5480
5481         memset(&link_status, 0, sizeof(link_status));
5482         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5483         if (ret != I40E_SUCCESS) {
5484                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5485                 goto write_reg; /* Disable flow control */
5486         }
5487
5488         an_info = hw->phy.link_info.an_info;
5489         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5490                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5491                 ret = I40E_ERR_NOT_READY;
5492                 goto write_reg; /* Disable flow control */
5493         }
5494         /**
5495          * If link auto negotiation is enabled, flow control needs to
5496          * be configured according to it
5497          */
5498         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5499         case I40E_LINK_PAUSE_RXTX:
5500                 rxfc = 1;
5501                 txfc = 1;
5502                 hw->fc.current_mode = I40E_FC_FULL;
5503                 break;
5504         case I40E_AQ_LINK_PAUSE_RX:
5505                 rxfc = 1;
5506                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5507                 break;
5508         case I40E_AQ_LINK_PAUSE_TX:
5509                 txfc = 1;
5510                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5511                 break;
5512         default:
5513                 hw->fc.current_mode = I40E_FC_NONE;
5514                 break;
5515         }
5516
5517 write_reg:
5518         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5519                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5520         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5521         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5522         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5523         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5524
5525         return ret;
5526 }
5527
5528 /* PF setup */
5529 static int
5530 i40e_pf_setup(struct i40e_pf *pf)
5531 {
5532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5533         struct i40e_filter_control_settings settings;
5534         struct i40e_vsi *vsi;
5535         int ret;
5536
5537         /* Clear all stats counters */
5538         pf->offset_loaded = FALSE;
5539         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5540         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5541         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5542         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5543
5544         ret = i40e_pf_get_switch_config(pf);
5545         if (ret != I40E_SUCCESS) {
5546                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5547                 return ret;
5548         }
5549         if (pf->flags & I40E_FLAG_FDIR) {
5550                 /* make queue allocated first, let FDIR use queue pair 0*/
5551                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5552                 if (ret != I40E_FDIR_QUEUE_ID) {
5553                         PMD_DRV_LOG(ERR,
5554                                 "queue allocation fails for FDIR: ret =%d",
5555                                 ret);
5556                         pf->flags &= ~I40E_FLAG_FDIR;
5557                 }
5558         }
5559         /*  main VSI setup */
5560         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5561         if (!vsi) {
5562                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5563                 return I40E_ERR_NOT_READY;
5564         }
5565         pf->main_vsi = vsi;
5566
5567         /* Configure filter control */
5568         memset(&settings, 0, sizeof(settings));
5569         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5570                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5571         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5572                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5573         else {
5574                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5575                         hw->func_caps.rss_table_size);
5576                 return I40E_ERR_PARAM;
5577         }
5578         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5579                 hw->func_caps.rss_table_size);
5580         pf->hash_lut_size = hw->func_caps.rss_table_size;
5581
5582         /* Enable ethtype and macvlan filters */
5583         settings.enable_ethtype = TRUE;
5584         settings.enable_macvlan = TRUE;
5585         ret = i40e_set_filter_control(hw, &settings);
5586         if (ret)
5587                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5588                                                                 ret);
5589
5590         /* Update flow control according to the auto negotiation */
5591         i40e_update_flow_control(hw);
5592
5593         return I40E_SUCCESS;
5594 }
5595
5596 int
5597 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5598 {
5599         uint32_t reg;
5600         uint16_t j;
5601
5602         /**
5603          * Set or clear TX Queue Disable flags,
5604          * which is required by hardware.
5605          */
5606         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5607         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5608
5609         /* Wait until the request is finished */
5610         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5611                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5612                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5613                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5614                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5615                                                         & 0x1))) {
5616                         break;
5617                 }
5618         }
5619         if (on) {
5620                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5621                         return I40E_SUCCESS; /* already on, skip next steps */
5622
5623                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5624                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5625         } else {
5626                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5627                         return I40E_SUCCESS; /* already off, skip next steps */
5628                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5629         }
5630         /* Write the register */
5631         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5632         /* Check the result */
5633         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5634                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5635                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5636                 if (on) {
5637                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5638                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5639                                 break;
5640                 } else {
5641                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5642                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5643                                 break;
5644                 }
5645         }
5646         /* Check if it is timeout */
5647         if (j >= I40E_CHK_Q_ENA_COUNT) {
5648                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5649                             (on ? "enable" : "disable"), q_idx);
5650                 return I40E_ERR_TIMEOUT;
5651         }
5652
5653         return I40E_SUCCESS;
5654 }
5655
5656 /* Swith on or off the tx queues */
5657 static int
5658 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5659 {
5660         struct rte_eth_dev_data *dev_data = pf->dev_data;
5661         struct i40e_tx_queue *txq;
5662         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5663         uint16_t i;
5664         int ret;
5665
5666         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5667                 txq = dev_data->tx_queues[i];
5668                 /* Don't operate the queue if not configured or
5669                  * if starting only per queue */
5670                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5671                         continue;
5672                 if (on)
5673                         ret = i40e_dev_tx_queue_start(dev, i);
5674                 else
5675                         ret = i40e_dev_tx_queue_stop(dev, i);
5676                 if ( ret != I40E_SUCCESS)
5677                         return ret;
5678         }
5679
5680         return I40E_SUCCESS;
5681 }
5682
5683 int
5684 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5685 {
5686         uint32_t reg;
5687         uint16_t j;
5688
5689         /* Wait until the request is finished */
5690         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5691                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5692                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5693                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5694                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5695                         break;
5696         }
5697
5698         if (on) {
5699                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5700                         return I40E_SUCCESS; /* Already on, skip next steps */
5701                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5702         } else {
5703                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5704                         return I40E_SUCCESS; /* Already off, skip next steps */
5705                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5706         }
5707
5708         /* Write the register */
5709         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5710         /* Check the result */
5711         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5712                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5713                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5714                 if (on) {
5715                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5716                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5717                                 break;
5718                 } else {
5719                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5720                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5721                                 break;
5722                 }
5723         }
5724
5725         /* Check if it is timeout */
5726         if (j >= I40E_CHK_Q_ENA_COUNT) {
5727                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5728                             (on ? "enable" : "disable"), q_idx);
5729                 return I40E_ERR_TIMEOUT;
5730         }
5731
5732         return I40E_SUCCESS;
5733 }
5734 /* Switch on or off the rx queues */
5735 static int
5736 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5737 {
5738         struct rte_eth_dev_data *dev_data = pf->dev_data;
5739         struct i40e_rx_queue *rxq;
5740         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5741         uint16_t i;
5742         int ret;
5743
5744         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5745                 rxq = dev_data->rx_queues[i];
5746                 /* Don't operate the queue if not configured or
5747                  * if starting only per queue */
5748                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5749                         continue;
5750                 if (on)
5751                         ret = i40e_dev_rx_queue_start(dev, i);
5752                 else
5753                         ret = i40e_dev_rx_queue_stop(dev, i);
5754                 if (ret != I40E_SUCCESS)
5755                         return ret;
5756         }
5757
5758         return I40E_SUCCESS;
5759 }
5760
5761 /* Switch on or off all the rx/tx queues */
5762 int
5763 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5764 {
5765         int ret;
5766
5767         if (on) {
5768                 /* enable rx queues before enabling tx queues */
5769                 ret = i40e_dev_switch_rx_queues(pf, on);
5770                 if (ret) {
5771                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5772                         return ret;
5773                 }
5774                 ret = i40e_dev_switch_tx_queues(pf, on);
5775         } else {
5776                 /* Stop tx queues before stopping rx queues */
5777                 ret = i40e_dev_switch_tx_queues(pf, on);
5778                 if (ret) {
5779                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5780                         return ret;
5781                 }
5782                 ret = i40e_dev_switch_rx_queues(pf, on);
5783         }
5784
5785         return ret;
5786 }
5787
5788 /* Initialize VSI for TX */
5789 static int
5790 i40e_dev_tx_init(struct i40e_pf *pf)
5791 {
5792         struct rte_eth_dev_data *data = pf->dev_data;
5793         uint16_t i;
5794         uint32_t ret = I40E_SUCCESS;
5795         struct i40e_tx_queue *txq;
5796
5797         for (i = 0; i < data->nb_tx_queues; i++) {
5798                 txq = data->tx_queues[i];
5799                 if (!txq || !txq->q_set)
5800                         continue;
5801                 ret = i40e_tx_queue_init(txq);
5802                 if (ret != I40E_SUCCESS)
5803                         break;
5804         }
5805         if (ret == I40E_SUCCESS)
5806                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5807                                      ->eth_dev);
5808
5809         return ret;
5810 }
5811
5812 /* Initialize VSI for RX */
5813 static int
5814 i40e_dev_rx_init(struct i40e_pf *pf)
5815 {
5816         struct rte_eth_dev_data *data = pf->dev_data;
5817         int ret = I40E_SUCCESS;
5818         uint16_t i;
5819         struct i40e_rx_queue *rxq;
5820
5821         i40e_pf_config_mq_rx(pf);
5822         for (i = 0; i < data->nb_rx_queues; i++) {
5823                 rxq = data->rx_queues[i];
5824                 if (!rxq || !rxq->q_set)
5825                         continue;
5826
5827                 ret = i40e_rx_queue_init(rxq);
5828                 if (ret != I40E_SUCCESS) {
5829                         PMD_DRV_LOG(ERR,
5830                                 "Failed to do RX queue initialization");
5831                         break;
5832                 }
5833         }
5834         if (ret == I40E_SUCCESS)
5835                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5836                                      ->eth_dev);
5837
5838         return ret;
5839 }
5840
5841 static int
5842 i40e_dev_rxtx_init(struct i40e_pf *pf)
5843 {
5844         int err;
5845
5846         err = i40e_dev_tx_init(pf);
5847         if (err) {
5848                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5849                 return err;
5850         }
5851         err = i40e_dev_rx_init(pf);
5852         if (err) {
5853                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5854                 return err;
5855         }
5856
5857         return err;
5858 }
5859
5860 static int
5861 i40e_vmdq_setup(struct rte_eth_dev *dev)
5862 {
5863         struct rte_eth_conf *conf = &dev->data->dev_conf;
5864         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5865         int i, err, conf_vsis, j, loop;
5866         struct i40e_vsi *vsi;
5867         struct i40e_vmdq_info *vmdq_info;
5868         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5869         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5870
5871         /*
5872          * Disable interrupt to avoid message from VF. Furthermore, it will
5873          * avoid race condition in VSI creation/destroy.
5874          */
5875         i40e_pf_disable_irq0(hw);
5876
5877         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5878                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5879                 return -ENOTSUP;
5880         }
5881
5882         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5883         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5884                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5885                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5886                         pf->max_nb_vmdq_vsi);
5887                 return -ENOTSUP;
5888         }
5889
5890         if (pf->vmdq != NULL) {
5891                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5892                 return 0;
5893         }
5894
5895         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5896                                 sizeof(*vmdq_info) * conf_vsis, 0);
5897
5898         if (pf->vmdq == NULL) {
5899                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5900                 return -ENOMEM;
5901         }
5902
5903         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5904
5905         /* Create VMDQ VSI */
5906         for (i = 0; i < conf_vsis; i++) {
5907                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5908                                 vmdq_conf->enable_loop_back);
5909                 if (vsi == NULL) {
5910                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5911                         err = -1;
5912                         goto err_vsi_setup;
5913                 }
5914                 vmdq_info = &pf->vmdq[i];
5915                 vmdq_info->pf = pf;
5916                 vmdq_info->vsi = vsi;
5917         }
5918         pf->nb_cfg_vmdq_vsi = conf_vsis;
5919
5920         /* Configure Vlan */
5921         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5922         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5923                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5924                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5925                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5926                                         vmdq_conf->pool_map[i].vlan_id, j);
5927
5928                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5929                                                 vmdq_conf->pool_map[i].vlan_id);
5930                                 if (err) {
5931                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5932                                         err = -1;
5933                                         goto err_vsi_setup;
5934                                 }
5935                         }
5936                 }
5937         }
5938
5939         i40e_pf_enable_irq0(hw);
5940
5941         return 0;
5942
5943 err_vsi_setup:
5944         for (i = 0; i < conf_vsis; i++)
5945                 if (pf->vmdq[i].vsi == NULL)
5946                         break;
5947                 else
5948                         i40e_vsi_release(pf->vmdq[i].vsi);
5949
5950         rte_free(pf->vmdq);
5951         pf->vmdq = NULL;
5952         i40e_pf_enable_irq0(hw);
5953         return err;
5954 }
5955
5956 static void
5957 i40e_stat_update_32(struct i40e_hw *hw,
5958                    uint32_t reg,
5959                    bool offset_loaded,
5960                    uint64_t *offset,
5961                    uint64_t *stat)
5962 {
5963         uint64_t new_data;
5964
5965         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5966         if (!offset_loaded)
5967                 *offset = new_data;
5968
5969         if (new_data >= *offset)
5970                 *stat = (uint64_t)(new_data - *offset);
5971         else
5972                 *stat = (uint64_t)((new_data +
5973                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5974 }
5975
5976 static void
5977 i40e_stat_update_48(struct i40e_hw *hw,
5978                    uint32_t hireg,
5979                    uint32_t loreg,
5980                    bool offset_loaded,
5981                    uint64_t *offset,
5982                    uint64_t *stat)
5983 {
5984         uint64_t new_data;
5985
5986         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5987         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5988                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5989
5990         if (!offset_loaded)
5991                 *offset = new_data;
5992
5993         if (new_data >= *offset)
5994                 *stat = new_data - *offset;
5995         else
5996                 *stat = (uint64_t)((new_data +
5997                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5998
5999         *stat &= I40E_48_BIT_MASK;
6000 }
6001
6002 /* Disable IRQ0 */
6003 void
6004 i40e_pf_disable_irq0(struct i40e_hw *hw)
6005 {
6006         /* Disable all interrupt types */
6007         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6008         I40E_WRITE_FLUSH(hw);
6009 }
6010
6011 /* Enable IRQ0 */
6012 void
6013 i40e_pf_enable_irq0(struct i40e_hw *hw)
6014 {
6015         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6016                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6017                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6018                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6019         I40E_WRITE_FLUSH(hw);
6020 }
6021
6022 static void
6023 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6024 {
6025         /* read pending request and disable first */
6026         i40e_pf_disable_irq0(hw);
6027         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6028         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6029                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6030
6031         if (no_queue)
6032                 /* Link no queues with irq0 */
6033                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6034                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6035 }
6036
6037 static void
6038 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6039 {
6040         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6042         int i;
6043         uint16_t abs_vf_id;
6044         uint32_t index, offset, val;
6045
6046         if (!pf->vfs)
6047                 return;
6048         /**
6049          * Try to find which VF trigger a reset, use absolute VF id to access
6050          * since the reg is global register.
6051          */
6052         for (i = 0; i < pf->vf_num; i++) {
6053                 abs_vf_id = hw->func_caps.vf_base_id + i;
6054                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6055                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6056                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6057                 /* VFR event occurred */
6058                 if (val & (0x1 << offset)) {
6059                         int ret;
6060
6061                         /* Clear the event first */
6062                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6063                                                         (0x1 << offset));
6064                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6065                         /**
6066                          * Only notify a VF reset event occurred,
6067                          * don't trigger another SW reset
6068                          */
6069                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6070                         if (ret != I40E_SUCCESS)
6071                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6072                 }
6073         }
6074 }
6075
6076 static void
6077 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6078 {
6079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6080         int i;
6081
6082         for (i = 0; i < pf->vf_num; i++)
6083                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6084 }
6085
6086 static void
6087 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6088 {
6089         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6090         struct i40e_arq_event_info info;
6091         uint16_t pending, opcode;
6092         int ret;
6093
6094         info.buf_len = I40E_AQ_BUF_SZ;
6095         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6096         if (!info.msg_buf) {
6097                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6098                 return;
6099         }
6100
6101         pending = 1;
6102         while (pending) {
6103                 ret = i40e_clean_arq_element(hw, &info, &pending);
6104
6105                 if (ret != I40E_SUCCESS) {
6106                         PMD_DRV_LOG(INFO,
6107                                 "Failed to read msg from AdminQ, aq_err: %u",
6108                                 hw->aq.asq_last_status);
6109                         break;
6110                 }
6111                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6112
6113                 switch (opcode) {
6114                 case i40e_aqc_opc_send_msg_to_pf:
6115                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6116                         i40e_pf_host_handle_vf_msg(dev,
6117                                         rte_le_to_cpu_16(info.desc.retval),
6118                                         rte_le_to_cpu_32(info.desc.cookie_high),
6119                                         rte_le_to_cpu_32(info.desc.cookie_low),
6120                                         info.msg_buf,
6121                                         info.msg_len);
6122                         break;
6123                 case i40e_aqc_opc_get_link_status:
6124                         ret = i40e_dev_link_update(dev, 0);
6125                         if (!ret)
6126                                 _rte_eth_dev_callback_process(dev,
6127                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6128                         break;
6129                 default:
6130                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6131                                     opcode);
6132                         break;
6133                 }
6134         }
6135         rte_free(info.msg_buf);
6136 }
6137
6138 /**
6139  * Interrupt handler triggered by NIC  for handling
6140  * specific interrupt.
6141  *
6142  * @param handle
6143  *  Pointer to interrupt handle.
6144  * @param param
6145  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6146  *
6147  * @return
6148  *  void
6149  */
6150 static void
6151 i40e_dev_interrupt_handler(void *param)
6152 {
6153         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         uint32_t icr0;
6156
6157         /* Disable interrupt */
6158         i40e_pf_disable_irq0(hw);
6159
6160         /* read out interrupt causes */
6161         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6162
6163         /* No interrupt event indicated */
6164         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6165                 PMD_DRV_LOG(INFO, "No interrupt event");
6166                 goto done;
6167         }
6168         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6169                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6170         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6171                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6172         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6173                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6174         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6175                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6176         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6177                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6178         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6179                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6180         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6181                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6182
6183         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6184                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6185                 i40e_dev_handle_vfr_event(dev);
6186         }
6187         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6188                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6189                 i40e_dev_handle_aq_msg(dev);
6190         }
6191
6192 done:
6193         /* Enable interrupt */
6194         i40e_pf_enable_irq0(hw);
6195         rte_intr_enable(dev->intr_handle);
6196 }
6197
6198 int
6199 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6200                          struct i40e_macvlan_filter *filter,
6201                          int total)
6202 {
6203         int ele_num, ele_buff_size;
6204         int num, actual_num, i;
6205         uint16_t flags;
6206         int ret = I40E_SUCCESS;
6207         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6208         struct i40e_aqc_add_macvlan_element_data *req_list;
6209
6210         if (filter == NULL  || total == 0)
6211                 return I40E_ERR_PARAM;
6212         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6213         ele_buff_size = hw->aq.asq_buf_size;
6214
6215         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6216         if (req_list == NULL) {
6217                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6218                 return I40E_ERR_NO_MEMORY;
6219         }
6220
6221         num = 0;
6222         do {
6223                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6224                 memset(req_list, 0, ele_buff_size);
6225
6226                 for (i = 0; i < actual_num; i++) {
6227                         rte_memcpy(req_list[i].mac_addr,
6228                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6229                         req_list[i].vlan_tag =
6230                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6231
6232                         switch (filter[num + i].filter_type) {
6233                         case RTE_MAC_PERFECT_MATCH:
6234                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6235                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6236                                 break;
6237                         case RTE_MACVLAN_PERFECT_MATCH:
6238                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6239                                 break;
6240                         case RTE_MAC_HASH_MATCH:
6241                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6242                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6243                                 break;
6244                         case RTE_MACVLAN_HASH_MATCH:
6245                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6246                                 break;
6247                         default:
6248                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6249                                 ret = I40E_ERR_PARAM;
6250                                 goto DONE;
6251                         }
6252
6253                         req_list[i].queue_number = 0;
6254
6255                         req_list[i].flags = rte_cpu_to_le_16(flags);
6256                 }
6257
6258                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6259                                                 actual_num, NULL);
6260                 if (ret != I40E_SUCCESS) {
6261                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6262                         goto DONE;
6263                 }
6264                 num += actual_num;
6265         } while (num < total);
6266
6267 DONE:
6268         rte_free(req_list);
6269         return ret;
6270 }
6271
6272 int
6273 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6274                             struct i40e_macvlan_filter *filter,
6275                             int total)
6276 {
6277         int ele_num, ele_buff_size;
6278         int num, actual_num, i;
6279         uint16_t flags;
6280         int ret = I40E_SUCCESS;
6281         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6282         struct i40e_aqc_remove_macvlan_element_data *req_list;
6283
6284         if (filter == NULL  || total == 0)
6285                 return I40E_ERR_PARAM;
6286
6287         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6288         ele_buff_size = hw->aq.asq_buf_size;
6289
6290         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6291         if (req_list == NULL) {
6292                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6293                 return I40E_ERR_NO_MEMORY;
6294         }
6295
6296         num = 0;
6297         do {
6298                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6299                 memset(req_list, 0, ele_buff_size);
6300
6301                 for (i = 0; i < actual_num; i++) {
6302                         rte_memcpy(req_list[i].mac_addr,
6303                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6304                         req_list[i].vlan_tag =
6305                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6306
6307                         switch (filter[num + i].filter_type) {
6308                         case RTE_MAC_PERFECT_MATCH:
6309                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6310                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6311                                 break;
6312                         case RTE_MACVLAN_PERFECT_MATCH:
6313                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6314                                 break;
6315                         case RTE_MAC_HASH_MATCH:
6316                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6317                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6318                                 break;
6319                         case RTE_MACVLAN_HASH_MATCH:
6320                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6321                                 break;
6322                         default:
6323                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6324                                 ret = I40E_ERR_PARAM;
6325                                 goto DONE;
6326                         }
6327                         req_list[i].flags = rte_cpu_to_le_16(flags);
6328                 }
6329
6330                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6331                                                 actual_num, NULL);
6332                 if (ret != I40E_SUCCESS) {
6333                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6334                         goto DONE;
6335                 }
6336                 num += actual_num;
6337         } while (num < total);
6338
6339 DONE:
6340         rte_free(req_list);
6341         return ret;
6342 }
6343
6344 /* Find out specific MAC filter */
6345 static struct i40e_mac_filter *
6346 i40e_find_mac_filter(struct i40e_vsi *vsi,
6347                          struct ether_addr *macaddr)
6348 {
6349         struct i40e_mac_filter *f;
6350
6351         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6352                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6353                         return f;
6354         }
6355
6356         return NULL;
6357 }
6358
6359 static bool
6360 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6361                          uint16_t vlan_id)
6362 {
6363         uint32_t vid_idx, vid_bit;
6364
6365         if (vlan_id > ETH_VLAN_ID_MAX)
6366                 return 0;
6367
6368         vid_idx = I40E_VFTA_IDX(vlan_id);
6369         vid_bit = I40E_VFTA_BIT(vlan_id);
6370
6371         if (vsi->vfta[vid_idx] & vid_bit)
6372                 return 1;
6373         else
6374                 return 0;
6375 }
6376
6377 static void
6378 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6379                        uint16_t vlan_id, bool on)
6380 {
6381         uint32_t vid_idx, vid_bit;
6382
6383         vid_idx = I40E_VFTA_IDX(vlan_id);
6384         vid_bit = I40E_VFTA_BIT(vlan_id);
6385
6386         if (on)
6387                 vsi->vfta[vid_idx] |= vid_bit;
6388         else
6389                 vsi->vfta[vid_idx] &= ~vid_bit;
6390 }
6391
6392 void
6393 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6394                      uint16_t vlan_id, bool on)
6395 {
6396         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6397         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6398         int ret;
6399
6400         if (vlan_id > ETH_VLAN_ID_MAX)
6401                 return;
6402
6403         i40e_store_vlan_filter(vsi, vlan_id, on);
6404
6405         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6406                 return;
6407
6408         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6409
6410         if (on) {
6411                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6412                                        &vlan_data, 1, NULL);
6413                 if (ret != I40E_SUCCESS)
6414                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6415         } else {
6416                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6417                                           &vlan_data, 1, NULL);
6418                 if (ret != I40E_SUCCESS)
6419                         PMD_DRV_LOG(ERR,
6420                                     "Failed to remove vlan filter");
6421         }
6422 }
6423
6424 /**
6425  * Find all vlan options for specific mac addr,
6426  * return with actual vlan found.
6427  */
6428 int
6429 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6430                            struct i40e_macvlan_filter *mv_f,
6431                            int num, struct ether_addr *addr)
6432 {
6433         int i;
6434         uint32_t j, k;
6435
6436         /**
6437          * Not to use i40e_find_vlan_filter to decrease the loop time,
6438          * although the code looks complex.
6439           */
6440         if (num < vsi->vlan_num)
6441                 return I40E_ERR_PARAM;
6442
6443         i = 0;
6444         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6445                 if (vsi->vfta[j]) {
6446                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6447                                 if (vsi->vfta[j] & (1 << k)) {
6448                                         if (i > num - 1) {
6449                                                 PMD_DRV_LOG(ERR,
6450                                                         "vlan number doesn't match");
6451                                                 return I40E_ERR_PARAM;
6452                                         }
6453                                         rte_memcpy(&mv_f[i].macaddr,
6454                                                         addr, ETH_ADDR_LEN);
6455                                         mv_f[i].vlan_id =
6456                                                 j * I40E_UINT32_BIT_SIZE + k;
6457                                         i++;
6458                                 }
6459                         }
6460                 }
6461         }
6462         return I40E_SUCCESS;
6463 }
6464
6465 static inline int
6466 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6467                            struct i40e_macvlan_filter *mv_f,
6468                            int num,
6469                            uint16_t vlan)
6470 {
6471         int i = 0;
6472         struct i40e_mac_filter *f;
6473
6474         if (num < vsi->mac_num)
6475                 return I40E_ERR_PARAM;
6476
6477         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6478                 if (i > num - 1) {
6479                         PMD_DRV_LOG(ERR, "buffer number not match");
6480                         return I40E_ERR_PARAM;
6481                 }
6482                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6483                                 ETH_ADDR_LEN);
6484                 mv_f[i].vlan_id = vlan;
6485                 mv_f[i].filter_type = f->mac_info.filter_type;
6486                 i++;
6487         }
6488
6489         return I40E_SUCCESS;
6490 }
6491
6492 static int
6493 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6494 {
6495         int i, j, num;
6496         struct i40e_mac_filter *f;
6497         struct i40e_macvlan_filter *mv_f;
6498         int ret = I40E_SUCCESS;
6499
6500         if (vsi == NULL || vsi->mac_num == 0)
6501                 return I40E_ERR_PARAM;
6502
6503         /* Case that no vlan is set */
6504         if (vsi->vlan_num == 0)
6505                 num = vsi->mac_num;
6506         else
6507                 num = vsi->mac_num * vsi->vlan_num;
6508
6509         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6510         if (mv_f == NULL) {
6511                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6512                 return I40E_ERR_NO_MEMORY;
6513         }
6514
6515         i = 0;
6516         if (vsi->vlan_num == 0) {
6517                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6518                         rte_memcpy(&mv_f[i].macaddr,
6519                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6520                         mv_f[i].filter_type = f->mac_info.filter_type;
6521                         mv_f[i].vlan_id = 0;
6522                         i++;
6523                 }
6524         } else {
6525                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6526                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6527                                         vsi->vlan_num, &f->mac_info.mac_addr);
6528                         if (ret != I40E_SUCCESS)
6529                                 goto DONE;
6530                         for (j = i; j < i + vsi->vlan_num; j++)
6531                                 mv_f[j].filter_type = f->mac_info.filter_type;
6532                         i += vsi->vlan_num;
6533                 }
6534         }
6535
6536         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6537 DONE:
6538         rte_free(mv_f);
6539
6540         return ret;
6541 }
6542
6543 int
6544 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6545 {
6546         struct i40e_macvlan_filter *mv_f;
6547         int mac_num;
6548         int ret = I40E_SUCCESS;
6549
6550         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6551                 return I40E_ERR_PARAM;
6552
6553         /* If it's already set, just return */
6554         if (i40e_find_vlan_filter(vsi,vlan))
6555                 return I40E_SUCCESS;
6556
6557         mac_num = vsi->mac_num;
6558
6559         if (mac_num == 0) {
6560                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6561                 return I40E_ERR_PARAM;
6562         }
6563
6564         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6565
6566         if (mv_f == NULL) {
6567                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6568                 return I40E_ERR_NO_MEMORY;
6569         }
6570
6571         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6572
6573         if (ret != I40E_SUCCESS)
6574                 goto DONE;
6575
6576         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6577
6578         if (ret != I40E_SUCCESS)
6579                 goto DONE;
6580
6581         i40e_set_vlan_filter(vsi, vlan, 1);
6582
6583         vsi->vlan_num++;
6584         ret = I40E_SUCCESS;
6585 DONE:
6586         rte_free(mv_f);
6587         return ret;
6588 }
6589
6590 int
6591 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6592 {
6593         struct i40e_macvlan_filter *mv_f;
6594         int mac_num;
6595         int ret = I40E_SUCCESS;
6596
6597         /**
6598          * Vlan 0 is the generic filter for untagged packets
6599          * and can't be removed.
6600          */
6601         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6602                 return I40E_ERR_PARAM;
6603
6604         /* If can't find it, just return */
6605         if (!i40e_find_vlan_filter(vsi, vlan))
6606                 return I40E_ERR_PARAM;
6607
6608         mac_num = vsi->mac_num;
6609
6610         if (mac_num == 0) {
6611                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6612                 return I40E_ERR_PARAM;
6613         }
6614
6615         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6616
6617         if (mv_f == NULL) {
6618                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6619                 return I40E_ERR_NO_MEMORY;
6620         }
6621
6622         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6623
6624         if (ret != I40E_SUCCESS)
6625                 goto DONE;
6626
6627         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6628
6629         if (ret != I40E_SUCCESS)
6630                 goto DONE;
6631
6632         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6633         if (vsi->vlan_num == 1) {
6634                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6635                 if (ret != I40E_SUCCESS)
6636                         goto DONE;
6637
6638                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6639                 if (ret != I40E_SUCCESS)
6640                         goto DONE;
6641         }
6642
6643         i40e_set_vlan_filter(vsi, vlan, 0);
6644
6645         vsi->vlan_num--;
6646         ret = I40E_SUCCESS;
6647 DONE:
6648         rte_free(mv_f);
6649         return ret;
6650 }
6651
6652 int
6653 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6654 {
6655         struct i40e_mac_filter *f;
6656         struct i40e_macvlan_filter *mv_f;
6657         int i, vlan_num = 0;
6658         int ret = I40E_SUCCESS;
6659
6660         /* If it's add and we've config it, return */
6661         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6662         if (f != NULL)
6663                 return I40E_SUCCESS;
6664         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6665                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6666
6667                 /**
6668                  * If vlan_num is 0, that's the first time to add mac,
6669                  * set mask for vlan_id 0.
6670                  */
6671                 if (vsi->vlan_num == 0) {
6672                         i40e_set_vlan_filter(vsi, 0, 1);
6673                         vsi->vlan_num = 1;
6674                 }
6675                 vlan_num = vsi->vlan_num;
6676         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6677                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6678                 vlan_num = 1;
6679
6680         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6681         if (mv_f == NULL) {
6682                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6683                 return I40E_ERR_NO_MEMORY;
6684         }
6685
6686         for (i = 0; i < vlan_num; i++) {
6687                 mv_f[i].filter_type = mac_filter->filter_type;
6688                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6689                                 ETH_ADDR_LEN);
6690         }
6691
6692         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6693                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6694                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6695                                         &mac_filter->mac_addr);
6696                 if (ret != I40E_SUCCESS)
6697                         goto DONE;
6698         }
6699
6700         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6701         if (ret != I40E_SUCCESS)
6702                 goto DONE;
6703
6704         /* Add the mac addr into mac list */
6705         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6706         if (f == NULL) {
6707                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6708                 ret = I40E_ERR_NO_MEMORY;
6709                 goto DONE;
6710         }
6711         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6712                         ETH_ADDR_LEN);
6713         f->mac_info.filter_type = mac_filter->filter_type;
6714         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6715         vsi->mac_num++;
6716
6717         ret = I40E_SUCCESS;
6718 DONE:
6719         rte_free(mv_f);
6720
6721         return ret;
6722 }
6723
6724 int
6725 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6726 {
6727         struct i40e_mac_filter *f;
6728         struct i40e_macvlan_filter *mv_f;
6729         int i, vlan_num;
6730         enum rte_mac_filter_type filter_type;
6731         int ret = I40E_SUCCESS;
6732
6733         /* Can't find it, return an error */
6734         f = i40e_find_mac_filter(vsi, addr);
6735         if (f == NULL)
6736                 return I40E_ERR_PARAM;
6737
6738         vlan_num = vsi->vlan_num;
6739         filter_type = f->mac_info.filter_type;
6740         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6741                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6742                 if (vlan_num == 0) {
6743                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6744                         return I40E_ERR_PARAM;
6745                 }
6746         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6747                         filter_type == RTE_MAC_HASH_MATCH)
6748                 vlan_num = 1;
6749
6750         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6751         if (mv_f == NULL) {
6752                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6753                 return I40E_ERR_NO_MEMORY;
6754         }
6755
6756         for (i = 0; i < vlan_num; i++) {
6757                 mv_f[i].filter_type = filter_type;
6758                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6759                                 ETH_ADDR_LEN);
6760         }
6761         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6762                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6763                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6764                 if (ret != I40E_SUCCESS)
6765                         goto DONE;
6766         }
6767
6768         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6769         if (ret != I40E_SUCCESS)
6770                 goto DONE;
6771
6772         /* Remove the mac addr into mac list */
6773         TAILQ_REMOVE(&vsi->mac_list, f, next);
6774         rte_free(f);
6775         vsi->mac_num--;
6776
6777         ret = I40E_SUCCESS;
6778 DONE:
6779         rte_free(mv_f);
6780         return ret;
6781 }
6782
6783 /* Configure hash enable flags for RSS */
6784 uint64_t
6785 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6786 {
6787         uint64_t hena = 0;
6788         int i;
6789
6790         if (!flags)
6791                 return hena;
6792
6793         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6794                 if (flags & (1ULL << i))
6795                         hena |= adapter->pctypes_tbl[i];
6796         }
6797
6798         return hena;
6799 }
6800
6801 /* Parse the hash enable flags */
6802 uint64_t
6803 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6804 {
6805         uint64_t rss_hf = 0;
6806
6807         if (!flags)
6808                 return rss_hf;
6809         int i;
6810
6811         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6812                 if (flags & adapter->pctypes_tbl[i])
6813                         rss_hf |= (1ULL << i);
6814         }
6815         return rss_hf;
6816 }
6817
6818 /* Disable RSS */
6819 static void
6820 i40e_pf_disable_rss(struct i40e_pf *pf)
6821 {
6822         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6823
6824         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6825         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6826         I40E_WRITE_FLUSH(hw);
6827 }
6828
6829 int
6830 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6831 {
6832         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6833         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6834         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6835                            I40E_VFQF_HKEY_MAX_INDEX :
6836                            I40E_PFQF_HKEY_MAX_INDEX;
6837         int ret = 0;
6838
6839         if (!key || key_len == 0) {
6840                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6841                 return 0;
6842         } else if (key_len != (key_idx + 1) *
6843                 sizeof(uint32_t)) {
6844                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6845                 return -EINVAL;
6846         }
6847
6848         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6849                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6850                         (struct i40e_aqc_get_set_rss_key_data *)key;
6851
6852                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6853                 if (ret)
6854                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6855         } else {
6856                 uint32_t *hash_key = (uint32_t *)key;
6857                 uint16_t i;
6858
6859                 if (vsi->type == I40E_VSI_SRIOV) {
6860                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6861                                 I40E_WRITE_REG(
6862                                         hw,
6863                                         I40E_VFQF_HKEY1(i, vsi->user_param),
6864                                         hash_key[i]);
6865
6866                 } else {
6867                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6868                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6869                                                hash_key[i]);
6870                 }
6871                 I40E_WRITE_FLUSH(hw);
6872         }
6873
6874         return ret;
6875 }
6876
6877 static int
6878 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6879 {
6880         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6881         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6882         uint32_t reg;
6883         int ret;
6884
6885         if (!key || !key_len)
6886                 return -EINVAL;
6887
6888         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6889                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6890                         (struct i40e_aqc_get_set_rss_key_data *)key);
6891                 if (ret) {
6892                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6893                         return ret;
6894                 }
6895         } else {
6896                 uint32_t *key_dw = (uint32_t *)key;
6897                 uint16_t i;
6898
6899                 if (vsi->type == I40E_VSI_SRIOV) {
6900                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6901                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6902                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6903                         }
6904                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6905                                    sizeof(uint32_t);
6906                 } else {
6907                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6908                                 reg = I40E_PFQF_HKEY(i);
6909                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6910                         }
6911                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6912                                    sizeof(uint32_t);
6913                 }
6914         }
6915         return 0;
6916 }
6917
6918 static int
6919 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6920 {
6921         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6922         uint64_t hena;
6923         int ret;
6924
6925         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6926                                rss_conf->rss_key_len);
6927         if (ret)
6928                 return ret;
6929
6930         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6931         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6932         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6933         I40E_WRITE_FLUSH(hw);
6934
6935         return 0;
6936 }
6937
6938 static int
6939 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6940                          struct rte_eth_rss_conf *rss_conf)
6941 {
6942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6944         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6945         uint64_t hena;
6946
6947         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6948         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6949
6950         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6951                 if (rss_hf != 0) /* Enable RSS */
6952                         return -EINVAL;
6953                 return 0; /* Nothing to do */
6954         }
6955         /* RSS enabled */
6956         if (rss_hf == 0) /* Disable RSS */
6957                 return -EINVAL;
6958
6959         return i40e_hw_rss_hash_set(pf, rss_conf);
6960 }
6961
6962 static int
6963 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6964                            struct rte_eth_rss_conf *rss_conf)
6965 {
6966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6968         uint64_t hena;
6969
6970         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6971                          &rss_conf->rss_key_len);
6972
6973         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6974         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6975         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6976
6977         return 0;
6978 }
6979
6980 static int
6981 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6982 {
6983         switch (filter_type) {
6984         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6985                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6986                 break;
6987         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6988                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6989                 break;
6990         case RTE_TUNNEL_FILTER_IMAC_TENID:
6991                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6992                 break;
6993         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6994                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6995                 break;
6996         case ETH_TUNNEL_FILTER_IMAC:
6997                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6998                 break;
6999         case ETH_TUNNEL_FILTER_OIP:
7000                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7001                 break;
7002         case ETH_TUNNEL_FILTER_IIP:
7003                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7004                 break;
7005         default:
7006                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7007                 return -EINVAL;
7008         }
7009
7010         return 0;
7011 }
7012
7013 /* Convert tunnel filter structure */
7014 static int
7015 i40e_tunnel_filter_convert(
7016         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7017         struct i40e_tunnel_filter *tunnel_filter)
7018 {
7019         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7020                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7021         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7022                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7023         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7024         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7025              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7026             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7027                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7028         else
7029                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7030         tunnel_filter->input.flags = cld_filter->element.flags;
7031         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7032         tunnel_filter->queue = cld_filter->element.queue_number;
7033         rte_memcpy(tunnel_filter->input.general_fields,
7034                    cld_filter->general_fields,
7035                    sizeof(cld_filter->general_fields));
7036
7037         return 0;
7038 }
7039
7040 /* Check if there exists the tunnel filter */
7041 struct i40e_tunnel_filter *
7042 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7043                              const struct i40e_tunnel_filter_input *input)
7044 {
7045         int ret;
7046
7047         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7048         if (ret < 0)
7049                 return NULL;
7050
7051         return tunnel_rule->hash_map[ret];
7052 }
7053
7054 /* Add a tunnel filter into the SW list */
7055 static int
7056 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7057                              struct i40e_tunnel_filter *tunnel_filter)
7058 {
7059         struct i40e_tunnel_rule *rule = &pf->tunnel;
7060         int ret;
7061
7062         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7063         if (ret < 0) {
7064                 PMD_DRV_LOG(ERR,
7065                             "Failed to insert tunnel filter to hash table %d!",
7066                             ret);
7067                 return ret;
7068         }
7069         rule->hash_map[ret] = tunnel_filter;
7070
7071         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7072
7073         return 0;
7074 }
7075
7076 /* Delete a tunnel filter from the SW list */
7077 int
7078 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7079                           struct i40e_tunnel_filter_input *input)
7080 {
7081         struct i40e_tunnel_rule *rule = &pf->tunnel;
7082         struct i40e_tunnel_filter *tunnel_filter;
7083         int ret;
7084
7085         ret = rte_hash_del_key(rule->hash_table, input);
7086         if (ret < 0) {
7087                 PMD_DRV_LOG(ERR,
7088                             "Failed to delete tunnel filter to hash table %d!",
7089                             ret);
7090                 return ret;
7091         }
7092         tunnel_filter = rule->hash_map[ret];
7093         rule->hash_map[ret] = NULL;
7094
7095         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7096         rte_free(tunnel_filter);
7097
7098         return 0;
7099 }
7100
7101 int
7102 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7103                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7104                         uint8_t add)
7105 {
7106         uint16_t ip_type;
7107         uint32_t ipv4_addr, ipv4_addr_le;
7108         uint8_t i, tun_type = 0;
7109         /* internal varialbe to convert ipv6 byte order */
7110         uint32_t convert_ipv6[4];
7111         int val, ret = 0;
7112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7113         struct i40e_vsi *vsi = pf->main_vsi;
7114         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7115         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7116         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7117         struct i40e_tunnel_filter *tunnel, *node;
7118         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7119
7120         cld_filter = rte_zmalloc("tunnel_filter",
7121                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7122         0);
7123
7124         if (NULL == cld_filter) {
7125                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7126                 return -ENOMEM;
7127         }
7128         pfilter = cld_filter;
7129
7130         ether_addr_copy(&tunnel_filter->outer_mac,
7131                         (struct ether_addr *)&pfilter->element.outer_mac);
7132         ether_addr_copy(&tunnel_filter->inner_mac,
7133                         (struct ether_addr *)&pfilter->element.inner_mac);
7134
7135         pfilter->element.inner_vlan =
7136                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7137         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7138                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7139                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7140                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7141                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7142                                 &ipv4_addr_le,
7143                                 sizeof(pfilter->element.ipaddr.v4.data));
7144         } else {
7145                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7146                 for (i = 0; i < 4; i++) {
7147                         convert_ipv6[i] =
7148                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7149                 }
7150                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7151                            &convert_ipv6,
7152                            sizeof(pfilter->element.ipaddr.v6.data));
7153         }
7154
7155         /* check tunneled type */
7156         switch (tunnel_filter->tunnel_type) {
7157         case RTE_TUNNEL_TYPE_VXLAN:
7158                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7159                 break;
7160         case RTE_TUNNEL_TYPE_NVGRE:
7161                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7162                 break;
7163         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7164                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7165                 break;
7166         default:
7167                 /* Other tunnel types is not supported. */
7168                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7169                 rte_free(cld_filter);
7170                 return -EINVAL;
7171         }
7172
7173         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7174                                        &pfilter->element.flags);
7175         if (val < 0) {
7176                 rte_free(cld_filter);
7177                 return -EINVAL;
7178         }
7179
7180         pfilter->element.flags |= rte_cpu_to_le_16(
7181                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7182                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7183         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7184         pfilter->element.queue_number =
7185                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7186
7187         /* Check if there is the filter in SW list */
7188         memset(&check_filter, 0, sizeof(check_filter));
7189         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7190         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7191         if (add && node) {
7192                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7193                 rte_free(cld_filter);
7194                 return -EINVAL;
7195         }
7196
7197         if (!add && !node) {
7198                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7199                 rte_free(cld_filter);
7200                 return -EINVAL;
7201         }
7202
7203         if (add) {
7204                 ret = i40e_aq_add_cloud_filters(hw,
7205                                         vsi->seid, &cld_filter->element, 1);
7206                 if (ret < 0) {
7207                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7208                         rte_free(cld_filter);
7209                         return -ENOTSUP;
7210                 }
7211                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7212                 if (tunnel == NULL) {
7213                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7214                         rte_free(cld_filter);
7215                         return -ENOMEM;
7216                 }
7217
7218                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7219                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7220                 if (ret < 0)
7221                         rte_free(tunnel);
7222         } else {
7223                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7224                                                    &cld_filter->element, 1);
7225                 if (ret < 0) {
7226                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7227                         rte_free(cld_filter);
7228                         return -ENOTSUP;
7229                 }
7230                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7231         }
7232
7233         rte_free(cld_filter);
7234         return ret;
7235 }
7236
7237 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7238 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7239 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7240 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7241 #define I40E_TR_GRE_KEY_MASK                    0x400
7242 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7243 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7244
7245 static enum
7246 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7247 {
7248         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7249         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7251         enum i40e_status_code status = I40E_SUCCESS;
7252
7253         memset(&filter_replace, 0,
7254                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7255         memset(&filter_replace_buf, 0,
7256                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7257
7258         /* create L1 filter */
7259         filter_replace.old_filter_type =
7260                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7261         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7262         filter_replace.tr_bit = 0;
7263
7264         /* Prepare the buffer, 3 entries */
7265         filter_replace_buf.data[0] =
7266                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7267         filter_replace_buf.data[0] |=
7268                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7269         filter_replace_buf.data[2] = 0xFF;
7270         filter_replace_buf.data[3] = 0xFF;
7271         filter_replace_buf.data[4] =
7272                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7273         filter_replace_buf.data[4] |=
7274                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7275         filter_replace_buf.data[7] = 0xF0;
7276         filter_replace_buf.data[8]
7277                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7278         filter_replace_buf.data[8] |=
7279                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7280         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7281                 I40E_TR_GENEVE_KEY_MASK |
7282                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7283         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7284                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7285                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7286
7287         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7288                                                &filter_replace_buf);
7289         return status;
7290 }
7291
7292 static enum
7293 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7294 {
7295         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7296         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7297         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7298         enum i40e_status_code status = I40E_SUCCESS;
7299
7300         /* For MPLSoUDP */
7301         memset(&filter_replace, 0,
7302                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7303         memset(&filter_replace_buf, 0,
7304                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7305         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7306                 I40E_AQC_MIRROR_CLOUD_FILTER;
7307         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7308         filter_replace.new_filter_type =
7309                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7310         /* Prepare the buffer, 2 entries */
7311         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7312         filter_replace_buf.data[0] |=
7313                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7314         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7315         filter_replace_buf.data[4] |=
7316                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7317         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7318                                                &filter_replace_buf);
7319         if (status < 0)
7320                 return status;
7321
7322         /* For MPLSoGRE */
7323         memset(&filter_replace, 0,
7324                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7325         memset(&filter_replace_buf, 0,
7326                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7327
7328         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7329                 I40E_AQC_MIRROR_CLOUD_FILTER;
7330         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7331         filter_replace.new_filter_type =
7332                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7333         /* Prepare the buffer, 2 entries */
7334         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7335         filter_replace_buf.data[0] |=
7336                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7337         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7338         filter_replace_buf.data[4] |=
7339                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7340
7341         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7342                                                &filter_replace_buf);
7343         return status;
7344 }
7345
7346 static enum i40e_status_code
7347 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7348 {
7349         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7350         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7351         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7352         enum i40e_status_code status = I40E_SUCCESS;
7353
7354         /* For GTP-C */
7355         memset(&filter_replace, 0,
7356                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7357         memset(&filter_replace_buf, 0,
7358                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7359         /* create L1 filter */
7360         filter_replace.old_filter_type =
7361                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7362         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7363         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7364                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7365         /* Prepare the buffer, 2 entries */
7366         filter_replace_buf.data[0] =
7367                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7368         filter_replace_buf.data[0] |=
7369                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7370         filter_replace_buf.data[2] = 0xFF;
7371         filter_replace_buf.data[3] = 0xFF;
7372         filter_replace_buf.data[4] =
7373                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7374         filter_replace_buf.data[4] |=
7375                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7376         filter_replace_buf.data[6] = 0xFF;
7377         filter_replace_buf.data[7] = 0xFF;
7378         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7379                                                &filter_replace_buf);
7380         if (status < 0)
7381                 return status;
7382
7383         /* for GTP-U */
7384         memset(&filter_replace, 0,
7385                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7386         memset(&filter_replace_buf, 0,
7387                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7388         /* create L1 filter */
7389         filter_replace.old_filter_type =
7390                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7391         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7392         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7393                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7394         /* Prepare the buffer, 2 entries */
7395         filter_replace_buf.data[0] =
7396                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7397         filter_replace_buf.data[0] |=
7398                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7399         filter_replace_buf.data[2] = 0xFF;
7400         filter_replace_buf.data[3] = 0xFF;
7401         filter_replace_buf.data[4] =
7402                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7403         filter_replace_buf.data[4] |=
7404                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7405         filter_replace_buf.data[6] = 0xFF;
7406         filter_replace_buf.data[7] = 0xFF;
7407
7408         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7409                                                &filter_replace_buf);
7410         return status;
7411 }
7412
7413 static enum
7414 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7415 {
7416         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7417         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7419         enum i40e_status_code status = I40E_SUCCESS;
7420
7421         /* for GTP-C */
7422         memset(&filter_replace, 0,
7423                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7424         memset(&filter_replace_buf, 0,
7425                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7426         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7427         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7428         filter_replace.new_filter_type =
7429                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7430         /* Prepare the buffer, 2 entries */
7431         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7432         filter_replace_buf.data[0] |=
7433                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7434         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7435         filter_replace_buf.data[4] |=
7436                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7437         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7438                                                &filter_replace_buf);
7439         if (status < 0)
7440                 return status;
7441
7442         /* for GTP-U */
7443         memset(&filter_replace, 0,
7444                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7445         memset(&filter_replace_buf, 0,
7446                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7447         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7448         filter_replace.old_filter_type =
7449                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7450         filter_replace.new_filter_type =
7451                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7452         /* Prepare the buffer, 2 entries */
7453         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7454         filter_replace_buf.data[0] |=
7455                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7456         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7457         filter_replace_buf.data[4] |=
7458                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7459
7460         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7461                                                &filter_replace_buf);
7462         return status;
7463 }
7464
7465 int
7466 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7467                       struct i40e_tunnel_filter_conf *tunnel_filter,
7468                       uint8_t add)
7469 {
7470         uint16_t ip_type;
7471         uint32_t ipv4_addr, ipv4_addr_le;
7472         uint8_t i, tun_type = 0;
7473         /* internal variable to convert ipv6 byte order */
7474         uint32_t convert_ipv6[4];
7475         int val, ret = 0;
7476         struct i40e_pf_vf *vf = NULL;
7477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7478         struct i40e_vsi *vsi;
7479         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7480         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7481         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7482         struct i40e_tunnel_filter *tunnel, *node;
7483         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7484         uint32_t teid_le;
7485         bool big_buffer = 0;
7486
7487         cld_filter = rte_zmalloc("tunnel_filter",
7488                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7489                          0);
7490
7491         if (cld_filter == NULL) {
7492                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7493                 return -ENOMEM;
7494         }
7495         pfilter = cld_filter;
7496
7497         ether_addr_copy(&tunnel_filter->outer_mac,
7498                         (struct ether_addr *)&pfilter->element.outer_mac);
7499         ether_addr_copy(&tunnel_filter->inner_mac,
7500                         (struct ether_addr *)&pfilter->element.inner_mac);
7501
7502         pfilter->element.inner_vlan =
7503                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7504         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7505                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7506                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7507                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7508                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7509                                 &ipv4_addr_le,
7510                                 sizeof(pfilter->element.ipaddr.v4.data));
7511         } else {
7512                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7513                 for (i = 0; i < 4; i++) {
7514                         convert_ipv6[i] =
7515                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7516                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7517                 }
7518                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7519                            &convert_ipv6,
7520                            sizeof(pfilter->element.ipaddr.v6.data));
7521         }
7522
7523         /* check tunneled type */
7524         switch (tunnel_filter->tunnel_type) {
7525         case I40E_TUNNEL_TYPE_VXLAN:
7526                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7527                 break;
7528         case I40E_TUNNEL_TYPE_NVGRE:
7529                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7530                 break;
7531         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7532                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7533                 break;
7534         case I40E_TUNNEL_TYPE_MPLSoUDP:
7535                 if (!pf->mpls_replace_flag) {
7536                         i40e_replace_mpls_l1_filter(pf);
7537                         i40e_replace_mpls_cloud_filter(pf);
7538                         pf->mpls_replace_flag = 1;
7539                 }
7540                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7541                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7542                         teid_le >> 4;
7543                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7544                         (teid_le & 0xF) << 12;
7545                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7546                         0x40;
7547                 big_buffer = 1;
7548                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7549                 break;
7550         case I40E_TUNNEL_TYPE_MPLSoGRE:
7551                 if (!pf->mpls_replace_flag) {
7552                         i40e_replace_mpls_l1_filter(pf);
7553                         i40e_replace_mpls_cloud_filter(pf);
7554                         pf->mpls_replace_flag = 1;
7555                 }
7556                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7557                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7558                         teid_le >> 4;
7559                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7560                         (teid_le & 0xF) << 12;
7561                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7562                         0x0;
7563                 big_buffer = 1;
7564                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7565                 break;
7566         case I40E_TUNNEL_TYPE_GTPC:
7567                 if (!pf->gtp_replace_flag) {
7568                         i40e_replace_gtp_l1_filter(pf);
7569                         i40e_replace_gtp_cloud_filter(pf);
7570                         pf->gtp_replace_flag = 1;
7571                 }
7572                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7573                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7574                         (teid_le >> 16) & 0xFFFF;
7575                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7576                         teid_le & 0xFFFF;
7577                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7578                         0x0;
7579                 big_buffer = 1;
7580                 break;
7581         case I40E_TUNNEL_TYPE_GTPU:
7582                 if (!pf->gtp_replace_flag) {
7583                         i40e_replace_gtp_l1_filter(pf);
7584                         i40e_replace_gtp_cloud_filter(pf);
7585                         pf->gtp_replace_flag = 1;
7586                 }
7587                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7588                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7589                         (teid_le >> 16) & 0xFFFF;
7590                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7591                         teid_le & 0xFFFF;
7592                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7593                         0x0;
7594                 big_buffer = 1;
7595                 break;
7596         case I40E_TUNNEL_TYPE_QINQ:
7597                 if (!pf->qinq_replace_flag) {
7598                         ret = i40e_cloud_filter_qinq_create(pf);
7599                         if (ret < 0)
7600                                 PMD_DRV_LOG(DEBUG,
7601                                             "QinQ tunnel filter already created.");
7602                         pf->qinq_replace_flag = 1;
7603                 }
7604                 /*      Add in the General fields the values of
7605                  *      the Outer and Inner VLAN
7606                  *      Big Buffer should be set, see changes in
7607                  *      i40e_aq_add_cloud_filters
7608                  */
7609                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7610                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7611                 big_buffer = 1;
7612                 break;
7613         default:
7614                 /* Other tunnel types is not supported. */
7615                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7616                 rte_free(cld_filter);
7617                 return -EINVAL;
7618         }
7619
7620         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7621                 pfilter->element.flags =
7622                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7623         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7624                 pfilter->element.flags =
7625                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7626         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7627                 pfilter->element.flags =
7628                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7629         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7630                 pfilter->element.flags =
7631                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7632         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7633                 pfilter->element.flags |=
7634                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7635         else {
7636                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7637                                                 &pfilter->element.flags);
7638                 if (val < 0) {
7639                         rte_free(cld_filter);
7640                         return -EINVAL;
7641                 }
7642         }
7643
7644         pfilter->element.flags |= rte_cpu_to_le_16(
7645                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7646                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7647         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7648         pfilter->element.queue_number =
7649                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7650
7651         if (!tunnel_filter->is_to_vf)
7652                 vsi = pf->main_vsi;
7653         else {
7654                 if (tunnel_filter->vf_id >= pf->vf_num) {
7655                         PMD_DRV_LOG(ERR, "Invalid argument.");
7656                         rte_free(cld_filter);
7657                         return -EINVAL;
7658                 }
7659                 vf = &pf->vfs[tunnel_filter->vf_id];
7660                 vsi = vf->vsi;
7661         }
7662
7663         /* Check if there is the filter in SW list */
7664         memset(&check_filter, 0, sizeof(check_filter));
7665         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7666         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7667         check_filter.vf_id = tunnel_filter->vf_id;
7668         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7669         if (add && node) {
7670                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7671                 rte_free(cld_filter);
7672                 return -EINVAL;
7673         }
7674
7675         if (!add && !node) {
7676                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7677                 rte_free(cld_filter);
7678                 return -EINVAL;
7679         }
7680
7681         if (add) {
7682                 if (big_buffer)
7683                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7684                                                    vsi->seid, cld_filter, 1);
7685                 else
7686                         ret = i40e_aq_add_cloud_filters(hw,
7687                                         vsi->seid, &cld_filter->element, 1);
7688                 if (ret < 0) {
7689                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7690                         rte_free(cld_filter);
7691                         return -ENOTSUP;
7692                 }
7693                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7694                 if (tunnel == NULL) {
7695                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7696                         rte_free(cld_filter);
7697                         return -ENOMEM;
7698                 }
7699
7700                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7701                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7702                 if (ret < 0)
7703                         rte_free(tunnel);
7704         } else {
7705                 if (big_buffer)
7706                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7707                                 hw, vsi->seid, cld_filter, 1);
7708                 else
7709                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7710                                                    &cld_filter->element, 1);
7711                 if (ret < 0) {
7712                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7713                         rte_free(cld_filter);
7714                         return -ENOTSUP;
7715                 }
7716                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7717         }
7718
7719         rte_free(cld_filter);
7720         return ret;
7721 }
7722
7723 static int
7724 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7725 {
7726         uint8_t i;
7727
7728         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7729                 if (pf->vxlan_ports[i] == port)
7730                         return i;
7731         }
7732
7733         return -1;
7734 }
7735
7736 static int
7737 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7738 {
7739         int  idx, ret;
7740         uint8_t filter_idx;
7741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7742
7743         idx = i40e_get_vxlan_port_idx(pf, port);
7744
7745         /* Check if port already exists */
7746         if (idx >= 0) {
7747                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7748                 return -EINVAL;
7749         }
7750
7751         /* Now check if there is space to add the new port */
7752         idx = i40e_get_vxlan_port_idx(pf, 0);
7753         if (idx < 0) {
7754                 PMD_DRV_LOG(ERR,
7755                         "Maximum number of UDP ports reached, not adding port %d",
7756                         port);
7757                 return -ENOSPC;
7758         }
7759
7760         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7761                                         &filter_idx, NULL);
7762         if (ret < 0) {
7763                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7764                 return -1;
7765         }
7766
7767         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7768                          port,  filter_idx);
7769
7770         /* New port: add it and mark its index in the bitmap */
7771         pf->vxlan_ports[idx] = port;
7772         pf->vxlan_bitmap |= (1 << idx);
7773
7774         if (!(pf->flags & I40E_FLAG_VXLAN))
7775                 pf->flags |= I40E_FLAG_VXLAN;
7776
7777         return 0;
7778 }
7779
7780 static int
7781 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7782 {
7783         int idx;
7784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7785
7786         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7787                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7788                 return -EINVAL;
7789         }
7790
7791         idx = i40e_get_vxlan_port_idx(pf, port);
7792
7793         if (idx < 0) {
7794                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7795                 return -EINVAL;
7796         }
7797
7798         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7799                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7800                 return -1;
7801         }
7802
7803         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7804                         port, idx);
7805
7806         pf->vxlan_ports[idx] = 0;
7807         pf->vxlan_bitmap &= ~(1 << idx);
7808
7809         if (!pf->vxlan_bitmap)
7810                 pf->flags &= ~I40E_FLAG_VXLAN;
7811
7812         return 0;
7813 }
7814
7815 /* Add UDP tunneling port */
7816 static int
7817 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7818                              struct rte_eth_udp_tunnel *udp_tunnel)
7819 {
7820         int ret = 0;
7821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7822
7823         if (udp_tunnel == NULL)
7824                 return -EINVAL;
7825
7826         switch (udp_tunnel->prot_type) {
7827         case RTE_TUNNEL_TYPE_VXLAN:
7828                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7829                 break;
7830
7831         case RTE_TUNNEL_TYPE_GENEVE:
7832         case RTE_TUNNEL_TYPE_TEREDO:
7833                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7834                 ret = -1;
7835                 break;
7836
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -1;
7840                 break;
7841         }
7842
7843         return ret;
7844 }
7845
7846 /* Remove UDP tunneling port */
7847 static int
7848 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7849                              struct rte_eth_udp_tunnel *udp_tunnel)
7850 {
7851         int ret = 0;
7852         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7853
7854         if (udp_tunnel == NULL)
7855                 return -EINVAL;
7856
7857         switch (udp_tunnel->prot_type) {
7858         case RTE_TUNNEL_TYPE_VXLAN:
7859                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7860                 break;
7861         case RTE_TUNNEL_TYPE_GENEVE:
7862         case RTE_TUNNEL_TYPE_TEREDO:
7863                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7864                 ret = -1;
7865                 break;
7866         default:
7867                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7868                 ret = -1;
7869                 break;
7870         }
7871
7872         return ret;
7873 }
7874
7875 /* Calculate the maximum number of contiguous PF queues that are configured */
7876 static int
7877 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7878 {
7879         struct rte_eth_dev_data *data = pf->dev_data;
7880         int i, num;
7881         struct i40e_rx_queue *rxq;
7882
7883         num = 0;
7884         for (i = 0; i < pf->lan_nb_qps; i++) {
7885                 rxq = data->rx_queues[i];
7886                 if (rxq && rxq->q_set)
7887                         num++;
7888                 else
7889                         break;
7890         }
7891
7892         return num;
7893 }
7894
7895 /* Configure RSS */
7896 static int
7897 i40e_pf_config_rss(struct i40e_pf *pf)
7898 {
7899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7900         struct rte_eth_rss_conf rss_conf;
7901         uint32_t i, lut = 0;
7902         uint16_t j, num;
7903
7904         /*
7905          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7906          * It's necessary to calculate the actual PF queues that are configured.
7907          */
7908         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7909                 num = i40e_pf_calc_configured_queues_num(pf);
7910         else
7911                 num = pf->dev_data->nb_rx_queues;
7912
7913         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7914         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7915                         num);
7916
7917         if (num == 0) {
7918                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7919                 return -ENOTSUP;
7920         }
7921
7922         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7923                 if (j == num)
7924                         j = 0;
7925                 lut = (lut << 8) | (j & ((0x1 <<
7926                         hw->func_caps.rss_table_entry_width) - 1));
7927                 if ((i & 3) == 3)
7928                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7929         }
7930
7931         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7932         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7933                 i40e_pf_disable_rss(pf);
7934                 return 0;
7935         }
7936         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7937                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7938                 /* Random default keys */
7939                 static uint32_t rss_key_default[] = {0x6b793944,
7940                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7941                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7942                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7943
7944                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7945                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7946                                                         sizeof(uint32_t);
7947         }
7948
7949         return i40e_hw_rss_hash_set(pf, &rss_conf);
7950 }
7951
7952 static int
7953 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7954                                struct rte_eth_tunnel_filter_conf *filter)
7955 {
7956         if (pf == NULL || filter == NULL) {
7957                 PMD_DRV_LOG(ERR, "Invalid parameter");
7958                 return -EINVAL;
7959         }
7960
7961         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7962                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7963                 return -EINVAL;
7964         }
7965
7966         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7967                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7968                 return -EINVAL;
7969         }
7970
7971         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7972                 (is_zero_ether_addr(&filter->outer_mac))) {
7973                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7974                 return -EINVAL;
7975         }
7976
7977         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7978                 (is_zero_ether_addr(&filter->inner_mac))) {
7979                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7980                 return -EINVAL;
7981         }
7982
7983         return 0;
7984 }
7985
7986 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7987 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7988 static int
7989 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7990 {
7991         uint32_t val, reg;
7992         int ret = -EINVAL;
7993
7994         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7995         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7996
7997         if (len == 3) {
7998                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7999         } else if (len == 4) {
8000                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8001         } else {
8002                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8003                 return ret;
8004         }
8005
8006         if (reg != val) {
8007                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8008                                                    reg, NULL);
8009                 if (ret != 0)
8010                         return ret;
8011         } else {
8012                 ret = 0;
8013         }
8014         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8015                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8016
8017         return ret;
8018 }
8019
8020 static int
8021 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8022 {
8023         int ret = -EINVAL;
8024
8025         if (!hw || !cfg)
8026                 return -EINVAL;
8027
8028         switch (cfg->cfg_type) {
8029         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8030                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8031                 break;
8032         default:
8033                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8034                 break;
8035         }
8036
8037         return ret;
8038 }
8039
8040 static int
8041 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8042                                enum rte_filter_op filter_op,
8043                                void *arg)
8044 {
8045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046         int ret = I40E_ERR_PARAM;
8047
8048         switch (filter_op) {
8049         case RTE_ETH_FILTER_SET:
8050                 ret = i40e_dev_global_config_set(hw,
8051                         (struct rte_eth_global_cfg *)arg);
8052                 break;
8053         default:
8054                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8055                 break;
8056         }
8057
8058         return ret;
8059 }
8060
8061 static int
8062 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8063                           enum rte_filter_op filter_op,
8064                           void *arg)
8065 {
8066         struct rte_eth_tunnel_filter_conf *filter;
8067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8068         int ret = I40E_SUCCESS;
8069
8070         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8071
8072         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8073                 return I40E_ERR_PARAM;
8074
8075         switch (filter_op) {
8076         case RTE_ETH_FILTER_NOP:
8077                 if (!(pf->flags & I40E_FLAG_VXLAN))
8078                         ret = I40E_NOT_SUPPORTED;
8079                 break;
8080         case RTE_ETH_FILTER_ADD:
8081                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8082                 break;
8083         case RTE_ETH_FILTER_DELETE:
8084                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8085                 break;
8086         default:
8087                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8088                 ret = I40E_ERR_PARAM;
8089                 break;
8090         }
8091
8092         return ret;
8093 }
8094
8095 static int
8096 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8097 {
8098         int ret = 0;
8099         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8100
8101         /* RSS setup */
8102         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8103                 ret = i40e_pf_config_rss(pf);
8104         else
8105                 i40e_pf_disable_rss(pf);
8106
8107         return ret;
8108 }
8109
8110 /* Get the symmetric hash enable configurations per port */
8111 static void
8112 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8113 {
8114         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8115
8116         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8117 }
8118
8119 /* Set the symmetric hash enable configurations per port */
8120 static void
8121 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8122 {
8123         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8124
8125         if (enable > 0) {
8126                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8127                         PMD_DRV_LOG(INFO,
8128                                 "Symmetric hash has already been enabled");
8129                         return;
8130                 }
8131                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8132         } else {
8133                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8134                         PMD_DRV_LOG(INFO,
8135                                 "Symmetric hash has already been disabled");
8136                         return;
8137                 }
8138                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8139         }
8140         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8141         I40E_WRITE_FLUSH(hw);
8142 }
8143
8144 /*
8145  * Get global configurations of hash function type and symmetric hash enable
8146  * per flow type (pctype). Note that global configuration means it affects all
8147  * the ports on the same NIC.
8148  */
8149 static int
8150 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8151                                    struct rte_eth_hash_global_conf *g_cfg)
8152 {
8153         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8154         uint32_t reg;
8155         uint16_t i, j;
8156
8157         memset(g_cfg, 0, sizeof(*g_cfg));
8158         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8159         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8160                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8161         else
8162                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8163         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8164                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8165
8166         /*
8167          * As i40e supports less than 64 flow types, only first 64 bits need to
8168          * be checked.
8169          */
8170         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8171                 g_cfg->valid_bit_mask[i] = 0ULL;
8172                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8173         }
8174
8175         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8176
8177         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8178                 if (!adapter->pctypes_tbl[i])
8179                         continue;
8180                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8181                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8182                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8183                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8184                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8185                                         g_cfg->sym_hash_enable_mask[0] |=
8186                                                                 (1ULL << i);
8187                                 }
8188                         }
8189                 }
8190         }
8191
8192         return 0;
8193 }
8194
8195 static int
8196 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8197                               const struct rte_eth_hash_global_conf *g_cfg)
8198 {
8199         uint32_t i;
8200         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8201
8202         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8203                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8204                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8205                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8206                                                 g_cfg->hash_func);
8207                 return -EINVAL;
8208         }
8209
8210         /*
8211          * As i40e supports less than 64 flow types, only first 64 bits need to
8212          * be checked.
8213          */
8214         mask0 = g_cfg->valid_bit_mask[0];
8215         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8216                 if (i == 0) {
8217                         /* Check if any unsupported flow type configured */
8218                         if ((mask0 | i40e_mask) ^ i40e_mask)
8219                                 goto mask_err;
8220                 } else {
8221                         if (g_cfg->valid_bit_mask[i])
8222                                 goto mask_err;
8223                 }
8224         }
8225
8226         return 0;
8227
8228 mask_err:
8229         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8230
8231         return -EINVAL;
8232 }
8233
8234 /*
8235  * Set global configurations of hash function type and symmetric hash enable
8236  * per flow type (pctype). Note any modifying global configuration will affect
8237  * all the ports on the same NIC.
8238  */
8239 static int
8240 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8241                                    struct rte_eth_hash_global_conf *g_cfg)
8242 {
8243         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8244         int ret;
8245         uint16_t i, j;
8246         uint32_t reg;
8247         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8248
8249         /* Check the input parameters */
8250         ret = i40e_hash_global_config_check(adapter, g_cfg);
8251         if (ret < 0)
8252                 return ret;
8253
8254         /*
8255          * As i40e supports less than 64 flow types, only first 64 bits need to
8256          * be configured.
8257          */
8258         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8259                 if (mask0 & (1UL << i)) {
8260                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8261                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8262
8263                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8264                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8265                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8266                                         i40e_write_rx_ctl(hw,
8267                                                           I40E_GLQF_HSYM(j),
8268                                                           reg);
8269                         }
8270                 }
8271         }
8272
8273         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8274         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8275                 /* Toeplitz */
8276                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8277                         PMD_DRV_LOG(DEBUG,
8278                                 "Hash function already set to Toeplitz");
8279                         goto out;
8280                 }
8281                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8282         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8283                 /* Simple XOR */
8284                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8285                         PMD_DRV_LOG(DEBUG,
8286                                 "Hash function already set to Simple XOR");
8287                         goto out;
8288                 }
8289                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8290         } else
8291                 /* Use the default, and keep it as it is */
8292                 goto out;
8293
8294         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8295
8296 out:
8297         I40E_WRITE_FLUSH(hw);
8298
8299         return 0;
8300 }
8301
8302 /**
8303  * Valid input sets for hash and flow director filters per PCTYPE
8304  */
8305 static uint64_t
8306 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8307                 enum rte_filter_type filter)
8308 {
8309         uint64_t valid;
8310
8311         static const uint64_t valid_hash_inset_table[] = {
8312                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8313                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8314                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8315                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8316                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8317                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8318                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8319                         I40E_INSET_FLEX_PAYLOAD,
8320                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8321                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8322                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8323                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8324                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8325                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8326                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8327                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8328                         I40E_INSET_FLEX_PAYLOAD,
8329                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8330                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8331                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8332                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8333                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8334                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8335                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8336                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8337                         I40E_INSET_FLEX_PAYLOAD,
8338                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8339                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8340                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8341                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8342                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8343                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8344                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8345                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8346                         I40E_INSET_FLEX_PAYLOAD,
8347                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8348                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8349                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8351                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8352                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8353                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8354                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8355                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8356                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8357                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8358                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8359                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8360                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8361                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8362                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8363                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8364                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8365                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8366                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8367                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8368                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8369                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8370                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8371                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8372                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8373                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8374                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8375                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8376                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8377                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8378                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8379                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8380                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8381                         I40E_INSET_FLEX_PAYLOAD,
8382                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8383                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8384                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8385                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8386                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8387                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8388                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8389                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8390                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8391                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8392                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8393                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8394                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8395                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8396                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8397                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8398                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8399                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8400                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8401                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8402                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8403                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8404                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8405                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8406                         I40E_INSET_FLEX_PAYLOAD,
8407                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8408                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8409                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8410                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8411                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8412                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8413                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8414                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8415                         I40E_INSET_FLEX_PAYLOAD,
8416                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8417                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8418                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8419                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8420                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8421                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8422                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8423                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8424                         I40E_INSET_FLEX_PAYLOAD,
8425                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8426                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8427                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8428                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8429                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8430                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8431                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8432                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8433                         I40E_INSET_FLEX_PAYLOAD,
8434                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8435                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8436                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8437                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8438                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8439                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8440                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8441                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8442                         I40E_INSET_FLEX_PAYLOAD,
8443                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8444                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8445                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8446                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8447                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8448                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8449                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8450                         I40E_INSET_FLEX_PAYLOAD,
8451                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8452                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8453                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8454                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8455                         I40E_INSET_FLEX_PAYLOAD,
8456         };
8457
8458         /**
8459          * Flow director supports only fields defined in
8460          * union rte_eth_fdir_flow.
8461          */
8462         static const uint64_t valid_fdir_inset_table[] = {
8463                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8464                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8465                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8466                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8467                 I40E_INSET_IPV4_TTL,
8468                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8469                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8470                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8471                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8472                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8473                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8474                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8475                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8476                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8477                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8478                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8479                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8480                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8481                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8482                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8483                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8484                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8485                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8486                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8487                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8488                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8489                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8490                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8491                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8492                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8493                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8494                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8495                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8496                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8497                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8498                 I40E_INSET_SCTP_VT,
8499                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8500                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8501                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8502                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8503                 I40E_INSET_IPV4_TTL,
8504                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8505                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8506                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8507                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8508                 I40E_INSET_IPV6_HOP_LIMIT,
8509                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8510                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8511                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8512                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8513                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8514                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8515                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8516                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8517                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8518                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8519                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8520                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8521                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8522                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8523                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8524                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8525                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8526                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8527                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8528                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8529                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8530                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8531                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8532                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8533                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8534                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8535                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8536                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8537                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8538                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8539                 I40E_INSET_SCTP_VT,
8540                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8541                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8542                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8543                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8544                 I40E_INSET_IPV6_HOP_LIMIT,
8545                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8546                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8547                 I40E_INSET_LAST_ETHER_TYPE,
8548         };
8549
8550         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8551                 return 0;
8552         if (filter == RTE_ETH_FILTER_HASH)
8553                 valid = valid_hash_inset_table[pctype];
8554         else
8555                 valid = valid_fdir_inset_table[pctype];
8556
8557         return valid;
8558 }
8559
8560 /**
8561  * Validate if the input set is allowed for a specific PCTYPE
8562  */
8563 int
8564 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8565                 enum rte_filter_type filter, uint64_t inset)
8566 {
8567         uint64_t valid;
8568
8569         valid = i40e_get_valid_input_set(pctype, filter);
8570         if (inset & (~valid))
8571                 return -EINVAL;
8572
8573         return 0;
8574 }
8575
8576 /* default input set fields combination per pctype */
8577 uint64_t
8578 i40e_get_default_input_set(uint16_t pctype)
8579 {
8580         static const uint64_t default_inset_table[] = {
8581                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8582                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8583                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8584                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8585                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8586                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8587                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8588                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8589                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8590                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8591                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8592                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8593                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8594                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8595                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8596                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8597                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8598                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8599                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8600                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8601                         I40E_INSET_SCTP_VT,
8602                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8603                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8604                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8605                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8606                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8607                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8608                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8609                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8610                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8611                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8612                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8613                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8614                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8615                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8616                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8617                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8618                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8619                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8620                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8621                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8622                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8623                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8624                         I40E_INSET_SCTP_VT,
8625                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8626                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8627                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8628                         I40E_INSET_LAST_ETHER_TYPE,
8629         };
8630
8631         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8632                 return 0;
8633
8634         return default_inset_table[pctype];
8635 }
8636
8637 /**
8638  * Parse the input set from index to logical bit masks
8639  */
8640 static int
8641 i40e_parse_input_set(uint64_t *inset,
8642                      enum i40e_filter_pctype pctype,
8643                      enum rte_eth_input_set_field *field,
8644                      uint16_t size)
8645 {
8646         uint16_t i, j;
8647         int ret = -EINVAL;
8648
8649         static const struct {
8650                 enum rte_eth_input_set_field field;
8651                 uint64_t inset;
8652         } inset_convert_table[] = {
8653                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8654                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8655                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8656                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8657                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8658                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8659                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8660                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8661                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8662                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8663                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8664                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8665                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8666                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8667                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8668                         I40E_INSET_IPV6_NEXT_HDR},
8669                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8670                         I40E_INSET_IPV6_HOP_LIMIT},
8671                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8672                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8673                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8674                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8675                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8676                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8677                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8678                         I40E_INSET_SCTP_VT},
8679                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8680                         I40E_INSET_TUNNEL_DMAC},
8681                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8682                         I40E_INSET_VLAN_TUNNEL},
8683                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8684                         I40E_INSET_TUNNEL_ID},
8685                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8686                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8687                         I40E_INSET_FLEX_PAYLOAD_W1},
8688                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8689                         I40E_INSET_FLEX_PAYLOAD_W2},
8690                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8691                         I40E_INSET_FLEX_PAYLOAD_W3},
8692                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8693                         I40E_INSET_FLEX_PAYLOAD_W4},
8694                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8695                         I40E_INSET_FLEX_PAYLOAD_W5},
8696                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8697                         I40E_INSET_FLEX_PAYLOAD_W6},
8698                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8699                         I40E_INSET_FLEX_PAYLOAD_W7},
8700                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8701                         I40E_INSET_FLEX_PAYLOAD_W8},
8702         };
8703
8704         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8705                 return ret;
8706
8707         /* Only one item allowed for default or all */
8708         if (size == 1) {
8709                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8710                         *inset = i40e_get_default_input_set(pctype);
8711                         return 0;
8712                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8713                         *inset = I40E_INSET_NONE;
8714                         return 0;
8715                 }
8716         }
8717
8718         for (i = 0, *inset = 0; i < size; i++) {
8719                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8720                         if (field[i] == inset_convert_table[j].field) {
8721                                 *inset |= inset_convert_table[j].inset;
8722                                 break;
8723                         }
8724                 }
8725
8726                 /* It contains unsupported input set, return immediately */
8727                 if (j == RTE_DIM(inset_convert_table))
8728                         return ret;
8729         }
8730
8731         return 0;
8732 }
8733
8734 /**
8735  * Translate the input set from bit masks to register aware bit masks
8736  * and vice versa
8737  */
8738 uint64_t
8739 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8740 {
8741         uint64_t val = 0;
8742         uint16_t i;
8743
8744         struct inset_map {
8745                 uint64_t inset;
8746                 uint64_t inset_reg;
8747         };
8748
8749         static const struct inset_map inset_map_common[] = {
8750                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8751                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8752                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8753                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8754                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8755                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8756                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8757                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8758                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8759                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8760                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8761                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8762                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8763                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8764                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8765                 {I40E_INSET_TUNNEL_DMAC,
8766                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8767                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8768                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8769                 {I40E_INSET_TUNNEL_SRC_PORT,
8770                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8771                 {I40E_INSET_TUNNEL_DST_PORT,
8772                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8773                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8774                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8775                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8776                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8777                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8778                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8779                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8780                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8781                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8782         };
8783
8784     /* some different registers map in x722*/
8785         static const struct inset_map inset_map_diff_x722[] = {
8786                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8787                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8788                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8789                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8790         };
8791
8792         static const struct inset_map inset_map_diff_not_x722[] = {
8793                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8794                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8795                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8796                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8797         };
8798
8799         if (input == 0)
8800                 return val;
8801
8802         /* Translate input set to register aware inset */
8803         if (type == I40E_MAC_X722) {
8804                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8805                         if (input & inset_map_diff_x722[i].inset)
8806                                 val |= inset_map_diff_x722[i].inset_reg;
8807                 }
8808         } else {
8809                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8810                         if (input & inset_map_diff_not_x722[i].inset)
8811                                 val |= inset_map_diff_not_x722[i].inset_reg;
8812                 }
8813         }
8814
8815         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8816                 if (input & inset_map_common[i].inset)
8817                         val |= inset_map_common[i].inset_reg;
8818         }
8819
8820         return val;
8821 }
8822
8823 int
8824 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8825 {
8826         uint8_t i, idx = 0;
8827         uint64_t inset_need_mask = inset;
8828
8829         static const struct {
8830                 uint64_t inset;
8831                 uint32_t mask;
8832         } inset_mask_map[] = {
8833                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8834                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8835                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8836                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8837                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8838                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8839                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8840                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8841         };
8842
8843         if (!inset || !mask || !nb_elem)
8844                 return 0;
8845
8846         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8847                 /* Clear the inset bit, if no MASK is required,
8848                  * for example proto + ttl
8849                  */
8850                 if ((inset & inset_mask_map[i].inset) ==
8851                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8852                         inset_need_mask &= ~inset_mask_map[i].inset;
8853                 if (!inset_need_mask)
8854                         return 0;
8855         }
8856         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8857                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8858                     inset_mask_map[i].inset) {
8859                         if (idx >= nb_elem) {
8860                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8861                                 return -EINVAL;
8862                         }
8863                         mask[idx] = inset_mask_map[i].mask;
8864                         idx++;
8865                 }
8866         }
8867
8868         return idx;
8869 }
8870
8871 void
8872 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8873 {
8874         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8875
8876         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8877         if (reg != val)
8878                 i40e_write_rx_ctl(hw, addr, val);
8879         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8880                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8881 }
8882
8883 static void
8884 i40e_filter_input_set_init(struct i40e_pf *pf)
8885 {
8886         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8887         enum i40e_filter_pctype pctype;
8888         uint64_t input_set, inset_reg;
8889         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8890         int num, i;
8891         uint16_t flow_type;
8892
8893         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8894              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8895                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8896
8897                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8898                         continue;
8899
8900                 input_set = i40e_get_default_input_set(pctype);
8901
8902                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8903                                                    I40E_INSET_MASK_NUM_REG);
8904                 if (num < 0)
8905                         return;
8906                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8907                                         input_set);
8908
8909                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8910                                       (uint32_t)(inset_reg & UINT32_MAX));
8911                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8912                                      (uint32_t)((inset_reg >>
8913                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8914                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8915                                       (uint32_t)(inset_reg & UINT32_MAX));
8916                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8917                                      (uint32_t)((inset_reg >>
8918                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8919
8920                 for (i = 0; i < num; i++) {
8921                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8922                                              mask_reg[i]);
8923                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8924                                              mask_reg[i]);
8925                 }
8926                 /*clear unused mask registers of the pctype */
8927                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8928                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8929                                              0);
8930                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8931                                              0);
8932                 }
8933                 I40E_WRITE_FLUSH(hw);
8934
8935                 /* store the default input set */
8936                 pf->hash_input_set[pctype] = input_set;
8937                 pf->fdir.input_set[pctype] = input_set;
8938         }
8939 }
8940
8941 int
8942 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8943                          struct rte_eth_input_set_conf *conf)
8944 {
8945         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8946         enum i40e_filter_pctype pctype;
8947         uint64_t input_set, inset_reg = 0;
8948         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8949         int ret, i, num;
8950
8951         if (!conf) {
8952                 PMD_DRV_LOG(ERR, "Invalid pointer");
8953                 return -EFAULT;
8954         }
8955         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8956             conf->op != RTE_ETH_INPUT_SET_ADD) {
8957                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8958                 return -EINVAL;
8959         }
8960
8961         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8962         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8963                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8964                 return -EINVAL;
8965         }
8966
8967         if (hw->mac.type == I40E_MAC_X722) {
8968                 /* get translated pctype value in fd pctype register */
8969                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8970                         I40E_GLQF_FD_PCTYPES((int)pctype));
8971         }
8972
8973         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8974                                    conf->inset_size);
8975         if (ret) {
8976                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8977                 return -EINVAL;
8978         }
8979
8980         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8981                 /* get inset value in register */
8982                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8983                 inset_reg <<= I40E_32_BIT_WIDTH;
8984                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8985                 input_set |= pf->hash_input_set[pctype];
8986         }
8987         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8988                                            I40E_INSET_MASK_NUM_REG);
8989         if (num < 0)
8990                 return -EINVAL;
8991
8992         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8993
8994         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8995                               (uint32_t)(inset_reg & UINT32_MAX));
8996         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8997                              (uint32_t)((inset_reg >>
8998                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8999
9000         for (i = 0; i < num; i++)
9001                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9002                                      mask_reg[i]);
9003         /*clear unused mask registers of the pctype */
9004         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9005                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9006                                      0);
9007         I40E_WRITE_FLUSH(hw);
9008
9009         pf->hash_input_set[pctype] = input_set;
9010         return 0;
9011 }
9012
9013 int
9014 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9015                          struct rte_eth_input_set_conf *conf)
9016 {
9017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9018         enum i40e_filter_pctype pctype;
9019         uint64_t input_set, inset_reg = 0;
9020         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9021         int ret, i, num;
9022
9023         if (!hw || !conf) {
9024                 PMD_DRV_LOG(ERR, "Invalid pointer");
9025                 return -EFAULT;
9026         }
9027         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9028             conf->op != RTE_ETH_INPUT_SET_ADD) {
9029                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9030                 return -EINVAL;
9031         }
9032
9033         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9034
9035         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9036                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9037                 return -EINVAL;
9038         }
9039
9040         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9041                                    conf->inset_size);
9042         if (ret) {
9043                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9044                 return -EINVAL;
9045         }
9046
9047         /* get inset value in register */
9048         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9049         inset_reg <<= I40E_32_BIT_WIDTH;
9050         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9051
9052         /* Can not change the inset reg for flex payload for fdir,
9053          * it is done by writing I40E_PRTQF_FD_FLXINSET
9054          * in i40e_set_flex_mask_on_pctype.
9055          */
9056         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9057                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9058         else
9059                 input_set |= pf->fdir.input_set[pctype];
9060         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9061                                            I40E_INSET_MASK_NUM_REG);
9062         if (num < 0)
9063                 return -EINVAL;
9064
9065         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9066
9067         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9068                               (uint32_t)(inset_reg & UINT32_MAX));
9069         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9070                              (uint32_t)((inset_reg >>
9071                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9072
9073         for (i = 0; i < num; i++)
9074                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9075                                      mask_reg[i]);
9076         /*clear unused mask registers of the pctype */
9077         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9078                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9079                                      0);
9080         I40E_WRITE_FLUSH(hw);
9081
9082         pf->fdir.input_set[pctype] = input_set;
9083         return 0;
9084 }
9085
9086 static int
9087 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9088 {
9089         int ret = 0;
9090
9091         if (!hw || !info) {
9092                 PMD_DRV_LOG(ERR, "Invalid pointer");
9093                 return -EFAULT;
9094         }
9095
9096         switch (info->info_type) {
9097         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9098                 i40e_get_symmetric_hash_enable_per_port(hw,
9099                                         &(info->info.enable));
9100                 break;
9101         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9102                 ret = i40e_get_hash_filter_global_config(hw,
9103                                 &(info->info.global_conf));
9104                 break;
9105         default:
9106                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9107                                                         info->info_type);
9108                 ret = -EINVAL;
9109                 break;
9110         }
9111
9112         return ret;
9113 }
9114
9115 static int
9116 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9117 {
9118         int ret = 0;
9119
9120         if (!hw || !info) {
9121                 PMD_DRV_LOG(ERR, "Invalid pointer");
9122                 return -EFAULT;
9123         }
9124
9125         switch (info->info_type) {
9126         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9127                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9128                 break;
9129         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9130                 ret = i40e_set_hash_filter_global_config(hw,
9131                                 &(info->info.global_conf));
9132                 break;
9133         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9134                 ret = i40e_hash_filter_inset_select(hw,
9135                                                &(info->info.input_set_conf));
9136                 break;
9137
9138         default:
9139                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9140                                                         info->info_type);
9141                 ret = -EINVAL;
9142                 break;
9143         }
9144
9145         return ret;
9146 }
9147
9148 /* Operations for hash function */
9149 static int
9150 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9151                       enum rte_filter_op filter_op,
9152                       void *arg)
9153 {
9154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9155         int ret = 0;
9156
9157         switch (filter_op) {
9158         case RTE_ETH_FILTER_NOP:
9159                 break;
9160         case RTE_ETH_FILTER_GET:
9161                 ret = i40e_hash_filter_get(hw,
9162                         (struct rte_eth_hash_filter_info *)arg);
9163                 break;
9164         case RTE_ETH_FILTER_SET:
9165                 ret = i40e_hash_filter_set(hw,
9166                         (struct rte_eth_hash_filter_info *)arg);
9167                 break;
9168         default:
9169                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9170                                                                 filter_op);
9171                 ret = -ENOTSUP;
9172                 break;
9173         }
9174
9175         return ret;
9176 }
9177
9178 /* Convert ethertype filter structure */
9179 static int
9180 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9181                               struct i40e_ethertype_filter *filter)
9182 {
9183         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9184         filter->input.ether_type = input->ether_type;
9185         filter->flags = input->flags;
9186         filter->queue = input->queue;
9187
9188         return 0;
9189 }
9190
9191 /* Check if there exists the ehtertype filter */
9192 struct i40e_ethertype_filter *
9193 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9194                                 const struct i40e_ethertype_filter_input *input)
9195 {
9196         int ret;
9197
9198         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9199         if (ret < 0)
9200                 return NULL;
9201
9202         return ethertype_rule->hash_map[ret];
9203 }
9204
9205 /* Add ethertype filter in SW list */
9206 static int
9207 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9208                                 struct i40e_ethertype_filter *filter)
9209 {
9210         struct i40e_ethertype_rule *rule = &pf->ethertype;
9211         int ret;
9212
9213         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9214         if (ret < 0) {
9215                 PMD_DRV_LOG(ERR,
9216                             "Failed to insert ethertype filter"
9217                             " to hash table %d!",
9218                             ret);
9219                 return ret;
9220         }
9221         rule->hash_map[ret] = filter;
9222
9223         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9224
9225         return 0;
9226 }
9227
9228 /* Delete ethertype filter in SW list */
9229 int
9230 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9231                              struct i40e_ethertype_filter_input *input)
9232 {
9233         struct i40e_ethertype_rule *rule = &pf->ethertype;
9234         struct i40e_ethertype_filter *filter;
9235         int ret;
9236
9237         ret = rte_hash_del_key(rule->hash_table, input);
9238         if (ret < 0) {
9239                 PMD_DRV_LOG(ERR,
9240                             "Failed to delete ethertype filter"
9241                             " to hash table %d!",
9242                             ret);
9243                 return ret;
9244         }
9245         filter = rule->hash_map[ret];
9246         rule->hash_map[ret] = NULL;
9247
9248         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9249         rte_free(filter);
9250
9251         return 0;
9252 }
9253
9254 /*
9255  * Configure ethertype filter, which can director packet by filtering
9256  * with mac address and ether_type or only ether_type
9257  */
9258 int
9259 i40e_ethertype_filter_set(struct i40e_pf *pf,
9260                         struct rte_eth_ethertype_filter *filter,
9261                         bool add)
9262 {
9263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9264         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9265         struct i40e_ethertype_filter *ethertype_filter, *node;
9266         struct i40e_ethertype_filter check_filter;
9267         struct i40e_control_filter_stats stats;
9268         uint16_t flags = 0;
9269         int ret;
9270
9271         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9272                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9273                 return -EINVAL;
9274         }
9275         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9276                 filter->ether_type == ETHER_TYPE_IPv6) {
9277                 PMD_DRV_LOG(ERR,
9278                         "unsupported ether_type(0x%04x) in control packet filter.",
9279                         filter->ether_type);
9280                 return -EINVAL;
9281         }
9282         if (filter->ether_type == ETHER_TYPE_VLAN)
9283                 PMD_DRV_LOG(WARNING,
9284                         "filter vlan ether_type in first tag is not supported.");
9285
9286         /* Check if there is the filter in SW list */
9287         memset(&check_filter, 0, sizeof(check_filter));
9288         i40e_ethertype_filter_convert(filter, &check_filter);
9289         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9290                                                &check_filter.input);
9291         if (add && node) {
9292                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9293                 return -EINVAL;
9294         }
9295
9296         if (!add && !node) {
9297                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9298                 return -EINVAL;
9299         }
9300
9301         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9302                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9303         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9304                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9305         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9306
9307         memset(&stats, 0, sizeof(stats));
9308         ret = i40e_aq_add_rem_control_packet_filter(hw,
9309                         filter->mac_addr.addr_bytes,
9310                         filter->ether_type, flags,
9311                         pf->main_vsi->seid,
9312                         filter->queue, add, &stats, NULL);
9313
9314         PMD_DRV_LOG(INFO,
9315                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9316                 ret, stats.mac_etype_used, stats.etype_used,
9317                 stats.mac_etype_free, stats.etype_free);
9318         if (ret < 0)
9319                 return -ENOSYS;
9320
9321         /* Add or delete a filter in SW list */
9322         if (add) {
9323                 ethertype_filter = rte_zmalloc("ethertype_filter",
9324                                        sizeof(*ethertype_filter), 0);
9325                 if (ethertype_filter == NULL) {
9326                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9327                         return -ENOMEM;
9328                 }
9329
9330                 rte_memcpy(ethertype_filter, &check_filter,
9331                            sizeof(check_filter));
9332                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9333                 if (ret < 0)
9334                         rte_free(ethertype_filter);
9335         } else {
9336                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9337         }
9338
9339         return ret;
9340 }
9341
9342 /*
9343  * Handle operations for ethertype filter.
9344  */
9345 static int
9346 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9347                                 enum rte_filter_op filter_op,
9348                                 void *arg)
9349 {
9350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9351         int ret = 0;
9352
9353         if (filter_op == RTE_ETH_FILTER_NOP)
9354                 return ret;
9355
9356         if (arg == NULL) {
9357                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9358                             filter_op);
9359                 return -EINVAL;
9360         }
9361
9362         switch (filter_op) {
9363         case RTE_ETH_FILTER_ADD:
9364                 ret = i40e_ethertype_filter_set(pf,
9365                         (struct rte_eth_ethertype_filter *)arg,
9366                         TRUE);
9367                 break;
9368         case RTE_ETH_FILTER_DELETE:
9369                 ret = i40e_ethertype_filter_set(pf,
9370                         (struct rte_eth_ethertype_filter *)arg,
9371                         FALSE);
9372                 break;
9373         default:
9374                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9375                 ret = -ENOSYS;
9376                 break;
9377         }
9378         return ret;
9379 }
9380
9381 static int
9382 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9383                      enum rte_filter_type filter_type,
9384                      enum rte_filter_op filter_op,
9385                      void *arg)
9386 {
9387         int ret = 0;
9388
9389         if (dev == NULL)
9390                 return -EINVAL;
9391
9392         switch (filter_type) {
9393         case RTE_ETH_FILTER_NONE:
9394                 /* For global configuration */
9395                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9396                 break;
9397         case RTE_ETH_FILTER_HASH:
9398                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9399                 break;
9400         case RTE_ETH_FILTER_MACVLAN:
9401                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9402                 break;
9403         case RTE_ETH_FILTER_ETHERTYPE:
9404                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9405                 break;
9406         case RTE_ETH_FILTER_TUNNEL:
9407                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9408                 break;
9409         case RTE_ETH_FILTER_FDIR:
9410                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9411                 break;
9412         case RTE_ETH_FILTER_GENERIC:
9413                 if (filter_op != RTE_ETH_FILTER_GET)
9414                         return -EINVAL;
9415                 *(const void **)arg = &i40e_flow_ops;
9416                 break;
9417         default:
9418                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9419                                                         filter_type);
9420                 ret = -EINVAL;
9421                 break;
9422         }
9423
9424         return ret;
9425 }
9426
9427 /*
9428  * Check and enable Extended Tag.
9429  * Enabling Extended Tag is important for 40G performance.
9430  */
9431 static void
9432 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9433 {
9434         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9435         uint32_t buf = 0;
9436         int ret;
9437
9438         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9439                                       PCI_DEV_CAP_REG);
9440         if (ret < 0) {
9441                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9442                             PCI_DEV_CAP_REG);
9443                 return;
9444         }
9445         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9446                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9447                 return;
9448         }
9449
9450         buf = 0;
9451         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9452                                       PCI_DEV_CTRL_REG);
9453         if (ret < 0) {
9454                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9455                             PCI_DEV_CTRL_REG);
9456                 return;
9457         }
9458         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9459                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9460                 return;
9461         }
9462         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9463         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9464                                        PCI_DEV_CTRL_REG);
9465         if (ret < 0) {
9466                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9467                             PCI_DEV_CTRL_REG);
9468                 return;
9469         }
9470 }
9471
9472 /*
9473  * As some registers wouldn't be reset unless a global hardware reset,
9474  * hardware initialization is needed to put those registers into an
9475  * expected initial state.
9476  */
9477 static void
9478 i40e_hw_init(struct rte_eth_dev *dev)
9479 {
9480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9481
9482         i40e_enable_extended_tag(dev);
9483
9484         /* clear the PF Queue Filter control register */
9485         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9486
9487         /* Disable symmetric hash per port */
9488         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9489 }
9490
9491 /*
9492  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9493  * however this function will return only one highest pctype index,
9494  * which is not quite correct. This is known problem of i40e driver
9495  * and needs to be fixed later.
9496  */
9497 enum i40e_filter_pctype
9498 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9499 {
9500         int i;
9501         uint64_t pctype_mask;
9502
9503         if (flow_type < I40E_FLOW_TYPE_MAX) {
9504                 pctype_mask = adapter->pctypes_tbl[flow_type];
9505                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9506                         if (pctype_mask & (1ULL << i))
9507                                 return (enum i40e_filter_pctype)i;
9508                 }
9509         }
9510         return I40E_FILTER_PCTYPE_INVALID;
9511 }
9512
9513 uint16_t
9514 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9515                         enum i40e_filter_pctype pctype)
9516 {
9517         uint16_t flowtype;
9518         uint64_t pctype_mask = 1ULL << pctype;
9519
9520         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9521              flowtype++) {
9522                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9523                         return flowtype;
9524         }
9525
9526         return RTE_ETH_FLOW_UNKNOWN;
9527 }
9528
9529 /*
9530  * On X710, performance number is far from the expectation on recent firmware
9531  * versions; on XL710, performance number is also far from the expectation on
9532  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9533  * mode is enabled and port MAC address is equal to the packet destination MAC
9534  * address. The fix for this issue may not be integrated in the following
9535  * firmware version. So the workaround in software driver is needed. It needs
9536  * to modify the initial values of 3 internal only registers for both X710 and
9537  * XL710. Note that the values for X710 or XL710 could be different, and the
9538  * workaround can be removed when it is fixed in firmware in the future.
9539  */
9540
9541 /* For both X710 and XL710 */
9542 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9543 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9544 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9545
9546 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9547 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9548
9549 /* For X722 */
9550 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9551 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9552
9553 /* For X710 */
9554 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9555 /* For XL710 */
9556 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9557 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9558
9559 static int
9560 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9561 {
9562         enum i40e_status_code status;
9563         struct i40e_aq_get_phy_abilities_resp phy_ab;
9564         int ret = -ENOTSUP;
9565         int retries = 0;
9566
9567         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9568                                               NULL);
9569
9570         while (status) {
9571                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9572                         status);
9573                 retries++;
9574                 rte_delay_us(100000);
9575                 if  (retries < 5)
9576                         status = i40e_aq_get_phy_capabilities(hw, false,
9577                                         true, &phy_ab, NULL);
9578                 else
9579                         return ret;
9580         }
9581         return 0;
9582 }
9583
9584 static void
9585 i40e_configure_registers(struct i40e_hw *hw)
9586 {
9587         static struct {
9588                 uint32_t addr;
9589                 uint64_t val;
9590         } reg_table[] = {
9591                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9592                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9593                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9594         };
9595         uint64_t reg;
9596         uint32_t i;
9597         int ret;
9598
9599         for (i = 0; i < RTE_DIM(reg_table); i++) {
9600                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9601                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9602                                 reg_table[i].val =
9603                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9604                         else /* For X710/XL710/XXV710 */
9605                                 if (hw->aq.fw_maj_ver < 6)
9606                                         reg_table[i].val =
9607                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9608                                 else
9609                                         reg_table[i].val =
9610                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9611                 }
9612
9613                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9614                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9615                                 reg_table[i].val =
9616                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9617                         else /* For X710/XL710/XXV710 */
9618                                 reg_table[i].val =
9619                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9620                 }
9621
9622                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9623                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9624                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9625                                 reg_table[i].val =
9626                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9627                         else /* For X710 */
9628                                 reg_table[i].val =
9629                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9630                 }
9631
9632                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9633                                                         &reg, NULL);
9634                 if (ret < 0) {
9635                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9636                                                         reg_table[i].addr);
9637                         break;
9638                 }
9639                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9640                                                 reg_table[i].addr, reg);
9641                 if (reg == reg_table[i].val)
9642                         continue;
9643
9644                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9645                                                 reg_table[i].val, NULL);
9646                 if (ret < 0) {
9647                         PMD_DRV_LOG(ERR,
9648                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9649                                 reg_table[i].val, reg_table[i].addr);
9650                         break;
9651                 }
9652                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9653                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9654         }
9655 }
9656
9657 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9658 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9659 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9660 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9661 static int
9662 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9663 {
9664         uint32_t reg;
9665         int ret;
9666
9667         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9668                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9669                 return -EINVAL;
9670         }
9671
9672         /* Configure for double VLAN RX stripping */
9673         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9674         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9675                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9676                 ret = i40e_aq_debug_write_register(hw,
9677                                                    I40E_VSI_TSR(vsi->vsi_id),
9678                                                    reg, NULL);
9679                 if (ret < 0) {
9680                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9681                                     vsi->vsi_id);
9682                         return I40E_ERR_CONFIG;
9683                 }
9684         }
9685
9686         /* Configure for double VLAN TX insertion */
9687         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9688         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9689                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9690                 ret = i40e_aq_debug_write_register(hw,
9691                                                    I40E_VSI_L2TAGSTXVALID(
9692                                                    vsi->vsi_id), reg, NULL);
9693                 if (ret < 0) {
9694                         PMD_DRV_LOG(ERR,
9695                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9696                                 vsi->vsi_id);
9697                         return I40E_ERR_CONFIG;
9698                 }
9699         }
9700
9701         return 0;
9702 }
9703
9704 /**
9705  * i40e_aq_add_mirror_rule
9706  * @hw: pointer to the hardware structure
9707  * @seid: VEB seid to add mirror rule to
9708  * @dst_id: destination vsi seid
9709  * @entries: Buffer which contains the entities to be mirrored
9710  * @count: number of entities contained in the buffer
9711  * @rule_id:the rule_id of the rule to be added
9712  *
9713  * Add a mirror rule for a given veb.
9714  *
9715  **/
9716 static enum i40e_status_code
9717 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9718                         uint16_t seid, uint16_t dst_id,
9719                         uint16_t rule_type, uint16_t *entries,
9720                         uint16_t count, uint16_t *rule_id)
9721 {
9722         struct i40e_aq_desc desc;
9723         struct i40e_aqc_add_delete_mirror_rule cmd;
9724         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9725                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9726                 &desc.params.raw;
9727         uint16_t buff_len;
9728         enum i40e_status_code status;
9729
9730         i40e_fill_default_direct_cmd_desc(&desc,
9731                                           i40e_aqc_opc_add_mirror_rule);
9732         memset(&cmd, 0, sizeof(cmd));
9733
9734         buff_len = sizeof(uint16_t) * count;
9735         desc.datalen = rte_cpu_to_le_16(buff_len);
9736         if (buff_len > 0)
9737                 desc.flags |= rte_cpu_to_le_16(
9738                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9739         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9740                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9741         cmd.num_entries = rte_cpu_to_le_16(count);
9742         cmd.seid = rte_cpu_to_le_16(seid);
9743         cmd.destination = rte_cpu_to_le_16(dst_id);
9744
9745         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9746         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9747         PMD_DRV_LOG(INFO,
9748                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9749                 hw->aq.asq_last_status, resp->rule_id,
9750                 resp->mirror_rules_used, resp->mirror_rules_free);
9751         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9752
9753         return status;
9754 }
9755
9756 /**
9757  * i40e_aq_del_mirror_rule
9758  * @hw: pointer to the hardware structure
9759  * @seid: VEB seid to add mirror rule to
9760  * @entries: Buffer which contains the entities to be mirrored
9761  * @count: number of entities contained in the buffer
9762  * @rule_id:the rule_id of the rule to be delete
9763  *
9764  * Delete a mirror rule for a given veb.
9765  *
9766  **/
9767 static enum i40e_status_code
9768 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9769                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9770                 uint16_t count, uint16_t rule_id)
9771 {
9772         struct i40e_aq_desc desc;
9773         struct i40e_aqc_add_delete_mirror_rule cmd;
9774         uint16_t buff_len = 0;
9775         enum i40e_status_code status;
9776         void *buff = NULL;
9777
9778         i40e_fill_default_direct_cmd_desc(&desc,
9779                                           i40e_aqc_opc_delete_mirror_rule);
9780         memset(&cmd, 0, sizeof(cmd));
9781         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9782                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9783                                                           I40E_AQ_FLAG_RD));
9784                 cmd.num_entries = count;
9785                 buff_len = sizeof(uint16_t) * count;
9786                 desc.datalen = rte_cpu_to_le_16(buff_len);
9787                 buff = (void *)entries;
9788         } else
9789                 /* rule id is filled in destination field for deleting mirror rule */
9790                 cmd.destination = rte_cpu_to_le_16(rule_id);
9791
9792         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9793                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9794         cmd.seid = rte_cpu_to_le_16(seid);
9795
9796         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9797         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9798
9799         return status;
9800 }
9801
9802 /**
9803  * i40e_mirror_rule_set
9804  * @dev: pointer to the hardware structure
9805  * @mirror_conf: mirror rule info
9806  * @sw_id: mirror rule's sw_id
9807  * @on: enable/disable
9808  *
9809  * set a mirror rule.
9810  *
9811  **/
9812 static int
9813 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9814                         struct rte_eth_mirror_conf *mirror_conf,
9815                         uint8_t sw_id, uint8_t on)
9816 {
9817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9818         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9819         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9820         struct i40e_mirror_rule *parent = NULL;
9821         uint16_t seid, dst_seid, rule_id;
9822         uint16_t i, j = 0;
9823         int ret;
9824
9825         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9826
9827         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9828                 PMD_DRV_LOG(ERR,
9829                         "mirror rule can not be configured without veb or vfs.");
9830                 return -ENOSYS;
9831         }
9832         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9833                 PMD_DRV_LOG(ERR, "mirror table is full.");
9834                 return -ENOSPC;
9835         }
9836         if (mirror_conf->dst_pool > pf->vf_num) {
9837                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9838                                  mirror_conf->dst_pool);
9839                 return -EINVAL;
9840         }
9841
9842         seid = pf->main_vsi->veb->seid;
9843
9844         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9845                 if (sw_id <= it->index) {
9846                         mirr_rule = it;
9847                         break;
9848                 }
9849                 parent = it;
9850         }
9851         if (mirr_rule && sw_id == mirr_rule->index) {
9852                 if (on) {
9853                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9854                         return -EEXIST;
9855                 } else {
9856                         ret = i40e_aq_del_mirror_rule(hw, seid,
9857                                         mirr_rule->rule_type,
9858                                         mirr_rule->entries,
9859                                         mirr_rule->num_entries, mirr_rule->id);
9860                         if (ret < 0) {
9861                                 PMD_DRV_LOG(ERR,
9862                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9863                                         ret, hw->aq.asq_last_status);
9864                                 return -ENOSYS;
9865                         }
9866                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9867                         rte_free(mirr_rule);
9868                         pf->nb_mirror_rule--;
9869                         return 0;
9870                 }
9871         } else if (!on) {
9872                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9873                 return -ENOENT;
9874         }
9875
9876         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9877                                 sizeof(struct i40e_mirror_rule) , 0);
9878         if (!mirr_rule) {
9879                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9880                 return I40E_ERR_NO_MEMORY;
9881         }
9882         switch (mirror_conf->rule_type) {
9883         case ETH_MIRROR_VLAN:
9884                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9885                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9886                                 mirr_rule->entries[j] =
9887                                         mirror_conf->vlan.vlan_id[i];
9888                                 j++;
9889                         }
9890                 }
9891                 if (j == 0) {
9892                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9893                         rte_free(mirr_rule);
9894                         return -EINVAL;
9895                 }
9896                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9897                 break;
9898         case ETH_MIRROR_VIRTUAL_POOL_UP:
9899         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9900                 /* check if the specified pool bit is out of range */
9901                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9902                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9903                         rte_free(mirr_rule);
9904                         return -EINVAL;
9905                 }
9906                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9907                         if (mirror_conf->pool_mask & (1ULL << i)) {
9908                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9909                                 j++;
9910                         }
9911                 }
9912                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9913                         /* add pf vsi to entries */
9914                         mirr_rule->entries[j] = pf->main_vsi_seid;
9915                         j++;
9916                 }
9917                 if (j == 0) {
9918                         PMD_DRV_LOG(ERR, "pool is not specified.");
9919                         rte_free(mirr_rule);
9920                         return -EINVAL;
9921                 }
9922                 /* egress and ingress in aq commands means from switch but not port */
9923                 mirr_rule->rule_type =
9924                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9925                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9926                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9927                 break;
9928         case ETH_MIRROR_UPLINK_PORT:
9929                 /* egress and ingress in aq commands means from switch but not port*/
9930                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9931                 break;
9932         case ETH_MIRROR_DOWNLINK_PORT:
9933                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9934                 break;
9935         default:
9936                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9937                         mirror_conf->rule_type);
9938                 rte_free(mirr_rule);
9939                 return -EINVAL;
9940         }
9941
9942         /* If the dst_pool is equal to vf_num, consider it as PF */
9943         if (mirror_conf->dst_pool == pf->vf_num)
9944                 dst_seid = pf->main_vsi_seid;
9945         else
9946                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9947
9948         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9949                                       mirr_rule->rule_type, mirr_rule->entries,
9950                                       j, &rule_id);
9951         if (ret < 0) {
9952                 PMD_DRV_LOG(ERR,
9953                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9954                         ret, hw->aq.asq_last_status);
9955                 rte_free(mirr_rule);
9956                 return -ENOSYS;
9957         }
9958
9959         mirr_rule->index = sw_id;
9960         mirr_rule->num_entries = j;
9961         mirr_rule->id = rule_id;
9962         mirr_rule->dst_vsi_seid = dst_seid;
9963
9964         if (parent)
9965                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9966         else
9967                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9968
9969         pf->nb_mirror_rule++;
9970         return 0;
9971 }
9972
9973 /**
9974  * i40e_mirror_rule_reset
9975  * @dev: pointer to the device
9976  * @sw_id: mirror rule's sw_id
9977  *
9978  * reset a mirror rule.
9979  *
9980  **/
9981 static int
9982 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9983 {
9984         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9986         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9987         uint16_t seid;
9988         int ret;
9989
9990         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9991
9992         seid = pf->main_vsi->veb->seid;
9993
9994         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9995                 if (sw_id == it->index) {
9996                         mirr_rule = it;
9997                         break;
9998                 }
9999         }
10000         if (mirr_rule) {
10001                 ret = i40e_aq_del_mirror_rule(hw, seid,
10002                                 mirr_rule->rule_type,
10003                                 mirr_rule->entries,
10004                                 mirr_rule->num_entries, mirr_rule->id);
10005                 if (ret < 0) {
10006                         PMD_DRV_LOG(ERR,
10007                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10008                                 ret, hw->aq.asq_last_status);
10009                         return -ENOSYS;
10010                 }
10011                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10012                 rte_free(mirr_rule);
10013                 pf->nb_mirror_rule--;
10014         } else {
10015                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10016                 return -ENOENT;
10017         }
10018         return 0;
10019 }
10020
10021 static uint64_t
10022 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10023 {
10024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10025         uint64_t systim_cycles;
10026
10027         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10028         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10029                         << 32;
10030
10031         return systim_cycles;
10032 }
10033
10034 static uint64_t
10035 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10036 {
10037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10038         uint64_t rx_tstamp;
10039
10040         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10041         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10042                         << 32;
10043
10044         return rx_tstamp;
10045 }
10046
10047 static uint64_t
10048 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10049 {
10050         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10051         uint64_t tx_tstamp;
10052
10053         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10054         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10055                         << 32;
10056
10057         return tx_tstamp;
10058 }
10059
10060 static void
10061 i40e_start_timecounters(struct rte_eth_dev *dev)
10062 {
10063         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10064         struct i40e_adapter *adapter =
10065                         (struct i40e_adapter *)dev->data->dev_private;
10066         struct rte_eth_link link;
10067         uint32_t tsync_inc_l;
10068         uint32_t tsync_inc_h;
10069
10070         /* Get current link speed. */
10071         memset(&link, 0, sizeof(link));
10072         i40e_dev_link_update(dev, 1);
10073         rte_i40e_dev_atomic_read_link_status(dev, &link);
10074
10075         switch (link.link_speed) {
10076         case ETH_SPEED_NUM_40G:
10077                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10078                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10079                 break;
10080         case ETH_SPEED_NUM_10G:
10081                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10082                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10083                 break;
10084         case ETH_SPEED_NUM_1G:
10085                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10086                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10087                 break;
10088         default:
10089                 tsync_inc_l = 0x0;
10090                 tsync_inc_h = 0x0;
10091         }
10092
10093         /* Set the timesync increment value. */
10094         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10095         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10096
10097         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10098         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10099         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10100
10101         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10102         adapter->systime_tc.cc_shift = 0;
10103         adapter->systime_tc.nsec_mask = 0;
10104
10105         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10106         adapter->rx_tstamp_tc.cc_shift = 0;
10107         adapter->rx_tstamp_tc.nsec_mask = 0;
10108
10109         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10110         adapter->tx_tstamp_tc.cc_shift = 0;
10111         adapter->tx_tstamp_tc.nsec_mask = 0;
10112 }
10113
10114 static int
10115 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10116 {
10117         struct i40e_adapter *adapter =
10118                         (struct i40e_adapter *)dev->data->dev_private;
10119
10120         adapter->systime_tc.nsec += delta;
10121         adapter->rx_tstamp_tc.nsec += delta;
10122         adapter->tx_tstamp_tc.nsec += delta;
10123
10124         return 0;
10125 }
10126
10127 static int
10128 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10129 {
10130         uint64_t ns;
10131         struct i40e_adapter *adapter =
10132                         (struct i40e_adapter *)dev->data->dev_private;
10133
10134         ns = rte_timespec_to_ns(ts);
10135
10136         /* Set the timecounters to a new value. */
10137         adapter->systime_tc.nsec = ns;
10138         adapter->rx_tstamp_tc.nsec = ns;
10139         adapter->tx_tstamp_tc.nsec = ns;
10140
10141         return 0;
10142 }
10143
10144 static int
10145 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10146 {
10147         uint64_t ns, systime_cycles;
10148         struct i40e_adapter *adapter =
10149                         (struct i40e_adapter *)dev->data->dev_private;
10150
10151         systime_cycles = i40e_read_systime_cyclecounter(dev);
10152         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10153         *ts = rte_ns_to_timespec(ns);
10154
10155         return 0;
10156 }
10157
10158 static int
10159 i40e_timesync_enable(struct rte_eth_dev *dev)
10160 {
10161         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10162         uint32_t tsync_ctl_l;
10163         uint32_t tsync_ctl_h;
10164
10165         /* Stop the timesync system time. */
10166         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10167         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10168         /* Reset the timesync system time value. */
10169         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10170         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10171
10172         i40e_start_timecounters(dev);
10173
10174         /* Clear timesync registers. */
10175         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10176         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10177         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10178         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10179         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10180         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10181
10182         /* Enable timestamping of PTP packets. */
10183         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10184         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10185
10186         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10187         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10188         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10189
10190         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10191         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10192
10193         return 0;
10194 }
10195
10196 static int
10197 i40e_timesync_disable(struct rte_eth_dev *dev)
10198 {
10199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10200         uint32_t tsync_ctl_l;
10201         uint32_t tsync_ctl_h;
10202
10203         /* Disable timestamping of transmitted PTP packets. */
10204         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10205         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10206
10207         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10208         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10209
10210         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10211         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10212
10213         /* Reset the timesync increment value. */
10214         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10215         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10216
10217         return 0;
10218 }
10219
10220 static int
10221 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10222                                 struct timespec *timestamp, uint32_t flags)
10223 {
10224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10225         struct i40e_adapter *adapter =
10226                 (struct i40e_adapter *)dev->data->dev_private;
10227
10228         uint32_t sync_status;
10229         uint32_t index = flags & 0x03;
10230         uint64_t rx_tstamp_cycles;
10231         uint64_t ns;
10232
10233         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10234         if ((sync_status & (1 << index)) == 0)
10235                 return -EINVAL;
10236
10237         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10238         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10239         *timestamp = rte_ns_to_timespec(ns);
10240
10241         return 0;
10242 }
10243
10244 static int
10245 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10246                                 struct timespec *timestamp)
10247 {
10248         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10249         struct i40e_adapter *adapter =
10250                 (struct i40e_adapter *)dev->data->dev_private;
10251
10252         uint32_t sync_status;
10253         uint64_t tx_tstamp_cycles;
10254         uint64_t ns;
10255
10256         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10257         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10258                 return -EINVAL;
10259
10260         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10261         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10262         *timestamp = rte_ns_to_timespec(ns);
10263
10264         return 0;
10265 }
10266
10267 /*
10268  * i40e_parse_dcb_configure - parse dcb configure from user
10269  * @dev: the device being configured
10270  * @dcb_cfg: pointer of the result of parse
10271  * @*tc_map: bit map of enabled traffic classes
10272  *
10273  * Returns 0 on success, negative value on failure
10274  */
10275 static int
10276 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10277                          struct i40e_dcbx_config *dcb_cfg,
10278                          uint8_t *tc_map)
10279 {
10280         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10281         uint8_t i, tc_bw, bw_lf;
10282
10283         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10284
10285         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10286         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10287                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10288                 return -EINVAL;
10289         }
10290
10291         /* assume each tc has the same bw */
10292         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10293         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10294                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10295         /* to ensure the sum of tcbw is equal to 100 */
10296         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10297         for (i = 0; i < bw_lf; i++)
10298                 dcb_cfg->etscfg.tcbwtable[i]++;
10299
10300         /* assume each tc has the same Transmission Selection Algorithm */
10301         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10302                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10303
10304         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10305                 dcb_cfg->etscfg.prioritytable[i] =
10306                                 dcb_rx_conf->dcb_tc[i];
10307
10308         /* FW needs one App to configure HW */
10309         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10310         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10311         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10312         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10313
10314         if (dcb_rx_conf->nb_tcs == 0)
10315                 *tc_map = 1; /* tc0 only */
10316         else
10317                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10318
10319         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10320                 dcb_cfg->pfc.willing = 0;
10321                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10322                 dcb_cfg->pfc.pfcenable = *tc_map;
10323         }
10324         return 0;
10325 }
10326
10327
10328 static enum i40e_status_code
10329 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10330                               struct i40e_aqc_vsi_properties_data *info,
10331                               uint8_t enabled_tcmap)
10332 {
10333         enum i40e_status_code ret;
10334         int i, total_tc = 0;
10335         uint16_t qpnum_per_tc, bsf, qp_idx;
10336         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10337         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10338         uint16_t used_queues;
10339
10340         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10341         if (ret != I40E_SUCCESS)
10342                 return ret;
10343
10344         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10345                 if (enabled_tcmap & (1 << i))
10346                         total_tc++;
10347         }
10348         if (total_tc == 0)
10349                 total_tc = 1;
10350         vsi->enabled_tc = enabled_tcmap;
10351
10352         /* different VSI has different queues assigned */
10353         if (vsi->type == I40E_VSI_MAIN)
10354                 used_queues = dev_data->nb_rx_queues -
10355                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10356         else if (vsi->type == I40E_VSI_VMDQ2)
10357                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10358         else {
10359                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10360                 return I40E_ERR_NO_AVAILABLE_VSI;
10361         }
10362
10363         qpnum_per_tc = used_queues / total_tc;
10364         /* Number of queues per enabled TC */
10365         if (qpnum_per_tc == 0) {
10366                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10367                 return I40E_ERR_INVALID_QP_ID;
10368         }
10369         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10370                                 I40E_MAX_Q_PER_TC);
10371         bsf = rte_bsf32(qpnum_per_tc);
10372
10373         /**
10374          * Configure TC and queue mapping parameters, for enabled TC,
10375          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10376          * default queue will serve it.
10377          */
10378         qp_idx = 0;
10379         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10380                 if (vsi->enabled_tc & (1 << i)) {
10381                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10382                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10383                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10384                         qp_idx += qpnum_per_tc;
10385                 } else
10386                         info->tc_mapping[i] = 0;
10387         }
10388
10389         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10390         if (vsi->type == I40E_VSI_SRIOV) {
10391                 info->mapping_flags |=
10392                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10393                 for (i = 0; i < vsi->nb_qps; i++)
10394                         info->queue_mapping[i] =
10395                                 rte_cpu_to_le_16(vsi->base_queue + i);
10396         } else {
10397                 info->mapping_flags |=
10398                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10399                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10400         }
10401         info->valid_sections |=
10402                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10403
10404         return I40E_SUCCESS;
10405 }
10406
10407 /*
10408  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10409  * @veb: VEB to be configured
10410  * @tc_map: enabled TC bitmap
10411  *
10412  * Returns 0 on success, negative value on failure
10413  */
10414 static enum i40e_status_code
10415 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10416 {
10417         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10418         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10419         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10420         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10421         enum i40e_status_code ret = I40E_SUCCESS;
10422         int i;
10423         uint32_t bw_max;
10424
10425         /* Check if enabled_tc is same as existing or new TCs */
10426         if (veb->enabled_tc == tc_map)
10427                 return ret;
10428
10429         /* configure tc bandwidth */
10430         memset(&veb_bw, 0, sizeof(veb_bw));
10431         veb_bw.tc_valid_bits = tc_map;
10432         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10433         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10434                 if (tc_map & BIT_ULL(i))
10435                         veb_bw.tc_bw_share_credits[i] = 1;
10436         }
10437         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10438                                                    &veb_bw, NULL);
10439         if (ret) {
10440                 PMD_INIT_LOG(ERR,
10441                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10442                         hw->aq.asq_last_status);
10443                 return ret;
10444         }
10445
10446         memset(&ets_query, 0, sizeof(ets_query));
10447         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10448                                                    &ets_query, NULL);
10449         if (ret != I40E_SUCCESS) {
10450                 PMD_DRV_LOG(ERR,
10451                         "Failed to get switch_comp ETS configuration %u",
10452                         hw->aq.asq_last_status);
10453                 return ret;
10454         }
10455         memset(&bw_query, 0, sizeof(bw_query));
10456         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10457                                                   &bw_query, NULL);
10458         if (ret != I40E_SUCCESS) {
10459                 PMD_DRV_LOG(ERR,
10460                         "Failed to get switch_comp bandwidth configuration %u",
10461                         hw->aq.asq_last_status);
10462                 return ret;
10463         }
10464
10465         /* store and print out BW info */
10466         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10467         veb->bw_info.bw_max = ets_query.tc_bw_max;
10468         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10469         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10470         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10471                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10472                      I40E_16_BIT_WIDTH);
10473         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10474                 veb->bw_info.bw_ets_share_credits[i] =
10475                                 bw_query.tc_bw_share_credits[i];
10476                 veb->bw_info.bw_ets_credits[i] =
10477                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10478                 /* 4 bits per TC, 4th bit is reserved */
10479                 veb->bw_info.bw_ets_max[i] =
10480                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10481                                   RTE_LEN2MASK(3, uint8_t));
10482                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10483                             veb->bw_info.bw_ets_share_credits[i]);
10484                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10485                             veb->bw_info.bw_ets_credits[i]);
10486                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10487                             veb->bw_info.bw_ets_max[i]);
10488         }
10489
10490         veb->enabled_tc = tc_map;
10491
10492         return ret;
10493 }
10494
10495
10496 /*
10497  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10498  * @vsi: VSI to be configured
10499  * @tc_map: enabled TC bitmap
10500  *
10501  * Returns 0 on success, negative value on failure
10502  */
10503 static enum i40e_status_code
10504 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10505 {
10506         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10507         struct i40e_vsi_context ctxt;
10508         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10509         enum i40e_status_code ret = I40E_SUCCESS;
10510         int i;
10511
10512         /* Check if enabled_tc is same as existing or new TCs */
10513         if (vsi->enabled_tc == tc_map)
10514                 return ret;
10515
10516         /* configure tc bandwidth */
10517         memset(&bw_data, 0, sizeof(bw_data));
10518         bw_data.tc_valid_bits = tc_map;
10519         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10520         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10521                 if (tc_map & BIT_ULL(i))
10522                         bw_data.tc_bw_credits[i] = 1;
10523         }
10524         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10525         if (ret) {
10526                 PMD_INIT_LOG(ERR,
10527                         "AQ command Config VSI BW allocation per TC failed = %d",
10528                         hw->aq.asq_last_status);
10529                 goto out;
10530         }
10531         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10532                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10533
10534         /* Update Queue Pairs Mapping for currently enabled UPs */
10535         ctxt.seid = vsi->seid;
10536         ctxt.pf_num = hw->pf_id;
10537         ctxt.vf_num = 0;
10538         ctxt.uplink_seid = vsi->uplink_seid;
10539         ctxt.info = vsi->info;
10540         i40e_get_cap(hw);
10541         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10542         if (ret)
10543                 goto out;
10544
10545         /* Update the VSI after updating the VSI queue-mapping information */
10546         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10547         if (ret) {
10548                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10549                         hw->aq.asq_last_status);
10550                 goto out;
10551         }
10552         /* update the local VSI info with updated queue map */
10553         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10554                                         sizeof(vsi->info.tc_mapping));
10555         rte_memcpy(&vsi->info.queue_mapping,
10556                         &ctxt.info.queue_mapping,
10557                 sizeof(vsi->info.queue_mapping));
10558         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10559         vsi->info.valid_sections = 0;
10560
10561         /* query and update current VSI BW information */
10562         ret = i40e_vsi_get_bw_config(vsi);
10563         if (ret) {
10564                 PMD_INIT_LOG(ERR,
10565                          "Failed updating vsi bw info, err %s aq_err %s",
10566                          i40e_stat_str(hw, ret),
10567                          i40e_aq_str(hw, hw->aq.asq_last_status));
10568                 goto out;
10569         }
10570
10571         vsi->enabled_tc = tc_map;
10572
10573 out:
10574         return ret;
10575 }
10576
10577 /*
10578  * i40e_dcb_hw_configure - program the dcb setting to hw
10579  * @pf: pf the configuration is taken on
10580  * @new_cfg: new configuration
10581  * @tc_map: enabled TC bitmap
10582  *
10583  * Returns 0 on success, negative value on failure
10584  */
10585 static enum i40e_status_code
10586 i40e_dcb_hw_configure(struct i40e_pf *pf,
10587                       struct i40e_dcbx_config *new_cfg,
10588                       uint8_t tc_map)
10589 {
10590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10591         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10592         struct i40e_vsi *main_vsi = pf->main_vsi;
10593         struct i40e_vsi_list *vsi_list;
10594         enum i40e_status_code ret;
10595         int i;
10596         uint32_t val;
10597
10598         /* Use the FW API if FW > v4.4*/
10599         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10600               (hw->aq.fw_maj_ver >= 5))) {
10601                 PMD_INIT_LOG(ERR,
10602                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10603                 return I40E_ERR_FIRMWARE_API_VERSION;
10604         }
10605
10606         /* Check if need reconfiguration */
10607         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10608                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10609                 return I40E_SUCCESS;
10610         }
10611
10612         /* Copy the new config to the current config */
10613         *old_cfg = *new_cfg;
10614         old_cfg->etsrec = old_cfg->etscfg;
10615         ret = i40e_set_dcb_config(hw);
10616         if (ret) {
10617                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10618                          i40e_stat_str(hw, ret),
10619                          i40e_aq_str(hw, hw->aq.asq_last_status));
10620                 return ret;
10621         }
10622         /* set receive Arbiter to RR mode and ETS scheme by default */
10623         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10624                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10625                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10626                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10627                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10628                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10629                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10630                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10631                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10632                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10633                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10634                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10635                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10636         }
10637         /* get local mib to check whether it is configured correctly */
10638         /* IEEE mode */
10639         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10640         /* Get Local DCB Config */
10641         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10642                                      &hw->local_dcbx_config);
10643
10644         /* if Veb is created, need to update TC of it at first */
10645         if (main_vsi->veb) {
10646                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10647                 if (ret)
10648                         PMD_INIT_LOG(WARNING,
10649                                  "Failed configuring TC for VEB seid=%d",
10650                                  main_vsi->veb->seid);
10651         }
10652         /* Update each VSI */
10653         i40e_vsi_config_tc(main_vsi, tc_map);
10654         if (main_vsi->veb) {
10655                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10656                         /* Beside main VSI and VMDQ VSIs, only enable default
10657                          * TC for other VSIs
10658                          */
10659                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10660                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10661                                                          tc_map);
10662                         else
10663                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10664                                                          I40E_DEFAULT_TCMAP);
10665                         if (ret)
10666                                 PMD_INIT_LOG(WARNING,
10667                                         "Failed configuring TC for VSI seid=%d",
10668                                         vsi_list->vsi->seid);
10669                         /* continue */
10670                 }
10671         }
10672         return I40E_SUCCESS;
10673 }
10674
10675 /*
10676  * i40e_dcb_init_configure - initial dcb config
10677  * @dev: device being configured
10678  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10679  *
10680  * Returns 0 on success, negative value on failure
10681  */
10682 int
10683 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10684 {
10685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10687         int i, ret = 0;
10688
10689         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10690                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10691                 return -ENOTSUP;
10692         }
10693
10694         /* DCB initialization:
10695          * Update DCB configuration from the Firmware and configure
10696          * LLDP MIB change event.
10697          */
10698         if (sw_dcb == TRUE) {
10699                 ret = i40e_init_dcb(hw);
10700                 /* If lldp agent is stopped, the return value from
10701                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10702                  * adminq status. Otherwise, it should return success.
10703                  */
10704                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10705                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10706                         memset(&hw->local_dcbx_config, 0,
10707                                 sizeof(struct i40e_dcbx_config));
10708                         /* set dcb default configuration */
10709                         hw->local_dcbx_config.etscfg.willing = 0;
10710                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10711                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10712                         hw->local_dcbx_config.etscfg.tsatable[0] =
10713                                                 I40E_IEEE_TSA_ETS;
10714                         /* all UPs mapping to TC0 */
10715                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10716                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10717                         hw->local_dcbx_config.etsrec =
10718                                 hw->local_dcbx_config.etscfg;
10719                         hw->local_dcbx_config.pfc.willing = 0;
10720                         hw->local_dcbx_config.pfc.pfccap =
10721                                                 I40E_MAX_TRAFFIC_CLASS;
10722                         /* FW needs one App to configure HW */
10723                         hw->local_dcbx_config.numapps = 1;
10724                         hw->local_dcbx_config.app[0].selector =
10725                                                 I40E_APP_SEL_ETHTYPE;
10726                         hw->local_dcbx_config.app[0].priority = 3;
10727                         hw->local_dcbx_config.app[0].protocolid =
10728                                                 I40E_APP_PROTOID_FCOE;
10729                         ret = i40e_set_dcb_config(hw);
10730                         if (ret) {
10731                                 PMD_INIT_LOG(ERR,
10732                                         "default dcb config fails. err = %d, aq_err = %d.",
10733                                         ret, hw->aq.asq_last_status);
10734                                 return -ENOSYS;
10735                         }
10736                 } else {
10737                         PMD_INIT_LOG(ERR,
10738                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10739                                 ret, hw->aq.asq_last_status);
10740                         return -ENOTSUP;
10741                 }
10742         } else {
10743                 ret = i40e_aq_start_lldp(hw, NULL);
10744                 if (ret != I40E_SUCCESS)
10745                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10746
10747                 ret = i40e_init_dcb(hw);
10748                 if (!ret) {
10749                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10750                                 PMD_INIT_LOG(ERR,
10751                                         "HW doesn't support DCBX offload.");
10752                                 return -ENOTSUP;
10753                         }
10754                 } else {
10755                         PMD_INIT_LOG(ERR,
10756                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10757                                 ret, hw->aq.asq_last_status);
10758                         return -ENOTSUP;
10759                 }
10760         }
10761         return 0;
10762 }
10763
10764 /*
10765  * i40e_dcb_setup - setup dcb related config
10766  * @dev: device being configured
10767  *
10768  * Returns 0 on success, negative value on failure
10769  */
10770 static int
10771 i40e_dcb_setup(struct rte_eth_dev *dev)
10772 {
10773         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10774         struct i40e_dcbx_config dcb_cfg;
10775         uint8_t tc_map = 0;
10776         int ret = 0;
10777
10778         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10779                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10780                 return -ENOTSUP;
10781         }
10782
10783         if (pf->vf_num != 0)
10784                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10785
10786         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10787         if (ret) {
10788                 PMD_INIT_LOG(ERR, "invalid dcb config");
10789                 return -EINVAL;
10790         }
10791         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10792         if (ret) {
10793                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10794                 return -ENOSYS;
10795         }
10796
10797         return 0;
10798 }
10799
10800 static int
10801 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10802                       struct rte_eth_dcb_info *dcb_info)
10803 {
10804         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10806         struct i40e_vsi *vsi = pf->main_vsi;
10807         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10808         uint16_t bsf, tc_mapping;
10809         int i, j = 0;
10810
10811         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10812                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10813         else
10814                 dcb_info->nb_tcs = 1;
10815         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10816                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10817         for (i = 0; i < dcb_info->nb_tcs; i++)
10818                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10819
10820         /* get queue mapping if vmdq is disabled */
10821         if (!pf->nb_cfg_vmdq_vsi) {
10822                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10823                         if (!(vsi->enabled_tc & (1 << i)))
10824                                 continue;
10825                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10826                         dcb_info->tc_queue.tc_rxq[j][i].base =
10827                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10828                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10829                         dcb_info->tc_queue.tc_txq[j][i].base =
10830                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10831                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10832                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10833                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10834                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10835                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10836                 }
10837                 return 0;
10838         }
10839
10840         /* get queue mapping if vmdq is enabled */
10841         do {
10842                 vsi = pf->vmdq[j].vsi;
10843                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10844                         if (!(vsi->enabled_tc & (1 << i)))
10845                                 continue;
10846                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10847                         dcb_info->tc_queue.tc_rxq[j][i].base =
10848                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10849                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10850                         dcb_info->tc_queue.tc_txq[j][i].base =
10851                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10852                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10853                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10854                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10855                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10856                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10857                 }
10858                 j++;
10859         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10860         return 0;
10861 }
10862
10863 static int
10864 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10865 {
10866         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10867         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10869         uint16_t interval =
10870                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10871         uint16_t msix_intr;
10872
10873         msix_intr = intr_handle->intr_vec[queue_id];
10874         if (msix_intr == I40E_MISC_VEC_ID)
10875                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10876                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10877                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10878                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10879                                (interval <<
10880                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10881         else
10882                 I40E_WRITE_REG(hw,
10883                                I40E_PFINT_DYN_CTLN(msix_intr -
10884                                                    I40E_RX_VEC_START),
10885                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10886                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10887                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10888                                (interval <<
10889                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10890
10891         I40E_WRITE_FLUSH(hw);
10892         rte_intr_enable(&pci_dev->intr_handle);
10893
10894         return 0;
10895 }
10896
10897 static int
10898 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10899 {
10900         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10901         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10903         uint16_t msix_intr;
10904
10905         msix_intr = intr_handle->intr_vec[queue_id];
10906         if (msix_intr == I40E_MISC_VEC_ID)
10907                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10908         else
10909                 I40E_WRITE_REG(hw,
10910                                I40E_PFINT_DYN_CTLN(msix_intr -
10911                                                    I40E_RX_VEC_START),
10912                                0);
10913         I40E_WRITE_FLUSH(hw);
10914
10915         return 0;
10916 }
10917
10918 static int i40e_get_regs(struct rte_eth_dev *dev,
10919                          struct rte_dev_reg_info *regs)
10920 {
10921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10922         uint32_t *ptr_data = regs->data;
10923         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10924         const struct i40e_reg_info *reg_info;
10925
10926         if (ptr_data == NULL) {
10927                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10928                 regs->width = sizeof(uint32_t);
10929                 return 0;
10930         }
10931
10932         /* The first few registers have to be read using AQ operations */
10933         reg_idx = 0;
10934         while (i40e_regs_adminq[reg_idx].name) {
10935                 reg_info = &i40e_regs_adminq[reg_idx++];
10936                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10937                         for (arr_idx2 = 0;
10938                                         arr_idx2 <= reg_info->count2;
10939                                         arr_idx2++) {
10940                                 reg_offset = arr_idx * reg_info->stride1 +
10941                                         arr_idx2 * reg_info->stride2;
10942                                 reg_offset += reg_info->base_addr;
10943                                 ptr_data[reg_offset >> 2] =
10944                                         i40e_read_rx_ctl(hw, reg_offset);
10945                         }
10946         }
10947
10948         /* The remaining registers can be read using primitives */
10949         reg_idx = 0;
10950         while (i40e_regs_others[reg_idx].name) {
10951                 reg_info = &i40e_regs_others[reg_idx++];
10952                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10953                         for (arr_idx2 = 0;
10954                                         arr_idx2 <= reg_info->count2;
10955                                         arr_idx2++) {
10956                                 reg_offset = arr_idx * reg_info->stride1 +
10957                                         arr_idx2 * reg_info->stride2;
10958                                 reg_offset += reg_info->base_addr;
10959                                 ptr_data[reg_offset >> 2] =
10960                                         I40E_READ_REG(hw, reg_offset);
10961                         }
10962         }
10963
10964         return 0;
10965 }
10966
10967 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10968 {
10969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10970
10971         /* Convert word count to byte count */
10972         return hw->nvm.sr_size << 1;
10973 }
10974
10975 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10976                            struct rte_dev_eeprom_info *eeprom)
10977 {
10978         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10979         uint16_t *data = eeprom->data;
10980         uint16_t offset, length, cnt_words;
10981         int ret_code;
10982
10983         offset = eeprom->offset >> 1;
10984         length = eeprom->length >> 1;
10985         cnt_words = length;
10986
10987         if (offset > hw->nvm.sr_size ||
10988                 offset + length > hw->nvm.sr_size) {
10989                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10990                 return -EINVAL;
10991         }
10992
10993         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10994
10995         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10996         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10997                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10998                 return -EIO;
10999         }
11000
11001         return 0;
11002 }
11003
11004 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11005                                       struct ether_addr *mac_addr)
11006 {
11007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11008         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11009         struct i40e_vsi *vsi = pf->main_vsi;
11010         struct i40e_mac_filter_info mac_filter;
11011         struct i40e_mac_filter *f;
11012         int ret;
11013
11014         if (!is_valid_assigned_ether_addr(mac_addr)) {
11015                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11016                 return;
11017         }
11018
11019         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11020                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11021                         break;
11022         }
11023
11024         if (f == NULL) {
11025                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11026                 return;
11027         }
11028
11029         mac_filter = f->mac_info;
11030         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11031         if (ret != I40E_SUCCESS) {
11032                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11033                 return;
11034         }
11035         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11036         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11037         if (ret != I40E_SUCCESS) {
11038                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11039                 return;
11040         }
11041         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11042
11043         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11044                                   mac_addr->addr_bytes, NULL);
11045 }
11046
11047 static int
11048 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11049 {
11050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11051         struct rte_eth_dev_data *dev_data = pf->dev_data;
11052         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11053         int ret = 0;
11054
11055         /* check if mtu is within the allowed range */
11056         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11057                 return -EINVAL;
11058
11059         /* mtu setting is forbidden if port is start */
11060         if (dev_data->dev_started) {
11061                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11062                             dev_data->port_id);
11063                 return -EBUSY;
11064         }
11065
11066         if (frame_size > ETHER_MAX_LEN)
11067                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11068         else
11069                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11070
11071         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11072
11073         return ret;
11074 }
11075
11076 /* Restore ethertype filter */
11077 static void
11078 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11079 {
11080         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11081         struct i40e_ethertype_filter_list
11082                 *ethertype_list = &pf->ethertype.ethertype_list;
11083         struct i40e_ethertype_filter *f;
11084         struct i40e_control_filter_stats stats;
11085         uint16_t flags;
11086
11087         TAILQ_FOREACH(f, ethertype_list, rules) {
11088                 flags = 0;
11089                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11090                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11091                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11092                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11093                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11094
11095                 memset(&stats, 0, sizeof(stats));
11096                 i40e_aq_add_rem_control_packet_filter(hw,
11097                                             f->input.mac_addr.addr_bytes,
11098                                             f->input.ether_type,
11099                                             flags, pf->main_vsi->seid,
11100                                             f->queue, 1, &stats, NULL);
11101         }
11102         PMD_DRV_LOG(INFO, "Ethertype filter:"
11103                     " mac_etype_used = %u, etype_used = %u,"
11104                     " mac_etype_free = %u, etype_free = %u",
11105                     stats.mac_etype_used, stats.etype_used,
11106                     stats.mac_etype_free, stats.etype_free);
11107 }
11108
11109 /* Restore tunnel filter */
11110 static void
11111 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11112 {
11113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11114         struct i40e_vsi *vsi;
11115         struct i40e_pf_vf *vf;
11116         struct i40e_tunnel_filter_list
11117                 *tunnel_list = &pf->tunnel.tunnel_list;
11118         struct i40e_tunnel_filter *f;
11119         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11120         bool big_buffer = 0;
11121
11122         TAILQ_FOREACH(f, tunnel_list, rules) {
11123                 if (!f->is_to_vf)
11124                         vsi = pf->main_vsi;
11125                 else {
11126                         vf = &pf->vfs[f->vf_id];
11127                         vsi = vf->vsi;
11128                 }
11129                 memset(&cld_filter, 0, sizeof(cld_filter));
11130                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11131                         (struct ether_addr *)&cld_filter.element.outer_mac);
11132                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11133                         (struct ether_addr *)&cld_filter.element.inner_mac);
11134                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11135                 cld_filter.element.flags = f->input.flags;
11136                 cld_filter.element.tenant_id = f->input.tenant_id;
11137                 cld_filter.element.queue_number = f->queue;
11138                 rte_memcpy(cld_filter.general_fields,
11139                            f->input.general_fields,
11140                            sizeof(f->input.general_fields));
11141
11142                 if (((f->input.flags &
11143                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11144                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11145                     ((f->input.flags &
11146                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11147                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11148                     ((f->input.flags &
11149                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11150                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11151                         big_buffer = 1;
11152
11153                 if (big_buffer)
11154                         i40e_aq_add_cloud_filters_big_buffer(hw,
11155                                              vsi->seid, &cld_filter, 1);
11156                 else
11157                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11158                                                   &cld_filter.element, 1);
11159         }
11160 }
11161
11162 /* Restore rss filter */
11163 static inline void
11164 i40e_rss_filter_restore(struct i40e_pf *pf)
11165 {
11166         struct i40e_rte_flow_rss_conf *conf =
11167                                         &pf->rss_info;
11168         if (conf->num)
11169                 i40e_config_rss_filter(pf, conf, TRUE);
11170 }
11171
11172 static void
11173 i40e_filter_restore(struct i40e_pf *pf)
11174 {
11175         i40e_ethertype_filter_restore(pf);
11176         i40e_tunnel_filter_restore(pf);
11177         i40e_fdir_filter_restore(pf);
11178         i40e_rss_filter_restore(pf);
11179 }
11180
11181 static bool
11182 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11183 {
11184         if (strcmp(dev->device->driver->name, drv->driver.name))
11185                 return false;
11186
11187         return true;
11188 }
11189
11190 bool
11191 is_i40e_supported(struct rte_eth_dev *dev)
11192 {
11193         return is_device_supported(dev, &rte_i40e_pmd);
11194 }
11195
11196 struct i40e_customized_pctype*
11197 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11198 {
11199         int i;
11200
11201         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11202                 if (pf->customized_pctype[i].index == index)
11203                         return &pf->customized_pctype[i];
11204         }
11205         return NULL;
11206 }
11207
11208 static int
11209 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11210                               uint32_t pkg_size, uint32_t proto_num,
11211                               struct rte_pmd_i40e_proto_info *proto)
11212 {
11213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11214         uint32_t pctype_num;
11215         struct rte_pmd_i40e_ptype_info *pctype;
11216         uint32_t buff_size;
11217         struct i40e_customized_pctype *new_pctype = NULL;
11218         uint8_t proto_id;
11219         uint8_t pctype_value;
11220         char name[64];
11221         uint32_t i, j, n;
11222         int ret;
11223
11224         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11225                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11226                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11227         if (ret) {
11228                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11229                 return -1;
11230         }
11231         if (!pctype_num) {
11232                 PMD_DRV_LOG(INFO, "No new pctype added");
11233                 return -1;
11234         }
11235
11236         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11237         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11238         if (!pctype) {
11239                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11240                 return -1;
11241         }
11242         /* get information about new pctype list */
11243         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11244                                         (uint8_t *)pctype, buff_size,
11245                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11246         if (ret) {
11247                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11248                 rte_free(pctype);
11249                 return -1;
11250         }
11251
11252         /* Update customized pctype. */
11253         for (i = 0; i < pctype_num; i++) {
11254                 pctype_value = pctype[i].ptype_id;
11255                 memset(name, 0, sizeof(name));
11256                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11257                         proto_id = pctype[i].protocols[j];
11258                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11259                                 continue;
11260                         for (n = 0; n < proto_num; n++) {
11261                                 if (proto[n].proto_id != proto_id)
11262                                         continue;
11263                                 strcat(name, proto[n].name);
11264                                 strcat(name, "_");
11265                                 break;
11266                         }
11267                 }
11268                 name[strlen(name) - 1] = '\0';
11269                 if (!strcmp(name, "GTPC"))
11270                         new_pctype =
11271                                 i40e_find_customized_pctype(pf,
11272                                                       I40E_CUSTOMIZED_GTPC);
11273                 else if (!strcmp(name, "GTPU_IPV4"))
11274                         new_pctype =
11275                                 i40e_find_customized_pctype(pf,
11276                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11277                 else if (!strcmp(name, "GTPU_IPV6"))
11278                         new_pctype =
11279                                 i40e_find_customized_pctype(pf,
11280                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11281                 else if (!strcmp(name, "GTPU"))
11282                         new_pctype =
11283                                 i40e_find_customized_pctype(pf,
11284                                                       I40E_CUSTOMIZED_GTPU);
11285                 if (new_pctype) {
11286                         new_pctype->pctype = pctype_value;
11287                         new_pctype->valid = true;
11288                 }
11289         }
11290
11291         rte_free(pctype);
11292         return 0;
11293 }
11294
11295 static int
11296 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11297                                uint32_t pkg_size, uint32_t proto_num,
11298                                struct rte_pmd_i40e_proto_info *proto)
11299 {
11300         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11301         uint16_t port_id = dev->data->port_id;
11302         uint32_t ptype_num;
11303         struct rte_pmd_i40e_ptype_info *ptype;
11304         uint32_t buff_size;
11305         uint8_t proto_id;
11306         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11307         uint32_t i, j, n;
11308         bool in_tunnel;
11309         int ret;
11310
11311         /* get information about new ptype num */
11312         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11313                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11314                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11315         if (ret) {
11316                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11317                 return ret;
11318         }
11319         if (!ptype_num) {
11320                 PMD_DRV_LOG(INFO, "No new ptype added");
11321                 return -1;
11322         }
11323
11324         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11325         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11326         if (!ptype) {
11327                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11328                 return -1;
11329         }
11330
11331         /* get information about new ptype list */
11332         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11333                                         (uint8_t *)ptype, buff_size,
11334                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11335         if (ret) {
11336                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11337                 rte_free(ptype);
11338                 return ret;
11339         }
11340
11341         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11342         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11343         if (!ptype_mapping) {
11344                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11345                 rte_free(ptype);
11346                 return -1;
11347         }
11348
11349         /* Update ptype mapping table. */
11350         for (i = 0; i < ptype_num; i++) {
11351                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11352                 ptype_mapping[i].sw_ptype = 0;
11353                 in_tunnel = false;
11354                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11355                         proto_id = ptype[i].protocols[j];
11356                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11357                                 continue;
11358                         for (n = 0; n < proto_num; n++) {
11359                                 if (proto[n].proto_id != proto_id)
11360                                         continue;
11361                                 memset(name, 0, sizeof(name));
11362                                 strcpy(name, proto[n].name);
11363                                 if (!strncasecmp(name, "PPPOE", 5))
11364                                         ptype_mapping[i].sw_ptype |=
11365                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11366                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11367                                          !in_tunnel) {
11368                                         ptype_mapping[i].sw_ptype |=
11369                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11370                                         ptype_mapping[i].sw_ptype |=
11371                                                 RTE_PTYPE_L4_FRAG;
11372                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11373                                            in_tunnel) {
11374                                         ptype_mapping[i].sw_ptype |=
11375                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11376                                         ptype_mapping[i].sw_ptype |=
11377                                                 RTE_PTYPE_INNER_L4_FRAG;
11378                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11379                                         ptype_mapping[i].sw_ptype |=
11380                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11381                                         in_tunnel = true;
11382                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11383                                            !in_tunnel)
11384                                         ptype_mapping[i].sw_ptype |=
11385                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11386                                 else if (!strncasecmp(name, "IPV4", 4) &&
11387                                          in_tunnel)
11388                                         ptype_mapping[i].sw_ptype |=
11389                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11390                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11391                                          !in_tunnel) {
11392                                         ptype_mapping[i].sw_ptype |=
11393                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11394                                         ptype_mapping[i].sw_ptype |=
11395                                                 RTE_PTYPE_L4_FRAG;
11396                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11397                                            in_tunnel) {
11398                                         ptype_mapping[i].sw_ptype |=
11399                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11400                                         ptype_mapping[i].sw_ptype |=
11401                                                 RTE_PTYPE_INNER_L4_FRAG;
11402                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11403                                         ptype_mapping[i].sw_ptype |=
11404                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11405                                         in_tunnel = true;
11406                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11407                                            !in_tunnel)
11408                                         ptype_mapping[i].sw_ptype |=
11409                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11410                                 else if (!strncasecmp(name, "IPV6", 4) &&
11411                                          in_tunnel)
11412                                         ptype_mapping[i].sw_ptype |=
11413                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11414                                 else if (!strncasecmp(name, "UDP", 3) &&
11415                                          !in_tunnel)
11416                                         ptype_mapping[i].sw_ptype |=
11417                                                 RTE_PTYPE_L4_UDP;
11418                                 else if (!strncasecmp(name, "UDP", 3) &&
11419                                          in_tunnel)
11420                                         ptype_mapping[i].sw_ptype |=
11421                                                 RTE_PTYPE_INNER_L4_UDP;
11422                                 else if (!strncasecmp(name, "TCP", 3) &&
11423                                          !in_tunnel)
11424                                         ptype_mapping[i].sw_ptype |=
11425                                                 RTE_PTYPE_L4_TCP;
11426                                 else if (!strncasecmp(name, "TCP", 3) &&
11427                                          in_tunnel)
11428                                         ptype_mapping[i].sw_ptype |=
11429                                                 RTE_PTYPE_INNER_L4_TCP;
11430                                 else if (!strncasecmp(name, "SCTP", 4) &&
11431                                          !in_tunnel)
11432                                         ptype_mapping[i].sw_ptype |=
11433                                                 RTE_PTYPE_L4_SCTP;
11434                                 else if (!strncasecmp(name, "SCTP", 4) &&
11435                                          in_tunnel)
11436                                         ptype_mapping[i].sw_ptype |=
11437                                                 RTE_PTYPE_INNER_L4_SCTP;
11438                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11439                                           !strncasecmp(name, "ICMPV6", 6)) &&
11440                                          !in_tunnel)
11441                                         ptype_mapping[i].sw_ptype |=
11442                                                 RTE_PTYPE_L4_ICMP;
11443                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11444                                           !strncasecmp(name, "ICMPV6", 6)) &&
11445                                          in_tunnel)
11446                                         ptype_mapping[i].sw_ptype |=
11447                                                 RTE_PTYPE_INNER_L4_ICMP;
11448                                 else if (!strncasecmp(name, "GTPC", 4)) {
11449                                         ptype_mapping[i].sw_ptype |=
11450                                                 RTE_PTYPE_TUNNEL_GTPC;
11451                                         in_tunnel = true;
11452                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11453                                         ptype_mapping[i].sw_ptype |=
11454                                                 RTE_PTYPE_TUNNEL_GTPU;
11455                                         in_tunnel = true;
11456                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11457                                         ptype_mapping[i].sw_ptype |=
11458                                                 RTE_PTYPE_TUNNEL_GRENAT;
11459                                         in_tunnel = true;
11460                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11461                                         ptype_mapping[i].sw_ptype |=
11462                                                 RTE_PTYPE_TUNNEL_L2TP;
11463                                         in_tunnel = true;
11464                                 }
11465
11466                                 break;
11467                         }
11468                 }
11469         }
11470
11471         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11472                                                 ptype_num, 0);
11473         if (ret)
11474                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11475
11476         rte_free(ptype_mapping);
11477         rte_free(ptype);
11478         return ret;
11479 }
11480
11481 void
11482 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11483                               uint32_t pkg_size)
11484 {
11485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11486         uint32_t proto_num;
11487         struct rte_pmd_i40e_proto_info *proto;
11488         uint32_t buff_size;
11489         uint32_t i;
11490         int ret;
11491
11492         /* get information about protocol number */
11493         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11494                                        (uint8_t *)&proto_num, sizeof(proto_num),
11495                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11496         if (ret) {
11497                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11498                 return;
11499         }
11500         if (!proto_num) {
11501                 PMD_DRV_LOG(INFO, "No new protocol added");
11502                 return;
11503         }
11504
11505         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11506         proto = rte_zmalloc("new_proto", buff_size, 0);
11507         if (!proto) {
11508                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11509                 return;
11510         }
11511
11512         /* get information about protocol list */
11513         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11514                                         (uint8_t *)proto, buff_size,
11515                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11516         if (ret) {
11517                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11518                 rte_free(proto);
11519                 return;
11520         }
11521
11522         /* Check if GTP is supported. */
11523         for (i = 0; i < proto_num; i++) {
11524                 if (!strncmp(proto[i].name, "GTP", 3)) {
11525                         pf->gtp_support = true;
11526                         break;
11527                 }
11528         }
11529
11530         /* Update customized pctype info */
11531         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11532                                             proto_num, proto);
11533         if (ret)
11534                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11535
11536         /* Update customized ptype info */
11537         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11538                                            proto_num, proto);
11539         if (ret)
11540                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11541
11542         rte_free(proto);
11543 }
11544
11545 /* Create a QinQ cloud filter
11546  *
11547  * The Fortville NIC has limited resources for tunnel filters,
11548  * so we can only reuse existing filters.
11549  *
11550  * In step 1 we define which Field Vector fields can be used for
11551  * filter types.
11552  * As we do not have the inner tag defined as a field,
11553  * we have to define it first, by reusing one of L1 entries.
11554  *
11555  * In step 2 we are replacing one of existing filter types with
11556  * a new one for QinQ.
11557  * As we reusing L1 and replacing L2, some of the default filter
11558  * types will disappear,which depends on L1 and L2 entries we reuse.
11559  *
11560  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11561  *
11562  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11563  *              later when we define the cloud filter.
11564  *      a.      Valid_flags.replace_cloud = 0
11565  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11566  *      c.      New_filter = 0x10
11567  *      d.      TR bit = 0xff (optional, not used here)
11568  *      e.      Buffer – 2 entries:
11569  *              i.      Byte 0 = 8 (outer vlan FV index).
11570  *                      Byte 1 = 0 (rsv)
11571  *                      Byte 2-3 = 0x0fff
11572  *              ii.     Byte 0 = 37 (inner vlan FV index).
11573  *                      Byte 1 =0 (rsv)
11574  *                      Byte 2-3 = 0x0fff
11575  *
11576  * Step 2:
11577  * 2.   Create cloud filter using two L1 filters entries: stag and
11578  *              new filter(outer vlan+ inner vlan)
11579  *      a.      Valid_flags.replace_cloud = 1
11580  *      b.      Old_filter = 1 (instead of outer IP)
11581  *      c.      New_filter = 0x10
11582  *      d.      Buffer – 2 entries:
11583  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11584  *                      Byte 1-3 = 0 (rsv)
11585  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11586  *                      Byte 9-11 = 0 (rsv)
11587  */
11588 static int
11589 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11590 {
11591         int ret = -ENOTSUP;
11592         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11593         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11594         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11595
11596         /* Init */
11597         memset(&filter_replace, 0,
11598                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11599         memset(&filter_replace_buf, 0,
11600                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11601
11602         /* create L1 filter */
11603         filter_replace.old_filter_type =
11604                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11605         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11606         filter_replace.tr_bit = 0;
11607
11608         /* Prepare the buffer, 2 entries */
11609         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11610         filter_replace_buf.data[0] |=
11611                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11612         /* Field Vector 12b mask */
11613         filter_replace_buf.data[2] = 0xff;
11614         filter_replace_buf.data[3] = 0x0f;
11615         filter_replace_buf.data[4] =
11616                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11617         filter_replace_buf.data[4] |=
11618                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11619         /* Field Vector 12b mask */
11620         filter_replace_buf.data[6] = 0xff;
11621         filter_replace_buf.data[7] = 0x0f;
11622         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11623                         &filter_replace_buf);
11624         if (ret != I40E_SUCCESS)
11625                 return ret;
11626
11627         /* Apply the second L2 cloud filter */
11628         memset(&filter_replace, 0,
11629                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11630         memset(&filter_replace_buf, 0,
11631                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11632
11633         /* create L2 filter, input for L2 filter will be L1 filter  */
11634         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11635         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11636         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11637
11638         /* Prepare the buffer, 2 entries */
11639         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11640         filter_replace_buf.data[0] |=
11641                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11642         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11643         filter_replace_buf.data[4] |=
11644                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11645         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11646                         &filter_replace_buf);
11647         return ret;
11648 }
11649
11650 int
11651 i40e_config_rss_filter(struct i40e_pf *pf,
11652                 struct i40e_rte_flow_rss_conf *conf, bool add)
11653 {
11654         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11655         uint32_t i, lut = 0;
11656         uint16_t j, num;
11657         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11658         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11659
11660         if (!add) {
11661                 if (memcmp(conf, rss_info,
11662                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11663                         i40e_pf_disable_rss(pf);
11664                         memset(rss_info, 0,
11665                                 sizeof(struct i40e_rte_flow_rss_conf));
11666                         return 0;
11667                 }
11668                 return -EINVAL;
11669         }
11670
11671         if (rss_info->num)
11672                 return -EINVAL;
11673
11674         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11675          * It's necessary to calculate the actual PF queues that are configured.
11676          */
11677         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11678                 num = i40e_pf_calc_configured_queues_num(pf);
11679         else
11680                 num = pf->dev_data->nb_rx_queues;
11681
11682         num = RTE_MIN(num, conf->num);
11683         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11684                         num);
11685
11686         if (num == 0) {
11687                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11688                 return -ENOTSUP;
11689         }
11690
11691         /* Fill in redirection table */
11692         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11693                 if (j == num)
11694                         j = 0;
11695                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11696                         hw->func_caps.rss_table_entry_width) - 1));
11697                 if ((i & 3) == 3)
11698                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11699         }
11700
11701         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11702                 i40e_pf_disable_rss(pf);
11703                 return 0;
11704         }
11705         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11706                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11707                 /* Random default keys */
11708                 static uint32_t rss_key_default[] = {0x6b793944,
11709                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11710                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11711                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11712
11713                 rss_conf.rss_key = (uint8_t *)rss_key_default;
11714                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11715                                                         sizeof(uint32_t);
11716         }
11717
11718         i40e_hw_rss_hash_set(pf, &rss_conf);
11719
11720         rte_memcpy(rss_info,
11721                 conf, sizeof(struct i40e_rte_flow_rss_conf));
11722
11723         return 0;
11724 }
11725
11726 RTE_INIT(i40e_init_log);
11727 static void
11728 i40e_init_log(void)
11729 {
11730         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
11731         if (i40e_logtype_init >= 0)
11732                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11733         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
11734         if (i40e_logtype_driver >= 0)
11735                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11736 }