drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 242                                             uint16_t queue_id,
 243                                             uint8_t stat_idx,
 244                                             uint8_t is_rx);
 245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 246                                 char *fw_version, size_t fw_size);
 247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 248                               struct rte_eth_dev_info *dev_info);
 249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 250                                 uint16_t vlan_id,
 251                                 int on);
 252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 253                               enum rte_vlan_type vlan_type,
 254                               uint16_t tpid);
 255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 257                                       uint16_t queue,
 258                                       int on);
 259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 263                               struct rte_eth_fc_conf *fc_conf);
 264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 265                               struct rte_eth_fc_conf *fc_conf);
 266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 267                                        struct rte_eth_pfc_conf *pfc_conf);
 268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 269                             struct ether_addr *mac_addr,
 270                             uint32_t index,
 271                             uint32_t pool);
 272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 274                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                     uint16_t reta_size);
 276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 277                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 278                                    uint16_t reta_size);
 279
 280 static int i40e_get_cap(struct i40e_hw *hw);
 281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 282 static int i40e_pf_setup(struct i40e_pf *pf);
 283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 287                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 288 static void i40e_stat_update_48(struct i40e_hw *hw,
 289                                uint32_t hireg,
 290                                uint32_t loreg,
 291                                bool offset_loaded,
 292                                uint64_t *offset,
 293                                uint64_t *stat);
 294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 295 static void i40e_dev_interrupt_handler(void *param);
 296 static void i40e_dev_alarm_handler(void *param);
 297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 298                                 uint32_t base, uint32_t num);
 299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 301                         uint32_t base);
 302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 303                         uint16_t num);
 304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 305 static int i40e_veb_release(struct i40e_veb *veb);
 306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 307                                                 struct i40e_vsi *vsi);
 308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 311                                              struct i40e_macvlan_filter *mv_f,
 312                                              int num,
 313                                              uint16_t vlan);
 314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 316                                     struct rte_eth_rss_conf *rss_conf);
 317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 318                                       struct rte_eth_rss_conf *rss_conf);
 319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 320                                         struct rte_eth_udp_tunnel *udp_tunnel);
 321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 322                                         struct rte_eth_udp_tunnel *udp_tunnel);
 323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 328                                 enum rte_filter_type filter_type,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                   struct rte_eth_dcb_info *dcb_info);
 333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 334 static void i40e_configure_registers(struct i40e_hw *hw);
 335 static void i40e_hw_init(struct rte_eth_dev *dev);
 336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 338                                                      uint16_t seid,
 339                                                      uint16_t rule_type,
 340                                                      uint16_t *entries,
 341                                                      uint16_t count,
 342                                                      uint16_t rule_id);
 343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 344                         struct rte_eth_mirror_conf *mirror_conf,
 345                         uint8_t sw_id, uint8_t on);
 346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 347
 348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp,
 352                                            uint32_t flags);
 353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp);
 355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 356
 357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 358
 359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 362                                     const struct timespec *timestamp);
 363
 364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 365                                          uint16_t queue_id);
 366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 367                                           uint16_t queue_id);
 368
 369 static int i40e_get_regs(struct rte_eth_dev *dev,
 370                          struct rte_dev_reg_info *regs);
 371
 372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 373
 374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 375                            struct rte_dev_eeprom_info *eeprom);
 376
 377 static int i40e_get_module_info(struct rte_eth_dev *dev,
 378                                 struct rte_eth_dev_module_info *modinfo);
 379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 380                                   struct rte_dev_eeprom_info *info);
 381
 382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 383                                       struct ether_addr *mac_addr);
 384
 385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 386
 387 static int i40e_ethertype_filter_convert(
 388         const struct rte_eth_ethertype_filter *input,
 389         struct i40e_ethertype_filter *filter);
 390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 391                                    struct i40e_ethertype_filter *filter);
 392
 393 static int i40e_tunnel_filter_convert(
 394         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 395         struct i40e_tunnel_filter *tunnel_filter);
 396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 397                                 struct i40e_tunnel_filter *tunnel_filter);
 398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 399
 400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 402 static void i40e_filter_restore(struct i40e_pf *pf);
 403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 404
 405 int i40e_logtype_init;
 406 int i40e_logtype_driver;
 407
 408 static const char *const valid_keys[] = {
 409         ETH_I40E_FLOATING_VEB_ARG,
 410         ETH_I40E_FLOATING_VEB_LIST_ARG,
 411         ETH_I40E_SUPPORT_MULTI_DRIVER,
 412         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 413         ETH_I40E_USE_LATEST_VEC,
 414         NULL};
 415
 416 static const struct rte_pci_id pci_id_i40e_map[] = {
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 437         { .vendor_id = 0, /* sentinel */ },
 438 };
 439
 440 static const struct eth_dev_ops i40e_eth_dev_ops = {
 441         .dev_configure                = i40e_dev_configure,
 442         .dev_start                    = i40e_dev_start,
 443         .dev_stop                     = i40e_dev_stop,
 444         .dev_close                    = i40e_dev_close,
 445         .dev_reset                    = i40e_dev_reset,
 446         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 447         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 448         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 449         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 450         .dev_set_link_up              = i40e_dev_set_link_up,
 451         .dev_set_link_down            = i40e_dev_set_link_down,
 452         .link_update                  = i40e_dev_link_update,
 453         .stats_get                    = i40e_dev_stats_get,
 454         .xstats_get                   = i40e_dev_xstats_get,
 455         .xstats_get_names             = i40e_dev_xstats_get_names,
 456         .stats_reset                  = i40e_dev_stats_reset,
 457         .xstats_reset                 = i40e_dev_stats_reset,
 458         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .mirror_rule_set              = i40e_mirror_rule_set,
 498         .mirror_rule_reset            = i40e_mirror_rule_reset,
 499         .timesync_enable              = i40e_timesync_enable,
 500         .timesync_disable             = i40e_timesync_disable,
 501         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 502         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 503         .get_dcb_info                 = i40e_dev_get_dcb_info,
 504         .timesync_adjust_time         = i40e_timesync_adjust_time,
 505         .timesync_read_time           = i40e_timesync_read_time,
 506         .timesync_write_time          = i40e_timesync_write_time,
 507         .get_reg                      = i40e_get_regs,
 508         .get_eeprom_length            = i40e_get_eeprom_length,
 509         .get_eeprom                   = i40e_get_eeprom,
 510         .get_module_info              = i40e_get_module_info,
 511         .get_module_eeprom            = i40e_get_module_eeprom,
 512         .mac_addr_set                 = i40e_set_default_mac_addr,
 513         .mtu_set                      = i40e_dev_mtu_set,
 514         .tm_ops_get                   = i40e_tm_ops_get,
 515 };
 516
 517 /* store statistics names and its offset in stats structure */
 518 struct rte_i40e_xstats_name_off {
 519         char name[RTE_ETH_XSTATS_NAME_SIZE];
 520         unsigned offset;
 521 };
 522
 523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 524         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 525         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 526         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 527         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 528         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 529                 rx_unknown_protocol)},
 530         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 531         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 532         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 533         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 534 };
 535
 536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 537                 sizeof(rte_i40e_stats_strings[0]))
 538
 539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 540         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 541                 tx_dropped_link_down)},
 542         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 543         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 544                 illegal_bytes)},
 545         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 546         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 547                 mac_local_faults)},
 548         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_remote_faults)},
 550         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_length_errors)},
 552         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 553         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 554         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 555         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 556         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 557         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 558                 rx_size_127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_255)},
 561         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_511)},
 563         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_1023)},
 565         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1522)},
 567         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_big)},
 569         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 570                 rx_undersize)},
 571         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_oversize)},
 573         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 574                 mac_short_packet_dropped)},
 575         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_fragments)},
 577         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 578         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 579         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 580                 tx_size_127)},
 581         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_255)},
 583         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_511)},
 585         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_1023)},
 587         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1522)},
 589         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_big)},
 591         {"rx_flow_director_atr_match_packets",
 592                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 593         {"rx_flow_director_sb_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 595         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 596                 tx_lpi_status)},
 597         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 rx_lpi_status)},
 599         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 600                 tx_lpi_count)},
 601         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 rx_lpi_count)},
 603 };
 604
 605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 606                 sizeof(rte_i40e_hw_port_strings[0]))
 607
 608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 609         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xon_rx)},
 611         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xoff_rx)},
 613 };
 614
 615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 616                 sizeof(rte_i40e_rxq_prio_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_tx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_tx)},
 623         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_2_xoff)},
 625 };
 626
 627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 628                 sizeof(rte_i40e_txq_prio_strings[0]))
 629
 630 static int
 631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 632         struct rte_pci_device *pci_dev)
 633 {
 634         char name[RTE_ETH_NAME_MAX_LEN];
 635         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 636         int i, retval;
 637
 638         if (pci_dev->device.devargs) {
 639                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 640                                 &eth_da);
 641                 if (retval)
 642                         return retval;
 643         }
 644
 645         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 646                 sizeof(struct i40e_adapter),
 647                 eth_dev_pci_specific_init, pci_dev,
 648                 eth_i40e_dev_init, NULL);
 649
 650         if (retval || eth_da.nb_representor_ports < 1)
 651                 return retval;
 652
 653         /* probe VF representor ports */
 654         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 655                 pci_dev->device.name);
 656
 657         if (pf_ethdev == NULL)
 658                 return -ENODEV;
 659
 660         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 661                 struct i40e_vf_representor representor = {
 662                         .vf_id = eth_da.representor_ports[i],
 663                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 664                                 pf_ethdev->data->dev_private)->switch_domain_id,
 665                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 666                                 pf_ethdev->data->dev_private)
 667                 };
 668
 669                 /* representor port net_bdf_port */
 670                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 671                         pci_dev->device.name, eth_da.representor_ports[i]);
 672
 673                 retval = rte_eth_dev_create(&pci_dev->device, name,
 674                         sizeof(struct i40e_vf_representor), NULL, NULL,
 675                         i40e_vf_representor_init, &representor);
 676
 677                 if (retval)
 678                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 679                                 "representor %s.", name);
 680         }
 681
 682         return 0;
 683 }
 684
 685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 686 {
 687         struct rte_eth_dev *ethdev;
 688
 689         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 690         if (!ethdev)
 691                 return -ENODEV;
 692
 693
 694         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 695                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 696         else
 697                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 698 }
 699
 700 static struct rte_pci_driver rte_i40e_pmd = {
 701         .id_table = pci_id_i40e_map,
 702         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 703                      RTE_PCI_DRV_IOVA_AS_VA,
 704         .probe = eth_i40e_pci_probe,
 705         .remove = eth_i40e_pci_remove,
 706 };
 707
 708 static inline void
 709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 710                          uint32_t reg_val)
 711 {
 712         uint32_t ori_reg_val;
 713         struct rte_eth_dev *dev;
 714
 715         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 716         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 717         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 718         if (ori_reg_val != reg_val)
 719                 PMD_DRV_LOG(WARNING,
 720                             "i40e device %s changed global register [0x%08x]."
 721                             " original: 0x%08x, new: 0x%08x",
 722                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 723 }
 724
 725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 728
 729 #ifndef I40E_GLQF_ORT
 730 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 731 #endif
 732 #ifndef I40E_GLQF_PIT
 733 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_L3_MAP
 736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 737 #endif
 738
 739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 740 {
 741         /*
 742          * Initialize registers for parsing packet type of QinQ
 743          * This should be removed from code once proper
 744          * configuration API is added to avoid configuration conflicts
 745          * between ports of the same device.
 746          */
 747         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 748         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 749 }
 750
 751 static inline void i40e_config_automask(struct i40e_pf *pf)
 752 {
 753         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 754         uint32_t val;
 755
 756         /* INTENA flag is not auto-cleared for interrupt */
 757         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 758         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 759                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 760
 761         /* If support multi-driver, PF will use INT0. */
 762         if (!pf->support_multi_driver)
 763                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 764
 765         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 766 }
 767
 768 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 769
 770 /*
 771  * Add a ethertype filter to drop all flow control frames transmitted
 772  * from VSIs.
 773 */
 774 static void
 775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 776 {
 777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 778         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 779                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 780                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 781         int ret;
 782
 783         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 784                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 785                                 pf->main_vsi_seid, 0,
 786                                 TRUE, NULL, NULL);
 787         if (ret)
 788                 PMD_INIT_LOG(ERR,
 789                         "Failed to add filter to drop flow control frames from VSIs.");
 790 }
 791
 792 static int
 793 floating_veb_list_handler(__rte_unused const char *key,
 794                           const char *floating_veb_value,
 795                           void *opaque)
 796 {
 797         int idx = 0;
 798         unsigned int count = 0;
 799         char *end = NULL;
 800         int min, max;
 801         bool *vf_floating_veb = opaque;
 802
 803         while (isblank(*floating_veb_value))
 804                 floating_veb_value++;
 805
 806         /* Reset floating VEB configuration for VFs */
 807         for (idx = 0; idx < I40E_MAX_VF; idx++)
 808                 vf_floating_veb[idx] = false;
 809
 810         min = I40E_MAX_VF;
 811         do {
 812                 while (isblank(*floating_veb_value))
 813                         floating_veb_value++;
 814                 if (*floating_veb_value == '\0')
 815                         return -1;
 816                 errno = 0;
 817                 idx = strtoul(floating_veb_value, &end, 10);
 818                 if (errno || end == NULL)
 819                         return -1;
 820                 while (isblank(*end))
 821                         end++;
 822                 if (*end == '-') {
 823                         min = idx;
 824                 } else if ((*end == ';') || (*end == '\0')) {
 825                         max = idx;
 826                         if (min == I40E_MAX_VF)
 827                                 min = idx;
 828                         if (max >= I40E_MAX_VF)
 829                                 max = I40E_MAX_VF - 1;
 830                         for (idx = min; idx <= max; idx++) {
 831                                 vf_floating_veb[idx] = true;
 832                                 count++;
 833                         }
 834                         min = I40E_MAX_VF;
 835                 } else {
 836                         return -1;
 837                 }
 838                 floating_veb_value = end + 1;
 839         } while (*end != '\0');
 840
 841         if (count == 0)
 842                 return -1;
 843
 844         return 0;
 845 }
 846
 847 static void
 848 config_vf_floating_veb(struct rte_devargs *devargs,
 849                        uint16_t floating_veb,
 850                        bool *vf_floating_veb)
 851 {
 852         struct rte_kvargs *kvlist;
 853         int i;
 854         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 855
 856         if (!floating_veb)
 857                 return;
 858         /* All the VFs attach to the floating VEB by default
 859          * when the floating VEB is enabled.
 860          */
 861         for (i = 0; i < I40E_MAX_VF; i++)
 862                 vf_floating_veb[i] = true;
 863
 864         if (devargs == NULL)
 865                 return;
 866
 867         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 868         if (kvlist == NULL)
 869                 return;
 870
 871         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 872                 rte_kvargs_free(kvlist);
 873                 return;
 874         }
 875         /* When the floating_veb_list parameter exists, all the VFs
 876          * will attach to the legacy VEB firstly, then configure VFs
 877          * to the floating VEB according to the floating_veb_list.
 878          */
 879         if (rte_kvargs_process(kvlist, floating_veb_list,
 880                                floating_veb_list_handler,
 881                                vf_floating_veb) < 0) {
 882                 rte_kvargs_free(kvlist);
 883                 return;
 884         }
 885         rte_kvargs_free(kvlist);
 886 }
 887
 888 static int
 889 i40e_check_floating_handler(__rte_unused const char *key,
 890                             const char *value,
 891                             __rte_unused void *opaque)
 892 {
 893         if (strcmp(value, "1"))
 894                 return -1;
 895
 896         return 0;
 897 }
 898
 899 static int
 900 is_floating_veb_supported(struct rte_devargs *devargs)
 901 {
 902         struct rte_kvargs *kvlist;
 903         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 904
 905         if (devargs == NULL)
 906                 return 0;
 907
 908         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 909         if (kvlist == NULL)
 910                 return 0;
 911
 912         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 913                 rte_kvargs_free(kvlist);
 914                 return 0;
 915         }
 916         /* Floating VEB is enabled when there's key-value:
 917          * enable_floating_veb=1
 918          */
 919         if (rte_kvargs_process(kvlist, floating_veb_key,
 920                                i40e_check_floating_handler, NULL) < 0) {
 921                 rte_kvargs_free(kvlist);
 922                 return 0;
 923         }
 924         rte_kvargs_free(kvlist);
 925
 926         return 1;
 927 }
 928
 929 static void
 930 config_floating_veb(struct rte_eth_dev *dev)
 931 {
 932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 933         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 935
 936         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 937
 938         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 939                 pf->floating_veb =
 940                         is_floating_veb_supported(pci_dev->device.devargs);
 941                 config_vf_floating_veb(pci_dev->device.devargs,
 942                                        pf->floating_veb,
 943                                        pf->floating_veb_list);
 944         } else {
 945                 pf->floating_veb = false;
 946         }
 947 }
 948
 949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 951
 952 static int
 953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 954 {
 955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 956         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 957         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 958         int ret;
 959
 960         struct rte_hash_parameters ethertype_hash_params = {
 961                 .name = ethertype_hash_name,
 962                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 963                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 964                 .hash_func = rte_hash_crc,
 965                 .hash_func_init_val = 0,
 966                 .socket_id = rte_socket_id(),
 967         };
 968
 969         /* Initialize ethertype filter rule list and hash */
 970         TAILQ_INIT(&ethertype_rule->ethertype_list);
 971         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 972                  "ethertype_%s", dev->device->name);
 973         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 974         if (!ethertype_rule->hash_table) {
 975                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 976                 return -EINVAL;
 977         }
 978         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 979                                        sizeof(struct i40e_ethertype_filter *) *
 980                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 981                                        0);
 982         if (!ethertype_rule->hash_map) {
 983                 PMD_INIT_LOG(ERR,
 984                              "Failed to allocate memory for ethertype hash map!");
 985                 ret = -ENOMEM;
 986                 goto err_ethertype_hash_map_alloc;
 987         }
 988
 989         return 0;
 990
 991 err_ethertype_hash_map_alloc:
 992         rte_hash_free(ethertype_rule->hash_table);
 993
 994         return ret;
 995 }
 996
 997 static int
 998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1003         int ret;
1004
1005         struct rte_hash_parameters tunnel_hash_params = {
1006                 .name = tunnel_hash_name,
1007                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009                 .hash_func = rte_hash_crc,
1010                 .hash_func_init_val = 0,
1011                 .socket_id = rte_socket_id(),
1012         };
1013
1014         /* Initialize tunnel filter rule list and hash */
1015         TAILQ_INIT(&tunnel_rule->tunnel_list);
1016         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017                  "tunnel_%s", dev->device->name);
1018         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019         if (!tunnel_rule->hash_table) {
1020                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1021                 return -EINVAL;
1022         }
1023         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024                                     sizeof(struct i40e_tunnel_filter *) *
1025                                     I40E_MAX_TUNNEL_FILTER_NUM,
1026                                     0);
1027         if (!tunnel_rule->hash_map) {
1028                 PMD_INIT_LOG(ERR,
1029                              "Failed to allocate memory for tunnel hash map!");
1030                 ret = -ENOMEM;
1031                 goto err_tunnel_hash_map_alloc;
1032         }
1033
1034         return 0;
1035
1036 err_tunnel_hash_map_alloc:
1037         rte_hash_free(tunnel_rule->hash_table);
1038
1039         return ret;
1040 }
1041
1042 static int
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1044 {
1045         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046         struct i40e_fdir_info *fdir_info = &pf->fdir;
1047         char fdir_hash_name[RTE_HASH_NAMESIZE];
1048         int ret;
1049
1050         struct rte_hash_parameters fdir_hash_params = {
1051                 .name = fdir_hash_name,
1052                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053                 .key_len = sizeof(struct i40e_fdir_input),
1054                 .hash_func = rte_hash_crc,
1055                 .hash_func_init_val = 0,
1056                 .socket_id = rte_socket_id(),
1057         };
1058
1059         /* Initialize flow director filter rule list and hash */
1060         TAILQ_INIT(&fdir_info->fdir_list);
1061         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062                  "fdir_%s", dev->device->name);
1063         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064         if (!fdir_info->hash_table) {
1065                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1066                 return -EINVAL;
1067         }
1068         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069                                           sizeof(struct i40e_fdir_filter *) *
1070                                           I40E_MAX_FDIR_FILTER_NUM,
1071                                           0);
1072         if (!fdir_info->hash_map) {
1073                 PMD_INIT_LOG(ERR,
1074                              "Failed to allocate memory for fdir hash map!");
1075                 ret = -ENOMEM;
1076                 goto err_fdir_hash_map_alloc;
1077         }
1078         return 0;
1079
1080 err_fdir_hash_map_alloc:
1081         rte_hash_free(fdir_info->hash_table);
1082
1083         return ret;
1084 }
1085
1086 static void
1087 i40e_init_customized_info(struct i40e_pf *pf)
1088 {
1089         int i;
1090
1091         /* Initialize customized pctype */
1092         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093                 pf->customized_pctype[i].index = i;
1094                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095                 pf->customized_pctype[i].valid = false;
1096         }
1097
1098         pf->gtp_support = false;
1099 }
1100
1101 void
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1103 {
1104         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106         struct i40e_queue_regions *info = &pf->queue_region;
1107         uint16_t i;
1108
1109         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1111
1112         memset(info, 0, sizeof(struct i40e_queue_regions));
1113 }
1114
1115 static int
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117                                const char *value,
1118                                void *opaque)
1119 {
1120         struct i40e_pf *pf;
1121         unsigned long support_multi_driver;
1122         char *end;
1123
1124         pf = (struct i40e_pf *)opaque;
1125
1126         errno = 0;
1127         support_multi_driver = strtoul(value, &end, 10);
1128         if (errno != 0 || end == value || *end != 0) {
1129                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1130                 return -(EINVAL);
1131         }
1132
1133         if (support_multi_driver == 1 || support_multi_driver == 0)
1134                 pf->support_multi_driver = (bool)support_multi_driver;
1135         else
1136                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137                             "enable global configuration by default."
1138                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1139         return 0;
1140 }
1141
1142 static int
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1144 {
1145         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146         struct rte_kvargs *kvlist;
1147         int kvargs_count;
1148
1149         /* Enable global configuration by default */
1150         pf->support_multi_driver = false;
1151
1152         if (!dev->device->devargs)
1153                 return 0;
1154
1155         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1156         if (!kvlist)
1157                 return -EINVAL;
1158
1159         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160         if (!kvargs_count) {
1161                 rte_kvargs_free(kvlist);
1162                 return 0;
1163         }
1164
1165         if (kvargs_count > 1)
1166                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167                             "the first invalid or last valid one is used !",
1168                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1169
1170         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171                                i40e_parse_multi_drv_handler, pf) < 0) {
1172                 rte_kvargs_free(kvlist);
1173                 return -EINVAL;
1174         }
1175
1176         rte_kvargs_free(kvlist);
1177         return 0;
1178 }
1179
1180 static int
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182                                     uint32_t reg_addr, uint64_t reg_val,
1183                                     struct i40e_asq_cmd_details *cmd_details)
1184 {
1185         uint64_t ori_reg_val;
1186         struct rte_eth_dev *dev;
1187         int ret;
1188
1189         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_DRV_LOG(ERR,
1192                             "Fail to debug read from 0x%08x",
1193                             reg_addr);
1194                 return -EIO;
1195         }
1196         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1197
1198         if (ori_reg_val != reg_val)
1199                 PMD_DRV_LOG(WARNING,
1200                             "i40e device %s changed global register [0x%08x]."
1201                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1203
1204         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1205 }
1206
1207 static int
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1209                                 const char *value,
1210                                 void *opaque)
1211 {
1212         struct i40e_adapter *ad;
1213         int use_latest_vec;
1214
1215         ad = (struct i40e_adapter *)opaque;
1216
1217         use_latest_vec = atoi(value);
1218
1219         if (use_latest_vec != 0 && use_latest_vec != 1)
1220                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221
1222         ad->use_latest_vec = (uint8_t)use_latest_vec;
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_adapter *ad =
1231                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232         struct rte_kvargs *kvlist;
1233         int kvargs_count;
1234
1235         ad->use_latest_vec = false;
1236
1237         if (!dev->device->devargs)
1238                 return 0;
1239
1240         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1241         if (!kvlist)
1242                 return -EINVAL;
1243
1244         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245         if (!kvargs_count) {
1246                 rte_kvargs_free(kvlist);
1247                 return 0;
1248         }
1249
1250         if (kvargs_count > 1)
1251                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252                             "the first invalid or last valid one is used !",
1253                             ETH_I40E_USE_LATEST_VEC);
1254
1255         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256                                 i40e_parse_latest_vec_handler, ad) < 0) {
1257                 rte_kvargs_free(kvlist);
1258                 return -EINVAL;
1259         }
1260
1261         rte_kvargs_free(kvlist);
1262         return 0;
1263 }
1264
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1266
1267 static int
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct rte_intr_handle *intr_handle;
1272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct i40e_vsi *vsi;
1275         int ret;
1276         uint32_t len, val;
1277         uint8_t aq_fail = 0;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         dev->dev_ops = &i40e_eth_dev_ops;
1282         dev->rx_pkt_burst = i40e_recv_pkts;
1283         dev->tx_pkt_burst = i40e_xmit_pkts;
1284         dev->tx_pkt_prepare = i40e_prep_pkts;
1285
1286         /* for secondary processes, we don't initialise any further as primary
1287          * has already done this work. Only check we don't need a different
1288          * RX function */
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290                 i40e_set_rx_function(dev);
1291                 i40e_set_tx_function(dev);
1292                 return 0;
1293         }
1294         i40e_set_default_ptype_table(dev);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296         intr_handle = &pci_dev->intr_handle;
1297
1298         rte_eth_copy_pci_info(dev, pci_dev);
1299
1300         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301         pf->adapter->eth_dev = dev;
1302         pf->dev_data = dev->data;
1303
1304         hw->back = I40E_PF_TO_ADAPTER(pf);
1305         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1306         if (!hw->hw_addr) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Hardware is not available, as address is NULL");
1309                 return -ENODEV;
1310         }
1311
1312         hw->vendor_id = pci_dev->id.vendor_id;
1313         hw->device_id = pci_dev->id.device_id;
1314         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316         hw->bus.device = pci_dev->addr.devid;
1317         hw->bus.func = pci_dev->addr.function;
1318         hw->adapter_stopped = 0;
1319
1320         /*
1321          * Switch Tag value should not be identical to either the First Tag
1322          * or Second Tag values. So set something other than common Ethertype
1323          * for internal switching.
1324          */
1325         hw->switch_tag = 0xffff;
1326
1327         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1328         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1329                 PMD_INIT_LOG(ERR, "\nERROR: "
1330                         "Firmware recovery mode detected. Limiting functionality.\n"
1331                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1332                         "User Guide for details on firmware recovery mode.");
1333                 return -EIO;
1334         }
1335
1336         /* Check if need to support multi-driver */
1337         i40e_support_multi_driver(dev);
1338         /* Check if users want the latest supported vec path */
1339         i40e_use_latest_vec(dev);
1340
1341         /* Make sure all is clean before doing PF reset */
1342         i40e_clear_hw(hw);
1343
1344         /* Reset here to make sure all is clean for each PF */
1345         ret = i40e_pf_reset(hw);
1346         if (ret) {
1347                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1348                 return ret;
1349         }
1350
1351         /* Initialize the shared code (base driver) */
1352         ret = i40e_init_shared_code(hw);
1353         if (ret) {
1354                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1355                 return ret;
1356         }
1357
1358         /* Initialize the parameters for adminq */
1359         i40e_init_adminq_parameter(hw);
1360         ret = i40e_init_adminq(hw);
1361         if (ret != I40E_SUCCESS) {
1362                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1363                 return -EIO;
1364         }
1365         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1366                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1367                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1368                      ((hw->nvm.version >> 12) & 0xf),
1369                      ((hw->nvm.version >> 4) & 0xff),
1370                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1371
1372         /* Initialize the hardware */
1373         i40e_hw_init(dev);
1374
1375         i40e_config_automask(pf);
1376
1377         i40e_set_default_pctype_table(dev);
1378
1379         /*
1380          * To work around the NVM issue, initialize registers
1381          * for packet type of QinQ by software.
1382          * It should be removed once issues are fixed in NVM.
1383          */
1384         if (!pf->support_multi_driver)
1385                 i40e_GLQF_reg_init(hw);
1386
1387         /* Initialize the input set for filters (hash and fd) to default value */
1388         i40e_filter_input_set_init(pf);
1389
1390         /* initialise the L3_MAP register */
1391         if (!pf->support_multi_driver) {
1392                 ret = i40e_aq_debug_write_global_register(hw,
1393                                                    I40E_GLQF_L3_MAP(40),
1394                                                    0x00000028,  NULL);
1395                 if (ret)
1396                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1397                                      ret);
1398                 PMD_INIT_LOG(DEBUG,
1399                              "Global register 0x%08x is changed with 0x28",
1400                              I40E_GLQF_L3_MAP(40));
1401         }
1402
1403         /* Need the special FW version to support floating VEB */
1404         config_floating_veb(dev);
1405         /* Clear PXE mode */
1406         i40e_clear_pxe_mode(hw);
1407         i40e_dev_sync_phy_type(hw);
1408
1409         /*
1410          * On X710, performance number is far from the expectation on recent
1411          * firmware versions. The fix for this issue may not be integrated in
1412          * the following firmware version. So the workaround in software driver
1413          * is needed. It needs to modify the initial values of 3 internal only
1414          * registers. Note that the workaround can be removed when it is fixed
1415          * in firmware in the future.
1416          */
1417         i40e_configure_registers(hw);
1418
1419         /* Get hw capabilities */
1420         ret = i40e_get_cap(hw);
1421         if (ret != I40E_SUCCESS) {
1422                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1423                 goto err_get_capabilities;
1424         }
1425
1426         /* Initialize parameters for PF */
1427         ret = i40e_pf_parameter_init(dev);
1428         if (ret != 0) {
1429                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1430                 goto err_parameter_init;
1431         }
1432
1433         /* Initialize the queue management */
1434         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1435         if (ret < 0) {
1436                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1437                 goto err_qp_pool_init;
1438         }
1439         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1440                                 hw->func_caps.num_msix_vectors - 1);
1441         if (ret < 0) {
1442                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1443                 goto err_msix_pool_init;
1444         }
1445
1446         /* Initialize lan hmc */
1447         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1448                                 hw->func_caps.num_rx_qp, 0, 0);
1449         if (ret != I40E_SUCCESS) {
1450                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1451                 goto err_init_lan_hmc;
1452         }
1453
1454         /* Configure lan hmc */
1455         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1456         if (ret != I40E_SUCCESS) {
1457                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1458                 goto err_configure_lan_hmc;
1459         }
1460
1461         /* Get and check the mac address */
1462         i40e_get_mac_addr(hw, hw->mac.addr);
1463         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1464                 PMD_INIT_LOG(ERR, "mac address is not valid");
1465                 ret = -EIO;
1466                 goto err_get_mac_addr;
1467         }
1468         /* Copy the permanent MAC address */
1469         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1470                         (struct ether_addr *) hw->mac.perm_addr);
1471
1472         /* Disable flow control */
1473         hw->fc.requested_mode = I40E_FC_NONE;
1474         i40e_set_fc(hw, &aq_fail, TRUE);
1475
1476         /* Set the global registers with default ether type value */
1477         if (!pf->support_multi_driver) {
1478                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1479                                          ETHER_TYPE_VLAN);
1480                 if (ret != I40E_SUCCESS) {
1481                         PMD_INIT_LOG(ERR,
1482                                      "Failed to set the default outer "
1483                                      "VLAN ether type");
1484                         goto err_setup_pf_switch;
1485                 }
1486         }
1487
1488         /* PF setup, which includes VSI setup */
1489         ret = i40e_pf_setup(pf);
1490         if (ret) {
1491                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1492                 goto err_setup_pf_switch;
1493         }
1494
1495         /* reset all stats of the device, including pf and main vsi */
1496         i40e_dev_stats_reset(dev);
1497
1498         vsi = pf->main_vsi;
1499
1500         /* Disable double vlan by default */
1501         i40e_vsi_config_double_vlan(vsi, FALSE);
1502
1503         /* Disable S-TAG identification when floating_veb is disabled */
1504         if (!pf->floating_veb) {
1505                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1506                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1507                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1508                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1509                 }
1510         }
1511
1512         if (!vsi->max_macaddrs)
1513                 len = ETHER_ADDR_LEN;
1514         else
1515                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1516
1517         /* Should be after VSI initialized */
1518         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1519         if (!dev->data->mac_addrs) {
1520                 PMD_INIT_LOG(ERR,
1521                         "Failed to allocated memory for storing mac address");
1522                 goto err_mac_alloc;
1523         }
1524         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1525                                         &dev->data->mac_addrs[0]);
1526
1527         /* Init dcb to sw mode by default */
1528         ret = i40e_dcb_init_configure(dev, TRUE);
1529         if (ret != I40E_SUCCESS) {
1530                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1531                 pf->flags &= ~I40E_FLAG_DCB;
1532         }
1533         /* Update HW struct after DCB configuration */
1534         i40e_get_cap(hw);
1535
1536         /* initialize pf host driver to setup SRIOV resource if applicable */
1537         i40e_pf_host_init(dev);
1538
1539         /* register callback func to eal lib */
1540         rte_intr_callback_register(intr_handle,
1541                                    i40e_dev_interrupt_handler, dev);
1542
1543         /* configure and enable device interrupt */
1544         i40e_pf_config_irq0(hw, TRUE);
1545         i40e_pf_enable_irq0(hw);
1546
1547         /* enable uio intr after callback register */
1548         rte_intr_enable(intr_handle);
1549
1550         /* By default disable flexible payload in global configuration */
1551         if (!pf->support_multi_driver)
1552                 i40e_flex_payload_reg_set_default(hw);
1553
1554         /*
1555          * Add an ethertype filter to drop all flow control frames transmitted
1556          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1557          * frames to wire.
1558          */
1559         i40e_add_tx_flow_control_drop_filter(pf);
1560
1561         /* Set the max frame size to 0x2600 by default,
1562          * in case other drivers changed the default value.
1563          */
1564         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1565
1566         /* initialize mirror rule list */
1567         TAILQ_INIT(&pf->mirror_list);
1568
1569         /* initialize Traffic Manager configuration */
1570         i40e_tm_conf_init(dev);
1571
1572         /* Initialize customized information */
1573         i40e_init_customized_info(pf);
1574
1575         ret = i40e_init_ethtype_filter_list(dev);
1576         if (ret < 0)
1577                 goto err_init_ethtype_filter_list;
1578         ret = i40e_init_tunnel_filter_list(dev);
1579         if (ret < 0)
1580                 goto err_init_tunnel_filter_list;
1581         ret = i40e_init_fdir_filter_list(dev);
1582         if (ret < 0)
1583                 goto err_init_fdir_filter_list;
1584
1585         /* initialize queue region configuration */
1586         i40e_init_queue_region_conf(dev);
1587
1588         /* initialize rss configuration from rte_flow */
1589         memset(&pf->rss_info, 0,
1590                 sizeof(struct i40e_rte_flow_rss_conf));
1591
1592         return 0;
1593
1594 err_init_fdir_filter_list:
1595         rte_free(pf->tunnel.hash_table);
1596         rte_free(pf->tunnel.hash_map);
1597 err_init_tunnel_filter_list:
1598         rte_free(pf->ethertype.hash_table);
1599         rte_free(pf->ethertype.hash_map);
1600 err_init_ethtype_filter_list:
1601         rte_free(dev->data->mac_addrs);
1602 err_mac_alloc:
1603         i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1605 err_get_mac_addr:
1606 err_configure_lan_hmc:
1607         (void)i40e_shutdown_lan_hmc(hw);
1608 err_init_lan_hmc:
1609         i40e_res_pool_destroy(&pf->msix_pool);
1610 err_msix_pool_init:
1611         i40e_res_pool_destroy(&pf->qp_pool);
1612 err_qp_pool_init:
1613 err_parameter_init:
1614 err_get_capabilities:
1615         (void)i40e_shutdown_adminq(hw);
1616
1617         return ret;
1618 }
1619
1620 static void
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1622 {
1623         struct i40e_ethertype_filter *p_ethertype;
1624         struct i40e_ethertype_rule *ethertype_rule;
1625
1626         ethertype_rule = &pf->ethertype;
1627         /* Remove all ethertype filter rules and hash */
1628         if (ethertype_rule->hash_map)
1629                 rte_free(ethertype_rule->hash_map);
1630         if (ethertype_rule->hash_table)
1631                 rte_hash_free(ethertype_rule->hash_table);
1632
1633         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1634                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1635                              p_ethertype, rules);
1636                 rte_free(p_ethertype);
1637         }
1638 }
1639
1640 static void
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1642 {
1643         struct i40e_tunnel_filter *p_tunnel;
1644         struct i40e_tunnel_rule *tunnel_rule;
1645
1646         tunnel_rule = &pf->tunnel;
1647         /* Remove all tunnel director rules and hash */
1648         if (tunnel_rule->hash_map)
1649                 rte_free(tunnel_rule->hash_map);
1650         if (tunnel_rule->hash_table)
1651                 rte_hash_free(tunnel_rule->hash_table);
1652
1653         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1655                 rte_free(p_tunnel);
1656         }
1657 }
1658
1659 static void
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1661 {
1662         struct i40e_fdir_filter *p_fdir;
1663         struct i40e_fdir_info *fdir_info;
1664
1665         fdir_info = &pf->fdir;
1666         /* Remove all flow director rules and hash */
1667         if (fdir_info->hash_map)
1668                 rte_free(fdir_info->hash_map);
1669         if (fdir_info->hash_table)
1670                 rte_hash_free(fdir_info->hash_table);
1671
1672         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1674                 rte_free(p_fdir);
1675         }
1676 }
1677
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1679 {
1680         /*
1681          * Disable by default flexible payload
1682          * for corresponding L2/L3/L4 layers.
1683          */
1684         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1687 }
1688
1689 static int
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1691 {
1692         struct i40e_pf *pf;
1693         struct rte_pci_device *pci_dev;
1694         struct rte_intr_handle *intr_handle;
1695         struct i40e_hw *hw;
1696         struct i40e_filter_control_settings settings;
1697         struct rte_flow *p_flow;
1698         int ret;
1699         uint8_t aq_fail = 0;
1700         int retries = 0;
1701
1702         PMD_INIT_FUNC_TRACE();
1703
1704         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1705                 return 0;
1706
1707         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710         intr_handle = &pci_dev->intr_handle;
1711
1712         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1713         if (ret)
1714                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1715
1716         if (hw->adapter_stopped == 0)
1717                 i40e_dev_close(dev);
1718
1719         dev->dev_ops = NULL;
1720         dev->rx_pkt_burst = NULL;
1721         dev->tx_pkt_burst = NULL;
1722
1723         /* Clear PXE mode */
1724         i40e_clear_pxe_mode(hw);
1725
1726         /* Unconfigure filter control */
1727         memset(&settings, 0, sizeof(settings));
1728         ret = i40e_set_filter_control(hw, &settings);
1729         if (ret)
1730                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1731                                         ret);
1732
1733         /* Disable flow control */
1734         hw->fc.requested_mode = I40E_FC_NONE;
1735         i40e_set_fc(hw, &aq_fail, TRUE);
1736
1737         /* uninitialize pf host driver */
1738         i40e_pf_host_uninit(dev);
1739
1740         /* disable uio intr before callback unregister */
1741         rte_intr_disable(intr_handle);
1742
1743         /* unregister callback func to eal lib */
1744         do {
1745                 ret = rte_intr_callback_unregister(intr_handle,
1746                                 i40e_dev_interrupt_handler, dev);
1747                 if (ret >= 0) {
1748                         break;
1749                 } else if (ret != -EAGAIN) {
1750                         PMD_INIT_LOG(ERR,
1751                                  "intr callback unregister failed: %d",
1752                                  ret);
1753                         return ret;
1754                 }
1755                 i40e_msec_delay(500);
1756         } while (retries++ < 5);
1757
1758         i40e_rm_ethtype_filter_list(pf);
1759         i40e_rm_tunnel_filter_list(pf);
1760         i40e_rm_fdir_filter_list(pf);
1761
1762         /* Remove all flows */
1763         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1765                 rte_free(p_flow);
1766         }
1767
1768         /* Remove all Traffic Manager configuration */
1769         i40e_tm_conf_uninit(dev);
1770
1771         return 0;
1772 }
1773
1774 static int
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1776 {
1777         struct i40e_adapter *ad =
1778                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1782         int i, ret;
1783
1784         ret = i40e_dev_sync_phy_type(hw);
1785         if (ret)
1786                 return ret;
1787
1788         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789          * bulk allocation or vector Rx preconditions we will reset it.
1790          */
1791         ad->rx_bulk_alloc_allowed = true;
1792         ad->rx_vec_allowed = true;
1793         ad->tx_simple_allowed = true;
1794         ad->tx_vec_allowed = true;
1795
1796         /* Only legacy filter API needs the following fdir config. So when the
1797          * legacy filter API is deprecated, the following codes should also be
1798          * removed.
1799          */
1800         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801                 ret = i40e_fdir_setup(pf);
1802                 if (ret != I40E_SUCCESS) {
1803                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1804                         return -ENOTSUP;
1805                 }
1806                 ret = i40e_fdir_configure(dev);
1807                 if (ret < 0) {
1808                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1809                         goto err;
1810                 }
1811         } else
1812                 i40e_fdir_teardown(pf);
1813
1814         ret = i40e_dev_init_vlan(dev);
1815         if (ret < 0)
1816                 goto err;
1817
1818         /* VMDQ setup.
1819          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820          *  RSS setting have different requirements.
1821          *  General PMD driver call sequence are NIC init, configure,
1822          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1824          *  applicable. So, VMDQ setting has to be done before
1825          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1826          *  For RSS setting, it will try to calculate actual configured RX queue
1827          *  number, which will be available after rx_queue_setup(). dev_start()
1828          *  function is good to place RSS setup.
1829          */
1830         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831                 ret = i40e_vmdq_setup(dev);
1832                 if (ret)
1833                         goto err;
1834         }
1835
1836         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837                 ret = i40e_dcb_setup(dev);
1838                 if (ret) {
1839                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1840                         goto err_dcb;
1841                 }
1842         }
1843
1844         TAILQ_INIT(&pf->flow_list);
1845
1846         return 0;
1847
1848 err_dcb:
1849         /* need to release vmdq resource if exists */
1850         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851                 i40e_vsi_release(pf->vmdq[i].vsi);
1852                 pf->vmdq[i].vsi = NULL;
1853         }
1854         rte_free(pf->vmdq);
1855         pf->vmdq = NULL;
1856 err:
1857         /* Need to release fdir resource if exists.
1858          * Only legacy filter API needs the following fdir config. So when the
1859          * legacy filter API is deprecated, the following code should also be
1860          * removed.
1861          */
1862         i40e_fdir_teardown(pf);
1863         return ret;
1864 }
1865
1866 void
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1868 {
1869         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873         uint16_t msix_vect = vsi->msix_intr;
1874         uint16_t i;
1875
1876         for (i = 0; i < vsi->nb_qps; i++) {
1877                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1879                 rte_wmb();
1880         }
1881
1882         if (vsi->type != I40E_VSI_SRIOV) {
1883                 if (!rte_intr_allow_others(intr_handle)) {
1884                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1886                         I40E_WRITE_REG(hw,
1887                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1888                                        0);
1889                 } else {
1890                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1892                         I40E_WRITE_REG(hw,
1893                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1894                                                        msix_vect - 1), 0);
1895                 }
1896         } else {
1897                 uint32_t reg;
1898                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899                         vsi->user_param + (msix_vect - 1);
1900
1901                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1903         }
1904         I40E_WRITE_FLUSH(hw);
1905 }
1906
1907 static void
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909                        int base_queue, int nb_queue,
1910                        uint16_t itr_idx)
1911 {
1912         int i;
1913         uint32_t val;
1914         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1916
1917         /* Bind all RX queues to allocated MSIX interrupt */
1918         for (i = 0; i < nb_queue; i++) {
1919                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921                         ((base_queue + i + 1) <<
1922                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1925
1926                 if (i == nb_queue - 1)
1927                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1929         }
1930
1931         /* Write first RX queue to Link list register as the head element */
1932         if (vsi->type != I40E_VSI_SRIOV) {
1933                 uint16_t interval =
1934                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1935
1936                 if (msix_vect == I40E_MISC_VEC_ID) {
1937                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1938                                        (base_queue <<
1939                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1940                                        (0x0 <<
1941                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1942                         I40E_WRITE_REG(hw,
1943                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1944                                        interval);
1945                 } else {
1946                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1947                                        (base_queue <<
1948                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1949                                        (0x0 <<
1950                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1951                         I40E_WRITE_REG(hw,
1952                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1953                                                        msix_vect - 1),
1954                                        interval);
1955                 }
1956         } else {
1957                 uint32_t reg;
1958
1959                 if (msix_vect == I40E_MISC_VEC_ID) {
1960                         I40E_WRITE_REG(hw,
1961                                        I40E_VPINT_LNKLST0(vsi->user_param),
1962                                        (base_queue <<
1963                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1964                                        (0x0 <<
1965                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1966                 } else {
1967                         /* num_msix_vectors_vf needs to minus irq0 */
1968                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969                                 vsi->user_param + (msix_vect - 1);
1970
1971                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1972                                        (base_queue <<
1973                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1974                                        (0x0 <<
1975                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1976                 }
1977         }
1978
1979         I40E_WRITE_FLUSH(hw);
1980 }
1981
1982 void
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1984 {
1985         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989         uint16_t msix_vect = vsi->msix_intr;
1990         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991         uint16_t queue_idx = 0;
1992         int record = 0;
1993         int i;
1994
1995         for (i = 0; i < vsi->nb_qps; i++) {
1996                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1998         }
1999
2000         /* VF bind interrupt */
2001         if (vsi->type == I40E_VSI_SRIOV) {
2002                 __vsi_queues_bind_intr(vsi, msix_vect,
2003                                        vsi->base_queue, vsi->nb_qps,
2004                                        itr_idx);
2005                 return;
2006         }
2007
2008         /* PF & VMDq bind interrupt */
2009         if (rte_intr_dp_is_en(intr_handle)) {
2010                 if (vsi->type == I40E_VSI_MAIN) {
2011                         queue_idx = 0;
2012                         record = 1;
2013                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014                         struct i40e_vsi *main_vsi =
2015                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2017                         record = 1;
2018                 }
2019         }
2020
2021         for (i = 0; i < vsi->nb_used_qps; i++) {
2022                 if (nb_msix <= 1) {
2023                         if (!rte_intr_allow_others(intr_handle))
2024                                 /* allow to share MISC_VEC_ID */
2025                                 msix_vect = I40E_MISC_VEC_ID;
2026
2027                         /* no enough msix_vect, map all to one */
2028                         __vsi_queues_bind_intr(vsi, msix_vect,
2029                                                vsi->base_queue + i,
2030                                                vsi->nb_used_qps - i,
2031                                                itr_idx);
2032                         for (; !!record && i < vsi->nb_used_qps; i++)
2033                                 intr_handle->intr_vec[queue_idx + i] =
2034                                         msix_vect;
2035                         break;
2036                 }
2037                 /* 1:1 queue/msix_vect mapping */
2038                 __vsi_queues_bind_intr(vsi, msix_vect,
2039                                        vsi->base_queue + i, 1,
2040                                        itr_idx);
2041                 if (!!record)
2042                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2043
2044                 msix_vect++;
2045                 nb_msix--;
2046         }
2047 }
2048
2049 static void
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2051 {
2052         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057         uint16_t msix_intr, i;
2058
2059         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060                 for (i = 0; i < vsi->nb_msix; i++) {
2061                         msix_intr = vsi->msix_intr + i;
2062                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2066                 }
2067         else
2068                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2072
2073         I40E_WRITE_FLUSH(hw);
2074 }
2075
2076 static void
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2078 {
2079         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084         uint16_t msix_intr, i;
2085
2086         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087                 for (i = 0; i < vsi->nb_msix; i++) {
2088                         msix_intr = vsi->msix_intr + i;
2089                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2091                 }
2092         else
2093                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2095
2096         I40E_WRITE_FLUSH(hw);
2097 }
2098
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2101 {
2102         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2103
2104         if (link_speeds & ETH_LINK_SPEED_40G)
2105                 link_speed |= I40E_LINK_SPEED_40GB;
2106         if (link_speeds & ETH_LINK_SPEED_25G)
2107                 link_speed |= I40E_LINK_SPEED_25GB;
2108         if (link_speeds & ETH_LINK_SPEED_20G)
2109                 link_speed |= I40E_LINK_SPEED_20GB;
2110         if (link_speeds & ETH_LINK_SPEED_10G)
2111                 link_speed |= I40E_LINK_SPEED_10GB;
2112         if (link_speeds & ETH_LINK_SPEED_1G)
2113                 link_speed |= I40E_LINK_SPEED_1GB;
2114         if (link_speeds & ETH_LINK_SPEED_100M)
2115                 link_speed |= I40E_LINK_SPEED_100MB;
2116
2117         return link_speed;
2118 }
2119
2120 static int
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2122                    uint8_t abilities,
2123                    uint8_t force_speed,
2124                    bool is_up)
2125 {
2126         enum i40e_status_code status;
2127         struct i40e_aq_get_phy_abilities_resp phy_ab;
2128         struct i40e_aq_set_phy_config phy_conf;
2129         enum i40e_aq_phy_type cnt;
2130         uint8_t avail_speed;
2131         uint32_t phy_type_mask = 0;
2132
2133         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_LOW_POWER;
2137         int ret = -ENOTSUP;
2138
2139         /* To get phy capabilities of available speeds. */
2140         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2141                                               NULL);
2142         if (status) {
2143                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2144                                 status);
2145                 return ret;
2146         }
2147         avail_speed = phy_ab.link_speed;
2148
2149         /* To get the current phy config. */
2150         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2151                                               NULL);
2152         if (status) {
2153                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2154                                 status);
2155                 return ret;
2156         }
2157
2158         /* If link needs to go up and it is in autoneg mode the speed is OK,
2159          * no need to set up again.
2160          */
2161         if (is_up && phy_ab.phy_type != 0 &&
2162                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2163                      phy_ab.link_speed != 0)
2164                 return I40E_SUCCESS;
2165
2166         memset(&phy_conf, 0, sizeof(phy_conf));
2167
2168         /* bits 0-2 use the values from get_phy_abilities_resp */
2169         abilities &= ~mask;
2170         abilities |= phy_ab.abilities & mask;
2171
2172         phy_conf.abilities = abilities;
2173
2174         /* If link needs to go up, but the force speed is not supported,
2175          * Warn users and config the default available speeds.
2176          */
2177         if (is_up && !(force_speed & avail_speed)) {
2178                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179                 phy_conf.link_speed = avail_speed;
2180         } else {
2181                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2182         }
2183
2184         /* PHY type mask needs to include each type except PHY type extension */
2185         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186                 phy_type_mask |= 1 << cnt;
2187
2188         /* use get_phy_abilities_resp value for the rest */
2189         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194         phy_conf.eee_capability = phy_ab.eee_capability;
2195         phy_conf.eeer = phy_ab.eeer_val;
2196         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2197
2198         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199                     phy_ab.abilities, phy_ab.link_speed);
2200         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2201                     phy_conf.abilities, phy_conf.link_speed);
2202
2203         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2204         if (status)
2205                 return ret;
2206
2207         return I40E_SUCCESS;
2208 }
2209
2210 static int
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2212 {
2213         uint8_t speed;
2214         uint8_t abilities = 0;
2215         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216         struct rte_eth_conf *conf = &dev->data->dev_conf;
2217
2218         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219                 conf->link_speeds = ETH_LINK_SPEED_40G |
2220                                     ETH_LINK_SPEED_25G |
2221                                     ETH_LINK_SPEED_20G |
2222                                     ETH_LINK_SPEED_10G |
2223                                     ETH_LINK_SPEED_1G |
2224                                     ETH_LINK_SPEED_100M;
2225         }
2226         speed = i40e_parse_link_speeds(conf->link_speeds);
2227         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228                      I40E_AQ_PHY_AN_ENABLED |
2229                      I40E_AQ_PHY_LINK_ENABLED;
2230
2231         return i40e_phy_conf_link(hw, abilities, speed, true);
2232 }
2233
2234 static int
2235 i40e_dev_start(struct rte_eth_dev *dev)
2236 {
2237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239         struct i40e_vsi *main_vsi = pf->main_vsi;
2240         int ret, i;
2241         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243         uint32_t intr_vector = 0;
2244         struct i40e_vsi *vsi;
2245
2246         hw->adapter_stopped = 0;
2247
2248         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2249                 PMD_INIT_LOG(ERR,
2250                 "Invalid link_speeds for port %u, autonegotiation disabled",
2251                               dev->data->port_id);
2252                 return -EINVAL;
2253         }
2254
2255         rte_intr_disable(intr_handle);
2256
2257         if ((rte_intr_cap_multiple(intr_handle) ||
2258              !RTE_ETH_DEV_SRIOV(dev).active) &&
2259             dev->data->dev_conf.intr_conf.rxq != 0) {
2260                 intr_vector = dev->data->nb_rx_queues;
2261                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2262                 if (ret)
2263                         return ret;
2264         }
2265
2266         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267                 intr_handle->intr_vec =
2268                         rte_zmalloc("intr_vec",
2269                                     dev->data->nb_rx_queues * sizeof(int),
2270                                     0);
2271                 if (!intr_handle->intr_vec) {
2272                         PMD_INIT_LOG(ERR,
2273                                 "Failed to allocate %d rx_queues intr_vec",
2274                                 dev->data->nb_rx_queues);
2275                         return -ENOMEM;
2276                 }
2277         }
2278
2279         /* Initialize VSI */
2280         ret = i40e_dev_rxtx_init(pf);
2281         if (ret != I40E_SUCCESS) {
2282                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2283                 goto err_up;
2284         }
2285
2286         /* Map queues with MSIX interrupt */
2287         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290         i40e_vsi_enable_queues_intr(main_vsi);
2291
2292         /* Map VMDQ VSI queues with MSIX interrupt */
2293         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296                                           I40E_ITR_INDEX_DEFAULT);
2297                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2298         }
2299
2300         /* enable FDIR MSIX interrupt */
2301         if (pf->fdir.fdir_vsi) {
2302                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303                                           I40E_ITR_INDEX_NONE);
2304                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2305         }
2306
2307         /* Enable all queues which have been configured */
2308         ret = i40e_dev_switch_queues(pf, TRUE);
2309         if (ret != I40E_SUCCESS) {
2310                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2311                 goto err_up;
2312         }
2313
2314         /* Enable receiving broadcast packets */
2315         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316         if (ret != I40E_SUCCESS)
2317                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2318
2319         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2321                                                 true, NULL);
2322                 if (ret != I40E_SUCCESS)
2323                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2324         }
2325
2326         /* Enable the VLAN promiscuous mode. */
2327         if (pf->vfs) {
2328                 for (i = 0; i < pf->vf_num; i++) {
2329                         vsi = pf->vfs[i].vsi;
2330                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2331                                                      true, NULL);
2332                 }
2333         }
2334
2335         /* Enable mac loopback mode */
2336         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339                 if (ret != I40E_SUCCESS) {
2340                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2341                         goto err_up;
2342                 }
2343         }
2344
2345         /* Apply link configure */
2346         ret = i40e_apply_link_speed(dev);
2347         if (I40E_SUCCESS != ret) {
2348                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2349                 goto err_up;
2350         }
2351
2352         if (!rte_intr_allow_others(intr_handle)) {
2353                 rte_intr_callback_unregister(intr_handle,
2354                                              i40e_dev_interrupt_handler,
2355                                              (void *)dev);
2356                 /* configure and enable device interrupt */
2357                 i40e_pf_config_irq0(hw, FALSE);
2358                 i40e_pf_enable_irq0(hw);
2359
2360                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2361                         PMD_INIT_LOG(INFO,
2362                                 "lsc won't enable because of no intr multiplex");
2363         } else {
2364                 ret = i40e_aq_set_phy_int_mask(hw,
2365                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2368                 if (ret != I40E_SUCCESS)
2369                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2370
2371                 /* Call get_link_info aq commond to enable/disable LSE */
2372                 i40e_dev_link_update(dev, 0);
2373         }
2374
2375         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377                                   i40e_dev_alarm_handler, dev);
2378         } else {
2379                 /* enable uio intr after callback register */
2380                 rte_intr_enable(intr_handle);
2381         }
2382
2383         i40e_filter_restore(pf);
2384
2385         if (pf->tm_conf.root && !pf->tm_conf.committed)
2386                 PMD_DRV_LOG(WARNING,
2387                             "please call hierarchy_commit() "
2388                             "before starting the port");
2389
2390         return I40E_SUCCESS;
2391
2392 err_up:
2393         i40e_dev_switch_queues(pf, FALSE);
2394         i40e_dev_clear_queues(dev);
2395
2396         return ret;
2397 }
2398
2399 static void
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2401 {
2402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_vsi *main_vsi = pf->main_vsi;
2405         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2407         int i;
2408
2409         if (hw->adapter_stopped == 1)
2410                 return;
2411
2412         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414                 rte_intr_enable(intr_handle);
2415         }
2416
2417         /* Disable all queues */
2418         i40e_dev_switch_queues(pf, FALSE);
2419
2420         /* un-map queues with interrupt registers */
2421         i40e_vsi_disable_queues_intr(main_vsi);
2422         i40e_vsi_queues_unbind_intr(main_vsi);
2423
2424         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2427         }
2428
2429         if (pf->fdir.fdir_vsi) {
2430                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2432         }
2433         /* Clear all queues and release memory */
2434         i40e_dev_clear_queues(dev);
2435
2436         /* Set link down */
2437         i40e_dev_set_link_down(dev);
2438
2439         if (!rte_intr_allow_others(intr_handle))
2440                 /* resume to the default handler */
2441                 rte_intr_callback_register(intr_handle,
2442                                            i40e_dev_interrupt_handler,
2443                                            (void *)dev);
2444
2445         /* Clean datapath event and queue/vec mapping */
2446         rte_intr_efd_disable(intr_handle);
2447         if (intr_handle->intr_vec) {
2448                 rte_free(intr_handle->intr_vec);
2449                 intr_handle->intr_vec = NULL;
2450         }
2451
2452         /* reset hierarchy commit */
2453         pf->tm_conf.committed = false;
2454
2455         hw->adapter_stopped = 1;
2456 }
2457
2458 static void
2459 i40e_dev_close(struct rte_eth_dev *dev)
2460 {
2461         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2462         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2463         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2464         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2465         struct i40e_mirror_rule *p_mirror;
2466         uint32_t reg;
2467         int i;
2468         int ret;
2469
2470         PMD_INIT_FUNC_TRACE();
2471
2472         i40e_dev_stop(dev);
2473
2474         /* Remove all mirror rules */
2475         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2476                 ret = i40e_aq_del_mirror_rule(hw,
2477                                               pf->main_vsi->veb->seid,
2478                                               p_mirror->rule_type,
2479                                               p_mirror->entries,
2480                                               p_mirror->num_entries,
2481                                               p_mirror->id);
2482                 if (ret < 0)
2483                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2484                                     "status = %d, aq_err = %d.", ret,
2485                                     hw->aq.asq_last_status);
2486
2487                 /* remove mirror software resource anyway */
2488                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2489                 rte_free(p_mirror);
2490                 pf->nb_mirror_rule--;
2491         }
2492
2493         i40e_dev_free_queues(dev);
2494
2495         /* Disable interrupt */
2496         i40e_pf_disable_irq0(hw);
2497         rte_intr_disable(intr_handle);
2498
2499         /*
2500          * Only legacy filter API needs the following fdir config. So when the
2501          * legacy filter API is deprecated, the following code should also be
2502          * removed.
2503          */
2504         i40e_fdir_teardown(pf);
2505
2506         /* shutdown and destroy the HMC */
2507         i40e_shutdown_lan_hmc(hw);
2508
2509         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2510                 i40e_vsi_release(pf->vmdq[i].vsi);
2511                 pf->vmdq[i].vsi = NULL;
2512         }
2513         rte_free(pf->vmdq);
2514         pf->vmdq = NULL;
2515
2516         /* release all the existing VSIs and VEBs */
2517         i40e_vsi_release(pf->main_vsi);
2518
2519         /* shutdown the adminq */
2520         i40e_aq_queue_shutdown(hw, true);
2521         i40e_shutdown_adminq(hw);
2522
2523         i40e_res_pool_destroy(&pf->qp_pool);
2524         i40e_res_pool_destroy(&pf->msix_pool);
2525
2526         /* Disable flexible payload in global configuration */
2527         if (!pf->support_multi_driver)
2528                 i40e_flex_payload_reg_set_default(hw);
2529
2530         /* force a PF reset to clean anything leftover */
2531         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2532         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2533                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2534         I40E_WRITE_FLUSH(hw);
2535 }
2536
2537 /*
2538  * Reset PF device only to re-initialize resources in PMD layer
2539  */
2540 static int
2541 i40e_dev_reset(struct rte_eth_dev *dev)
2542 {
2543         int ret;
2544
2545         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2546          * its VF to make them align with it. The detailed notification
2547          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2548          * To avoid unexpected behavior in VF, currently reset of PF with
2549          * SR-IOV activation is not supported. It might be supported later.
2550          */
2551         if (dev->data->sriov.active)
2552                 return -ENOTSUP;
2553
2554         ret = eth_i40e_dev_uninit(dev);
2555         if (ret)
2556                 return ret;
2557
2558         ret = eth_i40e_dev_init(dev, NULL);
2559
2560         return ret;
2561 }
2562
2563 static void
2564 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2565 {
2566         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         struct i40e_vsi *vsi = pf->main_vsi;
2569         int status;
2570
2571         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2572                                                      true, NULL, true);
2573         if (status != I40E_SUCCESS)
2574                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2575
2576         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2577                                                         TRUE, NULL);
2578         if (status != I40E_SUCCESS)
2579                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2580
2581 }
2582
2583 static void
2584 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2585 {
2586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2588         struct i40e_vsi *vsi = pf->main_vsi;
2589         int status;
2590
2591         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2592                                                      false, NULL, true);
2593         if (status != I40E_SUCCESS)
2594                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2595
2596         /* must remain in all_multicast mode */
2597         if (dev->data->all_multicast == 1)
2598                 return;
2599
2600         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2601                                                         false, NULL);
2602         if (status != I40E_SUCCESS)
2603                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2604 }
2605
2606 static void
2607 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2608 {
2609         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2611         struct i40e_vsi *vsi = pf->main_vsi;
2612         int ret;
2613
2614         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2615         if (ret != I40E_SUCCESS)
2616                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2617 }
2618
2619 static void
2620 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2621 {
2622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2623         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624         struct i40e_vsi *vsi = pf->main_vsi;
2625         int ret;
2626
2627         if (dev->data->promiscuous == 1)
2628                 return; /* must remain in all_multicast mode */
2629
2630         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2631                                 vsi->seid, FALSE, NULL);
2632         if (ret != I40E_SUCCESS)
2633                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2634 }
2635
2636 /*
2637  * Set device link up.
2638  */
2639 static int
2640 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2641 {
2642         /* re-apply link speed setting */
2643         return i40e_apply_link_speed(dev);
2644 }
2645
2646 /*
2647  * Set device link down.
2648  */
2649 static int
2650 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2651 {
2652         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2653         uint8_t abilities = 0;
2654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2655
2656         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2657         return i40e_phy_conf_link(hw, abilities, speed, false);
2658 }
2659
2660 static __rte_always_inline void
2661 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2662 {
2663 /* Link status registers and values*/
2664 #define I40E_PRTMAC_LINKSTA             0x001E2420
2665 #define I40E_REG_LINK_UP                0x40000080
2666 #define I40E_PRTMAC_MACC                0x001E24E0
2667 #define I40E_REG_MACC_25GB              0x00020000
2668 #define I40E_REG_SPEED_MASK             0x38000000
2669 #define I40E_REG_SPEED_100MB            0x00000000
2670 #define I40E_REG_SPEED_1GB              0x08000000
2671 #define I40E_REG_SPEED_10GB             0x10000000
2672 #define I40E_REG_SPEED_20GB             0x20000000
2673 #define I40E_REG_SPEED_25_40GB          0x18000000
2674         uint32_t link_speed;
2675         uint32_t reg_val;
2676
2677         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2678         link_speed = reg_val & I40E_REG_SPEED_MASK;
2679         reg_val &= I40E_REG_LINK_UP;
2680         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2681
2682         if (unlikely(link->link_status == 0))
2683                 return;
2684
2685         /* Parse the link status */
2686         switch (link_speed) {
2687         case I40E_REG_SPEED_100MB:
2688                 link->link_speed = ETH_SPEED_NUM_100M;
2689                 break;
2690         case I40E_REG_SPEED_1GB:
2691                 link->link_speed = ETH_SPEED_NUM_1G;
2692                 break;
2693         case I40E_REG_SPEED_10GB:
2694                 link->link_speed = ETH_SPEED_NUM_10G;
2695                 break;
2696         case I40E_REG_SPEED_20GB:
2697                 link->link_speed = ETH_SPEED_NUM_20G;
2698                 break;
2699         case I40E_REG_SPEED_25_40GB:
2700                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2701
2702                 if (reg_val & I40E_REG_MACC_25GB)
2703                         link->link_speed = ETH_SPEED_NUM_25G;
2704                 else
2705                         link->link_speed = ETH_SPEED_NUM_40G;
2706
2707                 break;
2708         default:
2709                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2710                 break;
2711         }
2712 }
2713
2714 static __rte_always_inline void
2715 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2716         bool enable_lse, int wait_to_complete)
2717 {
2718 #define CHECK_INTERVAL             100  /* 100ms */
2719 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2720         uint32_t rep_cnt = MAX_REPEAT_TIME;
2721         struct i40e_link_status link_status;
2722         int status;
2723
2724         memset(&link_status, 0, sizeof(link_status));
2725
2726         do {
2727                 memset(&link_status, 0, sizeof(link_status));
2728
2729                 /* Get link status information from hardware */
2730                 status = i40e_aq_get_link_info(hw, enable_lse,
2731                                                 &link_status, NULL);
2732                 if (unlikely(status != I40E_SUCCESS)) {
2733                         link->link_speed = ETH_SPEED_NUM_100M;
2734                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2735                         PMD_DRV_LOG(ERR, "Failed to get link info");
2736                         return;
2737                 }
2738
2739                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2740                 if (!wait_to_complete || link->link_status)
2741                         break;
2742
2743                 rte_delay_ms(CHECK_INTERVAL);
2744         } while (--rep_cnt);
2745
2746         /* Parse the link status */
2747         switch (link_status.link_speed) {
2748         case I40E_LINK_SPEED_100MB:
2749                 link->link_speed = ETH_SPEED_NUM_100M;
2750                 break;
2751         case I40E_LINK_SPEED_1GB:
2752                 link->link_speed = ETH_SPEED_NUM_1G;
2753                 break;
2754         case I40E_LINK_SPEED_10GB:
2755                 link->link_speed = ETH_SPEED_NUM_10G;
2756                 break;
2757         case I40E_LINK_SPEED_20GB:
2758                 link->link_speed = ETH_SPEED_NUM_20G;
2759                 break;
2760         case I40E_LINK_SPEED_25GB:
2761                 link->link_speed = ETH_SPEED_NUM_25G;
2762                 break;
2763         case I40E_LINK_SPEED_40GB:
2764                 link->link_speed = ETH_SPEED_NUM_40G;
2765                 break;
2766         default:
2767                 link->link_speed = ETH_SPEED_NUM_100M;
2768                 break;
2769         }
2770 }
2771
2772 int
2773 i40e_dev_link_update(struct rte_eth_dev *dev,
2774                      int wait_to_complete)
2775 {
2776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777         struct rte_eth_link link;
2778         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2779         int ret;
2780
2781         memset(&link, 0, sizeof(link));
2782
2783         /* i40e uses full duplex only */
2784         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2785         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2786                         ETH_LINK_SPEED_FIXED);
2787
2788         if (!wait_to_complete && !enable_lse)
2789                 update_link_reg(hw, &link);
2790         else
2791                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2792
2793         ret = rte_eth_linkstatus_set(dev, &link);
2794         i40e_notify_all_vfs_link_status(dev);
2795
2796         return ret;
2797 }
2798
2799 /* Get all the statistics of a VSI */
2800 void
2801 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2802 {
2803         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2804         struct i40e_eth_stats *nes = &vsi->eth_stats;
2805         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2806         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2807
2808         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2809                             vsi->offset_loaded, &oes->rx_bytes,
2810                             &nes->rx_bytes);
2811         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2812                             vsi->offset_loaded, &oes->rx_unicast,
2813                             &nes->rx_unicast);
2814         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2815                             vsi->offset_loaded, &oes->rx_multicast,
2816                             &nes->rx_multicast);
2817         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2818                             vsi->offset_loaded, &oes->rx_broadcast,
2819                             &nes->rx_broadcast);
2820         /* exclude CRC bytes */
2821         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2822                 nes->rx_broadcast) * ETHER_CRC_LEN;
2823
2824         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2825                             &oes->rx_discards, &nes->rx_discards);
2826         /* GLV_REPC not supported */
2827         /* GLV_RMPC not supported */
2828         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2829                             &oes->rx_unknown_protocol,
2830                             &nes->rx_unknown_protocol);
2831         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2832                             vsi->offset_loaded, &oes->tx_bytes,
2833                             &nes->tx_bytes);
2834         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2835                             vsi->offset_loaded, &oes->tx_unicast,
2836                             &nes->tx_unicast);
2837         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2838                             vsi->offset_loaded, &oes->tx_multicast,
2839                             &nes->tx_multicast);
2840         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2841                             vsi->offset_loaded,  &oes->tx_broadcast,
2842                             &nes->tx_broadcast);
2843         /* GLV_TDPC not supported */
2844         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2845                             &oes->tx_errors, &nes->tx_errors);
2846         vsi->offset_loaded = true;
2847
2848         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2849                     vsi->vsi_id);
2850         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2851         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2852         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2853         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2854         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2855         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2856                     nes->rx_unknown_protocol);
2857         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2858         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2859         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2860         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2861         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2862         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2863         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2864                     vsi->vsi_id);
2865 }
2866
2867 static void
2868 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2869 {
2870         unsigned int i;
2871         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2872         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2873
2874         /* Get rx/tx bytes of internal transfer packets */
2875         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2876                         I40E_GLV_GORCL(hw->port),
2877                         pf->offset_loaded,
2878                         &pf->internal_stats_offset.rx_bytes,
2879                         &pf->internal_stats.rx_bytes);
2880
2881         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2882                         I40E_GLV_GOTCL(hw->port),
2883                         pf->offset_loaded,
2884                         &pf->internal_stats_offset.tx_bytes,
2885                         &pf->internal_stats.tx_bytes);
2886         /* Get total internal rx packet count */
2887         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2888                             I40E_GLV_UPRCL(hw->port),
2889                             pf->offset_loaded,
2890                             &pf->internal_stats_offset.rx_unicast,
2891                             &pf->internal_stats.rx_unicast);
2892         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2893                             I40E_GLV_MPRCL(hw->port),
2894                             pf->offset_loaded,
2895                             &pf->internal_stats_offset.rx_multicast,
2896                             &pf->internal_stats.rx_multicast);
2897         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2898                             I40E_GLV_BPRCL(hw->port),
2899                             pf->offset_loaded,
2900                             &pf->internal_stats_offset.rx_broadcast,
2901                             &pf->internal_stats.rx_broadcast);
2902         /* Get total internal tx packet count */
2903         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2904                             I40E_GLV_UPTCL(hw->port),
2905                             pf->offset_loaded,
2906                             &pf->internal_stats_offset.tx_unicast,
2907                             &pf->internal_stats.tx_unicast);
2908         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2909                             I40E_GLV_MPTCL(hw->port),
2910                             pf->offset_loaded,
2911                             &pf->internal_stats_offset.tx_multicast,
2912                             &pf->internal_stats.tx_multicast);
2913         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2914                             I40E_GLV_BPTCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.tx_broadcast,
2917                             &pf->internal_stats.tx_broadcast);
2918
2919         /* exclude CRC size */
2920         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2921                 pf->internal_stats.rx_multicast +
2922                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2923
2924         /* Get statistics of struct i40e_eth_stats */
2925         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2926                             I40E_GLPRT_GORCL(hw->port),
2927                             pf->offset_loaded, &os->eth.rx_bytes,
2928                             &ns->eth.rx_bytes);
2929         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2930                             I40E_GLPRT_UPRCL(hw->port),
2931                             pf->offset_loaded, &os->eth.rx_unicast,
2932                             &ns->eth.rx_unicast);
2933         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2934                             I40E_GLPRT_MPRCL(hw->port),
2935                             pf->offset_loaded, &os->eth.rx_multicast,
2936                             &ns->eth.rx_multicast);
2937         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2938                             I40E_GLPRT_BPRCL(hw->port),
2939                             pf->offset_loaded, &os->eth.rx_broadcast,
2940                             &ns->eth.rx_broadcast);
2941         /* Workaround: CRC size should not be included in byte statistics,
2942          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2943          */
2944         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2945                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2946
2947         /* exclude internal rx bytes
2948          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2949          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2950          * value.
2951          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2952          */
2953         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2954                 ns->eth.rx_bytes = 0;
2955         else
2956                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2957
2958         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2959                 ns->eth.rx_unicast = 0;
2960         else
2961                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2962
2963         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2964                 ns->eth.rx_multicast = 0;
2965         else
2966                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2967
2968         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2969                 ns->eth.rx_broadcast = 0;
2970         else
2971                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2972
2973         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2974                             pf->offset_loaded, &os->eth.rx_discards,
2975                             &ns->eth.rx_discards);
2976         /* GLPRT_REPC not supported */
2977         /* GLPRT_RMPC not supported */
2978         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2979                             pf->offset_loaded,
2980                             &os->eth.rx_unknown_protocol,
2981                             &ns->eth.rx_unknown_protocol);
2982         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2983                             I40E_GLPRT_GOTCL(hw->port),
2984                             pf->offset_loaded, &os->eth.tx_bytes,
2985                             &ns->eth.tx_bytes);
2986         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2987                             I40E_GLPRT_UPTCL(hw->port),
2988                             pf->offset_loaded, &os->eth.tx_unicast,
2989                             &ns->eth.tx_unicast);
2990         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2991                             I40E_GLPRT_MPTCL(hw->port),
2992                             pf->offset_loaded, &os->eth.tx_multicast,
2993                             &ns->eth.tx_multicast);
2994         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2995                             I40E_GLPRT_BPTCL(hw->port),
2996                             pf->offset_loaded, &os->eth.tx_broadcast,
2997                             &ns->eth.tx_broadcast);
2998         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2999                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3000
3001         /* exclude internal tx bytes
3002          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3003          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3004          * value.
3005          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3006          */
3007         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3008                 ns->eth.tx_bytes = 0;
3009         else
3010                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3011
3012         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3013                 ns->eth.tx_unicast = 0;
3014         else
3015                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3016
3017         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3018                 ns->eth.tx_multicast = 0;
3019         else
3020                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3021
3022         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3023                 ns->eth.tx_broadcast = 0;
3024         else
3025                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3026
3027         /* GLPRT_TEPC not supported */
3028
3029         /* additional port specific stats */
3030         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3031                             pf->offset_loaded, &os->tx_dropped_link_down,
3032                             &ns->tx_dropped_link_down);
3033         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3034                             pf->offset_loaded, &os->crc_errors,
3035                             &ns->crc_errors);
3036         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3037                             pf->offset_loaded, &os->illegal_bytes,
3038                             &ns->illegal_bytes);
3039         /* GLPRT_ERRBC not supported */
3040         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3041                             pf->offset_loaded, &os->mac_local_faults,
3042                             &ns->mac_local_faults);
3043         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3044                             pf->offset_loaded, &os->mac_remote_faults,
3045                             &ns->mac_remote_faults);
3046         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3047                             pf->offset_loaded, &os->rx_length_errors,
3048                             &ns->rx_length_errors);
3049         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3050                             pf->offset_loaded, &os->link_xon_rx,
3051                             &ns->link_xon_rx);
3052         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3053                             pf->offset_loaded, &os->link_xoff_rx,
3054                             &ns->link_xoff_rx);
3055         for (i = 0; i < 8; i++) {
3056                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3057                                     pf->offset_loaded,
3058                                     &os->priority_xon_rx[i],
3059                                     &ns->priority_xon_rx[i]);
3060                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3061                                     pf->offset_loaded,
3062                                     &os->priority_xoff_rx[i],
3063                                     &ns->priority_xoff_rx[i]);
3064         }
3065         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3066                             pf->offset_loaded, &os->link_xon_tx,
3067                             &ns->link_xon_tx);
3068         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3069                             pf->offset_loaded, &os->link_xoff_tx,
3070                             &ns->link_xoff_tx);
3071         for (i = 0; i < 8; i++) {
3072                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3073                                     pf->offset_loaded,
3074                                     &os->priority_xon_tx[i],
3075                                     &ns->priority_xon_tx[i]);
3076                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3077                                     pf->offset_loaded,
3078                                     &os->priority_xoff_tx[i],
3079                                     &ns->priority_xoff_tx[i]);
3080                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3081                                     pf->offset_loaded,
3082                                     &os->priority_xon_2_xoff[i],
3083                                     &ns->priority_xon_2_xoff[i]);
3084         }
3085         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3086                             I40E_GLPRT_PRC64L(hw->port),
3087                             pf->offset_loaded, &os->rx_size_64,
3088                             &ns->rx_size_64);
3089         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3090                             I40E_GLPRT_PRC127L(hw->port),
3091                             pf->offset_loaded, &os->rx_size_127,
3092                             &ns->rx_size_127);
3093         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3094                             I40E_GLPRT_PRC255L(hw->port),
3095                             pf->offset_loaded, &os->rx_size_255,
3096                             &ns->rx_size_255);
3097         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3098                             I40E_GLPRT_PRC511L(hw->port),
3099                             pf->offset_loaded, &os->rx_size_511,
3100                             &ns->rx_size_511);
3101         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3102                             I40E_GLPRT_PRC1023L(hw->port),
3103                             pf->offset_loaded, &os->rx_size_1023,
3104                             &ns->rx_size_1023);
3105         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3106                             I40E_GLPRT_PRC1522L(hw->port),
3107                             pf->offset_loaded, &os->rx_size_1522,
3108                             &ns->rx_size_1522);
3109         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3110                             I40E_GLPRT_PRC9522L(hw->port),
3111                             pf->offset_loaded, &os->rx_size_big,
3112                             &ns->rx_size_big);
3113         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3114                             pf->offset_loaded, &os->rx_undersize,
3115                             &ns->rx_undersize);
3116         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3117                             pf->offset_loaded, &os->rx_fragments,
3118                             &ns->rx_fragments);
3119         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3120                             pf->offset_loaded, &os->rx_oversize,
3121                             &ns->rx_oversize);
3122         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3123                             pf->offset_loaded, &os->rx_jabber,
3124                             &ns->rx_jabber);
3125         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3126                             I40E_GLPRT_PTC64L(hw->port),
3127                             pf->offset_loaded, &os->tx_size_64,
3128                             &ns->tx_size_64);
3129         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3130                             I40E_GLPRT_PTC127L(hw->port),
3131                             pf->offset_loaded, &os->tx_size_127,
3132                             &ns->tx_size_127);
3133         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3134                             I40E_GLPRT_PTC255L(hw->port),
3135                             pf->offset_loaded, &os->tx_size_255,
3136                             &ns->tx_size_255);
3137         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3138                             I40E_GLPRT_PTC511L(hw->port),
3139                             pf->offset_loaded, &os->tx_size_511,
3140                             &ns->tx_size_511);
3141         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3142                             I40E_GLPRT_PTC1023L(hw->port),
3143                             pf->offset_loaded, &os->tx_size_1023,
3144                             &ns->tx_size_1023);
3145         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3146                             I40E_GLPRT_PTC1522L(hw->port),
3147                             pf->offset_loaded, &os->tx_size_1522,
3148                             &ns->tx_size_1522);
3149         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3150                             I40E_GLPRT_PTC9522L(hw->port),
3151                             pf->offset_loaded, &os->tx_size_big,
3152                             &ns->tx_size_big);
3153         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3154                            pf->offset_loaded,
3155                            &os->fd_sb_match, &ns->fd_sb_match);
3156         /* GLPRT_MSPDC not supported */
3157         /* GLPRT_XEC not supported */
3158
3159         pf->offset_loaded = true;
3160
3161         if (pf->main_vsi)
3162                 i40e_update_vsi_stats(pf->main_vsi);
3163 }
3164
3165 /* Get all statistics of a port */
3166 static int
3167 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3168 {
3169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3172         unsigned i;
3173
3174         /* call read registers - updates values, now write them to struct */
3175         i40e_read_stats_registers(pf, hw);
3176
3177         stats->ipackets = ns->eth.rx_unicast +
3178                         ns->eth.rx_multicast +
3179                         ns->eth.rx_broadcast -
3180                         ns->eth.rx_discards -
3181                         pf->main_vsi->eth_stats.rx_discards;
3182         stats->opackets = ns->eth.tx_unicast +
3183                         ns->eth.tx_multicast +
3184                         ns->eth.tx_broadcast;
3185         stats->ibytes   = ns->eth.rx_bytes;
3186         stats->obytes   = ns->eth.tx_bytes;
3187         stats->oerrors  = ns->eth.tx_errors +
3188                         pf->main_vsi->eth_stats.tx_errors;
3189
3190         /* Rx Errors */
3191         stats->imissed  = ns->eth.rx_discards +
3192                         pf->main_vsi->eth_stats.rx_discards;
3193         stats->ierrors  = ns->crc_errors +
3194                         ns->rx_length_errors + ns->rx_undersize +
3195                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3196
3197         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3198         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3199         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3200         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3201         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3202         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3203         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3204                     ns->eth.rx_unknown_protocol);
3205         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3206         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3207         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3208         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3209         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3210         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3211
3212         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3213                     ns->tx_dropped_link_down);
3214         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3215         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3216                     ns->illegal_bytes);
3217         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3218         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3219                     ns->mac_local_faults);
3220         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3221                     ns->mac_remote_faults);
3222         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3223                     ns->rx_length_errors);
3224         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3225         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3226         for (i = 0; i < 8; i++) {
3227                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3228                                 i, ns->priority_xon_rx[i]);
3229                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3230                                 i, ns->priority_xoff_rx[i]);
3231         }
3232         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3233         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3234         for (i = 0; i < 8; i++) {
3235                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3236                                 i, ns->priority_xon_tx[i]);
3237                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3238                                 i, ns->priority_xoff_tx[i]);
3239                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3240                                 i, ns->priority_xon_2_xoff[i]);
3241         }
3242         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3243         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3244         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3245         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3246         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3247         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3248         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3249         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3250         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3251         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3252         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3253         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3254         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3255         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3256         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3257         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3258         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3259         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3260         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3261                         ns->mac_short_packet_dropped);
3262         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3263                     ns->checksum_error);
3264         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3265         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3266         return 0;
3267 }
3268
3269 /* Reset the statistics */
3270 static void
3271 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3272 {
3273         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3274         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3275
3276         /* Mark PF and VSI stats to update the offset, aka "reset" */
3277         pf->offset_loaded = false;
3278         if (pf->main_vsi)
3279                 pf->main_vsi->offset_loaded = false;
3280
3281         /* read the stats, reading current register values into offset */
3282         i40e_read_stats_registers(pf, hw);
3283 }
3284
3285 static uint32_t
3286 i40e_xstats_calc_num(void)
3287 {
3288         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3289                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3290                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3291 }
3292
3293 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3294                                      struct rte_eth_xstat_name *xstats_names,
3295                                      __rte_unused unsigned limit)
3296 {
3297         unsigned count = 0;
3298         unsigned i, prio;
3299
3300         if (xstats_names == NULL)
3301                 return i40e_xstats_calc_num();
3302
3303         /* Note: limit checked in rte_eth_xstats_names() */
3304
3305         /* Get stats from i40e_eth_stats struct */
3306         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3307                 snprintf(xstats_names[count].name,
3308                          sizeof(xstats_names[count].name),
3309                          "%s", rte_i40e_stats_strings[i].name);
3310                 count++;
3311         }
3312
3313         /* Get individiual stats from i40e_hw_port struct */
3314         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3315                 snprintf(xstats_names[count].name,
3316                         sizeof(xstats_names[count].name),
3317                          "%s", rte_i40e_hw_port_strings[i].name);
3318                 count++;
3319         }
3320
3321         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3322                 for (prio = 0; prio < 8; prio++) {
3323                         snprintf(xstats_names[count].name,
3324                                  sizeof(xstats_names[count].name),
3325                                  "rx_priority%u_%s", prio,
3326                                  rte_i40e_rxq_prio_strings[i].name);
3327                         count++;
3328                 }
3329         }
3330
3331         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3332                 for (prio = 0; prio < 8; prio++) {
3333                         snprintf(xstats_names[count].name,
3334                                  sizeof(xstats_names[count].name),
3335                                  "tx_priority%u_%s", prio,
3336                                  rte_i40e_txq_prio_strings[i].name);
3337                         count++;
3338                 }
3339         }
3340         return count;
3341 }
3342
3343 static int
3344 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3345                     unsigned n)
3346 {
3347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3349         unsigned i, count, prio;
3350         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3351
3352         count = i40e_xstats_calc_num();
3353         if (n < count)
3354                 return count;
3355
3356         i40e_read_stats_registers(pf, hw);
3357
3358         if (xstats == NULL)
3359                 return 0;
3360
3361         count = 0;
3362
3363         /* Get stats from i40e_eth_stats struct */
3364         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3365                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3366                         rte_i40e_stats_strings[i].offset);
3367                 xstats[count].id = count;
3368                 count++;
3369         }
3370
3371         /* Get individiual stats from i40e_hw_port struct */
3372         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3373                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3374                         rte_i40e_hw_port_strings[i].offset);
3375                 xstats[count].id = count;
3376                 count++;
3377         }
3378
3379         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3380                 for (prio = 0; prio < 8; prio++) {
3381                         xstats[count].value =
3382                                 *(uint64_t *)(((char *)hw_stats) +
3383                                 rte_i40e_rxq_prio_strings[i].offset +
3384                                 (sizeof(uint64_t) * prio));
3385                         xstats[count].id = count;
3386                         count++;
3387                 }
3388         }
3389
3390         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3391                 for (prio = 0; prio < 8; prio++) {
3392                         xstats[count].value =
3393                                 *(uint64_t *)(((char *)hw_stats) +
3394                                 rte_i40e_txq_prio_strings[i].offset +
3395                                 (sizeof(uint64_t) * prio));
3396                         xstats[count].id = count;
3397                         count++;
3398                 }
3399         }
3400
3401         return count;
3402 }
3403
3404 static int
3405 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3406                                  __rte_unused uint16_t queue_id,
3407                                  __rte_unused uint8_t stat_idx,
3408                                  __rte_unused uint8_t is_rx)
3409 {
3410         PMD_INIT_FUNC_TRACE();
3411
3412         return -ENOSYS;
3413 }
3414
3415 static int
3416 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3417 {
3418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419         u32 full_ver;
3420         u8 ver, patch;
3421         u16 build;
3422         int ret;
3423
3424         full_ver = hw->nvm.oem_ver;
3425         ver = (u8)(full_ver >> 24);
3426         build = (u16)((full_ver >> 8) & 0xffff);
3427         patch = (u8)(full_ver & 0xff);
3428
3429         ret = snprintf(fw_version, fw_size,
3430                  "%d.%d%d 0x%08x %d.%d.%d",
3431                  ((hw->nvm.version >> 12) & 0xf),
3432                  ((hw->nvm.version >> 4) & 0xff),
3433                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3434                  ver, build, patch);
3435
3436         ret += 1; /* add the size of '\0' */
3437         if (fw_size < (u32)ret)
3438                 return ret;
3439         else
3440                 return 0;
3441 }
3442
3443 static void
3444 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3445 {
3446         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3447         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3448         struct i40e_vsi *vsi = pf->main_vsi;
3449         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3450
3451         dev_info->max_rx_queues = vsi->nb_qps;
3452         dev_info->max_tx_queues = vsi->nb_qps;
3453         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3454         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3455         dev_info->max_mac_addrs = vsi->max_macaddrs;
3456         dev_info->max_vfs = pci_dev->max_vfs;
3457         dev_info->rx_queue_offload_capa = 0;
3458         dev_info->rx_offload_capa =
3459                 DEV_RX_OFFLOAD_VLAN_STRIP |
3460                 DEV_RX_OFFLOAD_QINQ_STRIP |
3461                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3462                 DEV_RX_OFFLOAD_UDP_CKSUM |
3463                 DEV_RX_OFFLOAD_TCP_CKSUM |
3464                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3465                 DEV_RX_OFFLOAD_KEEP_CRC |
3466                 DEV_RX_OFFLOAD_SCATTER |
3467                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3468                 DEV_RX_OFFLOAD_VLAN_FILTER |
3469                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3470
3471         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3472         dev_info->tx_offload_capa =
3473                 DEV_TX_OFFLOAD_VLAN_INSERT |
3474                 DEV_TX_OFFLOAD_QINQ_INSERT |
3475                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3476                 DEV_TX_OFFLOAD_UDP_CKSUM |
3477                 DEV_TX_OFFLOAD_TCP_CKSUM |
3478                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3479                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3480                 DEV_TX_OFFLOAD_TCP_TSO |
3481                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3482                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3483                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3484                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3485                 DEV_TX_OFFLOAD_MULTI_SEGS |
3486                 dev_info->tx_queue_offload_capa;
3487         dev_info->dev_capa =
3488                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3489                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3490
3491         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3492                                                 sizeof(uint32_t);
3493         dev_info->reta_size = pf->hash_lut_size;
3494         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3495
3496         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3497                 .rx_thresh = {
3498                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3499                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3500                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3501                 },
3502                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3503                 .rx_drop_en = 0,
3504                 .offloads = 0,
3505         };
3506
3507         dev_info->default_txconf = (struct rte_eth_txconf) {
3508                 .tx_thresh = {
3509                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3510                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3511                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3512                 },
3513                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3514                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3515                 .offloads = 0,
3516         };
3517
3518         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3519                 .nb_max = I40E_MAX_RING_DESC,
3520                 .nb_min = I40E_MIN_RING_DESC,
3521                 .nb_align = I40E_ALIGN_RING_DESC,
3522         };
3523
3524         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3525                 .nb_max = I40E_MAX_RING_DESC,
3526                 .nb_min = I40E_MIN_RING_DESC,
3527                 .nb_align = I40E_ALIGN_RING_DESC,
3528                 .nb_seg_max = I40E_TX_MAX_SEG,
3529                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3530         };
3531
3532         if (pf->flags & I40E_FLAG_VMDQ) {
3533                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3534                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3535                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3536                                                 pf->max_nb_vmdq_vsi;
3537                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3538                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3539                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3540         }
3541
3542         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3543                 /* For XL710 */
3544                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3545                 dev_info->default_rxportconf.nb_queues = 2;
3546                 dev_info->default_txportconf.nb_queues = 2;
3547                 if (dev->data->nb_rx_queues == 1)
3548                         dev_info->default_rxportconf.ring_size = 2048;
3549                 else
3550                         dev_info->default_rxportconf.ring_size = 1024;
3551                 if (dev->data->nb_tx_queues == 1)
3552                         dev_info->default_txportconf.ring_size = 1024;
3553                 else
3554                         dev_info->default_txportconf.ring_size = 512;
3555
3556         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3557                 /* For XXV710 */
3558                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3559                 dev_info->default_rxportconf.nb_queues = 1;
3560                 dev_info->default_txportconf.nb_queues = 1;
3561                 dev_info->default_rxportconf.ring_size = 256;
3562                 dev_info->default_txportconf.ring_size = 256;
3563         } else {
3564                 /* For X710 */
3565                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3566                 dev_info->default_rxportconf.nb_queues = 1;
3567                 dev_info->default_txportconf.nb_queues = 1;
3568                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3569                         dev_info->default_rxportconf.ring_size = 512;
3570                         dev_info->default_txportconf.ring_size = 256;
3571                 } else {
3572                         dev_info->default_rxportconf.ring_size = 256;
3573                         dev_info->default_txportconf.ring_size = 256;
3574                 }
3575         }
3576         dev_info->default_rxportconf.burst_size = 32;
3577         dev_info->default_txportconf.burst_size = 32;
3578 }
3579
3580 static int
3581 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3582 {
3583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3584         struct i40e_vsi *vsi = pf->main_vsi;
3585         PMD_INIT_FUNC_TRACE();
3586
3587         if (on)
3588                 return i40e_vsi_add_vlan(vsi, vlan_id);
3589         else
3590                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3591 }
3592
3593 static int
3594 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3595                                 enum rte_vlan_type vlan_type,
3596                                 uint16_t tpid, int qinq)
3597 {
3598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         uint64_t reg_r = 0;
3600         uint64_t reg_w = 0;
3601         uint16_t reg_id = 3;
3602         int ret;
3603
3604         if (qinq) {
3605                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3606                         reg_id = 2;
3607         }
3608
3609         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3610                                           &reg_r, NULL);
3611         if (ret != I40E_SUCCESS) {
3612                 PMD_DRV_LOG(ERR,
3613                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3614                            reg_id);
3615                 return -EIO;
3616         }
3617         PMD_DRV_LOG(DEBUG,
3618                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3619                     reg_id, reg_r);
3620
3621         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3622         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3623         if (reg_r == reg_w) {
3624                 PMD_DRV_LOG(DEBUG, "No need to write");
3625                 return 0;
3626         }
3627
3628         ret = i40e_aq_debug_write_global_register(hw,
3629                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3630                                            reg_w, NULL);
3631         if (ret != I40E_SUCCESS) {
3632                 PMD_DRV_LOG(ERR,
3633                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3634                             reg_id);
3635                 return -EIO;
3636         }
3637         PMD_DRV_LOG(DEBUG,
3638                     "Global register 0x%08x is changed with value 0x%08x",
3639                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3640
3641         return 0;
3642 }
3643
3644 static int
3645 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3646                    enum rte_vlan_type vlan_type,
3647                    uint16_t tpid)
3648 {
3649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3651         int qinq = dev->data->dev_conf.rxmode.offloads &
3652                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3653         int ret = 0;
3654
3655         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3656              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3657             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3658                 PMD_DRV_LOG(ERR,
3659                             "Unsupported vlan type.");
3660                 return -EINVAL;
3661         }
3662
3663         if (pf->support_multi_driver) {
3664                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3665                 return -ENOTSUP;
3666         }
3667
3668         /* 802.1ad frames ability is added in NVM API 1.7*/
3669         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3670                 if (qinq) {
3671                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3672                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3673                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3674                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3675                 } else {
3676                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3677                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3678                 }
3679                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3680                 if (ret != I40E_SUCCESS) {
3681                         PMD_DRV_LOG(ERR,
3682                                     "Set switch config failed aq_err: %d",
3683                                     hw->aq.asq_last_status);
3684                         ret = -EIO;
3685                 }
3686         } else
3687                 /* If NVM API < 1.7, keep the register setting */
3688                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3689                                                       tpid, qinq);
3690
3691         return ret;
3692 }
3693
3694 static int
3695 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3696 {
3697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3698         struct i40e_vsi *vsi = pf->main_vsi;
3699         struct rte_eth_rxmode *rxmode;
3700
3701         rxmode = &dev->data->dev_conf.rxmode;
3702         if (mask & ETH_VLAN_FILTER_MASK) {
3703                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3704                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3705                 else
3706                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3707         }
3708
3709         if (mask & ETH_VLAN_STRIP_MASK) {
3710                 /* Enable or disable VLAN stripping */
3711                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3712                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3713                 else
3714                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3715         }
3716
3717         if (mask & ETH_VLAN_EXTEND_MASK) {
3718                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3719                         i40e_vsi_config_double_vlan(vsi, TRUE);
3720                         /* Set global registers with default ethertype. */
3721                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3722                                            ETHER_TYPE_VLAN);
3723                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3724                                            ETHER_TYPE_VLAN);
3725                 }
3726                 else
3727                         i40e_vsi_config_double_vlan(vsi, FALSE);
3728         }
3729
3730         return 0;
3731 }
3732
3733 static void
3734 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3735                           __rte_unused uint16_t queue,
3736                           __rte_unused int on)
3737 {
3738         PMD_INIT_FUNC_TRACE();
3739 }
3740
3741 static int
3742 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3743 {
3744         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3745         struct i40e_vsi *vsi = pf->main_vsi;
3746         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3747         struct i40e_vsi_vlan_pvid_info info;
3748
3749         memset(&info, 0, sizeof(info));
3750         info.on = on;
3751         if (info.on)
3752                 info.config.pvid = pvid;
3753         else {
3754                 info.config.reject.tagged =
3755                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3756                 info.config.reject.untagged =
3757                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3758         }
3759
3760         return i40e_vsi_vlan_pvid_set(vsi, &info);
3761 }
3762
3763 static int
3764 i40e_dev_led_on(struct rte_eth_dev *dev)
3765 {
3766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3767         uint32_t mode = i40e_led_get(hw);
3768
3769         if (mode == 0)
3770                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3771
3772         return 0;
3773 }
3774
3775 static int
3776 i40e_dev_led_off(struct rte_eth_dev *dev)
3777 {
3778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779         uint32_t mode = i40e_led_get(hw);
3780
3781         if (mode != 0)
3782                 i40e_led_set(hw, 0, false);
3783
3784         return 0;
3785 }
3786
3787 static int
3788 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3789 {
3790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3792
3793         fc_conf->pause_time = pf->fc_conf.pause_time;
3794
3795         /* read out from register, in case they are modified by other port */
3796         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3797                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3798         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3799                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3800
3801         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3802         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3803
3804          /* Return current mode according to actual setting*/
3805         switch (hw->fc.current_mode) {
3806         case I40E_FC_FULL:
3807                 fc_conf->mode = RTE_FC_FULL;
3808                 break;
3809         case I40E_FC_TX_PAUSE:
3810                 fc_conf->mode = RTE_FC_TX_PAUSE;
3811                 break;
3812         case I40E_FC_RX_PAUSE:
3813                 fc_conf->mode = RTE_FC_RX_PAUSE;
3814                 break;
3815         case I40E_FC_NONE:
3816         default:
3817                 fc_conf->mode = RTE_FC_NONE;
3818         };
3819
3820         return 0;
3821 }
3822
3823 static int
3824 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3825 {
3826         uint32_t mflcn_reg, fctrl_reg, reg;
3827         uint32_t max_high_water;
3828         uint8_t i, aq_failure;
3829         int err;
3830         struct i40e_hw *hw;
3831         struct i40e_pf *pf;
3832         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3833                 [RTE_FC_NONE] = I40E_FC_NONE,
3834                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3835                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3836                 [RTE_FC_FULL] = I40E_FC_FULL
3837         };
3838
3839         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3840
3841         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3842         if ((fc_conf->high_water > max_high_water) ||
3843                         (fc_conf->high_water < fc_conf->low_water)) {
3844                 PMD_INIT_LOG(ERR,
3845                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3846                         max_high_water);
3847                 return -EINVAL;
3848         }
3849
3850         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3851         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3852         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3853
3854         pf->fc_conf.pause_time = fc_conf->pause_time;
3855         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3856         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3857
3858         PMD_INIT_FUNC_TRACE();
3859
3860         /* All the link flow control related enable/disable register
3861          * configuration is handle by the F/W
3862          */
3863         err = i40e_set_fc(hw, &aq_failure, true);
3864         if (err < 0)
3865                 return -ENOSYS;
3866
3867         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3868                 /* Configure flow control refresh threshold,
3869                  * the value for stat_tx_pause_refresh_timer[8]
3870                  * is used for global pause operation.
3871                  */
3872
3873                 I40E_WRITE_REG(hw,
3874                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3875                                pf->fc_conf.pause_time);
3876
3877                 /* configure the timer value included in transmitted pause
3878                  * frame,
3879                  * the value for stat_tx_pause_quanta[8] is used for global
3880                  * pause operation
3881                  */
3882                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3883                                pf->fc_conf.pause_time);
3884
3885                 fctrl_reg = I40E_READ_REG(hw,
3886                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3887
3888                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3889                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3890                 else
3891                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3892
3893                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3894                                fctrl_reg);
3895         } else {
3896                 /* Configure pause time (2 TCs per register) */
3897                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3898                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3899                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3900
3901                 /* Configure flow control refresh threshold value */
3902                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3903                                pf->fc_conf.pause_time / 2);
3904
3905                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3906
3907                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3908                  *depending on configuration
3909                  */
3910                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3911                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3912                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3913                 } else {
3914                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3915                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3916                 }
3917
3918                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3919         }
3920
3921         if (!pf->support_multi_driver) {
3922                 /* config water marker both based on the packets and bytes */
3923                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3924                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3925                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3926                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3927                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3928                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3929                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3930                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3931                                   << I40E_KILOSHIFT);
3932                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3933                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3934                                    << I40E_KILOSHIFT);
3935         } else {
3936                 PMD_DRV_LOG(ERR,
3937                             "Water marker configuration is not supported.");
3938         }
3939
3940         I40E_WRITE_FLUSH(hw);
3941
3942         return 0;
3943 }
3944
3945 static int
3946 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3947                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3948 {
3949         PMD_INIT_FUNC_TRACE();
3950
3951         return -ENOSYS;
3952 }
3953
3954 /* Add a MAC address, and update filters */
3955 static int
3956 i40e_macaddr_add(struct rte_eth_dev *dev,
3957                  struct ether_addr *mac_addr,
3958                  __rte_unused uint32_t index,
3959                  uint32_t pool)
3960 {
3961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3962         struct i40e_mac_filter_info mac_filter;
3963         struct i40e_vsi *vsi;
3964         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3965         int ret;
3966
3967         /* If VMDQ not enabled or configured, return */
3968         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3969                           !pf->nb_cfg_vmdq_vsi)) {
3970                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3971                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3972                         pool);
3973                 return -ENOTSUP;
3974         }
3975
3976         if (pool > pf->nb_cfg_vmdq_vsi) {
3977                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3978                                 pool, pf->nb_cfg_vmdq_vsi);
3979                 return -EINVAL;
3980         }
3981
3982         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3983         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3984                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3985         else
3986                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3987
3988         if (pool == 0)
3989                 vsi = pf->main_vsi;
3990         else
3991                 vsi = pf->vmdq[pool - 1].vsi;
3992
3993         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3994         if (ret != I40E_SUCCESS) {
3995                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3996                 return -ENODEV;
3997         }
3998         return 0;
3999 }
4000
4001 /* Remove a MAC address, and update filters */
4002 static void
4003 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4004 {
4005         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4006         struct i40e_vsi *vsi;
4007         struct rte_eth_dev_data *data = dev->data;
4008         struct ether_addr *macaddr;
4009         int ret;
4010         uint32_t i;
4011         uint64_t pool_sel;
4012
4013         macaddr = &(data->mac_addrs[index]);
4014
4015         pool_sel = dev->data->mac_pool_sel[index];
4016
4017         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4018                 if (pool_sel & (1ULL << i)) {
4019                         if (i == 0)
4020                                 vsi = pf->main_vsi;
4021                         else {
4022                                 /* No VMDQ pool enabled or configured */
4023                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4024                                         (i > pf->nb_cfg_vmdq_vsi)) {
4025                                         PMD_DRV_LOG(ERR,
4026                                                 "No VMDQ pool enabled/configured");
4027                                         return;
4028                                 }
4029                                 vsi = pf->vmdq[i - 1].vsi;
4030                         }
4031                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4032
4033                         if (ret) {
4034                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4035                                 return;
4036                         }
4037                 }
4038         }
4039 }
4040
4041 /* Set perfect match or hash match of MAC and VLAN for a VF */
4042 static int
4043 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4044                  struct rte_eth_mac_filter *filter,
4045                  bool add)
4046 {
4047         struct i40e_hw *hw;
4048         struct i40e_mac_filter_info mac_filter;
4049         struct ether_addr old_mac;
4050         struct ether_addr *new_mac;
4051         struct i40e_pf_vf *vf = NULL;
4052         uint16_t vf_id;
4053         int ret;
4054
4055         if (pf == NULL) {
4056                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4057                 return -EINVAL;
4058         }
4059         hw = I40E_PF_TO_HW(pf);
4060
4061         if (filter == NULL) {
4062                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4063                 return -EINVAL;
4064         }
4065
4066         new_mac = &filter->mac_addr;
4067
4068         if (is_zero_ether_addr(new_mac)) {
4069                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4070                 return -EINVAL;
4071         }
4072
4073         vf_id = filter->dst_id;
4074
4075         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4076                 PMD_DRV_LOG(ERR, "Invalid argument.");
4077                 return -EINVAL;
4078         }
4079         vf = &pf->vfs[vf_id];
4080
4081         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4082                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4083                 return -EINVAL;
4084         }
4085
4086         if (add) {
4087                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4088                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4089                                 ETHER_ADDR_LEN);
4090                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4091                                  ETHER_ADDR_LEN);
4092
4093                 mac_filter.filter_type = filter->filter_type;
4094                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4095                 if (ret != I40E_SUCCESS) {
4096                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4097                         return -1;
4098                 }
4099                 ether_addr_copy(new_mac, &pf->dev_addr);
4100         } else {
4101                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4102                                 ETHER_ADDR_LEN);
4103                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4104                 if (ret != I40E_SUCCESS) {
4105                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4106                         return -1;
4107                 }
4108
4109                 /* Clear device address as it has been removed */
4110                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4111                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4112         }
4113
4114         return 0;
4115 }
4116
4117 /* MAC filter handle */
4118 static int
4119 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4120                 void *arg)
4121 {
4122         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4123         struct rte_eth_mac_filter *filter;
4124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4125         int ret = I40E_NOT_SUPPORTED;
4126
4127         filter = (struct rte_eth_mac_filter *)(arg);
4128
4129         switch (filter_op) {
4130         case RTE_ETH_FILTER_NOP:
4131                 ret = I40E_SUCCESS;
4132                 break;
4133         case RTE_ETH_FILTER_ADD:
4134                 i40e_pf_disable_irq0(hw);
4135                 if (filter->is_vf)
4136                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4137                 i40e_pf_enable_irq0(hw);
4138                 break;
4139         case RTE_ETH_FILTER_DELETE:
4140                 i40e_pf_disable_irq0(hw);
4141                 if (filter->is_vf)
4142                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4143                 i40e_pf_enable_irq0(hw);
4144                 break;
4145         default:
4146                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4147                 ret = I40E_ERR_PARAM;
4148                 break;
4149         }
4150
4151         return ret;
4152 }
4153
4154 static int
4155 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4156 {
4157         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159         uint32_t reg;
4160         int ret;
4161
4162         if (!lut)
4163                 return -EINVAL;
4164
4165         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4166                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4167                                           lut, lut_size);
4168                 if (ret) {
4169                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4170                         return ret;
4171                 }
4172         } else {
4173                 uint32_t *lut_dw = (uint32_t *)lut;
4174                 uint16_t i, lut_size_dw = lut_size / 4;
4175
4176                 if (vsi->type == I40E_VSI_SRIOV) {
4177                         for (i = 0; i <= lut_size_dw; i++) {
4178                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4179                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4180                         }
4181                 } else {
4182                         for (i = 0; i < lut_size_dw; i++)
4183                                 lut_dw[i] = I40E_READ_REG(hw,
4184                                                           I40E_PFQF_HLUT(i));
4185                 }
4186         }
4187
4188         return 0;
4189 }
4190
4191 int
4192 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4193 {
4194         struct i40e_pf *pf;
4195         struct i40e_hw *hw;
4196         int ret;
4197
4198         if (!vsi || !lut)
4199                 return -EINVAL;
4200
4201         pf = I40E_VSI_TO_PF(vsi);
4202         hw = I40E_VSI_TO_HW(vsi);
4203
4204         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4205                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4206                                           lut, lut_size);
4207                 if (ret) {
4208                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4209                         return ret;
4210                 }
4211         } else {
4212                 uint32_t *lut_dw = (uint32_t *)lut;
4213                 uint16_t i, lut_size_dw = lut_size / 4;
4214
4215                 if (vsi->type == I40E_VSI_SRIOV) {
4216                         for (i = 0; i < lut_size_dw; i++)
4217                                 I40E_WRITE_REG(
4218                                         hw,
4219                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4220                                         lut_dw[i]);
4221                 } else {
4222                         for (i = 0; i < lut_size_dw; i++)
4223                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4224                                                lut_dw[i]);
4225                 }
4226                 I40E_WRITE_FLUSH(hw);
4227         }
4228
4229         return 0;
4230 }
4231
4232 static int
4233 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4234                          struct rte_eth_rss_reta_entry64 *reta_conf,
4235                          uint16_t reta_size)
4236 {
4237         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4238         uint16_t i, lut_size = pf->hash_lut_size;
4239         uint16_t idx, shift;
4240         uint8_t *lut;
4241         int ret;
4242
4243         if (reta_size != lut_size ||
4244                 reta_size > ETH_RSS_RETA_SIZE_512) {
4245                 PMD_DRV_LOG(ERR,
4246                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4247                         reta_size, lut_size);
4248                 return -EINVAL;
4249         }
4250
4251         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4252         if (!lut) {
4253                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4254                 return -ENOMEM;
4255         }
4256         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4257         if (ret)
4258                 goto out;
4259         for (i = 0; i < reta_size; i++) {
4260                 idx = i / RTE_RETA_GROUP_SIZE;
4261                 shift = i % RTE_RETA_GROUP_SIZE;
4262                 if (reta_conf[idx].mask & (1ULL << shift))
4263                         lut[i] = reta_conf[idx].reta[shift];
4264         }
4265         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4266
4267 out:
4268         rte_free(lut);
4269
4270         return ret;
4271 }
4272
4273 static int
4274 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4275                         struct rte_eth_rss_reta_entry64 *reta_conf,
4276                         uint16_t reta_size)
4277 {
4278         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4279         uint16_t i, lut_size = pf->hash_lut_size;
4280         uint16_t idx, shift;
4281         uint8_t *lut;
4282         int ret;
4283
4284         if (reta_size != lut_size ||
4285                 reta_size > ETH_RSS_RETA_SIZE_512) {
4286                 PMD_DRV_LOG(ERR,
4287                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4288                         reta_size, lut_size);
4289                 return -EINVAL;
4290         }
4291
4292         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4293         if (!lut) {
4294                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4295                 return -ENOMEM;
4296         }
4297
4298         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4299         if (ret)
4300                 goto out;
4301         for (i = 0; i < reta_size; i++) {
4302                 idx = i / RTE_RETA_GROUP_SIZE;
4303                 shift = i % RTE_RETA_GROUP_SIZE;
4304                 if (reta_conf[idx].mask & (1ULL << shift))
4305                         reta_conf[idx].reta[shift] = lut[i];
4306         }
4307
4308 out:
4309         rte_free(lut);
4310
4311         return ret;
4312 }
4313
4314 /**
4315  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4316  * @hw:   pointer to the HW structure
4317  * @mem:  pointer to mem struct to fill out
4318  * @size: size of memory requested
4319  * @alignment: what to align the allocation to
4320  **/
4321 enum i40e_status_code
4322 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4323                         struct i40e_dma_mem *mem,
4324                         u64 size,
4325                         u32 alignment)
4326 {
4327         const struct rte_memzone *mz = NULL;
4328         char z_name[RTE_MEMZONE_NAMESIZE];
4329
4330         if (!mem)
4331                 return I40E_ERR_PARAM;
4332
4333         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4334         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4335                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4336         if (!mz)
4337                 return I40E_ERR_NO_MEMORY;
4338
4339         mem->size = size;
4340         mem->va = mz->addr;
4341         mem->pa = mz->iova;
4342         mem->zone = (const void *)mz;
4343         PMD_DRV_LOG(DEBUG,
4344                 "memzone %s allocated with physical address: %"PRIu64,
4345                 mz->name, mem->pa);
4346
4347         return I40E_SUCCESS;
4348 }
4349
4350 /**
4351  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4352  * @hw:   pointer to the HW structure
4353  * @mem:  ptr to mem struct to free
4354  **/
4355 enum i40e_status_code
4356 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4357                     struct i40e_dma_mem *mem)
4358 {
4359         if (!mem)
4360                 return I40E_ERR_PARAM;
4361
4362         PMD_DRV_LOG(DEBUG,
4363                 "memzone %s to be freed with physical address: %"PRIu64,
4364                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4365         rte_memzone_free((const struct rte_memzone *)mem->zone);
4366         mem->zone = NULL;
4367         mem->va = NULL;
4368         mem->pa = (u64)0;
4369
4370         return I40E_SUCCESS;
4371 }
4372
4373 /**
4374  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4375  * @hw:   pointer to the HW structure
4376  * @mem:  pointer to mem struct to fill out
4377  * @size: size of memory requested
4378  **/
4379 enum i40e_status_code
4380 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4381                          struct i40e_virt_mem *mem,
4382                          u32 size)
4383 {
4384         if (!mem)
4385                 return I40E_ERR_PARAM;
4386
4387         mem->size = size;
4388         mem->va = rte_zmalloc("i40e", size, 0);
4389
4390         if (mem->va)
4391                 return I40E_SUCCESS;
4392         else
4393                 return I40E_ERR_NO_MEMORY;
4394 }
4395
4396 /**
4397  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4398  * @hw:   pointer to the HW structure
4399  * @mem:  pointer to mem struct to free
4400  **/
4401 enum i40e_status_code
4402 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4403                      struct i40e_virt_mem *mem)
4404 {
4405         if (!mem)
4406                 return I40E_ERR_PARAM;
4407
4408         rte_free(mem->va);
4409         mem->va = NULL;
4410
4411         return I40E_SUCCESS;
4412 }
4413
4414 void
4415 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4416 {
4417         rte_spinlock_init(&sp->spinlock);
4418 }
4419
4420 void
4421 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4422 {
4423         rte_spinlock_lock(&sp->spinlock);
4424 }
4425
4426 void
4427 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4428 {
4429         rte_spinlock_unlock(&sp->spinlock);
4430 }
4431
4432 void
4433 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4434 {
4435         return;
4436 }
4437
4438 /**
4439  * Get the hardware capabilities, which will be parsed
4440  * and saved into struct i40e_hw.
4441  */
4442 static int
4443 i40e_get_cap(struct i40e_hw *hw)
4444 {
4445         struct i40e_aqc_list_capabilities_element_resp *buf;
4446         uint16_t len, size = 0;
4447         int ret;
4448
4449         /* Calculate a huge enough buff for saving response data temporarily */
4450         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4451                                                 I40E_MAX_CAP_ELE_NUM;
4452         buf = rte_zmalloc("i40e", len, 0);
4453         if (!buf) {
4454                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4455                 return I40E_ERR_NO_MEMORY;
4456         }
4457
4458         /* Get, parse the capabilities and save it to hw */
4459         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4460                         i40e_aqc_opc_list_func_capabilities, NULL);
4461         if (ret != I40E_SUCCESS)
4462                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4463
4464         /* Free the temporary buffer after being used */
4465         rte_free(buf);
4466
4467         return ret;
4468 }
4469
4470 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4471
4472 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4473                 const char *value,
4474                 void *opaque)
4475 {
4476         struct i40e_pf *pf;
4477         unsigned long num;
4478         char *end;
4479
4480         pf = (struct i40e_pf *)opaque;
4481         RTE_SET_USED(key);
4482
4483         errno = 0;
4484         num = strtoul(value, &end, 0);
4485         if (errno != 0 || end == value || *end != 0) {
4486                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4487                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4488                 return -(EINVAL);
4489         }
4490
4491         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4492                 pf->vf_nb_qp_max = (uint16_t)num;
4493         else
4494                 /* here return 0 to make next valid same argument work */
4495                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4496                             "power of 2 and equal or less than 16 !, Now it is "
4497                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4498
4499         return 0;
4500 }
4501
4502 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4503 {
4504         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4505         struct rte_kvargs *kvlist;
4506         int kvargs_count;
4507
4508         /* set default queue number per VF as 4 */
4509         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4510
4511         if (dev->device->devargs == NULL)
4512                 return 0;
4513
4514         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4515         if (kvlist == NULL)
4516                 return -(EINVAL);
4517
4518         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4519         if (!kvargs_count) {
4520                 rte_kvargs_free(kvlist);
4521                 return 0;
4522         }
4523
4524         if (kvargs_count > 1)
4525                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4526                             "the first invalid or last valid one is used !",
4527                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4528
4529         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4530                            i40e_pf_parse_vf_queue_number_handler, pf);
4531
4532         rte_kvargs_free(kvlist);
4533
4534         return 0;
4535 }
4536
4537 static int
4538 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4539 {
4540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4541         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4542         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4543         uint16_t qp_count = 0, vsi_count = 0;
4544
4545         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4546                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4547                 return -EINVAL;
4548         }
4549
4550         i40e_pf_config_vf_rxq_number(dev);
4551
4552         /* Add the parameter init for LFC */
4553         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4554         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4555         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4556
4557         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4558         pf->max_num_vsi = hw->func_caps.num_vsis;
4559         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4560         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4561
4562         /* FDir queue/VSI allocation */
4563         pf->fdir_qp_offset = 0;
4564         if (hw->func_caps.fd) {
4565                 pf->flags |= I40E_FLAG_FDIR;
4566                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4567         } else {
4568                 pf->fdir_nb_qps = 0;
4569         }
4570         qp_count += pf->fdir_nb_qps;
4571         vsi_count += 1;
4572
4573         /* LAN queue/VSI allocation */
4574         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4575         if (!hw->func_caps.rss) {
4576                 pf->lan_nb_qps = 1;
4577         } else {
4578                 pf->flags |= I40E_FLAG_RSS;
4579                 if (hw->mac.type == I40E_MAC_X722)
4580                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4581                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4582         }
4583         qp_count += pf->lan_nb_qps;
4584         vsi_count += 1;
4585
4586         /* VF queue/VSI allocation */
4587         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4588         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4589                 pf->flags |= I40E_FLAG_SRIOV;
4590                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4591                 pf->vf_num = pci_dev->max_vfs;
4592                 PMD_DRV_LOG(DEBUG,
4593                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4594                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4595         } else {
4596                 pf->vf_nb_qps = 0;
4597                 pf->vf_num = 0;
4598         }
4599         qp_count += pf->vf_nb_qps * pf->vf_num;
4600         vsi_count += pf->vf_num;
4601
4602         /* VMDq queue/VSI allocation */
4603         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4604         pf->vmdq_nb_qps = 0;
4605         pf->max_nb_vmdq_vsi = 0;
4606         if (hw->func_caps.vmdq) {
4607                 if (qp_count < hw->func_caps.num_tx_qp &&
4608                         vsi_count < hw->func_caps.num_vsis) {
4609                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4610                                 qp_count) / pf->vmdq_nb_qp_max;
4611
4612                         /* Limit the maximum number of VMDq vsi to the maximum
4613                          * ethdev can support
4614                          */
4615                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4616                                 hw->func_caps.num_vsis - vsi_count);
4617                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4618                                 ETH_64_POOLS);
4619                         if (pf->max_nb_vmdq_vsi) {
4620                                 pf->flags |= I40E_FLAG_VMDQ;
4621                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4622                                 PMD_DRV_LOG(DEBUG,
4623                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4624                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4625                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4626                         } else {
4627                                 PMD_DRV_LOG(INFO,
4628                                         "No enough queues left for VMDq");
4629                         }
4630                 } else {
4631                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4632                 }
4633         }
4634         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4635         vsi_count += pf->max_nb_vmdq_vsi;
4636
4637         if (hw->func_caps.dcb)
4638                 pf->flags |= I40E_FLAG_DCB;
4639
4640         if (qp_count > hw->func_caps.num_tx_qp) {
4641                 PMD_DRV_LOG(ERR,
4642                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4643                         qp_count, hw->func_caps.num_tx_qp);
4644                 return -EINVAL;
4645         }
4646         if (vsi_count > hw->func_caps.num_vsis) {
4647                 PMD_DRV_LOG(ERR,
4648                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4649                         vsi_count, hw->func_caps.num_vsis);
4650                 return -EINVAL;
4651         }
4652
4653         return 0;
4654 }
4655
4656 static int
4657 i40e_pf_get_switch_config(struct i40e_pf *pf)
4658 {
4659         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4660         struct i40e_aqc_get_switch_config_resp *switch_config;
4661         struct i40e_aqc_switch_config_element_resp *element;
4662         uint16_t start_seid = 0, num_reported;
4663         int ret;
4664
4665         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4666                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4667         if (!switch_config) {
4668                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4669                 return -ENOMEM;
4670         }
4671
4672         /* Get the switch configurations */
4673         ret = i40e_aq_get_switch_config(hw, switch_config,
4674                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4675         if (ret != I40E_SUCCESS) {
4676                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4677                 goto fail;
4678         }
4679         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4680         if (num_reported != 1) { /* The number should be 1 */
4681                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4682                 goto fail;
4683         }
4684
4685         /* Parse the switch configuration elements */
4686         element = &(switch_config->element[0]);
4687         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4688                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4689                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4690         } else
4691                 PMD_DRV_LOG(INFO, "Unknown element type");
4692
4693 fail:
4694         rte_free(switch_config);
4695
4696         return ret;
4697 }
4698
4699 static int
4700 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4701                         uint32_t num)
4702 {
4703         struct pool_entry *entry;
4704
4705         if (pool == NULL || num == 0)
4706                 return -EINVAL;
4707
4708         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4709         if (entry == NULL) {
4710                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4711                 return -ENOMEM;
4712         }
4713
4714         /* queue heap initialize */
4715         pool->num_free = num;
4716         pool->num_alloc = 0;
4717         pool->base = base;
4718         LIST_INIT(&pool->alloc_list);
4719         LIST_INIT(&pool->free_list);
4720
4721         /* Initialize element  */
4722         entry->base = 0;
4723         entry->len = num;
4724
4725         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4726         return 0;
4727 }
4728
4729 static void
4730 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4731 {
4732         struct pool_entry *entry, *next_entry;
4733
4734         if (pool == NULL)
4735                 return;
4736
4737         for (entry = LIST_FIRST(&pool->alloc_list);
4738                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4739                         entry = next_entry) {
4740                 LIST_REMOVE(entry, next);
4741                 rte_free(entry);
4742         }
4743
4744         for (entry = LIST_FIRST(&pool->free_list);
4745                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4746                         entry = next_entry) {
4747                 LIST_REMOVE(entry, next);
4748                 rte_free(entry);
4749         }
4750
4751         pool->num_free = 0;
4752         pool->num_alloc = 0;
4753         pool->base = 0;
4754         LIST_INIT(&pool->alloc_list);
4755         LIST_INIT(&pool->free_list);
4756 }
4757
4758 static int
4759 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4760                        uint32_t base)
4761 {
4762         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4763         uint32_t pool_offset;
4764         int insert;
4765
4766         if (pool == NULL) {
4767                 PMD_DRV_LOG(ERR, "Invalid parameter");
4768                 return -EINVAL;
4769         }
4770
4771         pool_offset = base - pool->base;
4772         /* Lookup in alloc list */
4773         LIST_FOREACH(entry, &pool->alloc_list, next) {
4774                 if (entry->base == pool_offset) {
4775                         valid_entry = entry;
4776                         LIST_REMOVE(entry, next);
4777                         break;
4778                 }
4779         }
4780
4781         /* Not find, return */
4782         if (valid_entry == NULL) {
4783                 PMD_DRV_LOG(ERR, "Failed to find entry");
4784                 return -EINVAL;
4785         }
4786
4787         /**
4788          * Found it, move it to free list  and try to merge.
4789          * In order to make merge easier, always sort it by qbase.
4790          * Find adjacent prev and last entries.
4791          */
4792         prev = next = NULL;
4793         LIST_FOREACH(entry, &pool->free_list, next) {
4794                 if (entry->base > valid_entry->base) {
4795                         next = entry;
4796                         break;
4797                 }
4798                 prev = entry;
4799         }
4800
4801         insert = 0;
4802         /* Try to merge with next one*/
4803         if (next != NULL) {
4804                 /* Merge with next one */
4805                 if (valid_entry->base + valid_entry->len == next->base) {
4806                         next->base = valid_entry->base;
4807                         next->len += valid_entry->len;
4808                         rte_free(valid_entry);
4809                         valid_entry = next;
4810                         insert = 1;
4811                 }
4812         }
4813
4814         if (prev != NULL) {
4815                 /* Merge with previous one */
4816                 if (prev->base + prev->len == valid_entry->base) {
4817                         prev->len += valid_entry->len;
4818                         /* If it merge with next one, remove next node */
4819                         if (insert == 1) {
4820                                 LIST_REMOVE(valid_entry, next);
4821                                 rte_free(valid_entry);
4822                         } else {
4823                                 rte_free(valid_entry);
4824                                 insert = 1;
4825                         }
4826                 }
4827         }
4828
4829         /* Not find any entry to merge, insert */
4830         if (insert == 0) {
4831                 if (prev != NULL)
4832                         LIST_INSERT_AFTER(prev, valid_entry, next);
4833                 else if (next != NULL)
4834                         LIST_INSERT_BEFORE(next, valid_entry, next);
4835                 else /* It's empty list, insert to head */
4836                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4837         }
4838
4839         pool->num_free += valid_entry->len;
4840         pool->num_alloc -= valid_entry->len;
4841
4842         return 0;
4843 }
4844
4845 static int
4846 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4847                        uint16_t num)
4848 {
4849         struct pool_entry *entry, *valid_entry;
4850
4851         if (pool == NULL || num == 0) {
4852                 PMD_DRV_LOG(ERR, "Invalid parameter");
4853                 return -EINVAL;
4854         }
4855
4856         if (pool->num_free < num) {
4857                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4858                             num, pool->num_free);
4859                 return -ENOMEM;
4860         }
4861
4862         valid_entry = NULL;
4863         /* Lookup  in free list and find most fit one */
4864         LIST_FOREACH(entry, &pool->free_list, next) {
4865                 if (entry->len >= num) {
4866                         /* Find best one */
4867                         if (entry->len == num) {
4868                                 valid_entry = entry;
4869                                 break;
4870                         }
4871                         if (valid_entry == NULL || valid_entry->len > entry->len)
4872                                 valid_entry = entry;
4873                 }
4874         }
4875
4876         /* Not find one to satisfy the request, return */
4877         if (valid_entry == NULL) {
4878                 PMD_DRV_LOG(ERR, "No valid entry found");
4879                 return -ENOMEM;
4880         }
4881         /**
4882          * The entry have equal queue number as requested,
4883          * remove it from alloc_list.
4884          */
4885         if (valid_entry->len == num) {
4886                 LIST_REMOVE(valid_entry, next);
4887         } else {
4888                 /**
4889                  * The entry have more numbers than requested,
4890                  * create a new entry for alloc_list and minus its
4891                  * queue base and number in free_list.
4892                  */
4893                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4894                 if (entry == NULL) {
4895                         PMD_DRV_LOG(ERR,
4896                                 "Failed to allocate memory for resource pool");
4897                         return -ENOMEM;
4898                 }
4899                 entry->base = valid_entry->base;
4900                 entry->len = num;
4901                 valid_entry->base += num;
4902                 valid_entry->len -= num;
4903                 valid_entry = entry;
4904         }
4905
4906         /* Insert it into alloc list, not sorted */
4907         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4908
4909         pool->num_free -= valid_entry->len;
4910         pool->num_alloc += valid_entry->len;
4911
4912         return valid_entry->base + pool->base;
4913 }
4914
4915 /**
4916  * bitmap_is_subset - Check whether src2 is subset of src1
4917  **/
4918 static inline int
4919 bitmap_is_subset(uint8_t src1, uint8_t src2)
4920 {
4921         return !((src1 ^ src2) & src2);
4922 }
4923
4924 static enum i40e_status_code
4925 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4926 {
4927         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4928
4929         /* If DCB is not supported, only default TC is supported */
4930         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4931                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4932                 return I40E_NOT_SUPPORTED;
4933         }
4934
4935         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4936                 PMD_DRV_LOG(ERR,
4937                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4938                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4939                 return I40E_NOT_SUPPORTED;
4940         }
4941         return I40E_SUCCESS;
4942 }
4943
4944 int
4945 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4946                                 struct i40e_vsi_vlan_pvid_info *info)
4947 {
4948         struct i40e_hw *hw;
4949         struct i40e_vsi_context ctxt;
4950         uint8_t vlan_flags = 0;
4951         int ret;
4952
4953         if (vsi == NULL || info == NULL) {
4954                 PMD_DRV_LOG(ERR, "invalid parameters");
4955                 return I40E_ERR_PARAM;
4956         }
4957
4958         if (info->on) {
4959                 vsi->info.pvid = info->config.pvid;
4960                 /**
4961                  * If insert pvid is enabled, only tagged pkts are
4962                  * allowed to be sent out.
4963                  */
4964                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4965                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4966         } else {
4967                 vsi->info.pvid = 0;
4968                 if (info->config.reject.tagged == 0)
4969                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4970
4971                 if (info->config.reject.untagged == 0)
4972                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4973         }
4974         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4975                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4976         vsi->info.port_vlan_flags |= vlan_flags;
4977         vsi->info.valid_sections =
4978                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4979         memset(&ctxt, 0, sizeof(ctxt));
4980         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4981         ctxt.seid = vsi->seid;
4982
4983         hw = I40E_VSI_TO_HW(vsi);
4984         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4985         if (ret != I40E_SUCCESS)
4986                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4987
4988         return ret;
4989 }
4990
4991 static int
4992 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4993 {
4994         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4995         int i, ret;
4996         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4997
4998         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4999         if (ret != I40E_SUCCESS)
5000                 return ret;
5001
5002         if (!vsi->seid) {
5003                 PMD_DRV_LOG(ERR, "seid not valid");
5004                 return -EINVAL;
5005         }
5006
5007         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5008         tc_bw_data.tc_valid_bits = enabled_tcmap;
5009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5010                 tc_bw_data.tc_bw_credits[i] =
5011                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5012
5013         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5014         if (ret != I40E_SUCCESS) {
5015                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5016                 return ret;
5017         }
5018
5019         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5020                                         sizeof(vsi->info.qs_handle));
5021         return I40E_SUCCESS;
5022 }
5023
5024 static enum i40e_status_code
5025 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5026                                  struct i40e_aqc_vsi_properties_data *info,
5027                                  uint8_t enabled_tcmap)
5028 {
5029         enum i40e_status_code ret;
5030         int i, total_tc = 0;
5031         uint16_t qpnum_per_tc, bsf, qp_idx;
5032
5033         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5034         if (ret != I40E_SUCCESS)
5035                 return ret;
5036
5037         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5038                 if (enabled_tcmap & (1 << i))
5039                         total_tc++;
5040         if (total_tc == 0)
5041                 total_tc = 1;
5042         vsi->enabled_tc = enabled_tcmap;
5043
5044         /* Number of queues per enabled TC */
5045         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5046         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5047         bsf = rte_bsf32(qpnum_per_tc);
5048
5049         /* Adjust the queue number to actual queues that can be applied */
5050         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5051                 vsi->nb_qps = qpnum_per_tc * total_tc;
5052
5053         /**
5054          * Configure TC and queue mapping parameters, for enabled TC,
5055          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5056          * default queue will serve it.
5057          */
5058         qp_idx = 0;
5059         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5060                 if (vsi->enabled_tc & (1 << i)) {
5061                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5062                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5063                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5064                         qp_idx += qpnum_per_tc;
5065                 } else
5066                         info->tc_mapping[i] = 0;
5067         }
5068
5069         /* Associate queue number with VSI */
5070         if (vsi->type == I40E_VSI_SRIOV) {
5071                 info->mapping_flags |=
5072                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5073                 for (i = 0; i < vsi->nb_qps; i++)
5074                         info->queue_mapping[i] =
5075                                 rte_cpu_to_le_16(vsi->base_queue + i);
5076         } else {
5077                 info->mapping_flags |=
5078                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5079                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5080         }
5081         info->valid_sections |=
5082                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5083
5084         return I40E_SUCCESS;
5085 }
5086
5087 static int
5088 i40e_veb_release(struct i40e_veb *veb)
5089 {
5090         struct i40e_vsi *vsi;
5091         struct i40e_hw *hw;
5092
5093         if (veb == NULL)
5094                 return -EINVAL;
5095
5096         if (!TAILQ_EMPTY(&veb->head)) {
5097                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5098                 return -EACCES;
5099         }
5100         /* associate_vsi field is NULL for floating VEB */
5101         if (veb->associate_vsi != NULL) {
5102                 vsi = veb->associate_vsi;
5103                 hw = I40E_VSI_TO_HW(vsi);
5104
5105                 vsi->uplink_seid = veb->uplink_seid;
5106                 vsi->veb = NULL;
5107         } else {
5108                 veb->associate_pf->main_vsi->floating_veb = NULL;
5109                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5110         }
5111
5112         i40e_aq_delete_element(hw, veb->seid, NULL);
5113         rte_free(veb);
5114         return I40E_SUCCESS;
5115 }
5116
5117 /* Setup a veb */
5118 static struct i40e_veb *
5119 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5120 {
5121         struct i40e_veb *veb;
5122         int ret;
5123         struct i40e_hw *hw;
5124
5125         if (pf == NULL) {
5126                 PMD_DRV_LOG(ERR,
5127                             "veb setup failed, associated PF shouldn't null");
5128                 return NULL;
5129         }
5130         hw = I40E_PF_TO_HW(pf);
5131
5132         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5133         if (!veb) {
5134                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5135                 goto fail;
5136         }
5137
5138         veb->associate_vsi = vsi;
5139         veb->associate_pf = pf;
5140         TAILQ_INIT(&veb->head);
5141         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5142
5143         /* create floating veb if vsi is NULL */
5144         if (vsi != NULL) {
5145                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5146                                       I40E_DEFAULT_TCMAP, false,
5147                                       &veb->seid, false, NULL);
5148         } else {
5149                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5150                                       true, &veb->seid, false, NULL);
5151         }
5152
5153         if (ret != I40E_SUCCESS) {
5154                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5155                             hw->aq.asq_last_status);
5156                 goto fail;
5157         }
5158         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5159
5160         /* get statistics index */
5161         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5162                                 &veb->stats_idx, NULL, NULL, NULL);
5163         if (ret != I40E_SUCCESS) {
5164                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5165                             hw->aq.asq_last_status);
5166                 goto fail;
5167         }
5168         /* Get VEB bandwidth, to be implemented */
5169         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5170         if (vsi)
5171                 vsi->uplink_seid = veb->seid;
5172
5173         return veb;
5174 fail:
5175         rte_free(veb);
5176         return NULL;
5177 }
5178
5179 int
5180 i40e_vsi_release(struct i40e_vsi *vsi)
5181 {
5182         struct i40e_pf *pf;
5183         struct i40e_hw *hw;
5184         struct i40e_vsi_list *vsi_list;
5185         void *temp;
5186         int ret;
5187         struct i40e_mac_filter *f;
5188         uint16_t user_param;
5189
5190         if (!vsi)
5191                 return I40E_SUCCESS;
5192
5193         if (!vsi->adapter)
5194                 return -EFAULT;
5195
5196         user_param = vsi->user_param;
5197
5198         pf = I40E_VSI_TO_PF(vsi);
5199         hw = I40E_VSI_TO_HW(vsi);
5200
5201         /* VSI has child to attach, release child first */
5202         if (vsi->veb) {
5203                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5204                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5205                                 return -1;
5206                 }
5207                 i40e_veb_release(vsi->veb);
5208         }
5209
5210         if (vsi->floating_veb) {
5211                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5212                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5213                                 return -1;
5214                 }
5215         }
5216
5217         /* Remove all macvlan filters of the VSI */
5218         i40e_vsi_remove_all_macvlan_filter(vsi);
5219         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5220                 rte_free(f);
5221
5222         if (vsi->type != I40E_VSI_MAIN &&
5223             ((vsi->type != I40E_VSI_SRIOV) ||
5224             !pf->floating_veb_list[user_param])) {
5225                 /* Remove vsi from parent's sibling list */
5226                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5227                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5228                         return I40E_ERR_PARAM;
5229                 }
5230                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5231                                 &vsi->sib_vsi_list, list);
5232
5233                 /* Remove all switch element of the VSI */
5234                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5235                 if (ret != I40E_SUCCESS)
5236                         PMD_DRV_LOG(ERR, "Failed to delete element");
5237         }
5238
5239         if ((vsi->type == I40E_VSI_SRIOV) &&
5240             pf->floating_veb_list[user_param]) {
5241                 /* Remove vsi from parent's sibling list */
5242                 if (vsi->parent_vsi == NULL ||
5243                     vsi->parent_vsi->floating_veb == NULL) {
5244                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5245                         return I40E_ERR_PARAM;
5246                 }
5247                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5248                              &vsi->sib_vsi_list, list);
5249
5250                 /* Remove all switch element of the VSI */
5251                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5252                 if (ret != I40E_SUCCESS)
5253                         PMD_DRV_LOG(ERR, "Failed to delete element");
5254         }
5255
5256         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5257
5258         if (vsi->type != I40E_VSI_SRIOV)
5259                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5260         rte_free(vsi);
5261
5262         return I40E_SUCCESS;
5263 }
5264
5265 static int
5266 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5267 {
5268         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5269         struct i40e_aqc_remove_macvlan_element_data def_filter;
5270         struct i40e_mac_filter_info filter;
5271         int ret;
5272
5273         if (vsi->type != I40E_VSI_MAIN)
5274                 return I40E_ERR_CONFIG;
5275         memset(&def_filter, 0, sizeof(def_filter));
5276         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5277                                         ETH_ADDR_LEN);
5278         def_filter.vlan_tag = 0;
5279         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5280                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5281         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5282         if (ret != I40E_SUCCESS) {
5283                 struct i40e_mac_filter *f;
5284                 struct ether_addr *mac;
5285
5286                 PMD_DRV_LOG(DEBUG,
5287                             "Cannot remove the default macvlan filter");
5288                 /* It needs to add the permanent mac into mac list */
5289                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5290                 if (f == NULL) {
5291                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5292                         return I40E_ERR_NO_MEMORY;
5293                 }
5294                 mac = &f->mac_info.mac_addr;
5295                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5296                                 ETH_ADDR_LEN);
5297                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5298                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5299                 vsi->mac_num++;
5300
5301                 return ret;
5302         }
5303         rte_memcpy(&filter.mac_addr,
5304                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5305         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5306         return i40e_vsi_add_mac(vsi, &filter);
5307 }
5308
5309 /*
5310  * i40e_vsi_get_bw_config - Query VSI BW Information
5311  * @vsi: the VSI to be queried
5312  *
5313  * Returns 0 on success, negative value on failure
5314  */
5315 static enum i40e_status_code
5316 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5317 {
5318         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5319         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5320         struct i40e_hw *hw = &vsi->adapter->hw;
5321         i40e_status ret;
5322         int i;
5323         uint32_t bw_max;
5324
5325         memset(&bw_config, 0, sizeof(bw_config));
5326         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5327         if (ret != I40E_SUCCESS) {
5328                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5329                             hw->aq.asq_last_status);
5330                 return ret;
5331         }
5332
5333         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5334         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5335                                         &ets_sla_config, NULL);
5336         if (ret != I40E_SUCCESS) {
5337                 PMD_DRV_LOG(ERR,
5338                         "VSI failed to get TC bandwdith configuration %u",
5339                         hw->aq.asq_last_status);
5340                 return ret;
5341         }
5342
5343         /* store and print out BW info */
5344         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5345         vsi->bw_info.bw_max = bw_config.max_bw;
5346         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5347         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5348         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5349                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5350                      I40E_16_BIT_WIDTH);
5351         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5352                 vsi->bw_info.bw_ets_share_credits[i] =
5353                                 ets_sla_config.share_credits[i];
5354                 vsi->bw_info.bw_ets_credits[i] =
5355                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5356                 /* 4 bits per TC, 4th bit is reserved */
5357                 vsi->bw_info.bw_ets_max[i] =
5358                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5359                                   RTE_LEN2MASK(3, uint8_t));
5360                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5361                             vsi->bw_info.bw_ets_share_credits[i]);
5362                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5363                             vsi->bw_info.bw_ets_credits[i]);
5364                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5365                             vsi->bw_info.bw_ets_max[i]);
5366         }
5367
5368         return I40E_SUCCESS;
5369 }
5370
5371 /* i40e_enable_pf_lb
5372  * @pf: pointer to the pf structure
5373  *
5374  * allow loopback on pf
5375  */
5376 static inline void
5377 i40e_enable_pf_lb(struct i40e_pf *pf)
5378 {
5379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5380         struct i40e_vsi_context ctxt;
5381         int ret;
5382
5383         /* Use the FW API if FW >= v5.0 */
5384         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5385                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5386                 return;
5387         }
5388
5389         memset(&ctxt, 0, sizeof(ctxt));
5390         ctxt.seid = pf->main_vsi_seid;
5391         ctxt.pf_num = hw->pf_id;
5392         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5393         if (ret) {
5394                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5395                             ret, hw->aq.asq_last_status);
5396                 return;
5397         }
5398         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5399         ctxt.info.valid_sections =
5400                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5401         ctxt.info.switch_id |=
5402                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5403
5404         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5405         if (ret)
5406                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5407                             hw->aq.asq_last_status);
5408 }
5409
5410 /* Setup a VSI */
5411 struct i40e_vsi *
5412 i40e_vsi_setup(struct i40e_pf *pf,
5413                enum i40e_vsi_type type,
5414                struct i40e_vsi *uplink_vsi,
5415                uint16_t user_param)
5416 {
5417         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5418         struct i40e_vsi *vsi;
5419         struct i40e_mac_filter_info filter;
5420         int ret;
5421         struct i40e_vsi_context ctxt;
5422         struct ether_addr broadcast =
5423                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5424
5425         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5426             uplink_vsi == NULL) {
5427                 PMD_DRV_LOG(ERR,
5428                         "VSI setup failed, VSI link shouldn't be NULL");
5429                 return NULL;
5430         }
5431
5432         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5433                 PMD_DRV_LOG(ERR,
5434                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5435                 return NULL;
5436         }
5437
5438         /* two situations
5439          * 1.type is not MAIN and uplink vsi is not NULL
5440          * If uplink vsi didn't setup VEB, create one first under veb field
5441          * 2.type is SRIOV and the uplink is NULL
5442          * If floating VEB is NULL, create one veb under floating veb field
5443          */
5444
5445         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5446             uplink_vsi->veb == NULL) {
5447                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5448
5449                 if (uplink_vsi->veb == NULL) {
5450                         PMD_DRV_LOG(ERR, "VEB setup failed");
5451                         return NULL;
5452                 }
5453                 /* set ALLOWLOOPBACk on pf, when veb is created */
5454                 i40e_enable_pf_lb(pf);
5455         }
5456
5457         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5458             pf->main_vsi->floating_veb == NULL) {
5459                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5460
5461                 if (pf->main_vsi->floating_veb == NULL) {
5462                         PMD_DRV_LOG(ERR, "VEB setup failed");
5463                         return NULL;
5464                 }
5465         }
5466
5467         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5468         if (!vsi) {
5469                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5470                 return NULL;
5471         }
5472         TAILQ_INIT(&vsi->mac_list);
5473         vsi->type = type;
5474         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5475         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5476         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5477         vsi->user_param = user_param;
5478         vsi->vlan_anti_spoof_on = 0;
5479         vsi->vlan_filter_on = 0;
5480         /* Allocate queues */
5481         switch (vsi->type) {
5482         case I40E_VSI_MAIN  :
5483                 vsi->nb_qps = pf->lan_nb_qps;
5484                 break;
5485         case I40E_VSI_SRIOV :
5486                 vsi->nb_qps = pf->vf_nb_qps;
5487                 break;
5488         case I40E_VSI_VMDQ2:
5489                 vsi->nb_qps = pf->vmdq_nb_qps;
5490                 break;
5491         case I40E_VSI_FDIR:
5492                 vsi->nb_qps = pf->fdir_nb_qps;
5493                 break;
5494         default:
5495                 goto fail_mem;
5496         }
5497         /*
5498          * The filter status descriptor is reported in rx queue 0,
5499          * while the tx queue for fdir filter programming has no
5500          * such constraints, can be non-zero queues.
5501          * To simplify it, choose FDIR vsi use queue 0 pair.
5502          * To make sure it will use queue 0 pair, queue allocation
5503          * need be done before this function is called
5504          */
5505         if (type != I40E_VSI_FDIR) {
5506                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5507                         if (ret < 0) {
5508                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5509                                                 vsi->seid, ret);
5510                                 goto fail_mem;
5511                         }
5512                         vsi->base_queue = ret;
5513         } else
5514                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5515
5516         /* VF has MSIX interrupt in VF range, don't allocate here */
5517         if (type == I40E_VSI_MAIN) {
5518                 if (pf->support_multi_driver) {
5519                         /* If support multi-driver, need to use INT0 instead of
5520                          * allocating from msix pool. The Msix pool is init from
5521                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5522                          * to 1 without calling i40e_res_pool_alloc.
5523                          */
5524                         vsi->msix_intr = 0;
5525                         vsi->nb_msix = 1;
5526                 } else {
5527                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5528                                                   RTE_MIN(vsi->nb_qps,
5529                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5530                         if (ret < 0) {
5531                                 PMD_DRV_LOG(ERR,
5532                                             "VSI MAIN %d get heap failed %d",
5533                                             vsi->seid, ret);
5534                                 goto fail_queue_alloc;
5535                         }
5536                         vsi->msix_intr = ret;
5537                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5538                                                RTE_MAX_RXTX_INTR_VEC_ID);
5539                 }
5540         } else if (type != I40E_VSI_SRIOV) {
5541                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5542                 if (ret < 0) {
5543                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5544                         goto fail_queue_alloc;
5545                 }
5546                 vsi->msix_intr = ret;
5547                 vsi->nb_msix = 1;
5548         } else {
5549                 vsi->msix_intr = 0;
5550                 vsi->nb_msix = 0;
5551         }
5552
5553         /* Add VSI */
5554         if (type == I40E_VSI_MAIN) {
5555                 /* For main VSI, no need to add since it's default one */
5556                 vsi->uplink_seid = pf->mac_seid;
5557                 vsi->seid = pf->main_vsi_seid;
5558                 /* Bind queues with specific MSIX interrupt */
5559                 /**
5560                  * Needs 2 interrupt at least, one for misc cause which will
5561                  * enabled from OS side, Another for queues binding the
5562                  * interrupt from device side only.
5563                  */
5564
5565                 /* Get default VSI parameters from hardware */
5566                 memset(&ctxt, 0, sizeof(ctxt));
5567                 ctxt.seid = vsi->seid;
5568                 ctxt.pf_num = hw->pf_id;
5569                 ctxt.uplink_seid = vsi->uplink_seid;
5570                 ctxt.vf_num = 0;
5571                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5572                 if (ret != I40E_SUCCESS) {
5573                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5574                         goto fail_msix_alloc;
5575                 }
5576                 rte_memcpy(&vsi->info, &ctxt.info,
5577                         sizeof(struct i40e_aqc_vsi_properties_data));
5578                 vsi->vsi_id = ctxt.vsi_number;
5579                 vsi->info.valid_sections = 0;
5580
5581                 /* Configure tc, enabled TC0 only */
5582                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5583                         I40E_SUCCESS) {
5584                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5585                         goto fail_msix_alloc;
5586                 }
5587
5588                 /* TC, queue mapping */
5589                 memset(&ctxt, 0, sizeof(ctxt));
5590                 vsi->info.valid_sections |=
5591                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5592                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5593                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5594                 rte_memcpy(&ctxt.info, &vsi->info,
5595                         sizeof(struct i40e_aqc_vsi_properties_data));
5596                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5597                                                 I40E_DEFAULT_TCMAP);
5598                 if (ret != I40E_SUCCESS) {
5599                         PMD_DRV_LOG(ERR,
5600                                 "Failed to configure TC queue mapping");
5601                         goto fail_msix_alloc;
5602                 }
5603                 ctxt.seid = vsi->seid;
5604                 ctxt.pf_num = hw->pf_id;
5605                 ctxt.uplink_seid = vsi->uplink_seid;
5606                 ctxt.vf_num = 0;
5607
5608                 /* Update VSI parameters */
5609                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5610                 if (ret != I40E_SUCCESS) {
5611                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5612                         goto fail_msix_alloc;
5613                 }
5614
5615                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5616                                                 sizeof(vsi->info.tc_mapping));
5617                 rte_memcpy(&vsi->info.queue_mapping,
5618                                 &ctxt.info.queue_mapping,
5619                         sizeof(vsi->info.queue_mapping));
5620                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5621                 vsi->info.valid_sections = 0;
5622
5623                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5624                                 ETH_ADDR_LEN);
5625
5626                 /**
5627                  * Updating default filter settings are necessary to prevent
5628                  * reception of tagged packets.
5629                  * Some old firmware configurations load a default macvlan
5630                  * filter which accepts both tagged and untagged packets.
5631                  * The updating is to use a normal filter instead if needed.
5632                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5633                  * The firmware with correct configurations load the default
5634                  * macvlan filter which is expected and cannot be removed.
5635                  */
5636                 i40e_update_default_filter_setting(vsi);
5637                 i40e_config_qinq(hw, vsi);
5638         } else if (type == I40E_VSI_SRIOV) {
5639                 memset(&ctxt, 0, sizeof(ctxt));
5640                 /**
5641                  * For other VSI, the uplink_seid equals to uplink VSI's
5642                  * uplink_seid since they share same VEB
5643                  */
5644                 if (uplink_vsi == NULL)
5645                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5646                 else
5647                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5648                 ctxt.pf_num = hw->pf_id;
5649                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5650                 ctxt.uplink_seid = vsi->uplink_seid;
5651                 ctxt.connection_type = 0x1;
5652                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5653
5654                 /* Use the VEB configuration if FW >= v5.0 */
5655                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5656                         /* Configure switch ID */
5657                         ctxt.info.valid_sections |=
5658                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5659                         ctxt.info.switch_id =
5660                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5661                 }
5662
5663                 /* Configure port/vlan */
5664                 ctxt.info.valid_sections |=
5665                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5666                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5667                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5668                                                 hw->func_caps.enabled_tcmap);
5669                 if (ret != I40E_SUCCESS) {
5670                         PMD_DRV_LOG(ERR,
5671                                 "Failed to configure TC queue mapping");
5672                         goto fail_msix_alloc;
5673                 }
5674
5675                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5676                 ctxt.info.valid_sections |=
5677                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5678                 /**
5679                  * Since VSI is not created yet, only configure parameter,
5680                  * will add vsi below.
5681                  */
5682
5683                 i40e_config_qinq(hw, vsi);
5684         } else if (type == I40E_VSI_VMDQ2) {
5685                 memset(&ctxt, 0, sizeof(ctxt));
5686                 /*
5687                  * For other VSI, the uplink_seid equals to uplink VSI's
5688                  * uplink_seid since they share same VEB
5689                  */
5690                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5691                 ctxt.pf_num = hw->pf_id;
5692                 ctxt.vf_num = 0;
5693                 ctxt.uplink_seid = vsi->uplink_seid;
5694                 ctxt.connection_type = 0x1;
5695                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5696
5697                 ctxt.info.valid_sections |=
5698                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5699                 /* user_param carries flag to enable loop back */
5700                 if (user_param) {
5701                         ctxt.info.switch_id =
5702                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5703                         ctxt.info.switch_id |=
5704                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5705                 }
5706
5707                 /* Configure port/vlan */
5708                 ctxt.info.valid_sections |=
5709                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5710                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5711                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5712                                                 I40E_DEFAULT_TCMAP);
5713                 if (ret != I40E_SUCCESS) {
5714                         PMD_DRV_LOG(ERR,
5715                                 "Failed to configure TC queue mapping");
5716                         goto fail_msix_alloc;
5717                 }
5718                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5719                 ctxt.info.valid_sections |=
5720                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5721         } else if (type == I40E_VSI_FDIR) {
5722                 memset(&ctxt, 0, sizeof(ctxt));
5723                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5724                 ctxt.pf_num = hw->pf_id;
5725                 ctxt.vf_num = 0;
5726                 ctxt.uplink_seid = vsi->uplink_seid;
5727                 ctxt.connection_type = 0x1;     /* regular data port */
5728                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5729                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5730                                                 I40E_DEFAULT_TCMAP);
5731                 if (ret != I40E_SUCCESS) {
5732                         PMD_DRV_LOG(ERR,
5733                                 "Failed to configure TC queue mapping.");
5734                         goto fail_msix_alloc;
5735                 }
5736                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5737                 ctxt.info.valid_sections |=
5738                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5739         } else {
5740                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5741                 goto fail_msix_alloc;
5742         }
5743
5744         if (vsi->type != I40E_VSI_MAIN) {
5745                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5746                 if (ret != I40E_SUCCESS) {
5747                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5748                                     hw->aq.asq_last_status);
5749                         goto fail_msix_alloc;
5750                 }
5751                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5752                 vsi->info.valid_sections = 0;
5753                 vsi->seid = ctxt.seid;
5754                 vsi->vsi_id = ctxt.vsi_number;
5755                 vsi->sib_vsi_list.vsi = vsi;
5756                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5757                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5758                                           &vsi->sib_vsi_list, list);
5759                 } else {
5760                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5761                                           &vsi->sib_vsi_list, list);
5762                 }
5763         }
5764
5765         /* MAC/VLAN configuration */
5766         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5767         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5768
5769         ret = i40e_vsi_add_mac(vsi, &filter);
5770         if (ret != I40E_SUCCESS) {
5771                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5772                 goto fail_msix_alloc;
5773         }
5774
5775         /* Get VSI BW information */
5776         i40e_vsi_get_bw_config(vsi);
5777         return vsi;
5778 fail_msix_alloc:
5779         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5780 fail_queue_alloc:
5781         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5782 fail_mem:
5783         rte_free(vsi);
5784         return NULL;
5785 }
5786
5787 /* Configure vlan filter on or off */
5788 int
5789 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5790 {
5791         int i, num;
5792         struct i40e_mac_filter *f;
5793         void *temp;
5794         struct i40e_mac_filter_info *mac_filter;
5795         enum rte_mac_filter_type desired_filter;
5796         int ret = I40E_SUCCESS;
5797
5798         if (on) {
5799                 /* Filter to match MAC and VLAN */
5800                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5801         } else {
5802                 /* Filter to match only MAC */
5803                 desired_filter = RTE_MAC_PERFECT_MATCH;
5804         }
5805
5806         num = vsi->mac_num;
5807
5808         mac_filter = rte_zmalloc("mac_filter_info_data",
5809                                  num * sizeof(*mac_filter), 0);
5810         if (mac_filter == NULL) {
5811                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5812                 return I40E_ERR_NO_MEMORY;
5813         }
5814
5815         i = 0;
5816
5817         /* Remove all existing mac */
5818         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5819                 mac_filter[i] = f->mac_info;
5820                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5821                 if (ret) {
5822                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5823                                     on ? "enable" : "disable");
5824                         goto DONE;
5825                 }
5826                 i++;
5827         }
5828
5829         /* Override with new filter */
5830         for (i = 0; i < num; i++) {
5831                 mac_filter[i].filter_type = desired_filter;
5832                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5833                 if (ret) {
5834                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5835                                     on ? "enable" : "disable");
5836                         goto DONE;
5837                 }
5838         }
5839
5840 DONE:
5841         rte_free(mac_filter);
5842         return ret;
5843 }
5844
5845 /* Configure vlan stripping on or off */
5846 int
5847 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5848 {
5849         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5850         struct i40e_vsi_context ctxt;
5851         uint8_t vlan_flags;
5852         int ret = I40E_SUCCESS;
5853
5854         /* Check if it has been already on or off */
5855         if (vsi->info.valid_sections &
5856                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5857                 if (on) {
5858                         if ((vsi->info.port_vlan_flags &
5859                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5860                                 return 0; /* already on */
5861                 } else {
5862                         if ((vsi->info.port_vlan_flags &
5863                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5864                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5865                                 return 0; /* already off */
5866                 }
5867         }
5868
5869         if (on)
5870                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5871         else
5872                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5873         vsi->info.valid_sections =
5874                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5875         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5876         vsi->info.port_vlan_flags |= vlan_flags;
5877         ctxt.seid = vsi->seid;
5878         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5879         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5880         if (ret)
5881                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5882                             on ? "enable" : "disable");
5883
5884         return ret;
5885 }
5886
5887 static int
5888 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5889 {
5890         struct rte_eth_dev_data *data = dev->data;
5891         int ret;
5892         int mask = 0;
5893
5894         /* Apply vlan offload setting */
5895         mask = ETH_VLAN_STRIP_MASK |
5896                ETH_VLAN_FILTER_MASK |
5897                ETH_VLAN_EXTEND_MASK;
5898         ret = i40e_vlan_offload_set(dev, mask);
5899         if (ret) {
5900                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5901                 return ret;
5902         }
5903
5904         /* Apply pvid setting */
5905         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5906                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5907         if (ret)
5908                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5909
5910         return ret;
5911 }
5912
5913 static int
5914 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5915 {
5916         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5917
5918         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5919 }
5920
5921 static int
5922 i40e_update_flow_control(struct i40e_hw *hw)
5923 {
5924 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5925         struct i40e_link_status link_status;
5926         uint32_t rxfc = 0, txfc = 0, reg;
5927         uint8_t an_info;
5928         int ret;
5929
5930         memset(&link_status, 0, sizeof(link_status));
5931         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5932         if (ret != I40E_SUCCESS) {
5933                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5934                 goto write_reg; /* Disable flow control */
5935         }
5936
5937         an_info = hw->phy.link_info.an_info;
5938         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5939                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5940                 ret = I40E_ERR_NOT_READY;
5941                 goto write_reg; /* Disable flow control */
5942         }
5943         /**
5944          * If link auto negotiation is enabled, flow control needs to
5945          * be configured according to it
5946          */
5947         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5948         case I40E_LINK_PAUSE_RXTX:
5949                 rxfc = 1;
5950                 txfc = 1;
5951                 hw->fc.current_mode = I40E_FC_FULL;
5952                 break;
5953         case I40E_AQ_LINK_PAUSE_RX:
5954                 rxfc = 1;
5955                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5956                 break;
5957         case I40E_AQ_LINK_PAUSE_TX:
5958                 txfc = 1;
5959                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5960                 break;
5961         default:
5962                 hw->fc.current_mode = I40E_FC_NONE;
5963                 break;
5964         }
5965
5966 write_reg:
5967         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5968                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5969         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5970         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5971         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5972         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5973
5974         return ret;
5975 }
5976
5977 /* PF setup */
5978 static int
5979 i40e_pf_setup(struct i40e_pf *pf)
5980 {
5981         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5982         struct i40e_filter_control_settings settings;
5983         struct i40e_vsi *vsi;
5984         int ret;
5985
5986         /* Clear all stats counters */
5987         pf->offset_loaded = FALSE;
5988         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5989         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5990         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5991         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5992
5993         ret = i40e_pf_get_switch_config(pf);
5994         if (ret != I40E_SUCCESS) {
5995                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5996                 return ret;
5997         }
5998
5999         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6000         if (ret)
6001                 PMD_INIT_LOG(WARNING,
6002                         "failed to allocate switch domain for device %d", ret);
6003
6004         if (pf->flags & I40E_FLAG_FDIR) {
6005                 /* make queue allocated first, let FDIR use queue pair 0*/
6006                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6007                 if (ret != I40E_FDIR_QUEUE_ID) {
6008                         PMD_DRV_LOG(ERR,
6009                                 "queue allocation fails for FDIR: ret =%d",
6010                                 ret);
6011                         pf->flags &= ~I40E_FLAG_FDIR;
6012                 }
6013         }
6014         /*  main VSI setup */
6015         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6016         if (!vsi) {
6017                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6018                 return I40E_ERR_NOT_READY;
6019         }
6020         pf->main_vsi = vsi;
6021
6022         /* Configure filter control */
6023         memset(&settings, 0, sizeof(settings));
6024         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6025                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6026         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6027                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6028         else {
6029                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6030                         hw->func_caps.rss_table_size);
6031                 return I40E_ERR_PARAM;
6032         }
6033         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6034                 hw->func_caps.rss_table_size);
6035         pf->hash_lut_size = hw->func_caps.rss_table_size;
6036
6037         /* Enable ethtype and macvlan filters */
6038         settings.enable_ethtype = TRUE;
6039         settings.enable_macvlan = TRUE;
6040         ret = i40e_set_filter_control(hw, &settings);
6041         if (ret)
6042                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6043                                                                 ret);
6044
6045         /* Update flow control according to the auto negotiation */
6046         i40e_update_flow_control(hw);
6047
6048         return I40E_SUCCESS;
6049 }
6050
6051 int
6052 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6053 {
6054         uint32_t reg;
6055         uint16_t j;
6056
6057         /**
6058          * Set or clear TX Queue Disable flags,
6059          * which is required by hardware.
6060          */
6061         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6062         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6063
6064         /* Wait until the request is finished */
6065         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6066                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6067                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6068                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6069                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6070                                                         & 0x1))) {
6071                         break;
6072                 }
6073         }
6074         if (on) {
6075                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6076                         return I40E_SUCCESS; /* already on, skip next steps */
6077
6078                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6079                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6080         } else {
6081                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6082                         return I40E_SUCCESS; /* already off, skip next steps */
6083                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6084         }
6085         /* Write the register */
6086         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6087         /* Check the result */
6088         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6089                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6090                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6091                 if (on) {
6092                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6093                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6094                                 break;
6095                 } else {
6096                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6097                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6098                                 break;
6099                 }
6100         }
6101         /* Check if it is timeout */
6102         if (j >= I40E_CHK_Q_ENA_COUNT) {
6103                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6104                             (on ? "enable" : "disable"), q_idx);
6105                 return I40E_ERR_TIMEOUT;
6106         }
6107
6108         return I40E_SUCCESS;
6109 }
6110
6111 /* Swith on or off the tx queues */
6112 static int
6113 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6114 {
6115         struct rte_eth_dev_data *dev_data = pf->dev_data;
6116         struct i40e_tx_queue *txq;
6117         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6118         uint16_t i;
6119         int ret;
6120
6121         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6122                 txq = dev_data->tx_queues[i];
6123                 /* Don't operate the queue if not configured or
6124                  * if starting only per queue */
6125                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6126                         continue;
6127                 if (on)
6128                         ret = i40e_dev_tx_queue_start(dev, i);
6129                 else
6130                         ret = i40e_dev_tx_queue_stop(dev, i);
6131                 if ( ret != I40E_SUCCESS)
6132                         return ret;
6133         }
6134
6135         return I40E_SUCCESS;
6136 }
6137
6138 int
6139 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6140 {
6141         uint32_t reg;
6142         uint16_t j;
6143
6144         /* Wait until the request is finished */
6145         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6146                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6147                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6148                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6149                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6150                         break;
6151         }
6152
6153         if (on) {
6154                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6155                         return I40E_SUCCESS; /* Already on, skip next steps */
6156                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6157         } else {
6158                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6159                         return I40E_SUCCESS; /* Already off, skip next steps */
6160                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6161         }
6162
6163         /* Write the register */
6164         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6165         /* Check the result */
6166         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6167                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6168                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6169                 if (on) {
6170                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6171                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6172                                 break;
6173                 } else {
6174                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6175                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6176                                 break;
6177                 }
6178         }
6179
6180         /* Check if it is timeout */
6181         if (j >= I40E_CHK_Q_ENA_COUNT) {
6182                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6183                             (on ? "enable" : "disable"), q_idx);
6184                 return I40E_ERR_TIMEOUT;
6185         }
6186
6187         return I40E_SUCCESS;
6188 }
6189 /* Switch on or off the rx queues */
6190 static int
6191 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6192 {
6193         struct rte_eth_dev_data *dev_data = pf->dev_data;
6194         struct i40e_rx_queue *rxq;
6195         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6196         uint16_t i;
6197         int ret;
6198
6199         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6200                 rxq = dev_data->rx_queues[i];
6201                 /* Don't operate the queue if not configured or
6202                  * if starting only per queue */
6203                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6204                         continue;
6205                 if (on)
6206                         ret = i40e_dev_rx_queue_start(dev, i);
6207                 else
6208                         ret = i40e_dev_rx_queue_stop(dev, i);
6209                 if (ret != I40E_SUCCESS)
6210                         return ret;
6211         }
6212
6213         return I40E_SUCCESS;
6214 }
6215
6216 /* Switch on or off all the rx/tx queues */
6217 int
6218 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6219 {
6220         int ret;
6221
6222         if (on) {
6223                 /* enable rx queues before enabling tx queues */
6224                 ret = i40e_dev_switch_rx_queues(pf, on);
6225                 if (ret) {
6226                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6227                         return ret;
6228                 }
6229                 ret = i40e_dev_switch_tx_queues(pf, on);
6230         } else {
6231                 /* Stop tx queues before stopping rx queues */
6232                 ret = i40e_dev_switch_tx_queues(pf, on);
6233                 if (ret) {
6234                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6235                         return ret;
6236                 }
6237                 ret = i40e_dev_switch_rx_queues(pf, on);
6238         }
6239
6240         return ret;
6241 }
6242
6243 /* Initialize VSI for TX */
6244 static int
6245 i40e_dev_tx_init(struct i40e_pf *pf)
6246 {
6247         struct rte_eth_dev_data *data = pf->dev_data;
6248         uint16_t i;
6249         uint32_t ret = I40E_SUCCESS;
6250         struct i40e_tx_queue *txq;
6251
6252         for (i = 0; i < data->nb_tx_queues; i++) {
6253                 txq = data->tx_queues[i];
6254                 if (!txq || !txq->q_set)
6255                         continue;
6256                 ret = i40e_tx_queue_init(txq);
6257                 if (ret != I40E_SUCCESS)
6258                         break;
6259         }
6260         if (ret == I40E_SUCCESS)
6261                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6262                                      ->eth_dev);
6263
6264         return ret;
6265 }
6266
6267 /* Initialize VSI for RX */
6268 static int
6269 i40e_dev_rx_init(struct i40e_pf *pf)
6270 {
6271         struct rte_eth_dev_data *data = pf->dev_data;
6272         int ret = I40E_SUCCESS;
6273         uint16_t i;
6274         struct i40e_rx_queue *rxq;
6275
6276         i40e_pf_config_mq_rx(pf);
6277         for (i = 0; i < data->nb_rx_queues; i++) {
6278                 rxq = data->rx_queues[i];
6279                 if (!rxq || !rxq->q_set)
6280                         continue;
6281
6282                 ret = i40e_rx_queue_init(rxq);
6283                 if (ret != I40E_SUCCESS) {
6284                         PMD_DRV_LOG(ERR,
6285                                 "Failed to do RX queue initialization");
6286                         break;
6287                 }
6288         }
6289         if (ret == I40E_SUCCESS)
6290                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6291                                      ->eth_dev);
6292
6293         return ret;
6294 }
6295
6296 static int
6297 i40e_dev_rxtx_init(struct i40e_pf *pf)
6298 {
6299         int err;
6300
6301         err = i40e_dev_tx_init(pf);
6302         if (err) {
6303                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6304                 return err;
6305         }
6306         err = i40e_dev_rx_init(pf);
6307         if (err) {
6308                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6309                 return err;
6310         }
6311
6312         return err;
6313 }
6314
6315 static int
6316 i40e_vmdq_setup(struct rte_eth_dev *dev)
6317 {
6318         struct rte_eth_conf *conf = &dev->data->dev_conf;
6319         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6320         int i, err, conf_vsis, j, loop;
6321         struct i40e_vsi *vsi;
6322         struct i40e_vmdq_info *vmdq_info;
6323         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6324         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6325
6326         /*
6327          * Disable interrupt to avoid message from VF. Furthermore, it will
6328          * avoid race condition in VSI creation/destroy.
6329          */
6330         i40e_pf_disable_irq0(hw);
6331
6332         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6333                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6334                 return -ENOTSUP;
6335         }
6336
6337         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6338         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6339                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6340                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6341                         pf->max_nb_vmdq_vsi);
6342                 return -ENOTSUP;
6343         }
6344
6345         if (pf->vmdq != NULL) {
6346                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6347                 return 0;
6348         }
6349
6350         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6351                                 sizeof(*vmdq_info) * conf_vsis, 0);
6352
6353         if (pf->vmdq == NULL) {
6354                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6355                 return -ENOMEM;
6356         }
6357
6358         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6359
6360         /* Create VMDQ VSI */
6361         for (i = 0; i < conf_vsis; i++) {
6362                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6363                                 vmdq_conf->enable_loop_back);
6364                 if (vsi == NULL) {
6365                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6366                         err = -1;
6367                         goto err_vsi_setup;
6368                 }
6369                 vmdq_info = &pf->vmdq[i];
6370                 vmdq_info->pf = pf;
6371                 vmdq_info->vsi = vsi;
6372         }
6373         pf->nb_cfg_vmdq_vsi = conf_vsis;
6374
6375         /* Configure Vlan */
6376         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6377         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6378                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6379                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6380                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6381                                         vmdq_conf->pool_map[i].vlan_id, j);
6382
6383                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6384                                                 vmdq_conf->pool_map[i].vlan_id);
6385                                 if (err) {
6386                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6387                                         err = -1;
6388                                         goto err_vsi_setup;
6389                                 }
6390                         }
6391                 }
6392         }
6393
6394         i40e_pf_enable_irq0(hw);
6395
6396         return 0;
6397
6398 err_vsi_setup:
6399         for (i = 0; i < conf_vsis; i++)
6400                 if (pf->vmdq[i].vsi == NULL)
6401                         break;
6402                 else
6403                         i40e_vsi_release(pf->vmdq[i].vsi);
6404
6405         rte_free(pf->vmdq);
6406         pf->vmdq = NULL;
6407         i40e_pf_enable_irq0(hw);
6408         return err;
6409 }
6410
6411 static void
6412 i40e_stat_update_32(struct i40e_hw *hw,
6413                    uint32_t reg,
6414                    bool offset_loaded,
6415                    uint64_t *offset,
6416                    uint64_t *stat)
6417 {
6418         uint64_t new_data;
6419
6420         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6421         if (!offset_loaded)
6422                 *offset = new_data;
6423
6424         if (new_data >= *offset)
6425                 *stat = (uint64_t)(new_data - *offset);
6426         else
6427                 *stat = (uint64_t)((new_data +
6428                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6429 }
6430
6431 static void
6432 i40e_stat_update_48(struct i40e_hw *hw,
6433                    uint32_t hireg,
6434                    uint32_t loreg,
6435                    bool offset_loaded,
6436                    uint64_t *offset,
6437                    uint64_t *stat)
6438 {
6439         uint64_t new_data;
6440
6441         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6442         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6443                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6444
6445         if (!offset_loaded)
6446                 *offset = new_data;
6447
6448         if (new_data >= *offset)
6449                 *stat = new_data - *offset;
6450         else
6451                 *stat = (uint64_t)((new_data +
6452                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6453
6454         *stat &= I40E_48_BIT_MASK;
6455 }
6456
6457 /* Disable IRQ0 */
6458 void
6459 i40e_pf_disable_irq0(struct i40e_hw *hw)
6460 {
6461         /* Disable all interrupt types */
6462         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6463                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6464         I40E_WRITE_FLUSH(hw);
6465 }
6466
6467 /* Enable IRQ0 */
6468 void
6469 i40e_pf_enable_irq0(struct i40e_hw *hw)
6470 {
6471         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6472                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6473                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6474                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6475         I40E_WRITE_FLUSH(hw);
6476 }
6477
6478 static void
6479 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6480 {
6481         /* read pending request and disable first */
6482         i40e_pf_disable_irq0(hw);
6483         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6484         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6485                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6486
6487         if (no_queue)
6488                 /* Link no queues with irq0 */
6489                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6490                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6491 }
6492
6493 static void
6494 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6495 {
6496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6498         int i;
6499         uint16_t abs_vf_id;
6500         uint32_t index, offset, val;
6501
6502         if (!pf->vfs)
6503                 return;
6504         /**
6505          * Try to find which VF trigger a reset, use absolute VF id to access
6506          * since the reg is global register.
6507          */
6508         for (i = 0; i < pf->vf_num; i++) {
6509                 abs_vf_id = hw->func_caps.vf_base_id + i;
6510                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6511                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6512                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6513                 /* VFR event occurred */
6514                 if (val & (0x1 << offset)) {
6515                         int ret;
6516
6517                         /* Clear the event first */
6518                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6519                                                         (0x1 << offset));
6520                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6521                         /**
6522                          * Only notify a VF reset event occurred,
6523                          * don't trigger another SW reset
6524                          */
6525                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6526                         if (ret != I40E_SUCCESS)
6527                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6528                 }
6529         }
6530 }
6531
6532 static void
6533 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6534 {
6535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6536         int i;
6537
6538         for (i = 0; i < pf->vf_num; i++)
6539                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6540 }
6541
6542 static void
6543 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6544 {
6545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6546         struct i40e_arq_event_info info;
6547         uint16_t pending, opcode;
6548         int ret;
6549
6550         info.buf_len = I40E_AQ_BUF_SZ;
6551         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6552         if (!info.msg_buf) {
6553                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6554                 return;
6555         }
6556
6557         pending = 1;
6558         while (pending) {
6559                 ret = i40e_clean_arq_element(hw, &info, &pending);
6560
6561                 if (ret != I40E_SUCCESS) {
6562                         PMD_DRV_LOG(INFO,
6563                                 "Failed to read msg from AdminQ, aq_err: %u",
6564                                 hw->aq.asq_last_status);
6565                         break;
6566                 }
6567                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6568
6569                 switch (opcode) {
6570                 case i40e_aqc_opc_send_msg_to_pf:
6571                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6572                         i40e_pf_host_handle_vf_msg(dev,
6573                                         rte_le_to_cpu_16(info.desc.retval),
6574                                         rte_le_to_cpu_32(info.desc.cookie_high),
6575                                         rte_le_to_cpu_32(info.desc.cookie_low),
6576                                         info.msg_buf,
6577                                         info.msg_len);
6578                         break;
6579                 case i40e_aqc_opc_get_link_status:
6580                         ret = i40e_dev_link_update(dev, 0);
6581                         if (!ret)
6582                                 _rte_eth_dev_callback_process(dev,
6583                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6584                         break;
6585                 default:
6586                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6587                                     opcode);
6588                         break;
6589                 }
6590         }
6591         rte_free(info.msg_buf);
6592 }
6593
6594 /**
6595  * Interrupt handler triggered by NIC  for handling
6596  * specific interrupt.
6597  *
6598  * @param handle
6599  *  Pointer to interrupt handle.
6600  * @param param
6601  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6602  *
6603  * @return
6604  *  void
6605  */
6606 static void
6607 i40e_dev_interrupt_handler(void *param)
6608 {
6609         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6610         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6611         uint32_t icr0;
6612
6613         /* Disable interrupt */
6614         i40e_pf_disable_irq0(hw);
6615
6616         /* read out interrupt causes */
6617         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6618
6619         /* No interrupt event indicated */
6620         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6621                 PMD_DRV_LOG(INFO, "No interrupt event");
6622                 goto done;
6623         }
6624         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6625                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6626         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6627                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6628         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6629                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6630         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6631                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6632         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6633                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6634         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6635                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6636         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6637                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6638
6639         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6640                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6641                 i40e_dev_handle_vfr_event(dev);
6642         }
6643         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6644                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6645                 i40e_dev_handle_aq_msg(dev);
6646         }
6647
6648 done:
6649         /* Enable interrupt */
6650         i40e_pf_enable_irq0(hw);
6651 }
6652
6653 static void
6654 i40e_dev_alarm_handler(void *param)
6655 {
6656         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658         uint32_t icr0;
6659
6660         /* Disable interrupt */
6661         i40e_pf_disable_irq0(hw);
6662
6663         /* read out interrupt causes */
6664         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6665
6666         /* No interrupt event indicated */
6667         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6668                 goto done;
6669         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6670                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6671         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6672                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6673         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6674                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6675         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6676                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6677         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6678                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6679         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6680                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6681         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6682                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6683
6684         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6685                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6686                 i40e_dev_handle_vfr_event(dev);
6687         }
6688         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6689                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6690                 i40e_dev_handle_aq_msg(dev);
6691         }
6692
6693 done:
6694         /* Enable interrupt */
6695         i40e_pf_enable_irq0(hw);
6696         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6697                           i40e_dev_alarm_handler, dev);
6698 }
6699
6700 int
6701 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6702                          struct i40e_macvlan_filter *filter,
6703                          int total)
6704 {
6705         int ele_num, ele_buff_size;
6706         int num, actual_num, i;
6707         uint16_t flags;
6708         int ret = I40E_SUCCESS;
6709         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6710         struct i40e_aqc_add_macvlan_element_data *req_list;
6711
6712         if (filter == NULL  || total == 0)
6713                 return I40E_ERR_PARAM;
6714         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6715         ele_buff_size = hw->aq.asq_buf_size;
6716
6717         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6718         if (req_list == NULL) {
6719                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6720                 return I40E_ERR_NO_MEMORY;
6721         }
6722
6723         num = 0;
6724         do {
6725                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6726                 memset(req_list, 0, ele_buff_size);
6727
6728                 for (i = 0; i < actual_num; i++) {
6729                         rte_memcpy(req_list[i].mac_addr,
6730                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6731                         req_list[i].vlan_tag =
6732                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6733
6734                         switch (filter[num + i].filter_type) {
6735                         case RTE_MAC_PERFECT_MATCH:
6736                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6737                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6738                                 break;
6739                         case RTE_MACVLAN_PERFECT_MATCH:
6740                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6741                                 break;
6742                         case RTE_MAC_HASH_MATCH:
6743                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6744                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6745                                 break;
6746                         case RTE_MACVLAN_HASH_MATCH:
6747                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6748                                 break;
6749                         default:
6750                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6751                                 ret = I40E_ERR_PARAM;
6752                                 goto DONE;
6753                         }
6754
6755                         req_list[i].queue_number = 0;
6756
6757                         req_list[i].flags = rte_cpu_to_le_16(flags);
6758                 }
6759
6760                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6761                                                 actual_num, NULL);
6762                 if (ret != I40E_SUCCESS) {
6763                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6764                         goto DONE;
6765                 }
6766                 num += actual_num;
6767         } while (num < total);
6768
6769 DONE:
6770         rte_free(req_list);
6771         return ret;
6772 }
6773
6774 int
6775 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6776                             struct i40e_macvlan_filter *filter,
6777                             int total)
6778 {
6779         int ele_num, ele_buff_size;
6780         int num, actual_num, i;
6781         uint16_t flags;
6782         int ret = I40E_SUCCESS;
6783         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6784         struct i40e_aqc_remove_macvlan_element_data *req_list;
6785
6786         if (filter == NULL  || total == 0)
6787                 return I40E_ERR_PARAM;
6788
6789         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6790         ele_buff_size = hw->aq.asq_buf_size;
6791
6792         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6793         if (req_list == NULL) {
6794                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6795                 return I40E_ERR_NO_MEMORY;
6796         }
6797
6798         num = 0;
6799         do {
6800                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6801                 memset(req_list, 0, ele_buff_size);
6802
6803                 for (i = 0; i < actual_num; i++) {
6804                         rte_memcpy(req_list[i].mac_addr,
6805                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6806                         req_list[i].vlan_tag =
6807                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6808
6809                         switch (filter[num + i].filter_type) {
6810                         case RTE_MAC_PERFECT_MATCH:
6811                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6812                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6813                                 break;
6814                         case RTE_MACVLAN_PERFECT_MATCH:
6815                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6816                                 break;
6817                         case RTE_MAC_HASH_MATCH:
6818                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6819                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6820                                 break;
6821                         case RTE_MACVLAN_HASH_MATCH:
6822                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6823                                 break;
6824                         default:
6825                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6826                                 ret = I40E_ERR_PARAM;
6827                                 goto DONE;
6828                         }
6829                         req_list[i].flags = rte_cpu_to_le_16(flags);
6830                 }
6831
6832                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6833                                                 actual_num, NULL);
6834                 if (ret != I40E_SUCCESS) {
6835                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6836                         goto DONE;
6837                 }
6838                 num += actual_num;
6839         } while (num < total);
6840
6841 DONE:
6842         rte_free(req_list);
6843         return ret;
6844 }
6845
6846 /* Find out specific MAC filter */
6847 static struct i40e_mac_filter *
6848 i40e_find_mac_filter(struct i40e_vsi *vsi,
6849                          struct ether_addr *macaddr)
6850 {
6851         struct i40e_mac_filter *f;
6852
6853         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6854                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6855                         return f;
6856         }
6857
6858         return NULL;
6859 }
6860
6861 static bool
6862 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6863                          uint16_t vlan_id)
6864 {
6865         uint32_t vid_idx, vid_bit;
6866
6867         if (vlan_id > ETH_VLAN_ID_MAX)
6868                 return 0;
6869
6870         vid_idx = I40E_VFTA_IDX(vlan_id);
6871         vid_bit = I40E_VFTA_BIT(vlan_id);
6872
6873         if (vsi->vfta[vid_idx] & vid_bit)
6874                 return 1;
6875         else
6876                 return 0;
6877 }
6878
6879 static void
6880 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6881                        uint16_t vlan_id, bool on)
6882 {
6883         uint32_t vid_idx, vid_bit;
6884
6885         vid_idx = I40E_VFTA_IDX(vlan_id);
6886         vid_bit = I40E_VFTA_BIT(vlan_id);
6887
6888         if (on)
6889                 vsi->vfta[vid_idx] |= vid_bit;
6890         else
6891                 vsi->vfta[vid_idx] &= ~vid_bit;
6892 }
6893
6894 void
6895 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6896                      uint16_t vlan_id, bool on)
6897 {
6898         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6899         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6900         int ret;
6901
6902         if (vlan_id > ETH_VLAN_ID_MAX)
6903                 return;
6904
6905         i40e_store_vlan_filter(vsi, vlan_id, on);
6906
6907         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6908                 return;
6909
6910         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6911
6912         if (on) {
6913                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6914                                        &vlan_data, 1, NULL);
6915                 if (ret != I40E_SUCCESS)
6916                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6917         } else {
6918                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6919                                           &vlan_data, 1, NULL);
6920                 if (ret != I40E_SUCCESS)
6921                         PMD_DRV_LOG(ERR,
6922                                     "Failed to remove vlan filter");
6923         }
6924 }
6925
6926 /**
6927  * Find all vlan options for specific mac addr,
6928  * return with actual vlan found.
6929  */
6930 int
6931 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6932                            struct i40e_macvlan_filter *mv_f,
6933                            int num, struct ether_addr *addr)
6934 {
6935         int i;
6936         uint32_t j, k;
6937
6938         /**
6939          * Not to use i40e_find_vlan_filter to decrease the loop time,
6940          * although the code looks complex.
6941           */
6942         if (num < vsi->vlan_num)
6943                 return I40E_ERR_PARAM;
6944
6945         i = 0;
6946         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6947                 if (vsi->vfta[j]) {
6948                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6949                                 if (vsi->vfta[j] & (1 << k)) {
6950                                         if (i > num - 1) {
6951                                                 PMD_DRV_LOG(ERR,
6952                                                         "vlan number doesn't match");
6953                                                 return I40E_ERR_PARAM;
6954                                         }
6955                                         rte_memcpy(&mv_f[i].macaddr,
6956                                                         addr, ETH_ADDR_LEN);
6957                                         mv_f[i].vlan_id =
6958                                                 j * I40E_UINT32_BIT_SIZE + k;
6959                                         i++;
6960                                 }
6961                         }
6962                 }
6963         }
6964         return I40E_SUCCESS;
6965 }
6966
6967 static inline int
6968 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6969                            struct i40e_macvlan_filter *mv_f,
6970                            int num,
6971                            uint16_t vlan)
6972 {
6973         int i = 0;
6974         struct i40e_mac_filter *f;
6975
6976         if (num < vsi->mac_num)
6977                 return I40E_ERR_PARAM;
6978
6979         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6980                 if (i > num - 1) {
6981                         PMD_DRV_LOG(ERR, "buffer number not match");
6982                         return I40E_ERR_PARAM;
6983                 }
6984                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6985                                 ETH_ADDR_LEN);
6986                 mv_f[i].vlan_id = vlan;
6987                 mv_f[i].filter_type = f->mac_info.filter_type;
6988                 i++;
6989         }
6990
6991         return I40E_SUCCESS;
6992 }
6993
6994 static int
6995 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6996 {
6997         int i, j, num;
6998         struct i40e_mac_filter *f;
6999         struct i40e_macvlan_filter *mv_f;
7000         int ret = I40E_SUCCESS;
7001
7002         if (vsi == NULL || vsi->mac_num == 0)
7003                 return I40E_ERR_PARAM;
7004
7005         /* Case that no vlan is set */
7006         if (vsi->vlan_num == 0)
7007                 num = vsi->mac_num;
7008         else
7009                 num = vsi->mac_num * vsi->vlan_num;
7010
7011         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7012         if (mv_f == NULL) {
7013                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7014                 return I40E_ERR_NO_MEMORY;
7015         }
7016
7017         i = 0;
7018         if (vsi->vlan_num == 0) {
7019                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7020                         rte_memcpy(&mv_f[i].macaddr,
7021                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7022                         mv_f[i].filter_type = f->mac_info.filter_type;
7023                         mv_f[i].vlan_id = 0;
7024                         i++;
7025                 }
7026         } else {
7027                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7028                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7029                                         vsi->vlan_num, &f->mac_info.mac_addr);
7030                         if (ret != I40E_SUCCESS)
7031                                 goto DONE;
7032                         for (j = i; j < i + vsi->vlan_num; j++)
7033                                 mv_f[j].filter_type = f->mac_info.filter_type;
7034                         i += vsi->vlan_num;
7035                 }
7036         }
7037
7038         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7039 DONE:
7040         rte_free(mv_f);
7041
7042         return ret;
7043 }
7044
7045 int
7046 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7047 {
7048         struct i40e_macvlan_filter *mv_f;
7049         int mac_num;
7050         int ret = I40E_SUCCESS;
7051
7052         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7053                 return I40E_ERR_PARAM;
7054
7055         /* If it's already set, just return */
7056         if (i40e_find_vlan_filter(vsi,vlan))
7057                 return I40E_SUCCESS;
7058
7059         mac_num = vsi->mac_num;
7060
7061         if (mac_num == 0) {
7062                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7063                 return I40E_ERR_PARAM;
7064         }
7065
7066         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7067
7068         if (mv_f == NULL) {
7069                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7070                 return I40E_ERR_NO_MEMORY;
7071         }
7072
7073         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7074
7075         if (ret != I40E_SUCCESS)
7076                 goto DONE;
7077
7078         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7079
7080         if (ret != I40E_SUCCESS)
7081                 goto DONE;
7082
7083         i40e_set_vlan_filter(vsi, vlan, 1);
7084
7085         vsi->vlan_num++;
7086         ret = I40E_SUCCESS;
7087 DONE:
7088         rte_free(mv_f);
7089         return ret;
7090 }
7091
7092 int
7093 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7094 {
7095         struct i40e_macvlan_filter *mv_f;
7096         int mac_num;
7097         int ret = I40E_SUCCESS;
7098
7099         /**
7100          * Vlan 0 is the generic filter for untagged packets
7101          * and can't be removed.
7102          */
7103         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7104                 return I40E_ERR_PARAM;
7105
7106         /* If can't find it, just return */
7107         if (!i40e_find_vlan_filter(vsi, vlan))
7108                 return I40E_ERR_PARAM;
7109
7110         mac_num = vsi->mac_num;
7111
7112         if (mac_num == 0) {
7113                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7114                 return I40E_ERR_PARAM;
7115         }
7116
7117         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7118
7119         if (mv_f == NULL) {
7120                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7121                 return I40E_ERR_NO_MEMORY;
7122         }
7123
7124         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7125
7126         if (ret != I40E_SUCCESS)
7127                 goto DONE;
7128
7129         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7130
7131         if (ret != I40E_SUCCESS)
7132                 goto DONE;
7133
7134         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7135         if (vsi->vlan_num == 1) {
7136                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7137                 if (ret != I40E_SUCCESS)
7138                         goto DONE;
7139
7140                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7141                 if (ret != I40E_SUCCESS)
7142                         goto DONE;
7143         }
7144
7145         i40e_set_vlan_filter(vsi, vlan, 0);
7146
7147         vsi->vlan_num--;
7148         ret = I40E_SUCCESS;
7149 DONE:
7150         rte_free(mv_f);
7151         return ret;
7152 }
7153
7154 int
7155 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7156 {
7157         struct i40e_mac_filter *f;
7158         struct i40e_macvlan_filter *mv_f;
7159         int i, vlan_num = 0;
7160         int ret = I40E_SUCCESS;
7161
7162         /* If it's add and we've config it, return */
7163         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7164         if (f != NULL)
7165                 return I40E_SUCCESS;
7166         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7167                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7168
7169                 /**
7170                  * If vlan_num is 0, that's the first time to add mac,
7171                  * set mask for vlan_id 0.
7172                  */
7173                 if (vsi->vlan_num == 0) {
7174                         i40e_set_vlan_filter(vsi, 0, 1);
7175                         vsi->vlan_num = 1;
7176                 }
7177                 vlan_num = vsi->vlan_num;
7178         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7179                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7180                 vlan_num = 1;
7181
7182         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7183         if (mv_f == NULL) {
7184                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7185                 return I40E_ERR_NO_MEMORY;
7186         }
7187
7188         for (i = 0; i < vlan_num; i++) {
7189                 mv_f[i].filter_type = mac_filter->filter_type;
7190                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7191                                 ETH_ADDR_LEN);
7192         }
7193
7194         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7195                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7196                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7197                                         &mac_filter->mac_addr);
7198                 if (ret != I40E_SUCCESS)
7199                         goto DONE;
7200         }
7201
7202         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7203         if (ret != I40E_SUCCESS)
7204                 goto DONE;
7205
7206         /* Add the mac addr into mac list */
7207         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7208         if (f == NULL) {
7209                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7210                 ret = I40E_ERR_NO_MEMORY;
7211                 goto DONE;
7212         }
7213         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7214                         ETH_ADDR_LEN);
7215         f->mac_info.filter_type = mac_filter->filter_type;
7216         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7217         vsi->mac_num++;
7218
7219         ret = I40E_SUCCESS;
7220 DONE:
7221         rte_free(mv_f);
7222
7223         return ret;
7224 }
7225
7226 int
7227 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7228 {
7229         struct i40e_mac_filter *f;
7230         struct i40e_macvlan_filter *mv_f;
7231         int i, vlan_num;
7232         enum rte_mac_filter_type filter_type;
7233         int ret = I40E_SUCCESS;
7234
7235         /* Can't find it, return an error */
7236         f = i40e_find_mac_filter(vsi, addr);
7237         if (f == NULL)
7238                 return I40E_ERR_PARAM;
7239
7240         vlan_num = vsi->vlan_num;
7241         filter_type = f->mac_info.filter_type;
7242         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7243                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7244                 if (vlan_num == 0) {
7245                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7246                         return I40E_ERR_PARAM;
7247                 }
7248         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7249                         filter_type == RTE_MAC_HASH_MATCH)
7250                 vlan_num = 1;
7251
7252         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7253         if (mv_f == NULL) {
7254                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7255                 return I40E_ERR_NO_MEMORY;
7256         }
7257
7258         for (i = 0; i < vlan_num; i++) {
7259                 mv_f[i].filter_type = filter_type;
7260                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7261                                 ETH_ADDR_LEN);
7262         }
7263         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7264                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7265                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7266                 if (ret != I40E_SUCCESS)
7267                         goto DONE;
7268         }
7269
7270         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7271         if (ret != I40E_SUCCESS)
7272                 goto DONE;
7273
7274         /* Remove the mac addr into mac list */
7275         TAILQ_REMOVE(&vsi->mac_list, f, next);
7276         rte_free(f);
7277         vsi->mac_num--;
7278
7279         ret = I40E_SUCCESS;
7280 DONE:
7281         rte_free(mv_f);
7282         return ret;
7283 }
7284
7285 /* Configure hash enable flags for RSS */
7286 uint64_t
7287 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7288 {
7289         uint64_t hena = 0;
7290         int i;
7291
7292         if (!flags)
7293                 return hena;
7294
7295         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7296                 if (flags & (1ULL << i))
7297                         hena |= adapter->pctypes_tbl[i];
7298         }
7299
7300         return hena;
7301 }
7302
7303 /* Parse the hash enable flags */
7304 uint64_t
7305 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7306 {
7307         uint64_t rss_hf = 0;
7308
7309         if (!flags)
7310                 return rss_hf;
7311         int i;
7312
7313         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7314                 if (flags & adapter->pctypes_tbl[i])
7315                         rss_hf |= (1ULL << i);
7316         }
7317         return rss_hf;
7318 }
7319
7320 /* Disable RSS */
7321 static void
7322 i40e_pf_disable_rss(struct i40e_pf *pf)
7323 {
7324         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7325
7326         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7327         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7328         I40E_WRITE_FLUSH(hw);
7329 }
7330
7331 int
7332 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7333 {
7334         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7335         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7336         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7337                            I40E_VFQF_HKEY_MAX_INDEX :
7338                            I40E_PFQF_HKEY_MAX_INDEX;
7339         int ret = 0;
7340
7341         if (!key || key_len == 0) {
7342                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7343                 return 0;
7344         } else if (key_len != (key_idx + 1) *
7345                 sizeof(uint32_t)) {
7346                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7347                 return -EINVAL;
7348         }
7349
7350         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7351                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7352                         (struct i40e_aqc_get_set_rss_key_data *)key;
7353
7354                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7355                 if (ret)
7356                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7357         } else {
7358                 uint32_t *hash_key = (uint32_t *)key;
7359                 uint16_t i;
7360
7361                 if (vsi->type == I40E_VSI_SRIOV) {
7362                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7363                                 I40E_WRITE_REG(
7364                                         hw,
7365                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7366                                         hash_key[i]);
7367
7368                 } else {
7369                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7370                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7371                                                hash_key[i]);
7372                 }
7373                 I40E_WRITE_FLUSH(hw);
7374         }
7375
7376         return ret;
7377 }
7378
7379 static int
7380 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7381 {
7382         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7383         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7384         uint32_t reg;
7385         int ret;
7386
7387         if (!key || !key_len)
7388                 return -EINVAL;
7389
7390         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7391                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7392                         (struct i40e_aqc_get_set_rss_key_data *)key);
7393                 if (ret) {
7394                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7395                         return ret;
7396                 }
7397         } else {
7398                 uint32_t *key_dw = (uint32_t *)key;
7399                 uint16_t i;
7400
7401                 if (vsi->type == I40E_VSI_SRIOV) {
7402                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7403                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7404                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7405                         }
7406                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7407                                    sizeof(uint32_t);
7408                 } else {
7409                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7410                                 reg = I40E_PFQF_HKEY(i);
7411                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7412                         }
7413                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7414                                    sizeof(uint32_t);
7415                 }
7416         }
7417         return 0;
7418 }
7419
7420 static int
7421 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7422 {
7423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7424         uint64_t hena;
7425         int ret;
7426
7427         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7428                                rss_conf->rss_key_len);
7429         if (ret)
7430                 return ret;
7431
7432         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7433         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7434         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7435         I40E_WRITE_FLUSH(hw);
7436
7437         return 0;
7438 }
7439
7440 static int
7441 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7442                          struct rte_eth_rss_conf *rss_conf)
7443 {
7444         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7445         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7446         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7447         uint64_t hena;
7448
7449         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7450         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7451
7452         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7453                 if (rss_hf != 0) /* Enable RSS */
7454                         return -EINVAL;
7455                 return 0; /* Nothing to do */
7456         }
7457         /* RSS enabled */
7458         if (rss_hf == 0) /* Disable RSS */
7459                 return -EINVAL;
7460
7461         return i40e_hw_rss_hash_set(pf, rss_conf);
7462 }
7463
7464 static int
7465 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7466                            struct rte_eth_rss_conf *rss_conf)
7467 {
7468         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint64_t hena;
7471         int ret;
7472
7473         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7474                          &rss_conf->rss_key_len);
7475         if (ret)
7476                 return ret;
7477
7478         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7479         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7480         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7481
7482         return 0;
7483 }
7484
7485 static int
7486 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7487 {
7488         switch (filter_type) {
7489         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7490                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7491                 break;
7492         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7493                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7494                 break;
7495         case RTE_TUNNEL_FILTER_IMAC_TENID:
7496                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7497                 break;
7498         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7499                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7500                 break;
7501         case ETH_TUNNEL_FILTER_IMAC:
7502                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7503                 break;
7504         case ETH_TUNNEL_FILTER_OIP:
7505                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7506                 break;
7507         case ETH_TUNNEL_FILTER_IIP:
7508                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7509                 break;
7510         default:
7511                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7512                 return -EINVAL;
7513         }
7514
7515         return 0;
7516 }
7517
7518 /* Convert tunnel filter structure */
7519 static int
7520 i40e_tunnel_filter_convert(
7521         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7522         struct i40e_tunnel_filter *tunnel_filter)
7523 {
7524         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7525                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7526         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7527                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7528         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7529         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7530              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7531             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7532                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7533         else
7534                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7535         tunnel_filter->input.flags = cld_filter->element.flags;
7536         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7537         tunnel_filter->queue = cld_filter->element.queue_number;
7538         rte_memcpy(tunnel_filter->input.general_fields,
7539                    cld_filter->general_fields,
7540                    sizeof(cld_filter->general_fields));
7541
7542         return 0;
7543 }
7544
7545 /* Check if there exists the tunnel filter */
7546 struct i40e_tunnel_filter *
7547 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7548                              const struct i40e_tunnel_filter_input *input)
7549 {
7550         int ret;
7551
7552         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7553         if (ret < 0)
7554                 return NULL;
7555
7556         return tunnel_rule->hash_map[ret];
7557 }
7558
7559 /* Add a tunnel filter into the SW list */
7560 static int
7561 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7562                              struct i40e_tunnel_filter *tunnel_filter)
7563 {
7564         struct i40e_tunnel_rule *rule = &pf->tunnel;
7565         int ret;
7566
7567         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7568         if (ret < 0) {
7569                 PMD_DRV_LOG(ERR,
7570                             "Failed to insert tunnel filter to hash table %d!",
7571                             ret);
7572                 return ret;
7573         }
7574         rule->hash_map[ret] = tunnel_filter;
7575
7576         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7577
7578         return 0;
7579 }
7580
7581 /* Delete a tunnel filter from the SW list */
7582 int
7583 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7584                           struct i40e_tunnel_filter_input *input)
7585 {
7586         struct i40e_tunnel_rule *rule = &pf->tunnel;
7587         struct i40e_tunnel_filter *tunnel_filter;
7588         int ret;
7589
7590         ret = rte_hash_del_key(rule->hash_table, input);
7591         if (ret < 0) {
7592                 PMD_DRV_LOG(ERR,
7593                             "Failed to delete tunnel filter to hash table %d!",
7594                             ret);
7595                 return ret;
7596         }
7597         tunnel_filter = rule->hash_map[ret];
7598         rule->hash_map[ret] = NULL;
7599
7600         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7601         rte_free(tunnel_filter);
7602
7603         return 0;
7604 }
7605
7606 int
7607 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7608                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7609                         uint8_t add)
7610 {
7611         uint16_t ip_type;
7612         uint32_t ipv4_addr, ipv4_addr_le;
7613         uint8_t i, tun_type = 0;
7614         /* internal varialbe to convert ipv6 byte order */
7615         uint32_t convert_ipv6[4];
7616         int val, ret = 0;
7617         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7618         struct i40e_vsi *vsi = pf->main_vsi;
7619         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7620         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7621         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7622         struct i40e_tunnel_filter *tunnel, *node;
7623         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7624
7625         cld_filter = rte_zmalloc("tunnel_filter",
7626                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7627         0);
7628
7629         if (NULL == cld_filter) {
7630                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7631                 return -ENOMEM;
7632         }
7633         pfilter = cld_filter;
7634
7635         ether_addr_copy(&tunnel_filter->outer_mac,
7636                         (struct ether_addr *)&pfilter->element.outer_mac);
7637         ether_addr_copy(&tunnel_filter->inner_mac,
7638                         (struct ether_addr *)&pfilter->element.inner_mac);
7639
7640         pfilter->element.inner_vlan =
7641                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7642         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7643                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7644                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7645                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7646                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7647                                 &ipv4_addr_le,
7648                                 sizeof(pfilter->element.ipaddr.v4.data));
7649         } else {
7650                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7651                 for (i = 0; i < 4; i++) {
7652                         convert_ipv6[i] =
7653                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7654                 }
7655                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7656                            &convert_ipv6,
7657                            sizeof(pfilter->element.ipaddr.v6.data));
7658         }
7659
7660         /* check tunneled type */
7661         switch (tunnel_filter->tunnel_type) {
7662         case RTE_TUNNEL_TYPE_VXLAN:
7663                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7664                 break;
7665         case RTE_TUNNEL_TYPE_NVGRE:
7666                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7667                 break;
7668         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7669                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7670                 break;
7671         default:
7672                 /* Other tunnel types is not supported. */
7673                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7674                 rte_free(cld_filter);
7675                 return -EINVAL;
7676         }
7677
7678         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7679                                        &pfilter->element.flags);
7680         if (val < 0) {
7681                 rte_free(cld_filter);
7682                 return -EINVAL;
7683         }
7684
7685         pfilter->element.flags |= rte_cpu_to_le_16(
7686                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7687                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7688         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7689         pfilter->element.queue_number =
7690                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7691
7692         /* Check if there is the filter in SW list */
7693         memset(&check_filter, 0, sizeof(check_filter));
7694         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7695         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7696         if (add && node) {
7697                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7698                 rte_free(cld_filter);
7699                 return -EINVAL;
7700         }
7701
7702         if (!add && !node) {
7703                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7704                 rte_free(cld_filter);
7705                 return -EINVAL;
7706         }
7707
7708         if (add) {
7709                 ret = i40e_aq_add_cloud_filters(hw,
7710                                         vsi->seid, &cld_filter->element, 1);
7711                 if (ret < 0) {
7712                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7713                         rte_free(cld_filter);
7714                         return -ENOTSUP;
7715                 }
7716                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7717                 if (tunnel == NULL) {
7718                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7719                         rte_free(cld_filter);
7720                         return -ENOMEM;
7721                 }
7722
7723                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7724                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7725                 if (ret < 0)
7726                         rte_free(tunnel);
7727         } else {
7728                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7729                                                    &cld_filter->element, 1);
7730                 if (ret < 0) {
7731                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7732                         rte_free(cld_filter);
7733                         return -ENOTSUP;
7734                 }
7735                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7736         }
7737
7738         rte_free(cld_filter);
7739         return ret;
7740 }
7741
7742 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7743 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7744 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7745 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7746 #define I40E_TR_GRE_KEY_MASK                    0x400
7747 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7748 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7749
7750 static enum
7751 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7752 {
7753         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7754         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7756         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7757         enum i40e_status_code status = I40E_SUCCESS;
7758
7759         if (pf->support_multi_driver) {
7760                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7761                 return I40E_NOT_SUPPORTED;
7762         }
7763
7764         memset(&filter_replace, 0,
7765                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7766         memset(&filter_replace_buf, 0,
7767                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7768
7769         /* create L1 filter */
7770         filter_replace.old_filter_type =
7771                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7772         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7773         filter_replace.tr_bit = 0;
7774
7775         /* Prepare the buffer, 3 entries */
7776         filter_replace_buf.data[0] =
7777                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7778         filter_replace_buf.data[0] |=
7779                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7780         filter_replace_buf.data[2] = 0xFF;
7781         filter_replace_buf.data[3] = 0xFF;
7782         filter_replace_buf.data[4] =
7783                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7784         filter_replace_buf.data[4] |=
7785                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7786         filter_replace_buf.data[7] = 0xF0;
7787         filter_replace_buf.data[8]
7788                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7789         filter_replace_buf.data[8] |=
7790                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7791         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7792                 I40E_TR_GENEVE_KEY_MASK |
7793                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7794         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7795                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7796                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7797
7798         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7799                                                &filter_replace_buf);
7800         if (!status && (filter_replace.old_filter_type !=
7801                         filter_replace.new_filter_type))
7802                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7803                             " original: 0x%x, new: 0x%x",
7804                             dev->device->name,
7805                             filter_replace.old_filter_type,
7806                             filter_replace.new_filter_type);
7807
7808         return status;
7809 }
7810
7811 static enum
7812 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7813 {
7814         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7815         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7816         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7817         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7818         enum i40e_status_code status = I40E_SUCCESS;
7819
7820         if (pf->support_multi_driver) {
7821                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7822                 return I40E_NOT_SUPPORTED;
7823         }
7824
7825         /* For MPLSoUDP */
7826         memset(&filter_replace, 0,
7827                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7828         memset(&filter_replace_buf, 0,
7829                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7830         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7831                 I40E_AQC_MIRROR_CLOUD_FILTER;
7832         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7833         filter_replace.new_filter_type =
7834                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7835         /* Prepare the buffer, 2 entries */
7836         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7837         filter_replace_buf.data[0] |=
7838                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7839         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7840         filter_replace_buf.data[4] |=
7841                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7842         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7843                                                &filter_replace_buf);
7844         if (status < 0)
7845                 return status;
7846         if (filter_replace.old_filter_type !=
7847             filter_replace.new_filter_type)
7848                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7849                             " original: 0x%x, new: 0x%x",
7850                             dev->device->name,
7851                             filter_replace.old_filter_type,
7852                             filter_replace.new_filter_type);
7853
7854         /* For MPLSoGRE */
7855         memset(&filter_replace, 0,
7856                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7857         memset(&filter_replace_buf, 0,
7858                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7859
7860         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7861                 I40E_AQC_MIRROR_CLOUD_FILTER;
7862         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7863         filter_replace.new_filter_type =
7864                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7865         /* Prepare the buffer, 2 entries */
7866         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7867         filter_replace_buf.data[0] |=
7868                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7869         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7870         filter_replace_buf.data[4] |=
7871                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7872
7873         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7874                                                &filter_replace_buf);
7875         if (!status && (filter_replace.old_filter_type !=
7876                         filter_replace.new_filter_type))
7877                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7878                             " original: 0x%x, new: 0x%x",
7879                             dev->device->name,
7880                             filter_replace.old_filter_type,
7881                             filter_replace.new_filter_type);
7882
7883         return status;
7884 }
7885
7886 static enum i40e_status_code
7887 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7888 {
7889         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7890         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7891         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7892         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7893         enum i40e_status_code status = I40E_SUCCESS;
7894
7895         if (pf->support_multi_driver) {
7896                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7897                 return I40E_NOT_SUPPORTED;
7898         }
7899
7900         /* For GTP-C */
7901         memset(&filter_replace, 0,
7902                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7903         memset(&filter_replace_buf, 0,
7904                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7905         /* create L1 filter */
7906         filter_replace.old_filter_type =
7907                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7908         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7909         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7910                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7911         /* Prepare the buffer, 2 entries */
7912         filter_replace_buf.data[0] =
7913                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7914         filter_replace_buf.data[0] |=
7915                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7916         filter_replace_buf.data[2] = 0xFF;
7917         filter_replace_buf.data[3] = 0xFF;
7918         filter_replace_buf.data[4] =
7919                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7920         filter_replace_buf.data[4] |=
7921                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7922         filter_replace_buf.data[6] = 0xFF;
7923         filter_replace_buf.data[7] = 0xFF;
7924         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7925                                                &filter_replace_buf);
7926         if (status < 0)
7927                 return status;
7928         if (filter_replace.old_filter_type !=
7929             filter_replace.new_filter_type)
7930                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7931                             " original: 0x%x, new: 0x%x",
7932                             dev->device->name,
7933                             filter_replace.old_filter_type,
7934                             filter_replace.new_filter_type);
7935
7936         /* for GTP-U */
7937         memset(&filter_replace, 0,
7938                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7939         memset(&filter_replace_buf, 0,
7940                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7941         /* create L1 filter */
7942         filter_replace.old_filter_type =
7943                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7944         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7945         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7946                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7947         /* Prepare the buffer, 2 entries */
7948         filter_replace_buf.data[0] =
7949                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7950         filter_replace_buf.data[0] |=
7951                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7952         filter_replace_buf.data[2] = 0xFF;
7953         filter_replace_buf.data[3] = 0xFF;
7954         filter_replace_buf.data[4] =
7955                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7956         filter_replace_buf.data[4] |=
7957                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7958         filter_replace_buf.data[6] = 0xFF;
7959         filter_replace_buf.data[7] = 0xFF;
7960
7961         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7962                                                &filter_replace_buf);
7963         if (!status && (filter_replace.old_filter_type !=
7964                         filter_replace.new_filter_type))
7965                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7966                             " original: 0x%x, new: 0x%x",
7967                             dev->device->name,
7968                             filter_replace.old_filter_type,
7969                             filter_replace.new_filter_type);
7970
7971         return status;
7972 }
7973
7974 static enum
7975 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7976 {
7977         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7978         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7980         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7981         enum i40e_status_code status = I40E_SUCCESS;
7982
7983         if (pf->support_multi_driver) {
7984                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7985                 return I40E_NOT_SUPPORTED;
7986         }
7987
7988         /* for GTP-C */
7989         memset(&filter_replace, 0,
7990                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7991         memset(&filter_replace_buf, 0,
7992                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7993         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7994         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7995         filter_replace.new_filter_type =
7996                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7997         /* Prepare the buffer, 2 entries */
7998         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7999         filter_replace_buf.data[0] |=
8000                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8001         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8002         filter_replace_buf.data[4] |=
8003                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8004         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8005                                                &filter_replace_buf);
8006         if (status < 0)
8007                 return status;
8008         if (filter_replace.old_filter_type !=
8009             filter_replace.new_filter_type)
8010                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8011                             " original: 0x%x, new: 0x%x",
8012                             dev->device->name,
8013                             filter_replace.old_filter_type,
8014                             filter_replace.new_filter_type);
8015
8016         /* for GTP-U */
8017         memset(&filter_replace, 0,
8018                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8019         memset(&filter_replace_buf, 0,
8020                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8021         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8022         filter_replace.old_filter_type =
8023                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8024         filter_replace.new_filter_type =
8025                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8026         /* Prepare the buffer, 2 entries */
8027         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8028         filter_replace_buf.data[0] |=
8029                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8030         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8031         filter_replace_buf.data[4] |=
8032                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8033
8034         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8035                                                &filter_replace_buf);
8036         if (!status && (filter_replace.old_filter_type !=
8037                         filter_replace.new_filter_type))
8038                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8039                             " original: 0x%x, new: 0x%x",
8040                             dev->device->name,
8041                             filter_replace.old_filter_type,
8042                             filter_replace.new_filter_type);
8043
8044         return status;
8045 }
8046
8047 int
8048 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8049                       struct i40e_tunnel_filter_conf *tunnel_filter,
8050                       uint8_t add)
8051 {
8052         uint16_t ip_type;
8053         uint32_t ipv4_addr, ipv4_addr_le;
8054         uint8_t i, tun_type = 0;
8055         /* internal variable to convert ipv6 byte order */
8056         uint32_t convert_ipv6[4];
8057         int val, ret = 0;
8058         struct i40e_pf_vf *vf = NULL;
8059         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8060         struct i40e_vsi *vsi;
8061         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8062         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8063         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8064         struct i40e_tunnel_filter *tunnel, *node;
8065         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8066         uint32_t teid_le;
8067         bool big_buffer = 0;
8068
8069         cld_filter = rte_zmalloc("tunnel_filter",
8070                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8071                          0);
8072
8073         if (cld_filter == NULL) {
8074                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8075                 return -ENOMEM;
8076         }
8077         pfilter = cld_filter;
8078
8079         ether_addr_copy(&tunnel_filter->outer_mac,
8080                         (struct ether_addr *)&pfilter->element.outer_mac);
8081         ether_addr_copy(&tunnel_filter->inner_mac,
8082                         (struct ether_addr *)&pfilter->element.inner_mac);
8083
8084         pfilter->element.inner_vlan =
8085                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8086         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8087                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8088                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8089                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8090                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8091                                 &ipv4_addr_le,
8092                                 sizeof(pfilter->element.ipaddr.v4.data));
8093         } else {
8094                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8095                 for (i = 0; i < 4; i++) {
8096                         convert_ipv6[i] =
8097                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8098                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8099                 }
8100                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8101                            &convert_ipv6,
8102                            sizeof(pfilter->element.ipaddr.v6.data));
8103         }
8104
8105         /* check tunneled type */
8106         switch (tunnel_filter->tunnel_type) {
8107         case I40E_TUNNEL_TYPE_VXLAN:
8108                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8109                 break;
8110         case I40E_TUNNEL_TYPE_NVGRE:
8111                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8112                 break;
8113         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8114                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8115                 break;
8116         case I40E_TUNNEL_TYPE_MPLSoUDP:
8117                 if (!pf->mpls_replace_flag) {
8118                         i40e_replace_mpls_l1_filter(pf);
8119                         i40e_replace_mpls_cloud_filter(pf);
8120                         pf->mpls_replace_flag = 1;
8121                 }
8122                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8123                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8124                         teid_le >> 4;
8125                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8126                         (teid_le & 0xF) << 12;
8127                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8128                         0x40;
8129                 big_buffer = 1;
8130                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8131                 break;
8132         case I40E_TUNNEL_TYPE_MPLSoGRE:
8133                 if (!pf->mpls_replace_flag) {
8134                         i40e_replace_mpls_l1_filter(pf);
8135                         i40e_replace_mpls_cloud_filter(pf);
8136                         pf->mpls_replace_flag = 1;
8137                 }
8138                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8139                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8140                         teid_le >> 4;
8141                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8142                         (teid_le & 0xF) << 12;
8143                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8144                         0x0;
8145                 big_buffer = 1;
8146                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8147                 break;
8148         case I40E_TUNNEL_TYPE_GTPC:
8149                 if (!pf->gtp_replace_flag) {
8150                         i40e_replace_gtp_l1_filter(pf);
8151                         i40e_replace_gtp_cloud_filter(pf);
8152                         pf->gtp_replace_flag = 1;
8153                 }
8154                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8155                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8156                         (teid_le >> 16) & 0xFFFF;
8157                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8158                         teid_le & 0xFFFF;
8159                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8160                         0x0;
8161                 big_buffer = 1;
8162                 break;
8163         case I40E_TUNNEL_TYPE_GTPU:
8164                 if (!pf->gtp_replace_flag) {
8165                         i40e_replace_gtp_l1_filter(pf);
8166                         i40e_replace_gtp_cloud_filter(pf);
8167                         pf->gtp_replace_flag = 1;
8168                 }
8169                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8170                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8171                         (teid_le >> 16) & 0xFFFF;
8172                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8173                         teid_le & 0xFFFF;
8174                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8175                         0x0;
8176                 big_buffer = 1;
8177                 break;
8178         case I40E_TUNNEL_TYPE_QINQ:
8179                 if (!pf->qinq_replace_flag) {
8180                         ret = i40e_cloud_filter_qinq_create(pf);
8181                         if (ret < 0)
8182                                 PMD_DRV_LOG(DEBUG,
8183                                             "QinQ tunnel filter already created.");
8184                         pf->qinq_replace_flag = 1;
8185                 }
8186                 /*      Add in the General fields the values of
8187                  *      the Outer and Inner VLAN
8188                  *      Big Buffer should be set, see changes in
8189                  *      i40e_aq_add_cloud_filters
8190                  */
8191                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8192                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8193                 big_buffer = 1;
8194                 break;
8195         default:
8196                 /* Other tunnel types is not supported. */
8197                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8198                 rte_free(cld_filter);
8199                 return -EINVAL;
8200         }
8201
8202         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8203                 pfilter->element.flags =
8204                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8205         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8206                 pfilter->element.flags =
8207                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8208         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8209                 pfilter->element.flags =
8210                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8211         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8212                 pfilter->element.flags =
8213                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8214         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8215                 pfilter->element.flags |=
8216                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8217         else {
8218                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8219                                                 &pfilter->element.flags);
8220                 if (val < 0) {
8221                         rte_free(cld_filter);
8222                         return -EINVAL;
8223                 }
8224         }
8225
8226         pfilter->element.flags |= rte_cpu_to_le_16(
8227                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8228                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8229         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8230         pfilter->element.queue_number =
8231                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8232
8233         if (!tunnel_filter->is_to_vf)
8234                 vsi = pf->main_vsi;
8235         else {
8236                 if (tunnel_filter->vf_id >= pf->vf_num) {
8237                         PMD_DRV_LOG(ERR, "Invalid argument.");
8238                         rte_free(cld_filter);
8239                         return -EINVAL;
8240                 }
8241                 vf = &pf->vfs[tunnel_filter->vf_id];
8242                 vsi = vf->vsi;
8243         }
8244
8245         /* Check if there is the filter in SW list */
8246         memset(&check_filter, 0, sizeof(check_filter));
8247         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8248         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8249         check_filter.vf_id = tunnel_filter->vf_id;
8250         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8251         if (add && node) {
8252                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8253                 rte_free(cld_filter);
8254                 return -EINVAL;
8255         }
8256
8257         if (!add && !node) {
8258                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8259                 rte_free(cld_filter);
8260                 return -EINVAL;
8261         }
8262
8263         if (add) {
8264                 if (big_buffer)
8265                         ret = i40e_aq_add_cloud_filters_bb(hw,
8266                                                    vsi->seid, cld_filter, 1);
8267                 else
8268                         ret = i40e_aq_add_cloud_filters(hw,
8269                                         vsi->seid, &cld_filter->element, 1);
8270                 if (ret < 0) {
8271                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8272                         rte_free(cld_filter);
8273                         return -ENOTSUP;
8274                 }
8275                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8276                 if (tunnel == NULL) {
8277                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8278                         rte_free(cld_filter);
8279                         return -ENOMEM;
8280                 }
8281
8282                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8283                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8284                 if (ret < 0)
8285                         rte_free(tunnel);
8286         } else {
8287                 if (big_buffer)
8288                         ret = i40e_aq_rem_cloud_filters_bb(
8289                                 hw, vsi->seid, cld_filter, 1);
8290                 else
8291                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8292                                                 &cld_filter->element, 1);
8293                 if (ret < 0) {
8294                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8295                         rte_free(cld_filter);
8296                         return -ENOTSUP;
8297                 }
8298                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8299         }
8300
8301         rte_free(cld_filter);
8302         return ret;
8303 }
8304
8305 static int
8306 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8307 {
8308         uint8_t i;
8309
8310         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8311                 if (pf->vxlan_ports[i] == port)
8312                         return i;
8313         }
8314
8315         return -1;
8316 }
8317
8318 static int
8319 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8320 {
8321         int  idx, ret;
8322         uint8_t filter_idx;
8323         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8324
8325         idx = i40e_get_vxlan_port_idx(pf, port);
8326
8327         /* Check if port already exists */
8328         if (idx >= 0) {
8329                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8330                 return -EINVAL;
8331         }
8332
8333         /* Now check if there is space to add the new port */
8334         idx = i40e_get_vxlan_port_idx(pf, 0);
8335         if (idx < 0) {
8336                 PMD_DRV_LOG(ERR,
8337                         "Maximum number of UDP ports reached, not adding port %d",
8338                         port);
8339                 return -ENOSPC;
8340         }
8341
8342         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8343                                         &filter_idx, NULL);
8344         if (ret < 0) {
8345                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8346                 return -1;
8347         }
8348
8349         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8350                          port,  filter_idx);
8351
8352         /* New port: add it and mark its index in the bitmap */
8353         pf->vxlan_ports[idx] = port;
8354         pf->vxlan_bitmap |= (1 << idx);
8355
8356         if (!(pf->flags & I40E_FLAG_VXLAN))
8357                 pf->flags |= I40E_FLAG_VXLAN;
8358
8359         return 0;
8360 }
8361
8362 static int
8363 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8364 {
8365         int idx;
8366         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8367
8368         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8369                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8370                 return -EINVAL;
8371         }
8372
8373         idx = i40e_get_vxlan_port_idx(pf, port);
8374
8375         if (idx < 0) {
8376                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8377                 return -EINVAL;
8378         }
8379
8380         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8381                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8382                 return -1;
8383         }
8384
8385         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8386                         port, idx);
8387
8388         pf->vxlan_ports[idx] = 0;
8389         pf->vxlan_bitmap &= ~(1 << idx);
8390
8391         if (!pf->vxlan_bitmap)
8392                 pf->flags &= ~I40E_FLAG_VXLAN;
8393
8394         return 0;
8395 }
8396
8397 /* Add UDP tunneling port */
8398 static int
8399 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8400                              struct rte_eth_udp_tunnel *udp_tunnel)
8401 {
8402         int ret = 0;
8403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8404
8405         if (udp_tunnel == NULL)
8406                 return -EINVAL;
8407
8408         switch (udp_tunnel->prot_type) {
8409         case RTE_TUNNEL_TYPE_VXLAN:
8410                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8411                 break;
8412
8413         case RTE_TUNNEL_TYPE_GENEVE:
8414         case RTE_TUNNEL_TYPE_TEREDO:
8415                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8416                 ret = -1;
8417                 break;
8418
8419         default:
8420                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8421                 ret = -1;
8422                 break;
8423         }
8424
8425         return ret;
8426 }
8427
8428 /* Remove UDP tunneling port */
8429 static int
8430 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8431                              struct rte_eth_udp_tunnel *udp_tunnel)
8432 {
8433         int ret = 0;
8434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8435
8436         if (udp_tunnel == NULL)
8437                 return -EINVAL;
8438
8439         switch (udp_tunnel->prot_type) {
8440         case RTE_TUNNEL_TYPE_VXLAN:
8441                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8442                 break;
8443         case RTE_TUNNEL_TYPE_GENEVE:
8444         case RTE_TUNNEL_TYPE_TEREDO:
8445                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8446                 ret = -1;
8447                 break;
8448         default:
8449                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8450                 ret = -1;
8451                 break;
8452         }
8453
8454         return ret;
8455 }
8456
8457 /* Calculate the maximum number of contiguous PF queues that are configured */
8458 static int
8459 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8460 {
8461         struct rte_eth_dev_data *data = pf->dev_data;
8462         int i, num;
8463         struct i40e_rx_queue *rxq;
8464
8465         num = 0;
8466         for (i = 0; i < pf->lan_nb_qps; i++) {
8467                 rxq = data->rx_queues[i];
8468                 if (rxq && rxq->q_set)
8469                         num++;
8470                 else
8471                         break;
8472         }
8473
8474         return num;
8475 }
8476
8477 /* Configure RSS */
8478 static int
8479 i40e_pf_config_rss(struct i40e_pf *pf)
8480 {
8481         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8482         struct rte_eth_rss_conf rss_conf;
8483         uint32_t i, lut = 0;
8484         uint16_t j, num;
8485
8486         /*
8487          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8488          * It's necessary to calculate the actual PF queues that are configured.
8489          */
8490         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8491                 num = i40e_pf_calc_configured_queues_num(pf);
8492         else
8493                 num = pf->dev_data->nb_rx_queues;
8494
8495         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8496         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8497                         num);
8498
8499         if (num == 0) {
8500                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8501                 return -ENOTSUP;
8502         }
8503
8504         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8505                 if (j == num)
8506                         j = 0;
8507                 lut = (lut << 8) | (j & ((0x1 <<
8508                         hw->func_caps.rss_table_entry_width) - 1));
8509                 if ((i & 3) == 3)
8510                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8511         }
8512
8513         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8514         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8515                 i40e_pf_disable_rss(pf);
8516                 return 0;
8517         }
8518         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8519                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8520                 /* Random default keys */
8521                 static uint32_t rss_key_default[] = {0x6b793944,
8522                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8523                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8524                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8525
8526                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8527                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8528                                                         sizeof(uint32_t);
8529         }
8530
8531         return i40e_hw_rss_hash_set(pf, &rss_conf);
8532 }
8533
8534 static int
8535 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8536                                struct rte_eth_tunnel_filter_conf *filter)
8537 {
8538         if (pf == NULL || filter == NULL) {
8539                 PMD_DRV_LOG(ERR, "Invalid parameter");
8540                 return -EINVAL;
8541         }
8542
8543         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8544                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8545                 return -EINVAL;
8546         }
8547
8548         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8549                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8550                 return -EINVAL;
8551         }
8552
8553         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8554                 (is_zero_ether_addr(&filter->outer_mac))) {
8555                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8556                 return -EINVAL;
8557         }
8558
8559         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8560                 (is_zero_ether_addr(&filter->inner_mac))) {
8561                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8562                 return -EINVAL;
8563         }
8564
8565         return 0;
8566 }
8567
8568 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8569 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8570 static int
8571 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8572 {
8573         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8574         uint32_t val, reg;
8575         int ret = -EINVAL;
8576
8577         if (pf->support_multi_driver) {
8578                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8579                 return -ENOTSUP;
8580         }
8581
8582         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8583         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8584
8585         if (len == 3) {
8586                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8587         } else if (len == 4) {
8588                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8589         } else {
8590                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8591                 return ret;
8592         }
8593
8594         if (reg != val) {
8595                 ret = i40e_aq_debug_write_global_register(hw,
8596                                                    I40E_GL_PRS_FVBM(2),
8597                                                    reg, NULL);
8598                 if (ret != 0)
8599                         return ret;
8600                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8601                             "with value 0x%08x",
8602                             I40E_GL_PRS_FVBM(2), reg);
8603         } else {
8604                 ret = 0;
8605         }
8606         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8607                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8608
8609         return ret;
8610 }
8611
8612 static int
8613 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8614 {
8615         int ret = -EINVAL;
8616
8617         if (!hw || !cfg)
8618                 return -EINVAL;
8619
8620         switch (cfg->cfg_type) {
8621         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8622                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8623                 break;
8624         default:
8625                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8626                 break;
8627         }
8628
8629         return ret;
8630 }
8631
8632 static int
8633 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8634                                enum rte_filter_op filter_op,
8635                                void *arg)
8636 {
8637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8638         int ret = I40E_ERR_PARAM;
8639
8640         switch (filter_op) {
8641         case RTE_ETH_FILTER_SET:
8642                 ret = i40e_dev_global_config_set(hw,
8643                         (struct rte_eth_global_cfg *)arg);
8644                 break;
8645         default:
8646                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8647                 break;
8648         }
8649
8650         return ret;
8651 }
8652
8653 static int
8654 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8655                           enum rte_filter_op filter_op,
8656                           void *arg)
8657 {
8658         struct rte_eth_tunnel_filter_conf *filter;
8659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8660         int ret = I40E_SUCCESS;
8661
8662         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8663
8664         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8665                 return I40E_ERR_PARAM;
8666
8667         switch (filter_op) {
8668         case RTE_ETH_FILTER_NOP:
8669                 if (!(pf->flags & I40E_FLAG_VXLAN))
8670                         ret = I40E_NOT_SUPPORTED;
8671                 break;
8672         case RTE_ETH_FILTER_ADD:
8673                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8674                 break;
8675         case RTE_ETH_FILTER_DELETE:
8676                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8677                 break;
8678         default:
8679                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8680                 ret = I40E_ERR_PARAM;
8681                 break;
8682         }
8683
8684         return ret;
8685 }
8686
8687 static int
8688 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8689 {
8690         int ret = 0;
8691         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8692
8693         /* RSS setup */
8694         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8695                 ret = i40e_pf_config_rss(pf);
8696         else
8697                 i40e_pf_disable_rss(pf);
8698
8699         return ret;
8700 }
8701
8702 /* Get the symmetric hash enable configurations per port */
8703 static void
8704 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8705 {
8706         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8707
8708         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8709 }
8710
8711 /* Set the symmetric hash enable configurations per port */
8712 static void
8713 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8714 {
8715         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8716
8717         if (enable > 0) {
8718                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8719                         PMD_DRV_LOG(INFO,
8720                                 "Symmetric hash has already been enabled");
8721                         return;
8722                 }
8723                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8724         } else {
8725                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8726                         PMD_DRV_LOG(INFO,
8727                                 "Symmetric hash has already been disabled");
8728                         return;
8729                 }
8730                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8731         }
8732         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8733         I40E_WRITE_FLUSH(hw);
8734 }
8735
8736 /*
8737  * Get global configurations of hash function type and symmetric hash enable
8738  * per flow type (pctype). Note that global configuration means it affects all
8739  * the ports on the same NIC.
8740  */
8741 static int
8742 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8743                                    struct rte_eth_hash_global_conf *g_cfg)
8744 {
8745         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8746         uint32_t reg;
8747         uint16_t i, j;
8748
8749         memset(g_cfg, 0, sizeof(*g_cfg));
8750         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8751         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8752                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8753         else
8754                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8755         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8756                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8757
8758         /*
8759          * As i40e supports less than 64 flow types, only first 64 bits need to
8760          * be checked.
8761          */
8762         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8763                 g_cfg->valid_bit_mask[i] = 0ULL;
8764                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8765         }
8766
8767         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8768
8769         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8770                 if (!adapter->pctypes_tbl[i])
8771                         continue;
8772                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8773                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8774                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8775                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8776                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8777                                         g_cfg->sym_hash_enable_mask[0] |=
8778                                                                 (1ULL << i);
8779                                 }
8780                         }
8781                 }
8782         }
8783
8784         return 0;
8785 }
8786
8787 static int
8788 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8789                               const struct rte_eth_hash_global_conf *g_cfg)
8790 {
8791         uint32_t i;
8792         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8793
8794         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8795                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8796                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8797                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8798                                                 g_cfg->hash_func);
8799                 return -EINVAL;
8800         }
8801
8802         /*
8803          * As i40e supports less than 64 flow types, only first 64 bits need to
8804          * be checked.
8805          */
8806         mask0 = g_cfg->valid_bit_mask[0];
8807         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8808                 if (i == 0) {
8809                         /* Check if any unsupported flow type configured */
8810                         if ((mask0 | i40e_mask) ^ i40e_mask)
8811                                 goto mask_err;
8812                 } else {
8813                         if (g_cfg->valid_bit_mask[i])
8814                                 goto mask_err;
8815                 }
8816         }
8817
8818         return 0;
8819
8820 mask_err:
8821         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8822
8823         return -EINVAL;
8824 }
8825
8826 /*
8827  * Set global configurations of hash function type and symmetric hash enable
8828  * per flow type (pctype). Note any modifying global configuration will affect
8829  * all the ports on the same NIC.
8830  */
8831 static int
8832 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8833                                    struct rte_eth_hash_global_conf *g_cfg)
8834 {
8835         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8836         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8837         int ret;
8838         uint16_t i, j;
8839         uint32_t reg;
8840         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8841
8842         if (pf->support_multi_driver) {
8843                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8844                 return -ENOTSUP;
8845         }
8846
8847         /* Check the input parameters */
8848         ret = i40e_hash_global_config_check(adapter, g_cfg);
8849         if (ret < 0)
8850                 return ret;
8851
8852         /*
8853          * As i40e supports less than 64 flow types, only first 64 bits need to
8854          * be configured.
8855          */
8856         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8857                 if (mask0 & (1UL << i)) {
8858                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8859                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8860
8861                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8862                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8863                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8864                                         i40e_write_global_rx_ctl(hw,
8865                                                           I40E_GLQF_HSYM(j),
8866                                                           reg);
8867                         }
8868                 }
8869         }
8870
8871         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8872         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8873                 /* Toeplitz */
8874                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8875                         PMD_DRV_LOG(DEBUG,
8876                                 "Hash function already set to Toeplitz");
8877                         goto out;
8878                 }
8879                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8880         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8881                 /* Simple XOR */
8882                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8883                         PMD_DRV_LOG(DEBUG,
8884                                 "Hash function already set to Simple XOR");
8885                         goto out;
8886                 }
8887                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8888         } else
8889                 /* Use the default, and keep it as it is */
8890                 goto out;
8891
8892         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8893
8894 out:
8895         I40E_WRITE_FLUSH(hw);
8896
8897         return 0;
8898 }
8899
8900 /**
8901  * Valid input sets for hash and flow director filters per PCTYPE
8902  */
8903 static uint64_t
8904 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8905                 enum rte_filter_type filter)
8906 {
8907         uint64_t valid;
8908
8909         static const uint64_t valid_hash_inset_table[] = {
8910                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8911                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8912                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8913                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8914                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8915                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8916                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8917                         I40E_INSET_FLEX_PAYLOAD,
8918                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8919                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8920                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8921                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8922                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8923                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8924                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8925                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8926                         I40E_INSET_FLEX_PAYLOAD,
8927                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8928                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8929                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8930                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8931                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8932                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8933                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8934                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8935                         I40E_INSET_FLEX_PAYLOAD,
8936                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8937                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8938                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8939                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8940                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8941                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8942                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8943                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8944                         I40E_INSET_FLEX_PAYLOAD,
8945                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8946                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8947                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8948                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8949                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8950                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8951                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8952                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8953                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8954                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8955                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8956                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8957                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8958                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8959                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8960                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8961                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8962                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8963                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8964                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8965                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8966                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8967                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8968                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8969                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8970                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8971                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8972                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8973                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8974                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8975                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8976                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8977                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8978                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8979                         I40E_INSET_FLEX_PAYLOAD,
8980                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8981                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8982                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8983                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8984                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8985                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8986                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8987                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8988                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8989                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8990                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8991                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8992                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8993                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8994                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8995                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8996                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8997                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8998                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8999                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9000                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9001                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9002                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9003                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9004                         I40E_INSET_FLEX_PAYLOAD,
9005                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9006                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9007                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9008                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9009                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9010                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9011                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9012                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9013                         I40E_INSET_FLEX_PAYLOAD,
9014                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9015                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9016                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9017                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9018                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9019                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9020                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9021                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9022                         I40E_INSET_FLEX_PAYLOAD,
9023                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9024                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9025                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9026                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9027                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9028                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9029                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9030                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9031                         I40E_INSET_FLEX_PAYLOAD,
9032                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9033                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9034                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9035                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9036                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9037                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9038                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9039                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9040                         I40E_INSET_FLEX_PAYLOAD,
9041                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9042                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9043                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9044                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9045                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9046                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9047                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9048                         I40E_INSET_FLEX_PAYLOAD,
9049                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9050                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9051                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9052                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9053                         I40E_INSET_FLEX_PAYLOAD,
9054         };
9055
9056         /**
9057          * Flow director supports only fields defined in
9058          * union rte_eth_fdir_flow.
9059          */
9060         static const uint64_t valid_fdir_inset_table[] = {
9061                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9062                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9063                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9064                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9065                 I40E_INSET_IPV4_TTL,
9066                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9067                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9068                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9069                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9070                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9071                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9072                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9073                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9074                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9075                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9076                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9077                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9078                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9079                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9080                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9081                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9082                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9083                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9084                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9085                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9086                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9087                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9088                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9090                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9092                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9093                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9094                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9095                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9096                 I40E_INSET_SCTP_VT,
9097                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9098                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9099                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9100                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9101                 I40E_INSET_IPV4_TTL,
9102                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9103                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9104                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9105                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9106                 I40E_INSET_IPV6_HOP_LIMIT,
9107                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9108                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9109                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9110                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9111                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9112                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9113                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9115                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9116                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9117                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9118                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9120                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9121                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9122                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9123                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9124                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9125                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9126                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9127                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9128                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9130                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9131                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9132                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9133                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9134                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9135                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9136                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9137                 I40E_INSET_SCTP_VT,
9138                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9139                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9141                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9142                 I40E_INSET_IPV6_HOP_LIMIT,
9143                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145                 I40E_INSET_LAST_ETHER_TYPE,
9146         };
9147
9148         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9149                 return 0;
9150         if (filter == RTE_ETH_FILTER_HASH)
9151                 valid = valid_hash_inset_table[pctype];
9152         else
9153                 valid = valid_fdir_inset_table[pctype];
9154
9155         return valid;
9156 }
9157
9158 /**
9159  * Validate if the input set is allowed for a specific PCTYPE
9160  */
9161 int
9162 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9163                 enum rte_filter_type filter, uint64_t inset)
9164 {
9165         uint64_t valid;
9166
9167         valid = i40e_get_valid_input_set(pctype, filter);
9168         if (inset & (~valid))
9169                 return -EINVAL;
9170
9171         return 0;
9172 }
9173
9174 /* default input set fields combination per pctype */
9175 uint64_t
9176 i40e_get_default_input_set(uint16_t pctype)
9177 {
9178         static const uint64_t default_inset_table[] = {
9179                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9180                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9181                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9182                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9183                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9184                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9185                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9187                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9188                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9189                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9190                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9191                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9192                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9193                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9194                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9195                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9196                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9197                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9198                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9199                         I40E_INSET_SCTP_VT,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9201                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9202                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9203                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9204                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9205                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9206                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9207                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9208                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9209                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9211                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9212                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9213                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9214                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9215                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9216                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9217                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9218                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9219                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9220                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9221                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9222                         I40E_INSET_SCTP_VT,
9223                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9224                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9225                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9226                         I40E_INSET_LAST_ETHER_TYPE,
9227         };
9228
9229         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9230                 return 0;
9231
9232         return default_inset_table[pctype];
9233 }
9234
9235 /**
9236  * Parse the input set from index to logical bit masks
9237  */
9238 static int
9239 i40e_parse_input_set(uint64_t *inset,
9240                      enum i40e_filter_pctype pctype,
9241                      enum rte_eth_input_set_field *field,
9242                      uint16_t size)
9243 {
9244         uint16_t i, j;
9245         int ret = -EINVAL;
9246
9247         static const struct {
9248                 enum rte_eth_input_set_field field;
9249                 uint64_t inset;
9250         } inset_convert_table[] = {
9251                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9252                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9253                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9254                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9255                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9256                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9257                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9258                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9259                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9260                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9261                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9262                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9263                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9264                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9265                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9266                         I40E_INSET_IPV6_NEXT_HDR},
9267                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9268                         I40E_INSET_IPV6_HOP_LIMIT},
9269                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9270                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9271                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9272                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9273                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9274                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9275                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9276                         I40E_INSET_SCTP_VT},
9277                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9278                         I40E_INSET_TUNNEL_DMAC},
9279                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9280                         I40E_INSET_VLAN_TUNNEL},
9281                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9282                         I40E_INSET_TUNNEL_ID},
9283                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9284                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9285                         I40E_INSET_FLEX_PAYLOAD_W1},
9286                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9287                         I40E_INSET_FLEX_PAYLOAD_W2},
9288                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9289                         I40E_INSET_FLEX_PAYLOAD_W3},
9290                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9291                         I40E_INSET_FLEX_PAYLOAD_W4},
9292                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9293                         I40E_INSET_FLEX_PAYLOAD_W5},
9294                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9295                         I40E_INSET_FLEX_PAYLOAD_W6},
9296                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9297                         I40E_INSET_FLEX_PAYLOAD_W7},
9298                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9299                         I40E_INSET_FLEX_PAYLOAD_W8},
9300         };
9301
9302         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9303                 return ret;
9304
9305         /* Only one item allowed for default or all */
9306         if (size == 1) {
9307                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9308                         *inset = i40e_get_default_input_set(pctype);
9309                         return 0;
9310                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9311                         *inset = I40E_INSET_NONE;
9312                         return 0;
9313                 }
9314         }
9315
9316         for (i = 0, *inset = 0; i < size; i++) {
9317                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9318                         if (field[i] == inset_convert_table[j].field) {
9319                                 *inset |= inset_convert_table[j].inset;
9320                                 break;
9321                         }
9322                 }
9323
9324                 /* It contains unsupported input set, return immediately */
9325                 if (j == RTE_DIM(inset_convert_table))
9326                         return ret;
9327         }
9328
9329         return 0;
9330 }
9331
9332 /**
9333  * Translate the input set from bit masks to register aware bit masks
9334  * and vice versa
9335  */
9336 uint64_t
9337 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9338 {
9339         uint64_t val = 0;
9340         uint16_t i;
9341
9342         struct inset_map {
9343                 uint64_t inset;
9344                 uint64_t inset_reg;
9345         };
9346
9347         static const struct inset_map inset_map_common[] = {
9348                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9349                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9350                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9351                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9352                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9353                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9354                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9355                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9356                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9357                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9358                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9359                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9360                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9361                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9362                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9363                 {I40E_INSET_TUNNEL_DMAC,
9364                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9365                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9366                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9367                 {I40E_INSET_TUNNEL_SRC_PORT,
9368                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9369                 {I40E_INSET_TUNNEL_DST_PORT,
9370                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9371                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9372                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9373                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9374                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9375                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9376                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9377                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9378                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9379                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9380         };
9381
9382     /* some different registers map in x722*/
9383         static const struct inset_map inset_map_diff_x722[] = {
9384                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9385                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9386                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9387                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9388         };
9389
9390         static const struct inset_map inset_map_diff_not_x722[] = {
9391                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9392                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9393                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9394                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9395         };
9396
9397         if (input == 0)
9398                 return val;
9399
9400         /* Translate input set to register aware inset */
9401         if (type == I40E_MAC_X722) {
9402                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9403                         if (input & inset_map_diff_x722[i].inset)
9404                                 val |= inset_map_diff_x722[i].inset_reg;
9405                 }
9406         } else {
9407                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9408                         if (input & inset_map_diff_not_x722[i].inset)
9409                                 val |= inset_map_diff_not_x722[i].inset_reg;
9410                 }
9411         }
9412
9413         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9414                 if (input & inset_map_common[i].inset)
9415                         val |= inset_map_common[i].inset_reg;
9416         }
9417
9418         return val;
9419 }
9420
9421 int
9422 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9423 {
9424         uint8_t i, idx = 0;
9425         uint64_t inset_need_mask = inset;
9426
9427         static const struct {
9428                 uint64_t inset;
9429                 uint32_t mask;
9430         } inset_mask_map[] = {
9431                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9432                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9433                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9434                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9435                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9436                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9437                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9438                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9439         };
9440
9441         if (!inset || !mask || !nb_elem)
9442                 return 0;
9443
9444         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9445                 /* Clear the inset bit, if no MASK is required,
9446                  * for example proto + ttl
9447                  */
9448                 if ((inset & inset_mask_map[i].inset) ==
9449                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9450                         inset_need_mask &= ~inset_mask_map[i].inset;
9451                 if (!inset_need_mask)
9452                         return 0;
9453         }
9454         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9455                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9456                     inset_mask_map[i].inset) {
9457                         if (idx >= nb_elem) {
9458                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9459                                 return -EINVAL;
9460                         }
9461                         mask[idx] = inset_mask_map[i].mask;
9462                         idx++;
9463                 }
9464         }
9465
9466         return idx;
9467 }
9468
9469 void
9470 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9471 {
9472         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9473
9474         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9475         if (reg != val)
9476                 i40e_write_rx_ctl(hw, addr, val);
9477         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9478                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9479 }
9480
9481 void
9482 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9483 {
9484         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9485         struct rte_eth_dev *dev;
9486
9487         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9488         if (reg != val) {
9489                 i40e_write_rx_ctl(hw, addr, val);
9490                 PMD_DRV_LOG(WARNING,
9491                             "i40e device %s changed global register [0x%08x]."
9492                             " original: 0x%08x, new: 0x%08x",
9493                             dev->device->name, addr, reg,
9494                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9495         }
9496 }
9497
9498 static void
9499 i40e_filter_input_set_init(struct i40e_pf *pf)
9500 {
9501         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9502         enum i40e_filter_pctype pctype;
9503         uint64_t input_set, inset_reg;
9504         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9505         int num, i;
9506         uint16_t flow_type;
9507
9508         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9509              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9510                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9511
9512                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9513                         continue;
9514
9515                 input_set = i40e_get_default_input_set(pctype);
9516
9517                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9518                                                    I40E_INSET_MASK_NUM_REG);
9519                 if (num < 0)
9520                         return;
9521                 if (pf->support_multi_driver && num > 0) {
9522                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9523                         return;
9524                 }
9525                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9526                                         input_set);
9527
9528                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9529                                       (uint32_t)(inset_reg & UINT32_MAX));
9530                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9531                                      (uint32_t)((inset_reg >>
9532                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9533                 if (!pf->support_multi_driver) {
9534                         i40e_check_write_global_reg(hw,
9535                                             I40E_GLQF_HASH_INSET(0, pctype),
9536                                             (uint32_t)(inset_reg & UINT32_MAX));
9537                         i40e_check_write_global_reg(hw,
9538                                              I40E_GLQF_HASH_INSET(1, pctype),
9539                                              (uint32_t)((inset_reg >>
9540                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9541
9542                         for (i = 0; i < num; i++) {
9543                                 i40e_check_write_global_reg(hw,
9544                                                     I40E_GLQF_FD_MSK(i, pctype),
9545                                                     mask_reg[i]);
9546                                 i40e_check_write_global_reg(hw,
9547                                                   I40E_GLQF_HASH_MSK(i, pctype),
9548                                                   mask_reg[i]);
9549                         }
9550                         /*clear unused mask registers of the pctype */
9551                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9552                                 i40e_check_write_global_reg(hw,
9553                                                     I40E_GLQF_FD_MSK(i, pctype),
9554                                                     0);
9555                                 i40e_check_write_global_reg(hw,
9556                                                   I40E_GLQF_HASH_MSK(i, pctype),
9557                                                   0);
9558                         }
9559                 } else {
9560                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9561                 }
9562                 I40E_WRITE_FLUSH(hw);
9563
9564                 /* store the default input set */
9565                 if (!pf->support_multi_driver)
9566                         pf->hash_input_set[pctype] = input_set;
9567                 pf->fdir.input_set[pctype] = input_set;
9568         }
9569 }
9570
9571 int
9572 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9573                          struct rte_eth_input_set_conf *conf)
9574 {
9575         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9576         enum i40e_filter_pctype pctype;
9577         uint64_t input_set, inset_reg = 0;
9578         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9579         int ret, i, num;
9580
9581         if (!conf) {
9582                 PMD_DRV_LOG(ERR, "Invalid pointer");
9583                 return -EFAULT;
9584         }
9585         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9586             conf->op != RTE_ETH_INPUT_SET_ADD) {
9587                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9588                 return -EINVAL;
9589         }
9590
9591         if (pf->support_multi_driver) {
9592                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9593                 return -ENOTSUP;
9594         }
9595
9596         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9597         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9598                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9599                 return -EINVAL;
9600         }
9601
9602         if (hw->mac.type == I40E_MAC_X722) {
9603                 /* get translated pctype value in fd pctype register */
9604                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9605                         I40E_GLQF_FD_PCTYPES((int)pctype));
9606         }
9607
9608         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9609                                    conf->inset_size);
9610         if (ret) {
9611                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9612                 return -EINVAL;
9613         }
9614
9615         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9616                 /* get inset value in register */
9617                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9618                 inset_reg <<= I40E_32_BIT_WIDTH;
9619                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9620                 input_set |= pf->hash_input_set[pctype];
9621         }
9622         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9623                                            I40E_INSET_MASK_NUM_REG);
9624         if (num < 0)
9625                 return -EINVAL;
9626
9627         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9628
9629         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9630                                     (uint32_t)(inset_reg & UINT32_MAX));
9631         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9632                                     (uint32_t)((inset_reg >>
9633                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9634
9635         for (i = 0; i < num; i++)
9636                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9637                                             mask_reg[i]);
9638         /*clear unused mask registers of the pctype */
9639         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9640                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9641                                             0);
9642         I40E_WRITE_FLUSH(hw);
9643
9644         pf->hash_input_set[pctype] = input_set;
9645         return 0;
9646 }
9647
9648 int
9649 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9650                          struct rte_eth_input_set_conf *conf)
9651 {
9652         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9653         enum i40e_filter_pctype pctype;
9654         uint64_t input_set, inset_reg = 0;
9655         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9656         int ret, i, num;
9657
9658         if (!hw || !conf) {
9659                 PMD_DRV_LOG(ERR, "Invalid pointer");
9660                 return -EFAULT;
9661         }
9662         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9663             conf->op != RTE_ETH_INPUT_SET_ADD) {
9664                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9665                 return -EINVAL;
9666         }
9667
9668         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9669
9670         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9671                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9672                 return -EINVAL;
9673         }
9674
9675         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9676                                    conf->inset_size);
9677         if (ret) {
9678                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9679                 return -EINVAL;
9680         }
9681
9682         /* get inset value in register */
9683         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9684         inset_reg <<= I40E_32_BIT_WIDTH;
9685         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9686
9687         /* Can not change the inset reg for flex payload for fdir,
9688          * it is done by writing I40E_PRTQF_FD_FLXINSET
9689          * in i40e_set_flex_mask_on_pctype.
9690          */
9691         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9692                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9693         else
9694                 input_set |= pf->fdir.input_set[pctype];
9695         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9696                                            I40E_INSET_MASK_NUM_REG);
9697         if (num < 0)
9698                 return -EINVAL;
9699         if (pf->support_multi_driver && num > 0) {
9700                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9701                 return -ENOTSUP;
9702         }
9703
9704         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9705
9706         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9707                               (uint32_t)(inset_reg & UINT32_MAX));
9708         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9709                              (uint32_t)((inset_reg >>
9710                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9711
9712         if (!pf->support_multi_driver) {
9713                 for (i = 0; i < num; i++)
9714                         i40e_check_write_global_reg(hw,
9715                                                     I40E_GLQF_FD_MSK(i, pctype),
9716                                                     mask_reg[i]);
9717                 /*clear unused mask registers of the pctype */
9718                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9719                         i40e_check_write_global_reg(hw,
9720                                                     I40E_GLQF_FD_MSK(i, pctype),
9721                                                     0);
9722         } else {
9723                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9724         }
9725         I40E_WRITE_FLUSH(hw);
9726
9727         pf->fdir.input_set[pctype] = input_set;
9728         return 0;
9729 }
9730
9731 static int
9732 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9733 {
9734         int ret = 0;
9735
9736         if (!hw || !info) {
9737                 PMD_DRV_LOG(ERR, "Invalid pointer");
9738                 return -EFAULT;
9739         }
9740
9741         switch (info->info_type) {
9742         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9743                 i40e_get_symmetric_hash_enable_per_port(hw,
9744                                         &(info->info.enable));
9745                 break;
9746         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9747                 ret = i40e_get_hash_filter_global_config(hw,
9748                                 &(info->info.global_conf));
9749                 break;
9750         default:
9751                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9752                                                         info->info_type);
9753                 ret = -EINVAL;
9754                 break;
9755         }
9756
9757         return ret;
9758 }
9759
9760 static int
9761 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9762 {
9763         int ret = 0;
9764
9765         if (!hw || !info) {
9766                 PMD_DRV_LOG(ERR, "Invalid pointer");
9767                 return -EFAULT;
9768         }
9769
9770         switch (info->info_type) {
9771         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9772                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9773                 break;
9774         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9775                 ret = i40e_set_hash_filter_global_config(hw,
9776                                 &(info->info.global_conf));
9777                 break;
9778         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9779                 ret = i40e_hash_filter_inset_select(hw,
9780                                                &(info->info.input_set_conf));
9781                 break;
9782
9783         default:
9784                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9785                                                         info->info_type);
9786                 ret = -EINVAL;
9787                 break;
9788         }
9789
9790         return ret;
9791 }
9792
9793 /* Operations for hash function */
9794 static int
9795 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9796                       enum rte_filter_op filter_op,
9797                       void *arg)
9798 {
9799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9800         int ret = 0;
9801
9802         switch (filter_op) {
9803         case RTE_ETH_FILTER_NOP:
9804                 break;
9805         case RTE_ETH_FILTER_GET:
9806                 ret = i40e_hash_filter_get(hw,
9807                         (struct rte_eth_hash_filter_info *)arg);
9808                 break;
9809         case RTE_ETH_FILTER_SET:
9810                 ret = i40e_hash_filter_set(hw,
9811                         (struct rte_eth_hash_filter_info *)arg);
9812                 break;
9813         default:
9814                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9815                                                                 filter_op);
9816                 ret = -ENOTSUP;
9817                 break;
9818         }
9819
9820         return ret;
9821 }
9822
9823 /* Convert ethertype filter structure */
9824 static int
9825 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9826                               struct i40e_ethertype_filter *filter)
9827 {
9828         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9829         filter->input.ether_type = input->ether_type;
9830         filter->flags = input->flags;
9831         filter->queue = input->queue;
9832
9833         return 0;
9834 }
9835
9836 /* Check if there exists the ehtertype filter */
9837 struct i40e_ethertype_filter *
9838 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9839                                 const struct i40e_ethertype_filter_input *input)
9840 {
9841         int ret;
9842
9843         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9844         if (ret < 0)
9845                 return NULL;
9846
9847         return ethertype_rule->hash_map[ret];
9848 }
9849
9850 /* Add ethertype filter in SW list */
9851 static int
9852 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9853                                 struct i40e_ethertype_filter *filter)
9854 {
9855         struct i40e_ethertype_rule *rule = &pf->ethertype;
9856         int ret;
9857
9858         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9859         if (ret < 0) {
9860                 PMD_DRV_LOG(ERR,
9861                             "Failed to insert ethertype filter"
9862                             " to hash table %d!",
9863                             ret);
9864                 return ret;
9865         }
9866         rule->hash_map[ret] = filter;
9867
9868         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9869
9870         return 0;
9871 }
9872
9873 /* Delete ethertype filter in SW list */
9874 int
9875 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9876                              struct i40e_ethertype_filter_input *input)
9877 {
9878         struct i40e_ethertype_rule *rule = &pf->ethertype;
9879         struct i40e_ethertype_filter *filter;
9880         int ret;
9881
9882         ret = rte_hash_del_key(rule->hash_table, input);
9883         if (ret < 0) {
9884                 PMD_DRV_LOG(ERR,
9885                             "Failed to delete ethertype filter"
9886                             " to hash table %d!",
9887                             ret);
9888                 return ret;
9889         }
9890         filter = rule->hash_map[ret];
9891         rule->hash_map[ret] = NULL;
9892
9893         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9894         rte_free(filter);
9895
9896         return 0;
9897 }
9898
9899 /*
9900  * Configure ethertype filter, which can director packet by filtering
9901  * with mac address and ether_type or only ether_type
9902  */
9903 int
9904 i40e_ethertype_filter_set(struct i40e_pf *pf,
9905                         struct rte_eth_ethertype_filter *filter,
9906                         bool add)
9907 {
9908         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9909         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9910         struct i40e_ethertype_filter *ethertype_filter, *node;
9911         struct i40e_ethertype_filter check_filter;
9912         struct i40e_control_filter_stats stats;
9913         uint16_t flags = 0;
9914         int ret;
9915
9916         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9917                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9918                 return -EINVAL;
9919         }
9920         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9921                 filter->ether_type == ETHER_TYPE_IPv6) {
9922                 PMD_DRV_LOG(ERR,
9923                         "unsupported ether_type(0x%04x) in control packet filter.",
9924                         filter->ether_type);
9925                 return -EINVAL;
9926         }
9927         if (filter->ether_type == ETHER_TYPE_VLAN)
9928                 PMD_DRV_LOG(WARNING,
9929                         "filter vlan ether_type in first tag is not supported.");
9930
9931         /* Check if there is the filter in SW list */
9932         memset(&check_filter, 0, sizeof(check_filter));
9933         i40e_ethertype_filter_convert(filter, &check_filter);
9934         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9935                                                &check_filter.input);
9936         if (add && node) {
9937                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9938                 return -EINVAL;
9939         }
9940
9941         if (!add && !node) {
9942                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9943                 return -EINVAL;
9944         }
9945
9946         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9947                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9948         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9949                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9950         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9951
9952         memset(&stats, 0, sizeof(stats));
9953         ret = i40e_aq_add_rem_control_packet_filter(hw,
9954                         filter->mac_addr.addr_bytes,
9955                         filter->ether_type, flags,
9956                         pf->main_vsi->seid,
9957                         filter->queue, add, &stats, NULL);
9958
9959         PMD_DRV_LOG(INFO,
9960                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9961                 ret, stats.mac_etype_used, stats.etype_used,
9962                 stats.mac_etype_free, stats.etype_free);
9963         if (ret < 0)
9964                 return -ENOSYS;
9965
9966         /* Add or delete a filter in SW list */
9967         if (add) {
9968                 ethertype_filter = rte_zmalloc("ethertype_filter",
9969                                        sizeof(*ethertype_filter), 0);
9970                 if (ethertype_filter == NULL) {
9971                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9972                         return -ENOMEM;
9973                 }
9974
9975                 rte_memcpy(ethertype_filter, &check_filter,
9976                            sizeof(check_filter));
9977                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9978                 if (ret < 0)
9979                         rte_free(ethertype_filter);
9980         } else {
9981                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9982         }
9983
9984         return ret;
9985 }
9986
9987 /*
9988  * Handle operations for ethertype filter.
9989  */
9990 static int
9991 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9992                                 enum rte_filter_op filter_op,
9993                                 void *arg)
9994 {
9995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9996         int ret = 0;
9997
9998         if (filter_op == RTE_ETH_FILTER_NOP)
9999                 return ret;
10000
10001         if (arg == NULL) {
10002                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10003                             filter_op);
10004                 return -EINVAL;
10005         }
10006
10007         switch (filter_op) {
10008         case RTE_ETH_FILTER_ADD:
10009                 ret = i40e_ethertype_filter_set(pf,
10010                         (struct rte_eth_ethertype_filter *)arg,
10011                         TRUE);
10012                 break;
10013         case RTE_ETH_FILTER_DELETE:
10014                 ret = i40e_ethertype_filter_set(pf,
10015                         (struct rte_eth_ethertype_filter *)arg,
10016                         FALSE);
10017                 break;
10018         default:
10019                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10020                 ret = -ENOSYS;
10021                 break;
10022         }
10023         return ret;
10024 }
10025
10026 static int
10027 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10028                      enum rte_filter_type filter_type,
10029                      enum rte_filter_op filter_op,
10030                      void *arg)
10031 {
10032         int ret = 0;
10033
10034         if (dev == NULL)
10035                 return -EINVAL;
10036
10037         switch (filter_type) {
10038         case RTE_ETH_FILTER_NONE:
10039                 /* For global configuration */
10040                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10041                 break;
10042         case RTE_ETH_FILTER_HASH:
10043                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10044                 break;
10045         case RTE_ETH_FILTER_MACVLAN:
10046                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10047                 break;
10048         case RTE_ETH_FILTER_ETHERTYPE:
10049                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10050                 break;
10051         case RTE_ETH_FILTER_TUNNEL:
10052                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10053                 break;
10054         case RTE_ETH_FILTER_FDIR:
10055                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10056                 break;
10057         case RTE_ETH_FILTER_GENERIC:
10058                 if (filter_op != RTE_ETH_FILTER_GET)
10059                         return -EINVAL;
10060                 *(const void **)arg = &i40e_flow_ops;
10061                 break;
10062         default:
10063                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10064                                                         filter_type);
10065                 ret = -EINVAL;
10066                 break;
10067         }
10068
10069         return ret;
10070 }
10071
10072 /*
10073  * Check and enable Extended Tag.
10074  * Enabling Extended Tag is important for 40G performance.
10075  */
10076 static void
10077 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10078 {
10079         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10080         uint32_t buf = 0;
10081         int ret;
10082
10083         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10084                                       PCI_DEV_CAP_REG);
10085         if (ret < 0) {
10086                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10087                             PCI_DEV_CAP_REG);
10088                 return;
10089         }
10090         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10091                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10092                 return;
10093         }
10094
10095         buf = 0;
10096         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10097                                       PCI_DEV_CTRL_REG);
10098         if (ret < 0) {
10099                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10100                             PCI_DEV_CTRL_REG);
10101                 return;
10102         }
10103         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10104                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10105                 return;
10106         }
10107         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10108         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10109                                        PCI_DEV_CTRL_REG);
10110         if (ret < 0) {
10111                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10112                             PCI_DEV_CTRL_REG);
10113                 return;
10114         }
10115 }
10116
10117 /*
10118  * As some registers wouldn't be reset unless a global hardware reset,
10119  * hardware initialization is needed to put those registers into an
10120  * expected initial state.
10121  */
10122 static void
10123 i40e_hw_init(struct rte_eth_dev *dev)
10124 {
10125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10126
10127         i40e_enable_extended_tag(dev);
10128
10129         /* clear the PF Queue Filter control register */
10130         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10131
10132         /* Disable symmetric hash per port */
10133         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10134 }
10135
10136 /*
10137  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10138  * however this function will return only one highest pctype index,
10139  * which is not quite correct. This is known problem of i40e driver
10140  * and needs to be fixed later.
10141  */
10142 enum i40e_filter_pctype
10143 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10144 {
10145         int i;
10146         uint64_t pctype_mask;
10147
10148         if (flow_type < I40E_FLOW_TYPE_MAX) {
10149                 pctype_mask = adapter->pctypes_tbl[flow_type];
10150                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10151                         if (pctype_mask & (1ULL << i))
10152                                 return (enum i40e_filter_pctype)i;
10153                 }
10154         }
10155         return I40E_FILTER_PCTYPE_INVALID;
10156 }
10157
10158 uint16_t
10159 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10160                         enum i40e_filter_pctype pctype)
10161 {
10162         uint16_t flowtype;
10163         uint64_t pctype_mask = 1ULL << pctype;
10164
10165         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10166              flowtype++) {
10167                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10168                         return flowtype;
10169         }
10170
10171         return RTE_ETH_FLOW_UNKNOWN;
10172 }
10173
10174 /*
10175  * On X710, performance number is far from the expectation on recent firmware
10176  * versions; on XL710, performance number is also far from the expectation on
10177  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10178  * mode is enabled and port MAC address is equal to the packet destination MAC
10179  * address. The fix for this issue may not be integrated in the following
10180  * firmware version. So the workaround in software driver is needed. It needs
10181  * to modify the initial values of 3 internal only registers for both X710 and
10182  * XL710. Note that the values for X710 or XL710 could be different, and the
10183  * workaround can be removed when it is fixed in firmware in the future.
10184  */
10185
10186 /* For both X710 and XL710 */
10187 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10188 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10189 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10190
10191 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10192 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10193
10194 /* For X722 */
10195 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10196 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10197
10198 /* For X710 */
10199 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10200 /* For XL710 */
10201 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10202 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10203
10204 /*
10205  * GL_SWR_PM_UP_THR:
10206  * The value is not impacted from the link speed, its value is set according
10207  * to the total number of ports for a better pipe-monitor configuration.
10208  */
10209 static bool
10210 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10211 {
10212 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10213                 .device_id = (dev),   \
10214                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10215
10216 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10217                 .device_id = (dev),   \
10218                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10219
10220         static const struct {
10221                 uint16_t device_id;
10222                 uint32_t val;
10223         } swr_pm_table[] = {
10224                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10225                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10226                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10227                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10228
10229                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10230                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10231                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10232                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10233                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10234                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10235                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10236         };
10237         uint32_t i;
10238
10239         if (value == NULL) {
10240                 PMD_DRV_LOG(ERR, "value is NULL");
10241                 return false;
10242         }
10243
10244         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10245                 if (hw->device_id == swr_pm_table[i].device_id) {
10246                         *value = swr_pm_table[i].val;
10247
10248                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10249                                     "value - 0x%08x",
10250                                     hw->device_id, *value);
10251                         return true;
10252                 }
10253         }
10254
10255         return false;
10256 }
10257
10258 static int
10259 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10260 {
10261         enum i40e_status_code status;
10262         struct i40e_aq_get_phy_abilities_resp phy_ab;
10263         int ret = -ENOTSUP;
10264         int retries = 0;
10265
10266         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10267                                               NULL);
10268
10269         while (status) {
10270                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10271                         status);
10272                 retries++;
10273                 rte_delay_us(100000);
10274                 if  (retries < 5)
10275                         status = i40e_aq_get_phy_capabilities(hw, false,
10276                                         true, &phy_ab, NULL);
10277                 else
10278                         return ret;
10279         }
10280         return 0;
10281 }
10282
10283 static void
10284 i40e_configure_registers(struct i40e_hw *hw)
10285 {
10286         static struct {
10287                 uint32_t addr;
10288                 uint64_t val;
10289         } reg_table[] = {
10290                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10291                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10292                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10293         };
10294         uint64_t reg;
10295         uint32_t i;
10296         int ret;
10297
10298         for (i = 0; i < RTE_DIM(reg_table); i++) {
10299                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10300                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10301                                 reg_table[i].val =
10302                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10303                         else /* For X710/XL710/XXV710 */
10304                                 if (hw->aq.fw_maj_ver < 6)
10305                                         reg_table[i].val =
10306                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10307                                 else
10308                                         reg_table[i].val =
10309                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10310                 }
10311
10312                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10313                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10314                                 reg_table[i].val =
10315                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10316                         else /* For X710/XL710/XXV710 */
10317                                 reg_table[i].val =
10318                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10319                 }
10320
10321                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10322                         uint32_t cfg_val;
10323
10324                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10325                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10326                                             "GL_SWR_PM_UP_THR value fixup",
10327                                             hw->device_id);
10328                                 continue;
10329                         }
10330
10331                         reg_table[i].val = cfg_val;
10332                 }
10333
10334                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10335                                                         &reg, NULL);
10336                 if (ret < 0) {
10337                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10338                                                         reg_table[i].addr);
10339                         break;
10340                 }
10341                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10342                                                 reg_table[i].addr, reg);
10343                 if (reg == reg_table[i].val)
10344                         continue;
10345
10346                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10347                                                 reg_table[i].val, NULL);
10348                 if (ret < 0) {
10349                         PMD_DRV_LOG(ERR,
10350                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10351                                 reg_table[i].val, reg_table[i].addr);
10352                         break;
10353                 }
10354                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10355                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10356         }
10357 }
10358
10359 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10360 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10361 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10362 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10363 static int
10364 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10365 {
10366         uint32_t reg;
10367         int ret;
10368
10369         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10370                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10371                 return -EINVAL;
10372         }
10373
10374         /* Configure for double VLAN RX stripping */
10375         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10376         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10377                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10378                 ret = i40e_aq_debug_write_register(hw,
10379                                                    I40E_VSI_TSR(vsi->vsi_id),
10380                                                    reg, NULL);
10381                 if (ret < 0) {
10382                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10383                                     vsi->vsi_id);
10384                         return I40E_ERR_CONFIG;
10385                 }
10386         }
10387
10388         /* Configure for double VLAN TX insertion */
10389         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10390         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10391                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10392                 ret = i40e_aq_debug_write_register(hw,
10393                                                    I40E_VSI_L2TAGSTXVALID(
10394                                                    vsi->vsi_id), reg, NULL);
10395                 if (ret < 0) {
10396                         PMD_DRV_LOG(ERR,
10397                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10398                                 vsi->vsi_id);
10399                         return I40E_ERR_CONFIG;
10400                 }
10401         }
10402
10403         return 0;
10404 }
10405
10406 /**
10407  * i40e_aq_add_mirror_rule
10408  * @hw: pointer to the hardware structure
10409  * @seid: VEB seid to add mirror rule to
10410  * @dst_id: destination vsi seid
10411  * @entries: Buffer which contains the entities to be mirrored
10412  * @count: number of entities contained in the buffer
10413  * @rule_id:the rule_id of the rule to be added
10414  *
10415  * Add a mirror rule for a given veb.
10416  *
10417  **/
10418 static enum i40e_status_code
10419 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10420                         uint16_t seid, uint16_t dst_id,
10421                         uint16_t rule_type, uint16_t *entries,
10422                         uint16_t count, uint16_t *rule_id)
10423 {
10424         struct i40e_aq_desc desc;
10425         struct i40e_aqc_add_delete_mirror_rule cmd;
10426         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10427                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10428                 &desc.params.raw;
10429         uint16_t buff_len;
10430         enum i40e_status_code status;
10431
10432         i40e_fill_default_direct_cmd_desc(&desc,
10433                                           i40e_aqc_opc_add_mirror_rule);
10434         memset(&cmd, 0, sizeof(cmd));
10435
10436         buff_len = sizeof(uint16_t) * count;
10437         desc.datalen = rte_cpu_to_le_16(buff_len);
10438         if (buff_len > 0)
10439                 desc.flags |= rte_cpu_to_le_16(
10440                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10441         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10442                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10443         cmd.num_entries = rte_cpu_to_le_16(count);
10444         cmd.seid = rte_cpu_to_le_16(seid);
10445         cmd.destination = rte_cpu_to_le_16(dst_id);
10446
10447         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10448         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10449         PMD_DRV_LOG(INFO,
10450                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10451                 hw->aq.asq_last_status, resp->rule_id,
10452                 resp->mirror_rules_used, resp->mirror_rules_free);
10453         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10454
10455         return status;
10456 }
10457
10458 /**
10459  * i40e_aq_del_mirror_rule
10460  * @hw: pointer to the hardware structure
10461  * @seid: VEB seid to add mirror rule to
10462  * @entries: Buffer which contains the entities to be mirrored
10463  * @count: number of entities contained in the buffer
10464  * @rule_id:the rule_id of the rule to be delete
10465  *
10466  * Delete a mirror rule for a given veb.
10467  *
10468  **/
10469 static enum i40e_status_code
10470 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10471                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10472                 uint16_t count, uint16_t rule_id)
10473 {
10474         struct i40e_aq_desc desc;
10475         struct i40e_aqc_add_delete_mirror_rule cmd;
10476         uint16_t buff_len = 0;
10477         enum i40e_status_code status;
10478         void *buff = NULL;
10479
10480         i40e_fill_default_direct_cmd_desc(&desc,
10481                                           i40e_aqc_opc_delete_mirror_rule);
10482         memset(&cmd, 0, sizeof(cmd));
10483         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10484                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10485                                                           I40E_AQ_FLAG_RD));
10486                 cmd.num_entries = count;
10487                 buff_len = sizeof(uint16_t) * count;
10488                 desc.datalen = rte_cpu_to_le_16(buff_len);
10489                 buff = (void *)entries;
10490         } else
10491                 /* rule id is filled in destination field for deleting mirror rule */
10492                 cmd.destination = rte_cpu_to_le_16(rule_id);
10493
10494         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10495                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10496         cmd.seid = rte_cpu_to_le_16(seid);
10497
10498         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10499         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10500
10501         return status;
10502 }
10503
10504 /**
10505  * i40e_mirror_rule_set
10506  * @dev: pointer to the hardware structure
10507  * @mirror_conf: mirror rule info
10508  * @sw_id: mirror rule's sw_id
10509  * @on: enable/disable
10510  *
10511  * set a mirror rule.
10512  *
10513  **/
10514 static int
10515 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10516                         struct rte_eth_mirror_conf *mirror_conf,
10517                         uint8_t sw_id, uint8_t on)
10518 {
10519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10520         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10521         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10522         struct i40e_mirror_rule *parent = NULL;
10523         uint16_t seid, dst_seid, rule_id;
10524         uint16_t i, j = 0;
10525         int ret;
10526
10527         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10528
10529         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10530                 PMD_DRV_LOG(ERR,
10531                         "mirror rule can not be configured without veb or vfs.");
10532                 return -ENOSYS;
10533         }
10534         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10535                 PMD_DRV_LOG(ERR, "mirror table is full.");
10536                 return -ENOSPC;
10537         }
10538         if (mirror_conf->dst_pool > pf->vf_num) {
10539                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10540                                  mirror_conf->dst_pool);
10541                 return -EINVAL;
10542         }
10543
10544         seid = pf->main_vsi->veb->seid;
10545
10546         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10547                 if (sw_id <= it->index) {
10548                         mirr_rule = it;
10549                         break;
10550                 }
10551                 parent = it;
10552         }
10553         if (mirr_rule && sw_id == mirr_rule->index) {
10554                 if (on) {
10555                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10556                         return -EEXIST;
10557                 } else {
10558                         ret = i40e_aq_del_mirror_rule(hw, seid,
10559                                         mirr_rule->rule_type,
10560                                         mirr_rule->entries,
10561                                         mirr_rule->num_entries, mirr_rule->id);
10562                         if (ret < 0) {
10563                                 PMD_DRV_LOG(ERR,
10564                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10565                                         ret, hw->aq.asq_last_status);
10566                                 return -ENOSYS;
10567                         }
10568                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10569                         rte_free(mirr_rule);
10570                         pf->nb_mirror_rule--;
10571                         return 0;
10572                 }
10573         } else if (!on) {
10574                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10575                 return -ENOENT;
10576         }
10577
10578         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10579                                 sizeof(struct i40e_mirror_rule) , 0);
10580         if (!mirr_rule) {
10581                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10582                 return I40E_ERR_NO_MEMORY;
10583         }
10584         switch (mirror_conf->rule_type) {
10585         case ETH_MIRROR_VLAN:
10586                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10587                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10588                                 mirr_rule->entries[j] =
10589                                         mirror_conf->vlan.vlan_id[i];
10590                                 j++;
10591                         }
10592                 }
10593                 if (j == 0) {
10594                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10595                         rte_free(mirr_rule);
10596                         return -EINVAL;
10597                 }
10598                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10599                 break;
10600         case ETH_MIRROR_VIRTUAL_POOL_UP:
10601         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10602                 /* check if the specified pool bit is out of range */
10603                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10604                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10605                         rte_free(mirr_rule);
10606                         return -EINVAL;
10607                 }
10608                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10609                         if (mirror_conf->pool_mask & (1ULL << i)) {
10610                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10611                                 j++;
10612                         }
10613                 }
10614                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10615                         /* add pf vsi to entries */
10616                         mirr_rule->entries[j] = pf->main_vsi_seid;
10617                         j++;
10618                 }
10619                 if (j == 0) {
10620                         PMD_DRV_LOG(ERR, "pool is not specified.");
10621                         rte_free(mirr_rule);
10622                         return -EINVAL;
10623                 }
10624                 /* egress and ingress in aq commands means from switch but not port */
10625                 mirr_rule->rule_type =
10626                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10627                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10628                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10629                 break;
10630         case ETH_MIRROR_UPLINK_PORT:
10631                 /* egress and ingress in aq commands means from switch but not port*/
10632                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10633                 break;
10634         case ETH_MIRROR_DOWNLINK_PORT:
10635                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10636                 break;
10637         default:
10638                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10639                         mirror_conf->rule_type);
10640                 rte_free(mirr_rule);
10641                 return -EINVAL;
10642         }
10643
10644         /* If the dst_pool is equal to vf_num, consider it as PF */
10645         if (mirror_conf->dst_pool == pf->vf_num)
10646                 dst_seid = pf->main_vsi_seid;
10647         else
10648                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10649
10650         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10651                                       mirr_rule->rule_type, mirr_rule->entries,
10652                                       j, &rule_id);
10653         if (ret < 0) {
10654                 PMD_DRV_LOG(ERR,
10655                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10656                         ret, hw->aq.asq_last_status);
10657                 rte_free(mirr_rule);
10658                 return -ENOSYS;
10659         }
10660
10661         mirr_rule->index = sw_id;
10662         mirr_rule->num_entries = j;
10663         mirr_rule->id = rule_id;
10664         mirr_rule->dst_vsi_seid = dst_seid;
10665
10666         if (parent)
10667                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10668         else
10669                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10670
10671         pf->nb_mirror_rule++;
10672         return 0;
10673 }
10674
10675 /**
10676  * i40e_mirror_rule_reset
10677  * @dev: pointer to the device
10678  * @sw_id: mirror rule's sw_id
10679  *
10680  * reset a mirror rule.
10681  *
10682  **/
10683 static int
10684 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10685 {
10686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10688         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10689         uint16_t seid;
10690         int ret;
10691
10692         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10693
10694         seid = pf->main_vsi->veb->seid;
10695
10696         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10697                 if (sw_id == it->index) {
10698                         mirr_rule = it;
10699                         break;
10700                 }
10701         }
10702         if (mirr_rule) {
10703                 ret = i40e_aq_del_mirror_rule(hw, seid,
10704                                 mirr_rule->rule_type,
10705                                 mirr_rule->entries,
10706                                 mirr_rule->num_entries, mirr_rule->id);
10707                 if (ret < 0) {
10708                         PMD_DRV_LOG(ERR,
10709                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10710                                 ret, hw->aq.asq_last_status);
10711                         return -ENOSYS;
10712                 }
10713                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10714                 rte_free(mirr_rule);
10715                 pf->nb_mirror_rule--;
10716         } else {
10717                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10718                 return -ENOENT;
10719         }
10720         return 0;
10721 }
10722
10723 static uint64_t
10724 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10725 {
10726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10727         uint64_t systim_cycles;
10728
10729         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10730         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10731                         << 32;
10732
10733         return systim_cycles;
10734 }
10735
10736 static uint64_t
10737 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10738 {
10739         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10740         uint64_t rx_tstamp;
10741
10742         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10743         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10744                         << 32;
10745
10746         return rx_tstamp;
10747 }
10748
10749 static uint64_t
10750 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10751 {
10752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10753         uint64_t tx_tstamp;
10754
10755         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10756         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10757                         << 32;
10758
10759         return tx_tstamp;
10760 }
10761
10762 static void
10763 i40e_start_timecounters(struct rte_eth_dev *dev)
10764 {
10765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10766         struct i40e_adapter *adapter =
10767                         (struct i40e_adapter *)dev->data->dev_private;
10768         struct rte_eth_link link;
10769         uint32_t tsync_inc_l;
10770         uint32_t tsync_inc_h;
10771
10772         /* Get current link speed. */
10773         i40e_dev_link_update(dev, 1);
10774         rte_eth_linkstatus_get(dev, &link);
10775
10776         switch (link.link_speed) {
10777         case ETH_SPEED_NUM_40G:
10778                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10779                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10780                 break;
10781         case ETH_SPEED_NUM_10G:
10782                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10783                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10784                 break;
10785         case ETH_SPEED_NUM_1G:
10786                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10787                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10788                 break;
10789         default:
10790                 tsync_inc_l = 0x0;
10791                 tsync_inc_h = 0x0;
10792         }
10793
10794         /* Set the timesync increment value. */
10795         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10796         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10797
10798         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10799         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10800         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10801
10802         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10803         adapter->systime_tc.cc_shift = 0;
10804         adapter->systime_tc.nsec_mask = 0;
10805
10806         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10807         adapter->rx_tstamp_tc.cc_shift = 0;
10808         adapter->rx_tstamp_tc.nsec_mask = 0;
10809
10810         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10811         adapter->tx_tstamp_tc.cc_shift = 0;
10812         adapter->tx_tstamp_tc.nsec_mask = 0;
10813 }
10814
10815 static int
10816 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10817 {
10818         struct i40e_adapter *adapter =
10819                         (struct i40e_adapter *)dev->data->dev_private;
10820
10821         adapter->systime_tc.nsec += delta;
10822         adapter->rx_tstamp_tc.nsec += delta;
10823         adapter->tx_tstamp_tc.nsec += delta;
10824
10825         return 0;
10826 }
10827
10828 static int
10829 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10830 {
10831         uint64_t ns;
10832         struct i40e_adapter *adapter =
10833                         (struct i40e_adapter *)dev->data->dev_private;
10834
10835         ns = rte_timespec_to_ns(ts);
10836
10837         /* Set the timecounters to a new value. */
10838         adapter->systime_tc.nsec = ns;
10839         adapter->rx_tstamp_tc.nsec = ns;
10840         adapter->tx_tstamp_tc.nsec = ns;
10841
10842         return 0;
10843 }
10844
10845 static int
10846 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10847 {
10848         uint64_t ns, systime_cycles;
10849         struct i40e_adapter *adapter =
10850                         (struct i40e_adapter *)dev->data->dev_private;
10851
10852         systime_cycles = i40e_read_systime_cyclecounter(dev);
10853         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10854         *ts = rte_ns_to_timespec(ns);
10855
10856         return 0;
10857 }
10858
10859 static int
10860 i40e_timesync_enable(struct rte_eth_dev *dev)
10861 {
10862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10863         uint32_t tsync_ctl_l;
10864         uint32_t tsync_ctl_h;
10865
10866         /* Stop the timesync system time. */
10867         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10868         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10869         /* Reset the timesync system time value. */
10870         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10871         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10872
10873         i40e_start_timecounters(dev);
10874
10875         /* Clear timesync registers. */
10876         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10877         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10878         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10879         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10880         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10881         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10882
10883         /* Enable timestamping of PTP packets. */
10884         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10885         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10886
10887         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10888         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10889         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10890
10891         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10892         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10893
10894         return 0;
10895 }
10896
10897 static int
10898 i40e_timesync_disable(struct rte_eth_dev *dev)
10899 {
10900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10901         uint32_t tsync_ctl_l;
10902         uint32_t tsync_ctl_h;
10903
10904         /* Disable timestamping of transmitted PTP packets. */
10905         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10906         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10907
10908         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10909         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10910
10911         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10912         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10913
10914         /* Reset the timesync increment value. */
10915         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10916         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10917
10918         return 0;
10919 }
10920
10921 static int
10922 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10923                                 struct timespec *timestamp, uint32_t flags)
10924 {
10925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10926         struct i40e_adapter *adapter =
10927                 (struct i40e_adapter *)dev->data->dev_private;
10928
10929         uint32_t sync_status;
10930         uint32_t index = flags & 0x03;
10931         uint64_t rx_tstamp_cycles;
10932         uint64_t ns;
10933
10934         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10935         if ((sync_status & (1 << index)) == 0)
10936                 return -EINVAL;
10937
10938         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10939         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10940         *timestamp = rte_ns_to_timespec(ns);
10941
10942         return 0;
10943 }
10944
10945 static int
10946 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10947                                 struct timespec *timestamp)
10948 {
10949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10950         struct i40e_adapter *adapter =
10951                 (struct i40e_adapter *)dev->data->dev_private;
10952
10953         uint32_t sync_status;
10954         uint64_t tx_tstamp_cycles;
10955         uint64_t ns;
10956
10957         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10958         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10959                 return -EINVAL;
10960
10961         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10962         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10963         *timestamp = rte_ns_to_timespec(ns);
10964
10965         return 0;
10966 }
10967
10968 /*
10969  * i40e_parse_dcb_configure - parse dcb configure from user
10970  * @dev: the device being configured
10971  * @dcb_cfg: pointer of the result of parse
10972  * @*tc_map: bit map of enabled traffic classes
10973  *
10974  * Returns 0 on success, negative value on failure
10975  */
10976 static int
10977 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10978                          struct i40e_dcbx_config *dcb_cfg,
10979                          uint8_t *tc_map)
10980 {
10981         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10982         uint8_t i, tc_bw, bw_lf;
10983
10984         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10985
10986         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10987         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10988                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10989                 return -EINVAL;
10990         }
10991
10992         /* assume each tc has the same bw */
10993         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10994         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10995                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10996         /* to ensure the sum of tcbw is equal to 100 */
10997         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10998         for (i = 0; i < bw_lf; i++)
10999                 dcb_cfg->etscfg.tcbwtable[i]++;
11000
11001         /* assume each tc has the same Transmission Selection Algorithm */
11002         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11003                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11004
11005         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11006                 dcb_cfg->etscfg.prioritytable[i] =
11007                                 dcb_rx_conf->dcb_tc[i];
11008
11009         /* FW needs one App to configure HW */
11010         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11011         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11012         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11013         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11014
11015         if (dcb_rx_conf->nb_tcs == 0)
11016                 *tc_map = 1; /* tc0 only */
11017         else
11018                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11019
11020         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11021                 dcb_cfg->pfc.willing = 0;
11022                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11023                 dcb_cfg->pfc.pfcenable = *tc_map;
11024         }
11025         return 0;
11026 }
11027
11028
11029 static enum i40e_status_code
11030 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11031                               struct i40e_aqc_vsi_properties_data *info,
11032                               uint8_t enabled_tcmap)
11033 {
11034         enum i40e_status_code ret;
11035         int i, total_tc = 0;
11036         uint16_t qpnum_per_tc, bsf, qp_idx;
11037         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11038         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11039         uint16_t used_queues;
11040
11041         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11042         if (ret != I40E_SUCCESS)
11043                 return ret;
11044
11045         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11046                 if (enabled_tcmap & (1 << i))
11047                         total_tc++;
11048         }
11049         if (total_tc == 0)
11050                 total_tc = 1;
11051         vsi->enabled_tc = enabled_tcmap;
11052
11053         /* different VSI has different queues assigned */
11054         if (vsi->type == I40E_VSI_MAIN)
11055                 used_queues = dev_data->nb_rx_queues -
11056                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11057         else if (vsi->type == I40E_VSI_VMDQ2)
11058                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11059         else {
11060                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11061                 return I40E_ERR_NO_AVAILABLE_VSI;
11062         }
11063
11064         qpnum_per_tc = used_queues / total_tc;
11065         /* Number of queues per enabled TC */
11066         if (qpnum_per_tc == 0) {
11067                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11068                 return I40E_ERR_INVALID_QP_ID;
11069         }
11070         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11071                                 I40E_MAX_Q_PER_TC);
11072         bsf = rte_bsf32(qpnum_per_tc);
11073
11074         /**
11075          * Configure TC and queue mapping parameters, for enabled TC,
11076          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11077          * default queue will serve it.
11078          */
11079         qp_idx = 0;
11080         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11081                 if (vsi->enabled_tc & (1 << i)) {
11082                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11083                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11084                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11085                         qp_idx += qpnum_per_tc;
11086                 } else
11087                         info->tc_mapping[i] = 0;
11088         }
11089
11090         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11091         if (vsi->type == I40E_VSI_SRIOV) {
11092                 info->mapping_flags |=
11093                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11094                 for (i = 0; i < vsi->nb_qps; i++)
11095                         info->queue_mapping[i] =
11096                                 rte_cpu_to_le_16(vsi->base_queue + i);
11097         } else {
11098                 info->mapping_flags |=
11099                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11100                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11101         }
11102         info->valid_sections |=
11103                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11104
11105         return I40E_SUCCESS;
11106 }
11107
11108 /*
11109  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11110  * @veb: VEB to be configured
11111  * @tc_map: enabled TC bitmap
11112  *
11113  * Returns 0 on success, negative value on failure
11114  */
11115 static enum i40e_status_code
11116 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11117 {
11118         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11119         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11120         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11121         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11122         enum i40e_status_code ret = I40E_SUCCESS;
11123         int i;
11124         uint32_t bw_max;
11125
11126         /* Check if enabled_tc is same as existing or new TCs */
11127         if (veb->enabled_tc == tc_map)
11128                 return ret;
11129
11130         /* configure tc bandwidth */
11131         memset(&veb_bw, 0, sizeof(veb_bw));
11132         veb_bw.tc_valid_bits = tc_map;
11133         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11134         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11135                 if (tc_map & BIT_ULL(i))
11136                         veb_bw.tc_bw_share_credits[i] = 1;
11137         }
11138         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11139                                                    &veb_bw, NULL);
11140         if (ret) {
11141                 PMD_INIT_LOG(ERR,
11142                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11143                         hw->aq.asq_last_status);
11144                 return ret;
11145         }
11146
11147         memset(&ets_query, 0, sizeof(ets_query));
11148         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11149                                                    &ets_query, NULL);
11150         if (ret != I40E_SUCCESS) {
11151                 PMD_DRV_LOG(ERR,
11152                         "Failed to get switch_comp ETS configuration %u",
11153                         hw->aq.asq_last_status);
11154                 return ret;
11155         }
11156         memset(&bw_query, 0, sizeof(bw_query));
11157         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11158                                                   &bw_query, NULL);
11159         if (ret != I40E_SUCCESS) {
11160                 PMD_DRV_LOG(ERR,
11161                         "Failed to get switch_comp bandwidth configuration %u",
11162                         hw->aq.asq_last_status);
11163                 return ret;
11164         }
11165
11166         /* store and print out BW info */
11167         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11168         veb->bw_info.bw_max = ets_query.tc_bw_max;
11169         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11170         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11171         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11172                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11173                      I40E_16_BIT_WIDTH);
11174         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11175                 veb->bw_info.bw_ets_share_credits[i] =
11176                                 bw_query.tc_bw_share_credits[i];
11177                 veb->bw_info.bw_ets_credits[i] =
11178                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11179                 /* 4 bits per TC, 4th bit is reserved */
11180                 veb->bw_info.bw_ets_max[i] =
11181                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11182                                   RTE_LEN2MASK(3, uint8_t));
11183                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11184                             veb->bw_info.bw_ets_share_credits[i]);
11185                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11186                             veb->bw_info.bw_ets_credits[i]);
11187                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11188                             veb->bw_info.bw_ets_max[i]);
11189         }
11190
11191         veb->enabled_tc = tc_map;
11192
11193         return ret;
11194 }
11195
11196
11197 /*
11198  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11199  * @vsi: VSI to be configured
11200  * @tc_map: enabled TC bitmap
11201  *
11202  * Returns 0 on success, negative value on failure
11203  */
11204 static enum i40e_status_code
11205 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11206 {
11207         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11208         struct i40e_vsi_context ctxt;
11209         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11210         enum i40e_status_code ret = I40E_SUCCESS;
11211         int i;
11212
11213         /* Check if enabled_tc is same as existing or new TCs */
11214         if (vsi->enabled_tc == tc_map)
11215                 return ret;
11216
11217         /* configure tc bandwidth */
11218         memset(&bw_data, 0, sizeof(bw_data));
11219         bw_data.tc_valid_bits = tc_map;
11220         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11221         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11222                 if (tc_map & BIT_ULL(i))
11223                         bw_data.tc_bw_credits[i] = 1;
11224         }
11225         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11226         if (ret) {
11227                 PMD_INIT_LOG(ERR,
11228                         "AQ command Config VSI BW allocation per TC failed = %d",
11229                         hw->aq.asq_last_status);
11230                 goto out;
11231         }
11232         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11233                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11234
11235         /* Update Queue Pairs Mapping for currently enabled UPs */
11236         ctxt.seid = vsi->seid;
11237         ctxt.pf_num = hw->pf_id;
11238         ctxt.vf_num = 0;
11239         ctxt.uplink_seid = vsi->uplink_seid;
11240         ctxt.info = vsi->info;
11241         i40e_get_cap(hw);
11242         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11243         if (ret)
11244                 goto out;
11245
11246         /* Update the VSI after updating the VSI queue-mapping information */
11247         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11248         if (ret) {
11249                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11250                         hw->aq.asq_last_status);
11251                 goto out;
11252         }
11253         /* update the local VSI info with updated queue map */
11254         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11255                                         sizeof(vsi->info.tc_mapping));
11256         rte_memcpy(&vsi->info.queue_mapping,
11257                         &ctxt.info.queue_mapping,
11258                 sizeof(vsi->info.queue_mapping));
11259         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11260         vsi->info.valid_sections = 0;
11261
11262         /* query and update current VSI BW information */
11263         ret = i40e_vsi_get_bw_config(vsi);
11264         if (ret) {
11265                 PMD_INIT_LOG(ERR,
11266                          "Failed updating vsi bw info, err %s aq_err %s",
11267                          i40e_stat_str(hw, ret),
11268                          i40e_aq_str(hw, hw->aq.asq_last_status));
11269                 goto out;
11270         }
11271
11272         vsi->enabled_tc = tc_map;
11273
11274 out:
11275         return ret;
11276 }
11277
11278 /*
11279  * i40e_dcb_hw_configure - program the dcb setting to hw
11280  * @pf: pf the configuration is taken on
11281  * @new_cfg: new configuration
11282  * @tc_map: enabled TC bitmap
11283  *
11284  * Returns 0 on success, negative value on failure
11285  */
11286 static enum i40e_status_code
11287 i40e_dcb_hw_configure(struct i40e_pf *pf,
11288                       struct i40e_dcbx_config *new_cfg,
11289                       uint8_t tc_map)
11290 {
11291         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11292         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11293         struct i40e_vsi *main_vsi = pf->main_vsi;
11294         struct i40e_vsi_list *vsi_list;
11295         enum i40e_status_code ret;
11296         int i;
11297         uint32_t val;
11298
11299         /* Use the FW API if FW > v4.4*/
11300         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11301               (hw->aq.fw_maj_ver >= 5))) {
11302                 PMD_INIT_LOG(ERR,
11303                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11304                 return I40E_ERR_FIRMWARE_API_VERSION;
11305         }
11306
11307         /* Check if need reconfiguration */
11308         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11309                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11310                 return I40E_SUCCESS;
11311         }
11312
11313         /* Copy the new config to the current config */
11314         *old_cfg = *new_cfg;
11315         old_cfg->etsrec = old_cfg->etscfg;
11316         ret = i40e_set_dcb_config(hw);
11317         if (ret) {
11318                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11319                          i40e_stat_str(hw, ret),
11320                          i40e_aq_str(hw, hw->aq.asq_last_status));
11321                 return ret;
11322         }
11323         /* set receive Arbiter to RR mode and ETS scheme by default */
11324         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11325                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11326                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11327                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11328                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11329                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11330                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11331                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11332                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11333                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11334                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11335                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11336                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11337         }
11338         /* get local mib to check whether it is configured correctly */
11339         /* IEEE mode */
11340         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11341         /* Get Local DCB Config */
11342         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11343                                      &hw->local_dcbx_config);
11344
11345         /* if Veb is created, need to update TC of it at first */
11346         if (main_vsi->veb) {
11347                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11348                 if (ret)
11349                         PMD_INIT_LOG(WARNING,
11350                                  "Failed configuring TC for VEB seid=%d",
11351                                  main_vsi->veb->seid);
11352         }
11353         /* Update each VSI */
11354         i40e_vsi_config_tc(main_vsi, tc_map);
11355         if (main_vsi->veb) {
11356                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11357                         /* Beside main VSI and VMDQ VSIs, only enable default
11358                          * TC for other VSIs
11359                          */
11360                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11361                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11362                                                          tc_map);
11363                         else
11364                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11365                                                          I40E_DEFAULT_TCMAP);
11366                         if (ret)
11367                                 PMD_INIT_LOG(WARNING,
11368                                         "Failed configuring TC for VSI seid=%d",
11369                                         vsi_list->vsi->seid);
11370                         /* continue */
11371                 }
11372         }
11373         return I40E_SUCCESS;
11374 }
11375
11376 /*
11377  * i40e_dcb_init_configure - initial dcb config
11378  * @dev: device being configured
11379  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11380  *
11381  * Returns 0 on success, negative value on failure
11382  */
11383 int
11384 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11385 {
11386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11388         int i, ret = 0;
11389
11390         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11391                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11392                 return -ENOTSUP;
11393         }
11394
11395         /* DCB initialization:
11396          * Update DCB configuration from the Firmware and configure
11397          * LLDP MIB change event.
11398          */
11399         if (sw_dcb == TRUE) {
11400                 /* When using NVM 6.01 or later, the RX data path does
11401                  * not hang if the FW LLDP is stopped.
11402                  */
11403                 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11404                     ((hw->nvm.version >> 4) & 0xff) >= 1) {
11405                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11406                         if (ret != I40E_SUCCESS)
11407                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11408                 }
11409
11410                 ret = i40e_init_dcb(hw);
11411                 /* If lldp agent is stopped, the return value from
11412                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11413                  * adminq status. Otherwise, it should return success.
11414                  */
11415                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11416                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11417                         memset(&hw->local_dcbx_config, 0,
11418                                 sizeof(struct i40e_dcbx_config));
11419                         /* set dcb default configuration */
11420                         hw->local_dcbx_config.etscfg.willing = 0;
11421                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11422                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11423                         hw->local_dcbx_config.etscfg.tsatable[0] =
11424                                                 I40E_IEEE_TSA_ETS;
11425                         /* all UPs mapping to TC0 */
11426                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11427                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11428                         hw->local_dcbx_config.etsrec =
11429                                 hw->local_dcbx_config.etscfg;
11430                         hw->local_dcbx_config.pfc.willing = 0;
11431                         hw->local_dcbx_config.pfc.pfccap =
11432                                                 I40E_MAX_TRAFFIC_CLASS;
11433                         /* FW needs one App to configure HW */
11434                         hw->local_dcbx_config.numapps = 1;
11435                         hw->local_dcbx_config.app[0].selector =
11436                                                 I40E_APP_SEL_ETHTYPE;
11437                         hw->local_dcbx_config.app[0].priority = 3;
11438                         hw->local_dcbx_config.app[0].protocolid =
11439                                                 I40E_APP_PROTOID_FCOE;
11440                         ret = i40e_set_dcb_config(hw);
11441                         if (ret) {
11442                                 PMD_INIT_LOG(ERR,
11443                                         "default dcb config fails. err = %d, aq_err = %d.",
11444                                         ret, hw->aq.asq_last_status);
11445                                 return -ENOSYS;
11446                         }
11447                 } else {
11448                         PMD_INIT_LOG(ERR,
11449                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11450                                 ret, hw->aq.asq_last_status);
11451                         return -ENOTSUP;
11452                 }
11453         } else {
11454                 ret = i40e_aq_start_lldp(hw, NULL);
11455                 if (ret != I40E_SUCCESS)
11456                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11457
11458                 ret = i40e_init_dcb(hw);
11459                 if (!ret) {
11460                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11461                                 PMD_INIT_LOG(ERR,
11462                                         "HW doesn't support DCBX offload.");
11463                                 return -ENOTSUP;
11464                         }
11465                 } else {
11466                         PMD_INIT_LOG(ERR,
11467                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11468                                 ret, hw->aq.asq_last_status);
11469                         return -ENOTSUP;
11470                 }
11471         }
11472         return 0;
11473 }
11474
11475 /*
11476  * i40e_dcb_setup - setup dcb related config
11477  * @dev: device being configured
11478  *
11479  * Returns 0 on success, negative value on failure
11480  */
11481 static int
11482 i40e_dcb_setup(struct rte_eth_dev *dev)
11483 {
11484         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11485         struct i40e_dcbx_config dcb_cfg;
11486         uint8_t tc_map = 0;
11487         int ret = 0;
11488
11489         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11490                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11491                 return -ENOTSUP;
11492         }
11493
11494         if (pf->vf_num != 0)
11495                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11496
11497         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11498         if (ret) {
11499                 PMD_INIT_LOG(ERR, "invalid dcb config");
11500                 return -EINVAL;
11501         }
11502         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11503         if (ret) {
11504                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11505                 return -ENOSYS;
11506         }
11507
11508         return 0;
11509 }
11510
11511 static int
11512 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11513                       struct rte_eth_dcb_info *dcb_info)
11514 {
11515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11517         struct i40e_vsi *vsi = pf->main_vsi;
11518         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11519         uint16_t bsf, tc_mapping;
11520         int i, j = 0;
11521
11522         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11523                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11524         else
11525                 dcb_info->nb_tcs = 1;
11526         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11527                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11528         for (i = 0; i < dcb_info->nb_tcs; i++)
11529                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11530
11531         /* get queue mapping if vmdq is disabled */
11532         if (!pf->nb_cfg_vmdq_vsi) {
11533                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11534                         if (!(vsi->enabled_tc & (1 << i)))
11535                                 continue;
11536                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11537                         dcb_info->tc_queue.tc_rxq[j][i].base =
11538                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11539                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11540                         dcb_info->tc_queue.tc_txq[j][i].base =
11541                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11542                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11543                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11544                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11545                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11546                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11547                 }
11548                 return 0;
11549         }
11550
11551         /* get queue mapping if vmdq is enabled */
11552         do {
11553                 vsi = pf->vmdq[j].vsi;
11554                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11555                         if (!(vsi->enabled_tc & (1 << i)))
11556                                 continue;
11557                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11558                         dcb_info->tc_queue.tc_rxq[j][i].base =
11559                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11560                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11561                         dcb_info->tc_queue.tc_txq[j][i].base =
11562                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11563                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11564                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11565                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11566                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11567                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11568                 }
11569                 j++;
11570         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11571         return 0;
11572 }
11573
11574 static int
11575 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11576 {
11577         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11578         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11579         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11580         uint16_t msix_intr;
11581
11582         msix_intr = intr_handle->intr_vec[queue_id];
11583         if (msix_intr == I40E_MISC_VEC_ID)
11584                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11585                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11586                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11587                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11588         else
11589                 I40E_WRITE_REG(hw,
11590                                I40E_PFINT_DYN_CTLN(msix_intr -
11591                                                    I40E_RX_VEC_START),
11592                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11593                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11594                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11595
11596         I40E_WRITE_FLUSH(hw);
11597         rte_intr_enable(&pci_dev->intr_handle);
11598
11599         return 0;
11600 }
11601
11602 static int
11603 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11604 {
11605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11608         uint16_t msix_intr;
11609
11610         msix_intr = intr_handle->intr_vec[queue_id];
11611         if (msix_intr == I40E_MISC_VEC_ID)
11612                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11613                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11614         else
11615                 I40E_WRITE_REG(hw,
11616                                I40E_PFINT_DYN_CTLN(msix_intr -
11617                                                    I40E_RX_VEC_START),
11618                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11619         I40E_WRITE_FLUSH(hw);
11620
11621         return 0;
11622 }
11623
11624 /**
11625  * This function is used to check if the register is valid.
11626  * Below is the valid registers list for X722 only:
11627  * 0x2b800--0x2bb00
11628  * 0x38700--0x38a00
11629  * 0x3d800--0x3db00
11630  * 0x208e00--0x209000
11631  * 0x20be00--0x20c000
11632  * 0x263c00--0x264000
11633  * 0x265c00--0x266000
11634  */
11635 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11636 {
11637         if ((type != I40E_MAC_X722) &&
11638             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11639              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11640              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11641              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11642              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11643              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11644              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11645                 return 0;
11646         else
11647                 return 1;
11648 }
11649
11650 static int i40e_get_regs(struct rte_eth_dev *dev,
11651                          struct rte_dev_reg_info *regs)
11652 {
11653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11654         uint32_t *ptr_data = regs->data;
11655         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11656         const struct i40e_reg_info *reg_info;
11657
11658         if (ptr_data == NULL) {
11659                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11660                 regs->width = sizeof(uint32_t);
11661                 return 0;
11662         }
11663
11664         /* The first few registers have to be read using AQ operations */
11665         reg_idx = 0;
11666         while (i40e_regs_adminq[reg_idx].name) {
11667                 reg_info = &i40e_regs_adminq[reg_idx++];
11668                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11669                         for (arr_idx2 = 0;
11670                                         arr_idx2 <= reg_info->count2;
11671                                         arr_idx2++) {
11672                                 reg_offset = arr_idx * reg_info->stride1 +
11673                                         arr_idx2 * reg_info->stride2;
11674                                 reg_offset += reg_info->base_addr;
11675                                 ptr_data[reg_offset >> 2] =
11676                                         i40e_read_rx_ctl(hw, reg_offset);
11677                         }
11678         }
11679
11680         /* The remaining registers can be read using primitives */
11681         reg_idx = 0;
11682         while (i40e_regs_others[reg_idx].name) {
11683                 reg_info = &i40e_regs_others[reg_idx++];
11684                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11685                         for (arr_idx2 = 0;
11686                                         arr_idx2 <= reg_info->count2;
11687                                         arr_idx2++) {
11688                                 reg_offset = arr_idx * reg_info->stride1 +
11689                                         arr_idx2 * reg_info->stride2;
11690                                 reg_offset += reg_info->base_addr;
11691                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11692                                         ptr_data[reg_offset >> 2] = 0;
11693                                 else
11694                                         ptr_data[reg_offset >> 2] =
11695                                                 I40E_READ_REG(hw, reg_offset);
11696                         }
11697         }
11698
11699         return 0;
11700 }
11701
11702 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11703 {
11704         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11705
11706         /* Convert word count to byte count */
11707         return hw->nvm.sr_size << 1;
11708 }
11709
11710 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11711                            struct rte_dev_eeprom_info *eeprom)
11712 {
11713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11714         uint16_t *data = eeprom->data;
11715         uint16_t offset, length, cnt_words;
11716         int ret_code;
11717
11718         offset = eeprom->offset >> 1;
11719         length = eeprom->length >> 1;
11720         cnt_words = length;
11721
11722         if (offset > hw->nvm.sr_size ||
11723                 offset + length > hw->nvm.sr_size) {
11724                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11725                 return -EINVAL;
11726         }
11727
11728         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11729
11730         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11731         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11732                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11733                 return -EIO;
11734         }
11735
11736         return 0;
11737 }
11738
11739 static int i40e_get_module_info(struct rte_eth_dev *dev,
11740                                 struct rte_eth_dev_module_info *modinfo)
11741 {
11742         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11743         uint32_t sff8472_comp = 0;
11744         uint32_t sff8472_swap = 0;
11745         uint32_t sff8636_rev = 0;
11746         i40e_status status;
11747         uint32_t type = 0;
11748
11749         /* Check if firmware supports reading module EEPROM. */
11750         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11751                 PMD_DRV_LOG(ERR,
11752                             "Module EEPROM memory read not supported. "
11753                             "Please update the NVM image.\n");
11754                 return -EINVAL;
11755         }
11756
11757         status = i40e_update_link_info(hw);
11758         if (status)
11759                 return -EIO;
11760
11761         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11762                 PMD_DRV_LOG(ERR,
11763                             "Cannot read module EEPROM memory. "
11764                             "No module connected.\n");
11765                 return -EINVAL;
11766         }
11767
11768         type = hw->phy.link_info.module_type[0];
11769
11770         switch (type) {
11771         case I40E_MODULE_TYPE_SFP:
11772                 status = i40e_aq_get_phy_register(hw,
11773                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11774                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11775                                 I40E_MODULE_SFF_8472_COMP,
11776                                 &sff8472_comp, NULL);
11777                 if (status)
11778                         return -EIO;
11779
11780                 status = i40e_aq_get_phy_register(hw,
11781                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11782                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11783                                 I40E_MODULE_SFF_8472_SWAP,
11784                                 &sff8472_swap, NULL);
11785                 if (status)
11786                         return -EIO;
11787
11788                 /* Check if the module requires address swap to access
11789                  * the other EEPROM memory page.
11790                  */
11791                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11792                         PMD_DRV_LOG(WARNING,
11793                                     "Module address swap to access "
11794                                     "page 0xA2 is not supported.\n");
11795                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11796                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11797                 } else if (sff8472_comp == 0x00) {
11798                         /* Module is not SFF-8472 compliant */
11799                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11800                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11801                 } else {
11802                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11803                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11804                 }
11805                 break;
11806         case I40E_MODULE_TYPE_QSFP_PLUS:
11807                 /* Read from memory page 0. */
11808                 status = i40e_aq_get_phy_register(hw,
11809                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11810                                 0, 1,
11811                                 I40E_MODULE_REVISION_ADDR,
11812                                 &sff8636_rev, NULL);
11813                 if (status)
11814                         return -EIO;
11815                 /* Determine revision compliance byte */
11816                 if (sff8636_rev > 0x02) {
11817                         /* Module is SFF-8636 compliant */
11818                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11819                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11820                 } else {
11821                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11822                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11823                 }
11824                 break;
11825         case I40E_MODULE_TYPE_QSFP28:
11826                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11827                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11828                 break;
11829         default:
11830                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11831                 return -EINVAL;
11832         }
11833         return 0;
11834 }
11835
11836 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11837                                   struct rte_dev_eeprom_info *info)
11838 {
11839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11840         bool is_sfp = false;
11841         i40e_status status;
11842         uint8_t *data = info->data;
11843         uint32_t value = 0;
11844         uint32_t i;
11845
11846         if (!info || !info->length || !data)
11847                 return -EINVAL;
11848
11849         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11850                 is_sfp = true;
11851
11852         for (i = 0; i < info->length; i++) {
11853                 u32 offset = i + info->offset;
11854                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11855
11856                 /* Check if we need to access the other memory page */
11857                 if (is_sfp) {
11858                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11859                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11860                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11861                         }
11862                 } else {
11863                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11864                                 /* Compute memory page number and offset. */
11865                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11866                                 addr++;
11867                         }
11868                 }
11869                 status = i40e_aq_get_phy_register(hw,
11870                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11871                                 addr, offset, 1, &value, NULL);
11872                 if (status)
11873                         return -EIO;
11874                 data[i] = (uint8_t)value;
11875         }
11876         return 0;
11877 }
11878
11879 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11880                                      struct ether_addr *mac_addr)
11881 {
11882         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11884         struct i40e_vsi *vsi = pf->main_vsi;
11885         struct i40e_mac_filter_info mac_filter;
11886         struct i40e_mac_filter *f;
11887         int ret;
11888
11889         if (!is_valid_assigned_ether_addr(mac_addr)) {
11890                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11891                 return -EINVAL;
11892         }
11893
11894         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11895                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11896                         break;
11897         }
11898
11899         if (f == NULL) {
11900                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11901                 return -EIO;
11902         }
11903
11904         mac_filter = f->mac_info;
11905         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11906         if (ret != I40E_SUCCESS) {
11907                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11908                 return -EIO;
11909         }
11910         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11911         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11912         if (ret != I40E_SUCCESS) {
11913                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11914                 return -EIO;
11915         }
11916         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11917
11918         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11919                                         mac_addr->addr_bytes, NULL);
11920         if (ret != I40E_SUCCESS) {
11921                 PMD_DRV_LOG(ERR, "Failed to change mac");
11922                 return -EIO;
11923         }
11924
11925         return 0;
11926 }
11927
11928 static int
11929 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11930 {
11931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11932         struct rte_eth_dev_data *dev_data = pf->dev_data;
11933         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11934         int ret = 0;
11935
11936         /* check if mtu is within the allowed range */
11937         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11938                 return -EINVAL;
11939
11940         /* mtu setting is forbidden if port is start */
11941         if (dev_data->dev_started) {
11942                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11943                             dev_data->port_id);
11944                 return -EBUSY;
11945         }
11946
11947         if (frame_size > ETHER_MAX_LEN)
11948                 dev_data->dev_conf.rxmode.offloads |=
11949                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11950         else
11951                 dev_data->dev_conf.rxmode.offloads &=
11952                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11953
11954         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11955
11956         return ret;
11957 }
11958
11959 /* Restore ethertype filter */
11960 static void
11961 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11962 {
11963         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11964         struct i40e_ethertype_filter_list
11965                 *ethertype_list = &pf->ethertype.ethertype_list;
11966         struct i40e_ethertype_filter *f;
11967         struct i40e_control_filter_stats stats;
11968         uint16_t flags;
11969
11970         TAILQ_FOREACH(f, ethertype_list, rules) {
11971                 flags = 0;
11972                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11973                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11974                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11975                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11976                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11977
11978                 memset(&stats, 0, sizeof(stats));
11979                 i40e_aq_add_rem_control_packet_filter(hw,
11980                                             f->input.mac_addr.addr_bytes,
11981                                             f->input.ether_type,
11982                                             flags, pf->main_vsi->seid,
11983                                             f->queue, 1, &stats, NULL);
11984         }
11985         PMD_DRV_LOG(INFO, "Ethertype filter:"
11986                     " mac_etype_used = %u, etype_used = %u,"
11987                     " mac_etype_free = %u, etype_free = %u",
11988                     stats.mac_etype_used, stats.etype_used,
11989                     stats.mac_etype_free, stats.etype_free);
11990 }
11991
11992 /* Restore tunnel filter */
11993 static void
11994 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11995 {
11996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11997         struct i40e_vsi *vsi;
11998         struct i40e_pf_vf *vf;
11999         struct i40e_tunnel_filter_list
12000                 *tunnel_list = &pf->tunnel.tunnel_list;
12001         struct i40e_tunnel_filter *f;
12002         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12003         bool big_buffer = 0;
12004
12005         TAILQ_FOREACH(f, tunnel_list, rules) {
12006                 if (!f->is_to_vf)
12007                         vsi = pf->main_vsi;
12008                 else {
12009                         vf = &pf->vfs[f->vf_id];
12010                         vsi = vf->vsi;
12011                 }
12012                 memset(&cld_filter, 0, sizeof(cld_filter));
12013                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12014                         (struct ether_addr *)&cld_filter.element.outer_mac);
12015                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12016                         (struct ether_addr *)&cld_filter.element.inner_mac);
12017                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12018                 cld_filter.element.flags = f->input.flags;
12019                 cld_filter.element.tenant_id = f->input.tenant_id;
12020                 cld_filter.element.queue_number = f->queue;
12021                 rte_memcpy(cld_filter.general_fields,
12022                            f->input.general_fields,
12023                            sizeof(f->input.general_fields));
12024
12025                 if (((f->input.flags &
12026                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12027                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12028                     ((f->input.flags &
12029                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12030                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12031                     ((f->input.flags &
12032                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12033                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12034                         big_buffer = 1;
12035
12036                 if (big_buffer)
12037                         i40e_aq_add_cloud_filters_bb(hw,
12038                                         vsi->seid, &cld_filter, 1);
12039                 else
12040                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12041                                                   &cld_filter.element, 1);
12042         }
12043 }
12044
12045 /* Restore rss filter */
12046 static inline void
12047 i40e_rss_filter_restore(struct i40e_pf *pf)
12048 {
12049         struct i40e_rte_flow_rss_conf *conf =
12050                                         &pf->rss_info;
12051         if (conf->conf.queue_num)
12052                 i40e_config_rss_filter(pf, conf, TRUE);
12053 }
12054
12055 static void
12056 i40e_filter_restore(struct i40e_pf *pf)
12057 {
12058         i40e_ethertype_filter_restore(pf);
12059         i40e_tunnel_filter_restore(pf);
12060         i40e_fdir_filter_restore(pf);
12061         i40e_rss_filter_restore(pf);
12062 }
12063
12064 static bool
12065 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12066 {
12067         if (strcmp(dev->device->driver->name, drv->driver.name))
12068                 return false;
12069
12070         return true;
12071 }
12072
12073 bool
12074 is_i40e_supported(struct rte_eth_dev *dev)
12075 {
12076         return is_device_supported(dev, &rte_i40e_pmd);
12077 }
12078
12079 struct i40e_customized_pctype*
12080 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12081 {
12082         int i;
12083
12084         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12085                 if (pf->customized_pctype[i].index == index)
12086                         return &pf->customized_pctype[i];
12087         }
12088         return NULL;
12089 }
12090
12091 static int
12092 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12093                               uint32_t pkg_size, uint32_t proto_num,
12094                               struct rte_pmd_i40e_proto_info *proto,
12095                               enum rte_pmd_i40e_package_op op)
12096 {
12097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12098         uint32_t pctype_num;
12099         struct rte_pmd_i40e_ptype_info *pctype;
12100         uint32_t buff_size;
12101         struct i40e_customized_pctype *new_pctype = NULL;
12102         uint8_t proto_id;
12103         uint8_t pctype_value;
12104         char name[64];
12105         uint32_t i, j, n;
12106         int ret;
12107
12108         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12109             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12110                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12111                 return -1;
12112         }
12113
12114         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12115                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12116                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12117         if (ret) {
12118                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12119                 return -1;
12120         }
12121         if (!pctype_num) {
12122                 PMD_DRV_LOG(INFO, "No new pctype added");
12123                 return -1;
12124         }
12125
12126         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12127         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12128         if (!pctype) {
12129                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12130                 return -1;
12131         }
12132         /* get information about new pctype list */
12133         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12134                                         (uint8_t *)pctype, buff_size,
12135                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12136         if (ret) {
12137                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12138                 rte_free(pctype);
12139                 return -1;
12140         }
12141
12142         /* Update customized pctype. */
12143         for (i = 0; i < pctype_num; i++) {
12144                 pctype_value = pctype[i].ptype_id;
12145                 memset(name, 0, sizeof(name));
12146                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12147                         proto_id = pctype[i].protocols[j];
12148                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12149                                 continue;
12150                         for (n = 0; n < proto_num; n++) {
12151                                 if (proto[n].proto_id != proto_id)
12152                                         continue;
12153                                 strcat(name, proto[n].name);
12154                                 strcat(name, "_");
12155                                 break;
12156                         }
12157                 }
12158                 name[strlen(name) - 1] = '\0';
12159                 if (!strcmp(name, "GTPC"))
12160                         new_pctype =
12161                                 i40e_find_customized_pctype(pf,
12162                                                       I40E_CUSTOMIZED_GTPC);
12163                 else if (!strcmp(name, "GTPU_IPV4"))
12164                         new_pctype =
12165                                 i40e_find_customized_pctype(pf,
12166                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12167                 else if (!strcmp(name, "GTPU_IPV6"))
12168                         new_pctype =
12169                                 i40e_find_customized_pctype(pf,
12170                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12171                 else if (!strcmp(name, "GTPU"))
12172                         new_pctype =
12173                                 i40e_find_customized_pctype(pf,
12174                                                       I40E_CUSTOMIZED_GTPU);
12175                 if (new_pctype) {
12176                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12177                                 new_pctype->pctype = pctype_value;
12178                                 new_pctype->valid = true;
12179                         } else {
12180                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12181                                 new_pctype->valid = false;
12182                         }
12183                 }
12184         }
12185
12186         rte_free(pctype);
12187         return 0;
12188 }
12189
12190 static int
12191 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12192                              uint32_t pkg_size, uint32_t proto_num,
12193                              struct rte_pmd_i40e_proto_info *proto,
12194                              enum rte_pmd_i40e_package_op op)
12195 {
12196         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12197         uint16_t port_id = dev->data->port_id;
12198         uint32_t ptype_num;
12199         struct rte_pmd_i40e_ptype_info *ptype;
12200         uint32_t buff_size;
12201         uint8_t proto_id;
12202         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12203         uint32_t i, j, n;
12204         bool in_tunnel;
12205         int ret;
12206
12207         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12208             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12209                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12210                 return -1;
12211         }
12212
12213         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12214                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12215                 return 0;
12216         }
12217
12218         /* get information about new ptype num */
12219         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12220                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12221                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12222         if (ret) {
12223                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12224                 return ret;
12225         }
12226         if (!ptype_num) {
12227                 PMD_DRV_LOG(INFO, "No new ptype added");
12228                 return -1;
12229         }
12230
12231         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12232         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12233         if (!ptype) {
12234                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12235                 return -1;
12236         }
12237
12238         /* get information about new ptype list */
12239         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12240                                         (uint8_t *)ptype, buff_size,
12241                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12242         if (ret) {
12243                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12244                 rte_free(ptype);
12245                 return ret;
12246         }
12247
12248         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12249         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12250         if (!ptype_mapping) {
12251                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12252                 rte_free(ptype);
12253                 return -1;
12254         }
12255
12256         /* Update ptype mapping table. */
12257         for (i = 0; i < ptype_num; i++) {
12258                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12259                 ptype_mapping[i].sw_ptype = 0;
12260                 in_tunnel = false;
12261                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12262                         proto_id = ptype[i].protocols[j];
12263                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12264                                 continue;
12265                         for (n = 0; n < proto_num; n++) {
12266                                 if (proto[n].proto_id != proto_id)
12267                                         continue;
12268                                 memset(name, 0, sizeof(name));
12269                                 strcpy(name, proto[n].name);
12270                                 if (!strncasecmp(name, "PPPOE", 5))
12271                                         ptype_mapping[i].sw_ptype |=
12272                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12273                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12274                                          !in_tunnel) {
12275                                         ptype_mapping[i].sw_ptype |=
12276                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12277                                         ptype_mapping[i].sw_ptype |=
12278                                                 RTE_PTYPE_L4_FRAG;
12279                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12280                                            in_tunnel) {
12281                                         ptype_mapping[i].sw_ptype |=
12282                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12283                                         ptype_mapping[i].sw_ptype |=
12284                                                 RTE_PTYPE_INNER_L4_FRAG;
12285                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12286                                         ptype_mapping[i].sw_ptype |=
12287                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12288                                         in_tunnel = true;
12289                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12290                                            !in_tunnel)
12291                                         ptype_mapping[i].sw_ptype |=
12292                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12293                                 else if (!strncasecmp(name, "IPV4", 4) &&
12294                                          in_tunnel)
12295                                         ptype_mapping[i].sw_ptype |=
12296                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12297                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12298                                          !in_tunnel) {
12299                                         ptype_mapping[i].sw_ptype |=
12300                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12301                                         ptype_mapping[i].sw_ptype |=
12302                                                 RTE_PTYPE_L4_FRAG;
12303                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12304                                            in_tunnel) {
12305                                         ptype_mapping[i].sw_ptype |=
12306                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12307                                         ptype_mapping[i].sw_ptype |=
12308                                                 RTE_PTYPE_INNER_L4_FRAG;
12309                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12310                                         ptype_mapping[i].sw_ptype |=
12311                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12312                                         in_tunnel = true;
12313                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12314                                            !in_tunnel)
12315                                         ptype_mapping[i].sw_ptype |=
12316                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12317                                 else if (!strncasecmp(name, "IPV6", 4) &&
12318                                          in_tunnel)
12319                                         ptype_mapping[i].sw_ptype |=
12320                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12321                                 else if (!strncasecmp(name, "UDP", 3) &&
12322                                          !in_tunnel)
12323                                         ptype_mapping[i].sw_ptype |=
12324                                                 RTE_PTYPE_L4_UDP;
12325                                 else if (!strncasecmp(name, "UDP", 3) &&
12326                                          in_tunnel)
12327                                         ptype_mapping[i].sw_ptype |=
12328                                                 RTE_PTYPE_INNER_L4_UDP;
12329                                 else if (!strncasecmp(name, "TCP", 3) &&
12330                                          !in_tunnel)
12331                                         ptype_mapping[i].sw_ptype |=
12332                                                 RTE_PTYPE_L4_TCP;
12333                                 else if (!strncasecmp(name, "TCP", 3) &&
12334                                          in_tunnel)
12335                                         ptype_mapping[i].sw_ptype |=
12336                                                 RTE_PTYPE_INNER_L4_TCP;
12337                                 else if (!strncasecmp(name, "SCTP", 4) &&
12338                                          !in_tunnel)
12339                                         ptype_mapping[i].sw_ptype |=
12340                                                 RTE_PTYPE_L4_SCTP;
12341                                 else if (!strncasecmp(name, "SCTP", 4) &&
12342                                          in_tunnel)
12343                                         ptype_mapping[i].sw_ptype |=
12344                                                 RTE_PTYPE_INNER_L4_SCTP;
12345                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12346                                           !strncasecmp(name, "ICMPV6", 6)) &&
12347                                          !in_tunnel)
12348                                         ptype_mapping[i].sw_ptype |=
12349                                                 RTE_PTYPE_L4_ICMP;
12350                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12351                                           !strncasecmp(name, "ICMPV6", 6)) &&
12352                                          in_tunnel)
12353                                         ptype_mapping[i].sw_ptype |=
12354                                                 RTE_PTYPE_INNER_L4_ICMP;
12355                                 else if (!strncasecmp(name, "GTPC", 4)) {
12356                                         ptype_mapping[i].sw_ptype |=
12357                                                 RTE_PTYPE_TUNNEL_GTPC;
12358                                         in_tunnel = true;
12359                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12360                                         ptype_mapping[i].sw_ptype |=
12361                                                 RTE_PTYPE_TUNNEL_GTPU;
12362                                         in_tunnel = true;
12363                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12364                                         ptype_mapping[i].sw_ptype |=
12365                                                 RTE_PTYPE_TUNNEL_GRENAT;
12366                                         in_tunnel = true;
12367                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12368                                            !strncasecmp(name, "L2TPV2", 6)) {
12369                                         ptype_mapping[i].sw_ptype |=
12370                                                 RTE_PTYPE_TUNNEL_L2TP;
12371                                         in_tunnel = true;
12372                                 }
12373
12374                                 break;
12375                         }
12376                 }
12377         }
12378
12379         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12380                                                 ptype_num, 0);
12381         if (ret)
12382                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12383
12384         rte_free(ptype_mapping);
12385         rte_free(ptype);
12386         return ret;
12387 }
12388
12389 void
12390 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12391                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12392 {
12393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12394         uint32_t proto_num;
12395         struct rte_pmd_i40e_proto_info *proto;
12396         uint32_t buff_size;
12397         uint32_t i;
12398         int ret;
12399
12400         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12401             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12402                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12403                 return;
12404         }
12405
12406         /* get information about protocol number */
12407         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12408                                        (uint8_t *)&proto_num, sizeof(proto_num),
12409                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12410         if (ret) {
12411                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12412                 return;
12413         }
12414         if (!proto_num) {
12415                 PMD_DRV_LOG(INFO, "No new protocol added");
12416                 return;
12417         }
12418
12419         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12420         proto = rte_zmalloc("new_proto", buff_size, 0);
12421         if (!proto) {
12422                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12423                 return;
12424         }
12425
12426         /* get information about protocol list */
12427         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12428                                         (uint8_t *)proto, buff_size,
12429                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12430         if (ret) {
12431                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12432                 rte_free(proto);
12433                 return;
12434         }
12435
12436         /* Check if GTP is supported. */
12437         for (i = 0; i < proto_num; i++) {
12438                 if (!strncmp(proto[i].name, "GTP", 3)) {
12439                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12440                                 pf->gtp_support = true;
12441                         else
12442                                 pf->gtp_support = false;
12443                         break;
12444                 }
12445         }
12446
12447         /* Update customized pctype info */
12448         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12449                                             proto_num, proto, op);
12450         if (ret)
12451                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12452
12453         /* Update customized ptype info */
12454         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12455                                            proto_num, proto, op);
12456         if (ret)
12457                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12458
12459         rte_free(proto);
12460 }
12461
12462 /* Create a QinQ cloud filter
12463  *
12464  * The Fortville NIC has limited resources for tunnel filters,
12465  * so we can only reuse existing filters.
12466  *
12467  * In step 1 we define which Field Vector fields can be used for
12468  * filter types.
12469  * As we do not have the inner tag defined as a field,
12470  * we have to define it first, by reusing one of L1 entries.
12471  *
12472  * In step 2 we are replacing one of existing filter types with
12473  * a new one for QinQ.
12474  * As we reusing L1 and replacing L2, some of the default filter
12475  * types will disappear,which depends on L1 and L2 entries we reuse.
12476  *
12477  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12478  *
12479  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12480  *              later when we define the cloud filter.
12481  *      a.      Valid_flags.replace_cloud = 0
12482  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12483  *      c.      New_filter = 0x10
12484  *      d.      TR bit = 0xff (optional, not used here)
12485  *      e.      Buffer – 2 entries:
12486  *              i.      Byte 0 = 8 (outer vlan FV index).
12487  *                      Byte 1 = 0 (rsv)
12488  *                      Byte 2-3 = 0x0fff
12489  *              ii.     Byte 0 = 37 (inner vlan FV index).
12490  *                      Byte 1 =0 (rsv)
12491  *                      Byte 2-3 = 0x0fff
12492  *
12493  * Step 2:
12494  * 2.   Create cloud filter using two L1 filters entries: stag and
12495  *              new filter(outer vlan+ inner vlan)
12496  *      a.      Valid_flags.replace_cloud = 1
12497  *      b.      Old_filter = 1 (instead of outer IP)
12498  *      c.      New_filter = 0x10
12499  *      d.      Buffer – 2 entries:
12500  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12501  *                      Byte 1-3 = 0 (rsv)
12502  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12503  *                      Byte 9-11 = 0 (rsv)
12504  */
12505 static int
12506 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12507 {
12508         int ret = -ENOTSUP;
12509         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12510         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12511         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12512         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12513
12514         if (pf->support_multi_driver) {
12515                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12516                 return ret;
12517         }
12518
12519         /* Init */
12520         memset(&filter_replace, 0,
12521                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12522         memset(&filter_replace_buf, 0,
12523                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12524
12525         /* create L1 filter */
12526         filter_replace.old_filter_type =
12527                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12528         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12529         filter_replace.tr_bit = 0;
12530
12531         /* Prepare the buffer, 2 entries */
12532         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12533         filter_replace_buf.data[0] |=
12534                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12535         /* Field Vector 12b mask */
12536         filter_replace_buf.data[2] = 0xff;
12537         filter_replace_buf.data[3] = 0x0f;
12538         filter_replace_buf.data[4] =
12539                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12540         filter_replace_buf.data[4] |=
12541                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12542         /* Field Vector 12b mask */
12543         filter_replace_buf.data[6] = 0xff;
12544         filter_replace_buf.data[7] = 0x0f;
12545         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12546                         &filter_replace_buf);
12547         if (ret != I40E_SUCCESS)
12548                 return ret;
12549
12550         if (filter_replace.old_filter_type !=
12551             filter_replace.new_filter_type)
12552                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12553                             " original: 0x%x, new: 0x%x",
12554                             dev->device->name,
12555                             filter_replace.old_filter_type,
12556                             filter_replace.new_filter_type);
12557
12558         /* Apply the second L2 cloud filter */
12559         memset(&filter_replace, 0,
12560                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12561         memset(&filter_replace_buf, 0,
12562                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12563
12564         /* create L2 filter, input for L2 filter will be L1 filter  */
12565         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12566         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12567         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12568
12569         /* Prepare the buffer, 2 entries */
12570         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12571         filter_replace_buf.data[0] |=
12572                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12573         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12574         filter_replace_buf.data[4] |=
12575                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12576         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12577                         &filter_replace_buf);
12578         if (!ret && (filter_replace.old_filter_type !=
12579                      filter_replace.new_filter_type))
12580                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12581                             " original: 0x%x, new: 0x%x",
12582                             dev->device->name,
12583                             filter_replace.old_filter_type,
12584                             filter_replace.new_filter_type);
12585
12586         return ret;
12587 }
12588
12589 int
12590 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12591                    const struct rte_flow_action_rss *in)
12592 {
12593         if (in->key_len > RTE_DIM(out->key) ||
12594             in->queue_num > RTE_DIM(out->queue))
12595                 return -EINVAL;
12596         if (!in->key && in->key_len)
12597                 return -EINVAL;
12598         out->conf = (struct rte_flow_action_rss){
12599                 .func = in->func,
12600                 .level = in->level,
12601                 .types = in->types,
12602                 .key_len = in->key_len,
12603                 .queue_num = in->queue_num,
12604                 .queue = memcpy(out->queue, in->queue,
12605                                 sizeof(*in->queue) * in->queue_num),
12606         };
12607         if (in->key)
12608                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12609         return 0;
12610 }
12611
12612 int
12613 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12614                      const struct rte_flow_action_rss *with)
12615 {
12616         return (comp->func == with->func &&
12617                 comp->level == with->level &&
12618                 comp->types == with->types &&
12619                 comp->key_len == with->key_len &&
12620                 comp->queue_num == with->queue_num &&
12621                 !memcmp(comp->key, with->key, with->key_len) &&
12622                 !memcmp(comp->queue, with->queue,
12623                         sizeof(*with->queue) * with->queue_num));
12624 }
12625
12626 int
12627 i40e_config_rss_filter(struct i40e_pf *pf,
12628                 struct i40e_rte_flow_rss_conf *conf, bool add)
12629 {
12630         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12631         uint32_t i, lut = 0;
12632         uint16_t j, num;
12633         struct rte_eth_rss_conf rss_conf = {
12634                 .rss_key = conf->conf.key_len ?
12635                         (void *)(uintptr_t)conf->conf.key : NULL,
12636                 .rss_key_len = conf->conf.key_len,
12637                 .rss_hf = conf->conf.types,
12638         };
12639         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12640
12641         if (!add) {
12642                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12643                         i40e_pf_disable_rss(pf);
12644                         memset(rss_info, 0,
12645                                 sizeof(struct i40e_rte_flow_rss_conf));
12646                         return 0;
12647                 }
12648                 return -EINVAL;
12649         }
12650
12651         if (rss_info->conf.queue_num)
12652                 return -EINVAL;
12653
12654         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12655          * It's necessary to calculate the actual PF queues that are configured.
12656          */
12657         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12658                 num = i40e_pf_calc_configured_queues_num(pf);
12659         else
12660                 num = pf->dev_data->nb_rx_queues;
12661
12662         num = RTE_MIN(num, conf->conf.queue_num);
12663         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12664                         num);
12665
12666         if (num == 0) {
12667                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12668                 return -ENOTSUP;
12669         }
12670
12671         /* Fill in redirection table */
12672         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12673                 if (j == num)
12674                         j = 0;
12675                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12676                         hw->func_caps.rss_table_entry_width) - 1));
12677                 if ((i & 3) == 3)
12678                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12679         }
12680
12681         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12682                 i40e_pf_disable_rss(pf);
12683                 return 0;
12684         }
12685         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12686                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12687                 /* Random default keys */
12688                 static uint32_t rss_key_default[] = {0x6b793944,
12689                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12690                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12691                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12692
12693                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12694                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12695                                                         sizeof(uint32_t);
12696         }
12697
12698         i40e_hw_rss_hash_set(pf, &rss_conf);
12699
12700         if (i40e_rss_conf_init(rss_info, &conf->conf))
12701                 return -EINVAL;
12702
12703         return 0;
12704 }
12705
12706 RTE_INIT(i40e_init_log)
12707 {
12708         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12709         if (i40e_logtype_init >= 0)
12710                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12711         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12712         if (i40e_logtype_driver >= 0)
12713                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12714 }
12715
12716 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12717                               ETH_I40E_FLOATING_VEB_ARG "=1"
12718                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12719                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12720                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12721                               ETH_I40E_USE_LATEST_VEC "=0|1");