drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_eth_ctrl.h>
  28 #include <rte_tailq.h>
  29 #include <rte_hash_crc.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403
 404 static const struct rte_pci_id pci_id_i40e_map[] = {
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 425         { .vendor_id = 0, /* sentinel */ },
 426 };
 427
 428 static const struct eth_dev_ops i40e_eth_dev_ops = {
 429         .dev_configure                = i40e_dev_configure,
 430         .dev_start                    = i40e_dev_start,
 431         .dev_stop                     = i40e_dev_stop,
 432         .dev_close                    = i40e_dev_close,
 433         .dev_reset                    = i40e_dev_reset,
 434         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 435         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 436         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 437         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 438         .dev_set_link_up              = i40e_dev_set_link_up,
 439         .dev_set_link_down            = i40e_dev_set_link_down,
 440         .link_update                  = i40e_dev_link_update,
 441         .stats_get                    = i40e_dev_stats_get,
 442         .xstats_get                   = i40e_dev_xstats_get,
 443         .xstats_get_names             = i40e_dev_xstats_get_names,
 444         .stats_reset                  = i40e_dev_stats_reset,
 445         .xstats_reset                 = i40e_dev_stats_reset,
 446         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 447         .fw_version_get               = i40e_fw_version_get,
 448         .dev_infos_get                = i40e_dev_info_get,
 449         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 450         .vlan_filter_set              = i40e_vlan_filter_set,
 451         .vlan_tpid_set                = i40e_vlan_tpid_set,
 452         .vlan_offload_set             = i40e_vlan_offload_set,
 453         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 454         .vlan_pvid_set                = i40e_vlan_pvid_set,
 455         .rx_queue_start               = i40e_dev_rx_queue_start,
 456         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 457         .tx_queue_start               = i40e_dev_tx_queue_start,
 458         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 459         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 460         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 461         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 462         .rx_queue_release             = i40e_dev_rx_queue_release,
 463         .rx_queue_count               = i40e_dev_rx_queue_count,
 464         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 465         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 466         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 467         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 468         .tx_queue_release             = i40e_dev_tx_queue_release,
 469         .dev_led_on                   = i40e_dev_led_on,
 470         .dev_led_off                  = i40e_dev_led_off,
 471         .flow_ctrl_get                = i40e_flow_ctrl_get,
 472         .flow_ctrl_set                = i40e_flow_ctrl_set,
 473         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 474         .mac_addr_add                 = i40e_macaddr_add,
 475         .mac_addr_remove              = i40e_macaddr_remove,
 476         .reta_update                  = i40e_dev_rss_reta_update,
 477         .reta_query                   = i40e_dev_rss_reta_query,
 478         .rss_hash_update              = i40e_dev_rss_hash_update,
 479         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 480         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 481         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 482         .filter_ctrl                  = i40e_dev_filter_ctrl,
 483         .rxq_info_get                 = i40e_rxq_info_get,
 484         .txq_info_get                 = i40e_txq_info_get,
 485         .mirror_rule_set              = i40e_mirror_rule_set,
 486         .mirror_rule_reset            = i40e_mirror_rule_reset,
 487         .timesync_enable              = i40e_timesync_enable,
 488         .timesync_disable             = i40e_timesync_disable,
 489         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 490         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 491         .get_dcb_info                 = i40e_dev_get_dcb_info,
 492         .timesync_adjust_time         = i40e_timesync_adjust_time,
 493         .timesync_read_time           = i40e_timesync_read_time,
 494         .timesync_write_time          = i40e_timesync_write_time,
 495         .get_reg                      = i40e_get_regs,
 496         .get_eeprom_length            = i40e_get_eeprom_length,
 497         .get_eeprom                   = i40e_get_eeprom,
 498         .get_module_info              = i40e_get_module_info,
 499         .get_module_eeprom            = i40e_get_module_eeprom,
 500         .mac_addr_set                 = i40e_set_default_mac_addr,
 501         .mtu_set                      = i40e_dev_mtu_set,
 502         .tm_ops_get                   = i40e_tm_ops_get,
 503 };
 504
 505 /* store statistics names and its offset in stats structure */
 506 struct rte_i40e_xstats_name_off {
 507         char name[RTE_ETH_XSTATS_NAME_SIZE];
 508         unsigned offset;
 509 };
 510
 511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 512         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 513         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 514         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 515         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 516         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 517                 rx_unknown_protocol)},
 518         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 519         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 520         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 521         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 522 };
 523
 524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 525                 sizeof(rte_i40e_stats_strings[0]))
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 528         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 529                 tx_dropped_link_down)},
 530         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 531         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 532                 illegal_bytes)},
 533         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 534         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 535                 mac_local_faults)},
 536         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 537                 mac_remote_faults)},
 538         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 539                 rx_length_errors)},
 540         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 541         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 542         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 543         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 544         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 545         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_127)},
 547         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 550                 rx_size_511)},
 551         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 552                 rx_size_1023)},
 553         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 554                 rx_size_1522)},
 555         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 556                 rx_size_big)},
 557         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 558                 rx_undersize)},
 559         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 560                 rx_oversize)},
 561         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 562                 mac_short_packet_dropped)},
 563         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 564                 rx_fragments)},
 565         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 566         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_127)},
 569         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_255)},
 571         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 tx_size_511)},
 573         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 tx_size_1023)},
 575         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 tx_size_1522)},
 577         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 tx_size_big)},
 579         {"rx_flow_director_atr_match_packets",
 580                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 581         {"rx_flow_director_sb_match_packets",
 582                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 583         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 584                 tx_lpi_status)},
 585         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 586                 rx_lpi_status)},
 587         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 588                 tx_lpi_count)},
 589         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 590                 rx_lpi_count)},
 591 };
 592
 593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 594                 sizeof(rte_i40e_hw_port_strings[0]))
 595
 596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 597         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 598                 priority_xon_rx)},
 599         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xoff_rx)},
 601 };
 602
 603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 604                 sizeof(rte_i40e_rxq_prio_strings[0]))
 605
 606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 607         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 608                 priority_xon_tx)},
 609         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 610                 priority_xoff_tx)},
 611         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_2_xoff)},
 613 };
 614
 615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 616                 sizeof(rte_i40e_txq_prio_strings[0]))
 617
 618 static int
 619 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 620         struct rte_pci_device *pci_dev)
 621 {
 622         char name[RTE_ETH_NAME_MAX_LEN];
 623         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 624         int i, retval;
 625
 626         if (pci_dev->device.devargs) {
 627                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 628                                 &eth_da);
 629                 if (retval)
 630                         return retval;
 631         }
 632
 633         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 634                 sizeof(struct i40e_adapter),
 635                 eth_dev_pci_specific_init, pci_dev,
 636                 eth_i40e_dev_init, NULL);
 637
 638         if (retval || eth_da.nb_representor_ports < 1)
 639                 return retval;
 640
 641         /* probe VF representor ports */
 642         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 643                 pci_dev->device.name);
 644
 645         if (pf_ethdev == NULL)
 646                 return -ENODEV;
 647
 648         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 649                 struct i40e_vf_representor representor = {
 650                         .vf_id = eth_da.representor_ports[i],
 651                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 652                                 pf_ethdev->data->dev_private)->switch_domain_id,
 653                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 654                                 pf_ethdev->data->dev_private)
 655                 };
 656
 657                 /* representor port net_bdf_port */
 658                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 659                         pci_dev->device.name, eth_da.representor_ports[i]);
 660
 661                 retval = rte_eth_dev_create(&pci_dev->device, name,
 662                         sizeof(struct i40e_vf_representor), NULL, NULL,
 663                         i40e_vf_representor_init, &representor);
 664
 665                 if (retval)
 666                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 667                                 "representor %s.", name);
 668         }
 669
 670         return 0;
 671 }
 672
 673 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 674 {
 675         struct rte_eth_dev *ethdev;
 676
 677         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 678         if (!ethdev)
 679                 return -ENODEV;
 680
 681
 682         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 683                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 684         else
 685                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 686 }
 687
 688 static struct rte_pci_driver rte_i40e_pmd = {
 689         .id_table = pci_id_i40e_map,
 690         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 691                      RTE_PCI_DRV_IOVA_AS_VA,
 692         .probe = eth_i40e_pci_probe,
 693         .remove = eth_i40e_pci_remove,
 694 };
 695
 696 static inline void
 697 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 698                          uint32_t reg_val)
 699 {
 700         uint32_t ori_reg_val;
 701         struct rte_eth_dev *dev;
 702
 703         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 704         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 705         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 706         if (ori_reg_val != reg_val)
 707                 PMD_DRV_LOG(WARNING,
 708                             "i40e device %s changed global register [0x%08x]."
 709                             " original: 0x%08x, new: 0x%08x",
 710                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 711 }
 712
 713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 715 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 716
 717 #ifndef I40E_GLQF_ORT
 718 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 719 #endif
 720 #ifndef I40E_GLQF_PIT
 721 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 722 #endif
 723 #ifndef I40E_GLQF_L3_MAP
 724 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 725 #endif
 726
 727 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 728 {
 729         /*
 730          * Initialize registers for parsing packet type of QinQ
 731          * This should be removed from code once proper
 732          * configuration API is added to avoid configuration conflicts
 733          * between ports of the same device.
 734          */
 735         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 736         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 737 }
 738
 739 static inline void i40e_config_automask(struct i40e_pf *pf)
 740 {
 741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 742         uint32_t val;
 743
 744         /* INTENA flag is not auto-cleared for interrupt */
 745         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 746         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 747                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 748
 749         /* If support multi-driver, PF will use INT0. */
 750         if (!pf->support_multi_driver)
 751                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 752
 753         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 754 }
 755
 756 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 757
 758 /*
 759  * Add a ethertype filter to drop all flow control frames transmitted
 760  * from VSIs.
 761 */
 762 static void
 763 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 764 {
 765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 766         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 767                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 768                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 769         int ret;
 770
 771         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 772                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 773                                 pf->main_vsi_seid, 0,
 774                                 TRUE, NULL, NULL);
 775         if (ret)
 776                 PMD_INIT_LOG(ERR,
 777                         "Failed to add filter to drop flow control frames from VSIs.");
 778 }
 779
 780 static int
 781 floating_veb_list_handler(__rte_unused const char *key,
 782                           const char *floating_veb_value,
 783                           void *opaque)
 784 {
 785         int idx = 0;
 786         unsigned int count = 0;
 787         char *end = NULL;
 788         int min, max;
 789         bool *vf_floating_veb = opaque;
 790
 791         while (isblank(*floating_veb_value))
 792                 floating_veb_value++;
 793
 794         /* Reset floating VEB configuration for VFs */
 795         for (idx = 0; idx < I40E_MAX_VF; idx++)
 796                 vf_floating_veb[idx] = false;
 797
 798         min = I40E_MAX_VF;
 799         do {
 800                 while (isblank(*floating_veb_value))
 801                         floating_veb_value++;
 802                 if (*floating_veb_value == '\0')
 803                         return -1;
 804                 errno = 0;
 805                 idx = strtoul(floating_veb_value, &end, 10);
 806                 if (errno || end == NULL)
 807                         return -1;
 808                 while (isblank(*end))
 809                         end++;
 810                 if (*end == '-') {
 811                         min = idx;
 812                 } else if ((*end == ';') || (*end == '\0')) {
 813                         max = idx;
 814                         if (min == I40E_MAX_VF)
 815                                 min = idx;
 816                         if (max >= I40E_MAX_VF)
 817                                 max = I40E_MAX_VF - 1;
 818                         for (idx = min; idx <= max; idx++) {
 819                                 vf_floating_veb[idx] = true;
 820                                 count++;
 821                         }
 822                         min = I40E_MAX_VF;
 823                 } else {
 824                         return -1;
 825                 }
 826                 floating_veb_value = end + 1;
 827         } while (*end != '\0');
 828
 829         if (count == 0)
 830                 return -1;
 831
 832         return 0;
 833 }
 834
 835 static void
 836 config_vf_floating_veb(struct rte_devargs *devargs,
 837                        uint16_t floating_veb,
 838                        bool *vf_floating_veb)
 839 {
 840         struct rte_kvargs *kvlist;
 841         int i;
 842         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 843
 844         if (!floating_veb)
 845                 return;
 846         /* All the VFs attach to the floating VEB by default
 847          * when the floating VEB is enabled.
 848          */
 849         for (i = 0; i < I40E_MAX_VF; i++)
 850                 vf_floating_veb[i] = true;
 851
 852         if (devargs == NULL)
 853                 return;
 854
 855         kvlist = rte_kvargs_parse(devargs->args, NULL);
 856         if (kvlist == NULL)
 857                 return;
 858
 859         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 860                 rte_kvargs_free(kvlist);
 861                 return;
 862         }
 863         /* When the floating_veb_list parameter exists, all the VFs
 864          * will attach to the legacy VEB firstly, then configure VFs
 865          * to the floating VEB according to the floating_veb_list.
 866          */
 867         if (rte_kvargs_process(kvlist, floating_veb_list,
 868                                floating_veb_list_handler,
 869                                vf_floating_veb) < 0) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         rte_kvargs_free(kvlist);
 874 }
 875
 876 static int
 877 i40e_check_floating_handler(__rte_unused const char *key,
 878                             const char *value,
 879                             __rte_unused void *opaque)
 880 {
 881         if (strcmp(value, "1"))
 882                 return -1;
 883
 884         return 0;
 885 }
 886
 887 static int
 888 is_floating_veb_supported(struct rte_devargs *devargs)
 889 {
 890         struct rte_kvargs *kvlist;
 891         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 892
 893         if (devargs == NULL)
 894                 return 0;
 895
 896         kvlist = rte_kvargs_parse(devargs->args, NULL);
 897         if (kvlist == NULL)
 898                 return 0;
 899
 900         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 901                 rte_kvargs_free(kvlist);
 902                 return 0;
 903         }
 904         /* Floating VEB is enabled when there's key-value:
 905          * enable_floating_veb=1
 906          */
 907         if (rte_kvargs_process(kvlist, floating_veb_key,
 908                                i40e_check_floating_handler, NULL) < 0) {
 909                 rte_kvargs_free(kvlist);
 910                 return 0;
 911         }
 912         rte_kvargs_free(kvlist);
 913
 914         return 1;
 915 }
 916
 917 static void
 918 config_floating_veb(struct rte_eth_dev *dev)
 919 {
 920         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 921         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 923
 924         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 925
 926         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 927                 pf->floating_veb =
 928                         is_floating_veb_supported(pci_dev->device.devargs);
 929                 config_vf_floating_veb(pci_dev->device.devargs,
 930                                        pf->floating_veb,
 931                                        pf->floating_veb_list);
 932         } else {
 933                 pf->floating_veb = false;
 934         }
 935 }
 936
 937 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 938 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 939
 940 static int
 941 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 945         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 946         int ret;
 947
 948         struct rte_hash_parameters ethertype_hash_params = {
 949                 .name = ethertype_hash_name,
 950                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 951                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 952                 .hash_func = rte_hash_crc,
 953                 .hash_func_init_val = 0,
 954                 .socket_id = rte_socket_id(),
 955         };
 956
 957         /* Initialize ethertype filter rule list and hash */
 958         TAILQ_INIT(&ethertype_rule->ethertype_list);
 959         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 960                  "ethertype_%s", dev->device->name);
 961         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 962         if (!ethertype_rule->hash_table) {
 963                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 964                 return -EINVAL;
 965         }
 966         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 967                                        sizeof(struct i40e_ethertype_filter *) *
 968                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 969                                        0);
 970         if (!ethertype_rule->hash_map) {
 971                 PMD_INIT_LOG(ERR,
 972                              "Failed to allocate memory for ethertype hash map!");
 973                 ret = -ENOMEM;
 974                 goto err_ethertype_hash_map_alloc;
 975         }
 976
 977         return 0;
 978
 979 err_ethertype_hash_map_alloc:
 980         rte_hash_free(ethertype_rule->hash_table);
 981
 982         return ret;
 983 }
 984
 985 static int
 986 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 987 {
 988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 989         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 990         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 991         int ret;
 992
 993         struct rte_hash_parameters tunnel_hash_params = {
 994                 .name = tunnel_hash_name,
 995                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 996                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 997                 .hash_func = rte_hash_crc,
 998                 .hash_func_init_val = 0,
 999                 .socket_id = rte_socket_id(),
1000         };
1001
1002         /* Initialize tunnel filter rule list and hash */
1003         TAILQ_INIT(&tunnel_rule->tunnel_list);
1004         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1005                  "tunnel_%s", dev->device->name);
1006         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1007         if (!tunnel_rule->hash_table) {
1008                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1009                 return -EINVAL;
1010         }
1011         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1012                                     sizeof(struct i40e_tunnel_filter *) *
1013                                     I40E_MAX_TUNNEL_FILTER_NUM,
1014                                     0);
1015         if (!tunnel_rule->hash_map) {
1016                 PMD_INIT_LOG(ERR,
1017                              "Failed to allocate memory for tunnel hash map!");
1018                 ret = -ENOMEM;
1019                 goto err_tunnel_hash_map_alloc;
1020         }
1021
1022         return 0;
1023
1024 err_tunnel_hash_map_alloc:
1025         rte_hash_free(tunnel_rule->hash_table);
1026
1027         return ret;
1028 }
1029
1030 static int
1031 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1032 {
1033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1034         struct i40e_fdir_info *fdir_info = &pf->fdir;
1035         char fdir_hash_name[RTE_HASH_NAMESIZE];
1036         int ret;
1037
1038         struct rte_hash_parameters fdir_hash_params = {
1039                 .name = fdir_hash_name,
1040                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1041                 .key_len = sizeof(struct i40e_fdir_input),
1042                 .hash_func = rte_hash_crc,
1043                 .hash_func_init_val = 0,
1044                 .socket_id = rte_socket_id(),
1045         };
1046
1047         /* Initialize flow director filter rule list and hash */
1048         TAILQ_INIT(&fdir_info->fdir_list);
1049         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1050                  "fdir_%s", dev->device->name);
1051         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1052         if (!fdir_info->hash_table) {
1053                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1054                 return -EINVAL;
1055         }
1056         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1057                                           sizeof(struct i40e_fdir_filter *) *
1058                                           I40E_MAX_FDIR_FILTER_NUM,
1059                                           0);
1060         if (!fdir_info->hash_map) {
1061                 PMD_INIT_LOG(ERR,
1062                              "Failed to allocate memory for fdir hash map!");
1063                 ret = -ENOMEM;
1064                 goto err_fdir_hash_map_alloc;
1065         }
1066         return 0;
1067
1068 err_fdir_hash_map_alloc:
1069         rte_hash_free(fdir_info->hash_table);
1070
1071         return ret;
1072 }
1073
1074 static void
1075 i40e_init_customized_info(struct i40e_pf *pf)
1076 {
1077         int i;
1078
1079         /* Initialize customized pctype */
1080         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1081                 pf->customized_pctype[i].index = i;
1082                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1083                 pf->customized_pctype[i].valid = false;
1084         }
1085
1086         pf->gtp_support = false;
1087 }
1088
1089 void
1090 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1091 {
1092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1093         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1094         struct i40e_queue_regions *info = &pf->queue_region;
1095         uint16_t i;
1096
1097         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1098                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1099
1100         memset(info, 0, sizeof(struct i40e_queue_regions));
1101 }
1102
1103 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1104
1105 static int
1106 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1107                                const char *value,
1108                                void *opaque)
1109 {
1110         struct i40e_pf *pf;
1111         unsigned long support_multi_driver;
1112         char *end;
1113
1114         pf = (struct i40e_pf *)opaque;
1115
1116         errno = 0;
1117         support_multi_driver = strtoul(value, &end, 10);
1118         if (errno != 0 || end == value || *end != 0) {
1119                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1120                 return -(EINVAL);
1121         }
1122
1123         if (support_multi_driver == 1 || support_multi_driver == 0)
1124                 pf->support_multi_driver = (bool)support_multi_driver;
1125         else
1126                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1127                             "enable global configuration by default."
1128                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1129         return 0;
1130 }
1131
1132 static int
1133 i40e_support_multi_driver(struct rte_eth_dev *dev)
1134 {
1135         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1136         static const char *const valid_keys[] = {
1137                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1138         struct rte_kvargs *kvlist;
1139
1140         /* Enable global configuration by default */
1141         pf->support_multi_driver = false;
1142
1143         if (!dev->device->devargs)
1144                 return 0;
1145
1146         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1147         if (!kvlist)
1148                 return -EINVAL;
1149
1150         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1151                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1152                             "the first invalid or last valid one is used !",
1153                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1154
1155         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1156                                i40e_parse_multi_drv_handler, pf) < 0) {
1157                 rte_kvargs_free(kvlist);
1158                 return -EINVAL;
1159         }
1160
1161         rte_kvargs_free(kvlist);
1162         return 0;
1163 }
1164
1165 static int
1166 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1167                                     uint32_t reg_addr, uint64_t reg_val,
1168                                     struct i40e_asq_cmd_details *cmd_details)
1169 {
1170         uint64_t ori_reg_val;
1171         struct rte_eth_dev *dev;
1172         int ret;
1173
1174         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1175         if (ret != I40E_SUCCESS) {
1176                 PMD_DRV_LOG(ERR,
1177                             "Fail to debug read from 0x%08x",
1178                             reg_addr);
1179                 return -EIO;
1180         }
1181         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1182
1183         if (ori_reg_val != reg_val)
1184                 PMD_DRV_LOG(WARNING,
1185                             "i40e device %s changed global register [0x%08x]."
1186                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1187                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1188
1189         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1190 }
1191
1192 static int
1193 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1194 {
1195         struct rte_pci_device *pci_dev;
1196         struct rte_intr_handle *intr_handle;
1197         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         struct i40e_vsi *vsi;
1200         int ret;
1201         uint32_t len;
1202         uint8_t aq_fail = 0;
1203
1204         PMD_INIT_FUNC_TRACE();
1205
1206         dev->dev_ops = &i40e_eth_dev_ops;
1207         dev->rx_pkt_burst = i40e_recv_pkts;
1208         dev->tx_pkt_burst = i40e_xmit_pkts;
1209         dev->tx_pkt_prepare = i40e_prep_pkts;
1210
1211         /* for secondary processes, we don't initialise any further as primary
1212          * has already done this work. Only check we don't need a different
1213          * RX function */
1214         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1215                 i40e_set_rx_function(dev);
1216                 i40e_set_tx_function(dev);
1217                 return 0;
1218         }
1219         i40e_set_default_ptype_table(dev);
1220         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1221         intr_handle = &pci_dev->intr_handle;
1222
1223         rte_eth_copy_pci_info(dev, pci_dev);
1224
1225         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226         pf->adapter->eth_dev = dev;
1227         pf->dev_data = dev->data;
1228
1229         hw->back = I40E_PF_TO_ADAPTER(pf);
1230         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1231         if (!hw->hw_addr) {
1232                 PMD_INIT_LOG(ERR,
1233                         "Hardware is not available, as address is NULL");
1234                 return -ENODEV;
1235         }
1236
1237         hw->vendor_id = pci_dev->id.vendor_id;
1238         hw->device_id = pci_dev->id.device_id;
1239         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1240         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1241         hw->bus.device = pci_dev->addr.devid;
1242         hw->bus.func = pci_dev->addr.function;
1243         hw->adapter_stopped = 0;
1244
1245         /*
1246          * Switch Tag value should not be identical to either the First Tag
1247          * or Second Tag values. So set something other than common Ethertype
1248          * for internal switching.
1249          */
1250         hw->switch_tag = 0xffff;
1251
1252         /* Check if need to support multi-driver */
1253         i40e_support_multi_driver(dev);
1254
1255         /* Make sure all is clean before doing PF reset */
1256         i40e_clear_hw(hw);
1257
1258         /* Initialize the hardware */
1259         i40e_hw_init(dev);
1260
1261         /* Reset here to make sure all is clean for each PF */
1262         ret = i40e_pf_reset(hw);
1263         if (ret) {
1264                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1265                 return ret;
1266         }
1267
1268         /* Initialize the shared code (base driver) */
1269         ret = i40e_init_shared_code(hw);
1270         if (ret) {
1271                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1272                 return ret;
1273         }
1274
1275         i40e_config_automask(pf);
1276
1277         i40e_set_default_pctype_table(dev);
1278
1279         /*
1280          * To work around the NVM issue, initialize registers
1281          * for packet type of QinQ by software.
1282          * It should be removed once issues are fixed in NVM.
1283          */
1284         if (!pf->support_multi_driver)
1285                 i40e_GLQF_reg_init(hw);
1286
1287         /* Initialize the input set for filters (hash and fd) to default value */
1288         i40e_filter_input_set_init(pf);
1289
1290         /* Initialize the parameters for adminq */
1291         i40e_init_adminq_parameter(hw);
1292         ret = i40e_init_adminq(hw);
1293         if (ret != I40E_SUCCESS) {
1294                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1295                 return -EIO;
1296         }
1297         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1298                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1299                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1300                      ((hw->nvm.version >> 12) & 0xf),
1301                      ((hw->nvm.version >> 4) & 0xff),
1302                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1303
1304         /* initialise the L3_MAP register */
1305         if (!pf->support_multi_driver) {
1306                 ret = i40e_aq_debug_write_global_register(hw,
1307                                                    I40E_GLQF_L3_MAP(40),
1308                                                    0x00000028,  NULL);
1309                 if (ret)
1310                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1311                                      ret);
1312                 PMD_INIT_LOG(DEBUG,
1313                              "Global register 0x%08x is changed with 0x28",
1314                              I40E_GLQF_L3_MAP(40));
1315         }
1316
1317         /* Need the special FW version to support floating VEB */
1318         config_floating_veb(dev);
1319         /* Clear PXE mode */
1320         i40e_clear_pxe_mode(hw);
1321         i40e_dev_sync_phy_type(hw);
1322
1323         /*
1324          * On X710, performance number is far from the expectation on recent
1325          * firmware versions. The fix for this issue may not be integrated in
1326          * the following firmware version. So the workaround in software driver
1327          * is needed. It needs to modify the initial values of 3 internal only
1328          * registers. Note that the workaround can be removed when it is fixed
1329          * in firmware in the future.
1330          */
1331         i40e_configure_registers(hw);
1332
1333         /* Get hw capabilities */
1334         ret = i40e_get_cap(hw);
1335         if (ret != I40E_SUCCESS) {
1336                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1337                 goto err_get_capabilities;
1338         }
1339
1340         /* Initialize parameters for PF */
1341         ret = i40e_pf_parameter_init(dev);
1342         if (ret != 0) {
1343                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1344                 goto err_parameter_init;
1345         }
1346
1347         /* Initialize the queue management */
1348         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1349         if (ret < 0) {
1350                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1351                 goto err_qp_pool_init;
1352         }
1353         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1354                                 hw->func_caps.num_msix_vectors - 1);
1355         if (ret < 0) {
1356                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1357                 goto err_msix_pool_init;
1358         }
1359
1360         /* Initialize lan hmc */
1361         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1362                                 hw->func_caps.num_rx_qp, 0, 0);
1363         if (ret != I40E_SUCCESS) {
1364                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1365                 goto err_init_lan_hmc;
1366         }
1367
1368         /* Configure lan hmc */
1369         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1370         if (ret != I40E_SUCCESS) {
1371                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1372                 goto err_configure_lan_hmc;
1373         }
1374
1375         /* Get and check the mac address */
1376         i40e_get_mac_addr(hw, hw->mac.addr);
1377         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1378                 PMD_INIT_LOG(ERR, "mac address is not valid");
1379                 ret = -EIO;
1380                 goto err_get_mac_addr;
1381         }
1382         /* Copy the permanent MAC address */
1383         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1384                         (struct ether_addr *) hw->mac.perm_addr);
1385
1386         /* Disable flow control */
1387         hw->fc.requested_mode = I40E_FC_NONE;
1388         i40e_set_fc(hw, &aq_fail, TRUE);
1389
1390         /* Set the global registers with default ether type value */
1391         if (!pf->support_multi_driver) {
1392                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1393                                          ETHER_TYPE_VLAN);
1394                 if (ret != I40E_SUCCESS) {
1395                         PMD_INIT_LOG(ERR,
1396                                      "Failed to set the default outer "
1397                                      "VLAN ether type");
1398                         goto err_setup_pf_switch;
1399                 }
1400         }
1401
1402         /* PF setup, which includes VSI setup */
1403         ret = i40e_pf_setup(pf);
1404         if (ret) {
1405                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1406                 goto err_setup_pf_switch;
1407         }
1408
1409         /* reset all stats of the device, including pf and main vsi */
1410         i40e_dev_stats_reset(dev);
1411
1412         vsi = pf->main_vsi;
1413
1414         /* Disable double vlan by default */
1415         i40e_vsi_config_double_vlan(vsi, FALSE);
1416
1417         /* Disable S-TAG identification when floating_veb is disabled */
1418         if (!pf->floating_veb) {
1419                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1420                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1421                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1422                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1423                 }
1424         }
1425
1426         if (!vsi->max_macaddrs)
1427                 len = ETHER_ADDR_LEN;
1428         else
1429                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1430
1431         /* Should be after VSI initialized */
1432         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1433         if (!dev->data->mac_addrs) {
1434                 PMD_INIT_LOG(ERR,
1435                         "Failed to allocated memory for storing mac address");
1436                 goto err_mac_alloc;
1437         }
1438         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1439                                         &dev->data->mac_addrs[0]);
1440
1441         /* Init dcb to sw mode by default */
1442         ret = i40e_dcb_init_configure(dev, TRUE);
1443         if (ret != I40E_SUCCESS) {
1444                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1445                 pf->flags &= ~I40E_FLAG_DCB;
1446         }
1447         /* Update HW struct after DCB configuration */
1448         i40e_get_cap(hw);
1449
1450         /* initialize pf host driver to setup SRIOV resource if applicable */
1451         i40e_pf_host_init(dev);
1452
1453         /* register callback func to eal lib */
1454         rte_intr_callback_register(intr_handle,
1455                                    i40e_dev_interrupt_handler, dev);
1456
1457         /* configure and enable device interrupt */
1458         i40e_pf_config_irq0(hw, TRUE);
1459         i40e_pf_enable_irq0(hw);
1460
1461         /* enable uio intr after callback register */
1462         rte_intr_enable(intr_handle);
1463
1464         /* By default disable flexible payload in global configuration */
1465         if (!pf->support_multi_driver)
1466                 i40e_flex_payload_reg_set_default(hw);
1467
1468         /*
1469          * Add an ethertype filter to drop all flow control frames transmitted
1470          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1471          * frames to wire.
1472          */
1473         i40e_add_tx_flow_control_drop_filter(pf);
1474
1475         /* Set the max frame size to 0x2600 by default,
1476          * in case other drivers changed the default value.
1477          */
1478         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1479
1480         /* initialize mirror rule list */
1481         TAILQ_INIT(&pf->mirror_list);
1482
1483         /* initialize Traffic Manager configuration */
1484         i40e_tm_conf_init(dev);
1485
1486         /* Initialize customized information */
1487         i40e_init_customized_info(pf);
1488
1489         ret = i40e_init_ethtype_filter_list(dev);
1490         if (ret < 0)
1491                 goto err_init_ethtype_filter_list;
1492         ret = i40e_init_tunnel_filter_list(dev);
1493         if (ret < 0)
1494                 goto err_init_tunnel_filter_list;
1495         ret = i40e_init_fdir_filter_list(dev);
1496         if (ret < 0)
1497                 goto err_init_fdir_filter_list;
1498
1499         /* initialize queue region configuration */
1500         i40e_init_queue_region_conf(dev);
1501
1502         /* initialize rss configuration from rte_flow */
1503         memset(&pf->rss_info, 0,
1504                 sizeof(struct i40e_rte_flow_rss_conf));
1505
1506         return 0;
1507
1508 err_init_fdir_filter_list:
1509         rte_free(pf->tunnel.hash_table);
1510         rte_free(pf->tunnel.hash_map);
1511 err_init_tunnel_filter_list:
1512         rte_free(pf->ethertype.hash_table);
1513         rte_free(pf->ethertype.hash_map);
1514 err_init_ethtype_filter_list:
1515         rte_free(dev->data->mac_addrs);
1516 err_mac_alloc:
1517         i40e_vsi_release(pf->main_vsi);
1518 err_setup_pf_switch:
1519 err_get_mac_addr:
1520 err_configure_lan_hmc:
1521         (void)i40e_shutdown_lan_hmc(hw);
1522 err_init_lan_hmc:
1523         i40e_res_pool_destroy(&pf->msix_pool);
1524 err_msix_pool_init:
1525         i40e_res_pool_destroy(&pf->qp_pool);
1526 err_qp_pool_init:
1527 err_parameter_init:
1528 err_get_capabilities:
1529         (void)i40e_shutdown_adminq(hw);
1530
1531         return ret;
1532 }
1533
1534 static void
1535 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1536 {
1537         struct i40e_ethertype_filter *p_ethertype;
1538         struct i40e_ethertype_rule *ethertype_rule;
1539
1540         ethertype_rule = &pf->ethertype;
1541         /* Remove all ethertype filter rules and hash */
1542         if (ethertype_rule->hash_map)
1543                 rte_free(ethertype_rule->hash_map);
1544         if (ethertype_rule->hash_table)
1545                 rte_hash_free(ethertype_rule->hash_table);
1546
1547         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1548                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1549                              p_ethertype, rules);
1550                 rte_free(p_ethertype);
1551         }
1552 }
1553
1554 static void
1555 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1556 {
1557         struct i40e_tunnel_filter *p_tunnel;
1558         struct i40e_tunnel_rule *tunnel_rule;
1559
1560         tunnel_rule = &pf->tunnel;
1561         /* Remove all tunnel director rules and hash */
1562         if (tunnel_rule->hash_map)
1563                 rte_free(tunnel_rule->hash_map);
1564         if (tunnel_rule->hash_table)
1565                 rte_hash_free(tunnel_rule->hash_table);
1566
1567         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1568                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1569                 rte_free(p_tunnel);
1570         }
1571 }
1572
1573 static void
1574 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1575 {
1576         struct i40e_fdir_filter *p_fdir;
1577         struct i40e_fdir_info *fdir_info;
1578
1579         fdir_info = &pf->fdir;
1580         /* Remove all flow director rules and hash */
1581         if (fdir_info->hash_map)
1582                 rte_free(fdir_info->hash_map);
1583         if (fdir_info->hash_table)
1584                 rte_hash_free(fdir_info->hash_table);
1585
1586         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1587                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1588                 rte_free(p_fdir);
1589         }
1590 }
1591
1592 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1593 {
1594         /*
1595          * Disable by default flexible payload
1596          * for corresponding L2/L3/L4 layers.
1597          */
1598         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1599         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1600         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1601 }
1602
1603 static int
1604 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1605 {
1606         struct i40e_pf *pf;
1607         struct rte_pci_device *pci_dev;
1608         struct rte_intr_handle *intr_handle;
1609         struct i40e_hw *hw;
1610         struct i40e_filter_control_settings settings;
1611         struct rte_flow *p_flow;
1612         int ret;
1613         uint8_t aq_fail = 0;
1614         int retries = 0;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1619                 return 0;
1620
1621         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1622         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1624         intr_handle = &pci_dev->intr_handle;
1625
1626         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1627         if (ret)
1628                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1629
1630         if (hw->adapter_stopped == 0)
1631                 i40e_dev_close(dev);
1632
1633         dev->dev_ops = NULL;
1634         dev->rx_pkt_burst = NULL;
1635         dev->tx_pkt_burst = NULL;
1636
1637         /* Clear PXE mode */
1638         i40e_clear_pxe_mode(hw);
1639
1640         /* Unconfigure filter control */
1641         memset(&settings, 0, sizeof(settings));
1642         ret = i40e_set_filter_control(hw, &settings);
1643         if (ret)
1644                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1645                                         ret);
1646
1647         /* Disable flow control */
1648         hw->fc.requested_mode = I40E_FC_NONE;
1649         i40e_set_fc(hw, &aq_fail, TRUE);
1650
1651         /* uninitialize pf host driver */
1652         i40e_pf_host_uninit(dev);
1653
1654         rte_free(dev->data->mac_addrs);
1655         dev->data->mac_addrs = NULL;
1656
1657         /* disable uio intr before callback unregister */
1658         rte_intr_disable(intr_handle);
1659
1660         /* unregister callback func to eal lib */
1661         do {
1662                 ret = rte_intr_callback_unregister(intr_handle,
1663                                 i40e_dev_interrupt_handler, dev);
1664                 if (ret >= 0) {
1665                         break;
1666                 } else if (ret != -EAGAIN) {
1667                         PMD_INIT_LOG(ERR,
1668                                  "intr callback unregister failed: %d",
1669                                  ret);
1670                         return ret;
1671                 }
1672                 i40e_msec_delay(500);
1673         } while (retries++ < 5);
1674
1675         i40e_rm_ethtype_filter_list(pf);
1676         i40e_rm_tunnel_filter_list(pf);
1677         i40e_rm_fdir_filter_list(pf);
1678
1679         /* Remove all flows */
1680         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1681                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1682                 rte_free(p_flow);
1683         }
1684
1685         /* Remove all Traffic Manager configuration */
1686         i40e_tm_conf_uninit(dev);
1687
1688         return 0;
1689 }
1690
1691 static int
1692 i40e_dev_configure(struct rte_eth_dev *dev)
1693 {
1694         struct i40e_adapter *ad =
1695                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1699         int i, ret;
1700
1701         ret = i40e_dev_sync_phy_type(hw);
1702         if (ret)
1703                 return ret;
1704
1705         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1706          * bulk allocation or vector Rx preconditions we will reset it.
1707          */
1708         ad->rx_bulk_alloc_allowed = true;
1709         ad->rx_vec_allowed = true;
1710         ad->tx_simple_allowed = true;
1711         ad->tx_vec_allowed = true;
1712
1713         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1714                 ret = i40e_fdir_setup(pf);
1715                 if (ret != I40E_SUCCESS) {
1716                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1717                         return -ENOTSUP;
1718                 }
1719                 ret = i40e_fdir_configure(dev);
1720                 if (ret < 0) {
1721                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1722                         goto err;
1723                 }
1724         } else
1725                 i40e_fdir_teardown(pf);
1726
1727         ret = i40e_dev_init_vlan(dev);
1728         if (ret < 0)
1729                 goto err;
1730
1731         /* VMDQ setup.
1732          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1733          *  RSS setting have different requirements.
1734          *  General PMD driver call sequence are NIC init, configure,
1735          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1736          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1737          *  applicable. So, VMDQ setting has to be done before
1738          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1739          *  For RSS setting, it will try to calculate actual configured RX queue
1740          *  number, which will be available after rx_queue_setup(). dev_start()
1741          *  function is good to place RSS setup.
1742          */
1743         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1744                 ret = i40e_vmdq_setup(dev);
1745                 if (ret)
1746                         goto err;
1747         }
1748
1749         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1750                 ret = i40e_dcb_setup(dev);
1751                 if (ret) {
1752                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1753                         goto err_dcb;
1754                 }
1755         }
1756
1757         TAILQ_INIT(&pf->flow_list);
1758
1759         return 0;
1760
1761 err_dcb:
1762         /* need to release vmdq resource if exists */
1763         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1764                 i40e_vsi_release(pf->vmdq[i].vsi);
1765                 pf->vmdq[i].vsi = NULL;
1766         }
1767         rte_free(pf->vmdq);
1768         pf->vmdq = NULL;
1769 err:
1770         /* need to release fdir resource if exists */
1771         i40e_fdir_teardown(pf);
1772         return ret;
1773 }
1774
1775 void
1776 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1777 {
1778         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1779         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1780         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1781         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1782         uint16_t msix_vect = vsi->msix_intr;
1783         uint16_t i;
1784
1785         for (i = 0; i < vsi->nb_qps; i++) {
1786                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1787                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1788                 rte_wmb();
1789         }
1790
1791         if (vsi->type != I40E_VSI_SRIOV) {
1792                 if (!rte_intr_allow_others(intr_handle)) {
1793                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1794                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1795                         I40E_WRITE_REG(hw,
1796                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1797                                        0);
1798                 } else {
1799                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1800                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1801                         I40E_WRITE_REG(hw,
1802                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1803                                                        msix_vect - 1), 0);
1804                 }
1805         } else {
1806                 uint32_t reg;
1807                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1808                         vsi->user_param + (msix_vect - 1);
1809
1810                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1811                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1812         }
1813         I40E_WRITE_FLUSH(hw);
1814 }
1815
1816 static void
1817 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1818                        int base_queue, int nb_queue,
1819                        uint16_t itr_idx)
1820 {
1821         int i;
1822         uint32_t val;
1823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1824         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1825
1826         /* Bind all RX queues to allocated MSIX interrupt */
1827         for (i = 0; i < nb_queue; i++) {
1828                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1829                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1830                         ((base_queue + i + 1) <<
1831                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1832                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1833                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1834
1835                 if (i == nb_queue - 1)
1836                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1837                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1838         }
1839
1840         /* Write first RX queue to Link list register as the head element */
1841         if (vsi->type != I40E_VSI_SRIOV) {
1842                 uint16_t interval =
1843                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1844
1845                 if (msix_vect == I40E_MISC_VEC_ID) {
1846                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1847                                        (base_queue <<
1848                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1849                                        (0x0 <<
1850                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1851                         I40E_WRITE_REG(hw,
1852                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1853                                        interval);
1854                 } else {
1855                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1856                                        (base_queue <<
1857                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1858                                        (0x0 <<
1859                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1860                         I40E_WRITE_REG(hw,
1861                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1862                                                        msix_vect - 1),
1863                                        interval);
1864                 }
1865         } else {
1866                 uint32_t reg;
1867
1868                 if (msix_vect == I40E_MISC_VEC_ID) {
1869                         I40E_WRITE_REG(hw,
1870                                        I40E_VPINT_LNKLST0(vsi->user_param),
1871                                        (base_queue <<
1872                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1873                                        (0x0 <<
1874                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1875                 } else {
1876                         /* num_msix_vectors_vf needs to minus irq0 */
1877                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1878                                 vsi->user_param + (msix_vect - 1);
1879
1880                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1881                                        (base_queue <<
1882                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1883                                        (0x0 <<
1884                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1885                 }
1886         }
1887
1888         I40E_WRITE_FLUSH(hw);
1889 }
1890
1891 void
1892 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1893 {
1894         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1895         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1898         uint16_t msix_vect = vsi->msix_intr;
1899         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1900         uint16_t queue_idx = 0;
1901         int record = 0;
1902         int i;
1903
1904         for (i = 0; i < vsi->nb_qps; i++) {
1905                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1906                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1907         }
1908
1909         /* VF bind interrupt */
1910         if (vsi->type == I40E_VSI_SRIOV) {
1911                 __vsi_queues_bind_intr(vsi, msix_vect,
1912                                        vsi->base_queue, vsi->nb_qps,
1913                                        itr_idx);
1914                 return;
1915         }
1916
1917         /* PF & VMDq bind interrupt */
1918         if (rte_intr_dp_is_en(intr_handle)) {
1919                 if (vsi->type == I40E_VSI_MAIN) {
1920                         queue_idx = 0;
1921                         record = 1;
1922                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1923                         struct i40e_vsi *main_vsi =
1924                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1925                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1926                         record = 1;
1927                 }
1928         }
1929
1930         for (i = 0; i < vsi->nb_used_qps; i++) {
1931                 if (nb_msix <= 1) {
1932                         if (!rte_intr_allow_others(intr_handle))
1933                                 /* allow to share MISC_VEC_ID */
1934                                 msix_vect = I40E_MISC_VEC_ID;
1935
1936                         /* no enough msix_vect, map all to one */
1937                         __vsi_queues_bind_intr(vsi, msix_vect,
1938                                                vsi->base_queue + i,
1939                                                vsi->nb_used_qps - i,
1940                                                itr_idx);
1941                         for (; !!record && i < vsi->nb_used_qps; i++)
1942                                 intr_handle->intr_vec[queue_idx + i] =
1943                                         msix_vect;
1944                         break;
1945                 }
1946                 /* 1:1 queue/msix_vect mapping */
1947                 __vsi_queues_bind_intr(vsi, msix_vect,
1948                                        vsi->base_queue + i, 1,
1949                                        itr_idx);
1950                 if (!!record)
1951                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1952
1953                 msix_vect++;
1954                 nb_msix--;
1955         }
1956 }
1957
1958 static void
1959 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1960 {
1961         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1962         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1963         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1964         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1965         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1966         uint16_t msix_intr, i;
1967
1968         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1969                 for (i = 0; i < vsi->nb_msix; i++) {
1970                         msix_intr = vsi->msix_intr + i;
1971                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1972                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1973                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1974                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1975                 }
1976         else
1977                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1978                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1979                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1980                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1981
1982         I40E_WRITE_FLUSH(hw);
1983 }
1984
1985 static void
1986 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1987 {
1988         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1992         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1993         uint16_t msix_intr, i;
1994
1995         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1996                 for (i = 0; i < vsi->nb_msix; i++) {
1997                         msix_intr = vsi->msix_intr + i;
1998                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1999                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2000                 }
2001         else
2002                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2003                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2004
2005         I40E_WRITE_FLUSH(hw);
2006 }
2007
2008 static inline uint8_t
2009 i40e_parse_link_speeds(uint16_t link_speeds)
2010 {
2011         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2012
2013         if (link_speeds & ETH_LINK_SPEED_40G)
2014                 link_speed |= I40E_LINK_SPEED_40GB;
2015         if (link_speeds & ETH_LINK_SPEED_25G)
2016                 link_speed |= I40E_LINK_SPEED_25GB;
2017         if (link_speeds & ETH_LINK_SPEED_20G)
2018                 link_speed |= I40E_LINK_SPEED_20GB;
2019         if (link_speeds & ETH_LINK_SPEED_10G)
2020                 link_speed |= I40E_LINK_SPEED_10GB;
2021         if (link_speeds & ETH_LINK_SPEED_1G)
2022                 link_speed |= I40E_LINK_SPEED_1GB;
2023         if (link_speeds & ETH_LINK_SPEED_100M)
2024                 link_speed |= I40E_LINK_SPEED_100MB;
2025
2026         return link_speed;
2027 }
2028
2029 static int
2030 i40e_phy_conf_link(struct i40e_hw *hw,
2031                    uint8_t abilities,
2032                    uint8_t force_speed,
2033                    bool is_up)
2034 {
2035         enum i40e_status_code status;
2036         struct i40e_aq_get_phy_abilities_resp phy_ab;
2037         struct i40e_aq_set_phy_config phy_conf;
2038         enum i40e_aq_phy_type cnt;
2039         uint8_t avail_speed;
2040         uint32_t phy_type_mask = 0;
2041
2042         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2043                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2044                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2045                         I40E_AQ_PHY_FLAG_LOW_POWER;
2046         int ret = -ENOTSUP;
2047
2048         /* To get phy capabilities of available speeds. */
2049         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2050                                               NULL);
2051         if (status) {
2052                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2053                                 status);
2054                 return ret;
2055         }
2056         avail_speed = phy_ab.link_speed;
2057
2058         /* To get the current phy config. */
2059         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2060                                               NULL);
2061         if (status) {
2062                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2063                                 status);
2064                 return ret;
2065         }
2066
2067         /* If link needs to go up and it is in autoneg mode the speed is OK,
2068          * no need to set up again.
2069          */
2070         if (is_up && phy_ab.phy_type != 0 &&
2071                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2072                      phy_ab.link_speed != 0)
2073                 return I40E_SUCCESS;
2074
2075         memset(&phy_conf, 0, sizeof(phy_conf));
2076
2077         /* bits 0-2 use the values from get_phy_abilities_resp */
2078         abilities &= ~mask;
2079         abilities |= phy_ab.abilities & mask;
2080
2081         phy_conf.abilities = abilities;
2082
2083         /* If link needs to go up, but the force speed is not supported,
2084          * Warn users and config the default available speeds.
2085          */
2086         if (is_up && !(force_speed & avail_speed)) {
2087                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2088                 phy_conf.link_speed = avail_speed;
2089         } else {
2090                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2091         }
2092
2093         /* PHY type mask needs to include each type except PHY type extension */
2094         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2095                 phy_type_mask |= 1 << cnt;
2096
2097         /* use get_phy_abilities_resp value for the rest */
2098         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2099         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2100                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2101                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2102         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2103         phy_conf.eee_capability = phy_ab.eee_capability;
2104         phy_conf.eeer = phy_ab.eeer_val;
2105         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2106
2107         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2108                     phy_ab.abilities, phy_ab.link_speed);
2109         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2110                     phy_conf.abilities, phy_conf.link_speed);
2111
2112         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2113         if (status)
2114                 return ret;
2115
2116         return I40E_SUCCESS;
2117 }
2118
2119 static int
2120 i40e_apply_link_speed(struct rte_eth_dev *dev)
2121 {
2122         uint8_t speed;
2123         uint8_t abilities = 0;
2124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2125         struct rte_eth_conf *conf = &dev->data->dev_conf;
2126
2127         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2128                 conf->link_speeds = ETH_LINK_SPEED_40G |
2129                                     ETH_LINK_SPEED_25G |
2130                                     ETH_LINK_SPEED_20G |
2131                                     ETH_LINK_SPEED_10G |
2132                                     ETH_LINK_SPEED_1G |
2133                                     ETH_LINK_SPEED_100M;
2134         }
2135         speed = i40e_parse_link_speeds(conf->link_speeds);
2136         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2137                      I40E_AQ_PHY_AN_ENABLED |
2138                      I40E_AQ_PHY_LINK_ENABLED;
2139
2140         return i40e_phy_conf_link(hw, abilities, speed, true);
2141 }
2142
2143 static int
2144 i40e_dev_start(struct rte_eth_dev *dev)
2145 {
2146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148         struct i40e_vsi *main_vsi = pf->main_vsi;
2149         int ret, i;
2150         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2151         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2152         uint32_t intr_vector = 0;
2153         struct i40e_vsi *vsi;
2154
2155         hw->adapter_stopped = 0;
2156
2157         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2158                 PMD_INIT_LOG(ERR,
2159                 "Invalid link_speeds for port %u, autonegotiation disabled",
2160                               dev->data->port_id);
2161                 return -EINVAL;
2162         }
2163
2164         rte_intr_disable(intr_handle);
2165
2166         if ((rte_intr_cap_multiple(intr_handle) ||
2167              !RTE_ETH_DEV_SRIOV(dev).active) &&
2168             dev->data->dev_conf.intr_conf.rxq != 0) {
2169                 intr_vector = dev->data->nb_rx_queues;
2170                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2171                 if (ret)
2172                         return ret;
2173         }
2174
2175         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2176                 intr_handle->intr_vec =
2177                         rte_zmalloc("intr_vec",
2178                                     dev->data->nb_rx_queues * sizeof(int),
2179                                     0);
2180                 if (!intr_handle->intr_vec) {
2181                         PMD_INIT_LOG(ERR,
2182                                 "Failed to allocate %d rx_queues intr_vec",
2183                                 dev->data->nb_rx_queues);
2184                         return -ENOMEM;
2185                 }
2186         }
2187
2188         /* Initialize VSI */
2189         ret = i40e_dev_rxtx_init(pf);
2190         if (ret != I40E_SUCCESS) {
2191                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2192                 goto err_up;
2193         }
2194
2195         /* Map queues with MSIX interrupt */
2196         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2197                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2198         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2199         i40e_vsi_enable_queues_intr(main_vsi);
2200
2201         /* Map VMDQ VSI queues with MSIX interrupt */
2202         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2203                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2204                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2205                                           I40E_ITR_INDEX_DEFAULT);
2206                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2207         }
2208
2209         /* enable FDIR MSIX interrupt */
2210         if (pf->fdir.fdir_vsi) {
2211                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2212                                           I40E_ITR_INDEX_NONE);
2213                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2214         }
2215
2216         /* Enable all queues which have been configured */
2217         ret = i40e_dev_switch_queues(pf, TRUE);
2218         if (ret != I40E_SUCCESS) {
2219                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2220                 goto err_up;
2221         }
2222
2223         /* Enable receiving broadcast packets */
2224         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2225         if (ret != I40E_SUCCESS)
2226                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2227
2228         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2229                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2230                                                 true, NULL);
2231                 if (ret != I40E_SUCCESS)
2232                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2233         }
2234
2235         /* Enable the VLAN promiscuous mode. */
2236         if (pf->vfs) {
2237                 for (i = 0; i < pf->vf_num; i++) {
2238                         vsi = pf->vfs[i].vsi;
2239                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2240                                                      true, NULL);
2241                 }
2242         }
2243
2244         /* Enable mac loopback mode */
2245         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2246             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2247                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2248                 if (ret != I40E_SUCCESS) {
2249                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2250                         goto err_up;
2251                 }
2252         }
2253
2254         /* Apply link configure */
2255         ret = i40e_apply_link_speed(dev);
2256         if (I40E_SUCCESS != ret) {
2257                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2258                 goto err_up;
2259         }
2260
2261         if (!rte_intr_allow_others(intr_handle)) {
2262                 rte_intr_callback_unregister(intr_handle,
2263                                              i40e_dev_interrupt_handler,
2264                                              (void *)dev);
2265                 /* configure and enable device interrupt */
2266                 i40e_pf_config_irq0(hw, FALSE);
2267                 i40e_pf_enable_irq0(hw);
2268
2269                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2270                         PMD_INIT_LOG(INFO,
2271                                 "lsc won't enable because of no intr multiplex");
2272         } else {
2273                 ret = i40e_aq_set_phy_int_mask(hw,
2274                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2275                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2276                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2277                 if (ret != I40E_SUCCESS)
2278                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2279
2280                 /* Call get_link_info aq commond to enable/disable LSE */
2281                 i40e_dev_link_update(dev, 0);
2282         }
2283
2284         /* enable uio intr after callback register */
2285         rte_intr_enable(intr_handle);
2286
2287         i40e_filter_restore(pf);
2288
2289         if (pf->tm_conf.root && !pf->tm_conf.committed)
2290                 PMD_DRV_LOG(WARNING,
2291                             "please call hierarchy_commit() "
2292                             "before starting the port");
2293
2294         return I40E_SUCCESS;
2295
2296 err_up:
2297         i40e_dev_switch_queues(pf, FALSE);
2298         i40e_dev_clear_queues(dev);
2299
2300         return ret;
2301 }
2302
2303 static void
2304 i40e_dev_stop(struct rte_eth_dev *dev)
2305 {
2306         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2307         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308         struct i40e_vsi *main_vsi = pf->main_vsi;
2309         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2310         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2311         int i;
2312
2313         if (hw->adapter_stopped == 1)
2314                 return;
2315         /* Disable all queues */
2316         i40e_dev_switch_queues(pf, FALSE);
2317
2318         /* un-map queues with interrupt registers */
2319         i40e_vsi_disable_queues_intr(main_vsi);
2320         i40e_vsi_queues_unbind_intr(main_vsi);
2321
2322         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2323                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2324                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2325         }
2326
2327         if (pf->fdir.fdir_vsi) {
2328                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2329                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2330         }
2331         /* Clear all queues and release memory */
2332         i40e_dev_clear_queues(dev);
2333
2334         /* Set link down */
2335         i40e_dev_set_link_down(dev);
2336
2337         if (!rte_intr_allow_others(intr_handle))
2338                 /* resume to the default handler */
2339                 rte_intr_callback_register(intr_handle,
2340                                            i40e_dev_interrupt_handler,
2341                                            (void *)dev);
2342
2343         /* Clean datapath event and queue/vec mapping */
2344         rte_intr_efd_disable(intr_handle);
2345         if (intr_handle->intr_vec) {
2346                 rte_free(intr_handle->intr_vec);
2347                 intr_handle->intr_vec = NULL;
2348         }
2349
2350         /* reset hierarchy commit */
2351         pf->tm_conf.committed = false;
2352
2353         hw->adapter_stopped = 1;
2354 }
2355
2356 static void
2357 i40e_dev_close(struct rte_eth_dev *dev)
2358 {
2359         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2362         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2363         struct i40e_mirror_rule *p_mirror;
2364         uint32_t reg;
2365         int i;
2366         int ret;
2367
2368         PMD_INIT_FUNC_TRACE();
2369
2370         i40e_dev_stop(dev);
2371
2372         /* Remove all mirror rules */
2373         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2374                 ret = i40e_aq_del_mirror_rule(hw,
2375                                               pf->main_vsi->veb->seid,
2376                                               p_mirror->rule_type,
2377                                               p_mirror->entries,
2378                                               p_mirror->num_entries,
2379                                               p_mirror->id);
2380                 if (ret < 0)
2381                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2382                                     "status = %d, aq_err = %d.", ret,
2383                                     hw->aq.asq_last_status);
2384
2385                 /* remove mirror software resource anyway */
2386                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2387                 rte_free(p_mirror);
2388                 pf->nb_mirror_rule--;
2389         }
2390
2391         i40e_dev_free_queues(dev);
2392
2393         /* Disable interrupt */
2394         i40e_pf_disable_irq0(hw);
2395         rte_intr_disable(intr_handle);
2396
2397         i40e_fdir_teardown(pf);
2398
2399         /* shutdown and destroy the HMC */
2400         i40e_shutdown_lan_hmc(hw);
2401
2402         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2403                 i40e_vsi_release(pf->vmdq[i].vsi);
2404                 pf->vmdq[i].vsi = NULL;
2405         }
2406         rte_free(pf->vmdq);
2407         pf->vmdq = NULL;
2408
2409         /* release all the existing VSIs and VEBs */
2410         i40e_vsi_release(pf->main_vsi);
2411
2412         /* shutdown the adminq */
2413         i40e_aq_queue_shutdown(hw, true);
2414         i40e_shutdown_adminq(hw);
2415
2416         i40e_res_pool_destroy(&pf->qp_pool);
2417         i40e_res_pool_destroy(&pf->msix_pool);
2418
2419         /* Disable flexible payload in global configuration */
2420         if (!pf->support_multi_driver)
2421                 i40e_flex_payload_reg_set_default(hw);
2422
2423         /* force a PF reset to clean anything leftover */
2424         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2425         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2426                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2427         I40E_WRITE_FLUSH(hw);
2428 }
2429
2430 /*
2431  * Reset PF device only to re-initialize resources in PMD layer
2432  */
2433 static int
2434 i40e_dev_reset(struct rte_eth_dev *dev)
2435 {
2436         int ret;
2437
2438         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2439          * its VF to make them align with it. The detailed notification
2440          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2441          * To avoid unexpected behavior in VF, currently reset of PF with
2442          * SR-IOV activation is not supported. It might be supported later.
2443          */
2444         if (dev->data->sriov.active)
2445                 return -ENOTSUP;
2446
2447         ret = eth_i40e_dev_uninit(dev);
2448         if (ret)
2449                 return ret;
2450
2451         ret = eth_i40e_dev_init(dev, NULL);
2452
2453         return ret;
2454 }
2455
2456 static void
2457 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2458 {
2459         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2460         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461         struct i40e_vsi *vsi = pf->main_vsi;
2462         int status;
2463
2464         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2465                                                      true, NULL, true);
2466         if (status != I40E_SUCCESS)
2467                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2468
2469         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2470                                                         TRUE, NULL);
2471         if (status != I40E_SUCCESS)
2472                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2473
2474 }
2475
2476 static void
2477 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2478 {
2479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2481         struct i40e_vsi *vsi = pf->main_vsi;
2482         int status;
2483
2484         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2485                                                      false, NULL, true);
2486         if (status != I40E_SUCCESS)
2487                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2488
2489         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2490                                                         false, NULL);
2491         if (status != I40E_SUCCESS)
2492                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2493 }
2494
2495 static void
2496 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2497 {
2498         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2499         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2500         struct i40e_vsi *vsi = pf->main_vsi;
2501         int ret;
2502
2503         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2504         if (ret != I40E_SUCCESS)
2505                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2506 }
2507
2508 static void
2509 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2510 {
2511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         struct i40e_vsi *vsi = pf->main_vsi;
2514         int ret;
2515
2516         if (dev->data->promiscuous == 1)
2517                 return; /* must remain in all_multicast mode */
2518
2519         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2520                                 vsi->seid, FALSE, NULL);
2521         if (ret != I40E_SUCCESS)
2522                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2523 }
2524
2525 /*
2526  * Set device link up.
2527  */
2528 static int
2529 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2530 {
2531         /* re-apply link speed setting */
2532         return i40e_apply_link_speed(dev);
2533 }
2534
2535 /*
2536  * Set device link down.
2537  */
2538 static int
2539 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2540 {
2541         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2542         uint8_t abilities = 0;
2543         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2544
2545         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2546         return i40e_phy_conf_link(hw, abilities, speed, false);
2547 }
2548
2549 static __rte_always_inline void
2550 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2551 {
2552 /* Link status registers and values*/
2553 #define I40E_PRTMAC_LINKSTA             0x001E2420
2554 #define I40E_REG_LINK_UP                0x40000080
2555 #define I40E_PRTMAC_MACC                0x001E24E0
2556 #define I40E_REG_MACC_25GB              0x00020000
2557 #define I40E_REG_SPEED_MASK             0x38000000
2558 #define I40E_REG_SPEED_100MB            0x00000000
2559 #define I40E_REG_SPEED_1GB              0x08000000
2560 #define I40E_REG_SPEED_10GB             0x10000000
2561 #define I40E_REG_SPEED_20GB             0x20000000
2562 #define I40E_REG_SPEED_25_40GB          0x18000000
2563         uint32_t link_speed;
2564         uint32_t reg_val;
2565
2566         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2567         link_speed = reg_val & I40E_REG_SPEED_MASK;
2568         reg_val &= I40E_REG_LINK_UP;
2569         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2570
2571         if (unlikely(link->link_status == 0))
2572                 return;
2573
2574         /* Parse the link status */
2575         switch (link_speed) {
2576         case I40E_REG_SPEED_100MB:
2577                 link->link_speed = ETH_SPEED_NUM_100M;
2578                 break;
2579         case I40E_REG_SPEED_1GB:
2580                 link->link_speed = ETH_SPEED_NUM_1G;
2581                 break;
2582         case I40E_REG_SPEED_10GB:
2583                 link->link_speed = ETH_SPEED_NUM_10G;
2584                 break;
2585         case I40E_REG_SPEED_20GB:
2586                 link->link_speed = ETH_SPEED_NUM_20G;
2587                 break;
2588         case I40E_REG_SPEED_25_40GB:
2589                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2590
2591                 if (reg_val & I40E_REG_MACC_25GB)
2592                         link->link_speed = ETH_SPEED_NUM_25G;
2593                 else
2594                         link->link_speed = ETH_SPEED_NUM_40G;
2595
2596                 break;
2597         default:
2598                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2599                 break;
2600         }
2601 }
2602
2603 static __rte_always_inline void
2604 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2605         bool enable_lse, int wait_to_complete)
2606 {
2607 #define CHECK_INTERVAL             100  /* 100ms */
2608 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2609         uint32_t rep_cnt = MAX_REPEAT_TIME;
2610         struct i40e_link_status link_status;
2611         int status;
2612
2613         memset(&link_status, 0, sizeof(link_status));
2614
2615         do {
2616                 memset(&link_status, 0, sizeof(link_status));
2617
2618                 /* Get link status information from hardware */
2619                 status = i40e_aq_get_link_info(hw, enable_lse,
2620                                                 &link_status, NULL);
2621                 if (unlikely(status != I40E_SUCCESS)) {
2622                         link->link_speed = ETH_SPEED_NUM_100M;
2623                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2624                         PMD_DRV_LOG(ERR, "Failed to get link info");
2625                         return;
2626                 }
2627
2628                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2629                 if (!wait_to_complete || link->link_status)
2630                         break;
2631
2632                 rte_delay_ms(CHECK_INTERVAL);
2633         } while (--rep_cnt);
2634
2635         /* Parse the link status */
2636         switch (link_status.link_speed) {
2637         case I40E_LINK_SPEED_100MB:
2638                 link->link_speed = ETH_SPEED_NUM_100M;
2639                 break;
2640         case I40E_LINK_SPEED_1GB:
2641                 link->link_speed = ETH_SPEED_NUM_1G;
2642                 break;
2643         case I40E_LINK_SPEED_10GB:
2644                 link->link_speed = ETH_SPEED_NUM_10G;
2645                 break;
2646         case I40E_LINK_SPEED_20GB:
2647                 link->link_speed = ETH_SPEED_NUM_20G;
2648                 break;
2649         case I40E_LINK_SPEED_25GB:
2650                 link->link_speed = ETH_SPEED_NUM_25G;
2651                 break;
2652         case I40E_LINK_SPEED_40GB:
2653                 link->link_speed = ETH_SPEED_NUM_40G;
2654                 break;
2655         default:
2656                 link->link_speed = ETH_SPEED_NUM_100M;
2657                 break;
2658         }
2659 }
2660
2661 int
2662 i40e_dev_link_update(struct rte_eth_dev *dev,
2663                      int wait_to_complete)
2664 {
2665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2666         struct rte_eth_link link;
2667         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2668         int ret;
2669
2670         memset(&link, 0, sizeof(link));
2671
2672         /* i40e uses full duplex only */
2673         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2674         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2675                         ETH_LINK_SPEED_FIXED);
2676
2677         if (!wait_to_complete && !enable_lse)
2678                 update_link_reg(hw, &link);
2679         else
2680                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2681
2682         ret = rte_eth_linkstatus_set(dev, &link);
2683         i40e_notify_all_vfs_link_status(dev);
2684
2685         return ret;
2686 }
2687
2688 /* Get all the statistics of a VSI */
2689 void
2690 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2691 {
2692         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2693         struct i40e_eth_stats *nes = &vsi->eth_stats;
2694         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2695         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2696
2697         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2698                             vsi->offset_loaded, &oes->rx_bytes,
2699                             &nes->rx_bytes);
2700         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2701                             vsi->offset_loaded, &oes->rx_unicast,
2702                             &nes->rx_unicast);
2703         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2704                             vsi->offset_loaded, &oes->rx_multicast,
2705                             &nes->rx_multicast);
2706         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2707                             vsi->offset_loaded, &oes->rx_broadcast,
2708                             &nes->rx_broadcast);
2709         /* exclude CRC bytes */
2710         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2711                 nes->rx_broadcast) * ETHER_CRC_LEN;
2712
2713         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2714                             &oes->rx_discards, &nes->rx_discards);
2715         /* GLV_REPC not supported */
2716         /* GLV_RMPC not supported */
2717         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2718                             &oes->rx_unknown_protocol,
2719                             &nes->rx_unknown_protocol);
2720         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2721                             vsi->offset_loaded, &oes->tx_bytes,
2722                             &nes->tx_bytes);
2723         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2724                             vsi->offset_loaded, &oes->tx_unicast,
2725                             &nes->tx_unicast);
2726         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2727                             vsi->offset_loaded, &oes->tx_multicast,
2728                             &nes->tx_multicast);
2729         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2730                             vsi->offset_loaded,  &oes->tx_broadcast,
2731                             &nes->tx_broadcast);
2732         /* GLV_TDPC not supported */
2733         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2734                             &oes->tx_errors, &nes->tx_errors);
2735         vsi->offset_loaded = true;
2736
2737         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2738                     vsi->vsi_id);
2739         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2740         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2741         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2742         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2743         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2744         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2745                     nes->rx_unknown_protocol);
2746         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2747         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2748         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2749         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2750         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2751         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2752         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2753                     vsi->vsi_id);
2754 }
2755
2756 static void
2757 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2758 {
2759         unsigned int i;
2760         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2761         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2762
2763         /* Get rx/tx bytes of internal transfer packets */
2764         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2765                         I40E_GLV_GORCL(hw->port),
2766                         pf->offset_loaded,
2767                         &pf->internal_stats_offset.rx_bytes,
2768                         &pf->internal_stats.rx_bytes);
2769
2770         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2771                         I40E_GLV_GOTCL(hw->port),
2772                         pf->offset_loaded,
2773                         &pf->internal_stats_offset.tx_bytes,
2774                         &pf->internal_stats.tx_bytes);
2775         /* Get total internal rx packet count */
2776         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2777                             I40E_GLV_UPRCL(hw->port),
2778                             pf->offset_loaded,
2779                             &pf->internal_stats_offset.rx_unicast,
2780                             &pf->internal_stats.rx_unicast);
2781         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2782                             I40E_GLV_MPRCL(hw->port),
2783                             pf->offset_loaded,
2784                             &pf->internal_stats_offset.rx_multicast,
2785                             &pf->internal_stats.rx_multicast);
2786         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2787                             I40E_GLV_BPRCL(hw->port),
2788                             pf->offset_loaded,
2789                             &pf->internal_stats_offset.rx_broadcast,
2790                             &pf->internal_stats.rx_broadcast);
2791         /* Get total internal tx packet count */
2792         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2793                             I40E_GLV_UPTCL(hw->port),
2794                             pf->offset_loaded,
2795                             &pf->internal_stats_offset.tx_unicast,
2796                             &pf->internal_stats.tx_unicast);
2797         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2798                             I40E_GLV_MPTCL(hw->port),
2799                             pf->offset_loaded,
2800                             &pf->internal_stats_offset.tx_multicast,
2801                             &pf->internal_stats.tx_multicast);
2802         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2803                             I40E_GLV_BPTCL(hw->port),
2804                             pf->offset_loaded,
2805                             &pf->internal_stats_offset.tx_broadcast,
2806                             &pf->internal_stats.tx_broadcast);
2807
2808         /* exclude CRC size */
2809         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2810                 pf->internal_stats.rx_multicast +
2811                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2812
2813         /* Get statistics of struct i40e_eth_stats */
2814         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2815                             I40E_GLPRT_GORCL(hw->port),
2816                             pf->offset_loaded, &os->eth.rx_bytes,
2817                             &ns->eth.rx_bytes);
2818         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2819                             I40E_GLPRT_UPRCL(hw->port),
2820                             pf->offset_loaded, &os->eth.rx_unicast,
2821                             &ns->eth.rx_unicast);
2822         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2823                             I40E_GLPRT_MPRCL(hw->port),
2824                             pf->offset_loaded, &os->eth.rx_multicast,
2825                             &ns->eth.rx_multicast);
2826         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2827                             I40E_GLPRT_BPRCL(hw->port),
2828                             pf->offset_loaded, &os->eth.rx_broadcast,
2829                             &ns->eth.rx_broadcast);
2830         /* Workaround: CRC size should not be included in byte statistics,
2831          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2832          */
2833         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2834                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2835
2836         /* exclude internal rx bytes
2837          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2838          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2839          * value.
2840          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2841          */
2842         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2843                 ns->eth.rx_bytes = 0;
2844         else
2845                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2846
2847         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2848                 ns->eth.rx_unicast = 0;
2849         else
2850                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2851
2852         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2853                 ns->eth.rx_multicast = 0;
2854         else
2855                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2856
2857         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2858                 ns->eth.rx_broadcast = 0;
2859         else
2860                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2861
2862         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2863                             pf->offset_loaded, &os->eth.rx_discards,
2864                             &ns->eth.rx_discards);
2865         /* GLPRT_REPC not supported */
2866         /* GLPRT_RMPC not supported */
2867         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2868                             pf->offset_loaded,
2869                             &os->eth.rx_unknown_protocol,
2870                             &ns->eth.rx_unknown_protocol);
2871         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2872                             I40E_GLPRT_GOTCL(hw->port),
2873                             pf->offset_loaded, &os->eth.tx_bytes,
2874                             &ns->eth.tx_bytes);
2875         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2876                             I40E_GLPRT_UPTCL(hw->port),
2877                             pf->offset_loaded, &os->eth.tx_unicast,
2878                             &ns->eth.tx_unicast);
2879         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2880                             I40E_GLPRT_MPTCL(hw->port),
2881                             pf->offset_loaded, &os->eth.tx_multicast,
2882                             &ns->eth.tx_multicast);
2883         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2884                             I40E_GLPRT_BPTCL(hw->port),
2885                             pf->offset_loaded, &os->eth.tx_broadcast,
2886                             &ns->eth.tx_broadcast);
2887         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2888                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2889
2890         /* exclude internal tx bytes
2891          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2892          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2893          * value.
2894          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2895          */
2896         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2897                 ns->eth.tx_bytes = 0;
2898         else
2899                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2900
2901         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2902                 ns->eth.tx_unicast = 0;
2903         else
2904                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2905
2906         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2907                 ns->eth.tx_multicast = 0;
2908         else
2909                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2910
2911         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2912                 ns->eth.tx_broadcast = 0;
2913         else
2914                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2915
2916         /* GLPRT_TEPC not supported */
2917
2918         /* additional port specific stats */
2919         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2920                             pf->offset_loaded, &os->tx_dropped_link_down,
2921                             &ns->tx_dropped_link_down);
2922         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2923                             pf->offset_loaded, &os->crc_errors,
2924                             &ns->crc_errors);
2925         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2926                             pf->offset_loaded, &os->illegal_bytes,
2927                             &ns->illegal_bytes);
2928         /* GLPRT_ERRBC not supported */
2929         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2930                             pf->offset_loaded, &os->mac_local_faults,
2931                             &ns->mac_local_faults);
2932         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2933                             pf->offset_loaded, &os->mac_remote_faults,
2934                             &ns->mac_remote_faults);
2935         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2936                             pf->offset_loaded, &os->rx_length_errors,
2937                             &ns->rx_length_errors);
2938         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2939                             pf->offset_loaded, &os->link_xon_rx,
2940                             &ns->link_xon_rx);
2941         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2942                             pf->offset_loaded, &os->link_xoff_rx,
2943                             &ns->link_xoff_rx);
2944         for (i = 0; i < 8; i++) {
2945                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2946                                     pf->offset_loaded,
2947                                     &os->priority_xon_rx[i],
2948                                     &ns->priority_xon_rx[i]);
2949                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2950                                     pf->offset_loaded,
2951                                     &os->priority_xoff_rx[i],
2952                                     &ns->priority_xoff_rx[i]);
2953         }
2954         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2955                             pf->offset_loaded, &os->link_xon_tx,
2956                             &ns->link_xon_tx);
2957         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2958                             pf->offset_loaded, &os->link_xoff_tx,
2959                             &ns->link_xoff_tx);
2960         for (i = 0; i < 8; i++) {
2961                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2962                                     pf->offset_loaded,
2963                                     &os->priority_xon_tx[i],
2964                                     &ns->priority_xon_tx[i]);
2965                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2966                                     pf->offset_loaded,
2967                                     &os->priority_xoff_tx[i],
2968                                     &ns->priority_xoff_tx[i]);
2969                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2970                                     pf->offset_loaded,
2971                                     &os->priority_xon_2_xoff[i],
2972                                     &ns->priority_xon_2_xoff[i]);
2973         }
2974         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2975                             I40E_GLPRT_PRC64L(hw->port),
2976                             pf->offset_loaded, &os->rx_size_64,
2977                             &ns->rx_size_64);
2978         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2979                             I40E_GLPRT_PRC127L(hw->port),
2980                             pf->offset_loaded, &os->rx_size_127,
2981                             &ns->rx_size_127);
2982         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2983                             I40E_GLPRT_PRC255L(hw->port),
2984                             pf->offset_loaded, &os->rx_size_255,
2985                             &ns->rx_size_255);
2986         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2987                             I40E_GLPRT_PRC511L(hw->port),
2988                             pf->offset_loaded, &os->rx_size_511,
2989                             &ns->rx_size_511);
2990         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2991                             I40E_GLPRT_PRC1023L(hw->port),
2992                             pf->offset_loaded, &os->rx_size_1023,
2993                             &ns->rx_size_1023);
2994         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2995                             I40E_GLPRT_PRC1522L(hw->port),
2996                             pf->offset_loaded, &os->rx_size_1522,
2997                             &ns->rx_size_1522);
2998         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2999                             I40E_GLPRT_PRC9522L(hw->port),
3000                             pf->offset_loaded, &os->rx_size_big,
3001                             &ns->rx_size_big);
3002         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3003                             pf->offset_loaded, &os->rx_undersize,
3004                             &ns->rx_undersize);
3005         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3006                             pf->offset_loaded, &os->rx_fragments,
3007                             &ns->rx_fragments);
3008         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3009                             pf->offset_loaded, &os->rx_oversize,
3010                             &ns->rx_oversize);
3011         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3012                             pf->offset_loaded, &os->rx_jabber,
3013                             &ns->rx_jabber);
3014         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3015                             I40E_GLPRT_PTC64L(hw->port),
3016                             pf->offset_loaded, &os->tx_size_64,
3017                             &ns->tx_size_64);
3018         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3019                             I40E_GLPRT_PTC127L(hw->port),
3020                             pf->offset_loaded, &os->tx_size_127,
3021                             &ns->tx_size_127);
3022         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3023                             I40E_GLPRT_PTC255L(hw->port),
3024                             pf->offset_loaded, &os->tx_size_255,
3025                             &ns->tx_size_255);
3026         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3027                             I40E_GLPRT_PTC511L(hw->port),
3028                             pf->offset_loaded, &os->tx_size_511,
3029                             &ns->tx_size_511);
3030         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3031                             I40E_GLPRT_PTC1023L(hw->port),
3032                             pf->offset_loaded, &os->tx_size_1023,
3033                             &ns->tx_size_1023);
3034         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3035                             I40E_GLPRT_PTC1522L(hw->port),
3036                             pf->offset_loaded, &os->tx_size_1522,
3037                             &ns->tx_size_1522);
3038         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3039                             I40E_GLPRT_PTC9522L(hw->port),
3040                             pf->offset_loaded, &os->tx_size_big,
3041                             &ns->tx_size_big);
3042         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3043                            pf->offset_loaded,
3044                            &os->fd_sb_match, &ns->fd_sb_match);
3045         /* GLPRT_MSPDC not supported */
3046         /* GLPRT_XEC not supported */
3047
3048         pf->offset_loaded = true;
3049
3050         if (pf->main_vsi)
3051                 i40e_update_vsi_stats(pf->main_vsi);
3052 }
3053
3054 /* Get all statistics of a port */
3055 static int
3056 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3057 {
3058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3060         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3061         unsigned i;
3062
3063         /* call read registers - updates values, now write them to struct */
3064         i40e_read_stats_registers(pf, hw);
3065
3066         stats->ipackets = ns->eth.rx_unicast +
3067                         ns->eth.rx_multicast +
3068                         ns->eth.rx_broadcast -
3069                         ns->eth.rx_discards -
3070                         pf->main_vsi->eth_stats.rx_discards;
3071         stats->opackets = ns->eth.tx_unicast +
3072                         ns->eth.tx_multicast +
3073                         ns->eth.tx_broadcast;
3074         stats->ibytes   = ns->eth.rx_bytes;
3075         stats->obytes   = ns->eth.tx_bytes;
3076         stats->oerrors  = ns->eth.tx_errors +
3077                         pf->main_vsi->eth_stats.tx_errors;
3078
3079         /* Rx Errors */
3080         stats->imissed  = ns->eth.rx_discards +
3081                         pf->main_vsi->eth_stats.rx_discards;
3082         stats->ierrors  = ns->crc_errors +
3083                         ns->rx_length_errors + ns->rx_undersize +
3084                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3085
3086         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3087         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3088         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3089         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3090         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3091         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3092         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3093                     ns->eth.rx_unknown_protocol);
3094         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3095         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3096         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3097         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3098         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3099         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3100
3101         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3102                     ns->tx_dropped_link_down);
3103         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3104         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3105                     ns->illegal_bytes);
3106         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3107         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3108                     ns->mac_local_faults);
3109         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3110                     ns->mac_remote_faults);
3111         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3112                     ns->rx_length_errors);
3113         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3114         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3115         for (i = 0; i < 8; i++) {
3116                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3117                                 i, ns->priority_xon_rx[i]);
3118                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3119                                 i, ns->priority_xoff_rx[i]);
3120         }
3121         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3122         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3123         for (i = 0; i < 8; i++) {
3124                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3125                                 i, ns->priority_xon_tx[i]);
3126                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3127                                 i, ns->priority_xoff_tx[i]);
3128                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3129                                 i, ns->priority_xon_2_xoff[i]);
3130         }
3131         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3132         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3133         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3134         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3135         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3136         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3137         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3138         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3139         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3140         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3141         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3142         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3143         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3144         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3145         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3146         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3147         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3148         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3149         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3150                         ns->mac_short_packet_dropped);
3151         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3152                     ns->checksum_error);
3153         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3154         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3155         return 0;
3156 }
3157
3158 /* Reset the statistics */
3159 static void
3160 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3161 {
3162         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164
3165         /* Mark PF and VSI stats to update the offset, aka "reset" */
3166         pf->offset_loaded = false;
3167         if (pf->main_vsi)
3168                 pf->main_vsi->offset_loaded = false;
3169
3170         /* read the stats, reading current register values into offset */
3171         i40e_read_stats_registers(pf, hw);
3172 }
3173
3174 static uint32_t
3175 i40e_xstats_calc_num(void)
3176 {
3177         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3178                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3179                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3180 }
3181
3182 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3183                                      struct rte_eth_xstat_name *xstats_names,
3184                                      __rte_unused unsigned limit)
3185 {
3186         unsigned count = 0;
3187         unsigned i, prio;
3188
3189         if (xstats_names == NULL)
3190                 return i40e_xstats_calc_num();
3191
3192         /* Note: limit checked in rte_eth_xstats_names() */
3193
3194         /* Get stats from i40e_eth_stats struct */
3195         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3196                 snprintf(xstats_names[count].name,
3197                          sizeof(xstats_names[count].name),
3198                          "%s", rte_i40e_stats_strings[i].name);
3199                 count++;
3200         }
3201
3202         /* Get individiual stats from i40e_hw_port struct */
3203         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3204                 snprintf(xstats_names[count].name,
3205                         sizeof(xstats_names[count].name),
3206                          "%s", rte_i40e_hw_port_strings[i].name);
3207                 count++;
3208         }
3209
3210         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3211                 for (prio = 0; prio < 8; prio++) {
3212                         snprintf(xstats_names[count].name,
3213                                  sizeof(xstats_names[count].name),
3214                                  "rx_priority%u_%s", prio,
3215                                  rte_i40e_rxq_prio_strings[i].name);
3216                         count++;
3217                 }
3218         }
3219
3220         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3221                 for (prio = 0; prio < 8; prio++) {
3222                         snprintf(xstats_names[count].name,
3223                                  sizeof(xstats_names[count].name),
3224                                  "tx_priority%u_%s", prio,
3225                                  rte_i40e_txq_prio_strings[i].name);
3226                         count++;
3227                 }
3228         }
3229         return count;
3230 }
3231
3232 static int
3233 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3234                     unsigned n)
3235 {
3236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3238         unsigned i, count, prio;
3239         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3240
3241         count = i40e_xstats_calc_num();
3242         if (n < count)
3243                 return count;
3244
3245         i40e_read_stats_registers(pf, hw);
3246
3247         if (xstats == NULL)
3248                 return 0;
3249
3250         count = 0;
3251
3252         /* Get stats from i40e_eth_stats struct */
3253         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3254                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3255                         rte_i40e_stats_strings[i].offset);
3256                 xstats[count].id = count;
3257                 count++;
3258         }
3259
3260         /* Get individiual stats from i40e_hw_port struct */
3261         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3262                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3263                         rte_i40e_hw_port_strings[i].offset);
3264                 xstats[count].id = count;
3265                 count++;
3266         }
3267
3268         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3269                 for (prio = 0; prio < 8; prio++) {
3270                         xstats[count].value =
3271                                 *(uint64_t *)(((char *)hw_stats) +
3272                                 rte_i40e_rxq_prio_strings[i].offset +
3273                                 (sizeof(uint64_t) * prio));
3274                         xstats[count].id = count;
3275                         count++;
3276                 }
3277         }
3278
3279         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3280                 for (prio = 0; prio < 8; prio++) {
3281                         xstats[count].value =
3282                                 *(uint64_t *)(((char *)hw_stats) +
3283                                 rte_i40e_txq_prio_strings[i].offset +
3284                                 (sizeof(uint64_t) * prio));
3285                         xstats[count].id = count;
3286                         count++;
3287                 }
3288         }
3289
3290         return count;
3291 }
3292
3293 static int
3294 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3295                                  __rte_unused uint16_t queue_id,
3296                                  __rte_unused uint8_t stat_idx,
3297                                  __rte_unused uint8_t is_rx)
3298 {
3299         PMD_INIT_FUNC_TRACE();
3300
3301         return -ENOSYS;
3302 }
3303
3304 static int
3305 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3306 {
3307         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3308         u32 full_ver;
3309         u8 ver, patch;
3310         u16 build;
3311         int ret;
3312
3313         full_ver = hw->nvm.oem_ver;
3314         ver = (u8)(full_ver >> 24);
3315         build = (u16)((full_ver >> 8) & 0xffff);
3316         patch = (u8)(full_ver & 0xff);
3317
3318         ret = snprintf(fw_version, fw_size,
3319                  "%d.%d%d 0x%08x %d.%d.%d",
3320                  ((hw->nvm.version >> 12) & 0xf),
3321                  ((hw->nvm.version >> 4) & 0xff),
3322                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3323                  ver, build, patch);
3324
3325         ret += 1; /* add the size of '\0' */
3326         if (fw_size < (u32)ret)
3327                 return ret;
3328         else
3329                 return 0;
3330 }
3331
3332 static void
3333 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3334 {
3335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct i40e_vsi *vsi = pf->main_vsi;
3338         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3339
3340         dev_info->max_rx_queues = vsi->nb_qps;
3341         dev_info->max_tx_queues = vsi->nb_qps;
3342         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3343         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3344         dev_info->max_mac_addrs = vsi->max_macaddrs;
3345         dev_info->max_vfs = pci_dev->max_vfs;
3346         dev_info->rx_queue_offload_capa = 0;
3347         dev_info->rx_offload_capa =
3348                 DEV_RX_OFFLOAD_VLAN_STRIP |
3349                 DEV_RX_OFFLOAD_QINQ_STRIP |
3350                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3351                 DEV_RX_OFFLOAD_UDP_CKSUM |
3352                 DEV_RX_OFFLOAD_TCP_CKSUM |
3353                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3354                 DEV_RX_OFFLOAD_CRC_STRIP |
3355                 DEV_RX_OFFLOAD_KEEP_CRC |
3356                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3357                 DEV_RX_OFFLOAD_VLAN_FILTER |
3358                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3359
3360         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3361         dev_info->tx_offload_capa =
3362                 DEV_TX_OFFLOAD_VLAN_INSERT |
3363                 DEV_TX_OFFLOAD_QINQ_INSERT |
3364                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3365                 DEV_TX_OFFLOAD_UDP_CKSUM |
3366                 DEV_TX_OFFLOAD_TCP_CKSUM |
3367                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3368                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3369                 DEV_TX_OFFLOAD_TCP_TSO |
3370                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3371                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3372                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3373                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3374                 DEV_TX_OFFLOAD_MULTI_SEGS |
3375                 dev_info->tx_queue_offload_capa;
3376         dev_info->dev_capa =
3377                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3378                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3379
3380         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3381                                                 sizeof(uint32_t);
3382         dev_info->reta_size = pf->hash_lut_size;
3383         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3384
3385         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3386                 .rx_thresh = {
3387                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3388                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3389                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3390                 },
3391                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3392                 .rx_drop_en = 0,
3393                 .offloads = 0,
3394         };
3395
3396         dev_info->default_txconf = (struct rte_eth_txconf) {
3397                 .tx_thresh = {
3398                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3399                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3400                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3401                 },
3402                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3403                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3404                 .offloads = 0,
3405         };
3406
3407         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3408                 .nb_max = I40E_MAX_RING_DESC,
3409                 .nb_min = I40E_MIN_RING_DESC,
3410                 .nb_align = I40E_ALIGN_RING_DESC,
3411         };
3412
3413         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3414                 .nb_max = I40E_MAX_RING_DESC,
3415                 .nb_min = I40E_MIN_RING_DESC,
3416                 .nb_align = I40E_ALIGN_RING_DESC,
3417                 .nb_seg_max = I40E_TX_MAX_SEG,
3418                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3419         };
3420
3421         if (pf->flags & I40E_FLAG_VMDQ) {
3422                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3423                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3424                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3425                                                 pf->max_nb_vmdq_vsi;
3426                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3427                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3428                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3429         }
3430
3431         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3432                 /* For XL710 */
3433                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3434                 dev_info->default_rxportconf.nb_queues = 2;
3435                 dev_info->default_txportconf.nb_queues = 2;
3436                 if (dev->data->nb_rx_queues == 1)
3437                         dev_info->default_rxportconf.ring_size = 2048;
3438                 else
3439                         dev_info->default_rxportconf.ring_size = 1024;
3440                 if (dev->data->nb_tx_queues == 1)
3441                         dev_info->default_txportconf.ring_size = 1024;
3442                 else
3443                         dev_info->default_txportconf.ring_size = 512;
3444
3445         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3446                 /* For XXV710 */
3447                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3448                 dev_info->default_rxportconf.nb_queues = 1;
3449                 dev_info->default_txportconf.nb_queues = 1;
3450                 dev_info->default_rxportconf.ring_size = 256;
3451                 dev_info->default_txportconf.ring_size = 256;
3452         } else {
3453                 /* For X710 */
3454                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3455                 dev_info->default_rxportconf.nb_queues = 1;
3456                 dev_info->default_txportconf.nb_queues = 1;
3457                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3458                         dev_info->default_rxportconf.ring_size = 512;
3459                         dev_info->default_txportconf.ring_size = 256;
3460                 } else {
3461                         dev_info->default_rxportconf.ring_size = 256;
3462                         dev_info->default_txportconf.ring_size = 256;
3463                 }
3464         }
3465         dev_info->default_rxportconf.burst_size = 32;
3466         dev_info->default_txportconf.burst_size = 32;
3467 }
3468
3469 static int
3470 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3471 {
3472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3473         struct i40e_vsi *vsi = pf->main_vsi;
3474         PMD_INIT_FUNC_TRACE();
3475
3476         if (on)
3477                 return i40e_vsi_add_vlan(vsi, vlan_id);
3478         else
3479                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3480 }
3481
3482 static int
3483 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3484                                 enum rte_vlan_type vlan_type,
3485                                 uint16_t tpid, int qinq)
3486 {
3487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3488         uint64_t reg_r = 0;
3489         uint64_t reg_w = 0;
3490         uint16_t reg_id = 3;
3491         int ret;
3492
3493         if (qinq) {
3494                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3495                         reg_id = 2;
3496         }
3497
3498         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3499                                           &reg_r, NULL);
3500         if (ret != I40E_SUCCESS) {
3501                 PMD_DRV_LOG(ERR,
3502                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3503                            reg_id);
3504                 return -EIO;
3505         }
3506         PMD_DRV_LOG(DEBUG,
3507                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3508                     reg_id, reg_r);
3509
3510         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3511         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3512         if (reg_r == reg_w) {
3513                 PMD_DRV_LOG(DEBUG, "No need to write");
3514                 return 0;
3515         }
3516
3517         ret = i40e_aq_debug_write_global_register(hw,
3518                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3519                                            reg_w, NULL);
3520         if (ret != I40E_SUCCESS) {
3521                 PMD_DRV_LOG(ERR,
3522                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3523                             reg_id);
3524                 return -EIO;
3525         }
3526         PMD_DRV_LOG(DEBUG,
3527                     "Global register 0x%08x is changed with value 0x%08x",
3528                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3529
3530         return 0;
3531 }
3532
3533 static int
3534 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3535                    enum rte_vlan_type vlan_type,
3536                    uint16_t tpid)
3537 {
3538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3540         int qinq = dev->data->dev_conf.rxmode.offloads &
3541                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3542         int ret = 0;
3543
3544         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3545              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3546             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3547                 PMD_DRV_LOG(ERR,
3548                             "Unsupported vlan type.");
3549                 return -EINVAL;
3550         }
3551
3552         if (pf->support_multi_driver) {
3553                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3554                 return -ENOTSUP;
3555         }
3556
3557         /* 802.1ad frames ability is added in NVM API 1.7*/
3558         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3559                 if (qinq) {
3560                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3561                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3562                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3563                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3564                 } else {
3565                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3566                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3567                 }
3568                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3569                 if (ret != I40E_SUCCESS) {
3570                         PMD_DRV_LOG(ERR,
3571                                     "Set switch config failed aq_err: %d",
3572                                     hw->aq.asq_last_status);
3573                         ret = -EIO;
3574                 }
3575         } else
3576                 /* If NVM API < 1.7, keep the register setting */
3577                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3578                                                       tpid, qinq);
3579
3580         return ret;
3581 }
3582
3583 static int
3584 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3585 {
3586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3587         struct i40e_vsi *vsi = pf->main_vsi;
3588         struct rte_eth_rxmode *rxmode;
3589
3590         rxmode = &dev->data->dev_conf.rxmode;
3591         if (mask & ETH_VLAN_FILTER_MASK) {
3592                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3593                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3594                 else
3595                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3596         }
3597
3598         if (mask & ETH_VLAN_STRIP_MASK) {
3599                 /* Enable or disable VLAN stripping */
3600                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3601                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3602                 else
3603                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3604         }
3605
3606         if (mask & ETH_VLAN_EXTEND_MASK) {
3607                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3608                         i40e_vsi_config_double_vlan(vsi, TRUE);
3609                         /* Set global registers with default ethertype. */
3610                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3611                                            ETHER_TYPE_VLAN);
3612                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3613                                            ETHER_TYPE_VLAN);
3614                 }
3615                 else
3616                         i40e_vsi_config_double_vlan(vsi, FALSE);
3617         }
3618
3619         return 0;
3620 }
3621
3622 static void
3623 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3624                           __rte_unused uint16_t queue,
3625                           __rte_unused int on)
3626 {
3627         PMD_INIT_FUNC_TRACE();
3628 }
3629
3630 static int
3631 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3632 {
3633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3634         struct i40e_vsi *vsi = pf->main_vsi;
3635         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3636         struct i40e_vsi_vlan_pvid_info info;
3637
3638         memset(&info, 0, sizeof(info));
3639         info.on = on;
3640         if (info.on)
3641                 info.config.pvid = pvid;
3642         else {
3643                 info.config.reject.tagged =
3644                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3645                 info.config.reject.untagged =
3646                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3647         }
3648
3649         return i40e_vsi_vlan_pvid_set(vsi, &info);
3650 }
3651
3652 static int
3653 i40e_dev_led_on(struct rte_eth_dev *dev)
3654 {
3655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656         uint32_t mode = i40e_led_get(hw);
3657
3658         if (mode == 0)
3659                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3660
3661         return 0;
3662 }
3663
3664 static int
3665 i40e_dev_led_off(struct rte_eth_dev *dev)
3666 {
3667         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668         uint32_t mode = i40e_led_get(hw);
3669
3670         if (mode != 0)
3671                 i40e_led_set(hw, 0, false);
3672
3673         return 0;
3674 }
3675
3676 static int
3677 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3678 {
3679         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3680         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3681
3682         fc_conf->pause_time = pf->fc_conf.pause_time;
3683
3684         /* read out from register, in case they are modified by other port */
3685         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3686                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3687         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3688                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3689
3690         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3691         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3692
3693          /* Return current mode according to actual setting*/
3694         switch (hw->fc.current_mode) {
3695         case I40E_FC_FULL:
3696                 fc_conf->mode = RTE_FC_FULL;
3697                 break;
3698         case I40E_FC_TX_PAUSE:
3699                 fc_conf->mode = RTE_FC_TX_PAUSE;
3700                 break;
3701         case I40E_FC_RX_PAUSE:
3702                 fc_conf->mode = RTE_FC_RX_PAUSE;
3703                 break;
3704         case I40E_FC_NONE:
3705         default:
3706                 fc_conf->mode = RTE_FC_NONE;
3707         };
3708
3709         return 0;
3710 }
3711
3712 static int
3713 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3714 {
3715         uint32_t mflcn_reg, fctrl_reg, reg;
3716         uint32_t max_high_water;
3717         uint8_t i, aq_failure;
3718         int err;
3719         struct i40e_hw *hw;
3720         struct i40e_pf *pf;
3721         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3722                 [RTE_FC_NONE] = I40E_FC_NONE,
3723                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3724                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3725                 [RTE_FC_FULL] = I40E_FC_FULL
3726         };
3727
3728         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3729
3730         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3731         if ((fc_conf->high_water > max_high_water) ||
3732                         (fc_conf->high_water < fc_conf->low_water)) {
3733                 PMD_INIT_LOG(ERR,
3734                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3735                         max_high_water);
3736                 return -EINVAL;
3737         }
3738
3739         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3740         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3741         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3742
3743         pf->fc_conf.pause_time = fc_conf->pause_time;
3744         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3745         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3746
3747         PMD_INIT_FUNC_TRACE();
3748
3749         /* All the link flow control related enable/disable register
3750          * configuration is handle by the F/W
3751          */
3752         err = i40e_set_fc(hw, &aq_failure, true);
3753         if (err < 0)
3754                 return -ENOSYS;
3755
3756         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3757                 /* Configure flow control refresh threshold,
3758                  * the value for stat_tx_pause_refresh_timer[8]
3759                  * is used for global pause operation.
3760                  */
3761
3762                 I40E_WRITE_REG(hw,
3763                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3764                                pf->fc_conf.pause_time);
3765
3766                 /* configure the timer value included in transmitted pause
3767                  * frame,
3768                  * the value for stat_tx_pause_quanta[8] is used for global
3769                  * pause operation
3770                  */
3771                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3772                                pf->fc_conf.pause_time);
3773
3774                 fctrl_reg = I40E_READ_REG(hw,
3775                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3776
3777                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3778                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3779                 else
3780                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3781
3782                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3783                                fctrl_reg);
3784         } else {
3785                 /* Configure pause time (2 TCs per register) */
3786                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3787                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3788                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3789
3790                 /* Configure flow control refresh threshold value */
3791                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3792                                pf->fc_conf.pause_time / 2);
3793
3794                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3795
3796                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3797                  *depending on configuration
3798                  */
3799                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3800                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3801                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3802                 } else {
3803                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3804                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3805                 }
3806
3807                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3808         }
3809
3810         if (!pf->support_multi_driver) {
3811                 /* config water marker both based on the packets and bytes */
3812                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3813                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3814                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3815                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3816                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3817                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3818                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3819                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3820                                   << I40E_KILOSHIFT);
3821                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3822                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3823                                    << I40E_KILOSHIFT);
3824         } else {
3825                 PMD_DRV_LOG(ERR,
3826                             "Water marker configuration is not supported.");
3827         }
3828
3829         I40E_WRITE_FLUSH(hw);
3830
3831         return 0;
3832 }
3833
3834 static int
3835 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3836                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3837 {
3838         PMD_INIT_FUNC_TRACE();
3839
3840         return -ENOSYS;
3841 }
3842
3843 /* Add a MAC address, and update filters */
3844 static int
3845 i40e_macaddr_add(struct rte_eth_dev *dev,
3846                  struct ether_addr *mac_addr,
3847                  __rte_unused uint32_t index,
3848                  uint32_t pool)
3849 {
3850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851         struct i40e_mac_filter_info mac_filter;
3852         struct i40e_vsi *vsi;
3853         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3854         int ret;
3855
3856         /* If VMDQ not enabled or configured, return */
3857         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3858                           !pf->nb_cfg_vmdq_vsi)) {
3859                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3860                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3861                         pool);
3862                 return -ENOTSUP;
3863         }
3864
3865         if (pool > pf->nb_cfg_vmdq_vsi) {
3866                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3867                                 pool, pf->nb_cfg_vmdq_vsi);
3868                 return -EINVAL;
3869         }
3870
3871         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3872         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3873                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3874         else
3875                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3876
3877         if (pool == 0)
3878                 vsi = pf->main_vsi;
3879         else
3880                 vsi = pf->vmdq[pool - 1].vsi;
3881
3882         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3883         if (ret != I40E_SUCCESS) {
3884                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3885                 return -ENODEV;
3886         }
3887         return 0;
3888 }
3889
3890 /* Remove a MAC address, and update filters */
3891 static void
3892 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3893 {
3894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3895         struct i40e_vsi *vsi;
3896         struct rte_eth_dev_data *data = dev->data;
3897         struct ether_addr *macaddr;
3898         int ret;
3899         uint32_t i;
3900         uint64_t pool_sel;
3901
3902         macaddr = &(data->mac_addrs[index]);
3903
3904         pool_sel = dev->data->mac_pool_sel[index];
3905
3906         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3907                 if (pool_sel & (1ULL << i)) {
3908                         if (i == 0)
3909                                 vsi = pf->main_vsi;
3910                         else {
3911                                 /* No VMDQ pool enabled or configured */
3912                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3913                                         (i > pf->nb_cfg_vmdq_vsi)) {
3914                                         PMD_DRV_LOG(ERR,
3915                                                 "No VMDQ pool enabled/configured");
3916                                         return;
3917                                 }
3918                                 vsi = pf->vmdq[i - 1].vsi;
3919                         }
3920                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3921
3922                         if (ret) {
3923                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3924                                 return;
3925                         }
3926                 }
3927         }
3928 }
3929
3930 /* Set perfect match or hash match of MAC and VLAN for a VF */
3931 static int
3932 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3933                  struct rte_eth_mac_filter *filter,
3934                  bool add)
3935 {
3936         struct i40e_hw *hw;
3937         struct i40e_mac_filter_info mac_filter;
3938         struct ether_addr old_mac;
3939         struct ether_addr *new_mac;
3940         struct i40e_pf_vf *vf = NULL;
3941         uint16_t vf_id;
3942         int ret;
3943
3944         if (pf == NULL) {
3945                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3946                 return -EINVAL;
3947         }
3948         hw = I40E_PF_TO_HW(pf);
3949
3950         if (filter == NULL) {
3951                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3952                 return -EINVAL;
3953         }
3954
3955         new_mac = &filter->mac_addr;
3956
3957         if (is_zero_ether_addr(new_mac)) {
3958                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3959                 return -EINVAL;
3960         }
3961
3962         vf_id = filter->dst_id;
3963
3964         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3965                 PMD_DRV_LOG(ERR, "Invalid argument.");
3966                 return -EINVAL;
3967         }
3968         vf = &pf->vfs[vf_id];
3969
3970         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3971                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3972                 return -EINVAL;
3973         }
3974
3975         if (add) {
3976                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3977                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3978                                 ETHER_ADDR_LEN);
3979                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3980                                  ETHER_ADDR_LEN);
3981
3982                 mac_filter.filter_type = filter->filter_type;
3983                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3984                 if (ret != I40E_SUCCESS) {
3985                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3986                         return -1;
3987                 }
3988                 ether_addr_copy(new_mac, &pf->dev_addr);
3989         } else {
3990                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3991                                 ETHER_ADDR_LEN);
3992                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3993                 if (ret != I40E_SUCCESS) {
3994                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3995                         return -1;
3996                 }
3997
3998                 /* Clear device address as it has been removed */
3999                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4000                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4001         }
4002
4003         return 0;
4004 }
4005
4006 /* MAC filter handle */
4007 static int
4008 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4009                 void *arg)
4010 {
4011         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4012         struct rte_eth_mac_filter *filter;
4013         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4014         int ret = I40E_NOT_SUPPORTED;
4015
4016         filter = (struct rte_eth_mac_filter *)(arg);
4017
4018         switch (filter_op) {
4019         case RTE_ETH_FILTER_NOP:
4020                 ret = I40E_SUCCESS;
4021                 break;
4022         case RTE_ETH_FILTER_ADD:
4023                 i40e_pf_disable_irq0(hw);
4024                 if (filter->is_vf)
4025                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4026                 i40e_pf_enable_irq0(hw);
4027                 break;
4028         case RTE_ETH_FILTER_DELETE:
4029                 i40e_pf_disable_irq0(hw);
4030                 if (filter->is_vf)
4031                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4032                 i40e_pf_enable_irq0(hw);
4033                 break;
4034         default:
4035                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4036                 ret = I40E_ERR_PARAM;
4037                 break;
4038         }
4039
4040         return ret;
4041 }
4042
4043 static int
4044 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4045 {
4046         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4047         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4048         uint32_t reg;
4049         int ret;
4050
4051         if (!lut)
4052                 return -EINVAL;
4053
4054         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4055                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4056                                           lut, lut_size);
4057                 if (ret) {
4058                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4059                         return ret;
4060                 }
4061         } else {
4062                 uint32_t *lut_dw = (uint32_t *)lut;
4063                 uint16_t i, lut_size_dw = lut_size / 4;
4064
4065                 if (vsi->type == I40E_VSI_SRIOV) {
4066                         for (i = 0; i <= lut_size_dw; i++) {
4067                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4068                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4069                         }
4070                 } else {
4071                         for (i = 0; i < lut_size_dw; i++)
4072                                 lut_dw[i] = I40E_READ_REG(hw,
4073                                                           I40E_PFQF_HLUT(i));
4074                 }
4075         }
4076
4077         return 0;
4078 }
4079
4080 int
4081 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4082 {
4083         struct i40e_pf *pf;
4084         struct i40e_hw *hw;
4085         int ret;
4086
4087         if (!vsi || !lut)
4088                 return -EINVAL;
4089
4090         pf = I40E_VSI_TO_PF(vsi);
4091         hw = I40E_VSI_TO_HW(vsi);
4092
4093         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4094                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4095                                           lut, lut_size);
4096                 if (ret) {
4097                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4098                         return ret;
4099                 }
4100         } else {
4101                 uint32_t *lut_dw = (uint32_t *)lut;
4102                 uint16_t i, lut_size_dw = lut_size / 4;
4103
4104                 if (vsi->type == I40E_VSI_SRIOV) {
4105                         for (i = 0; i < lut_size_dw; i++)
4106                                 I40E_WRITE_REG(
4107                                         hw,
4108                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4109                                         lut_dw[i]);
4110                 } else {
4111                         for (i = 0; i < lut_size_dw; i++)
4112                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4113                                                lut_dw[i]);
4114                 }
4115                 I40E_WRITE_FLUSH(hw);
4116         }
4117
4118         return 0;
4119 }
4120
4121 static int
4122 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4123                          struct rte_eth_rss_reta_entry64 *reta_conf,
4124                          uint16_t reta_size)
4125 {
4126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4127         uint16_t i, lut_size = pf->hash_lut_size;
4128         uint16_t idx, shift;
4129         uint8_t *lut;
4130         int ret;
4131
4132         if (reta_size != lut_size ||
4133                 reta_size > ETH_RSS_RETA_SIZE_512) {
4134                 PMD_DRV_LOG(ERR,
4135                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4136                         reta_size, lut_size);
4137                 return -EINVAL;
4138         }
4139
4140         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4141         if (!lut) {
4142                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4143                 return -ENOMEM;
4144         }
4145         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4146         if (ret)
4147                 goto out;
4148         for (i = 0; i < reta_size; i++) {
4149                 idx = i / RTE_RETA_GROUP_SIZE;
4150                 shift = i % RTE_RETA_GROUP_SIZE;
4151                 if (reta_conf[idx].mask & (1ULL << shift))
4152                         lut[i] = reta_conf[idx].reta[shift];
4153         }
4154         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4155
4156 out:
4157         rte_free(lut);
4158
4159         return ret;
4160 }
4161
4162 static int
4163 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4164                         struct rte_eth_rss_reta_entry64 *reta_conf,
4165                         uint16_t reta_size)
4166 {
4167         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4168         uint16_t i, lut_size = pf->hash_lut_size;
4169         uint16_t idx, shift;
4170         uint8_t *lut;
4171         int ret;
4172
4173         if (reta_size != lut_size ||
4174                 reta_size > ETH_RSS_RETA_SIZE_512) {
4175                 PMD_DRV_LOG(ERR,
4176                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4177                         reta_size, lut_size);
4178                 return -EINVAL;
4179         }
4180
4181         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4182         if (!lut) {
4183                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4184                 return -ENOMEM;
4185         }
4186
4187         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4188         if (ret)
4189                 goto out;
4190         for (i = 0; i < reta_size; i++) {
4191                 idx = i / RTE_RETA_GROUP_SIZE;
4192                 shift = i % RTE_RETA_GROUP_SIZE;
4193                 if (reta_conf[idx].mask & (1ULL << shift))
4194                         reta_conf[idx].reta[shift] = lut[i];
4195         }
4196
4197 out:
4198         rte_free(lut);
4199
4200         return ret;
4201 }
4202
4203 /**
4204  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4205  * @hw:   pointer to the HW structure
4206  * @mem:  pointer to mem struct to fill out
4207  * @size: size of memory requested
4208  * @alignment: what to align the allocation to
4209  **/
4210 enum i40e_status_code
4211 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4212                         struct i40e_dma_mem *mem,
4213                         u64 size,
4214                         u32 alignment)
4215 {
4216         const struct rte_memzone *mz = NULL;
4217         char z_name[RTE_MEMZONE_NAMESIZE];
4218
4219         if (!mem)
4220                 return I40E_ERR_PARAM;
4221
4222         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4223         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4224                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4225         if (!mz)
4226                 return I40E_ERR_NO_MEMORY;
4227
4228         mem->size = size;
4229         mem->va = mz->addr;
4230         mem->pa = mz->iova;
4231         mem->zone = (const void *)mz;
4232         PMD_DRV_LOG(DEBUG,
4233                 "memzone %s allocated with physical address: %"PRIu64,
4234                 mz->name, mem->pa);
4235
4236         return I40E_SUCCESS;
4237 }
4238
4239 /**
4240  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4241  * @hw:   pointer to the HW structure
4242  * @mem:  ptr to mem struct to free
4243  **/
4244 enum i40e_status_code
4245 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4246                     struct i40e_dma_mem *mem)
4247 {
4248         if (!mem)
4249                 return I40E_ERR_PARAM;
4250
4251         PMD_DRV_LOG(DEBUG,
4252                 "memzone %s to be freed with physical address: %"PRIu64,
4253                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4254         rte_memzone_free((const struct rte_memzone *)mem->zone);
4255         mem->zone = NULL;
4256         mem->va = NULL;
4257         mem->pa = (u64)0;
4258
4259         return I40E_SUCCESS;
4260 }
4261
4262 /**
4263  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4264  * @hw:   pointer to the HW structure
4265  * @mem:  pointer to mem struct to fill out
4266  * @size: size of memory requested
4267  **/
4268 enum i40e_status_code
4269 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4270                          struct i40e_virt_mem *mem,
4271                          u32 size)
4272 {
4273         if (!mem)
4274                 return I40E_ERR_PARAM;
4275
4276         mem->size = size;
4277         mem->va = rte_zmalloc("i40e", size, 0);
4278
4279         if (mem->va)
4280                 return I40E_SUCCESS;
4281         else
4282                 return I40E_ERR_NO_MEMORY;
4283 }
4284
4285 /**
4286  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4287  * @hw:   pointer to the HW structure
4288  * @mem:  pointer to mem struct to free
4289  **/
4290 enum i40e_status_code
4291 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4292                      struct i40e_virt_mem *mem)
4293 {
4294         if (!mem)
4295                 return I40E_ERR_PARAM;
4296
4297         rte_free(mem->va);
4298         mem->va = NULL;
4299
4300         return I40E_SUCCESS;
4301 }
4302
4303 void
4304 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4305 {
4306         rte_spinlock_init(&sp->spinlock);
4307 }
4308
4309 void
4310 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4311 {
4312         rte_spinlock_lock(&sp->spinlock);
4313 }
4314
4315 void
4316 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4317 {
4318         rte_spinlock_unlock(&sp->spinlock);
4319 }
4320
4321 void
4322 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4323 {
4324         return;
4325 }
4326
4327 /**
4328  * Get the hardware capabilities, which will be parsed
4329  * and saved into struct i40e_hw.
4330  */
4331 static int
4332 i40e_get_cap(struct i40e_hw *hw)
4333 {
4334         struct i40e_aqc_list_capabilities_element_resp *buf;
4335         uint16_t len, size = 0;
4336         int ret;
4337
4338         /* Calculate a huge enough buff for saving response data temporarily */
4339         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4340                                                 I40E_MAX_CAP_ELE_NUM;
4341         buf = rte_zmalloc("i40e", len, 0);
4342         if (!buf) {
4343                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4344                 return I40E_ERR_NO_MEMORY;
4345         }
4346
4347         /* Get, parse the capabilities and save it to hw */
4348         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4349                         i40e_aqc_opc_list_func_capabilities, NULL);
4350         if (ret != I40E_SUCCESS)
4351                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4352
4353         /* Free the temporary buffer after being used */
4354         rte_free(buf);
4355
4356         return ret;
4357 }
4358
4359 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4360 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4361
4362 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4363                 const char *value,
4364                 void *opaque)
4365 {
4366         struct i40e_pf *pf;
4367         unsigned long num;
4368         char *end;
4369
4370         pf = (struct i40e_pf *)opaque;
4371         RTE_SET_USED(key);
4372
4373         errno = 0;
4374         num = strtoul(value, &end, 0);
4375         if (errno != 0 || end == value || *end != 0) {
4376                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4377                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4378                 return -(EINVAL);
4379         }
4380
4381         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4382                 pf->vf_nb_qp_max = (uint16_t)num;
4383         else
4384                 /* here return 0 to make next valid same argument work */
4385                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4386                             "power of 2 and equal or less than 16 !, Now it is "
4387                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4388
4389         return 0;
4390 }
4391
4392 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4393 {
4394         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4396         struct rte_kvargs *kvlist;
4397
4398         /* set default queue number per VF as 4 */
4399         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4400
4401         if (dev->device->devargs == NULL)
4402                 return 0;
4403
4404         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4405         if (kvlist == NULL)
4406                 return -(EINVAL);
4407
4408         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4409                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4410                             "the first invalid or last valid one is used !",
4411                             QUEUE_NUM_PER_VF_ARG);
4412
4413         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4414                            i40e_pf_parse_vf_queue_number_handler, pf);
4415
4416         rte_kvargs_free(kvlist);
4417
4418         return 0;
4419 }
4420
4421 static int
4422 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4423 {
4424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4425         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4426         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4427         uint16_t qp_count = 0, vsi_count = 0;
4428
4429         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4430                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4431                 return -EINVAL;
4432         }
4433
4434         i40e_pf_config_vf_rxq_number(dev);
4435
4436         /* Add the parameter init for LFC */
4437         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4438         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4439         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4440
4441         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4442         pf->max_num_vsi = hw->func_caps.num_vsis;
4443         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4444         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4445
4446         /* FDir queue/VSI allocation */
4447         pf->fdir_qp_offset = 0;
4448         if (hw->func_caps.fd) {
4449                 pf->flags |= I40E_FLAG_FDIR;
4450                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4451         } else {
4452                 pf->fdir_nb_qps = 0;
4453         }
4454         qp_count += pf->fdir_nb_qps;
4455         vsi_count += 1;
4456
4457         /* LAN queue/VSI allocation */
4458         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4459         if (!hw->func_caps.rss) {
4460                 pf->lan_nb_qps = 1;
4461         } else {
4462                 pf->flags |= I40E_FLAG_RSS;
4463                 if (hw->mac.type == I40E_MAC_X722)
4464                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4465                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4466         }
4467         qp_count += pf->lan_nb_qps;
4468         vsi_count += 1;
4469
4470         /* VF queue/VSI allocation */
4471         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4472         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4473                 pf->flags |= I40E_FLAG_SRIOV;
4474                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4475                 pf->vf_num = pci_dev->max_vfs;
4476                 PMD_DRV_LOG(DEBUG,
4477                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4478                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4479         } else {
4480                 pf->vf_nb_qps = 0;
4481                 pf->vf_num = 0;
4482         }
4483         qp_count += pf->vf_nb_qps * pf->vf_num;
4484         vsi_count += pf->vf_num;
4485
4486         /* VMDq queue/VSI allocation */
4487         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4488         pf->vmdq_nb_qps = 0;
4489         pf->max_nb_vmdq_vsi = 0;
4490         if (hw->func_caps.vmdq) {
4491                 if (qp_count < hw->func_caps.num_tx_qp &&
4492                         vsi_count < hw->func_caps.num_vsis) {
4493                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4494                                 qp_count) / pf->vmdq_nb_qp_max;
4495
4496                         /* Limit the maximum number of VMDq vsi to the maximum
4497                          * ethdev can support
4498                          */
4499                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4500                                 hw->func_caps.num_vsis - vsi_count);
4501                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4502                                 ETH_64_POOLS);
4503                         if (pf->max_nb_vmdq_vsi) {
4504                                 pf->flags |= I40E_FLAG_VMDQ;
4505                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4506                                 PMD_DRV_LOG(DEBUG,
4507                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4508                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4509                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4510                         } else {
4511                                 PMD_DRV_LOG(INFO,
4512                                         "No enough queues left for VMDq");
4513                         }
4514                 } else {
4515                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4516                 }
4517         }
4518         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4519         vsi_count += pf->max_nb_vmdq_vsi;
4520
4521         if (hw->func_caps.dcb)
4522                 pf->flags |= I40E_FLAG_DCB;
4523
4524         if (qp_count > hw->func_caps.num_tx_qp) {
4525                 PMD_DRV_LOG(ERR,
4526                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4527                         qp_count, hw->func_caps.num_tx_qp);
4528                 return -EINVAL;
4529         }
4530         if (vsi_count > hw->func_caps.num_vsis) {
4531                 PMD_DRV_LOG(ERR,
4532                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4533                         vsi_count, hw->func_caps.num_vsis);
4534                 return -EINVAL;
4535         }
4536
4537         return 0;
4538 }
4539
4540 static int
4541 i40e_pf_get_switch_config(struct i40e_pf *pf)
4542 {
4543         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4544         struct i40e_aqc_get_switch_config_resp *switch_config;
4545         struct i40e_aqc_switch_config_element_resp *element;
4546         uint16_t start_seid = 0, num_reported;
4547         int ret;
4548
4549         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4550                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4551         if (!switch_config) {
4552                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4553                 return -ENOMEM;
4554         }
4555
4556         /* Get the switch configurations */
4557         ret = i40e_aq_get_switch_config(hw, switch_config,
4558                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4559         if (ret != I40E_SUCCESS) {
4560                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4561                 goto fail;
4562         }
4563         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4564         if (num_reported != 1) { /* The number should be 1 */
4565                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4566                 goto fail;
4567         }
4568
4569         /* Parse the switch configuration elements */
4570         element = &(switch_config->element[0]);
4571         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4572                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4573                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4574         } else
4575                 PMD_DRV_LOG(INFO, "Unknown element type");
4576
4577 fail:
4578         rte_free(switch_config);
4579
4580         return ret;
4581 }
4582
4583 static int
4584 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4585                         uint32_t num)
4586 {
4587         struct pool_entry *entry;
4588
4589         if (pool == NULL || num == 0)
4590                 return -EINVAL;
4591
4592         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4593         if (entry == NULL) {
4594                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4595                 return -ENOMEM;
4596         }
4597
4598         /* queue heap initialize */
4599         pool->num_free = num;
4600         pool->num_alloc = 0;
4601         pool->base = base;
4602         LIST_INIT(&pool->alloc_list);
4603         LIST_INIT(&pool->free_list);
4604
4605         /* Initialize element  */
4606         entry->base = 0;
4607         entry->len = num;
4608
4609         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4610         return 0;
4611 }
4612
4613 static void
4614 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4615 {
4616         struct pool_entry *entry, *next_entry;
4617
4618         if (pool == NULL)
4619                 return;
4620
4621         for (entry = LIST_FIRST(&pool->alloc_list);
4622                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4623                         entry = next_entry) {
4624                 LIST_REMOVE(entry, next);
4625                 rte_free(entry);
4626         }
4627
4628         for (entry = LIST_FIRST(&pool->free_list);
4629                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4630                         entry = next_entry) {
4631                 LIST_REMOVE(entry, next);
4632                 rte_free(entry);
4633         }
4634
4635         pool->num_free = 0;
4636         pool->num_alloc = 0;
4637         pool->base = 0;
4638         LIST_INIT(&pool->alloc_list);
4639         LIST_INIT(&pool->free_list);
4640 }
4641
4642 static int
4643 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4644                        uint32_t base)
4645 {
4646         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4647         uint32_t pool_offset;
4648         int insert;
4649
4650         if (pool == NULL) {
4651                 PMD_DRV_LOG(ERR, "Invalid parameter");
4652                 return -EINVAL;
4653         }
4654
4655         pool_offset = base - pool->base;
4656         /* Lookup in alloc list */
4657         LIST_FOREACH(entry, &pool->alloc_list, next) {
4658                 if (entry->base == pool_offset) {
4659                         valid_entry = entry;
4660                         LIST_REMOVE(entry, next);
4661                         break;
4662                 }
4663         }
4664
4665         /* Not find, return */
4666         if (valid_entry == NULL) {
4667                 PMD_DRV_LOG(ERR, "Failed to find entry");
4668                 return -EINVAL;
4669         }
4670
4671         /**
4672          * Found it, move it to free list  and try to merge.
4673          * In order to make merge easier, always sort it by qbase.
4674          * Find adjacent prev and last entries.
4675          */
4676         prev = next = NULL;
4677         LIST_FOREACH(entry, &pool->free_list, next) {
4678                 if (entry->base > valid_entry->base) {
4679                         next = entry;
4680                         break;
4681                 }
4682                 prev = entry;
4683         }
4684
4685         insert = 0;
4686         /* Try to merge with next one*/
4687         if (next != NULL) {
4688                 /* Merge with next one */
4689                 if (valid_entry->base + valid_entry->len == next->base) {
4690                         next->base = valid_entry->base;
4691                         next->len += valid_entry->len;
4692                         rte_free(valid_entry);
4693                         valid_entry = next;
4694                         insert = 1;
4695                 }
4696         }
4697
4698         if (prev != NULL) {
4699                 /* Merge with previous one */
4700                 if (prev->base + prev->len == valid_entry->base) {
4701                         prev->len += valid_entry->len;
4702                         /* If it merge with next one, remove next node */
4703                         if (insert == 1) {
4704                                 LIST_REMOVE(valid_entry, next);
4705                                 rte_free(valid_entry);
4706                         } else {
4707                                 rte_free(valid_entry);
4708                                 insert = 1;
4709                         }
4710                 }
4711         }
4712
4713         /* Not find any entry to merge, insert */
4714         if (insert == 0) {
4715                 if (prev != NULL)
4716                         LIST_INSERT_AFTER(prev, valid_entry, next);
4717                 else if (next != NULL)
4718                         LIST_INSERT_BEFORE(next, valid_entry, next);
4719                 else /* It's empty list, insert to head */
4720                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4721         }
4722
4723         pool->num_free += valid_entry->len;
4724         pool->num_alloc -= valid_entry->len;
4725
4726         return 0;
4727 }
4728
4729 static int
4730 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4731                        uint16_t num)
4732 {
4733         struct pool_entry *entry, *valid_entry;
4734
4735         if (pool == NULL || num == 0) {
4736                 PMD_DRV_LOG(ERR, "Invalid parameter");
4737                 return -EINVAL;
4738         }
4739
4740         if (pool->num_free < num) {
4741                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4742                             num, pool->num_free);
4743                 return -ENOMEM;
4744         }
4745
4746         valid_entry = NULL;
4747         /* Lookup  in free list and find most fit one */
4748         LIST_FOREACH(entry, &pool->free_list, next) {
4749                 if (entry->len >= num) {
4750                         /* Find best one */
4751                         if (entry->len == num) {
4752                                 valid_entry = entry;
4753                                 break;
4754                         }
4755                         if (valid_entry == NULL || valid_entry->len > entry->len)
4756                                 valid_entry = entry;
4757                 }
4758         }
4759
4760         /* Not find one to satisfy the request, return */
4761         if (valid_entry == NULL) {
4762                 PMD_DRV_LOG(ERR, "No valid entry found");
4763                 return -ENOMEM;
4764         }
4765         /**
4766          * The entry have equal queue number as requested,
4767          * remove it from alloc_list.
4768          */
4769         if (valid_entry->len == num) {
4770                 LIST_REMOVE(valid_entry, next);
4771         } else {
4772                 /**
4773                  * The entry have more numbers than requested,
4774                  * create a new entry for alloc_list and minus its
4775                  * queue base and number in free_list.
4776                  */
4777                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4778                 if (entry == NULL) {
4779                         PMD_DRV_LOG(ERR,
4780                                 "Failed to allocate memory for resource pool");
4781                         return -ENOMEM;
4782                 }
4783                 entry->base = valid_entry->base;
4784                 entry->len = num;
4785                 valid_entry->base += num;
4786                 valid_entry->len -= num;
4787                 valid_entry = entry;
4788         }
4789
4790         /* Insert it into alloc list, not sorted */
4791         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4792
4793         pool->num_free -= valid_entry->len;
4794         pool->num_alloc += valid_entry->len;
4795
4796         return valid_entry->base + pool->base;
4797 }
4798
4799 /**
4800  * bitmap_is_subset - Check whether src2 is subset of src1
4801  **/
4802 static inline int
4803 bitmap_is_subset(uint8_t src1, uint8_t src2)
4804 {
4805         return !((src1 ^ src2) & src2);
4806 }
4807
4808 static enum i40e_status_code
4809 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4810 {
4811         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4812
4813         /* If DCB is not supported, only default TC is supported */
4814         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4815                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4816                 return I40E_NOT_SUPPORTED;
4817         }
4818
4819         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4820                 PMD_DRV_LOG(ERR,
4821                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4822                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4823                 return I40E_NOT_SUPPORTED;
4824         }
4825         return I40E_SUCCESS;
4826 }
4827
4828 int
4829 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4830                                 struct i40e_vsi_vlan_pvid_info *info)
4831 {
4832         struct i40e_hw *hw;
4833         struct i40e_vsi_context ctxt;
4834         uint8_t vlan_flags = 0;
4835         int ret;
4836
4837         if (vsi == NULL || info == NULL) {
4838                 PMD_DRV_LOG(ERR, "invalid parameters");
4839                 return I40E_ERR_PARAM;
4840         }
4841
4842         if (info->on) {
4843                 vsi->info.pvid = info->config.pvid;
4844                 /**
4845                  * If insert pvid is enabled, only tagged pkts are
4846                  * allowed to be sent out.
4847                  */
4848                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4849                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4850         } else {
4851                 vsi->info.pvid = 0;
4852                 if (info->config.reject.tagged == 0)
4853                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4854
4855                 if (info->config.reject.untagged == 0)
4856                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4857         }
4858         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4859                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4860         vsi->info.port_vlan_flags |= vlan_flags;
4861         vsi->info.valid_sections =
4862                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4863         memset(&ctxt, 0, sizeof(ctxt));
4864         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4865         ctxt.seid = vsi->seid;
4866
4867         hw = I40E_VSI_TO_HW(vsi);
4868         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4869         if (ret != I40E_SUCCESS)
4870                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4871
4872         return ret;
4873 }
4874
4875 static int
4876 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4877 {
4878         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4879         int i, ret;
4880         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4881
4882         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4883         if (ret != I40E_SUCCESS)
4884                 return ret;
4885
4886         if (!vsi->seid) {
4887                 PMD_DRV_LOG(ERR, "seid not valid");
4888                 return -EINVAL;
4889         }
4890
4891         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4892         tc_bw_data.tc_valid_bits = enabled_tcmap;
4893         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4894                 tc_bw_data.tc_bw_credits[i] =
4895                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4896
4897         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4898         if (ret != I40E_SUCCESS) {
4899                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4900                 return ret;
4901         }
4902
4903         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4904                                         sizeof(vsi->info.qs_handle));
4905         return I40E_SUCCESS;
4906 }
4907
4908 static enum i40e_status_code
4909 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4910                                  struct i40e_aqc_vsi_properties_data *info,
4911                                  uint8_t enabled_tcmap)
4912 {
4913         enum i40e_status_code ret;
4914         int i, total_tc = 0;
4915         uint16_t qpnum_per_tc, bsf, qp_idx;
4916
4917         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4918         if (ret != I40E_SUCCESS)
4919                 return ret;
4920
4921         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4922                 if (enabled_tcmap & (1 << i))
4923                         total_tc++;
4924         if (total_tc == 0)
4925                 total_tc = 1;
4926         vsi->enabled_tc = enabled_tcmap;
4927
4928         /* Number of queues per enabled TC */
4929         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4930         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4931         bsf = rte_bsf32(qpnum_per_tc);
4932
4933         /* Adjust the queue number to actual queues that can be applied */
4934         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4935                 vsi->nb_qps = qpnum_per_tc * total_tc;
4936
4937         /**
4938          * Configure TC and queue mapping parameters, for enabled TC,
4939          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4940          * default queue will serve it.
4941          */
4942         qp_idx = 0;
4943         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4944                 if (vsi->enabled_tc & (1 << i)) {
4945                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4946                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4947                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4948                         qp_idx += qpnum_per_tc;
4949                 } else
4950                         info->tc_mapping[i] = 0;
4951         }
4952
4953         /* Associate queue number with VSI */
4954         if (vsi->type == I40E_VSI_SRIOV) {
4955                 info->mapping_flags |=
4956                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4957                 for (i = 0; i < vsi->nb_qps; i++)
4958                         info->queue_mapping[i] =
4959                                 rte_cpu_to_le_16(vsi->base_queue + i);
4960         } else {
4961                 info->mapping_flags |=
4962                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4963                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4964         }
4965         info->valid_sections |=
4966                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4967
4968         return I40E_SUCCESS;
4969 }
4970
4971 static int
4972 i40e_veb_release(struct i40e_veb *veb)
4973 {
4974         struct i40e_vsi *vsi;
4975         struct i40e_hw *hw;
4976
4977         if (veb == NULL)
4978                 return -EINVAL;
4979
4980         if (!TAILQ_EMPTY(&veb->head)) {
4981                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4982                 return -EACCES;
4983         }
4984         /* associate_vsi field is NULL for floating VEB */
4985         if (veb->associate_vsi != NULL) {
4986                 vsi = veb->associate_vsi;
4987                 hw = I40E_VSI_TO_HW(vsi);
4988
4989                 vsi->uplink_seid = veb->uplink_seid;
4990                 vsi->veb = NULL;
4991         } else {
4992                 veb->associate_pf->main_vsi->floating_veb = NULL;
4993                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4994         }
4995
4996         i40e_aq_delete_element(hw, veb->seid, NULL);
4997         rte_free(veb);
4998         return I40E_SUCCESS;
4999 }
5000
5001 /* Setup a veb */
5002 static struct i40e_veb *
5003 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5004 {
5005         struct i40e_veb *veb;
5006         int ret;
5007         struct i40e_hw *hw;
5008
5009         if (pf == NULL) {
5010                 PMD_DRV_LOG(ERR,
5011                             "veb setup failed, associated PF shouldn't null");
5012                 return NULL;
5013         }
5014         hw = I40E_PF_TO_HW(pf);
5015
5016         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5017         if (!veb) {
5018                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5019                 goto fail;
5020         }
5021
5022         veb->associate_vsi = vsi;
5023         veb->associate_pf = pf;
5024         TAILQ_INIT(&veb->head);
5025         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5026
5027         /* create floating veb if vsi is NULL */
5028         if (vsi != NULL) {
5029                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5030                                       I40E_DEFAULT_TCMAP, false,
5031                                       &veb->seid, false, NULL);
5032         } else {
5033                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5034                                       true, &veb->seid, false, NULL);
5035         }
5036
5037         if (ret != I40E_SUCCESS) {
5038                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5039                             hw->aq.asq_last_status);
5040                 goto fail;
5041         }
5042         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5043
5044         /* get statistics index */
5045         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5046                                 &veb->stats_idx, NULL, NULL, NULL);
5047         if (ret != I40E_SUCCESS) {
5048                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5049                             hw->aq.asq_last_status);
5050                 goto fail;
5051         }
5052         /* Get VEB bandwidth, to be implemented */
5053         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5054         if (vsi)
5055                 vsi->uplink_seid = veb->seid;
5056
5057         return veb;
5058 fail:
5059         rte_free(veb);
5060         return NULL;
5061 }
5062
5063 int
5064 i40e_vsi_release(struct i40e_vsi *vsi)
5065 {
5066         struct i40e_pf *pf;
5067         struct i40e_hw *hw;
5068         struct i40e_vsi_list *vsi_list;
5069         void *temp;
5070         int ret;
5071         struct i40e_mac_filter *f;
5072         uint16_t user_param;
5073
5074         if (!vsi)
5075                 return I40E_SUCCESS;
5076
5077         if (!vsi->adapter)
5078                 return -EFAULT;
5079
5080         user_param = vsi->user_param;
5081
5082         pf = I40E_VSI_TO_PF(vsi);
5083         hw = I40E_VSI_TO_HW(vsi);
5084
5085         /* VSI has child to attach, release child first */
5086         if (vsi->veb) {
5087                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5088                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5089                                 return -1;
5090                 }
5091                 i40e_veb_release(vsi->veb);
5092         }
5093
5094         if (vsi->floating_veb) {
5095                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5096                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5097                                 return -1;
5098                 }
5099         }
5100
5101         /* Remove all macvlan filters of the VSI */
5102         i40e_vsi_remove_all_macvlan_filter(vsi);
5103         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5104                 rte_free(f);
5105
5106         if (vsi->type != I40E_VSI_MAIN &&
5107             ((vsi->type != I40E_VSI_SRIOV) ||
5108             !pf->floating_veb_list[user_param])) {
5109                 /* Remove vsi from parent's sibling list */
5110                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5111                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5112                         return I40E_ERR_PARAM;
5113                 }
5114                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5115                                 &vsi->sib_vsi_list, list);
5116
5117                 /* Remove all switch element of the VSI */
5118                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5119                 if (ret != I40E_SUCCESS)
5120                         PMD_DRV_LOG(ERR, "Failed to delete element");
5121         }
5122
5123         if ((vsi->type == I40E_VSI_SRIOV) &&
5124             pf->floating_veb_list[user_param]) {
5125                 /* Remove vsi from parent's sibling list */
5126                 if (vsi->parent_vsi == NULL ||
5127                     vsi->parent_vsi->floating_veb == NULL) {
5128                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5129                         return I40E_ERR_PARAM;
5130                 }
5131                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5132                              &vsi->sib_vsi_list, list);
5133
5134                 /* Remove all switch element of the VSI */
5135                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5136                 if (ret != I40E_SUCCESS)
5137                         PMD_DRV_LOG(ERR, "Failed to delete element");
5138         }
5139
5140         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5141
5142         if (vsi->type != I40E_VSI_SRIOV)
5143                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5144         rte_free(vsi);
5145
5146         return I40E_SUCCESS;
5147 }
5148
5149 static int
5150 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5151 {
5152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5153         struct i40e_aqc_remove_macvlan_element_data def_filter;
5154         struct i40e_mac_filter_info filter;
5155         int ret;
5156
5157         if (vsi->type != I40E_VSI_MAIN)
5158                 return I40E_ERR_CONFIG;
5159         memset(&def_filter, 0, sizeof(def_filter));
5160         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5161                                         ETH_ADDR_LEN);
5162         def_filter.vlan_tag = 0;
5163         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5164                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5165         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5166         if (ret != I40E_SUCCESS) {
5167                 struct i40e_mac_filter *f;
5168                 struct ether_addr *mac;
5169
5170                 PMD_DRV_LOG(DEBUG,
5171                             "Cannot remove the default macvlan filter");
5172                 /* It needs to add the permanent mac into mac list */
5173                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5174                 if (f == NULL) {
5175                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5176                         return I40E_ERR_NO_MEMORY;
5177                 }
5178                 mac = &f->mac_info.mac_addr;
5179                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5180                                 ETH_ADDR_LEN);
5181                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5182                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5183                 vsi->mac_num++;
5184
5185                 return ret;
5186         }
5187         rte_memcpy(&filter.mac_addr,
5188                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5189         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5190         return i40e_vsi_add_mac(vsi, &filter);
5191 }
5192
5193 /*
5194  * i40e_vsi_get_bw_config - Query VSI BW Information
5195  * @vsi: the VSI to be queried
5196  *
5197  * Returns 0 on success, negative value on failure
5198  */
5199 static enum i40e_status_code
5200 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5201 {
5202         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5203         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5204         struct i40e_hw *hw = &vsi->adapter->hw;
5205         i40e_status ret;
5206         int i;
5207         uint32_t bw_max;
5208
5209         memset(&bw_config, 0, sizeof(bw_config));
5210         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5211         if (ret != I40E_SUCCESS) {
5212                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5213                             hw->aq.asq_last_status);
5214                 return ret;
5215         }
5216
5217         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5218         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5219                                         &ets_sla_config, NULL);
5220         if (ret != I40E_SUCCESS) {
5221                 PMD_DRV_LOG(ERR,
5222                         "VSI failed to get TC bandwdith configuration %u",
5223                         hw->aq.asq_last_status);
5224                 return ret;
5225         }
5226
5227         /* store and print out BW info */
5228         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5229         vsi->bw_info.bw_max = bw_config.max_bw;
5230         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5231         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5232         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5233                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5234                      I40E_16_BIT_WIDTH);
5235         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5236                 vsi->bw_info.bw_ets_share_credits[i] =
5237                                 ets_sla_config.share_credits[i];
5238                 vsi->bw_info.bw_ets_credits[i] =
5239                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5240                 /* 4 bits per TC, 4th bit is reserved */
5241                 vsi->bw_info.bw_ets_max[i] =
5242                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5243                                   RTE_LEN2MASK(3, uint8_t));
5244                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5245                             vsi->bw_info.bw_ets_share_credits[i]);
5246                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5247                             vsi->bw_info.bw_ets_credits[i]);
5248                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5249                             vsi->bw_info.bw_ets_max[i]);
5250         }
5251
5252         return I40E_SUCCESS;
5253 }
5254
5255 /* i40e_enable_pf_lb
5256  * @pf: pointer to the pf structure
5257  *
5258  * allow loopback on pf
5259  */
5260 static inline void
5261 i40e_enable_pf_lb(struct i40e_pf *pf)
5262 {
5263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5264         struct i40e_vsi_context ctxt;
5265         int ret;
5266
5267         /* Use the FW API if FW >= v5.0 */
5268         if (hw->aq.fw_maj_ver < 5) {
5269                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5270                 return;
5271         }
5272
5273         memset(&ctxt, 0, sizeof(ctxt));
5274         ctxt.seid = pf->main_vsi_seid;
5275         ctxt.pf_num = hw->pf_id;
5276         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5277         if (ret) {
5278                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5279                             ret, hw->aq.asq_last_status);
5280                 return;
5281         }
5282         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5283         ctxt.info.valid_sections =
5284                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5285         ctxt.info.switch_id |=
5286                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5287
5288         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5289         if (ret)
5290                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5291                             hw->aq.asq_last_status);
5292 }
5293
5294 /* Setup a VSI */
5295 struct i40e_vsi *
5296 i40e_vsi_setup(struct i40e_pf *pf,
5297                enum i40e_vsi_type type,
5298                struct i40e_vsi *uplink_vsi,
5299                uint16_t user_param)
5300 {
5301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5302         struct i40e_vsi *vsi;
5303         struct i40e_mac_filter_info filter;
5304         int ret;
5305         struct i40e_vsi_context ctxt;
5306         struct ether_addr broadcast =
5307                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5308
5309         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5310             uplink_vsi == NULL) {
5311                 PMD_DRV_LOG(ERR,
5312                         "VSI setup failed, VSI link shouldn't be NULL");
5313                 return NULL;
5314         }
5315
5316         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5317                 PMD_DRV_LOG(ERR,
5318                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5319                 return NULL;
5320         }
5321
5322         /* two situations
5323          * 1.type is not MAIN and uplink vsi is not NULL
5324          * If uplink vsi didn't setup VEB, create one first under veb field
5325          * 2.type is SRIOV and the uplink is NULL
5326          * If floating VEB is NULL, create one veb under floating veb field
5327          */
5328
5329         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5330             uplink_vsi->veb == NULL) {
5331                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5332
5333                 if (uplink_vsi->veb == NULL) {
5334                         PMD_DRV_LOG(ERR, "VEB setup failed");
5335                         return NULL;
5336                 }
5337                 /* set ALLOWLOOPBACk on pf, when veb is created */
5338                 i40e_enable_pf_lb(pf);
5339         }
5340
5341         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5342             pf->main_vsi->floating_veb == NULL) {
5343                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5344
5345                 if (pf->main_vsi->floating_veb == NULL) {
5346                         PMD_DRV_LOG(ERR, "VEB setup failed");
5347                         return NULL;
5348                 }
5349         }
5350
5351         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5352         if (!vsi) {
5353                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5354                 return NULL;
5355         }
5356         TAILQ_INIT(&vsi->mac_list);
5357         vsi->type = type;
5358         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5359         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5360         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5361         vsi->user_param = user_param;
5362         vsi->vlan_anti_spoof_on = 0;
5363         vsi->vlan_filter_on = 0;
5364         /* Allocate queues */
5365         switch (vsi->type) {
5366         case I40E_VSI_MAIN  :
5367                 vsi->nb_qps = pf->lan_nb_qps;
5368                 break;
5369         case I40E_VSI_SRIOV :
5370                 vsi->nb_qps = pf->vf_nb_qps;
5371                 break;
5372         case I40E_VSI_VMDQ2:
5373                 vsi->nb_qps = pf->vmdq_nb_qps;
5374                 break;
5375         case I40E_VSI_FDIR:
5376                 vsi->nb_qps = pf->fdir_nb_qps;
5377                 break;
5378         default:
5379                 goto fail_mem;
5380         }
5381         /*
5382          * The filter status descriptor is reported in rx queue 0,
5383          * while the tx queue for fdir filter programming has no
5384          * such constraints, can be non-zero queues.
5385          * To simplify it, choose FDIR vsi use queue 0 pair.
5386          * To make sure it will use queue 0 pair, queue allocation
5387          * need be done before this function is called
5388          */
5389         if (type != I40E_VSI_FDIR) {
5390                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5391                         if (ret < 0) {
5392                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5393                                                 vsi->seid, ret);
5394                                 goto fail_mem;
5395                         }
5396                         vsi->base_queue = ret;
5397         } else
5398                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5399
5400         /* VF has MSIX interrupt in VF range, don't allocate here */
5401         if (type == I40E_VSI_MAIN) {
5402                 if (pf->support_multi_driver) {
5403                         /* If support multi-driver, need to use INT0 instead of
5404                          * allocating from msix pool. The Msix pool is init from
5405                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5406                          * to 1 without calling i40e_res_pool_alloc.
5407                          */
5408                         vsi->msix_intr = 0;
5409                         vsi->nb_msix = 1;
5410                 } else {
5411                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5412                                                   RTE_MIN(vsi->nb_qps,
5413                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5414                         if (ret < 0) {
5415                                 PMD_DRV_LOG(ERR,
5416                                             "VSI MAIN %d get heap failed %d",
5417                                             vsi->seid, ret);
5418                                 goto fail_queue_alloc;
5419                         }
5420                         vsi->msix_intr = ret;
5421                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5422                                                RTE_MAX_RXTX_INTR_VEC_ID);
5423                 }
5424         } else if (type != I40E_VSI_SRIOV) {
5425                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5426                 if (ret < 0) {
5427                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5428                         goto fail_queue_alloc;
5429                 }
5430                 vsi->msix_intr = ret;
5431                 vsi->nb_msix = 1;
5432         } else {
5433                 vsi->msix_intr = 0;
5434                 vsi->nb_msix = 0;
5435         }
5436
5437         /* Add VSI */
5438         if (type == I40E_VSI_MAIN) {
5439                 /* For main VSI, no need to add since it's default one */
5440                 vsi->uplink_seid = pf->mac_seid;
5441                 vsi->seid = pf->main_vsi_seid;
5442                 /* Bind queues with specific MSIX interrupt */
5443                 /**
5444                  * Needs 2 interrupt at least, one for misc cause which will
5445                  * enabled from OS side, Another for queues binding the
5446                  * interrupt from device side only.
5447                  */
5448
5449                 /* Get default VSI parameters from hardware */
5450                 memset(&ctxt, 0, sizeof(ctxt));
5451                 ctxt.seid = vsi->seid;
5452                 ctxt.pf_num = hw->pf_id;
5453                 ctxt.uplink_seid = vsi->uplink_seid;
5454                 ctxt.vf_num = 0;
5455                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5456                 if (ret != I40E_SUCCESS) {
5457                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5458                         goto fail_msix_alloc;
5459                 }
5460                 rte_memcpy(&vsi->info, &ctxt.info,
5461                         sizeof(struct i40e_aqc_vsi_properties_data));
5462                 vsi->vsi_id = ctxt.vsi_number;
5463                 vsi->info.valid_sections = 0;
5464
5465                 /* Configure tc, enabled TC0 only */
5466                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5467                         I40E_SUCCESS) {
5468                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5469                         goto fail_msix_alloc;
5470                 }
5471
5472                 /* TC, queue mapping */
5473                 memset(&ctxt, 0, sizeof(ctxt));
5474                 vsi->info.valid_sections |=
5475                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5476                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5477                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5478                 rte_memcpy(&ctxt.info, &vsi->info,
5479                         sizeof(struct i40e_aqc_vsi_properties_data));
5480                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5481                                                 I40E_DEFAULT_TCMAP);
5482                 if (ret != I40E_SUCCESS) {
5483                         PMD_DRV_LOG(ERR,
5484                                 "Failed to configure TC queue mapping");
5485                         goto fail_msix_alloc;
5486                 }
5487                 ctxt.seid = vsi->seid;
5488                 ctxt.pf_num = hw->pf_id;
5489                 ctxt.uplink_seid = vsi->uplink_seid;
5490                 ctxt.vf_num = 0;
5491
5492                 /* Update VSI parameters */
5493                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5494                 if (ret != I40E_SUCCESS) {
5495                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5496                         goto fail_msix_alloc;
5497                 }
5498
5499                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5500                                                 sizeof(vsi->info.tc_mapping));
5501                 rte_memcpy(&vsi->info.queue_mapping,
5502                                 &ctxt.info.queue_mapping,
5503                         sizeof(vsi->info.queue_mapping));
5504                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5505                 vsi->info.valid_sections = 0;
5506
5507                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5508                                 ETH_ADDR_LEN);
5509
5510                 /**
5511                  * Updating default filter settings are necessary to prevent
5512                  * reception of tagged packets.
5513                  * Some old firmware configurations load a default macvlan
5514                  * filter which accepts both tagged and untagged packets.
5515                  * The updating is to use a normal filter instead if needed.
5516                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5517                  * The firmware with correct configurations load the default
5518                  * macvlan filter which is expected and cannot be removed.
5519                  */
5520                 i40e_update_default_filter_setting(vsi);
5521                 i40e_config_qinq(hw, vsi);
5522         } else if (type == I40E_VSI_SRIOV) {
5523                 memset(&ctxt, 0, sizeof(ctxt));
5524                 /**
5525                  * For other VSI, the uplink_seid equals to uplink VSI's
5526                  * uplink_seid since they share same VEB
5527                  */
5528                 if (uplink_vsi == NULL)
5529                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5530                 else
5531                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5532                 ctxt.pf_num = hw->pf_id;
5533                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5534                 ctxt.uplink_seid = vsi->uplink_seid;
5535                 ctxt.connection_type = 0x1;
5536                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5537
5538                 /* Use the VEB configuration if FW >= v5.0 */
5539                 if (hw->aq.fw_maj_ver >= 5) {
5540                         /* Configure switch ID */
5541                         ctxt.info.valid_sections |=
5542                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5543                         ctxt.info.switch_id =
5544                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5545                 }
5546
5547                 /* Configure port/vlan */
5548                 ctxt.info.valid_sections |=
5549                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5550                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5551                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5552                                                 hw->func_caps.enabled_tcmap);
5553                 if (ret != I40E_SUCCESS) {
5554                         PMD_DRV_LOG(ERR,
5555                                 "Failed to configure TC queue mapping");
5556                         goto fail_msix_alloc;
5557                 }
5558
5559                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5560                 ctxt.info.valid_sections |=
5561                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5562                 /**
5563                  * Since VSI is not created yet, only configure parameter,
5564                  * will add vsi below.
5565                  */
5566
5567                 i40e_config_qinq(hw, vsi);
5568         } else if (type == I40E_VSI_VMDQ2) {
5569                 memset(&ctxt, 0, sizeof(ctxt));
5570                 /*
5571                  * For other VSI, the uplink_seid equals to uplink VSI's
5572                  * uplink_seid since they share same VEB
5573                  */
5574                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5575                 ctxt.pf_num = hw->pf_id;
5576                 ctxt.vf_num = 0;
5577                 ctxt.uplink_seid = vsi->uplink_seid;
5578                 ctxt.connection_type = 0x1;
5579                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5580
5581                 ctxt.info.valid_sections |=
5582                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5583                 /* user_param carries flag to enable loop back */
5584                 if (user_param) {
5585                         ctxt.info.switch_id =
5586                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5587                         ctxt.info.switch_id |=
5588                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5589                 }
5590
5591                 /* Configure port/vlan */
5592                 ctxt.info.valid_sections |=
5593                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5594                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5595                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5596                                                 I40E_DEFAULT_TCMAP);
5597                 if (ret != I40E_SUCCESS) {
5598                         PMD_DRV_LOG(ERR,
5599                                 "Failed to configure TC queue mapping");
5600                         goto fail_msix_alloc;
5601                 }
5602                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5603                 ctxt.info.valid_sections |=
5604                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5605         } else if (type == I40E_VSI_FDIR) {
5606                 memset(&ctxt, 0, sizeof(ctxt));
5607                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5608                 ctxt.pf_num = hw->pf_id;
5609                 ctxt.vf_num = 0;
5610                 ctxt.uplink_seid = vsi->uplink_seid;
5611                 ctxt.connection_type = 0x1;     /* regular data port */
5612                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5613                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5614                                                 I40E_DEFAULT_TCMAP);
5615                 if (ret != I40E_SUCCESS) {
5616                         PMD_DRV_LOG(ERR,
5617                                 "Failed to configure TC queue mapping.");
5618                         goto fail_msix_alloc;
5619                 }
5620                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5621                 ctxt.info.valid_sections |=
5622                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5623         } else {
5624                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5625                 goto fail_msix_alloc;
5626         }
5627
5628         if (vsi->type != I40E_VSI_MAIN) {
5629                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5630                 if (ret != I40E_SUCCESS) {
5631                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5632                                     hw->aq.asq_last_status);
5633                         goto fail_msix_alloc;
5634                 }
5635                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5636                 vsi->info.valid_sections = 0;
5637                 vsi->seid = ctxt.seid;
5638                 vsi->vsi_id = ctxt.vsi_number;
5639                 vsi->sib_vsi_list.vsi = vsi;
5640                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5641                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5642                                           &vsi->sib_vsi_list, list);
5643                 } else {
5644                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5645                                           &vsi->sib_vsi_list, list);
5646                 }
5647         }
5648
5649         /* MAC/VLAN configuration */
5650         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5651         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5652
5653         ret = i40e_vsi_add_mac(vsi, &filter);
5654         if (ret != I40E_SUCCESS) {
5655                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5656                 goto fail_msix_alloc;
5657         }
5658
5659         /* Get VSI BW information */
5660         i40e_vsi_get_bw_config(vsi);
5661         return vsi;
5662 fail_msix_alloc:
5663         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5664 fail_queue_alloc:
5665         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5666 fail_mem:
5667         rte_free(vsi);
5668         return NULL;
5669 }
5670
5671 /* Configure vlan filter on or off */
5672 int
5673 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5674 {
5675         int i, num;
5676         struct i40e_mac_filter *f;
5677         void *temp;
5678         struct i40e_mac_filter_info *mac_filter;
5679         enum rte_mac_filter_type desired_filter;
5680         int ret = I40E_SUCCESS;
5681
5682         if (on) {
5683                 /* Filter to match MAC and VLAN */
5684                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5685         } else {
5686                 /* Filter to match only MAC */
5687                 desired_filter = RTE_MAC_PERFECT_MATCH;
5688         }
5689
5690         num = vsi->mac_num;
5691
5692         mac_filter = rte_zmalloc("mac_filter_info_data",
5693                                  num * sizeof(*mac_filter), 0);
5694         if (mac_filter == NULL) {
5695                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5696                 return I40E_ERR_NO_MEMORY;
5697         }
5698
5699         i = 0;
5700
5701         /* Remove all existing mac */
5702         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5703                 mac_filter[i] = f->mac_info;
5704                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5705                 if (ret) {
5706                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5707                                     on ? "enable" : "disable");
5708                         goto DONE;
5709                 }
5710                 i++;
5711         }
5712
5713         /* Override with new filter */
5714         for (i = 0; i < num; i++) {
5715                 mac_filter[i].filter_type = desired_filter;
5716                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5717                 if (ret) {
5718                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5719                                     on ? "enable" : "disable");
5720                         goto DONE;
5721                 }
5722         }
5723
5724 DONE:
5725         rte_free(mac_filter);
5726         return ret;
5727 }
5728
5729 /* Configure vlan stripping on or off */
5730 int
5731 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5732 {
5733         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5734         struct i40e_vsi_context ctxt;
5735         uint8_t vlan_flags;
5736         int ret = I40E_SUCCESS;
5737
5738         /* Check if it has been already on or off */
5739         if (vsi->info.valid_sections &
5740                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5741                 if (on) {
5742                         if ((vsi->info.port_vlan_flags &
5743                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5744                                 return 0; /* already on */
5745                 } else {
5746                         if ((vsi->info.port_vlan_flags &
5747                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5748                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5749                                 return 0; /* already off */
5750                 }
5751         }
5752
5753         if (on)
5754                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5755         else
5756                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5757         vsi->info.valid_sections =
5758                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5759         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5760         vsi->info.port_vlan_flags |= vlan_flags;
5761         ctxt.seid = vsi->seid;
5762         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5763         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5764         if (ret)
5765                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5766                             on ? "enable" : "disable");
5767
5768         return ret;
5769 }
5770
5771 static int
5772 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5773 {
5774         struct rte_eth_dev_data *data = dev->data;
5775         int ret;
5776         int mask = 0;
5777
5778         /* Apply vlan offload setting */
5779         mask = ETH_VLAN_STRIP_MASK |
5780                ETH_VLAN_FILTER_MASK |
5781                ETH_VLAN_EXTEND_MASK;
5782         ret = i40e_vlan_offload_set(dev, mask);
5783         if (ret) {
5784                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5785                 return ret;
5786         }
5787
5788         /* Apply pvid setting */
5789         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5790                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5791         if (ret)
5792                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5793
5794         return ret;
5795 }
5796
5797 static int
5798 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5799 {
5800         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5801
5802         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5803 }
5804
5805 static int
5806 i40e_update_flow_control(struct i40e_hw *hw)
5807 {
5808 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5809         struct i40e_link_status link_status;
5810         uint32_t rxfc = 0, txfc = 0, reg;
5811         uint8_t an_info;
5812         int ret;
5813
5814         memset(&link_status, 0, sizeof(link_status));
5815         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5816         if (ret != I40E_SUCCESS) {
5817                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5818                 goto write_reg; /* Disable flow control */
5819         }
5820
5821         an_info = hw->phy.link_info.an_info;
5822         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5823                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5824                 ret = I40E_ERR_NOT_READY;
5825                 goto write_reg; /* Disable flow control */
5826         }
5827         /**
5828          * If link auto negotiation is enabled, flow control needs to
5829          * be configured according to it
5830          */
5831         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5832         case I40E_LINK_PAUSE_RXTX:
5833                 rxfc = 1;
5834                 txfc = 1;
5835                 hw->fc.current_mode = I40E_FC_FULL;
5836                 break;
5837         case I40E_AQ_LINK_PAUSE_RX:
5838                 rxfc = 1;
5839                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5840                 break;
5841         case I40E_AQ_LINK_PAUSE_TX:
5842                 txfc = 1;
5843                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5844                 break;
5845         default:
5846                 hw->fc.current_mode = I40E_FC_NONE;
5847                 break;
5848         }
5849
5850 write_reg:
5851         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5852                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5853         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5854         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5855         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5856         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5857
5858         return ret;
5859 }
5860
5861 /* PF setup */
5862 static int
5863 i40e_pf_setup(struct i40e_pf *pf)
5864 {
5865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5866         struct i40e_filter_control_settings settings;
5867         struct i40e_vsi *vsi;
5868         int ret;
5869
5870         /* Clear all stats counters */
5871         pf->offset_loaded = FALSE;
5872         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5873         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5874         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5875         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5876
5877         ret = i40e_pf_get_switch_config(pf);
5878         if (ret != I40E_SUCCESS) {
5879                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5880                 return ret;
5881         }
5882
5883         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
5884         if (ret)
5885                 PMD_INIT_LOG(WARNING,
5886                         "failed to allocate switch domain for device %d", ret);
5887
5888         if (pf->flags & I40E_FLAG_FDIR) {
5889                 /* make queue allocated first, let FDIR use queue pair 0*/
5890                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5891                 if (ret != I40E_FDIR_QUEUE_ID) {
5892                         PMD_DRV_LOG(ERR,
5893                                 "queue allocation fails for FDIR: ret =%d",
5894                                 ret);
5895                         pf->flags &= ~I40E_FLAG_FDIR;
5896                 }
5897         }
5898         /*  main VSI setup */
5899         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5900         if (!vsi) {
5901                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5902                 return I40E_ERR_NOT_READY;
5903         }
5904         pf->main_vsi = vsi;
5905
5906         /* Configure filter control */
5907         memset(&settings, 0, sizeof(settings));
5908         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5909                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5910         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5911                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5912         else {
5913                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5914                         hw->func_caps.rss_table_size);
5915                 return I40E_ERR_PARAM;
5916         }
5917         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5918                 hw->func_caps.rss_table_size);
5919         pf->hash_lut_size = hw->func_caps.rss_table_size;
5920
5921         /* Enable ethtype and macvlan filters */
5922         settings.enable_ethtype = TRUE;
5923         settings.enable_macvlan = TRUE;
5924         ret = i40e_set_filter_control(hw, &settings);
5925         if (ret)
5926                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5927                                                                 ret);
5928
5929         /* Update flow control according to the auto negotiation */
5930         i40e_update_flow_control(hw);
5931
5932         return I40E_SUCCESS;
5933 }
5934
5935 int
5936 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5937 {
5938         uint32_t reg;
5939         uint16_t j;
5940
5941         /**
5942          * Set or clear TX Queue Disable flags,
5943          * which is required by hardware.
5944          */
5945         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5946         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5947
5948         /* Wait until the request is finished */
5949         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5950                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5951                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5952                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5953                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5954                                                         & 0x1))) {
5955                         break;
5956                 }
5957         }
5958         if (on) {
5959                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5960                         return I40E_SUCCESS; /* already on, skip next steps */
5961
5962                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5963                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5964         } else {
5965                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5966                         return I40E_SUCCESS; /* already off, skip next steps */
5967                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5968         }
5969         /* Write the register */
5970         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5971         /* Check the result */
5972         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5973                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5974                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5975                 if (on) {
5976                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5977                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5978                                 break;
5979                 } else {
5980                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5981                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5982                                 break;
5983                 }
5984         }
5985         /* Check if it is timeout */
5986         if (j >= I40E_CHK_Q_ENA_COUNT) {
5987                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5988                             (on ? "enable" : "disable"), q_idx);
5989                 return I40E_ERR_TIMEOUT;
5990         }
5991
5992         return I40E_SUCCESS;
5993 }
5994
5995 /* Swith on or off the tx queues */
5996 static int
5997 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5998 {
5999         struct rte_eth_dev_data *dev_data = pf->dev_data;
6000         struct i40e_tx_queue *txq;
6001         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6002         uint16_t i;
6003         int ret;
6004
6005         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6006                 txq = dev_data->tx_queues[i];
6007                 /* Don't operate the queue if not configured or
6008                  * if starting only per queue */
6009                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6010                         continue;
6011                 if (on)
6012                         ret = i40e_dev_tx_queue_start(dev, i);
6013                 else
6014                         ret = i40e_dev_tx_queue_stop(dev, i);
6015                 if ( ret != I40E_SUCCESS)
6016                         return ret;
6017         }
6018
6019         return I40E_SUCCESS;
6020 }
6021
6022 int
6023 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6024 {
6025         uint32_t reg;
6026         uint16_t j;
6027
6028         /* Wait until the request is finished */
6029         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6030                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6031                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6032                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6033                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6034                         break;
6035         }
6036
6037         if (on) {
6038                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6039                         return I40E_SUCCESS; /* Already on, skip next steps */
6040                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6041         } else {
6042                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6043                         return I40E_SUCCESS; /* Already off, skip next steps */
6044                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6045         }
6046
6047         /* Write the register */
6048         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6049         /* Check the result */
6050         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6051                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6052                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6053                 if (on) {
6054                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6055                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6056                                 break;
6057                 } else {
6058                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6059                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6060                                 break;
6061                 }
6062         }
6063
6064         /* Check if it is timeout */
6065         if (j >= I40E_CHK_Q_ENA_COUNT) {
6066                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6067                             (on ? "enable" : "disable"), q_idx);
6068                 return I40E_ERR_TIMEOUT;
6069         }
6070
6071         return I40E_SUCCESS;
6072 }
6073 /* Switch on or off the rx queues */
6074 static int
6075 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6076 {
6077         struct rte_eth_dev_data *dev_data = pf->dev_data;
6078         struct i40e_rx_queue *rxq;
6079         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6080         uint16_t i;
6081         int ret;
6082
6083         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6084                 rxq = dev_data->rx_queues[i];
6085                 /* Don't operate the queue if not configured or
6086                  * if starting only per queue */
6087                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6088                         continue;
6089                 if (on)
6090                         ret = i40e_dev_rx_queue_start(dev, i);
6091                 else
6092                         ret = i40e_dev_rx_queue_stop(dev, i);
6093                 if (ret != I40E_SUCCESS)
6094                         return ret;
6095         }
6096
6097         return I40E_SUCCESS;
6098 }
6099
6100 /* Switch on or off all the rx/tx queues */
6101 int
6102 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6103 {
6104         int ret;
6105
6106         if (on) {
6107                 /* enable rx queues before enabling tx queues */
6108                 ret = i40e_dev_switch_rx_queues(pf, on);
6109                 if (ret) {
6110                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6111                         return ret;
6112                 }
6113                 ret = i40e_dev_switch_tx_queues(pf, on);
6114         } else {
6115                 /* Stop tx queues before stopping rx queues */
6116                 ret = i40e_dev_switch_tx_queues(pf, on);
6117                 if (ret) {
6118                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6119                         return ret;
6120                 }
6121                 ret = i40e_dev_switch_rx_queues(pf, on);
6122         }
6123
6124         return ret;
6125 }
6126
6127 /* Initialize VSI for TX */
6128 static int
6129 i40e_dev_tx_init(struct i40e_pf *pf)
6130 {
6131         struct rte_eth_dev_data *data = pf->dev_data;
6132         uint16_t i;
6133         uint32_t ret = I40E_SUCCESS;
6134         struct i40e_tx_queue *txq;
6135
6136         for (i = 0; i < data->nb_tx_queues; i++) {
6137                 txq = data->tx_queues[i];
6138                 if (!txq || !txq->q_set)
6139                         continue;
6140                 ret = i40e_tx_queue_init(txq);
6141                 if (ret != I40E_SUCCESS)
6142                         break;
6143         }
6144         if (ret == I40E_SUCCESS)
6145                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6146                                      ->eth_dev);
6147
6148         return ret;
6149 }
6150
6151 /* Initialize VSI for RX */
6152 static int
6153 i40e_dev_rx_init(struct i40e_pf *pf)
6154 {
6155         struct rte_eth_dev_data *data = pf->dev_data;
6156         int ret = I40E_SUCCESS;
6157         uint16_t i;
6158         struct i40e_rx_queue *rxq;
6159
6160         i40e_pf_config_mq_rx(pf);
6161         for (i = 0; i < data->nb_rx_queues; i++) {
6162                 rxq = data->rx_queues[i];
6163                 if (!rxq || !rxq->q_set)
6164                         continue;
6165
6166                 ret = i40e_rx_queue_init(rxq);
6167                 if (ret != I40E_SUCCESS) {
6168                         PMD_DRV_LOG(ERR,
6169                                 "Failed to do RX queue initialization");
6170                         break;
6171                 }
6172         }
6173         if (ret == I40E_SUCCESS)
6174                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6175                                      ->eth_dev);
6176
6177         return ret;
6178 }
6179
6180 static int
6181 i40e_dev_rxtx_init(struct i40e_pf *pf)
6182 {
6183         int err;
6184
6185         err = i40e_dev_tx_init(pf);
6186         if (err) {
6187                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6188                 return err;
6189         }
6190         err = i40e_dev_rx_init(pf);
6191         if (err) {
6192                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6193                 return err;
6194         }
6195
6196         return err;
6197 }
6198
6199 static int
6200 i40e_vmdq_setup(struct rte_eth_dev *dev)
6201 {
6202         struct rte_eth_conf *conf = &dev->data->dev_conf;
6203         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6204         int i, err, conf_vsis, j, loop;
6205         struct i40e_vsi *vsi;
6206         struct i40e_vmdq_info *vmdq_info;
6207         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6208         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6209
6210         /*
6211          * Disable interrupt to avoid message from VF. Furthermore, it will
6212          * avoid race condition in VSI creation/destroy.
6213          */
6214         i40e_pf_disable_irq0(hw);
6215
6216         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6217                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6218                 return -ENOTSUP;
6219         }
6220
6221         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6222         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6223                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6224                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6225                         pf->max_nb_vmdq_vsi);
6226                 return -ENOTSUP;
6227         }
6228
6229         if (pf->vmdq != NULL) {
6230                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6231                 return 0;
6232         }
6233
6234         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6235                                 sizeof(*vmdq_info) * conf_vsis, 0);
6236
6237         if (pf->vmdq == NULL) {
6238                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6239                 return -ENOMEM;
6240         }
6241
6242         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6243
6244         /* Create VMDQ VSI */
6245         for (i = 0; i < conf_vsis; i++) {
6246                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6247                                 vmdq_conf->enable_loop_back);
6248                 if (vsi == NULL) {
6249                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6250                         err = -1;
6251                         goto err_vsi_setup;
6252                 }
6253                 vmdq_info = &pf->vmdq[i];
6254                 vmdq_info->pf = pf;
6255                 vmdq_info->vsi = vsi;
6256         }
6257         pf->nb_cfg_vmdq_vsi = conf_vsis;
6258
6259         /* Configure Vlan */
6260         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6261         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6262                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6263                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6264                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6265                                         vmdq_conf->pool_map[i].vlan_id, j);
6266
6267                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6268                                                 vmdq_conf->pool_map[i].vlan_id);
6269                                 if (err) {
6270                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6271                                         err = -1;
6272                                         goto err_vsi_setup;
6273                                 }
6274                         }
6275                 }
6276         }
6277
6278         i40e_pf_enable_irq0(hw);
6279
6280         return 0;
6281
6282 err_vsi_setup:
6283         for (i = 0; i < conf_vsis; i++)
6284                 if (pf->vmdq[i].vsi == NULL)
6285                         break;
6286                 else
6287                         i40e_vsi_release(pf->vmdq[i].vsi);
6288
6289         rte_free(pf->vmdq);
6290         pf->vmdq = NULL;
6291         i40e_pf_enable_irq0(hw);
6292         return err;
6293 }
6294
6295 static void
6296 i40e_stat_update_32(struct i40e_hw *hw,
6297                    uint32_t reg,
6298                    bool offset_loaded,
6299                    uint64_t *offset,
6300                    uint64_t *stat)
6301 {
6302         uint64_t new_data;
6303
6304         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6305         if (!offset_loaded)
6306                 *offset = new_data;
6307
6308         if (new_data >= *offset)
6309                 *stat = (uint64_t)(new_data - *offset);
6310         else
6311                 *stat = (uint64_t)((new_data +
6312                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6313 }
6314
6315 static void
6316 i40e_stat_update_48(struct i40e_hw *hw,
6317                    uint32_t hireg,
6318                    uint32_t loreg,
6319                    bool offset_loaded,
6320                    uint64_t *offset,
6321                    uint64_t *stat)
6322 {
6323         uint64_t new_data;
6324
6325         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6326         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6327                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6328
6329         if (!offset_loaded)
6330                 *offset = new_data;
6331
6332         if (new_data >= *offset)
6333                 *stat = new_data - *offset;
6334         else
6335                 *stat = (uint64_t)((new_data +
6336                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6337
6338         *stat &= I40E_48_BIT_MASK;
6339 }
6340
6341 /* Disable IRQ0 */
6342 void
6343 i40e_pf_disable_irq0(struct i40e_hw *hw)
6344 {
6345         /* Disable all interrupt types */
6346         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6347                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6348         I40E_WRITE_FLUSH(hw);
6349 }
6350
6351 /* Enable IRQ0 */
6352 void
6353 i40e_pf_enable_irq0(struct i40e_hw *hw)
6354 {
6355         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6356                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6357                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6358                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6359         I40E_WRITE_FLUSH(hw);
6360 }
6361
6362 static void
6363 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6364 {
6365         /* read pending request and disable first */
6366         i40e_pf_disable_irq0(hw);
6367         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6368         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6369                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6370
6371         if (no_queue)
6372                 /* Link no queues with irq0 */
6373                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6374                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6375 }
6376
6377 static void
6378 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6379 {
6380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6381         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6382         int i;
6383         uint16_t abs_vf_id;
6384         uint32_t index, offset, val;
6385
6386         if (!pf->vfs)
6387                 return;
6388         /**
6389          * Try to find which VF trigger a reset, use absolute VF id to access
6390          * since the reg is global register.
6391          */
6392         for (i = 0; i < pf->vf_num; i++) {
6393                 abs_vf_id = hw->func_caps.vf_base_id + i;
6394                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6395                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6396                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6397                 /* VFR event occurred */
6398                 if (val & (0x1 << offset)) {
6399                         int ret;
6400
6401                         /* Clear the event first */
6402                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6403                                                         (0x1 << offset));
6404                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6405                         /**
6406                          * Only notify a VF reset event occurred,
6407                          * don't trigger another SW reset
6408                          */
6409                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6410                         if (ret != I40E_SUCCESS)
6411                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6412                 }
6413         }
6414 }
6415
6416 static void
6417 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6418 {
6419         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6420         int i;
6421
6422         for (i = 0; i < pf->vf_num; i++)
6423                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6424 }
6425
6426 static void
6427 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6428 {
6429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430         struct i40e_arq_event_info info;
6431         uint16_t pending, opcode;
6432         int ret;
6433
6434         info.buf_len = I40E_AQ_BUF_SZ;
6435         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6436         if (!info.msg_buf) {
6437                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6438                 return;
6439         }
6440
6441         pending = 1;
6442         while (pending) {
6443                 ret = i40e_clean_arq_element(hw, &info, &pending);
6444
6445                 if (ret != I40E_SUCCESS) {
6446                         PMD_DRV_LOG(INFO,
6447                                 "Failed to read msg from AdminQ, aq_err: %u",
6448                                 hw->aq.asq_last_status);
6449                         break;
6450                 }
6451                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6452
6453                 switch (opcode) {
6454                 case i40e_aqc_opc_send_msg_to_pf:
6455                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6456                         i40e_pf_host_handle_vf_msg(dev,
6457                                         rte_le_to_cpu_16(info.desc.retval),
6458                                         rte_le_to_cpu_32(info.desc.cookie_high),
6459                                         rte_le_to_cpu_32(info.desc.cookie_low),
6460                                         info.msg_buf,
6461                                         info.msg_len);
6462                         break;
6463                 case i40e_aqc_opc_get_link_status:
6464                         ret = i40e_dev_link_update(dev, 0);
6465                         if (!ret)
6466                                 _rte_eth_dev_callback_process(dev,
6467                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6468                         break;
6469                 default:
6470                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6471                                     opcode);
6472                         break;
6473                 }
6474         }
6475         rte_free(info.msg_buf);
6476 }
6477
6478 /**
6479  * Interrupt handler triggered by NIC  for handling
6480  * specific interrupt.
6481  *
6482  * @param handle
6483  *  Pointer to interrupt handle.
6484  * @param param
6485  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6486  *
6487  * @return
6488  *  void
6489  */
6490 static void
6491 i40e_dev_interrupt_handler(void *param)
6492 {
6493         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495         uint32_t icr0;
6496
6497         /* Disable interrupt */
6498         i40e_pf_disable_irq0(hw);
6499
6500         /* read out interrupt causes */
6501         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6502
6503         /* No interrupt event indicated */
6504         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6505                 PMD_DRV_LOG(INFO, "No interrupt event");
6506                 goto done;
6507         }
6508         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6509                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6510         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6511                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6512         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6513                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6514         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6515                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6516         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6517                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6518         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6519                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6520         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6521                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6522
6523         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6524                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6525                 i40e_dev_handle_vfr_event(dev);
6526         }
6527         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6528                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6529                 i40e_dev_handle_aq_msg(dev);
6530         }
6531
6532 done:
6533         /* Enable interrupt */
6534         i40e_pf_enable_irq0(hw);
6535         rte_intr_enable(dev->intr_handle);
6536 }
6537
6538 int
6539 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6540                          struct i40e_macvlan_filter *filter,
6541                          int total)
6542 {
6543         int ele_num, ele_buff_size;
6544         int num, actual_num, i;
6545         uint16_t flags;
6546         int ret = I40E_SUCCESS;
6547         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6548         struct i40e_aqc_add_macvlan_element_data *req_list;
6549
6550         if (filter == NULL  || total == 0)
6551                 return I40E_ERR_PARAM;
6552         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6553         ele_buff_size = hw->aq.asq_buf_size;
6554
6555         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6556         if (req_list == NULL) {
6557                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6558                 return I40E_ERR_NO_MEMORY;
6559         }
6560
6561         num = 0;
6562         do {
6563                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6564                 memset(req_list, 0, ele_buff_size);
6565
6566                 for (i = 0; i < actual_num; i++) {
6567                         rte_memcpy(req_list[i].mac_addr,
6568                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6569                         req_list[i].vlan_tag =
6570                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6571
6572                         switch (filter[num + i].filter_type) {
6573                         case RTE_MAC_PERFECT_MATCH:
6574                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6575                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6576                                 break;
6577                         case RTE_MACVLAN_PERFECT_MATCH:
6578                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6579                                 break;
6580                         case RTE_MAC_HASH_MATCH:
6581                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6582                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6583                                 break;
6584                         case RTE_MACVLAN_HASH_MATCH:
6585                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6586                                 break;
6587                         default:
6588                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6589                                 ret = I40E_ERR_PARAM;
6590                                 goto DONE;
6591                         }
6592
6593                         req_list[i].queue_number = 0;
6594
6595                         req_list[i].flags = rte_cpu_to_le_16(flags);
6596                 }
6597
6598                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6599                                                 actual_num, NULL);
6600                 if (ret != I40E_SUCCESS) {
6601                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6602                         goto DONE;
6603                 }
6604                 num += actual_num;
6605         } while (num < total);
6606
6607 DONE:
6608         rte_free(req_list);
6609         return ret;
6610 }
6611
6612 int
6613 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6614                             struct i40e_macvlan_filter *filter,
6615                             int total)
6616 {
6617         int ele_num, ele_buff_size;
6618         int num, actual_num, i;
6619         uint16_t flags;
6620         int ret = I40E_SUCCESS;
6621         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6622         struct i40e_aqc_remove_macvlan_element_data *req_list;
6623
6624         if (filter == NULL  || total == 0)
6625                 return I40E_ERR_PARAM;
6626
6627         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6628         ele_buff_size = hw->aq.asq_buf_size;
6629
6630         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6631         if (req_list == NULL) {
6632                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6633                 return I40E_ERR_NO_MEMORY;
6634         }
6635
6636         num = 0;
6637         do {
6638                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6639                 memset(req_list, 0, ele_buff_size);
6640
6641                 for (i = 0; i < actual_num; i++) {
6642                         rte_memcpy(req_list[i].mac_addr,
6643                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6644                         req_list[i].vlan_tag =
6645                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6646
6647                         switch (filter[num + i].filter_type) {
6648                         case RTE_MAC_PERFECT_MATCH:
6649                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6650                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6651                                 break;
6652                         case RTE_MACVLAN_PERFECT_MATCH:
6653                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6654                                 break;
6655                         case RTE_MAC_HASH_MATCH:
6656                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6657                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6658                                 break;
6659                         case RTE_MACVLAN_HASH_MATCH:
6660                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6661                                 break;
6662                         default:
6663                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6664                                 ret = I40E_ERR_PARAM;
6665                                 goto DONE;
6666                         }
6667                         req_list[i].flags = rte_cpu_to_le_16(flags);
6668                 }
6669
6670                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6671                                                 actual_num, NULL);
6672                 if (ret != I40E_SUCCESS) {
6673                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6674                         goto DONE;
6675                 }
6676                 num += actual_num;
6677         } while (num < total);
6678
6679 DONE:
6680         rte_free(req_list);
6681         return ret;
6682 }
6683
6684 /* Find out specific MAC filter */
6685 static struct i40e_mac_filter *
6686 i40e_find_mac_filter(struct i40e_vsi *vsi,
6687                          struct ether_addr *macaddr)
6688 {
6689         struct i40e_mac_filter *f;
6690
6691         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6692                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6693                         return f;
6694         }
6695
6696         return NULL;
6697 }
6698
6699 static bool
6700 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6701                          uint16_t vlan_id)
6702 {
6703         uint32_t vid_idx, vid_bit;
6704
6705         if (vlan_id > ETH_VLAN_ID_MAX)
6706                 return 0;
6707
6708         vid_idx = I40E_VFTA_IDX(vlan_id);
6709         vid_bit = I40E_VFTA_BIT(vlan_id);
6710
6711         if (vsi->vfta[vid_idx] & vid_bit)
6712                 return 1;
6713         else
6714                 return 0;
6715 }
6716
6717 static void
6718 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6719                        uint16_t vlan_id, bool on)
6720 {
6721         uint32_t vid_idx, vid_bit;
6722
6723         vid_idx = I40E_VFTA_IDX(vlan_id);
6724         vid_bit = I40E_VFTA_BIT(vlan_id);
6725
6726         if (on)
6727                 vsi->vfta[vid_idx] |= vid_bit;
6728         else
6729                 vsi->vfta[vid_idx] &= ~vid_bit;
6730 }
6731
6732 void
6733 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6734                      uint16_t vlan_id, bool on)
6735 {
6736         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6737         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6738         int ret;
6739
6740         if (vlan_id > ETH_VLAN_ID_MAX)
6741                 return;
6742
6743         i40e_store_vlan_filter(vsi, vlan_id, on);
6744
6745         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6746                 return;
6747
6748         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6749
6750         if (on) {
6751                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6752                                        &vlan_data, 1, NULL);
6753                 if (ret != I40E_SUCCESS)
6754                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6755         } else {
6756                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6757                                           &vlan_data, 1, NULL);
6758                 if (ret != I40E_SUCCESS)
6759                         PMD_DRV_LOG(ERR,
6760                                     "Failed to remove vlan filter");
6761         }
6762 }
6763
6764 /**
6765  * Find all vlan options for specific mac addr,
6766  * return with actual vlan found.
6767  */
6768 int
6769 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6770                            struct i40e_macvlan_filter *mv_f,
6771                            int num, struct ether_addr *addr)
6772 {
6773         int i;
6774         uint32_t j, k;
6775
6776         /**
6777          * Not to use i40e_find_vlan_filter to decrease the loop time,
6778          * although the code looks complex.
6779           */
6780         if (num < vsi->vlan_num)
6781                 return I40E_ERR_PARAM;
6782
6783         i = 0;
6784         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6785                 if (vsi->vfta[j]) {
6786                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6787                                 if (vsi->vfta[j] & (1 << k)) {
6788                                         if (i > num - 1) {
6789                                                 PMD_DRV_LOG(ERR,
6790                                                         "vlan number doesn't match");
6791                                                 return I40E_ERR_PARAM;
6792                                         }
6793                                         rte_memcpy(&mv_f[i].macaddr,
6794                                                         addr, ETH_ADDR_LEN);
6795                                         mv_f[i].vlan_id =
6796                                                 j * I40E_UINT32_BIT_SIZE + k;
6797                                         i++;
6798                                 }
6799                         }
6800                 }
6801         }
6802         return I40E_SUCCESS;
6803 }
6804
6805 static inline int
6806 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6807                            struct i40e_macvlan_filter *mv_f,
6808                            int num,
6809                            uint16_t vlan)
6810 {
6811         int i = 0;
6812         struct i40e_mac_filter *f;
6813
6814         if (num < vsi->mac_num)
6815                 return I40E_ERR_PARAM;
6816
6817         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6818                 if (i > num - 1) {
6819                         PMD_DRV_LOG(ERR, "buffer number not match");
6820                         return I40E_ERR_PARAM;
6821                 }
6822                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6823                                 ETH_ADDR_LEN);
6824                 mv_f[i].vlan_id = vlan;
6825                 mv_f[i].filter_type = f->mac_info.filter_type;
6826                 i++;
6827         }
6828
6829         return I40E_SUCCESS;
6830 }
6831
6832 static int
6833 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6834 {
6835         int i, j, num;
6836         struct i40e_mac_filter *f;
6837         struct i40e_macvlan_filter *mv_f;
6838         int ret = I40E_SUCCESS;
6839
6840         if (vsi == NULL || vsi->mac_num == 0)
6841                 return I40E_ERR_PARAM;
6842
6843         /* Case that no vlan is set */
6844         if (vsi->vlan_num == 0)
6845                 num = vsi->mac_num;
6846         else
6847                 num = vsi->mac_num * vsi->vlan_num;
6848
6849         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6850         if (mv_f == NULL) {
6851                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6852                 return I40E_ERR_NO_MEMORY;
6853         }
6854
6855         i = 0;
6856         if (vsi->vlan_num == 0) {
6857                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6858                         rte_memcpy(&mv_f[i].macaddr,
6859                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6860                         mv_f[i].filter_type = f->mac_info.filter_type;
6861                         mv_f[i].vlan_id = 0;
6862                         i++;
6863                 }
6864         } else {
6865                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6866                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6867                                         vsi->vlan_num, &f->mac_info.mac_addr);
6868                         if (ret != I40E_SUCCESS)
6869                                 goto DONE;
6870                         for (j = i; j < i + vsi->vlan_num; j++)
6871                                 mv_f[j].filter_type = f->mac_info.filter_type;
6872                         i += vsi->vlan_num;
6873                 }
6874         }
6875
6876         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6877 DONE:
6878         rte_free(mv_f);
6879
6880         return ret;
6881 }
6882
6883 int
6884 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6885 {
6886         struct i40e_macvlan_filter *mv_f;
6887         int mac_num;
6888         int ret = I40E_SUCCESS;
6889
6890         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6891                 return I40E_ERR_PARAM;
6892
6893         /* If it's already set, just return */
6894         if (i40e_find_vlan_filter(vsi,vlan))
6895                 return I40E_SUCCESS;
6896
6897         mac_num = vsi->mac_num;
6898
6899         if (mac_num == 0) {
6900                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6901                 return I40E_ERR_PARAM;
6902         }
6903
6904         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6905
6906         if (mv_f == NULL) {
6907                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6908                 return I40E_ERR_NO_MEMORY;
6909         }
6910
6911         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6912
6913         if (ret != I40E_SUCCESS)
6914                 goto DONE;
6915
6916         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6917
6918         if (ret != I40E_SUCCESS)
6919                 goto DONE;
6920
6921         i40e_set_vlan_filter(vsi, vlan, 1);
6922
6923         vsi->vlan_num++;
6924         ret = I40E_SUCCESS;
6925 DONE:
6926         rte_free(mv_f);
6927         return ret;
6928 }
6929
6930 int
6931 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6932 {
6933         struct i40e_macvlan_filter *mv_f;
6934         int mac_num;
6935         int ret = I40E_SUCCESS;
6936
6937         /**
6938          * Vlan 0 is the generic filter for untagged packets
6939          * and can't be removed.
6940          */
6941         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6942                 return I40E_ERR_PARAM;
6943
6944         /* If can't find it, just return */
6945         if (!i40e_find_vlan_filter(vsi, vlan))
6946                 return I40E_ERR_PARAM;
6947
6948         mac_num = vsi->mac_num;
6949
6950         if (mac_num == 0) {
6951                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6952                 return I40E_ERR_PARAM;
6953         }
6954
6955         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6956
6957         if (mv_f == NULL) {
6958                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6959                 return I40E_ERR_NO_MEMORY;
6960         }
6961
6962         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6963
6964         if (ret != I40E_SUCCESS)
6965                 goto DONE;
6966
6967         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6968
6969         if (ret != I40E_SUCCESS)
6970                 goto DONE;
6971
6972         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6973         if (vsi->vlan_num == 1) {
6974                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6975                 if (ret != I40E_SUCCESS)
6976                         goto DONE;
6977
6978                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6979                 if (ret != I40E_SUCCESS)
6980                         goto DONE;
6981         }
6982
6983         i40e_set_vlan_filter(vsi, vlan, 0);
6984
6985         vsi->vlan_num--;
6986         ret = I40E_SUCCESS;
6987 DONE:
6988         rte_free(mv_f);
6989         return ret;
6990 }
6991
6992 int
6993 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6994 {
6995         struct i40e_mac_filter *f;
6996         struct i40e_macvlan_filter *mv_f;
6997         int i, vlan_num = 0;
6998         int ret = I40E_SUCCESS;
6999
7000         /* If it's add and we've config it, return */
7001         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7002         if (f != NULL)
7003                 return I40E_SUCCESS;
7004         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7005                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7006
7007                 /**
7008                  * If vlan_num is 0, that's the first time to add mac,
7009                  * set mask for vlan_id 0.
7010                  */
7011                 if (vsi->vlan_num == 0) {
7012                         i40e_set_vlan_filter(vsi, 0, 1);
7013                         vsi->vlan_num = 1;
7014                 }
7015                 vlan_num = vsi->vlan_num;
7016         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7017                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7018                 vlan_num = 1;
7019
7020         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7021         if (mv_f == NULL) {
7022                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7023                 return I40E_ERR_NO_MEMORY;
7024         }
7025
7026         for (i = 0; i < vlan_num; i++) {
7027                 mv_f[i].filter_type = mac_filter->filter_type;
7028                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7029                                 ETH_ADDR_LEN);
7030         }
7031
7032         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7033                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7034                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7035                                         &mac_filter->mac_addr);
7036                 if (ret != I40E_SUCCESS)
7037                         goto DONE;
7038         }
7039
7040         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7041         if (ret != I40E_SUCCESS)
7042                 goto DONE;
7043
7044         /* Add the mac addr into mac list */
7045         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7046         if (f == NULL) {
7047                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7048                 ret = I40E_ERR_NO_MEMORY;
7049                 goto DONE;
7050         }
7051         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7052                         ETH_ADDR_LEN);
7053         f->mac_info.filter_type = mac_filter->filter_type;
7054         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7055         vsi->mac_num++;
7056
7057         ret = I40E_SUCCESS;
7058 DONE:
7059         rte_free(mv_f);
7060
7061         return ret;
7062 }
7063
7064 int
7065 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7066 {
7067         struct i40e_mac_filter *f;
7068         struct i40e_macvlan_filter *mv_f;
7069         int i, vlan_num;
7070         enum rte_mac_filter_type filter_type;
7071         int ret = I40E_SUCCESS;
7072
7073         /* Can't find it, return an error */
7074         f = i40e_find_mac_filter(vsi, addr);
7075         if (f == NULL)
7076                 return I40E_ERR_PARAM;
7077
7078         vlan_num = vsi->vlan_num;
7079         filter_type = f->mac_info.filter_type;
7080         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7081                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7082                 if (vlan_num == 0) {
7083                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7084                         return I40E_ERR_PARAM;
7085                 }
7086         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7087                         filter_type == RTE_MAC_HASH_MATCH)
7088                 vlan_num = 1;
7089
7090         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7091         if (mv_f == NULL) {
7092                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7093                 return I40E_ERR_NO_MEMORY;
7094         }
7095
7096         for (i = 0; i < vlan_num; i++) {
7097                 mv_f[i].filter_type = filter_type;
7098                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7099                                 ETH_ADDR_LEN);
7100         }
7101         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7102                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7103                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7104                 if (ret != I40E_SUCCESS)
7105                         goto DONE;
7106         }
7107
7108         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7109         if (ret != I40E_SUCCESS)
7110                 goto DONE;
7111
7112         /* Remove the mac addr into mac list */
7113         TAILQ_REMOVE(&vsi->mac_list, f, next);
7114         rte_free(f);
7115         vsi->mac_num--;
7116
7117         ret = I40E_SUCCESS;
7118 DONE:
7119         rte_free(mv_f);
7120         return ret;
7121 }
7122
7123 /* Configure hash enable flags for RSS */
7124 uint64_t
7125 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7126 {
7127         uint64_t hena = 0;
7128         int i;
7129
7130         if (!flags)
7131                 return hena;
7132
7133         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7134                 if (flags & (1ULL << i))
7135                         hena |= adapter->pctypes_tbl[i];
7136         }
7137
7138         return hena;
7139 }
7140
7141 /* Parse the hash enable flags */
7142 uint64_t
7143 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7144 {
7145         uint64_t rss_hf = 0;
7146
7147         if (!flags)
7148                 return rss_hf;
7149         int i;
7150
7151         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7152                 if (flags & adapter->pctypes_tbl[i])
7153                         rss_hf |= (1ULL << i);
7154         }
7155         return rss_hf;
7156 }
7157
7158 /* Disable RSS */
7159 static void
7160 i40e_pf_disable_rss(struct i40e_pf *pf)
7161 {
7162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7163
7164         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7165         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7166         I40E_WRITE_FLUSH(hw);
7167 }
7168
7169 int
7170 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7171 {
7172         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7173         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7174         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7175                            I40E_VFQF_HKEY_MAX_INDEX :
7176                            I40E_PFQF_HKEY_MAX_INDEX;
7177         int ret = 0;
7178
7179         if (!key || key_len == 0) {
7180                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7181                 return 0;
7182         } else if (key_len != (key_idx + 1) *
7183                 sizeof(uint32_t)) {
7184                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7185                 return -EINVAL;
7186         }
7187
7188         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7189                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7190                         (struct i40e_aqc_get_set_rss_key_data *)key;
7191
7192                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7193                 if (ret)
7194                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7195         } else {
7196                 uint32_t *hash_key = (uint32_t *)key;
7197                 uint16_t i;
7198
7199                 if (vsi->type == I40E_VSI_SRIOV) {
7200                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7201                                 I40E_WRITE_REG(
7202                                         hw,
7203                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7204                                         hash_key[i]);
7205
7206                 } else {
7207                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7208                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7209                                                hash_key[i]);
7210                 }
7211                 I40E_WRITE_FLUSH(hw);
7212         }
7213
7214         return ret;
7215 }
7216
7217 static int
7218 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7219 {
7220         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7221         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7222         uint32_t reg;
7223         int ret;
7224
7225         if (!key || !key_len)
7226                 return -EINVAL;
7227
7228         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7229                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7230                         (struct i40e_aqc_get_set_rss_key_data *)key);
7231                 if (ret) {
7232                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7233                         return ret;
7234                 }
7235         } else {
7236                 uint32_t *key_dw = (uint32_t *)key;
7237                 uint16_t i;
7238
7239                 if (vsi->type == I40E_VSI_SRIOV) {
7240                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7241                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7242                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7243                         }
7244                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7245                                    sizeof(uint32_t);
7246                 } else {
7247                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7248                                 reg = I40E_PFQF_HKEY(i);
7249                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7250                         }
7251                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7252                                    sizeof(uint32_t);
7253                 }
7254         }
7255         return 0;
7256 }
7257
7258 static int
7259 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7260 {
7261         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7262         uint64_t hena;
7263         int ret;
7264
7265         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7266                                rss_conf->rss_key_len);
7267         if (ret)
7268                 return ret;
7269
7270         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7271         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7272         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7273         I40E_WRITE_FLUSH(hw);
7274
7275         return 0;
7276 }
7277
7278 static int
7279 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7280                          struct rte_eth_rss_conf *rss_conf)
7281 {
7282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7285         uint64_t hena;
7286
7287         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7288         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7289
7290         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7291                 if (rss_hf != 0) /* Enable RSS */
7292                         return -EINVAL;
7293                 return 0; /* Nothing to do */
7294         }
7295         /* RSS enabled */
7296         if (rss_hf == 0) /* Disable RSS */
7297                 return -EINVAL;
7298
7299         return i40e_hw_rss_hash_set(pf, rss_conf);
7300 }
7301
7302 static int
7303 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7304                            struct rte_eth_rss_conf *rss_conf)
7305 {
7306         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7307         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7308         uint64_t hena;
7309
7310         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7311                          &rss_conf->rss_key_len);
7312
7313         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7314         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7315         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7316
7317         return 0;
7318 }
7319
7320 static int
7321 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7322 {
7323         switch (filter_type) {
7324         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7325                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7326                 break;
7327         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7328                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7329                 break;
7330         case RTE_TUNNEL_FILTER_IMAC_TENID:
7331                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7332                 break;
7333         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7334                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7335                 break;
7336         case ETH_TUNNEL_FILTER_IMAC:
7337                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7338                 break;
7339         case ETH_TUNNEL_FILTER_OIP:
7340                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7341                 break;
7342         case ETH_TUNNEL_FILTER_IIP:
7343                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7344                 break;
7345         default:
7346                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7347                 return -EINVAL;
7348         }
7349
7350         return 0;
7351 }
7352
7353 /* Convert tunnel filter structure */
7354 static int
7355 i40e_tunnel_filter_convert(
7356         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7357         struct i40e_tunnel_filter *tunnel_filter)
7358 {
7359         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7360                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7361         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7362                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7363         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7364         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7365              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7366             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7367                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7368         else
7369                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7370         tunnel_filter->input.flags = cld_filter->element.flags;
7371         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7372         tunnel_filter->queue = cld_filter->element.queue_number;
7373         rte_memcpy(tunnel_filter->input.general_fields,
7374                    cld_filter->general_fields,
7375                    sizeof(cld_filter->general_fields));
7376
7377         return 0;
7378 }
7379
7380 /* Check if there exists the tunnel filter */
7381 struct i40e_tunnel_filter *
7382 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7383                              const struct i40e_tunnel_filter_input *input)
7384 {
7385         int ret;
7386
7387         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7388         if (ret < 0)
7389                 return NULL;
7390
7391         return tunnel_rule->hash_map[ret];
7392 }
7393
7394 /* Add a tunnel filter into the SW list */
7395 static int
7396 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7397                              struct i40e_tunnel_filter *tunnel_filter)
7398 {
7399         struct i40e_tunnel_rule *rule = &pf->tunnel;
7400         int ret;
7401
7402         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7403         if (ret < 0) {
7404                 PMD_DRV_LOG(ERR,
7405                             "Failed to insert tunnel filter to hash table %d!",
7406                             ret);
7407                 return ret;
7408         }
7409         rule->hash_map[ret] = tunnel_filter;
7410
7411         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7412
7413         return 0;
7414 }
7415
7416 /* Delete a tunnel filter from the SW list */
7417 int
7418 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7419                           struct i40e_tunnel_filter_input *input)
7420 {
7421         struct i40e_tunnel_rule *rule = &pf->tunnel;
7422         struct i40e_tunnel_filter *tunnel_filter;
7423         int ret;
7424
7425         ret = rte_hash_del_key(rule->hash_table, input);
7426         if (ret < 0) {
7427                 PMD_DRV_LOG(ERR,
7428                             "Failed to delete tunnel filter to hash table %d!",
7429                             ret);
7430                 return ret;
7431         }
7432         tunnel_filter = rule->hash_map[ret];
7433         rule->hash_map[ret] = NULL;
7434
7435         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7436         rte_free(tunnel_filter);
7437
7438         return 0;
7439 }
7440
7441 int
7442 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7443                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7444                         uint8_t add)
7445 {
7446         uint16_t ip_type;
7447         uint32_t ipv4_addr, ipv4_addr_le;
7448         uint8_t i, tun_type = 0;
7449         /* internal varialbe to convert ipv6 byte order */
7450         uint32_t convert_ipv6[4];
7451         int val, ret = 0;
7452         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7453         struct i40e_vsi *vsi = pf->main_vsi;
7454         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7455         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7456         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7457         struct i40e_tunnel_filter *tunnel, *node;
7458         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7459
7460         cld_filter = rte_zmalloc("tunnel_filter",
7461                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7462         0);
7463
7464         if (NULL == cld_filter) {
7465                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7466                 return -ENOMEM;
7467         }
7468         pfilter = cld_filter;
7469
7470         ether_addr_copy(&tunnel_filter->outer_mac,
7471                         (struct ether_addr *)&pfilter->element.outer_mac);
7472         ether_addr_copy(&tunnel_filter->inner_mac,
7473                         (struct ether_addr *)&pfilter->element.inner_mac);
7474
7475         pfilter->element.inner_vlan =
7476                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7477         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7478                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7479                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7480                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7481                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7482                                 &ipv4_addr_le,
7483                                 sizeof(pfilter->element.ipaddr.v4.data));
7484         } else {
7485                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7486                 for (i = 0; i < 4; i++) {
7487                         convert_ipv6[i] =
7488                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7489                 }
7490                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7491                            &convert_ipv6,
7492                            sizeof(pfilter->element.ipaddr.v6.data));
7493         }
7494
7495         /* check tunneled type */
7496         switch (tunnel_filter->tunnel_type) {
7497         case RTE_TUNNEL_TYPE_VXLAN:
7498                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7499                 break;
7500         case RTE_TUNNEL_TYPE_NVGRE:
7501                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7502                 break;
7503         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7504                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7505                 break;
7506         default:
7507                 /* Other tunnel types is not supported. */
7508                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7509                 rte_free(cld_filter);
7510                 return -EINVAL;
7511         }
7512
7513         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7514                                        &pfilter->element.flags);
7515         if (val < 0) {
7516                 rte_free(cld_filter);
7517                 return -EINVAL;
7518         }
7519
7520         pfilter->element.flags |= rte_cpu_to_le_16(
7521                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7522                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7523         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7524         pfilter->element.queue_number =
7525                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7526
7527         /* Check if there is the filter in SW list */
7528         memset(&check_filter, 0, sizeof(check_filter));
7529         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7530         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7531         if (add && node) {
7532                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7533                 rte_free(cld_filter);
7534                 return -EINVAL;
7535         }
7536
7537         if (!add && !node) {
7538                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7539                 rte_free(cld_filter);
7540                 return -EINVAL;
7541         }
7542
7543         if (add) {
7544                 ret = i40e_aq_add_cloud_filters(hw,
7545                                         vsi->seid, &cld_filter->element, 1);
7546                 if (ret < 0) {
7547                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7548                         rte_free(cld_filter);
7549                         return -ENOTSUP;
7550                 }
7551                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7552                 if (tunnel == NULL) {
7553                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7554                         rte_free(cld_filter);
7555                         return -ENOMEM;
7556                 }
7557
7558                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7559                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7560                 if (ret < 0)
7561                         rte_free(tunnel);
7562         } else {
7563                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7564                                                    &cld_filter->element, 1);
7565                 if (ret < 0) {
7566                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7567                         rte_free(cld_filter);
7568                         return -ENOTSUP;
7569                 }
7570                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7571         }
7572
7573         rte_free(cld_filter);
7574         return ret;
7575 }
7576
7577 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7578 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7579 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7580 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7581 #define I40E_TR_GRE_KEY_MASK                    0x400
7582 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7583 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7584
7585 static enum
7586 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7587 {
7588         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7589         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7591         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7592         enum i40e_status_code status = I40E_SUCCESS;
7593
7594         if (pf->support_multi_driver) {
7595                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7596                 return I40E_NOT_SUPPORTED;
7597         }
7598
7599         memset(&filter_replace, 0,
7600                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7601         memset(&filter_replace_buf, 0,
7602                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7603
7604         /* create L1 filter */
7605         filter_replace.old_filter_type =
7606                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7607         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7608         filter_replace.tr_bit = 0;
7609
7610         /* Prepare the buffer, 3 entries */
7611         filter_replace_buf.data[0] =
7612                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7613         filter_replace_buf.data[0] |=
7614                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7615         filter_replace_buf.data[2] = 0xFF;
7616         filter_replace_buf.data[3] = 0xFF;
7617         filter_replace_buf.data[4] =
7618                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7619         filter_replace_buf.data[4] |=
7620                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7621         filter_replace_buf.data[7] = 0xF0;
7622         filter_replace_buf.data[8]
7623                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7624         filter_replace_buf.data[8] |=
7625                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7626         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7627                 I40E_TR_GENEVE_KEY_MASK |
7628                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7629         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7630                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7631                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7632
7633         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7634                                                &filter_replace_buf);
7635         if (!status && (filter_replace.old_filter_type !=
7636                         filter_replace.new_filter_type))
7637                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7638                             " original: 0x%x, new: 0x%x",
7639                             dev->device->name,
7640                             filter_replace.old_filter_type,
7641                             filter_replace.new_filter_type);
7642
7643         return status;
7644 }
7645
7646 static enum
7647 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7648 {
7649         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7650         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7651         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7652         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7653         enum i40e_status_code status = I40E_SUCCESS;
7654
7655         if (pf->support_multi_driver) {
7656                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7657                 return I40E_NOT_SUPPORTED;
7658         }
7659
7660         /* For MPLSoUDP */
7661         memset(&filter_replace, 0,
7662                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7663         memset(&filter_replace_buf, 0,
7664                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7665         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7666                 I40E_AQC_MIRROR_CLOUD_FILTER;
7667         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7668         filter_replace.new_filter_type =
7669                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7670         /* Prepare the buffer, 2 entries */
7671         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7672         filter_replace_buf.data[0] |=
7673                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7674         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7675         filter_replace_buf.data[4] |=
7676                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7677         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7678                                                &filter_replace_buf);
7679         if (status < 0)
7680                 return status;
7681         if (filter_replace.old_filter_type !=
7682             filter_replace.new_filter_type)
7683                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7684                             " original: 0x%x, new: 0x%x",
7685                             dev->device->name,
7686                             filter_replace.old_filter_type,
7687                             filter_replace.new_filter_type);
7688
7689         /* For MPLSoGRE */
7690         memset(&filter_replace, 0,
7691                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7692         memset(&filter_replace_buf, 0,
7693                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7694
7695         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7696                 I40E_AQC_MIRROR_CLOUD_FILTER;
7697         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7698         filter_replace.new_filter_type =
7699                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7700         /* Prepare the buffer, 2 entries */
7701         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7702         filter_replace_buf.data[0] |=
7703                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7704         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7705         filter_replace_buf.data[4] |=
7706                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7707
7708         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7709                                                &filter_replace_buf);
7710         if (!status && (filter_replace.old_filter_type !=
7711                         filter_replace.new_filter_type))
7712                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7713                             " original: 0x%x, new: 0x%x",
7714                             dev->device->name,
7715                             filter_replace.old_filter_type,
7716                             filter_replace.new_filter_type);
7717
7718         return status;
7719 }
7720
7721 static enum i40e_status_code
7722 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7723 {
7724         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7725         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7726         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7727         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7728         enum i40e_status_code status = I40E_SUCCESS;
7729
7730         if (pf->support_multi_driver) {
7731                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7732                 return I40E_NOT_SUPPORTED;
7733         }
7734
7735         /* For GTP-C */
7736         memset(&filter_replace, 0,
7737                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7738         memset(&filter_replace_buf, 0,
7739                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7740         /* create L1 filter */
7741         filter_replace.old_filter_type =
7742                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7743         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7744         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7745                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7746         /* Prepare the buffer, 2 entries */
7747         filter_replace_buf.data[0] =
7748                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7749         filter_replace_buf.data[0] |=
7750                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7751         filter_replace_buf.data[2] = 0xFF;
7752         filter_replace_buf.data[3] = 0xFF;
7753         filter_replace_buf.data[4] =
7754                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7755         filter_replace_buf.data[4] |=
7756                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7757         filter_replace_buf.data[6] = 0xFF;
7758         filter_replace_buf.data[7] = 0xFF;
7759         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7760                                                &filter_replace_buf);
7761         if (status < 0)
7762                 return status;
7763         if (filter_replace.old_filter_type !=
7764             filter_replace.new_filter_type)
7765                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7766                             " original: 0x%x, new: 0x%x",
7767                             dev->device->name,
7768                             filter_replace.old_filter_type,
7769                             filter_replace.new_filter_type);
7770
7771         /* for GTP-U */
7772         memset(&filter_replace, 0,
7773                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7774         memset(&filter_replace_buf, 0,
7775                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7776         /* create L1 filter */
7777         filter_replace.old_filter_type =
7778                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7779         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7780         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7781                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7782         /* Prepare the buffer, 2 entries */
7783         filter_replace_buf.data[0] =
7784                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7785         filter_replace_buf.data[0] |=
7786                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7787         filter_replace_buf.data[2] = 0xFF;
7788         filter_replace_buf.data[3] = 0xFF;
7789         filter_replace_buf.data[4] =
7790                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7791         filter_replace_buf.data[4] |=
7792                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7793         filter_replace_buf.data[6] = 0xFF;
7794         filter_replace_buf.data[7] = 0xFF;
7795
7796         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7797                                                &filter_replace_buf);
7798         if (!status && (filter_replace.old_filter_type !=
7799                         filter_replace.new_filter_type))
7800                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7801                             " original: 0x%x, new: 0x%x",
7802                             dev->device->name,
7803                             filter_replace.old_filter_type,
7804                             filter_replace.new_filter_type);
7805
7806         return status;
7807 }
7808
7809 static enum
7810 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7811 {
7812         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7813         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7815         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7816         enum i40e_status_code status = I40E_SUCCESS;
7817
7818         if (pf->support_multi_driver) {
7819                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7820                 return I40E_NOT_SUPPORTED;
7821         }
7822
7823         /* for GTP-C */
7824         memset(&filter_replace, 0,
7825                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7826         memset(&filter_replace_buf, 0,
7827                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7828         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7829         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7830         filter_replace.new_filter_type =
7831                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7832         /* Prepare the buffer, 2 entries */
7833         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7834         filter_replace_buf.data[0] |=
7835                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7836         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7837         filter_replace_buf.data[4] |=
7838                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7839         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7840                                                &filter_replace_buf);
7841         if (status < 0)
7842                 return status;
7843         if (filter_replace.old_filter_type !=
7844             filter_replace.new_filter_type)
7845                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7846                             " original: 0x%x, new: 0x%x",
7847                             dev->device->name,
7848                             filter_replace.old_filter_type,
7849                             filter_replace.new_filter_type);
7850
7851         /* for GTP-U */
7852         memset(&filter_replace, 0,
7853                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7854         memset(&filter_replace_buf, 0,
7855                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7856         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7857         filter_replace.old_filter_type =
7858                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7859         filter_replace.new_filter_type =
7860                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7861         /* Prepare the buffer, 2 entries */
7862         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7863         filter_replace_buf.data[0] |=
7864                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7865         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7866         filter_replace_buf.data[4] |=
7867                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7868
7869         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7870                                                &filter_replace_buf);
7871         if (!status && (filter_replace.old_filter_type !=
7872                         filter_replace.new_filter_type))
7873                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7874                             " original: 0x%x, new: 0x%x",
7875                             dev->device->name,
7876                             filter_replace.old_filter_type,
7877                             filter_replace.new_filter_type);
7878
7879         return status;
7880 }
7881
7882 int
7883 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7884                       struct i40e_tunnel_filter_conf *tunnel_filter,
7885                       uint8_t add)
7886 {
7887         uint16_t ip_type;
7888         uint32_t ipv4_addr, ipv4_addr_le;
7889         uint8_t i, tun_type = 0;
7890         /* internal variable to convert ipv6 byte order */
7891         uint32_t convert_ipv6[4];
7892         int val, ret = 0;
7893         struct i40e_pf_vf *vf = NULL;
7894         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7895         struct i40e_vsi *vsi;
7896         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7897         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7898         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7899         struct i40e_tunnel_filter *tunnel, *node;
7900         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7901         uint32_t teid_le;
7902         bool big_buffer = 0;
7903
7904         cld_filter = rte_zmalloc("tunnel_filter",
7905                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7906                          0);
7907
7908         if (cld_filter == NULL) {
7909                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7910                 return -ENOMEM;
7911         }
7912         pfilter = cld_filter;
7913
7914         ether_addr_copy(&tunnel_filter->outer_mac,
7915                         (struct ether_addr *)&pfilter->element.outer_mac);
7916         ether_addr_copy(&tunnel_filter->inner_mac,
7917                         (struct ether_addr *)&pfilter->element.inner_mac);
7918
7919         pfilter->element.inner_vlan =
7920                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7921         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7922                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7923                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7924                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7925                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7926                                 &ipv4_addr_le,
7927                                 sizeof(pfilter->element.ipaddr.v4.data));
7928         } else {
7929                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7930                 for (i = 0; i < 4; i++) {
7931                         convert_ipv6[i] =
7932                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7933                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7934                 }
7935                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7936                            &convert_ipv6,
7937                            sizeof(pfilter->element.ipaddr.v6.data));
7938         }
7939
7940         /* check tunneled type */
7941         switch (tunnel_filter->tunnel_type) {
7942         case I40E_TUNNEL_TYPE_VXLAN:
7943                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7944                 break;
7945         case I40E_TUNNEL_TYPE_NVGRE:
7946                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7947                 break;
7948         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7949                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7950                 break;
7951         case I40E_TUNNEL_TYPE_MPLSoUDP:
7952                 if (!pf->mpls_replace_flag) {
7953                         i40e_replace_mpls_l1_filter(pf);
7954                         i40e_replace_mpls_cloud_filter(pf);
7955                         pf->mpls_replace_flag = 1;
7956                 }
7957                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7958                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7959                         teid_le >> 4;
7960                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7961                         (teid_le & 0xF) << 12;
7962                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7963                         0x40;
7964                 big_buffer = 1;
7965                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7966                 break;
7967         case I40E_TUNNEL_TYPE_MPLSoGRE:
7968                 if (!pf->mpls_replace_flag) {
7969                         i40e_replace_mpls_l1_filter(pf);
7970                         i40e_replace_mpls_cloud_filter(pf);
7971                         pf->mpls_replace_flag = 1;
7972                 }
7973                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7974                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7975                         teid_le >> 4;
7976                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7977                         (teid_le & 0xF) << 12;
7978                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7979                         0x0;
7980                 big_buffer = 1;
7981                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7982                 break;
7983         case I40E_TUNNEL_TYPE_GTPC:
7984                 if (!pf->gtp_replace_flag) {
7985                         i40e_replace_gtp_l1_filter(pf);
7986                         i40e_replace_gtp_cloud_filter(pf);
7987                         pf->gtp_replace_flag = 1;
7988                 }
7989                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7990                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7991                         (teid_le >> 16) & 0xFFFF;
7992                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7993                         teid_le & 0xFFFF;
7994                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7995                         0x0;
7996                 big_buffer = 1;
7997                 break;
7998         case I40E_TUNNEL_TYPE_GTPU:
7999                 if (!pf->gtp_replace_flag) {
8000                         i40e_replace_gtp_l1_filter(pf);
8001                         i40e_replace_gtp_cloud_filter(pf);
8002                         pf->gtp_replace_flag = 1;
8003                 }
8004                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8005                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8006                         (teid_le >> 16) & 0xFFFF;
8007                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8008                         teid_le & 0xFFFF;
8009                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8010                         0x0;
8011                 big_buffer = 1;
8012                 break;
8013         case I40E_TUNNEL_TYPE_QINQ:
8014                 if (!pf->qinq_replace_flag) {
8015                         ret = i40e_cloud_filter_qinq_create(pf);
8016                         if (ret < 0)
8017                                 PMD_DRV_LOG(DEBUG,
8018                                             "QinQ tunnel filter already created.");
8019                         pf->qinq_replace_flag = 1;
8020                 }
8021                 /*      Add in the General fields the values of
8022                  *      the Outer and Inner VLAN
8023                  *      Big Buffer should be set, see changes in
8024                  *      i40e_aq_add_cloud_filters
8025                  */
8026                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8027                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8028                 big_buffer = 1;
8029                 break;
8030         default:
8031                 /* Other tunnel types is not supported. */
8032                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8033                 rte_free(cld_filter);
8034                 return -EINVAL;
8035         }
8036
8037         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8038                 pfilter->element.flags =
8039                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8040         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8041                 pfilter->element.flags =
8042                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8043         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8044                 pfilter->element.flags =
8045                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8046         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8047                 pfilter->element.flags =
8048                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8049         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8050                 pfilter->element.flags |=
8051                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8052         else {
8053                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8054                                                 &pfilter->element.flags);
8055                 if (val < 0) {
8056                         rte_free(cld_filter);
8057                         return -EINVAL;
8058                 }
8059         }
8060
8061         pfilter->element.flags |= rte_cpu_to_le_16(
8062                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8063                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8064         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8065         pfilter->element.queue_number =
8066                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8067
8068         if (!tunnel_filter->is_to_vf)
8069                 vsi = pf->main_vsi;
8070         else {
8071                 if (tunnel_filter->vf_id >= pf->vf_num) {
8072                         PMD_DRV_LOG(ERR, "Invalid argument.");
8073                         rte_free(cld_filter);
8074                         return -EINVAL;
8075                 }
8076                 vf = &pf->vfs[tunnel_filter->vf_id];
8077                 vsi = vf->vsi;
8078         }
8079
8080         /* Check if there is the filter in SW list */
8081         memset(&check_filter, 0, sizeof(check_filter));
8082         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8083         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8084         check_filter.vf_id = tunnel_filter->vf_id;
8085         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8086         if (add && node) {
8087                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8088                 rte_free(cld_filter);
8089                 return -EINVAL;
8090         }
8091
8092         if (!add && !node) {
8093                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8094                 rte_free(cld_filter);
8095                 return -EINVAL;
8096         }
8097
8098         if (add) {
8099                 if (big_buffer)
8100                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
8101                                                    vsi->seid, cld_filter, 1);
8102                 else
8103                         ret = i40e_aq_add_cloud_filters(hw,
8104                                         vsi->seid, &cld_filter->element, 1);
8105                 if (ret < 0) {
8106                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8107                         rte_free(cld_filter);
8108                         return -ENOTSUP;
8109                 }
8110                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8111                 if (tunnel == NULL) {
8112                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8113                         rte_free(cld_filter);
8114                         return -ENOMEM;
8115                 }
8116
8117                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8118                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8119                 if (ret < 0)
8120                         rte_free(tunnel);
8121         } else {
8122                 if (big_buffer)
8123                         ret = i40e_aq_remove_cloud_filters_big_buffer(
8124                                 hw, vsi->seid, cld_filter, 1);
8125                 else
8126                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
8127                                                    &cld_filter->element, 1);
8128                 if (ret < 0) {
8129                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8130                         rte_free(cld_filter);
8131                         return -ENOTSUP;
8132                 }
8133                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8134         }
8135
8136         rte_free(cld_filter);
8137         return ret;
8138 }
8139
8140 static int
8141 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8142 {
8143         uint8_t i;
8144
8145         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8146                 if (pf->vxlan_ports[i] == port)
8147                         return i;
8148         }
8149
8150         return -1;
8151 }
8152
8153 static int
8154 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8155 {
8156         int  idx, ret;
8157         uint8_t filter_idx;
8158         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8159
8160         idx = i40e_get_vxlan_port_idx(pf, port);
8161
8162         /* Check if port already exists */
8163         if (idx >= 0) {
8164                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8165                 return -EINVAL;
8166         }
8167
8168         /* Now check if there is space to add the new port */
8169         idx = i40e_get_vxlan_port_idx(pf, 0);
8170         if (idx < 0) {
8171                 PMD_DRV_LOG(ERR,
8172                         "Maximum number of UDP ports reached, not adding port %d",
8173                         port);
8174                 return -ENOSPC;
8175         }
8176
8177         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8178                                         &filter_idx, NULL);
8179         if (ret < 0) {
8180                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8181                 return -1;
8182         }
8183
8184         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8185                          port,  filter_idx);
8186
8187         /* New port: add it and mark its index in the bitmap */
8188         pf->vxlan_ports[idx] = port;
8189         pf->vxlan_bitmap |= (1 << idx);
8190
8191         if (!(pf->flags & I40E_FLAG_VXLAN))
8192                 pf->flags |= I40E_FLAG_VXLAN;
8193
8194         return 0;
8195 }
8196
8197 static int
8198 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8199 {
8200         int idx;
8201         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8202
8203         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8204                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8205                 return -EINVAL;
8206         }
8207
8208         idx = i40e_get_vxlan_port_idx(pf, port);
8209
8210         if (idx < 0) {
8211                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8212                 return -EINVAL;
8213         }
8214
8215         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8216                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8217                 return -1;
8218         }
8219
8220         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8221                         port, idx);
8222
8223         pf->vxlan_ports[idx] = 0;
8224         pf->vxlan_bitmap &= ~(1 << idx);
8225
8226         if (!pf->vxlan_bitmap)
8227                 pf->flags &= ~I40E_FLAG_VXLAN;
8228
8229         return 0;
8230 }
8231
8232 /* Add UDP tunneling port */
8233 static int
8234 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8235                              struct rte_eth_udp_tunnel *udp_tunnel)
8236 {
8237         int ret = 0;
8238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8239
8240         if (udp_tunnel == NULL)
8241                 return -EINVAL;
8242
8243         switch (udp_tunnel->prot_type) {
8244         case RTE_TUNNEL_TYPE_VXLAN:
8245                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8246                 break;
8247
8248         case RTE_TUNNEL_TYPE_GENEVE:
8249         case RTE_TUNNEL_TYPE_TEREDO:
8250                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8251                 ret = -1;
8252                 break;
8253
8254         default:
8255                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8256                 ret = -1;
8257                 break;
8258         }
8259
8260         return ret;
8261 }
8262
8263 /* Remove UDP tunneling port */
8264 static int
8265 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8266                              struct rte_eth_udp_tunnel *udp_tunnel)
8267 {
8268         int ret = 0;
8269         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8270
8271         if (udp_tunnel == NULL)
8272                 return -EINVAL;
8273
8274         switch (udp_tunnel->prot_type) {
8275         case RTE_TUNNEL_TYPE_VXLAN:
8276                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8277                 break;
8278         case RTE_TUNNEL_TYPE_GENEVE:
8279         case RTE_TUNNEL_TYPE_TEREDO:
8280                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8281                 ret = -1;
8282                 break;
8283         default:
8284                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8285                 ret = -1;
8286                 break;
8287         }
8288
8289         return ret;
8290 }
8291
8292 /* Calculate the maximum number of contiguous PF queues that are configured */
8293 static int
8294 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8295 {
8296         struct rte_eth_dev_data *data = pf->dev_data;
8297         int i, num;
8298         struct i40e_rx_queue *rxq;
8299
8300         num = 0;
8301         for (i = 0; i < pf->lan_nb_qps; i++) {
8302                 rxq = data->rx_queues[i];
8303                 if (rxq && rxq->q_set)
8304                         num++;
8305                 else
8306                         break;
8307         }
8308
8309         return num;
8310 }
8311
8312 /* Configure RSS */
8313 static int
8314 i40e_pf_config_rss(struct i40e_pf *pf)
8315 {
8316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8317         struct rte_eth_rss_conf rss_conf;
8318         uint32_t i, lut = 0;
8319         uint16_t j, num;
8320
8321         /*
8322          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8323          * It's necessary to calculate the actual PF queues that are configured.
8324          */
8325         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8326                 num = i40e_pf_calc_configured_queues_num(pf);
8327         else
8328                 num = pf->dev_data->nb_rx_queues;
8329
8330         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8331         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8332                         num);
8333
8334         if (num == 0) {
8335                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8336                 return -ENOTSUP;
8337         }
8338
8339         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8340                 if (j == num)
8341                         j = 0;
8342                 lut = (lut << 8) | (j & ((0x1 <<
8343                         hw->func_caps.rss_table_entry_width) - 1));
8344                 if ((i & 3) == 3)
8345                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8346         }
8347
8348         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8349         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8350                 i40e_pf_disable_rss(pf);
8351                 return 0;
8352         }
8353         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8354                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8355                 /* Random default keys */
8356                 static uint32_t rss_key_default[] = {0x6b793944,
8357                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8358                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8359                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8360
8361                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8362                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8363                                                         sizeof(uint32_t);
8364         }
8365
8366         return i40e_hw_rss_hash_set(pf, &rss_conf);
8367 }
8368
8369 static int
8370 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8371                                struct rte_eth_tunnel_filter_conf *filter)
8372 {
8373         if (pf == NULL || filter == NULL) {
8374                 PMD_DRV_LOG(ERR, "Invalid parameter");
8375                 return -EINVAL;
8376         }
8377
8378         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8379                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8380                 return -EINVAL;
8381         }
8382
8383         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8384                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8385                 return -EINVAL;
8386         }
8387
8388         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8389                 (is_zero_ether_addr(&filter->outer_mac))) {
8390                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8391                 return -EINVAL;
8392         }
8393
8394         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8395                 (is_zero_ether_addr(&filter->inner_mac))) {
8396                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8397                 return -EINVAL;
8398         }
8399
8400         return 0;
8401 }
8402
8403 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8404 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8405 static int
8406 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8407 {
8408         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8409         uint32_t val, reg;
8410         int ret = -EINVAL;
8411
8412         if (pf->support_multi_driver) {
8413                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8414                 return -ENOTSUP;
8415         }
8416
8417         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8418         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8419
8420         if (len == 3) {
8421                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8422         } else if (len == 4) {
8423                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8424         } else {
8425                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8426                 return ret;
8427         }
8428
8429         if (reg != val) {
8430                 ret = i40e_aq_debug_write_global_register(hw,
8431                                                    I40E_GL_PRS_FVBM(2),
8432                                                    reg, NULL);
8433                 if (ret != 0)
8434                         return ret;
8435                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8436                             "with value 0x%08x",
8437                             I40E_GL_PRS_FVBM(2), reg);
8438         } else {
8439                 ret = 0;
8440         }
8441         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8442                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8443
8444         return ret;
8445 }
8446
8447 static int
8448 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8449 {
8450         int ret = -EINVAL;
8451
8452         if (!hw || !cfg)
8453                 return -EINVAL;
8454
8455         switch (cfg->cfg_type) {
8456         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8457                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8458                 break;
8459         default:
8460                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8461                 break;
8462         }
8463
8464         return ret;
8465 }
8466
8467 static int
8468 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8469                                enum rte_filter_op filter_op,
8470                                void *arg)
8471 {
8472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473         int ret = I40E_ERR_PARAM;
8474
8475         switch (filter_op) {
8476         case RTE_ETH_FILTER_SET:
8477                 ret = i40e_dev_global_config_set(hw,
8478                         (struct rte_eth_global_cfg *)arg);
8479                 break;
8480         default:
8481                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8482                 break;
8483         }
8484
8485         return ret;
8486 }
8487
8488 static int
8489 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8490                           enum rte_filter_op filter_op,
8491                           void *arg)
8492 {
8493         struct rte_eth_tunnel_filter_conf *filter;
8494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8495         int ret = I40E_SUCCESS;
8496
8497         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8498
8499         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8500                 return I40E_ERR_PARAM;
8501
8502         switch (filter_op) {
8503         case RTE_ETH_FILTER_NOP:
8504                 if (!(pf->flags & I40E_FLAG_VXLAN))
8505                         ret = I40E_NOT_SUPPORTED;
8506                 break;
8507         case RTE_ETH_FILTER_ADD:
8508                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8509                 break;
8510         case RTE_ETH_FILTER_DELETE:
8511                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8512                 break;
8513         default:
8514                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8515                 ret = I40E_ERR_PARAM;
8516                 break;
8517         }
8518
8519         return ret;
8520 }
8521
8522 static int
8523 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8524 {
8525         int ret = 0;
8526         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8527
8528         /* RSS setup */
8529         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8530                 ret = i40e_pf_config_rss(pf);
8531         else
8532                 i40e_pf_disable_rss(pf);
8533
8534         return ret;
8535 }
8536
8537 /* Get the symmetric hash enable configurations per port */
8538 static void
8539 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8540 {
8541         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8542
8543         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8544 }
8545
8546 /* Set the symmetric hash enable configurations per port */
8547 static void
8548 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8549 {
8550         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8551
8552         if (enable > 0) {
8553                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8554                         PMD_DRV_LOG(INFO,
8555                                 "Symmetric hash has already been enabled");
8556                         return;
8557                 }
8558                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8559         } else {
8560                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8561                         PMD_DRV_LOG(INFO,
8562                                 "Symmetric hash has already been disabled");
8563                         return;
8564                 }
8565                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8566         }
8567         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8568         I40E_WRITE_FLUSH(hw);
8569 }
8570
8571 /*
8572  * Get global configurations of hash function type and symmetric hash enable
8573  * per flow type (pctype). Note that global configuration means it affects all
8574  * the ports on the same NIC.
8575  */
8576 static int
8577 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8578                                    struct rte_eth_hash_global_conf *g_cfg)
8579 {
8580         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8581         uint32_t reg;
8582         uint16_t i, j;
8583
8584         memset(g_cfg, 0, sizeof(*g_cfg));
8585         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8586         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8587                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8588         else
8589                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8590         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8591                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8592
8593         /*
8594          * As i40e supports less than 64 flow types, only first 64 bits need to
8595          * be checked.
8596          */
8597         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8598                 g_cfg->valid_bit_mask[i] = 0ULL;
8599                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8600         }
8601
8602         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8603
8604         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8605                 if (!adapter->pctypes_tbl[i])
8606                         continue;
8607                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8608                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8609                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8610                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8611                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8612                                         g_cfg->sym_hash_enable_mask[0] |=
8613                                                                 (1ULL << i);
8614                                 }
8615                         }
8616                 }
8617         }
8618
8619         return 0;
8620 }
8621
8622 static int
8623 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8624                               const struct rte_eth_hash_global_conf *g_cfg)
8625 {
8626         uint32_t i;
8627         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8628
8629         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8630                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8631                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8632                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8633                                                 g_cfg->hash_func);
8634                 return -EINVAL;
8635         }
8636
8637         /*
8638          * As i40e supports less than 64 flow types, only first 64 bits need to
8639          * be checked.
8640          */
8641         mask0 = g_cfg->valid_bit_mask[0];
8642         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8643                 if (i == 0) {
8644                         /* Check if any unsupported flow type configured */
8645                         if ((mask0 | i40e_mask) ^ i40e_mask)
8646                                 goto mask_err;
8647                 } else {
8648                         if (g_cfg->valid_bit_mask[i])
8649                                 goto mask_err;
8650                 }
8651         }
8652
8653         return 0;
8654
8655 mask_err:
8656         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8657
8658         return -EINVAL;
8659 }
8660
8661 /*
8662  * Set global configurations of hash function type and symmetric hash enable
8663  * per flow type (pctype). Note any modifying global configuration will affect
8664  * all the ports on the same NIC.
8665  */
8666 static int
8667 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8668                                    struct rte_eth_hash_global_conf *g_cfg)
8669 {
8670         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8671         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8672         int ret;
8673         uint16_t i, j;
8674         uint32_t reg;
8675         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8676
8677         if (pf->support_multi_driver) {
8678                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8679                 return -ENOTSUP;
8680         }
8681
8682         /* Check the input parameters */
8683         ret = i40e_hash_global_config_check(adapter, g_cfg);
8684         if (ret < 0)
8685                 return ret;
8686
8687         /*
8688          * As i40e supports less than 64 flow types, only first 64 bits need to
8689          * be configured.
8690          */
8691         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8692                 if (mask0 & (1UL << i)) {
8693                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8694                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8695
8696                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8697                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8698                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8699                                         i40e_write_global_rx_ctl(hw,
8700                                                           I40E_GLQF_HSYM(j),
8701                                                           reg);
8702                         }
8703                 }
8704         }
8705
8706         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8707         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8708                 /* Toeplitz */
8709                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8710                         PMD_DRV_LOG(DEBUG,
8711                                 "Hash function already set to Toeplitz");
8712                         goto out;
8713                 }
8714                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8715         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8716                 /* Simple XOR */
8717                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8718                         PMD_DRV_LOG(DEBUG,
8719                                 "Hash function already set to Simple XOR");
8720                         goto out;
8721                 }
8722                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8723         } else
8724                 /* Use the default, and keep it as it is */
8725                 goto out;
8726
8727         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8728
8729 out:
8730         I40E_WRITE_FLUSH(hw);
8731
8732         return 0;
8733 }
8734
8735 /**
8736  * Valid input sets for hash and flow director filters per PCTYPE
8737  */
8738 static uint64_t
8739 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8740                 enum rte_filter_type filter)
8741 {
8742         uint64_t valid;
8743
8744         static const uint64_t valid_hash_inset_table[] = {
8745                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8746                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8747                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8748                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8749                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8750                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8751                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8752                         I40E_INSET_FLEX_PAYLOAD,
8753                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8754                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8755                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8756                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8757                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8758                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8759                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8760                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8761                         I40E_INSET_FLEX_PAYLOAD,
8762                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8763                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8764                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8765                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8766                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8767                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8768                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8770                         I40E_INSET_FLEX_PAYLOAD,
8771                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8772                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8773                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8774                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8775                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8776                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8777                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8779                         I40E_INSET_FLEX_PAYLOAD,
8780                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8781                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8782                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8783                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8784                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8785                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8786                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8787                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8788                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8789                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8790                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8791                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8792                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8793                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8794                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8795                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8796                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8797                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8798                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8799                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8800                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8801                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8802                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8803                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8804                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8805                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8806                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8807                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8808                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8809                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8810                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8811                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8812                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8813                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8814                         I40E_INSET_FLEX_PAYLOAD,
8815                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8816                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8817                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8818                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8819                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8820                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8821                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8822                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8823                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8824                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8825                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8826                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8827                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8828                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8829                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8830                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8831                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8832                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8833                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8834                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8835                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8836                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8837                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8838                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8839                         I40E_INSET_FLEX_PAYLOAD,
8840                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8841                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8842                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8843                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8844                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8845                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8846                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8847                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8848                         I40E_INSET_FLEX_PAYLOAD,
8849                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8850                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8851                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8852                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8853                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8854                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8855                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8856                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8857                         I40E_INSET_FLEX_PAYLOAD,
8858                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8859                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8860                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8861                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8862                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8863                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8864                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8865                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8866                         I40E_INSET_FLEX_PAYLOAD,
8867                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8868                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8869                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8870                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8871                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8872                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8873                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8874                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8875                         I40E_INSET_FLEX_PAYLOAD,
8876                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8877                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8878                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8879                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8880                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8881                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8882                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8883                         I40E_INSET_FLEX_PAYLOAD,
8884                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8885                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8886                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8887                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8888                         I40E_INSET_FLEX_PAYLOAD,
8889         };
8890
8891         /**
8892          * Flow director supports only fields defined in
8893          * union rte_eth_fdir_flow.
8894          */
8895         static const uint64_t valid_fdir_inset_table[] = {
8896                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8897                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8898                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8899                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8900                 I40E_INSET_IPV4_TTL,
8901                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8902                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8903                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8904                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8905                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8906                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8907                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8908                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8909                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8910                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8911                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8912                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8913                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8914                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8915                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8916                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8917                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8918                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8919                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8920                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8921                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8922                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8923                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8924                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8925                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8926                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8927                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8928                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8929                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8930                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8931                 I40E_INSET_SCTP_VT,
8932                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8933                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8934                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8935                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8936                 I40E_INSET_IPV4_TTL,
8937                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8938                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8939                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8940                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8941                 I40E_INSET_IPV6_HOP_LIMIT,
8942                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8943                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8944                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8945                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8946                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8947                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8948                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8949                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8950                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8951                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8952                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8953                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8954                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8955                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8956                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8957                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8958                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8959                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8960                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8961                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8962                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8963                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8964                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8965                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8966                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8967                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8968                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8969                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8970                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8971                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8972                 I40E_INSET_SCTP_VT,
8973                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8974                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8975                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8976                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8977                 I40E_INSET_IPV6_HOP_LIMIT,
8978                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8979                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8980                 I40E_INSET_LAST_ETHER_TYPE,
8981         };
8982
8983         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8984                 return 0;
8985         if (filter == RTE_ETH_FILTER_HASH)
8986                 valid = valid_hash_inset_table[pctype];
8987         else
8988                 valid = valid_fdir_inset_table[pctype];
8989
8990         return valid;
8991 }
8992
8993 /**
8994  * Validate if the input set is allowed for a specific PCTYPE
8995  */
8996 int
8997 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8998                 enum rte_filter_type filter, uint64_t inset)
8999 {
9000         uint64_t valid;
9001
9002         valid = i40e_get_valid_input_set(pctype, filter);
9003         if (inset & (~valid))
9004                 return -EINVAL;
9005
9006         return 0;
9007 }
9008
9009 /* default input set fields combination per pctype */
9010 uint64_t
9011 i40e_get_default_input_set(uint16_t pctype)
9012 {
9013         static const uint64_t default_inset_table[] = {
9014                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9015                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9016                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9017                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9018                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9019                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9020                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9021                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9022                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9023                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9024                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9025                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9026                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9027                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9028                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9029                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9030                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9031                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9032                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9033                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9034                         I40E_INSET_SCTP_VT,
9035                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9036                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9037                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9038                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9039                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9040                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9041                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9042                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9043                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9044                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9045                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9046                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9047                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9048                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9049                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9050                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9051                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9052                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9053                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9054                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9055                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9056                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9057                         I40E_INSET_SCTP_VT,
9058                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9059                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9060                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9061                         I40E_INSET_LAST_ETHER_TYPE,
9062         };
9063
9064         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9065                 return 0;
9066
9067         return default_inset_table[pctype];
9068 }
9069
9070 /**
9071  * Parse the input set from index to logical bit masks
9072  */
9073 static int
9074 i40e_parse_input_set(uint64_t *inset,
9075                      enum i40e_filter_pctype pctype,
9076                      enum rte_eth_input_set_field *field,
9077                      uint16_t size)
9078 {
9079         uint16_t i, j;
9080         int ret = -EINVAL;
9081
9082         static const struct {
9083                 enum rte_eth_input_set_field field;
9084                 uint64_t inset;
9085         } inset_convert_table[] = {
9086                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9087                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9088                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9089                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9090                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9091                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9092                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9093                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9094                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9095                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9096                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9097                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9098                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9099                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9100                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9101                         I40E_INSET_IPV6_NEXT_HDR},
9102                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9103                         I40E_INSET_IPV6_HOP_LIMIT},
9104                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9105                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9106                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9107                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9108                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9109                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9110                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9111                         I40E_INSET_SCTP_VT},
9112                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9113                         I40E_INSET_TUNNEL_DMAC},
9114                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9115                         I40E_INSET_VLAN_TUNNEL},
9116                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9117                         I40E_INSET_TUNNEL_ID},
9118                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9119                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9120                         I40E_INSET_FLEX_PAYLOAD_W1},
9121                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9122                         I40E_INSET_FLEX_PAYLOAD_W2},
9123                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9124                         I40E_INSET_FLEX_PAYLOAD_W3},
9125                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9126                         I40E_INSET_FLEX_PAYLOAD_W4},
9127                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9128                         I40E_INSET_FLEX_PAYLOAD_W5},
9129                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9130                         I40E_INSET_FLEX_PAYLOAD_W6},
9131                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9132                         I40E_INSET_FLEX_PAYLOAD_W7},
9133                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9134                         I40E_INSET_FLEX_PAYLOAD_W8},
9135         };
9136
9137         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9138                 return ret;
9139
9140         /* Only one item allowed for default or all */
9141         if (size == 1) {
9142                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9143                         *inset = i40e_get_default_input_set(pctype);
9144                         return 0;
9145                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9146                         *inset = I40E_INSET_NONE;
9147                         return 0;
9148                 }
9149         }
9150
9151         for (i = 0, *inset = 0; i < size; i++) {
9152                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9153                         if (field[i] == inset_convert_table[j].field) {
9154                                 *inset |= inset_convert_table[j].inset;
9155                                 break;
9156                         }
9157                 }
9158
9159                 /* It contains unsupported input set, return immediately */
9160                 if (j == RTE_DIM(inset_convert_table))
9161                         return ret;
9162         }
9163
9164         return 0;
9165 }
9166
9167 /**
9168  * Translate the input set from bit masks to register aware bit masks
9169  * and vice versa
9170  */
9171 uint64_t
9172 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9173 {
9174         uint64_t val = 0;
9175         uint16_t i;
9176
9177         struct inset_map {
9178                 uint64_t inset;
9179                 uint64_t inset_reg;
9180         };
9181
9182         static const struct inset_map inset_map_common[] = {
9183                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9184                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9185                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9186                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9187                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9188                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9189                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9190                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9191                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9192                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9193                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9194                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9195                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9196                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9197                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9198                 {I40E_INSET_TUNNEL_DMAC,
9199                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9200                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9201                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9202                 {I40E_INSET_TUNNEL_SRC_PORT,
9203                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9204                 {I40E_INSET_TUNNEL_DST_PORT,
9205                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9206                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9207                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9208                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9209                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9210                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9211                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9212                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9213                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9214                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9215         };
9216
9217     /* some different registers map in x722*/
9218         static const struct inset_map inset_map_diff_x722[] = {
9219                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9220                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9221                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9222                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9223         };
9224
9225         static const struct inset_map inset_map_diff_not_x722[] = {
9226                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9227                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9228                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9229                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9230         };
9231
9232         if (input == 0)
9233                 return val;
9234
9235         /* Translate input set to register aware inset */
9236         if (type == I40E_MAC_X722) {
9237                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9238                         if (input & inset_map_diff_x722[i].inset)
9239                                 val |= inset_map_diff_x722[i].inset_reg;
9240                 }
9241         } else {
9242                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9243                         if (input & inset_map_diff_not_x722[i].inset)
9244                                 val |= inset_map_diff_not_x722[i].inset_reg;
9245                 }
9246         }
9247
9248         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9249                 if (input & inset_map_common[i].inset)
9250                         val |= inset_map_common[i].inset_reg;
9251         }
9252
9253         return val;
9254 }
9255
9256 int
9257 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9258 {
9259         uint8_t i, idx = 0;
9260         uint64_t inset_need_mask = inset;
9261
9262         static const struct {
9263                 uint64_t inset;
9264                 uint32_t mask;
9265         } inset_mask_map[] = {
9266                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9267                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9268                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9269                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9270                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9271                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9272                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9273                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9274         };
9275
9276         if (!inset || !mask || !nb_elem)
9277                 return 0;
9278
9279         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9280                 /* Clear the inset bit, if no MASK is required,
9281                  * for example proto + ttl
9282                  */
9283                 if ((inset & inset_mask_map[i].inset) ==
9284                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9285                         inset_need_mask &= ~inset_mask_map[i].inset;
9286                 if (!inset_need_mask)
9287                         return 0;
9288         }
9289         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9290                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9291                     inset_mask_map[i].inset) {
9292                         if (idx >= nb_elem) {
9293                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9294                                 return -EINVAL;
9295                         }
9296                         mask[idx] = inset_mask_map[i].mask;
9297                         idx++;
9298                 }
9299         }
9300
9301         return idx;
9302 }
9303
9304 void
9305 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9306 {
9307         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9308
9309         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9310         if (reg != val)
9311                 i40e_write_rx_ctl(hw, addr, val);
9312         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9313                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9314 }
9315
9316 void
9317 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9318 {
9319         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9320         struct rte_eth_dev *dev;
9321
9322         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9323         if (reg != val) {
9324                 i40e_write_rx_ctl(hw, addr, val);
9325                 PMD_DRV_LOG(WARNING,
9326                             "i40e device %s changed global register [0x%08x]."
9327                             " original: 0x%08x, new: 0x%08x",
9328                             dev->device->name, addr, reg,
9329                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9330         }
9331 }
9332
9333 static void
9334 i40e_filter_input_set_init(struct i40e_pf *pf)
9335 {
9336         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9337         enum i40e_filter_pctype pctype;
9338         uint64_t input_set, inset_reg;
9339         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9340         int num, i;
9341         uint16_t flow_type;
9342
9343         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9344              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9345                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9346
9347                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9348                         continue;
9349
9350                 input_set = i40e_get_default_input_set(pctype);
9351
9352                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9353                                                    I40E_INSET_MASK_NUM_REG);
9354                 if (num < 0)
9355                         return;
9356                 if (pf->support_multi_driver && num > 0) {
9357                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9358                         return;
9359                 }
9360                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9361                                         input_set);
9362
9363                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9364                                       (uint32_t)(inset_reg & UINT32_MAX));
9365                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9366                                      (uint32_t)((inset_reg >>
9367                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9368                 if (!pf->support_multi_driver) {
9369                         i40e_check_write_global_reg(hw,
9370                                             I40E_GLQF_HASH_INSET(0, pctype),
9371                                             (uint32_t)(inset_reg & UINT32_MAX));
9372                         i40e_check_write_global_reg(hw,
9373                                              I40E_GLQF_HASH_INSET(1, pctype),
9374                                              (uint32_t)((inset_reg >>
9375                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9376
9377                         for (i = 0; i < num; i++) {
9378                                 i40e_check_write_global_reg(hw,
9379                                                     I40E_GLQF_FD_MSK(i, pctype),
9380                                                     mask_reg[i]);
9381                                 i40e_check_write_global_reg(hw,
9382                                                   I40E_GLQF_HASH_MSK(i, pctype),
9383                                                   mask_reg[i]);
9384                         }
9385                         /*clear unused mask registers of the pctype */
9386                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9387                                 i40e_check_write_global_reg(hw,
9388                                                     I40E_GLQF_FD_MSK(i, pctype),
9389                                                     0);
9390                                 i40e_check_write_global_reg(hw,
9391                                                   I40E_GLQF_HASH_MSK(i, pctype),
9392                                                   0);
9393                         }
9394                 } else {
9395                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9396                 }
9397                 I40E_WRITE_FLUSH(hw);
9398
9399                 /* store the default input set */
9400                 if (!pf->support_multi_driver)
9401                         pf->hash_input_set[pctype] = input_set;
9402                 pf->fdir.input_set[pctype] = input_set;
9403         }
9404 }
9405
9406 int
9407 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9408                          struct rte_eth_input_set_conf *conf)
9409 {
9410         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9411         enum i40e_filter_pctype pctype;
9412         uint64_t input_set, inset_reg = 0;
9413         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9414         int ret, i, num;
9415
9416         if (!conf) {
9417                 PMD_DRV_LOG(ERR, "Invalid pointer");
9418                 return -EFAULT;
9419         }
9420         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9421             conf->op != RTE_ETH_INPUT_SET_ADD) {
9422                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9423                 return -EINVAL;
9424         }
9425
9426         if (pf->support_multi_driver) {
9427                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9428                 return -ENOTSUP;
9429         }
9430
9431         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9432         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9433                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9434                 return -EINVAL;
9435         }
9436
9437         if (hw->mac.type == I40E_MAC_X722) {
9438                 /* get translated pctype value in fd pctype register */
9439                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9440                         I40E_GLQF_FD_PCTYPES((int)pctype));
9441         }
9442
9443         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9444                                    conf->inset_size);
9445         if (ret) {
9446                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9447                 return -EINVAL;
9448         }
9449
9450         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9451                 /* get inset value in register */
9452                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9453                 inset_reg <<= I40E_32_BIT_WIDTH;
9454                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9455                 input_set |= pf->hash_input_set[pctype];
9456         }
9457         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9458                                            I40E_INSET_MASK_NUM_REG);
9459         if (num < 0)
9460                 return -EINVAL;
9461
9462         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9463
9464         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9465                                     (uint32_t)(inset_reg & UINT32_MAX));
9466         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9467                                     (uint32_t)((inset_reg >>
9468                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9469
9470         for (i = 0; i < num; i++)
9471                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9472                                             mask_reg[i]);
9473         /*clear unused mask registers of the pctype */
9474         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9475                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9476                                             0);
9477         I40E_WRITE_FLUSH(hw);
9478
9479         pf->hash_input_set[pctype] = input_set;
9480         return 0;
9481 }
9482
9483 int
9484 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9485                          struct rte_eth_input_set_conf *conf)
9486 {
9487         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9488         enum i40e_filter_pctype pctype;
9489         uint64_t input_set, inset_reg = 0;
9490         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9491         int ret, i, num;
9492
9493         if (!hw || !conf) {
9494                 PMD_DRV_LOG(ERR, "Invalid pointer");
9495                 return -EFAULT;
9496         }
9497         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9498             conf->op != RTE_ETH_INPUT_SET_ADD) {
9499                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9500                 return -EINVAL;
9501         }
9502
9503         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9504
9505         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9506                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9507                 return -EINVAL;
9508         }
9509
9510         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9511                                    conf->inset_size);
9512         if (ret) {
9513                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9514                 return -EINVAL;
9515         }
9516
9517         /* get inset value in register */
9518         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9519         inset_reg <<= I40E_32_BIT_WIDTH;
9520         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9521
9522         /* Can not change the inset reg for flex payload for fdir,
9523          * it is done by writing I40E_PRTQF_FD_FLXINSET
9524          * in i40e_set_flex_mask_on_pctype.
9525          */
9526         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9527                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9528         else
9529                 input_set |= pf->fdir.input_set[pctype];
9530         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9531                                            I40E_INSET_MASK_NUM_REG);
9532         if (num < 0)
9533                 return -EINVAL;
9534         if (pf->support_multi_driver && num > 0) {
9535                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9536                 return -ENOTSUP;
9537         }
9538
9539         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9540
9541         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9542                               (uint32_t)(inset_reg & UINT32_MAX));
9543         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9544                              (uint32_t)((inset_reg >>
9545                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9546
9547         if (!pf->support_multi_driver) {
9548                 for (i = 0; i < num; i++)
9549                         i40e_check_write_global_reg(hw,
9550                                                     I40E_GLQF_FD_MSK(i, pctype),
9551                                                     mask_reg[i]);
9552                 /*clear unused mask registers of the pctype */
9553                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9554                         i40e_check_write_global_reg(hw,
9555                                                     I40E_GLQF_FD_MSK(i, pctype),
9556                                                     0);
9557         } else {
9558                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9559         }
9560         I40E_WRITE_FLUSH(hw);
9561
9562         pf->fdir.input_set[pctype] = input_set;
9563         return 0;
9564 }
9565
9566 static int
9567 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9568 {
9569         int ret = 0;
9570
9571         if (!hw || !info) {
9572                 PMD_DRV_LOG(ERR, "Invalid pointer");
9573                 return -EFAULT;
9574         }
9575
9576         switch (info->info_type) {
9577         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9578                 i40e_get_symmetric_hash_enable_per_port(hw,
9579                                         &(info->info.enable));
9580                 break;
9581         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9582                 ret = i40e_get_hash_filter_global_config(hw,
9583                                 &(info->info.global_conf));
9584                 break;
9585         default:
9586                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9587                                                         info->info_type);
9588                 ret = -EINVAL;
9589                 break;
9590         }
9591
9592         return ret;
9593 }
9594
9595 static int
9596 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9597 {
9598         int ret = 0;
9599
9600         if (!hw || !info) {
9601                 PMD_DRV_LOG(ERR, "Invalid pointer");
9602                 return -EFAULT;
9603         }
9604
9605         switch (info->info_type) {
9606         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9607                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9608                 break;
9609         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9610                 ret = i40e_set_hash_filter_global_config(hw,
9611                                 &(info->info.global_conf));
9612                 break;
9613         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9614                 ret = i40e_hash_filter_inset_select(hw,
9615                                                &(info->info.input_set_conf));
9616                 break;
9617
9618         default:
9619                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9620                                                         info->info_type);
9621                 ret = -EINVAL;
9622                 break;
9623         }
9624
9625         return ret;
9626 }
9627
9628 /* Operations for hash function */
9629 static int
9630 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9631                       enum rte_filter_op filter_op,
9632                       void *arg)
9633 {
9634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9635         int ret = 0;
9636
9637         switch (filter_op) {
9638         case RTE_ETH_FILTER_NOP:
9639                 break;
9640         case RTE_ETH_FILTER_GET:
9641                 ret = i40e_hash_filter_get(hw,
9642                         (struct rte_eth_hash_filter_info *)arg);
9643                 break;
9644         case RTE_ETH_FILTER_SET:
9645                 ret = i40e_hash_filter_set(hw,
9646                         (struct rte_eth_hash_filter_info *)arg);
9647                 break;
9648         default:
9649                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9650                                                                 filter_op);
9651                 ret = -ENOTSUP;
9652                 break;
9653         }
9654
9655         return ret;
9656 }
9657
9658 /* Convert ethertype filter structure */
9659 static int
9660 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9661                               struct i40e_ethertype_filter *filter)
9662 {
9663         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9664         filter->input.ether_type = input->ether_type;
9665         filter->flags = input->flags;
9666         filter->queue = input->queue;
9667
9668         return 0;
9669 }
9670
9671 /* Check if there exists the ehtertype filter */
9672 struct i40e_ethertype_filter *
9673 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9674                                 const struct i40e_ethertype_filter_input *input)
9675 {
9676         int ret;
9677
9678         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9679         if (ret < 0)
9680                 return NULL;
9681
9682         return ethertype_rule->hash_map[ret];
9683 }
9684
9685 /* Add ethertype filter in SW list */
9686 static int
9687 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9688                                 struct i40e_ethertype_filter *filter)
9689 {
9690         struct i40e_ethertype_rule *rule = &pf->ethertype;
9691         int ret;
9692
9693         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9694         if (ret < 0) {
9695                 PMD_DRV_LOG(ERR,
9696                             "Failed to insert ethertype filter"
9697                             " to hash table %d!",
9698                             ret);
9699                 return ret;
9700         }
9701         rule->hash_map[ret] = filter;
9702
9703         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9704
9705         return 0;
9706 }
9707
9708 /* Delete ethertype filter in SW list */
9709 int
9710 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9711                              struct i40e_ethertype_filter_input *input)
9712 {
9713         struct i40e_ethertype_rule *rule = &pf->ethertype;
9714         struct i40e_ethertype_filter *filter;
9715         int ret;
9716
9717         ret = rte_hash_del_key(rule->hash_table, input);
9718         if (ret < 0) {
9719                 PMD_DRV_LOG(ERR,
9720                             "Failed to delete ethertype filter"
9721                             " to hash table %d!",
9722                             ret);
9723                 return ret;
9724         }
9725         filter = rule->hash_map[ret];
9726         rule->hash_map[ret] = NULL;
9727
9728         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9729         rte_free(filter);
9730
9731         return 0;
9732 }
9733
9734 /*
9735  * Configure ethertype filter, which can director packet by filtering
9736  * with mac address and ether_type or only ether_type
9737  */
9738 int
9739 i40e_ethertype_filter_set(struct i40e_pf *pf,
9740                         struct rte_eth_ethertype_filter *filter,
9741                         bool add)
9742 {
9743         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9744         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9745         struct i40e_ethertype_filter *ethertype_filter, *node;
9746         struct i40e_ethertype_filter check_filter;
9747         struct i40e_control_filter_stats stats;
9748         uint16_t flags = 0;
9749         int ret;
9750
9751         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9752                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9753                 return -EINVAL;
9754         }
9755         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9756                 filter->ether_type == ETHER_TYPE_IPv6) {
9757                 PMD_DRV_LOG(ERR,
9758                         "unsupported ether_type(0x%04x) in control packet filter.",
9759                         filter->ether_type);
9760                 return -EINVAL;
9761         }
9762         if (filter->ether_type == ETHER_TYPE_VLAN)
9763                 PMD_DRV_LOG(WARNING,
9764                         "filter vlan ether_type in first tag is not supported.");
9765
9766         /* Check if there is the filter in SW list */
9767         memset(&check_filter, 0, sizeof(check_filter));
9768         i40e_ethertype_filter_convert(filter, &check_filter);
9769         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9770                                                &check_filter.input);
9771         if (add && node) {
9772                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9773                 return -EINVAL;
9774         }
9775
9776         if (!add && !node) {
9777                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9778                 return -EINVAL;
9779         }
9780
9781         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9782                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9783         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9784                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9785         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9786
9787         memset(&stats, 0, sizeof(stats));
9788         ret = i40e_aq_add_rem_control_packet_filter(hw,
9789                         filter->mac_addr.addr_bytes,
9790                         filter->ether_type, flags,
9791                         pf->main_vsi->seid,
9792                         filter->queue, add, &stats, NULL);
9793
9794         PMD_DRV_LOG(INFO,
9795                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9796                 ret, stats.mac_etype_used, stats.etype_used,
9797                 stats.mac_etype_free, stats.etype_free);
9798         if (ret < 0)
9799                 return -ENOSYS;
9800
9801         /* Add or delete a filter in SW list */
9802         if (add) {
9803                 ethertype_filter = rte_zmalloc("ethertype_filter",
9804                                        sizeof(*ethertype_filter), 0);
9805                 if (ethertype_filter == NULL) {
9806                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9807                         return -ENOMEM;
9808                 }
9809
9810                 rte_memcpy(ethertype_filter, &check_filter,
9811                            sizeof(check_filter));
9812                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9813                 if (ret < 0)
9814                         rte_free(ethertype_filter);
9815         } else {
9816                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9817         }
9818
9819         return ret;
9820 }
9821
9822 /*
9823  * Handle operations for ethertype filter.
9824  */
9825 static int
9826 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9827                                 enum rte_filter_op filter_op,
9828                                 void *arg)
9829 {
9830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9831         int ret = 0;
9832
9833         if (filter_op == RTE_ETH_FILTER_NOP)
9834                 return ret;
9835
9836         if (arg == NULL) {
9837                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9838                             filter_op);
9839                 return -EINVAL;
9840         }
9841
9842         switch (filter_op) {
9843         case RTE_ETH_FILTER_ADD:
9844                 ret = i40e_ethertype_filter_set(pf,
9845                         (struct rte_eth_ethertype_filter *)arg,
9846                         TRUE);
9847                 break;
9848         case RTE_ETH_FILTER_DELETE:
9849                 ret = i40e_ethertype_filter_set(pf,
9850                         (struct rte_eth_ethertype_filter *)arg,
9851                         FALSE);
9852                 break;
9853         default:
9854                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9855                 ret = -ENOSYS;
9856                 break;
9857         }
9858         return ret;
9859 }
9860
9861 static int
9862 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9863                      enum rte_filter_type filter_type,
9864                      enum rte_filter_op filter_op,
9865                      void *arg)
9866 {
9867         int ret = 0;
9868
9869         if (dev == NULL)
9870                 return -EINVAL;
9871
9872         switch (filter_type) {
9873         case RTE_ETH_FILTER_NONE:
9874                 /* For global configuration */
9875                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9876                 break;
9877         case RTE_ETH_FILTER_HASH:
9878                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9879                 break;
9880         case RTE_ETH_FILTER_MACVLAN:
9881                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9882                 break;
9883         case RTE_ETH_FILTER_ETHERTYPE:
9884                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9885                 break;
9886         case RTE_ETH_FILTER_TUNNEL:
9887                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9888                 break;
9889         case RTE_ETH_FILTER_FDIR:
9890                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9891                 break;
9892         case RTE_ETH_FILTER_GENERIC:
9893                 if (filter_op != RTE_ETH_FILTER_GET)
9894                         return -EINVAL;
9895                 *(const void **)arg = &i40e_flow_ops;
9896                 break;
9897         default:
9898                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9899                                                         filter_type);
9900                 ret = -EINVAL;
9901                 break;
9902         }
9903
9904         return ret;
9905 }
9906
9907 /*
9908  * Check and enable Extended Tag.
9909  * Enabling Extended Tag is important for 40G performance.
9910  */
9911 static void
9912 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9913 {
9914         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9915         uint32_t buf = 0;
9916         int ret;
9917
9918         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9919                                       PCI_DEV_CAP_REG);
9920         if (ret < 0) {
9921                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9922                             PCI_DEV_CAP_REG);
9923                 return;
9924         }
9925         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9926                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9927                 return;
9928         }
9929
9930         buf = 0;
9931         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9932                                       PCI_DEV_CTRL_REG);
9933         if (ret < 0) {
9934                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9935                             PCI_DEV_CTRL_REG);
9936                 return;
9937         }
9938         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9939                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9940                 return;
9941         }
9942         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9943         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9944                                        PCI_DEV_CTRL_REG);
9945         if (ret < 0) {
9946                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9947                             PCI_DEV_CTRL_REG);
9948                 return;
9949         }
9950 }
9951
9952 /*
9953  * As some registers wouldn't be reset unless a global hardware reset,
9954  * hardware initialization is needed to put those registers into an
9955  * expected initial state.
9956  */
9957 static void
9958 i40e_hw_init(struct rte_eth_dev *dev)
9959 {
9960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9961
9962         i40e_enable_extended_tag(dev);
9963
9964         /* clear the PF Queue Filter control register */
9965         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9966
9967         /* Disable symmetric hash per port */
9968         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9969 }
9970
9971 /*
9972  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9973  * however this function will return only one highest pctype index,
9974  * which is not quite correct. This is known problem of i40e driver
9975  * and needs to be fixed later.
9976  */
9977 enum i40e_filter_pctype
9978 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9979 {
9980         int i;
9981         uint64_t pctype_mask;
9982
9983         if (flow_type < I40E_FLOW_TYPE_MAX) {
9984                 pctype_mask = adapter->pctypes_tbl[flow_type];
9985                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9986                         if (pctype_mask & (1ULL << i))
9987                                 return (enum i40e_filter_pctype)i;
9988                 }
9989         }
9990         return I40E_FILTER_PCTYPE_INVALID;
9991 }
9992
9993 uint16_t
9994 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9995                         enum i40e_filter_pctype pctype)
9996 {
9997         uint16_t flowtype;
9998         uint64_t pctype_mask = 1ULL << pctype;
9999
10000         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10001              flowtype++) {
10002                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10003                         return flowtype;
10004         }
10005
10006         return RTE_ETH_FLOW_UNKNOWN;
10007 }
10008
10009 /*
10010  * On X710, performance number is far from the expectation on recent firmware
10011  * versions; on XL710, performance number is also far from the expectation on
10012  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10013  * mode is enabled and port MAC address is equal to the packet destination MAC
10014  * address. The fix for this issue may not be integrated in the following
10015  * firmware version. So the workaround in software driver is needed. It needs
10016  * to modify the initial values of 3 internal only registers for both X710 and
10017  * XL710. Note that the values for X710 or XL710 could be different, and the
10018  * workaround can be removed when it is fixed in firmware in the future.
10019  */
10020
10021 /* For both X710 and XL710 */
10022 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10023 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10024 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10025
10026 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10027 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10028
10029 /* For X722 */
10030 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10031 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10032
10033 /* For X710 */
10034 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10035 /* For XL710 */
10036 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10037 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10038
10039 /*
10040  * GL_SWR_PM_UP_THR:
10041  * The value is not impacted from the link speed, its value is set according
10042  * to the total number of ports for a better pipe-monitor configuration.
10043  */
10044 static bool
10045 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10046 {
10047 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10048                 .device_id = (dev),   \
10049                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10050
10051 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10052                 .device_id = (dev),   \
10053                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10054
10055         static const struct {
10056                 uint16_t device_id;
10057                 uint32_t val;
10058         } swr_pm_table[] = {
10059                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10060                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10061                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10062                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10063
10064                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10065                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10066                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10067                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10068                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10069                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10070                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10071         };
10072         uint32_t i;
10073
10074         if (value == NULL) {
10075                 PMD_DRV_LOG(ERR, "value is NULL");
10076                 return false;
10077         }
10078
10079         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10080                 if (hw->device_id == swr_pm_table[i].device_id) {
10081                         *value = swr_pm_table[i].val;
10082
10083                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10084                                     "value - 0x%08x",
10085                                     hw->device_id, *value);
10086                         return true;
10087                 }
10088         }
10089
10090         return false;
10091 }
10092
10093 static int
10094 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10095 {
10096         enum i40e_status_code status;
10097         struct i40e_aq_get_phy_abilities_resp phy_ab;
10098         int ret = -ENOTSUP;
10099         int retries = 0;
10100
10101         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10102                                               NULL);
10103
10104         while (status) {
10105                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10106                         status);
10107                 retries++;
10108                 rte_delay_us(100000);
10109                 if  (retries < 5)
10110                         status = i40e_aq_get_phy_capabilities(hw, false,
10111                                         true, &phy_ab, NULL);
10112                 else
10113                         return ret;
10114         }
10115         return 0;
10116 }
10117
10118 static void
10119 i40e_configure_registers(struct i40e_hw *hw)
10120 {
10121         static struct {
10122                 uint32_t addr;
10123                 uint64_t val;
10124         } reg_table[] = {
10125                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10126                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10127                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10128         };
10129         uint64_t reg;
10130         uint32_t i;
10131         int ret;
10132
10133         for (i = 0; i < RTE_DIM(reg_table); i++) {
10134                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10135                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10136                                 reg_table[i].val =
10137                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10138                         else /* For X710/XL710/XXV710 */
10139                                 if (hw->aq.fw_maj_ver < 6)
10140                                         reg_table[i].val =
10141                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10142                                 else
10143                                         reg_table[i].val =
10144                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10145                 }
10146
10147                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10148                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10149                                 reg_table[i].val =
10150                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10151                         else /* For X710/XL710/XXV710 */
10152                                 reg_table[i].val =
10153                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10154                 }
10155
10156                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10157                         uint32_t cfg_val;
10158
10159                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10160                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10161                                             "GL_SWR_PM_UP_THR value fixup",
10162                                             hw->device_id);
10163                                 continue;
10164                         }
10165
10166                         reg_table[i].val = cfg_val;
10167                 }
10168
10169                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10170                                                         &reg, NULL);
10171                 if (ret < 0) {
10172                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10173                                                         reg_table[i].addr);
10174                         break;
10175                 }
10176                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10177                                                 reg_table[i].addr, reg);
10178                 if (reg == reg_table[i].val)
10179                         continue;
10180
10181                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10182                                                 reg_table[i].val, NULL);
10183                 if (ret < 0) {
10184                         PMD_DRV_LOG(ERR,
10185                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10186                                 reg_table[i].val, reg_table[i].addr);
10187                         break;
10188                 }
10189                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10190                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10191         }
10192 }
10193
10194 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10195 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10196 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10197 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10198 static int
10199 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10200 {
10201         uint32_t reg;
10202         int ret;
10203
10204         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10205                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10206                 return -EINVAL;
10207         }
10208
10209         /* Configure for double VLAN RX stripping */
10210         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10211         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10212                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10213                 ret = i40e_aq_debug_write_register(hw,
10214                                                    I40E_VSI_TSR(vsi->vsi_id),
10215                                                    reg, NULL);
10216                 if (ret < 0) {
10217                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10218                                     vsi->vsi_id);
10219                         return I40E_ERR_CONFIG;
10220                 }
10221         }
10222
10223         /* Configure for double VLAN TX insertion */
10224         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10225         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10226                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10227                 ret = i40e_aq_debug_write_register(hw,
10228                                                    I40E_VSI_L2TAGSTXVALID(
10229                                                    vsi->vsi_id), reg, NULL);
10230                 if (ret < 0) {
10231                         PMD_DRV_LOG(ERR,
10232                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10233                                 vsi->vsi_id);
10234                         return I40E_ERR_CONFIG;
10235                 }
10236         }
10237
10238         return 0;
10239 }
10240
10241 /**
10242  * i40e_aq_add_mirror_rule
10243  * @hw: pointer to the hardware structure
10244  * @seid: VEB seid to add mirror rule to
10245  * @dst_id: destination vsi seid
10246  * @entries: Buffer which contains the entities to be mirrored
10247  * @count: number of entities contained in the buffer
10248  * @rule_id:the rule_id of the rule to be added
10249  *
10250  * Add a mirror rule for a given veb.
10251  *
10252  **/
10253 static enum i40e_status_code
10254 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10255                         uint16_t seid, uint16_t dst_id,
10256                         uint16_t rule_type, uint16_t *entries,
10257                         uint16_t count, uint16_t *rule_id)
10258 {
10259         struct i40e_aq_desc desc;
10260         struct i40e_aqc_add_delete_mirror_rule cmd;
10261         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10262                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10263                 &desc.params.raw;
10264         uint16_t buff_len;
10265         enum i40e_status_code status;
10266
10267         i40e_fill_default_direct_cmd_desc(&desc,
10268                                           i40e_aqc_opc_add_mirror_rule);
10269         memset(&cmd, 0, sizeof(cmd));
10270
10271         buff_len = sizeof(uint16_t) * count;
10272         desc.datalen = rte_cpu_to_le_16(buff_len);
10273         if (buff_len > 0)
10274                 desc.flags |= rte_cpu_to_le_16(
10275                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10276         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10277                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10278         cmd.num_entries = rte_cpu_to_le_16(count);
10279         cmd.seid = rte_cpu_to_le_16(seid);
10280         cmd.destination = rte_cpu_to_le_16(dst_id);
10281
10282         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10283         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10284         PMD_DRV_LOG(INFO,
10285                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10286                 hw->aq.asq_last_status, resp->rule_id,
10287                 resp->mirror_rules_used, resp->mirror_rules_free);
10288         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10289
10290         return status;
10291 }
10292
10293 /**
10294  * i40e_aq_del_mirror_rule
10295  * @hw: pointer to the hardware structure
10296  * @seid: VEB seid to add mirror rule to
10297  * @entries: Buffer which contains the entities to be mirrored
10298  * @count: number of entities contained in the buffer
10299  * @rule_id:the rule_id of the rule to be delete
10300  *
10301  * Delete a mirror rule for a given veb.
10302  *
10303  **/
10304 static enum i40e_status_code
10305 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10306                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10307                 uint16_t count, uint16_t rule_id)
10308 {
10309         struct i40e_aq_desc desc;
10310         struct i40e_aqc_add_delete_mirror_rule cmd;
10311         uint16_t buff_len = 0;
10312         enum i40e_status_code status;
10313         void *buff = NULL;
10314
10315         i40e_fill_default_direct_cmd_desc(&desc,
10316                                           i40e_aqc_opc_delete_mirror_rule);
10317         memset(&cmd, 0, sizeof(cmd));
10318         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10319                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10320                                                           I40E_AQ_FLAG_RD));
10321                 cmd.num_entries = count;
10322                 buff_len = sizeof(uint16_t) * count;
10323                 desc.datalen = rte_cpu_to_le_16(buff_len);
10324                 buff = (void *)entries;
10325         } else
10326                 /* rule id is filled in destination field for deleting mirror rule */
10327                 cmd.destination = rte_cpu_to_le_16(rule_id);
10328
10329         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10330                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10331         cmd.seid = rte_cpu_to_le_16(seid);
10332
10333         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10334         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10335
10336         return status;
10337 }
10338
10339 /**
10340  * i40e_mirror_rule_set
10341  * @dev: pointer to the hardware structure
10342  * @mirror_conf: mirror rule info
10343  * @sw_id: mirror rule's sw_id
10344  * @on: enable/disable
10345  *
10346  * set a mirror rule.
10347  *
10348  **/
10349 static int
10350 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10351                         struct rte_eth_mirror_conf *mirror_conf,
10352                         uint8_t sw_id, uint8_t on)
10353 {
10354         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10355         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10356         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10357         struct i40e_mirror_rule *parent = NULL;
10358         uint16_t seid, dst_seid, rule_id;
10359         uint16_t i, j = 0;
10360         int ret;
10361
10362         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10363
10364         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10365                 PMD_DRV_LOG(ERR,
10366                         "mirror rule can not be configured without veb or vfs.");
10367                 return -ENOSYS;
10368         }
10369         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10370                 PMD_DRV_LOG(ERR, "mirror table is full.");
10371                 return -ENOSPC;
10372         }
10373         if (mirror_conf->dst_pool > pf->vf_num) {
10374                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10375                                  mirror_conf->dst_pool);
10376                 return -EINVAL;
10377         }
10378
10379         seid = pf->main_vsi->veb->seid;
10380
10381         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10382                 if (sw_id <= it->index) {
10383                         mirr_rule = it;
10384                         break;
10385                 }
10386                 parent = it;
10387         }
10388         if (mirr_rule && sw_id == mirr_rule->index) {
10389                 if (on) {
10390                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10391                         return -EEXIST;
10392                 } else {
10393                         ret = i40e_aq_del_mirror_rule(hw, seid,
10394                                         mirr_rule->rule_type,
10395                                         mirr_rule->entries,
10396                                         mirr_rule->num_entries, mirr_rule->id);
10397                         if (ret < 0) {
10398                                 PMD_DRV_LOG(ERR,
10399                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10400                                         ret, hw->aq.asq_last_status);
10401                                 return -ENOSYS;
10402                         }
10403                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10404                         rte_free(mirr_rule);
10405                         pf->nb_mirror_rule--;
10406                         return 0;
10407                 }
10408         } else if (!on) {
10409                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10410                 return -ENOENT;
10411         }
10412
10413         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10414                                 sizeof(struct i40e_mirror_rule) , 0);
10415         if (!mirr_rule) {
10416                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10417                 return I40E_ERR_NO_MEMORY;
10418         }
10419         switch (mirror_conf->rule_type) {
10420         case ETH_MIRROR_VLAN:
10421                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10422                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10423                                 mirr_rule->entries[j] =
10424                                         mirror_conf->vlan.vlan_id[i];
10425                                 j++;
10426                         }
10427                 }
10428                 if (j == 0) {
10429                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10430                         rte_free(mirr_rule);
10431                         return -EINVAL;
10432                 }
10433                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10434                 break;
10435         case ETH_MIRROR_VIRTUAL_POOL_UP:
10436         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10437                 /* check if the specified pool bit is out of range */
10438                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10439                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10440                         rte_free(mirr_rule);
10441                         return -EINVAL;
10442                 }
10443                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10444                         if (mirror_conf->pool_mask & (1ULL << i)) {
10445                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10446                                 j++;
10447                         }
10448                 }
10449                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10450                         /* add pf vsi to entries */
10451                         mirr_rule->entries[j] = pf->main_vsi_seid;
10452                         j++;
10453                 }
10454                 if (j == 0) {
10455                         PMD_DRV_LOG(ERR, "pool is not specified.");
10456                         rte_free(mirr_rule);
10457                         return -EINVAL;
10458                 }
10459                 /* egress and ingress in aq commands means from switch but not port */
10460                 mirr_rule->rule_type =
10461                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10462                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10463                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10464                 break;
10465         case ETH_MIRROR_UPLINK_PORT:
10466                 /* egress and ingress in aq commands means from switch but not port*/
10467                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10468                 break;
10469         case ETH_MIRROR_DOWNLINK_PORT:
10470                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10471                 break;
10472         default:
10473                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10474                         mirror_conf->rule_type);
10475                 rte_free(mirr_rule);
10476                 return -EINVAL;
10477         }
10478
10479         /* If the dst_pool is equal to vf_num, consider it as PF */
10480         if (mirror_conf->dst_pool == pf->vf_num)
10481                 dst_seid = pf->main_vsi_seid;
10482         else
10483                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10484
10485         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10486                                       mirr_rule->rule_type, mirr_rule->entries,
10487                                       j, &rule_id);
10488         if (ret < 0) {
10489                 PMD_DRV_LOG(ERR,
10490                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10491                         ret, hw->aq.asq_last_status);
10492                 rte_free(mirr_rule);
10493                 return -ENOSYS;
10494         }
10495
10496         mirr_rule->index = sw_id;
10497         mirr_rule->num_entries = j;
10498         mirr_rule->id = rule_id;
10499         mirr_rule->dst_vsi_seid = dst_seid;
10500
10501         if (parent)
10502                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10503         else
10504                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10505
10506         pf->nb_mirror_rule++;
10507         return 0;
10508 }
10509
10510 /**
10511  * i40e_mirror_rule_reset
10512  * @dev: pointer to the device
10513  * @sw_id: mirror rule's sw_id
10514  *
10515  * reset a mirror rule.
10516  *
10517  **/
10518 static int
10519 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10520 {
10521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10522         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10523         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10524         uint16_t seid;
10525         int ret;
10526
10527         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10528
10529         seid = pf->main_vsi->veb->seid;
10530
10531         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10532                 if (sw_id == it->index) {
10533                         mirr_rule = it;
10534                         break;
10535                 }
10536         }
10537         if (mirr_rule) {
10538                 ret = i40e_aq_del_mirror_rule(hw, seid,
10539                                 mirr_rule->rule_type,
10540                                 mirr_rule->entries,
10541                                 mirr_rule->num_entries, mirr_rule->id);
10542                 if (ret < 0) {
10543                         PMD_DRV_LOG(ERR,
10544                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10545                                 ret, hw->aq.asq_last_status);
10546                         return -ENOSYS;
10547                 }
10548                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10549                 rte_free(mirr_rule);
10550                 pf->nb_mirror_rule--;
10551         } else {
10552                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10553                 return -ENOENT;
10554         }
10555         return 0;
10556 }
10557
10558 static uint64_t
10559 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10560 {
10561         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10562         uint64_t systim_cycles;
10563
10564         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10565         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10566                         << 32;
10567
10568         return systim_cycles;
10569 }
10570
10571 static uint64_t
10572 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10573 {
10574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10575         uint64_t rx_tstamp;
10576
10577         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10578         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10579                         << 32;
10580
10581         return rx_tstamp;
10582 }
10583
10584 static uint64_t
10585 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10586 {
10587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10588         uint64_t tx_tstamp;
10589
10590         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10591         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10592                         << 32;
10593
10594         return tx_tstamp;
10595 }
10596
10597 static void
10598 i40e_start_timecounters(struct rte_eth_dev *dev)
10599 {
10600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10601         struct i40e_adapter *adapter =
10602                         (struct i40e_adapter *)dev->data->dev_private;
10603         struct rte_eth_link link;
10604         uint32_t tsync_inc_l;
10605         uint32_t tsync_inc_h;
10606
10607         /* Get current link speed. */
10608         i40e_dev_link_update(dev, 1);
10609         rte_eth_linkstatus_get(dev, &link);
10610
10611         switch (link.link_speed) {
10612         case ETH_SPEED_NUM_40G:
10613                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10614                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10615                 break;
10616         case ETH_SPEED_NUM_10G:
10617                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10618                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10619                 break;
10620         case ETH_SPEED_NUM_1G:
10621                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10622                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10623                 break;
10624         default:
10625                 tsync_inc_l = 0x0;
10626                 tsync_inc_h = 0x0;
10627         }
10628
10629         /* Set the timesync increment value. */
10630         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10631         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10632
10633         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10634         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10635         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10636
10637         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10638         adapter->systime_tc.cc_shift = 0;
10639         adapter->systime_tc.nsec_mask = 0;
10640
10641         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10642         adapter->rx_tstamp_tc.cc_shift = 0;
10643         adapter->rx_tstamp_tc.nsec_mask = 0;
10644
10645         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10646         adapter->tx_tstamp_tc.cc_shift = 0;
10647         adapter->tx_tstamp_tc.nsec_mask = 0;
10648 }
10649
10650 static int
10651 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10652 {
10653         struct i40e_adapter *adapter =
10654                         (struct i40e_adapter *)dev->data->dev_private;
10655
10656         adapter->systime_tc.nsec += delta;
10657         adapter->rx_tstamp_tc.nsec += delta;
10658         adapter->tx_tstamp_tc.nsec += delta;
10659
10660         return 0;
10661 }
10662
10663 static int
10664 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10665 {
10666         uint64_t ns;
10667         struct i40e_adapter *adapter =
10668                         (struct i40e_adapter *)dev->data->dev_private;
10669
10670         ns = rte_timespec_to_ns(ts);
10671
10672         /* Set the timecounters to a new value. */
10673         adapter->systime_tc.nsec = ns;
10674         adapter->rx_tstamp_tc.nsec = ns;
10675         adapter->tx_tstamp_tc.nsec = ns;
10676
10677         return 0;
10678 }
10679
10680 static int
10681 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10682 {
10683         uint64_t ns, systime_cycles;
10684         struct i40e_adapter *adapter =
10685                         (struct i40e_adapter *)dev->data->dev_private;
10686
10687         systime_cycles = i40e_read_systime_cyclecounter(dev);
10688         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10689         *ts = rte_ns_to_timespec(ns);
10690
10691         return 0;
10692 }
10693
10694 static int
10695 i40e_timesync_enable(struct rte_eth_dev *dev)
10696 {
10697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10698         uint32_t tsync_ctl_l;
10699         uint32_t tsync_ctl_h;
10700
10701         /* Stop the timesync system time. */
10702         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10703         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10704         /* Reset the timesync system time value. */
10705         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10706         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10707
10708         i40e_start_timecounters(dev);
10709
10710         /* Clear timesync registers. */
10711         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10712         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10713         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10714         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10715         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10716         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10717
10718         /* Enable timestamping of PTP packets. */
10719         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10720         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10721
10722         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10723         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10724         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10725
10726         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10727         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10728
10729         return 0;
10730 }
10731
10732 static int
10733 i40e_timesync_disable(struct rte_eth_dev *dev)
10734 {
10735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10736         uint32_t tsync_ctl_l;
10737         uint32_t tsync_ctl_h;
10738
10739         /* Disable timestamping of transmitted PTP packets. */
10740         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10741         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10742
10743         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10744         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10745
10746         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10747         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10748
10749         /* Reset the timesync increment value. */
10750         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10751         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10752
10753         return 0;
10754 }
10755
10756 static int
10757 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10758                                 struct timespec *timestamp, uint32_t flags)
10759 {
10760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10761         struct i40e_adapter *adapter =
10762                 (struct i40e_adapter *)dev->data->dev_private;
10763
10764         uint32_t sync_status;
10765         uint32_t index = flags & 0x03;
10766         uint64_t rx_tstamp_cycles;
10767         uint64_t ns;
10768
10769         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10770         if ((sync_status & (1 << index)) == 0)
10771                 return -EINVAL;
10772
10773         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10774         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10775         *timestamp = rte_ns_to_timespec(ns);
10776
10777         return 0;
10778 }
10779
10780 static int
10781 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10782                                 struct timespec *timestamp)
10783 {
10784         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10785         struct i40e_adapter *adapter =
10786                 (struct i40e_adapter *)dev->data->dev_private;
10787
10788         uint32_t sync_status;
10789         uint64_t tx_tstamp_cycles;
10790         uint64_t ns;
10791
10792         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10793         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10794                 return -EINVAL;
10795
10796         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10797         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10798         *timestamp = rte_ns_to_timespec(ns);
10799
10800         return 0;
10801 }
10802
10803 /*
10804  * i40e_parse_dcb_configure - parse dcb configure from user
10805  * @dev: the device being configured
10806  * @dcb_cfg: pointer of the result of parse
10807  * @*tc_map: bit map of enabled traffic classes
10808  *
10809  * Returns 0 on success, negative value on failure
10810  */
10811 static int
10812 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10813                          struct i40e_dcbx_config *dcb_cfg,
10814                          uint8_t *tc_map)
10815 {
10816         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10817         uint8_t i, tc_bw, bw_lf;
10818
10819         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10820
10821         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10822         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10823                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10824                 return -EINVAL;
10825         }
10826
10827         /* assume each tc has the same bw */
10828         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10829         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10830                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10831         /* to ensure the sum of tcbw is equal to 100 */
10832         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10833         for (i = 0; i < bw_lf; i++)
10834                 dcb_cfg->etscfg.tcbwtable[i]++;
10835
10836         /* assume each tc has the same Transmission Selection Algorithm */
10837         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10838                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10839
10840         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10841                 dcb_cfg->etscfg.prioritytable[i] =
10842                                 dcb_rx_conf->dcb_tc[i];
10843
10844         /* FW needs one App to configure HW */
10845         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10846         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10847         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10848         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10849
10850         if (dcb_rx_conf->nb_tcs == 0)
10851                 *tc_map = 1; /* tc0 only */
10852         else
10853                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10854
10855         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10856                 dcb_cfg->pfc.willing = 0;
10857                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10858                 dcb_cfg->pfc.pfcenable = *tc_map;
10859         }
10860         return 0;
10861 }
10862
10863
10864 static enum i40e_status_code
10865 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10866                               struct i40e_aqc_vsi_properties_data *info,
10867                               uint8_t enabled_tcmap)
10868 {
10869         enum i40e_status_code ret;
10870         int i, total_tc = 0;
10871         uint16_t qpnum_per_tc, bsf, qp_idx;
10872         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10873         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10874         uint16_t used_queues;
10875
10876         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10877         if (ret != I40E_SUCCESS)
10878                 return ret;
10879
10880         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10881                 if (enabled_tcmap & (1 << i))
10882                         total_tc++;
10883         }
10884         if (total_tc == 0)
10885                 total_tc = 1;
10886         vsi->enabled_tc = enabled_tcmap;
10887
10888         /* different VSI has different queues assigned */
10889         if (vsi->type == I40E_VSI_MAIN)
10890                 used_queues = dev_data->nb_rx_queues -
10891                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10892         else if (vsi->type == I40E_VSI_VMDQ2)
10893                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10894         else {
10895                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10896                 return I40E_ERR_NO_AVAILABLE_VSI;
10897         }
10898
10899         qpnum_per_tc = used_queues / total_tc;
10900         /* Number of queues per enabled TC */
10901         if (qpnum_per_tc == 0) {
10902                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10903                 return I40E_ERR_INVALID_QP_ID;
10904         }
10905         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10906                                 I40E_MAX_Q_PER_TC);
10907         bsf = rte_bsf32(qpnum_per_tc);
10908
10909         /**
10910          * Configure TC and queue mapping parameters, for enabled TC,
10911          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10912          * default queue will serve it.
10913          */
10914         qp_idx = 0;
10915         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10916                 if (vsi->enabled_tc & (1 << i)) {
10917                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10918                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10919                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10920                         qp_idx += qpnum_per_tc;
10921                 } else
10922                         info->tc_mapping[i] = 0;
10923         }
10924
10925         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10926         if (vsi->type == I40E_VSI_SRIOV) {
10927                 info->mapping_flags |=
10928                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10929                 for (i = 0; i < vsi->nb_qps; i++)
10930                         info->queue_mapping[i] =
10931                                 rte_cpu_to_le_16(vsi->base_queue + i);
10932         } else {
10933                 info->mapping_flags |=
10934                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10935                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10936         }
10937         info->valid_sections |=
10938                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10939
10940         return I40E_SUCCESS;
10941 }
10942
10943 /*
10944  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10945  * @veb: VEB to be configured
10946  * @tc_map: enabled TC bitmap
10947  *
10948  * Returns 0 on success, negative value on failure
10949  */
10950 static enum i40e_status_code
10951 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10952 {
10953         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10954         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10955         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10956         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10957         enum i40e_status_code ret = I40E_SUCCESS;
10958         int i;
10959         uint32_t bw_max;
10960
10961         /* Check if enabled_tc is same as existing or new TCs */
10962         if (veb->enabled_tc == tc_map)
10963                 return ret;
10964
10965         /* configure tc bandwidth */
10966         memset(&veb_bw, 0, sizeof(veb_bw));
10967         veb_bw.tc_valid_bits = tc_map;
10968         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10969         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10970                 if (tc_map & BIT_ULL(i))
10971                         veb_bw.tc_bw_share_credits[i] = 1;
10972         }
10973         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10974                                                    &veb_bw, NULL);
10975         if (ret) {
10976                 PMD_INIT_LOG(ERR,
10977                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10978                         hw->aq.asq_last_status);
10979                 return ret;
10980         }
10981
10982         memset(&ets_query, 0, sizeof(ets_query));
10983         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10984                                                    &ets_query, NULL);
10985         if (ret != I40E_SUCCESS) {
10986                 PMD_DRV_LOG(ERR,
10987                         "Failed to get switch_comp ETS configuration %u",
10988                         hw->aq.asq_last_status);
10989                 return ret;
10990         }
10991         memset(&bw_query, 0, sizeof(bw_query));
10992         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10993                                                   &bw_query, NULL);
10994         if (ret != I40E_SUCCESS) {
10995                 PMD_DRV_LOG(ERR,
10996                         "Failed to get switch_comp bandwidth configuration %u",
10997                         hw->aq.asq_last_status);
10998                 return ret;
10999         }
11000
11001         /* store and print out BW info */
11002         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11003         veb->bw_info.bw_max = ets_query.tc_bw_max;
11004         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11005         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11006         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11007                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11008                      I40E_16_BIT_WIDTH);
11009         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11010                 veb->bw_info.bw_ets_share_credits[i] =
11011                                 bw_query.tc_bw_share_credits[i];
11012                 veb->bw_info.bw_ets_credits[i] =
11013                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11014                 /* 4 bits per TC, 4th bit is reserved */
11015                 veb->bw_info.bw_ets_max[i] =
11016                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11017                                   RTE_LEN2MASK(3, uint8_t));
11018                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11019                             veb->bw_info.bw_ets_share_credits[i]);
11020                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11021                             veb->bw_info.bw_ets_credits[i]);
11022                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11023                             veb->bw_info.bw_ets_max[i]);
11024         }
11025
11026         veb->enabled_tc = tc_map;
11027
11028         return ret;
11029 }
11030
11031
11032 /*
11033  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11034  * @vsi: VSI to be configured
11035  * @tc_map: enabled TC bitmap
11036  *
11037  * Returns 0 on success, negative value on failure
11038  */
11039 static enum i40e_status_code
11040 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11041 {
11042         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11043         struct i40e_vsi_context ctxt;
11044         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11045         enum i40e_status_code ret = I40E_SUCCESS;
11046         int i;
11047
11048         /* Check if enabled_tc is same as existing or new TCs */
11049         if (vsi->enabled_tc == tc_map)
11050                 return ret;
11051
11052         /* configure tc bandwidth */
11053         memset(&bw_data, 0, sizeof(bw_data));
11054         bw_data.tc_valid_bits = tc_map;
11055         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11056         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11057                 if (tc_map & BIT_ULL(i))
11058                         bw_data.tc_bw_credits[i] = 1;
11059         }
11060         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11061         if (ret) {
11062                 PMD_INIT_LOG(ERR,
11063                         "AQ command Config VSI BW allocation per TC failed = %d",
11064                         hw->aq.asq_last_status);
11065                 goto out;
11066         }
11067         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11068                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11069
11070         /* Update Queue Pairs Mapping for currently enabled UPs */
11071         ctxt.seid = vsi->seid;
11072         ctxt.pf_num = hw->pf_id;
11073         ctxt.vf_num = 0;
11074         ctxt.uplink_seid = vsi->uplink_seid;
11075         ctxt.info = vsi->info;
11076         i40e_get_cap(hw);
11077         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11078         if (ret)
11079                 goto out;
11080
11081         /* Update the VSI after updating the VSI queue-mapping information */
11082         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11083         if (ret) {
11084                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11085                         hw->aq.asq_last_status);
11086                 goto out;
11087         }
11088         /* update the local VSI info with updated queue map */
11089         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11090                                         sizeof(vsi->info.tc_mapping));
11091         rte_memcpy(&vsi->info.queue_mapping,
11092                         &ctxt.info.queue_mapping,
11093                 sizeof(vsi->info.queue_mapping));
11094         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11095         vsi->info.valid_sections = 0;
11096
11097         /* query and update current VSI BW information */
11098         ret = i40e_vsi_get_bw_config(vsi);
11099         if (ret) {
11100                 PMD_INIT_LOG(ERR,
11101                          "Failed updating vsi bw info, err %s aq_err %s",
11102                          i40e_stat_str(hw, ret),
11103                          i40e_aq_str(hw, hw->aq.asq_last_status));
11104                 goto out;
11105         }
11106
11107         vsi->enabled_tc = tc_map;
11108
11109 out:
11110         return ret;
11111 }
11112
11113 /*
11114  * i40e_dcb_hw_configure - program the dcb setting to hw
11115  * @pf: pf the configuration is taken on
11116  * @new_cfg: new configuration
11117  * @tc_map: enabled TC bitmap
11118  *
11119  * Returns 0 on success, negative value on failure
11120  */
11121 static enum i40e_status_code
11122 i40e_dcb_hw_configure(struct i40e_pf *pf,
11123                       struct i40e_dcbx_config *new_cfg,
11124                       uint8_t tc_map)
11125 {
11126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11127         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11128         struct i40e_vsi *main_vsi = pf->main_vsi;
11129         struct i40e_vsi_list *vsi_list;
11130         enum i40e_status_code ret;
11131         int i;
11132         uint32_t val;
11133
11134         /* Use the FW API if FW > v4.4*/
11135         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11136               (hw->aq.fw_maj_ver >= 5))) {
11137                 PMD_INIT_LOG(ERR,
11138                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11139                 return I40E_ERR_FIRMWARE_API_VERSION;
11140         }
11141
11142         /* Check if need reconfiguration */
11143         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11144                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11145                 return I40E_SUCCESS;
11146         }
11147
11148         /* Copy the new config to the current config */
11149         *old_cfg = *new_cfg;
11150         old_cfg->etsrec = old_cfg->etscfg;
11151         ret = i40e_set_dcb_config(hw);
11152         if (ret) {
11153                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11154                          i40e_stat_str(hw, ret),
11155                          i40e_aq_str(hw, hw->aq.asq_last_status));
11156                 return ret;
11157         }
11158         /* set receive Arbiter to RR mode and ETS scheme by default */
11159         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11160                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11161                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11162                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11163                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11164                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11165                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11166                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11167                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11168                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11169                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11170                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11171                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11172         }
11173         /* get local mib to check whether it is configured correctly */
11174         /* IEEE mode */
11175         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11176         /* Get Local DCB Config */
11177         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11178                                      &hw->local_dcbx_config);
11179
11180         /* if Veb is created, need to update TC of it at first */
11181         if (main_vsi->veb) {
11182                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11183                 if (ret)
11184                         PMD_INIT_LOG(WARNING,
11185                                  "Failed configuring TC for VEB seid=%d",
11186                                  main_vsi->veb->seid);
11187         }
11188         /* Update each VSI */
11189         i40e_vsi_config_tc(main_vsi, tc_map);
11190         if (main_vsi->veb) {
11191                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11192                         /* Beside main VSI and VMDQ VSIs, only enable default
11193                          * TC for other VSIs
11194                          */
11195                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11196                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11197                                                          tc_map);
11198                         else
11199                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11200                                                          I40E_DEFAULT_TCMAP);
11201                         if (ret)
11202                                 PMD_INIT_LOG(WARNING,
11203                                         "Failed configuring TC for VSI seid=%d",
11204                                         vsi_list->vsi->seid);
11205                         /* continue */
11206                 }
11207         }
11208         return I40E_SUCCESS;
11209 }
11210
11211 /*
11212  * i40e_dcb_init_configure - initial dcb config
11213  * @dev: device being configured
11214  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11215  *
11216  * Returns 0 on success, negative value on failure
11217  */
11218 int
11219 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11220 {
11221         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11223         int i, ret = 0;
11224
11225         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11226                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11227                 return -ENOTSUP;
11228         }
11229
11230         /* DCB initialization:
11231          * Update DCB configuration from the Firmware and configure
11232          * LLDP MIB change event.
11233          */
11234         if (sw_dcb == TRUE) {
11235                 ret = i40e_init_dcb(hw);
11236                 /* If lldp agent is stopped, the return value from
11237                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11238                  * adminq status. Otherwise, it should return success.
11239                  */
11240                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11241                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11242                         memset(&hw->local_dcbx_config, 0,
11243                                 sizeof(struct i40e_dcbx_config));
11244                         /* set dcb default configuration */
11245                         hw->local_dcbx_config.etscfg.willing = 0;
11246                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11247                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11248                         hw->local_dcbx_config.etscfg.tsatable[0] =
11249                                                 I40E_IEEE_TSA_ETS;
11250                         /* all UPs mapping to TC0 */
11251                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11252                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11253                         hw->local_dcbx_config.etsrec =
11254                                 hw->local_dcbx_config.etscfg;
11255                         hw->local_dcbx_config.pfc.willing = 0;
11256                         hw->local_dcbx_config.pfc.pfccap =
11257                                                 I40E_MAX_TRAFFIC_CLASS;
11258                         /* FW needs one App to configure HW */
11259                         hw->local_dcbx_config.numapps = 1;
11260                         hw->local_dcbx_config.app[0].selector =
11261                                                 I40E_APP_SEL_ETHTYPE;
11262                         hw->local_dcbx_config.app[0].priority = 3;
11263                         hw->local_dcbx_config.app[0].protocolid =
11264                                                 I40E_APP_PROTOID_FCOE;
11265                         ret = i40e_set_dcb_config(hw);
11266                         if (ret) {
11267                                 PMD_INIT_LOG(ERR,
11268                                         "default dcb config fails. err = %d, aq_err = %d.",
11269                                         ret, hw->aq.asq_last_status);
11270                                 return -ENOSYS;
11271                         }
11272                 } else {
11273                         PMD_INIT_LOG(ERR,
11274                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11275                                 ret, hw->aq.asq_last_status);
11276                         return -ENOTSUP;
11277                 }
11278         } else {
11279                 ret = i40e_aq_start_lldp(hw, NULL);
11280                 if (ret != I40E_SUCCESS)
11281                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11282
11283                 ret = i40e_init_dcb(hw);
11284                 if (!ret) {
11285                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11286                                 PMD_INIT_LOG(ERR,
11287                                         "HW doesn't support DCBX offload.");
11288                                 return -ENOTSUP;
11289                         }
11290                 } else {
11291                         PMD_INIT_LOG(ERR,
11292                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11293                                 ret, hw->aq.asq_last_status);
11294                         return -ENOTSUP;
11295                 }
11296         }
11297         return 0;
11298 }
11299
11300 /*
11301  * i40e_dcb_setup - setup dcb related config
11302  * @dev: device being configured
11303  *
11304  * Returns 0 on success, negative value on failure
11305  */
11306 static int
11307 i40e_dcb_setup(struct rte_eth_dev *dev)
11308 {
11309         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11310         struct i40e_dcbx_config dcb_cfg;
11311         uint8_t tc_map = 0;
11312         int ret = 0;
11313
11314         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11315                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11316                 return -ENOTSUP;
11317         }
11318
11319         if (pf->vf_num != 0)
11320                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11321
11322         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11323         if (ret) {
11324                 PMD_INIT_LOG(ERR, "invalid dcb config");
11325                 return -EINVAL;
11326         }
11327         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11328         if (ret) {
11329                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11330                 return -ENOSYS;
11331         }
11332
11333         return 0;
11334 }
11335
11336 static int
11337 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11338                       struct rte_eth_dcb_info *dcb_info)
11339 {
11340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11342         struct i40e_vsi *vsi = pf->main_vsi;
11343         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11344         uint16_t bsf, tc_mapping;
11345         int i, j = 0;
11346
11347         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11348                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11349         else
11350                 dcb_info->nb_tcs = 1;
11351         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11352                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11353         for (i = 0; i < dcb_info->nb_tcs; i++)
11354                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11355
11356         /* get queue mapping if vmdq is disabled */
11357         if (!pf->nb_cfg_vmdq_vsi) {
11358                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11359                         if (!(vsi->enabled_tc & (1 << i)))
11360                                 continue;
11361                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11362                         dcb_info->tc_queue.tc_rxq[j][i].base =
11363                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11364                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11365                         dcb_info->tc_queue.tc_txq[j][i].base =
11366                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11367                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11368                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11369                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11370                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11371                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11372                 }
11373                 return 0;
11374         }
11375
11376         /* get queue mapping if vmdq is enabled */
11377         do {
11378                 vsi = pf->vmdq[j].vsi;
11379                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11380                         if (!(vsi->enabled_tc & (1 << i)))
11381                                 continue;
11382                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11383                         dcb_info->tc_queue.tc_rxq[j][i].base =
11384                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11385                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11386                         dcb_info->tc_queue.tc_txq[j][i].base =
11387                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11388                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11389                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11390                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11391                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11392                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11393                 }
11394                 j++;
11395         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11396         return 0;
11397 }
11398
11399 static int
11400 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11401 {
11402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11403         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11405         uint16_t msix_intr;
11406
11407         msix_intr = intr_handle->intr_vec[queue_id];
11408         if (msix_intr == I40E_MISC_VEC_ID)
11409                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11410                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11411                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11412                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11413         else
11414                 I40E_WRITE_REG(hw,
11415                                I40E_PFINT_DYN_CTLN(msix_intr -
11416                                                    I40E_RX_VEC_START),
11417                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11418                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11419                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11420
11421         I40E_WRITE_FLUSH(hw);
11422         rte_intr_enable(&pci_dev->intr_handle);
11423
11424         return 0;
11425 }
11426
11427 static int
11428 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11429 {
11430         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11431         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11433         uint16_t msix_intr;
11434
11435         msix_intr = intr_handle->intr_vec[queue_id];
11436         if (msix_intr == I40E_MISC_VEC_ID)
11437                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11438                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11439         else
11440                 I40E_WRITE_REG(hw,
11441                                I40E_PFINT_DYN_CTLN(msix_intr -
11442                                                    I40E_RX_VEC_START),
11443                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11444         I40E_WRITE_FLUSH(hw);
11445
11446         return 0;
11447 }
11448
11449 static int i40e_get_regs(struct rte_eth_dev *dev,
11450                          struct rte_dev_reg_info *regs)
11451 {
11452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11453         uint32_t *ptr_data = regs->data;
11454         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11455         const struct i40e_reg_info *reg_info;
11456
11457         if (ptr_data == NULL) {
11458                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11459                 regs->width = sizeof(uint32_t);
11460                 return 0;
11461         }
11462
11463         /* The first few registers have to be read using AQ operations */
11464         reg_idx = 0;
11465         while (i40e_regs_adminq[reg_idx].name) {
11466                 reg_info = &i40e_regs_adminq[reg_idx++];
11467                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11468                         for (arr_idx2 = 0;
11469                                         arr_idx2 <= reg_info->count2;
11470                                         arr_idx2++) {
11471                                 reg_offset = arr_idx * reg_info->stride1 +
11472                                         arr_idx2 * reg_info->stride2;
11473                                 reg_offset += reg_info->base_addr;
11474                                 ptr_data[reg_offset >> 2] =
11475                                         i40e_read_rx_ctl(hw, reg_offset);
11476                         }
11477         }
11478
11479         /* The remaining registers can be read using primitives */
11480         reg_idx = 0;
11481         while (i40e_regs_others[reg_idx].name) {
11482                 reg_info = &i40e_regs_others[reg_idx++];
11483                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11484                         for (arr_idx2 = 0;
11485                                         arr_idx2 <= reg_info->count2;
11486                                         arr_idx2++) {
11487                                 reg_offset = arr_idx * reg_info->stride1 +
11488                                         arr_idx2 * reg_info->stride2;
11489                                 reg_offset += reg_info->base_addr;
11490                                 ptr_data[reg_offset >> 2] =
11491                                         I40E_READ_REG(hw, reg_offset);
11492                         }
11493         }
11494
11495         return 0;
11496 }
11497
11498 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11499 {
11500         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11501
11502         /* Convert word count to byte count */
11503         return hw->nvm.sr_size << 1;
11504 }
11505
11506 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11507                            struct rte_dev_eeprom_info *eeprom)
11508 {
11509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11510         uint16_t *data = eeprom->data;
11511         uint16_t offset, length, cnt_words;
11512         int ret_code;
11513
11514         offset = eeprom->offset >> 1;
11515         length = eeprom->length >> 1;
11516         cnt_words = length;
11517
11518         if (offset > hw->nvm.sr_size ||
11519                 offset + length > hw->nvm.sr_size) {
11520                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11521                 return -EINVAL;
11522         }
11523
11524         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11525
11526         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11527         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11528                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11529                 return -EIO;
11530         }
11531
11532         return 0;
11533 }
11534
11535 static int i40e_get_module_info(struct rte_eth_dev *dev,
11536                                 struct rte_eth_dev_module_info *modinfo)
11537 {
11538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11539         uint32_t sff8472_comp = 0;
11540         uint32_t sff8472_swap = 0;
11541         uint32_t sff8636_rev = 0;
11542         i40e_status status;
11543         uint32_t type = 0;
11544
11545         /* Check if firmware supports reading module EEPROM. */
11546         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11547                 PMD_DRV_LOG(ERR,
11548                             "Module EEPROM memory read not supported. "
11549                             "Please update the NVM image.\n");
11550                 return -EINVAL;
11551         }
11552
11553         status = i40e_update_link_info(hw);
11554         if (status)
11555                 return -EIO;
11556
11557         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11558                 PMD_DRV_LOG(ERR,
11559                             "Cannot read module EEPROM memory. "
11560                             "No module connected.\n");
11561                 return -EINVAL;
11562         }
11563
11564         type = hw->phy.link_info.module_type[0];
11565
11566         switch (type) {
11567         case I40E_MODULE_TYPE_SFP:
11568                 status = i40e_aq_get_phy_register(hw,
11569                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11570                                 I40E_I2C_EEPROM_DEV_ADDR,
11571                                 I40E_MODULE_SFF_8472_COMP,
11572                                 &sff8472_comp, NULL);
11573                 if (status)
11574                         return -EIO;
11575
11576                 status = i40e_aq_get_phy_register(hw,
11577                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11578                                 I40E_I2C_EEPROM_DEV_ADDR,
11579                                 I40E_MODULE_SFF_8472_SWAP,
11580                                 &sff8472_swap, NULL);
11581                 if (status)
11582                         return -EIO;
11583
11584                 /* Check if the module requires address swap to access
11585                  * the other EEPROM memory page.
11586                  */
11587                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11588                         PMD_DRV_LOG(WARNING,
11589                                     "Module address swap to access "
11590                                     "page 0xA2 is not supported.\n");
11591                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11592                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11593                 } else if (sff8472_comp == 0x00) {
11594                         /* Module is not SFF-8472 compliant */
11595                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11596                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11597                 } else {
11598                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11599                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11600                 }
11601                 break;
11602         case I40E_MODULE_TYPE_QSFP_PLUS:
11603                 /* Read from memory page 0. */
11604                 status = i40e_aq_get_phy_register(hw,
11605                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11606                                 0,
11607                                 I40E_MODULE_REVISION_ADDR,
11608                                 &sff8636_rev, NULL);
11609                 if (status)
11610                         return -EIO;
11611                 /* Determine revision compliance byte */
11612                 if (sff8636_rev > 0x02) {
11613                         /* Module is SFF-8636 compliant */
11614                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11615                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11616                 } else {
11617                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11618                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11619                 }
11620                 break;
11621         case I40E_MODULE_TYPE_QSFP28:
11622                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11623                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11624                 break;
11625         default:
11626                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11627                 return -EINVAL;
11628         }
11629         return 0;
11630 }
11631
11632 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11633                                   struct rte_dev_eeprom_info *info)
11634 {
11635         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11636         bool is_sfp = false;
11637         i40e_status status;
11638         uint8_t *data = info->data;
11639         uint32_t value = 0;
11640         uint32_t i;
11641
11642         if (!info || !info->length || !data)
11643                 return -EINVAL;
11644
11645         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11646                 is_sfp = true;
11647
11648         for (i = 0; i < info->length; i++) {
11649                 u32 offset = i + info->offset;
11650                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11651
11652                 /* Check if we need to access the other memory page */
11653                 if (is_sfp) {
11654                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11655                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11656                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11657                         }
11658                 } else {
11659                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11660                                 /* Compute memory page number and offset. */
11661                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11662                                 addr++;
11663                         }
11664                 }
11665                 status = i40e_aq_get_phy_register(hw,
11666                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11667                                 addr, offset, &value, NULL);
11668                 if (status)
11669                         return -EIO;
11670                 data[i] = (uint8_t)value;
11671         }
11672         return 0;
11673 }
11674
11675 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11676                                      struct ether_addr *mac_addr)
11677 {
11678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11680         struct i40e_vsi *vsi = pf->main_vsi;
11681         struct i40e_mac_filter_info mac_filter;
11682         struct i40e_mac_filter *f;
11683         int ret;
11684
11685         if (!is_valid_assigned_ether_addr(mac_addr)) {
11686                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11687                 return -EINVAL;
11688         }
11689
11690         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11691                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11692                         break;
11693         }
11694
11695         if (f == NULL) {
11696                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11697                 return -EIO;
11698         }
11699
11700         mac_filter = f->mac_info;
11701         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11702         if (ret != I40E_SUCCESS) {
11703                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11704                 return -EIO;
11705         }
11706         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11707         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11708         if (ret != I40E_SUCCESS) {
11709                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11710                 return -EIO;
11711         }
11712         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11713
11714         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11715                                         mac_addr->addr_bytes, NULL);
11716         if (ret != I40E_SUCCESS) {
11717                 PMD_DRV_LOG(ERR, "Failed to change mac");
11718                 return -EIO;
11719         }
11720
11721         return 0;
11722 }
11723
11724 static int
11725 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11726 {
11727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11728         struct rte_eth_dev_data *dev_data = pf->dev_data;
11729         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11730         int ret = 0;
11731
11732         /* check if mtu is within the allowed range */
11733         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11734                 return -EINVAL;
11735
11736         /* mtu setting is forbidden if port is start */
11737         if (dev_data->dev_started) {
11738                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11739                             dev_data->port_id);
11740                 return -EBUSY;
11741         }
11742
11743         if (frame_size > ETHER_MAX_LEN)
11744                 dev_data->dev_conf.rxmode.offloads |=
11745                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11746         else
11747                 dev_data->dev_conf.rxmode.offloads &=
11748                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11749
11750         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11751
11752         return ret;
11753 }
11754
11755 /* Restore ethertype filter */
11756 static void
11757 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11758 {
11759         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11760         struct i40e_ethertype_filter_list
11761                 *ethertype_list = &pf->ethertype.ethertype_list;
11762         struct i40e_ethertype_filter *f;
11763         struct i40e_control_filter_stats stats;
11764         uint16_t flags;
11765
11766         TAILQ_FOREACH(f, ethertype_list, rules) {
11767                 flags = 0;
11768                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11769                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11770                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11771                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11772                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11773
11774                 memset(&stats, 0, sizeof(stats));
11775                 i40e_aq_add_rem_control_packet_filter(hw,
11776                                             f->input.mac_addr.addr_bytes,
11777                                             f->input.ether_type,
11778                                             flags, pf->main_vsi->seid,
11779                                             f->queue, 1, &stats, NULL);
11780         }
11781         PMD_DRV_LOG(INFO, "Ethertype filter:"
11782                     " mac_etype_used = %u, etype_used = %u,"
11783                     " mac_etype_free = %u, etype_free = %u",
11784                     stats.mac_etype_used, stats.etype_used,
11785                     stats.mac_etype_free, stats.etype_free);
11786 }
11787
11788 /* Restore tunnel filter */
11789 static void
11790 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11791 {
11792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11793         struct i40e_vsi *vsi;
11794         struct i40e_pf_vf *vf;
11795         struct i40e_tunnel_filter_list
11796                 *tunnel_list = &pf->tunnel.tunnel_list;
11797         struct i40e_tunnel_filter *f;
11798         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11799         bool big_buffer = 0;
11800
11801         TAILQ_FOREACH(f, tunnel_list, rules) {
11802                 if (!f->is_to_vf)
11803                         vsi = pf->main_vsi;
11804                 else {
11805                         vf = &pf->vfs[f->vf_id];
11806                         vsi = vf->vsi;
11807                 }
11808                 memset(&cld_filter, 0, sizeof(cld_filter));
11809                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11810                         (struct ether_addr *)&cld_filter.element.outer_mac);
11811                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11812                         (struct ether_addr *)&cld_filter.element.inner_mac);
11813                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11814                 cld_filter.element.flags = f->input.flags;
11815                 cld_filter.element.tenant_id = f->input.tenant_id;
11816                 cld_filter.element.queue_number = f->queue;
11817                 rte_memcpy(cld_filter.general_fields,
11818                            f->input.general_fields,
11819                            sizeof(f->input.general_fields));
11820
11821                 if (((f->input.flags &
11822                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11823                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11824                     ((f->input.flags &
11825                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11826                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11827                     ((f->input.flags &
11828                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11829                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11830                         big_buffer = 1;
11831
11832                 if (big_buffer)
11833                         i40e_aq_add_cloud_filters_big_buffer(hw,
11834                                              vsi->seid, &cld_filter, 1);
11835                 else
11836                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11837                                                   &cld_filter.element, 1);
11838         }
11839 }
11840
11841 /* Restore rss filter */
11842 static inline void
11843 i40e_rss_filter_restore(struct i40e_pf *pf)
11844 {
11845         struct i40e_rte_flow_rss_conf *conf =
11846                                         &pf->rss_info;
11847         if (conf->conf.queue_num)
11848                 i40e_config_rss_filter(pf, conf, TRUE);
11849 }
11850
11851 static void
11852 i40e_filter_restore(struct i40e_pf *pf)
11853 {
11854         i40e_ethertype_filter_restore(pf);
11855         i40e_tunnel_filter_restore(pf);
11856         i40e_fdir_filter_restore(pf);
11857         i40e_rss_filter_restore(pf);
11858 }
11859
11860 static bool
11861 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11862 {
11863         if (strcmp(dev->device->driver->name, drv->driver.name))
11864                 return false;
11865
11866         return true;
11867 }
11868
11869 bool
11870 is_i40e_supported(struct rte_eth_dev *dev)
11871 {
11872         return is_device_supported(dev, &rte_i40e_pmd);
11873 }
11874
11875 struct i40e_customized_pctype*
11876 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11877 {
11878         int i;
11879
11880         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11881                 if (pf->customized_pctype[i].index == index)
11882                         return &pf->customized_pctype[i];
11883         }
11884         return NULL;
11885 }
11886
11887 static int
11888 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11889                               uint32_t pkg_size, uint32_t proto_num,
11890                               struct rte_pmd_i40e_proto_info *proto,
11891                               enum rte_pmd_i40e_package_op op)
11892 {
11893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11894         uint32_t pctype_num;
11895         struct rte_pmd_i40e_ptype_info *pctype;
11896         uint32_t buff_size;
11897         struct i40e_customized_pctype *new_pctype = NULL;
11898         uint8_t proto_id;
11899         uint8_t pctype_value;
11900         char name[64];
11901         uint32_t i, j, n;
11902         int ret;
11903
11904         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11905             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11906                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11907                 return -1;
11908         }
11909
11910         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11911                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11912                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11913         if (ret) {
11914                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11915                 return -1;
11916         }
11917         if (!pctype_num) {
11918                 PMD_DRV_LOG(INFO, "No new pctype added");
11919                 return -1;
11920         }
11921
11922         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11923         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11924         if (!pctype) {
11925                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11926                 return -1;
11927         }
11928         /* get information about new pctype list */
11929         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11930                                         (uint8_t *)pctype, buff_size,
11931                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11932         if (ret) {
11933                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11934                 rte_free(pctype);
11935                 return -1;
11936         }
11937
11938         /* Update customized pctype. */
11939         for (i = 0; i < pctype_num; i++) {
11940                 pctype_value = pctype[i].ptype_id;
11941                 memset(name, 0, sizeof(name));
11942                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11943                         proto_id = pctype[i].protocols[j];
11944                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11945                                 continue;
11946                         for (n = 0; n < proto_num; n++) {
11947                                 if (proto[n].proto_id != proto_id)
11948                                         continue;
11949                                 strcat(name, proto[n].name);
11950                                 strcat(name, "_");
11951                                 break;
11952                         }
11953                 }
11954                 name[strlen(name) - 1] = '\0';
11955                 if (!strcmp(name, "GTPC"))
11956                         new_pctype =
11957                                 i40e_find_customized_pctype(pf,
11958                                                       I40E_CUSTOMIZED_GTPC);
11959                 else if (!strcmp(name, "GTPU_IPV4"))
11960                         new_pctype =
11961                                 i40e_find_customized_pctype(pf,
11962                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11963                 else if (!strcmp(name, "GTPU_IPV6"))
11964                         new_pctype =
11965                                 i40e_find_customized_pctype(pf,
11966                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11967                 else if (!strcmp(name, "GTPU"))
11968                         new_pctype =
11969                                 i40e_find_customized_pctype(pf,
11970                                                       I40E_CUSTOMIZED_GTPU);
11971                 if (new_pctype) {
11972                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11973                                 new_pctype->pctype = pctype_value;
11974                                 new_pctype->valid = true;
11975                         } else {
11976                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11977                                 new_pctype->valid = false;
11978                         }
11979                 }
11980         }
11981
11982         rte_free(pctype);
11983         return 0;
11984 }
11985
11986 static int
11987 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11988                              uint32_t pkg_size, uint32_t proto_num,
11989                              struct rte_pmd_i40e_proto_info *proto,
11990                              enum rte_pmd_i40e_package_op op)
11991 {
11992         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11993         uint16_t port_id = dev->data->port_id;
11994         uint32_t ptype_num;
11995         struct rte_pmd_i40e_ptype_info *ptype;
11996         uint32_t buff_size;
11997         uint8_t proto_id;
11998         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11999         uint32_t i, j, n;
12000         bool in_tunnel;
12001         int ret;
12002
12003         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12004             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12005                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12006                 return -1;
12007         }
12008
12009         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12010                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12011                 return 0;
12012         }
12013
12014         /* get information about new ptype num */
12015         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12016                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12017                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12018         if (ret) {
12019                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12020                 return ret;
12021         }
12022         if (!ptype_num) {
12023                 PMD_DRV_LOG(INFO, "No new ptype added");
12024                 return -1;
12025         }
12026
12027         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12028         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12029         if (!ptype) {
12030                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12031                 return -1;
12032         }
12033
12034         /* get information about new ptype list */
12035         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12036                                         (uint8_t *)ptype, buff_size,
12037                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12038         if (ret) {
12039                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12040                 rte_free(ptype);
12041                 return ret;
12042         }
12043
12044         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12045         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12046         if (!ptype_mapping) {
12047                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12048                 rte_free(ptype);
12049                 return -1;
12050         }
12051
12052         /* Update ptype mapping table. */
12053         for (i = 0; i < ptype_num; i++) {
12054                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12055                 ptype_mapping[i].sw_ptype = 0;
12056                 in_tunnel = false;
12057                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12058                         proto_id = ptype[i].protocols[j];
12059                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12060                                 continue;
12061                         for (n = 0; n < proto_num; n++) {
12062                                 if (proto[n].proto_id != proto_id)
12063                                         continue;
12064                                 memset(name, 0, sizeof(name));
12065                                 strcpy(name, proto[n].name);
12066                                 if (!strncasecmp(name, "PPPOE", 5))
12067                                         ptype_mapping[i].sw_ptype |=
12068                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12069                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12070                                          !in_tunnel) {
12071                                         ptype_mapping[i].sw_ptype |=
12072                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12073                                         ptype_mapping[i].sw_ptype |=
12074                                                 RTE_PTYPE_L4_FRAG;
12075                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12076                                            in_tunnel) {
12077                                         ptype_mapping[i].sw_ptype |=
12078                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12079                                         ptype_mapping[i].sw_ptype |=
12080                                                 RTE_PTYPE_INNER_L4_FRAG;
12081                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12082                                         ptype_mapping[i].sw_ptype |=
12083                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12084                                         in_tunnel = true;
12085                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12086                                            !in_tunnel)
12087                                         ptype_mapping[i].sw_ptype |=
12088                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12089                                 else if (!strncasecmp(name, "IPV4", 4) &&
12090                                          in_tunnel)
12091                                         ptype_mapping[i].sw_ptype |=
12092                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12093                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12094                                          !in_tunnel) {
12095                                         ptype_mapping[i].sw_ptype |=
12096                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12097                                         ptype_mapping[i].sw_ptype |=
12098                                                 RTE_PTYPE_L4_FRAG;
12099                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12100                                            in_tunnel) {
12101                                         ptype_mapping[i].sw_ptype |=
12102                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12103                                         ptype_mapping[i].sw_ptype |=
12104                                                 RTE_PTYPE_INNER_L4_FRAG;
12105                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12106                                         ptype_mapping[i].sw_ptype |=
12107                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12108                                         in_tunnel = true;
12109                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12110                                            !in_tunnel)
12111                                         ptype_mapping[i].sw_ptype |=
12112                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12113                                 else if (!strncasecmp(name, "IPV6", 4) &&
12114                                          in_tunnel)
12115                                         ptype_mapping[i].sw_ptype |=
12116                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12117                                 else if (!strncasecmp(name, "UDP", 3) &&
12118                                          !in_tunnel)
12119                                         ptype_mapping[i].sw_ptype |=
12120                                                 RTE_PTYPE_L4_UDP;
12121                                 else if (!strncasecmp(name, "UDP", 3) &&
12122                                          in_tunnel)
12123                                         ptype_mapping[i].sw_ptype |=
12124                                                 RTE_PTYPE_INNER_L4_UDP;
12125                                 else if (!strncasecmp(name, "TCP", 3) &&
12126                                          !in_tunnel)
12127                                         ptype_mapping[i].sw_ptype |=
12128                                                 RTE_PTYPE_L4_TCP;
12129                                 else if (!strncasecmp(name, "TCP", 3) &&
12130                                          in_tunnel)
12131                                         ptype_mapping[i].sw_ptype |=
12132                                                 RTE_PTYPE_INNER_L4_TCP;
12133                                 else if (!strncasecmp(name, "SCTP", 4) &&
12134                                          !in_tunnel)
12135                                         ptype_mapping[i].sw_ptype |=
12136                                                 RTE_PTYPE_L4_SCTP;
12137                                 else if (!strncasecmp(name, "SCTP", 4) &&
12138                                          in_tunnel)
12139                                         ptype_mapping[i].sw_ptype |=
12140                                                 RTE_PTYPE_INNER_L4_SCTP;
12141                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12142                                           !strncasecmp(name, "ICMPV6", 6)) &&
12143                                          !in_tunnel)
12144                                         ptype_mapping[i].sw_ptype |=
12145                                                 RTE_PTYPE_L4_ICMP;
12146                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12147                                           !strncasecmp(name, "ICMPV6", 6)) &&
12148                                          in_tunnel)
12149                                         ptype_mapping[i].sw_ptype |=
12150                                                 RTE_PTYPE_INNER_L4_ICMP;
12151                                 else if (!strncasecmp(name, "GTPC", 4)) {
12152                                         ptype_mapping[i].sw_ptype |=
12153                                                 RTE_PTYPE_TUNNEL_GTPC;
12154                                         in_tunnel = true;
12155                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12156                                         ptype_mapping[i].sw_ptype |=
12157                                                 RTE_PTYPE_TUNNEL_GTPU;
12158                                         in_tunnel = true;
12159                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12160                                         ptype_mapping[i].sw_ptype |=
12161                                                 RTE_PTYPE_TUNNEL_GRENAT;
12162                                         in_tunnel = true;
12163                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12164                                            !strncasecmp(name, "L2TPV2", 6)) {
12165                                         ptype_mapping[i].sw_ptype |=
12166                                                 RTE_PTYPE_TUNNEL_L2TP;
12167                                         in_tunnel = true;
12168                                 }
12169
12170                                 break;
12171                         }
12172                 }
12173         }
12174
12175         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12176                                                 ptype_num, 0);
12177         if (ret)
12178                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12179
12180         rte_free(ptype_mapping);
12181         rte_free(ptype);
12182         return ret;
12183 }
12184
12185 void
12186 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12187                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12188 {
12189         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12190         uint32_t proto_num;
12191         struct rte_pmd_i40e_proto_info *proto;
12192         uint32_t buff_size;
12193         uint32_t i;
12194         int ret;
12195
12196         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12197             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12198                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12199                 return;
12200         }
12201
12202         /* get information about protocol number */
12203         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12204                                        (uint8_t *)&proto_num, sizeof(proto_num),
12205                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12206         if (ret) {
12207                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12208                 return;
12209         }
12210         if (!proto_num) {
12211                 PMD_DRV_LOG(INFO, "No new protocol added");
12212                 return;
12213         }
12214
12215         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12216         proto = rte_zmalloc("new_proto", buff_size, 0);
12217         if (!proto) {
12218                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12219                 return;
12220         }
12221
12222         /* get information about protocol list */
12223         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12224                                         (uint8_t *)proto, buff_size,
12225                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12226         if (ret) {
12227                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12228                 rte_free(proto);
12229                 return;
12230         }
12231
12232         /* Check if GTP is supported. */
12233         for (i = 0; i < proto_num; i++) {
12234                 if (!strncmp(proto[i].name, "GTP", 3)) {
12235                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12236                                 pf->gtp_support = true;
12237                         else
12238                                 pf->gtp_support = false;
12239                         break;
12240                 }
12241         }
12242
12243         /* Update customized pctype info */
12244         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12245                                             proto_num, proto, op);
12246         if (ret)
12247                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12248
12249         /* Update customized ptype info */
12250         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12251                                            proto_num, proto, op);
12252         if (ret)
12253                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12254
12255         rte_free(proto);
12256 }
12257
12258 /* Create a QinQ cloud filter
12259  *
12260  * The Fortville NIC has limited resources for tunnel filters,
12261  * so we can only reuse existing filters.
12262  *
12263  * In step 1 we define which Field Vector fields can be used for
12264  * filter types.
12265  * As we do not have the inner tag defined as a field,
12266  * we have to define it first, by reusing one of L1 entries.
12267  *
12268  * In step 2 we are replacing one of existing filter types with
12269  * a new one for QinQ.
12270  * As we reusing L1 and replacing L2, some of the default filter
12271  * types will disappear,which depends on L1 and L2 entries we reuse.
12272  *
12273  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12274  *
12275  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12276  *              later when we define the cloud filter.
12277  *      a.      Valid_flags.replace_cloud = 0
12278  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12279  *      c.      New_filter = 0x10
12280  *      d.      TR bit = 0xff (optional, not used here)
12281  *      e.      Buffer – 2 entries:
12282  *              i.      Byte 0 = 8 (outer vlan FV index).
12283  *                      Byte 1 = 0 (rsv)
12284  *                      Byte 2-3 = 0x0fff
12285  *              ii.     Byte 0 = 37 (inner vlan FV index).
12286  *                      Byte 1 =0 (rsv)
12287  *                      Byte 2-3 = 0x0fff
12288  *
12289  * Step 2:
12290  * 2.   Create cloud filter using two L1 filters entries: stag and
12291  *              new filter(outer vlan+ inner vlan)
12292  *      a.      Valid_flags.replace_cloud = 1
12293  *      b.      Old_filter = 1 (instead of outer IP)
12294  *      c.      New_filter = 0x10
12295  *      d.      Buffer – 2 entries:
12296  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12297  *                      Byte 1-3 = 0 (rsv)
12298  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12299  *                      Byte 9-11 = 0 (rsv)
12300  */
12301 static int
12302 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12303 {
12304         int ret = -ENOTSUP;
12305         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12306         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12307         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12308         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12309
12310         if (pf->support_multi_driver) {
12311                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12312                 return ret;
12313         }
12314
12315         /* Init */
12316         memset(&filter_replace, 0,
12317                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12318         memset(&filter_replace_buf, 0,
12319                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12320
12321         /* create L1 filter */
12322         filter_replace.old_filter_type =
12323                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12324         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12325         filter_replace.tr_bit = 0;
12326
12327         /* Prepare the buffer, 2 entries */
12328         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12329         filter_replace_buf.data[0] |=
12330                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12331         /* Field Vector 12b mask */
12332         filter_replace_buf.data[2] = 0xff;
12333         filter_replace_buf.data[3] = 0x0f;
12334         filter_replace_buf.data[4] =
12335                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12336         filter_replace_buf.data[4] |=
12337                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12338         /* Field Vector 12b mask */
12339         filter_replace_buf.data[6] = 0xff;
12340         filter_replace_buf.data[7] = 0x0f;
12341         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12342                         &filter_replace_buf);
12343         if (ret != I40E_SUCCESS)
12344                 return ret;
12345
12346         if (filter_replace.old_filter_type !=
12347             filter_replace.new_filter_type)
12348                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12349                             " original: 0x%x, new: 0x%x",
12350                             dev->device->name,
12351                             filter_replace.old_filter_type,
12352                             filter_replace.new_filter_type);
12353
12354         /* Apply the second L2 cloud filter */
12355         memset(&filter_replace, 0,
12356                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12357         memset(&filter_replace_buf, 0,
12358                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12359
12360         /* create L2 filter, input for L2 filter will be L1 filter  */
12361         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12362         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12363         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12364
12365         /* Prepare the buffer, 2 entries */
12366         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12367         filter_replace_buf.data[0] |=
12368                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12369         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12370         filter_replace_buf.data[4] |=
12371                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12372         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12373                         &filter_replace_buf);
12374         if (!ret && (filter_replace.old_filter_type !=
12375                      filter_replace.new_filter_type))
12376                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12377                             " original: 0x%x, new: 0x%x",
12378                             dev->device->name,
12379                             filter_replace.old_filter_type,
12380                             filter_replace.new_filter_type);
12381
12382         return ret;
12383 }
12384
12385 int
12386 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12387                    const struct rte_flow_action_rss *in)
12388 {
12389         if (in->key_len > RTE_DIM(out->key) ||
12390             in->queue_num > RTE_DIM(out->queue))
12391                 return -EINVAL;
12392         out->conf = (struct rte_flow_action_rss){
12393                 .func = in->func,
12394                 .level = in->level,
12395                 .types = in->types,
12396                 .key_len = in->key_len,
12397                 .queue_num = in->queue_num,
12398                 .key = memcpy(out->key, in->key, in->key_len),
12399                 .queue = memcpy(out->queue, in->queue,
12400                                 sizeof(*in->queue) * in->queue_num),
12401         };
12402         return 0;
12403 }
12404
12405 int
12406 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12407                      const struct rte_flow_action_rss *with)
12408 {
12409         return (comp->func == with->func &&
12410                 comp->level == with->level &&
12411                 comp->types == with->types &&
12412                 comp->key_len == with->key_len &&
12413                 comp->queue_num == with->queue_num &&
12414                 !memcmp(comp->key, with->key, with->key_len) &&
12415                 !memcmp(comp->queue, with->queue,
12416                         sizeof(*with->queue) * with->queue_num));
12417 }
12418
12419 int
12420 i40e_config_rss_filter(struct i40e_pf *pf,
12421                 struct i40e_rte_flow_rss_conf *conf, bool add)
12422 {
12423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12424         uint32_t i, lut = 0;
12425         uint16_t j, num;
12426         struct rte_eth_rss_conf rss_conf = {
12427                 .rss_key = conf->conf.key_len ?
12428                         (void *)(uintptr_t)conf->conf.key : NULL,
12429                 .rss_key_len = conf->conf.key_len,
12430                 .rss_hf = conf->conf.types,
12431         };
12432         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12433
12434         if (!add) {
12435                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12436                         i40e_pf_disable_rss(pf);
12437                         memset(rss_info, 0,
12438                                 sizeof(struct i40e_rte_flow_rss_conf));
12439                         return 0;
12440                 }
12441                 return -EINVAL;
12442         }
12443
12444         if (rss_info->conf.queue_num)
12445                 return -EINVAL;
12446
12447         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12448          * It's necessary to calculate the actual PF queues that are configured.
12449          */
12450         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12451                 num = i40e_pf_calc_configured_queues_num(pf);
12452         else
12453                 num = pf->dev_data->nb_rx_queues;
12454
12455         num = RTE_MIN(num, conf->conf.queue_num);
12456         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12457                         num);
12458
12459         if (num == 0) {
12460                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12461                 return -ENOTSUP;
12462         }
12463
12464         /* Fill in redirection table */
12465         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12466                 if (j == num)
12467                         j = 0;
12468                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12469                         hw->func_caps.rss_table_entry_width) - 1));
12470                 if ((i & 3) == 3)
12471                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12472         }
12473
12474         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12475                 i40e_pf_disable_rss(pf);
12476                 return 0;
12477         }
12478         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12479                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12480                 /* Random default keys */
12481                 static uint32_t rss_key_default[] = {0x6b793944,
12482                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12483                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12484                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12485
12486                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12487                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12488                                                         sizeof(uint32_t);
12489         }
12490
12491         i40e_hw_rss_hash_set(pf, &rss_conf);
12492
12493         if (i40e_rss_conf_init(rss_info, &conf->conf))
12494                 return -EINVAL;
12495
12496         return 0;
12497 }
12498
12499 RTE_INIT(i40e_init_log)
12500 {
12501         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12502         if (i40e_logtype_init >= 0)
12503                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12504         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12505         if (i40e_logtype_driver >= 0)
12506                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12507 }
12508
12509 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12510                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12511                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");