drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define I40E_CLEAR_PXE_WAIT_MS     200
  67
  68 /* Maximun number of capability elements */
  69 #define I40E_MAX_CAP_ELE_NUM       128
  70
  71 /* Wait count and inteval */
  72 #define I40E_CHK_Q_ENA_COUNT       1000
  73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  74
  75 /* Maximun number of VSI */
  76 #define I40E_MAX_NUM_VSIS          (384UL)
  77
  78 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  79
  80 /* Flow control default timer */
  81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  82
  83 /* Flow control default high water */
  84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  85
  86 /* Flow control default low water */
  87 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Receive Average Packet Size in Byte*/
  99 #define I40E_PACKET_AVERAGE_SIZE 128
 100
 101 /* Mask of PF interrupt causes */
 102 #define I40E_PFINT_ICR0_ENA_MASK ( \
 103                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 104                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 105                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 106                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 107                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 109                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 113
 114 #define I40E_FLOW_TYPES ( \
 115         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 116         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 126
 127 /* Additional timesync values. */
 128 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA     0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 133 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 134
 135 #define I40E_MAX_PERCENT            100
 136 #define I40E_DEFAULT_DCB_APP_NUM    1
 137 #define I40E_DEFAULT_DCB_APP_PRIO   3
 138
 139 #define I40E_INSET_NONE            0x00000000000000000ULL
 140
 141 /* bit0 ~ bit 7 */
 142 #define I40E_INSET_DMAC            0x0000000000000001ULL
 143 #define I40E_INSET_SMAC            0x0000000000000002ULL
 144 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 145 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 146 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 147
 148 /* bit 8 ~ bit 15 */
 149 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 150 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 151 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 152 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 153 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 154 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 155 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 156
 157 /* bit 16 ~ bit 31 */
 158 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 159 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 160 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 161 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 162 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 163 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 164 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 165 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 166
 167 /* bit 32 ~ bit 47, tunnel fields */
 168 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 169 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 170 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 171 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 172 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 173 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 174
 175 /* bit 48 ~ bit 55 */
 176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 177
 178 /* bit 56 ~ bit 63, Flex Payload */
 179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD \
 188         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 189         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 190         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 191         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 192
 193 /**
 194  * Below are values for writing un-exposed registers suggested
 195  * by silicon experts
 196  */
 197 /* Destination MAC address */
 198 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 199 /* Source MAC address */
 200 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 201 /* VLAN tag in the outer L2 header */
 202 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0080000000000000ULL
 203 /* VLAN tag in the inner L2 header */
 204 #define I40E_REG_INSET_L2_INNER_VLAN             0x0100000000000000ULL
 205 /* Source IPv4 address */
 206 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 207 /* Destination IPv4 address */
 208 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 209 /* IPv4 Type of Service (TOS) */
 210 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 211 /* IPv4 Protocol */
 212 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 213 /* IPv4 Time to Live */
 214 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 215 /* Source IPv6 address */
 216 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 217 /* Destination IPv6 address */
 218 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 219 /* IPv6 Traffic Class (TC) */
 220 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 221 /* IPv6 Next Header */
 222 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 223 /* IPv6 Hop Limit */
 224 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 225 /* Source L4 port */
 226 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 227 /* Destination L4 port */
 228 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 229 /* SCTP verification tag */
 230 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 231 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 232 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 233 /* Source port of tunneling UDP */
 234 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 235 /* Destination port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 237 /* UDP Tunneling ID, NVGRE/GRE key */
 238 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 239 /* Last ether type */
 240 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 241 /* Tunneling outer destination IPv4 address */
 242 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 243 /* Tunneling outer destination IPv6 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 245 /* 1st word of flex payload */
 246 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 247 /* 2nd word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 249 /* 3rd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 251 /* 4th word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 253 /* 5th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 255 /* 6th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 257 /* 7th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 259 /* 8th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 261 /* all 8 words flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 263 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 264
 265 #define I40E_TRANSLATE_INSET 0
 266 #define I40E_TRANSLATE_REG   1
 267
 268 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 269 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 270 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 272 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 273 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 274
 275 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 276 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 277 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 278         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 279
 280 /* PCI offset for querying capability */
 281 #define PCI_DEV_CAP_REG            0xA4
 282 /* PCI offset for enabling/disabling Extended Tag */
 283 #define PCI_DEV_CTRL_REG           0xA8
 284 /* Bit mask of Extended Tag capability */
 285 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 286 /* Bit shift of Extended Tag enable/disable */
 287 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 288 /* Bit mask of Extended Tag enable/disable */
 289 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 290
 291 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 292 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 293 static int i40e_dev_configure(struct rte_eth_dev *dev);
 294 static int i40e_dev_start(struct rte_eth_dev *dev);
 295 static void i40e_dev_stop(struct rte_eth_dev *dev);
 296 static void i40e_dev_close(struct rte_eth_dev *dev);
 297 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 298 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 299 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 300 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 301 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 302 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 303 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 304                                struct rte_eth_stats *stats);
 305 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 306                                struct rte_eth_xstats *xstats, unsigned n);
 307 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 308 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 309                                             uint16_t queue_id,
 310                                             uint8_t stat_idx,
 311                                             uint8_t is_rx);
 312 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 313                               struct rte_eth_dev_info *dev_info);
 314 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 315                                 uint16_t vlan_id,
 316                                 int on);
 317 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 318                               enum rte_vlan_type vlan_type,
 319                               uint16_t tpid);
 320 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 321 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 322                                       uint16_t queue,
 323                                       int on);
 324 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 325 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 326 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 327 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 328                               struct rte_eth_fc_conf *fc_conf);
 329 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 330                               struct rte_eth_fc_conf *fc_conf);
 331 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 332                                        struct rte_eth_pfc_conf *pfc_conf);
 333 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 334                           struct ether_addr *mac_addr,
 335                           uint32_t index,
 336                           uint32_t pool);
 337 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 338 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 339                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 340                                     uint16_t reta_size);
 341 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 342                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 343                                    uint16_t reta_size);
 344
 345 static int i40e_get_cap(struct i40e_hw *hw);
 346 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 347 static int i40e_pf_setup(struct i40e_pf *pf);
 348 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 349 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 350 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 351 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 352 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 353                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 354 static void i40e_stat_update_48(struct i40e_hw *hw,
 355                                uint32_t hireg,
 356                                uint32_t loreg,
 357                                bool offset_loaded,
 358                                uint64_t *offset,
 359                                uint64_t *stat);
 360 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 361 static void i40e_dev_interrupt_handler(
 362                 __rte_unused struct rte_intr_handle *handle, void *param);
 363 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 364                                 uint32_t base, uint32_t num);
 365 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 366 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 367                         uint32_t base);
 368 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 369                         uint16_t num);
 370 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 371 static int i40e_veb_release(struct i40e_veb *veb);
 372 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 373                                                 struct i40e_vsi *vsi);
 374 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 375 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 376 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 377                                              struct i40e_macvlan_filter *mv_f,
 378                                              int num,
 379                                              struct ether_addr *addr);
 380 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 381                                              struct i40e_macvlan_filter *mv_f,
 382                                              int num,
 383                                              uint16_t vlan);
 384 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 385 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 386                                     struct rte_eth_rss_conf *rss_conf);
 387 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 388                                       struct rte_eth_rss_conf *rss_conf);
 389 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 390                                         struct rte_eth_udp_tunnel *udp_tunnel);
 391 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 392                                         struct rte_eth_udp_tunnel *udp_tunnel);
 393 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 394 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 395                         struct rte_eth_ethertype_filter *filter,
 396                         bool add);
 397 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 398                                 enum rte_filter_op filter_op,
 399                                 void *arg);
 400 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 401                                 enum rte_filter_type filter_type,
 402                                 enum rte_filter_op filter_op,
 403                                 void *arg);
 404 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 405                                   struct rte_eth_dcb_info *dcb_info);
 406 static void i40e_configure_registers(struct i40e_hw *hw);
 407 static void i40e_hw_init(struct rte_eth_dev *dev);
 408 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 409 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 410                         struct rte_eth_mirror_conf *mirror_conf,
 411                         uint8_t sw_id, uint8_t on);
 412 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 413
 414 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 415 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 416 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 417                                            struct timespec *timestamp,
 418                                            uint32_t flags);
 419 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 420                                            struct timespec *timestamp);
 421 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 422
 423 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 424
 425 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 426                                    struct timespec *timestamp);
 427 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 428                                     const struct timespec *timestamp);
 429
 430 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 431                                          uint16_t queue_id);
 432 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 433                                           uint16_t queue_id);
 434
 435 static int i40e_get_reg_length(struct rte_eth_dev *dev);
 436
 437 static int i40e_get_regs(struct rte_eth_dev *dev,
 438                          struct rte_dev_reg_info *regs);
 439
 440 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 441
 442 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 443                            struct rte_dev_eeprom_info *eeprom);
 444
 445 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 446                                       struct ether_addr *mac_addr);
 447
 448 static const struct rte_pci_id pci_id_i40e_map[] = {
 449 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 450 #include "rte_pci_dev_ids.h"
 451 { .vendor_id = 0, /* sentinel */ },
 452 };
 453
 454 static const struct eth_dev_ops i40e_eth_dev_ops = {
 455         .dev_configure                = i40e_dev_configure,
 456         .dev_start                    = i40e_dev_start,
 457         .dev_stop                     = i40e_dev_stop,
 458         .dev_close                    = i40e_dev_close,
 459         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 460         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 461         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 462         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 463         .dev_set_link_up              = i40e_dev_set_link_up,
 464         .dev_set_link_down            = i40e_dev_set_link_down,
 465         .link_update                  = i40e_dev_link_update,
 466         .stats_get                    = i40e_dev_stats_get,
 467         .xstats_get                   = i40e_dev_xstats_get,
 468         .stats_reset                  = i40e_dev_stats_reset,
 469         .xstats_reset                 = i40e_dev_stats_reset,
 470         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 471         .dev_infos_get                = i40e_dev_info_get,
 472         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 473         .vlan_filter_set              = i40e_vlan_filter_set,
 474         .vlan_tpid_set                = i40e_vlan_tpid_set,
 475         .vlan_offload_set             = i40e_vlan_offload_set,
 476         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 477         .vlan_pvid_set                = i40e_vlan_pvid_set,
 478         .rx_queue_start               = i40e_dev_rx_queue_start,
 479         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 480         .tx_queue_start               = i40e_dev_tx_queue_start,
 481         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 482         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 483         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 484         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 485         .rx_queue_release             = i40e_dev_rx_queue_release,
 486         .rx_queue_count               = i40e_dev_rx_queue_count,
 487         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 488         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 489         .tx_queue_release             = i40e_dev_tx_queue_release,
 490         .dev_led_on                   = i40e_dev_led_on,
 491         .dev_led_off                  = i40e_dev_led_off,
 492         .flow_ctrl_get                = i40e_flow_ctrl_get,
 493         .flow_ctrl_set                = i40e_flow_ctrl_set,
 494         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 495         .mac_addr_add                 = i40e_macaddr_add,
 496         .mac_addr_remove              = i40e_macaddr_remove,
 497         .reta_update                  = i40e_dev_rss_reta_update,
 498         .reta_query                   = i40e_dev_rss_reta_query,
 499         .rss_hash_update              = i40e_dev_rss_hash_update,
 500         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 501         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 502         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 503         .filter_ctrl                  = i40e_dev_filter_ctrl,
 504         .rxq_info_get                 = i40e_rxq_info_get,
 505         .txq_info_get                 = i40e_txq_info_get,
 506         .mirror_rule_set              = i40e_mirror_rule_set,
 507         .mirror_rule_reset            = i40e_mirror_rule_reset,
 508         .timesync_enable              = i40e_timesync_enable,
 509         .timesync_disable             = i40e_timesync_disable,
 510         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 511         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 512         .get_dcb_info                 = i40e_dev_get_dcb_info,
 513         .timesync_adjust_time         = i40e_timesync_adjust_time,
 514         .timesync_read_time           = i40e_timesync_read_time,
 515         .timesync_write_time          = i40e_timesync_write_time,
 516         .get_reg_length               = i40e_get_reg_length,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .mac_addr_set                 = i40e_set_default_mac_addr,
 521 };
 522
 523 /* store statistics names and its offset in stats structure */
 524 struct rte_i40e_xstats_name_off {
 525         char name[RTE_ETH_XSTATS_NAME_SIZE];
 526         unsigned offset;
 527 };
 528
 529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 530         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 531         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 532         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 533         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 534         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 535                 rx_unknown_protocol)},
 536         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 537         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 538         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 539         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 540 };
 541
 542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 543                 sizeof(rte_i40e_stats_strings[0]))
 544
 545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 546         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 547                 tx_dropped_link_down)},
 548         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 549         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 550                 illegal_bytes)},
 551         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 552         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_local_faults)},
 554         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_remote_faults)},
 556         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_length_errors)},
 558         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 559         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 560         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 561         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 562         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 563         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_127)},
 565         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_255)},
 567         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_511)},
 569         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1023)},
 571         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1522)},
 573         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_big)},
 575         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_undersize)},
 577         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_oversize)},
 579         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 580                 mac_short_packet_dropped)},
 581         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_fragments)},
 583         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 584         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 585         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_127)},
 587         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_255)},
 589         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_511)},
 591         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1023)},
 593         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1522)},
 595         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_big)},
 597         {"rx_flow_director_atr_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 599         {"rx_flow_director_sb_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 601         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_status)},
 603         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_status)},
 605         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_count)},
 607         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_count)},
 609 };
 610
 611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 612                 sizeof(rte_i40e_hw_port_strings[0]))
 613
 614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 615         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xon_rx)},
 617         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xoff_rx)},
 619 };
 620
 621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 622                 sizeof(rte_i40e_rxq_prio_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_tx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_tx)},
 629         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_2_xoff)},
 631 };
 632
 633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 634                 sizeof(rte_i40e_txq_prio_strings[0]))
 635
 636 static struct eth_driver rte_i40e_pmd = {
 637         .pci_drv = {
 638                 .name = "rte_i40e_pmd",
 639                 .id_table = pci_id_i40e_map,
 640                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 641                         RTE_PCI_DRV_DETACHABLE,
 642         },
 643         .eth_dev_init = eth_i40e_dev_init,
 644         .eth_dev_uninit = eth_i40e_dev_uninit,
 645         .dev_private_size = sizeof(struct i40e_adapter),
 646 };
 647
 648 static inline int
 649 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 650                                      struct rte_eth_link *link)
 651 {
 652         struct rte_eth_link *dst = link;
 653         struct rte_eth_link *src = &(dev->data->dev_link);
 654
 655         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 656                                         *(uint64_t *)src) == 0)
 657                 return -1;
 658
 659         return 0;
 660 }
 661
 662 static inline int
 663 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 664                                       struct rte_eth_link *link)
 665 {
 666         struct rte_eth_link *dst = &(dev->data->dev_link);
 667         struct rte_eth_link *src = link;
 668
 669         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 670                                         *(uint64_t *)src) == 0)
 671                 return -1;
 672
 673         return 0;
 674 }
 675
 676 /*
 677  * Driver initialization routine.
 678  * Invoked once at EAL init time.
 679  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 680  */
 681 static int
 682 rte_i40e_pmd_init(const char *name __rte_unused,
 683                   const char *params __rte_unused)
 684 {
 685         PMD_INIT_FUNC_TRACE();
 686         rte_eth_driver_register(&rte_i40e_pmd);
 687
 688         return 0;
 689 }
 690
 691 static struct rte_driver rte_i40e_driver = {
 692         .type = PMD_PDEV,
 693         .init = rte_i40e_pmd_init,
 694 };
 695
 696 PMD_REGISTER_DRIVER(rte_i40e_driver);
 697
 698 /*
 699  * Initialize registers for flexible payload, which should be set by NVM.
 700  * This should be removed from code once it is fixed in NVM.
 701  */
 702 #ifndef I40E_GLQF_ORT
 703 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 704 #endif
 705 #ifndef I40E_GLQF_PIT
 706 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 707 #endif
 708
 709 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 710 {
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 713         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 714         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 715         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 716         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 718         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 719         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 720         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 721
 722         /* GLQF_PIT Registers */
 723         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 724         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 725 }
 726
 727 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 728
 729 /*
 730  * Add a ethertype filter to drop all flow control frames transmitted
 731  * from VSIs.
 732 */
 733 static void
 734 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 735 {
 736         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 737         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 738                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 739                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 740         int ret;
 741
 742         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 743                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 744                                 pf->main_vsi_seid, 0,
 745                                 TRUE, NULL, NULL);
 746         if (ret)
 747                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 748                                   " frames from VSIs.");
 749 }
 750
 751 static int
 752 eth_i40e_dev_init(struct rte_eth_dev *dev)
 753 {
 754         struct rte_pci_device *pci_dev;
 755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 757         struct i40e_vsi *vsi;
 758         int ret;
 759         uint32_t len;
 760         uint8_t aq_fail = 0;
 761
 762         PMD_INIT_FUNC_TRACE();
 763
 764         dev->dev_ops = &i40e_eth_dev_ops;
 765         dev->rx_pkt_burst = i40e_recv_pkts;
 766         dev->tx_pkt_burst = i40e_xmit_pkts;
 767
 768         /* for secondary processes, we don't initialise any further as primary
 769          * has already done this work. Only check we don't need a different
 770          * RX function */
 771         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 772                 i40e_set_rx_function(dev);
 773                 i40e_set_tx_function(dev);
 774                 return 0;
 775         }
 776         pci_dev = dev->pci_dev;
 777
 778         rte_eth_copy_pci_info(dev, pci_dev);
 779
 780         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 781         pf->adapter->eth_dev = dev;
 782         pf->dev_data = dev->data;
 783
 784         hw->back = I40E_PF_TO_ADAPTER(pf);
 785         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 786         if (!hw->hw_addr) {
 787                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 788                              "as address is NULL");
 789                 return -ENODEV;
 790         }
 791
 792         hw->vendor_id = pci_dev->id.vendor_id;
 793         hw->device_id = pci_dev->id.device_id;
 794         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 795         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 796         hw->bus.device = pci_dev->addr.devid;
 797         hw->bus.func = pci_dev->addr.function;
 798         hw->adapter_stopped = 0;
 799
 800         /* Make sure all is clean before doing PF reset */
 801         i40e_clear_hw(hw);
 802
 803         /* Initialize the hardware */
 804         i40e_hw_init(dev);
 805
 806         /* Reset here to make sure all is clean for each PF */
 807         ret = i40e_pf_reset(hw);
 808         if (ret) {
 809                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 810                 return ret;
 811         }
 812
 813         /* Initialize the shared code (base driver) */
 814         ret = i40e_init_shared_code(hw);
 815         if (ret) {
 816                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 817                 return ret;
 818         }
 819
 820         /*
 821          * To work around the NVM issue,initialize registers
 822          * for flexible payload by software.
 823          * It should be removed once issues are fixed in NVM.
 824          */
 825         i40e_flex_payload_reg_init(hw);
 826
 827         /* Initialize the input set for filters (hash and fd) to default value */
 828         i40e_filter_input_set_init(pf);
 829
 830         /* Initialize the parameters for adminq */
 831         i40e_init_adminq_parameter(hw);
 832         ret = i40e_init_adminq(hw);
 833         if (ret != I40E_SUCCESS) {
 834                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 835                 return -EIO;
 836         }
 837         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 838                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 839                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 840                      ((hw->nvm.version >> 12) & 0xf),
 841                      ((hw->nvm.version >> 4) & 0xff),
 842                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 843
 844         /* Clear PXE mode */
 845         i40e_clear_pxe_mode(hw);
 846
 847         /*
 848          * On X710, performance number is far from the expectation on recent
 849          * firmware versions. The fix for this issue may not be integrated in
 850          * the following firmware version. So the workaround in software driver
 851          * is needed. It needs to modify the initial values of 3 internal only
 852          * registers. Note that the workaround can be removed when it is fixed
 853          * in firmware in the future.
 854          */
 855         i40e_configure_registers(hw);
 856
 857         /* Get hw capabilities */
 858         ret = i40e_get_cap(hw);
 859         if (ret != I40E_SUCCESS) {
 860                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 861                 goto err_get_capabilities;
 862         }
 863
 864         /* Initialize parameters for PF */
 865         ret = i40e_pf_parameter_init(dev);
 866         if (ret != 0) {
 867                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 868                 goto err_parameter_init;
 869         }
 870
 871         /* Initialize the queue management */
 872         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 873         if (ret < 0) {
 874                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 875                 goto err_qp_pool_init;
 876         }
 877         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 878                                 hw->func_caps.num_msix_vectors - 1);
 879         if (ret < 0) {
 880                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 881                 goto err_msix_pool_init;
 882         }
 883
 884         /* Initialize lan hmc */
 885         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 886                                 hw->func_caps.num_rx_qp, 0, 0);
 887         if (ret != I40E_SUCCESS) {
 888                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 889                 goto err_init_lan_hmc;
 890         }
 891
 892         /* Configure lan hmc */
 893         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 894         if (ret != I40E_SUCCESS) {
 895                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 896                 goto err_configure_lan_hmc;
 897         }
 898
 899         /* Get and check the mac address */
 900         i40e_get_mac_addr(hw, hw->mac.addr);
 901         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 902                 PMD_INIT_LOG(ERR, "mac address is not valid");
 903                 ret = -EIO;
 904                 goto err_get_mac_addr;
 905         }
 906         /* Copy the permanent MAC address */
 907         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 908                         (struct ether_addr *) hw->mac.perm_addr);
 909
 910         /* Disable flow control */
 911         hw->fc.requested_mode = I40E_FC_NONE;
 912         i40e_set_fc(hw, &aq_fail, TRUE);
 913
 914         /* Set the global registers with default ether type value */
 915         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
 916         if (ret != I40E_SUCCESS) {
 917                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 918                              "VLAN ether type");
 919                 goto err_setup_pf_switch;
 920         }
 921         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
 922         if (ret != I40E_SUCCESS) {
 923                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
 924                              "VLAN ether type");
 925                 goto err_setup_pf_switch;
 926         }
 927
 928         /* PF setup, which includes VSI setup */
 929         ret = i40e_pf_setup(pf);
 930         if (ret) {
 931                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 932                 goto err_setup_pf_switch;
 933         }
 934
 935         vsi = pf->main_vsi;
 936
 937         /* Disable double vlan by default */
 938         i40e_vsi_config_double_vlan(vsi, FALSE);
 939
 940         if (!vsi->max_macaddrs)
 941                 len = ETHER_ADDR_LEN;
 942         else
 943                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 944
 945         /* Should be after VSI initialized */
 946         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 947         if (!dev->data->mac_addrs) {
 948                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 949                                         "for storing mac address");
 950                 goto err_mac_alloc;
 951         }
 952         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 953                                         &dev->data->mac_addrs[0]);
 954
 955         /* initialize pf host driver to setup SRIOV resource if applicable */
 956         i40e_pf_host_init(dev);
 957
 958         /* register callback func to eal lib */
 959         rte_intr_callback_register(&(pci_dev->intr_handle),
 960                 i40e_dev_interrupt_handler, (void *)dev);
 961
 962         /* configure and enable device interrupt */
 963         i40e_pf_config_irq0(hw, TRUE);
 964         i40e_pf_enable_irq0(hw);
 965
 966         /* enable uio intr after callback register */
 967         rte_intr_enable(&(pci_dev->intr_handle));
 968         /*
 969          * Add an ethertype filter to drop all flow control frames transmitted
 970          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 971          * frames to wire.
 972          */
 973         i40e_add_tx_flow_control_drop_filter(pf);
 974
 975         /* Set the max frame size to 0x2600 by default,
 976          * in case other drivers changed the default value.
 977          */
 978         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
 979
 980         /* initialize mirror rule list */
 981         TAILQ_INIT(&pf->mirror_list);
 982
 983         /* Init dcb to sw mode by default */
 984         ret = i40e_dcb_init_configure(dev, TRUE);
 985         if (ret != I40E_SUCCESS) {
 986                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 987                 pf->flags &= ~I40E_FLAG_DCB;
 988         }
 989
 990         return 0;
 991
 992 err_mac_alloc:
 993         i40e_vsi_release(pf->main_vsi);
 994 err_setup_pf_switch:
 995 err_get_mac_addr:
 996 err_configure_lan_hmc:
 997         (void)i40e_shutdown_lan_hmc(hw);
 998 err_init_lan_hmc:
 999         i40e_res_pool_destroy(&pf->msix_pool);
1000 err_msix_pool_init:
1001         i40e_res_pool_destroy(&pf->qp_pool);
1002 err_qp_pool_init:
1003 err_parameter_init:
1004 err_get_capabilities:
1005         (void)i40e_shutdown_adminq(hw);
1006
1007         return ret;
1008 }
1009
1010 static int
1011 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1012 {
1013         struct rte_pci_device *pci_dev;
1014         struct i40e_hw *hw;
1015         struct i40e_filter_control_settings settings;
1016         int ret;
1017         uint8_t aq_fail = 0;
1018
1019         PMD_INIT_FUNC_TRACE();
1020
1021         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1022                 return 0;
1023
1024         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1025         pci_dev = dev->pci_dev;
1026
1027         if (hw->adapter_stopped == 0)
1028                 i40e_dev_close(dev);
1029
1030         dev->dev_ops = NULL;
1031         dev->rx_pkt_burst = NULL;
1032         dev->tx_pkt_burst = NULL;
1033
1034         /* Disable LLDP */
1035         ret = i40e_aq_stop_lldp(hw, true, NULL);
1036         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1037                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1038
1039         /* Clear PXE mode */
1040         i40e_clear_pxe_mode(hw);
1041
1042         /* Unconfigure filter control */
1043         memset(&settings, 0, sizeof(settings));
1044         ret = i40e_set_filter_control(hw, &settings);
1045         if (ret)
1046                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1047                                         ret);
1048
1049         /* Disable flow control */
1050         hw->fc.requested_mode = I40E_FC_NONE;
1051         i40e_set_fc(hw, &aq_fail, TRUE);
1052
1053         /* uninitialize pf host driver */
1054         i40e_pf_host_uninit(dev);
1055
1056         rte_free(dev->data->mac_addrs);
1057         dev->data->mac_addrs = NULL;
1058
1059         /* disable uio intr before callback unregister */
1060         rte_intr_disable(&(pci_dev->intr_handle));
1061
1062         /* register callback func to eal lib */
1063         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1064                 i40e_dev_interrupt_handler, (void *)dev);
1065
1066         return 0;
1067 }
1068
1069 static int
1070 i40e_dev_configure(struct rte_eth_dev *dev)
1071 {
1072         struct i40e_adapter *ad =
1073                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1075         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1076         int i, ret;
1077
1078         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1079          * bulk allocation or vector Rx preconditions we will reset it.
1080          */
1081         ad->rx_bulk_alloc_allowed = true;
1082         ad->rx_vec_allowed = true;
1083         ad->tx_simple_allowed = true;
1084         ad->tx_vec_allowed = true;
1085
1086         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1087                 ret = i40e_fdir_setup(pf);
1088                 if (ret != I40E_SUCCESS) {
1089                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1090                         return -ENOTSUP;
1091                 }
1092                 ret = i40e_fdir_configure(dev);
1093                 if (ret < 0) {
1094                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1095                         goto err;
1096                 }
1097         } else
1098                 i40e_fdir_teardown(pf);
1099
1100         ret = i40e_dev_init_vlan(dev);
1101         if (ret < 0)
1102                 goto err;
1103
1104         /* VMDQ setup.
1105          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1106          *  RSS setting have different requirements.
1107          *  General PMD driver call sequence are NIC init, configure,
1108          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1109          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1110          *  applicable. So, VMDQ setting has to be done before
1111          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1112          *  For RSS setting, it will try to calculate actual configured RX queue
1113          *  number, which will be available after rx_queue_setup(). dev_start()
1114          *  function is good to place RSS setup.
1115          */
1116         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1117                 ret = i40e_vmdq_setup(dev);
1118                 if (ret)
1119                         goto err;
1120         }
1121
1122         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1123                 ret = i40e_dcb_setup(dev);
1124                 if (ret) {
1125                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1126                         goto err_dcb;
1127                 }
1128         }
1129
1130         return 0;
1131
1132 err_dcb:
1133         /* need to release vmdq resource if exists */
1134         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1135                 i40e_vsi_release(pf->vmdq[i].vsi);
1136                 pf->vmdq[i].vsi = NULL;
1137         }
1138         rte_free(pf->vmdq);
1139         pf->vmdq = NULL;
1140 err:
1141         /* need to release fdir resource if exists */
1142         i40e_fdir_teardown(pf);
1143         return ret;
1144 }
1145
1146 void
1147 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1148 {
1149         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1150         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1151         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1152         uint16_t msix_vect = vsi->msix_intr;
1153         uint16_t i;
1154
1155         for (i = 0; i < vsi->nb_qps; i++) {
1156                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1157                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1158                 rte_wmb();
1159         }
1160
1161         if (vsi->type != I40E_VSI_SRIOV) {
1162                 if (!rte_intr_allow_others(intr_handle)) {
1163                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1164                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1165                         I40E_WRITE_REG(hw,
1166                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1167                                        0);
1168                 } else {
1169                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1170                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1171                         I40E_WRITE_REG(hw,
1172                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1173                                                        msix_vect - 1), 0);
1174                 }
1175         } else {
1176                 uint32_t reg;
1177                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1178                         vsi->user_param + (msix_vect - 1);
1179
1180                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1181                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1182         }
1183         I40E_WRITE_FLUSH(hw);
1184 }
1185
1186 static void
1187 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1188                        int base_queue, int nb_queue)
1189 {
1190         int i;
1191         uint32_t val;
1192         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1193
1194         /* Bind all RX queues to allocated MSIX interrupt */
1195         for (i = 0; i < nb_queue; i++) {
1196                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1197                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1198                         ((base_queue + i + 1) <<
1199                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1200                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1201                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1202
1203                 if (i == nb_queue - 1)
1204                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1205                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1206         }
1207
1208         /* Write first RX queue to Link list register as the head element */
1209         if (vsi->type != I40E_VSI_SRIOV) {
1210                 uint16_t interval =
1211                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1212
1213                 if (msix_vect == I40E_MISC_VEC_ID) {
1214                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1215                                        (base_queue <<
1216                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1217                                        (0x0 <<
1218                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1219                         I40E_WRITE_REG(hw,
1220                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1221                                        interval);
1222                 } else {
1223                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1224                                        (base_queue <<
1225                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1226                                        (0x0 <<
1227                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1228                         I40E_WRITE_REG(hw,
1229                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1230                                                        msix_vect - 1),
1231                                        interval);
1232                 }
1233         } else {
1234                 uint32_t reg;
1235
1236                 if (msix_vect == I40E_MISC_VEC_ID) {
1237                         I40E_WRITE_REG(hw,
1238                                        I40E_VPINT_LNKLST0(vsi->user_param),
1239                                        (base_queue <<
1240                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1241                                        (0x0 <<
1242                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1243                 } else {
1244                         /* num_msix_vectors_vf needs to minus irq0 */
1245                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1246                                 vsi->user_param + (msix_vect - 1);
1247
1248                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1249                                        (base_queue <<
1250                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1251                                        (0x0 <<
1252                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1253                 }
1254         }
1255
1256         I40E_WRITE_FLUSH(hw);
1257 }
1258
1259 void
1260 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1261 {
1262         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1263         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1264         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1265         uint16_t msix_vect = vsi->msix_intr;
1266         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1267         uint16_t queue_idx = 0;
1268         int record = 0;
1269         uint32_t val;
1270         int i;
1271
1272         for (i = 0; i < vsi->nb_qps; i++) {
1273                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1274                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1275         }
1276
1277         /* INTENA flag is not auto-cleared for interrupt */
1278         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1279         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1280                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1281                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1282         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1283
1284         /* VF bind interrupt */
1285         if (vsi->type == I40E_VSI_SRIOV) {
1286                 __vsi_queues_bind_intr(vsi, msix_vect,
1287                                        vsi->base_queue, vsi->nb_qps);
1288                 return;
1289         }
1290
1291         /* PF & VMDq bind interrupt */
1292         if (rte_intr_dp_is_en(intr_handle)) {
1293                 if (vsi->type == I40E_VSI_MAIN) {
1294                         queue_idx = 0;
1295                         record = 1;
1296                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1297                         struct i40e_vsi *main_vsi =
1298                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1299                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1300                         record = 1;
1301                 }
1302         }
1303
1304         for (i = 0; i < vsi->nb_used_qps; i++) {
1305                 if (nb_msix <= 1) {
1306                         if (!rte_intr_allow_others(intr_handle))
1307                                 /* allow to share MISC_VEC_ID */
1308                                 msix_vect = I40E_MISC_VEC_ID;
1309
1310                         /* no enough msix_vect, map all to one */
1311                         __vsi_queues_bind_intr(vsi, msix_vect,
1312                                                vsi->base_queue + i,
1313                                                vsi->nb_used_qps - i);
1314                         for (; !!record && i < vsi->nb_used_qps; i++)
1315                                 intr_handle->intr_vec[queue_idx + i] =
1316                                         msix_vect;
1317                         break;
1318                 }
1319                 /* 1:1 queue/msix_vect mapping */
1320                 __vsi_queues_bind_intr(vsi, msix_vect,
1321                                        vsi->base_queue + i, 1);
1322                 if (!!record)
1323                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1324
1325                 msix_vect++;
1326                 nb_msix--;
1327         }
1328 }
1329
1330 static void
1331 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1332 {
1333         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1334         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1335         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1336         uint16_t interval = i40e_calc_itr_interval(\
1337                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1338         uint16_t msix_intr, i;
1339
1340         if (rte_intr_allow_others(intr_handle))
1341                 for (i = 0; i < vsi->nb_msix; i++) {
1342                         msix_intr = vsi->msix_intr + i;
1343                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1344                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1345                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1346                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1347                                 (interval <<
1348                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1349                 }
1350         else
1351                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1352                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1353                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1354                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1355                                (interval <<
1356                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1357
1358         I40E_WRITE_FLUSH(hw);
1359 }
1360
1361 static void
1362 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1363 {
1364         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1365         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1366         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1367         uint16_t msix_intr, i;
1368
1369         if (rte_intr_allow_others(intr_handle))
1370                 for (i = 0; i < vsi->nb_msix; i++) {
1371                         msix_intr = vsi->msix_intr + i;
1372                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1373                                        0);
1374                 }
1375         else
1376                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1377
1378         I40E_WRITE_FLUSH(hw);
1379 }
1380
1381 static inline uint8_t
1382 i40e_parse_link_speed(uint16_t eth_link_speed)
1383 {
1384         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1385
1386         switch (eth_link_speed) {
1387         case ETH_LINK_SPEED_40G:
1388                 link_speed = I40E_LINK_SPEED_40GB;
1389                 break;
1390         case ETH_LINK_SPEED_20G:
1391                 link_speed = I40E_LINK_SPEED_20GB;
1392                 break;
1393         case ETH_LINK_SPEED_10G:
1394                 link_speed = I40E_LINK_SPEED_10GB;
1395                 break;
1396         case ETH_LINK_SPEED_1000:
1397                 link_speed = I40E_LINK_SPEED_1GB;
1398                 break;
1399         case ETH_LINK_SPEED_100:
1400                 link_speed = I40E_LINK_SPEED_100MB;
1401                 break;
1402         }
1403
1404         return link_speed;
1405 }
1406
1407 static int
1408 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1409                    __rte_unused uint8_t abilities,
1410                    __rte_unused uint8_t force_speed)
1411 {
1412         /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1413          * for the link control limitation of that all link control should be
1414          * handled by firmware. It should follow up if link control will be
1415          * opened to software driver in future firmware versions.
1416          */
1417         return I40E_SUCCESS;
1418 }
1419
1420 static int
1421 i40e_apply_link_speed(struct rte_eth_dev *dev)
1422 {
1423         uint8_t speed;
1424         uint8_t abilities = 0;
1425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         struct rte_eth_conf *conf = &dev->data->dev_conf;
1427
1428         speed = i40e_parse_link_speed(conf->link_speed);
1429         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1430         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1431                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1432         else
1433                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1434
1435         return i40e_phy_conf_link(hw, abilities, speed);
1436 }
1437
1438 static int
1439 i40e_dev_start(struct rte_eth_dev *dev)
1440 {
1441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1442         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1443         struct i40e_vsi *main_vsi = pf->main_vsi;
1444         int ret, i;
1445         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1446         uint32_t intr_vector = 0;
1447
1448         hw->adapter_stopped = 0;
1449
1450         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1451                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1452                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1453                              dev->data->dev_conf.link_duplex,
1454                              dev->data->port_id);
1455                 return -EINVAL;
1456         }
1457
1458         rte_intr_disable(intr_handle);
1459
1460         if ((rte_intr_cap_multiple(intr_handle) ||
1461              !RTE_ETH_DEV_SRIOV(dev).active) &&
1462             dev->data->dev_conf.intr_conf.rxq != 0) {
1463                 intr_vector = dev->data->nb_rx_queues;
1464                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1465                         return -1;
1466         }
1467
1468         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1469                 intr_handle->intr_vec =
1470                         rte_zmalloc("intr_vec",
1471                                     dev->data->nb_rx_queues * sizeof(int),
1472                                     0);
1473                 if (!intr_handle->intr_vec) {
1474                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1475                                      " intr_vec\n", dev->data->nb_rx_queues);
1476                         return -ENOMEM;
1477                 }
1478         }
1479
1480         /* Initialize VSI */
1481         ret = i40e_dev_rxtx_init(pf);
1482         if (ret != I40E_SUCCESS) {
1483                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1484                 goto err_up;
1485         }
1486
1487         /* Map queues with MSIX interrupt */
1488         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1489                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1490         i40e_vsi_queues_bind_intr(main_vsi);
1491         i40e_vsi_enable_queues_intr(main_vsi);
1492
1493         /* Map VMDQ VSI queues with MSIX interrupt */
1494         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1495                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1496                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1497                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1498         }
1499
1500         /* enable FDIR MSIX interrupt */
1501         if (pf->fdir.fdir_vsi) {
1502                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1503                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1504         }
1505
1506         /* Enable all queues which have been configured */
1507         ret = i40e_dev_switch_queues(pf, TRUE);
1508         if (ret != I40E_SUCCESS) {
1509                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1510                 goto err_up;
1511         }
1512
1513         /* Enable receiving broadcast packets */
1514         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1515         if (ret != I40E_SUCCESS)
1516                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1517
1518         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1519                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1520                                                 true, NULL);
1521                 if (ret != I40E_SUCCESS)
1522                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1523         }
1524
1525         /* Apply link configure */
1526         ret = i40e_apply_link_speed(dev);
1527         if (I40E_SUCCESS != ret) {
1528                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1529                 goto err_up;
1530         }
1531
1532         if (!rte_intr_allow_others(intr_handle)) {
1533                 rte_intr_callback_unregister(intr_handle,
1534                                              i40e_dev_interrupt_handler,
1535                                              (void *)dev);
1536                 /* configure and enable device interrupt */
1537                 i40e_pf_config_irq0(hw, FALSE);
1538                 i40e_pf_enable_irq0(hw);
1539
1540                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1541                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1542                                      " no intr multiplex\n");
1543         }
1544
1545         /* enable uio intr after callback register */
1546         rte_intr_enable(intr_handle);
1547
1548         return I40E_SUCCESS;
1549
1550 err_up:
1551         i40e_dev_switch_queues(pf, FALSE);
1552         i40e_dev_clear_queues(dev);
1553
1554         return ret;
1555 }
1556
1557 static void
1558 i40e_dev_stop(struct rte_eth_dev *dev)
1559 {
1560         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1561         struct i40e_vsi *main_vsi = pf->main_vsi;
1562         struct i40e_mirror_rule *p_mirror;
1563         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1564         int i;
1565
1566         /* Disable all queues */
1567         i40e_dev_switch_queues(pf, FALSE);
1568
1569         /* un-map queues with interrupt registers */
1570         i40e_vsi_disable_queues_intr(main_vsi);
1571         i40e_vsi_queues_unbind_intr(main_vsi);
1572
1573         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1574                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1575                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1576         }
1577
1578         if (pf->fdir.fdir_vsi) {
1579                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1580                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1581         }
1582         /* Clear all queues and release memory */
1583         i40e_dev_clear_queues(dev);
1584
1585         /* Set link down */
1586         i40e_dev_set_link_down(dev);
1587
1588         /* Remove all mirror rules */
1589         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1590                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1591                 rte_free(p_mirror);
1592         }
1593         pf->nb_mirror_rule = 0;
1594
1595         if (!rte_intr_allow_others(intr_handle))
1596                 /* resume to the default handler */
1597                 rte_intr_callback_register(intr_handle,
1598                                            i40e_dev_interrupt_handler,
1599                                            (void *)dev);
1600
1601         /* Clean datapath event and queue/vec mapping */
1602         rte_intr_efd_disable(intr_handle);
1603         if (intr_handle->intr_vec) {
1604                 rte_free(intr_handle->intr_vec);
1605                 intr_handle->intr_vec = NULL;
1606         }
1607 }
1608
1609 static void
1610 i40e_dev_close(struct rte_eth_dev *dev)
1611 {
1612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614         uint32_t reg;
1615         int i;
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         i40e_dev_stop(dev);
1620         hw->adapter_stopped = 1;
1621         i40e_dev_free_queues(dev);
1622
1623         /* Disable interrupt */
1624         i40e_pf_disable_irq0(hw);
1625         rte_intr_disable(&(dev->pci_dev->intr_handle));
1626
1627         /* shutdown and destroy the HMC */
1628         i40e_shutdown_lan_hmc(hw);
1629
1630         /* release all the existing VSIs and VEBs */
1631         i40e_fdir_teardown(pf);
1632         i40e_vsi_release(pf->main_vsi);
1633
1634         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1635                 i40e_vsi_release(pf->vmdq[i].vsi);
1636                 pf->vmdq[i].vsi = NULL;
1637         }
1638
1639         rte_free(pf->vmdq);
1640         pf->vmdq = NULL;
1641
1642         /* shutdown the adminq */
1643         i40e_aq_queue_shutdown(hw, true);
1644         i40e_shutdown_adminq(hw);
1645
1646         i40e_res_pool_destroy(&pf->qp_pool);
1647         i40e_res_pool_destroy(&pf->msix_pool);
1648
1649         /* force a PF reset to clean anything leftover */
1650         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1651         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1652                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1653         I40E_WRITE_FLUSH(hw);
1654 }
1655
1656 static void
1657 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1658 {
1659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661         struct i40e_vsi *vsi = pf->main_vsi;
1662         int status;
1663
1664         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1665                                                         true, NULL);
1666         if (status != I40E_SUCCESS)
1667                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1668
1669         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1670                                                         TRUE, NULL);
1671         if (status != I40E_SUCCESS)
1672                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1673
1674 }
1675
1676 static void
1677 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1678 {
1679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct i40e_vsi *vsi = pf->main_vsi;
1682         int status;
1683
1684         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1685                                                         false, NULL);
1686         if (status != I40E_SUCCESS)
1687                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1688
1689         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1690                                                         false, NULL);
1691         if (status != I40E_SUCCESS)
1692                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1693 }
1694
1695 static void
1696 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1697 {
1698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1700         struct i40e_vsi *vsi = pf->main_vsi;
1701         int ret;
1702
1703         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1704         if (ret != I40E_SUCCESS)
1705                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1706 }
1707
1708 static void
1709 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1710 {
1711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1713         struct i40e_vsi *vsi = pf->main_vsi;
1714         int ret;
1715
1716         if (dev->data->promiscuous == 1)
1717                 return; /* must remain in all_multicast mode */
1718
1719         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1720                                 vsi->seid, FALSE, NULL);
1721         if (ret != I40E_SUCCESS)
1722                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1723 }
1724
1725 /*
1726  * Set device link up.
1727  */
1728 static int
1729 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1730 {
1731         /* re-apply link speed setting */
1732         return i40e_apply_link_speed(dev);
1733 }
1734
1735 /*
1736  * Set device link down.
1737  */
1738 static int
1739 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1740 {
1741         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1742         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1744
1745         return i40e_phy_conf_link(hw, abilities, speed);
1746 }
1747
1748 int
1749 i40e_dev_link_update(struct rte_eth_dev *dev,
1750                      int wait_to_complete)
1751 {
1752 #define CHECK_INTERVAL 100  /* 100ms */
1753 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1755         struct i40e_link_status link_status;
1756         struct rte_eth_link link, old;
1757         int status;
1758         unsigned rep_cnt = MAX_REPEAT_TIME;
1759
1760         memset(&link, 0, sizeof(link));
1761         memset(&old, 0, sizeof(old));
1762         memset(&link_status, 0, sizeof(link_status));
1763         rte_i40e_dev_atomic_read_link_status(dev, &old);
1764
1765         do {
1766                 /* Get link status information from hardware */
1767                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1768                 if (status != I40E_SUCCESS) {
1769                         link.link_speed = ETH_LINK_SPEED_100;
1770                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1771                         PMD_DRV_LOG(ERR, "Failed to get link info");
1772                         goto out;
1773                 }
1774
1775                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1776                 if (!wait_to_complete)
1777                         break;
1778
1779                 rte_delay_ms(CHECK_INTERVAL);
1780         } while (!link.link_status && rep_cnt--);
1781
1782         if (!link.link_status)
1783                 goto out;
1784
1785         /* i40e uses full duplex only */
1786         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1787
1788         /* Parse the link status */
1789         switch (link_status.link_speed) {
1790         case I40E_LINK_SPEED_100MB:
1791                 link.link_speed = ETH_LINK_SPEED_100;
1792                 break;
1793         case I40E_LINK_SPEED_1GB:
1794                 link.link_speed = ETH_LINK_SPEED_1000;
1795                 break;
1796         case I40E_LINK_SPEED_10GB:
1797                 link.link_speed = ETH_LINK_SPEED_10G;
1798                 break;
1799         case I40E_LINK_SPEED_20GB:
1800                 link.link_speed = ETH_LINK_SPEED_20G;
1801                 break;
1802         case I40E_LINK_SPEED_40GB:
1803                 link.link_speed = ETH_LINK_SPEED_40G;
1804                 break;
1805         default:
1806                 link.link_speed = ETH_LINK_SPEED_100;
1807                 break;
1808         }
1809
1810 out:
1811         rte_i40e_dev_atomic_write_link_status(dev, &link);
1812         if (link.link_status == old.link_status)
1813                 return -1;
1814
1815         return 0;
1816 }
1817
1818 /* Get all the statistics of a VSI */
1819 void
1820 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1821 {
1822         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1823         struct i40e_eth_stats *nes = &vsi->eth_stats;
1824         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1825         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1826
1827         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1828                             vsi->offset_loaded, &oes->rx_bytes,
1829                             &nes->rx_bytes);
1830         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1831                             vsi->offset_loaded, &oes->rx_unicast,
1832                             &nes->rx_unicast);
1833         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1834                             vsi->offset_loaded, &oes->rx_multicast,
1835                             &nes->rx_multicast);
1836         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1837                             vsi->offset_loaded, &oes->rx_broadcast,
1838                             &nes->rx_broadcast);
1839         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1840                             &oes->rx_discards, &nes->rx_discards);
1841         /* GLV_REPC not supported */
1842         /* GLV_RMPC not supported */
1843         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1844                             &oes->rx_unknown_protocol,
1845                             &nes->rx_unknown_protocol);
1846         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1847                             vsi->offset_loaded, &oes->tx_bytes,
1848                             &nes->tx_bytes);
1849         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1850                             vsi->offset_loaded, &oes->tx_unicast,
1851                             &nes->tx_unicast);
1852         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1853                             vsi->offset_loaded, &oes->tx_multicast,
1854                             &nes->tx_multicast);
1855         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1856                             vsi->offset_loaded,  &oes->tx_broadcast,
1857                             &nes->tx_broadcast);
1858         /* GLV_TDPC not supported */
1859         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1860                             &oes->tx_errors, &nes->tx_errors);
1861         vsi->offset_loaded = true;
1862
1863         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1864                     vsi->vsi_id);
1865         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1866         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1867         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1868         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1869         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1870         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1871                     nes->rx_unknown_protocol);
1872         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1873         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1874         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1875         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1876         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1877         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1878         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1879                     vsi->vsi_id);
1880 }
1881
1882 static void
1883 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1884 {
1885         unsigned int i;
1886         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1887         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1888
1889         /* Get statistics of struct i40e_eth_stats */
1890         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1891                             I40E_GLPRT_GORCL(hw->port),
1892                             pf->offset_loaded, &os->eth.rx_bytes,
1893                             &ns->eth.rx_bytes);
1894         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1895                             I40E_GLPRT_UPRCL(hw->port),
1896                             pf->offset_loaded, &os->eth.rx_unicast,
1897                             &ns->eth.rx_unicast);
1898         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1899                             I40E_GLPRT_MPRCL(hw->port),
1900                             pf->offset_loaded, &os->eth.rx_multicast,
1901                             &ns->eth.rx_multicast);
1902         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1903                             I40E_GLPRT_BPRCL(hw->port),
1904                             pf->offset_loaded, &os->eth.rx_broadcast,
1905                             &ns->eth.rx_broadcast);
1906         /* Workaround: CRC size should not be included in byte statistics,
1907          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1908          */
1909         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1910                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1911
1912         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1913                             pf->offset_loaded, &os->eth.rx_discards,
1914                             &ns->eth.rx_discards);
1915         /* GLPRT_REPC not supported */
1916         /* GLPRT_RMPC not supported */
1917         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1918                             pf->offset_loaded,
1919                             &os->eth.rx_unknown_protocol,
1920                             &ns->eth.rx_unknown_protocol);
1921         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1922                             I40E_GLPRT_GOTCL(hw->port),
1923                             pf->offset_loaded, &os->eth.tx_bytes,
1924                             &ns->eth.tx_bytes);
1925         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1926                             I40E_GLPRT_UPTCL(hw->port),
1927                             pf->offset_loaded, &os->eth.tx_unicast,
1928                             &ns->eth.tx_unicast);
1929         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1930                             I40E_GLPRT_MPTCL(hw->port),
1931                             pf->offset_loaded, &os->eth.tx_multicast,
1932                             &ns->eth.tx_multicast);
1933         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1934                             I40E_GLPRT_BPTCL(hw->port),
1935                             pf->offset_loaded, &os->eth.tx_broadcast,
1936                             &ns->eth.tx_broadcast);
1937         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1938                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1939         /* GLPRT_TEPC not supported */
1940
1941         /* additional port specific stats */
1942         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1943                             pf->offset_loaded, &os->tx_dropped_link_down,
1944                             &ns->tx_dropped_link_down);
1945         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1946                             pf->offset_loaded, &os->crc_errors,
1947                             &ns->crc_errors);
1948         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1949                             pf->offset_loaded, &os->illegal_bytes,
1950                             &ns->illegal_bytes);
1951         /* GLPRT_ERRBC not supported */
1952         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1953                             pf->offset_loaded, &os->mac_local_faults,
1954                             &ns->mac_local_faults);
1955         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1956                             pf->offset_loaded, &os->mac_remote_faults,
1957                             &ns->mac_remote_faults);
1958         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1959                             pf->offset_loaded, &os->rx_length_errors,
1960                             &ns->rx_length_errors);
1961         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1962                             pf->offset_loaded, &os->link_xon_rx,
1963                             &ns->link_xon_rx);
1964         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1965                             pf->offset_loaded, &os->link_xoff_rx,
1966                             &ns->link_xoff_rx);
1967         for (i = 0; i < 8; i++) {
1968                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1969                                     pf->offset_loaded,
1970                                     &os->priority_xon_rx[i],
1971                                     &ns->priority_xon_rx[i]);
1972                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1973                                     pf->offset_loaded,
1974                                     &os->priority_xoff_rx[i],
1975                                     &ns->priority_xoff_rx[i]);
1976         }
1977         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1978                             pf->offset_loaded, &os->link_xon_tx,
1979                             &ns->link_xon_tx);
1980         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1981                             pf->offset_loaded, &os->link_xoff_tx,
1982                             &ns->link_xoff_tx);
1983         for (i = 0; i < 8; i++) {
1984                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1985                                     pf->offset_loaded,
1986                                     &os->priority_xon_tx[i],
1987                                     &ns->priority_xon_tx[i]);
1988                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1989                                     pf->offset_loaded,
1990                                     &os->priority_xoff_tx[i],
1991                                     &ns->priority_xoff_tx[i]);
1992                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1993                                     pf->offset_loaded,
1994                                     &os->priority_xon_2_xoff[i],
1995                                     &ns->priority_xon_2_xoff[i]);
1996         }
1997         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1998                             I40E_GLPRT_PRC64L(hw->port),
1999                             pf->offset_loaded, &os->rx_size_64,
2000                             &ns->rx_size_64);
2001         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2002                             I40E_GLPRT_PRC127L(hw->port),
2003                             pf->offset_loaded, &os->rx_size_127,
2004                             &ns->rx_size_127);
2005         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2006                             I40E_GLPRT_PRC255L(hw->port),
2007                             pf->offset_loaded, &os->rx_size_255,
2008                             &ns->rx_size_255);
2009         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2010                             I40E_GLPRT_PRC511L(hw->port),
2011                             pf->offset_loaded, &os->rx_size_511,
2012                             &ns->rx_size_511);
2013         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2014                             I40E_GLPRT_PRC1023L(hw->port),
2015                             pf->offset_loaded, &os->rx_size_1023,
2016                             &ns->rx_size_1023);
2017         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2018                             I40E_GLPRT_PRC1522L(hw->port),
2019                             pf->offset_loaded, &os->rx_size_1522,
2020                             &ns->rx_size_1522);
2021         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2022                             I40E_GLPRT_PRC9522L(hw->port),
2023                             pf->offset_loaded, &os->rx_size_big,
2024                             &ns->rx_size_big);
2025         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2026                             pf->offset_loaded, &os->rx_undersize,
2027                             &ns->rx_undersize);
2028         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2029                             pf->offset_loaded, &os->rx_fragments,
2030                             &ns->rx_fragments);
2031         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2032                             pf->offset_loaded, &os->rx_oversize,
2033                             &ns->rx_oversize);
2034         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2035                             pf->offset_loaded, &os->rx_jabber,
2036                             &ns->rx_jabber);
2037         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2038                             I40E_GLPRT_PTC64L(hw->port),
2039                             pf->offset_loaded, &os->tx_size_64,
2040                             &ns->tx_size_64);
2041         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2042                             I40E_GLPRT_PTC127L(hw->port),
2043                             pf->offset_loaded, &os->tx_size_127,
2044                             &ns->tx_size_127);
2045         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2046                             I40E_GLPRT_PTC255L(hw->port),
2047                             pf->offset_loaded, &os->tx_size_255,
2048                             &ns->tx_size_255);
2049         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2050                             I40E_GLPRT_PTC511L(hw->port),
2051                             pf->offset_loaded, &os->tx_size_511,
2052                             &ns->tx_size_511);
2053         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2054                             I40E_GLPRT_PTC1023L(hw->port),
2055                             pf->offset_loaded, &os->tx_size_1023,
2056                             &ns->tx_size_1023);
2057         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2058                             I40E_GLPRT_PTC1522L(hw->port),
2059                             pf->offset_loaded, &os->tx_size_1522,
2060                             &ns->tx_size_1522);
2061         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2062                             I40E_GLPRT_PTC9522L(hw->port),
2063                             pf->offset_loaded, &os->tx_size_big,
2064                             &ns->tx_size_big);
2065         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2066                            pf->offset_loaded,
2067                            &os->fd_sb_match, &ns->fd_sb_match);
2068         /* GLPRT_MSPDC not supported */
2069         /* GLPRT_XEC not supported */
2070
2071         pf->offset_loaded = true;
2072
2073         if (pf->main_vsi)
2074                 i40e_update_vsi_stats(pf->main_vsi);
2075 }
2076
2077 /* Get all statistics of a port */
2078 static void
2079 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2080 {
2081         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2082         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2084         unsigned i;
2085
2086         /* call read registers - updates values, now write them to struct */
2087         i40e_read_stats_registers(pf, hw);
2088
2089         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2090                         pf->main_vsi->eth_stats.rx_multicast +
2091                         pf->main_vsi->eth_stats.rx_broadcast -
2092                         pf->main_vsi->eth_stats.rx_discards;
2093         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2094                         pf->main_vsi->eth_stats.tx_multicast +
2095                         pf->main_vsi->eth_stats.tx_broadcast;
2096         stats->ibytes   = ns->eth.rx_bytes;
2097         stats->obytes   = ns->eth.tx_bytes;
2098         stats->oerrors  = ns->eth.tx_errors +
2099                         pf->main_vsi->eth_stats.tx_errors;
2100         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2101
2102         /* Rx Errors */
2103         stats->imissed  = ns->eth.rx_discards +
2104                         pf->main_vsi->eth_stats.rx_discards;
2105         stats->ierrors  = ns->crc_errors +
2106                         ns->rx_length_errors + ns->rx_undersize +
2107                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2108
2109         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2110         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2111         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2112         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2113         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2114         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2115         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2116                     ns->eth.rx_unknown_protocol);
2117         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2118         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2119         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2120         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2121         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2122         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2123
2124         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2125                     ns->tx_dropped_link_down);
2126         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2127         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2128                     ns->illegal_bytes);
2129         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2130         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2131                     ns->mac_local_faults);
2132         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2133                     ns->mac_remote_faults);
2134         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2135                     ns->rx_length_errors);
2136         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2137         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2138         for (i = 0; i < 8; i++) {
2139                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2140                                 i, ns->priority_xon_rx[i]);
2141                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2142                                 i, ns->priority_xoff_rx[i]);
2143         }
2144         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2145         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2146         for (i = 0; i < 8; i++) {
2147                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2148                                 i, ns->priority_xon_tx[i]);
2149                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2150                                 i, ns->priority_xoff_tx[i]);
2151                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2152                                 i, ns->priority_xon_2_xoff[i]);
2153         }
2154         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2155         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2156         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2157         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2158         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2159         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2160         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2161         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2162         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2163         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2164         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2165         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2166         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2167         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2168         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2169         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2170         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2171         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2172         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2173                         ns->mac_short_packet_dropped);
2174         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2175                     ns->checksum_error);
2176         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2177         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2178 }
2179
2180 /* Reset the statistics */
2181 static void
2182 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2183 {
2184         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2186
2187         /* Mark PF and VSI stats to update the offset, aka "reset" */
2188         pf->offset_loaded = false;
2189         if (pf->main_vsi)
2190                 pf->main_vsi->offset_loaded = false;
2191
2192         /* read the stats, reading current register values into offset */
2193         i40e_read_stats_registers(pf, hw);
2194 }
2195
2196 static uint32_t
2197 i40e_xstats_calc_num(void)
2198 {
2199         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2200                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2201                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2202 }
2203
2204 static int
2205 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2206                     unsigned n)
2207 {
2208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2209         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2210         unsigned i, count, prio;
2211         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2212
2213         count = i40e_xstats_calc_num();
2214         if (n < count)
2215                 return count;
2216
2217         i40e_read_stats_registers(pf, hw);
2218
2219         if (xstats == NULL)
2220                 return 0;
2221
2222         count = 0;
2223
2224         /* Get stats from i40e_eth_stats struct */
2225         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2226                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2227                          "%s", rte_i40e_stats_strings[i].name);
2228                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2229                         rte_i40e_stats_strings[i].offset);
2230                 count++;
2231         }
2232
2233         /* Get individiual stats from i40e_hw_port struct */
2234         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2235                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2236                          "%s", rte_i40e_hw_port_strings[i].name);
2237                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2238                                 rte_i40e_hw_port_strings[i].offset);
2239                 count++;
2240         }
2241
2242         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2243                 for (prio = 0; prio < 8; prio++) {
2244                         snprintf(xstats[count].name,
2245                                  sizeof(xstats[count].name),
2246                                  "rx_priority%u_%s", prio,
2247                                  rte_i40e_rxq_prio_strings[i].name);
2248                         xstats[count].value =
2249                                 *(uint64_t *)(((char *)hw_stats) +
2250                                 rte_i40e_rxq_prio_strings[i].offset +
2251                                 (sizeof(uint64_t) * prio));
2252                         count++;
2253                 }
2254         }
2255
2256         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2257                 for (prio = 0; prio < 8; prio++) {
2258                         snprintf(xstats[count].name,
2259                                  sizeof(xstats[count].name),
2260                                  "tx_priority%u_%s", prio,
2261                                  rte_i40e_txq_prio_strings[i].name);
2262                         xstats[count].value =
2263                                 *(uint64_t *)(((char *)hw_stats) +
2264                                 rte_i40e_txq_prio_strings[i].offset +
2265                                 (sizeof(uint64_t) * prio));
2266                         count++;
2267                 }
2268         }
2269
2270         return count;
2271 }
2272
2273 static int
2274 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2275                                  __rte_unused uint16_t queue_id,
2276                                  __rte_unused uint8_t stat_idx,
2277                                  __rte_unused uint8_t is_rx)
2278 {
2279         PMD_INIT_FUNC_TRACE();
2280
2281         return -ENOSYS;
2282 }
2283
2284 static void
2285 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2286 {
2287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2288         struct i40e_vsi *vsi = pf->main_vsi;
2289
2290         dev_info->max_rx_queues = vsi->nb_qps;
2291         dev_info->max_tx_queues = vsi->nb_qps;
2292         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2293         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2294         dev_info->max_mac_addrs = vsi->max_macaddrs;
2295         dev_info->max_vfs = dev->pci_dev->max_vfs;
2296         dev_info->rx_offload_capa =
2297                 DEV_RX_OFFLOAD_VLAN_STRIP |
2298                 DEV_RX_OFFLOAD_QINQ_STRIP |
2299                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2300                 DEV_RX_OFFLOAD_UDP_CKSUM |
2301                 DEV_RX_OFFLOAD_TCP_CKSUM;
2302         dev_info->tx_offload_capa =
2303                 DEV_TX_OFFLOAD_VLAN_INSERT |
2304                 DEV_TX_OFFLOAD_QINQ_INSERT |
2305                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2306                 DEV_TX_OFFLOAD_UDP_CKSUM |
2307                 DEV_TX_OFFLOAD_TCP_CKSUM |
2308                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2309                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2310                 DEV_TX_OFFLOAD_TCP_TSO;
2311         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2312                                                 sizeof(uint32_t);
2313         dev_info->reta_size = pf->hash_lut_size;
2314         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2315
2316         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2317                 .rx_thresh = {
2318                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2319                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2320                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2321                 },
2322                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2323                 .rx_drop_en = 0,
2324         };
2325
2326         dev_info->default_txconf = (struct rte_eth_txconf) {
2327                 .tx_thresh = {
2328                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2329                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2330                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2331                 },
2332                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2333                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2334                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2335                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2336         };
2337
2338         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2339                 .nb_max = I40E_MAX_RING_DESC,
2340                 .nb_min = I40E_MIN_RING_DESC,
2341                 .nb_align = I40E_ALIGN_RING_DESC,
2342         };
2343
2344         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2345                 .nb_max = I40E_MAX_RING_DESC,
2346                 .nb_min = I40E_MIN_RING_DESC,
2347                 .nb_align = I40E_ALIGN_RING_DESC,
2348         };
2349
2350         if (pf->flags & I40E_FLAG_VMDQ) {
2351                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2352                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2353                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2354                                                 pf->max_nb_vmdq_vsi;
2355                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2356                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2357                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2358         }
2359 }
2360
2361 static int
2362 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2363 {
2364         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2365         struct i40e_vsi *vsi = pf->main_vsi;
2366         PMD_INIT_FUNC_TRACE();
2367
2368         if (on)
2369                 return i40e_vsi_add_vlan(vsi, vlan_id);
2370         else
2371                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2372 }
2373
2374 static int
2375 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2376                    enum rte_vlan_type vlan_type,
2377                    uint16_t tpid)
2378 {
2379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380         uint64_t reg_r = 0, reg_w = 0;
2381         uint16_t reg_id = 0;
2382         int ret = 0;
2383
2384         switch (vlan_type) {
2385         case ETH_VLAN_TYPE_OUTER:
2386                 reg_id = 2;
2387                 break;
2388         case ETH_VLAN_TYPE_INNER:
2389                 reg_id = 3;
2390                 break;
2391         default:
2392                 ret = -EINVAL;
2393                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2394                 return ret;
2395         }
2396         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2397                                           &reg_r, NULL);
2398         if (ret != I40E_SUCCESS) {
2399                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2400                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2401                 ret = -EIO;
2402                 return ret;
2403         }
2404         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2405                     "0x%08"PRIx64"", reg_id, reg_r);
2406
2407         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2408         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2409         if (reg_r == reg_w) {
2410                 ret = 0;
2411                 PMD_DRV_LOG(DEBUG, "No need to write");
2412                 return ret;
2413         }
2414
2415         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2416                                            reg_w, NULL);
2417         if (ret != I40E_SUCCESS) {
2418                 ret = -EIO;
2419                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2420                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2421                 return ret;
2422         }
2423         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2424                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2425
2426         return ret;
2427 }
2428
2429 static void
2430 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2431 {
2432         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2433         struct i40e_vsi *vsi = pf->main_vsi;
2434
2435         if (mask & ETH_VLAN_FILTER_MASK) {
2436                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2437                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2438                 else
2439                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2440         }
2441
2442         if (mask & ETH_VLAN_STRIP_MASK) {
2443                 /* Enable or disable VLAN stripping */
2444                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2445                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2446                 else
2447                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2448         }
2449
2450         if (mask & ETH_VLAN_EXTEND_MASK) {
2451                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2452                         i40e_vsi_config_double_vlan(vsi, TRUE);
2453                 else
2454                         i40e_vsi_config_double_vlan(vsi, FALSE);
2455         }
2456 }
2457
2458 static void
2459 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2460                           __rte_unused uint16_t queue,
2461                           __rte_unused int on)
2462 {
2463         PMD_INIT_FUNC_TRACE();
2464 }
2465
2466 static int
2467 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_vsi *vsi = pf->main_vsi;
2471         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2472         struct i40e_vsi_vlan_pvid_info info;
2473
2474         memset(&info, 0, sizeof(info));
2475         info.on = on;
2476         if (info.on)
2477                 info.config.pvid = pvid;
2478         else {
2479                 info.config.reject.tagged =
2480                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2481                 info.config.reject.untagged =
2482                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2483         }
2484
2485         return i40e_vsi_vlan_pvid_set(vsi, &info);
2486 }
2487
2488 static int
2489 i40e_dev_led_on(struct rte_eth_dev *dev)
2490 {
2491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2492         uint32_t mode = i40e_led_get(hw);
2493
2494         if (mode == 0)
2495                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2496
2497         return 0;
2498 }
2499
2500 static int
2501 i40e_dev_led_off(struct rte_eth_dev *dev)
2502 {
2503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2504         uint32_t mode = i40e_led_get(hw);
2505
2506         if (mode != 0)
2507                 i40e_led_set(hw, 0, false);
2508
2509         return 0;
2510 }
2511
2512 static int
2513 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2514 {
2515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2517
2518         fc_conf->pause_time = pf->fc_conf.pause_time;
2519         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2520         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2521
2522          /* Return current mode according to actual setting*/
2523         switch (hw->fc.current_mode) {
2524         case I40E_FC_FULL:
2525                 fc_conf->mode = RTE_FC_FULL;
2526                 break;
2527         case I40E_FC_TX_PAUSE:
2528                 fc_conf->mode = RTE_FC_TX_PAUSE;
2529                 break;
2530         case I40E_FC_RX_PAUSE:
2531                 fc_conf->mode = RTE_FC_RX_PAUSE;
2532                 break;
2533         case I40E_FC_NONE:
2534         default:
2535                 fc_conf->mode = RTE_FC_NONE;
2536         };
2537
2538         return 0;
2539 }
2540
2541 static int
2542 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2543 {
2544         uint32_t mflcn_reg, fctrl_reg, reg;
2545         uint32_t max_high_water;
2546         uint8_t i, aq_failure;
2547         int err;
2548         struct i40e_hw *hw;
2549         struct i40e_pf *pf;
2550         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2551                 [RTE_FC_NONE] = I40E_FC_NONE,
2552                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2553                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2554                 [RTE_FC_FULL] = I40E_FC_FULL
2555         };
2556
2557         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2558
2559         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2560         if ((fc_conf->high_water > max_high_water) ||
2561                         (fc_conf->high_water < fc_conf->low_water)) {
2562                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2563                         "High_water must <= %d.", max_high_water);
2564                 return -EINVAL;
2565         }
2566
2567         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2568         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2569         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2570
2571         pf->fc_conf.pause_time = fc_conf->pause_time;
2572         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2573         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2574
2575         PMD_INIT_FUNC_TRACE();
2576
2577         /* All the link flow control related enable/disable register
2578          * configuration is handle by the F/W
2579          */
2580         err = i40e_set_fc(hw, &aq_failure, true);
2581         if (err < 0)
2582                 return -ENOSYS;
2583
2584         if (i40e_is_40G_device(hw->device_id)) {
2585                 /* Configure flow control refresh threshold,
2586                  * the value for stat_tx_pause_refresh_timer[8]
2587                  * is used for global pause operation.
2588                  */
2589
2590                 I40E_WRITE_REG(hw,
2591                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2592                                pf->fc_conf.pause_time);
2593
2594                 /* configure the timer value included in transmitted pause
2595                  * frame,
2596                  * the value for stat_tx_pause_quanta[8] is used for global
2597                  * pause operation
2598                  */
2599                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2600                                pf->fc_conf.pause_time);
2601
2602                 fctrl_reg = I40E_READ_REG(hw,
2603                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2604
2605                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2606                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2607                 else
2608                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2609
2610                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2611                                fctrl_reg);
2612         } else {
2613                 /* Configure pause time (2 TCs per register) */
2614                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2615                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2616                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2617
2618                 /* Configure flow control refresh threshold value */
2619                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2620                                pf->fc_conf.pause_time / 2);
2621
2622                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2623
2624                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2625                  *depending on configuration
2626                  */
2627                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2628                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2629                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2630                 } else {
2631                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2632                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2633                 }
2634
2635                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2636         }
2637
2638         /* config the water marker both based on the packets and bytes */
2639         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2640                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2641                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2642         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2643                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2644                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2645         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2646                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2647                        << I40E_KILOSHIFT);
2648         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2649                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2650                        << I40E_KILOSHIFT);
2651
2652         I40E_WRITE_FLUSH(hw);
2653
2654         return 0;
2655 }
2656
2657 static int
2658 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2659                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2660 {
2661         PMD_INIT_FUNC_TRACE();
2662
2663         return -ENOSYS;
2664 }
2665
2666 /* Add a MAC address, and update filters */
2667 static void
2668 i40e_macaddr_add(struct rte_eth_dev *dev,
2669                  struct ether_addr *mac_addr,
2670                  __rte_unused uint32_t index,
2671                  uint32_t pool)
2672 {
2673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2674         struct i40e_mac_filter_info mac_filter;
2675         struct i40e_vsi *vsi;
2676         int ret;
2677
2678         /* If VMDQ not enabled or configured, return */
2679         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2680                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2681                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2682                         pool);
2683                 return;
2684         }
2685
2686         if (pool > pf->nb_cfg_vmdq_vsi) {
2687                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2688                                 pool, pf->nb_cfg_vmdq_vsi);
2689                 return;
2690         }
2691
2692         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2693         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2694                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2695         else
2696                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2697
2698         if (pool == 0)
2699                 vsi = pf->main_vsi;
2700         else
2701                 vsi = pf->vmdq[pool - 1].vsi;
2702
2703         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2704         if (ret != I40E_SUCCESS) {
2705                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2706                 return;
2707         }
2708 }
2709
2710 /* Remove a MAC address, and update filters */
2711 static void
2712 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2713 {
2714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2715         struct i40e_vsi *vsi;
2716         struct rte_eth_dev_data *data = dev->data;
2717         struct ether_addr *macaddr;
2718         int ret;
2719         uint32_t i;
2720         uint64_t pool_sel;
2721
2722         macaddr = &(data->mac_addrs[index]);
2723
2724         pool_sel = dev->data->mac_pool_sel[index];
2725
2726         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2727                 if (pool_sel & (1ULL << i)) {
2728                         if (i == 0)
2729                                 vsi = pf->main_vsi;
2730                         else {
2731                                 /* No VMDQ pool enabled or configured */
2732                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2733                                         (i > pf->nb_cfg_vmdq_vsi)) {
2734                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2735                                                         "/configured");
2736                                         return;
2737                                 }
2738                                 vsi = pf->vmdq[i - 1].vsi;
2739                         }
2740                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2741
2742                         if (ret) {
2743                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2744                                 return;
2745                         }
2746                 }
2747         }
2748 }
2749
2750 /* Set perfect match or hash match of MAC and VLAN for a VF */
2751 static int
2752 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2753                  struct rte_eth_mac_filter *filter,
2754                  bool add)
2755 {
2756         struct i40e_hw *hw;
2757         struct i40e_mac_filter_info mac_filter;
2758         struct ether_addr old_mac;
2759         struct ether_addr *new_mac;
2760         struct i40e_pf_vf *vf = NULL;
2761         uint16_t vf_id;
2762         int ret;
2763
2764         if (pf == NULL) {
2765                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2766                 return -EINVAL;
2767         }
2768         hw = I40E_PF_TO_HW(pf);
2769
2770         if (filter == NULL) {
2771                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2772                 return -EINVAL;
2773         }
2774
2775         new_mac = &filter->mac_addr;
2776
2777         if (is_zero_ether_addr(new_mac)) {
2778                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2779                 return -EINVAL;
2780         }
2781
2782         vf_id = filter->dst_id;
2783
2784         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2785                 PMD_DRV_LOG(ERR, "Invalid argument.");
2786                 return -EINVAL;
2787         }
2788         vf = &pf->vfs[vf_id];
2789
2790         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2791                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2792                 return -EINVAL;
2793         }
2794
2795         if (add) {
2796                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2797                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2798                                 ETHER_ADDR_LEN);
2799                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2800                                  ETHER_ADDR_LEN);
2801
2802                 mac_filter.filter_type = filter->filter_type;
2803                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2804                 if (ret != I40E_SUCCESS) {
2805                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2806                         return -1;
2807                 }
2808                 ether_addr_copy(new_mac, &pf->dev_addr);
2809         } else {
2810                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2811                                 ETHER_ADDR_LEN);
2812                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2813                 if (ret != I40E_SUCCESS) {
2814                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2815                         return -1;
2816                 }
2817
2818                 /* Clear device address as it has been removed */
2819                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2820                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2821         }
2822
2823         return 0;
2824 }
2825
2826 /* MAC filter handle */
2827 static int
2828 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2829                 void *arg)
2830 {
2831         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2832         struct rte_eth_mac_filter *filter;
2833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2834         int ret = I40E_NOT_SUPPORTED;
2835
2836         filter = (struct rte_eth_mac_filter *)(arg);
2837
2838         switch (filter_op) {
2839         case RTE_ETH_FILTER_NOP:
2840                 ret = I40E_SUCCESS;
2841                 break;
2842         case RTE_ETH_FILTER_ADD:
2843                 i40e_pf_disable_irq0(hw);
2844                 if (filter->is_vf)
2845                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2846                 i40e_pf_enable_irq0(hw);
2847                 break;
2848         case RTE_ETH_FILTER_DELETE:
2849                 i40e_pf_disable_irq0(hw);
2850                 if (filter->is_vf)
2851                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2852                 i40e_pf_enable_irq0(hw);
2853                 break;
2854         default:
2855                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2856                 ret = I40E_ERR_PARAM;
2857                 break;
2858         }
2859
2860         return ret;
2861 }
2862
2863 static int
2864 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2865 {
2866         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2867         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2868         int ret;
2869
2870         if (!lut)
2871                 return -EINVAL;
2872
2873         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2874                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2875                                           lut, lut_size);
2876                 if (ret) {
2877                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2878                         return ret;
2879                 }
2880         } else {
2881                 uint32_t *lut_dw = (uint32_t *)lut;
2882                 uint16_t i, lut_size_dw = lut_size / 4;
2883
2884                 for (i = 0; i < lut_size_dw; i++)
2885                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2886         }
2887
2888         return 0;
2889 }
2890
2891 static int
2892 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2893 {
2894         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2895         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2896         int ret;
2897
2898         if (!vsi || !lut)
2899                 return -EINVAL;
2900
2901         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2902                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2903                                           lut, lut_size);
2904                 if (ret) {
2905                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2906                         return ret;
2907                 }
2908         } else {
2909                 uint32_t *lut_dw = (uint32_t *)lut;
2910                 uint16_t i, lut_size_dw = lut_size / 4;
2911
2912                 for (i = 0; i < lut_size_dw; i++)
2913                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2914                 I40E_WRITE_FLUSH(hw);
2915         }
2916
2917         return 0;
2918 }
2919
2920 static int
2921 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2922                          struct rte_eth_rss_reta_entry64 *reta_conf,
2923                          uint16_t reta_size)
2924 {
2925         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2926         uint16_t i, lut_size = pf->hash_lut_size;
2927         uint16_t idx, shift;
2928         uint8_t *lut;
2929         int ret;
2930
2931         if (reta_size != lut_size ||
2932                 reta_size > ETH_RSS_RETA_SIZE_512) {
2933                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2934                         "(%d) doesn't match the number hardware can supported "
2935                                         "(%d)\n", reta_size, lut_size);
2936                 return -EINVAL;
2937         }
2938
2939         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2940         if (!lut) {
2941                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2942                 return -ENOMEM;
2943         }
2944         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2945         if (ret)
2946                 goto out;
2947         for (i = 0; i < reta_size; i++) {
2948                 idx = i / RTE_RETA_GROUP_SIZE;
2949                 shift = i % RTE_RETA_GROUP_SIZE;
2950                 if (reta_conf[idx].mask & (1ULL << shift))
2951                         lut[i] = reta_conf[idx].reta[shift];
2952         }
2953         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2954
2955 out:
2956         rte_free(lut);
2957
2958         return ret;
2959 }
2960
2961 static int
2962 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2963                         struct rte_eth_rss_reta_entry64 *reta_conf,
2964                         uint16_t reta_size)
2965 {
2966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2967         uint16_t i, lut_size = pf->hash_lut_size;
2968         uint16_t idx, shift;
2969         uint8_t *lut;
2970         int ret;
2971
2972         if (reta_size != lut_size ||
2973                 reta_size > ETH_RSS_RETA_SIZE_512) {
2974                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2975                         "(%d) doesn't match the number hardware can supported "
2976                                         "(%d)\n", reta_size, lut_size);
2977                 return -EINVAL;
2978         }
2979
2980         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2981         if (!lut) {
2982                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2983                 return -ENOMEM;
2984         }
2985
2986         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2987         if (ret)
2988                 goto out;
2989         for (i = 0; i < reta_size; i++) {
2990                 idx = i / RTE_RETA_GROUP_SIZE;
2991                 shift = i % RTE_RETA_GROUP_SIZE;
2992                 if (reta_conf[idx].mask & (1ULL << shift))
2993                         reta_conf[idx].reta[shift] = lut[i];
2994         }
2995
2996 out:
2997         rte_free(lut);
2998
2999         return ret;
3000 }
3001
3002 /**
3003  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3004  * @hw:   pointer to the HW structure
3005  * @mem:  pointer to mem struct to fill out
3006  * @size: size of memory requested
3007  * @alignment: what to align the allocation to
3008  **/
3009 enum i40e_status_code
3010 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3011                         struct i40e_dma_mem *mem,
3012                         u64 size,
3013                         u32 alignment)
3014 {
3015         const struct rte_memzone *mz = NULL;
3016         char z_name[RTE_MEMZONE_NAMESIZE];
3017
3018         if (!mem)
3019                 return I40E_ERR_PARAM;
3020
3021         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3022         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3023                                          alignment, RTE_PGSIZE_2M);
3024         if (!mz)
3025                 return I40E_ERR_NO_MEMORY;
3026
3027         mem->size = size;
3028         mem->va = mz->addr;
3029         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3030         mem->zone = (const void *)mz;
3031         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3032                     "%"PRIu64, mz->name, mem->pa);
3033
3034         return I40E_SUCCESS;
3035 }
3036
3037 /**
3038  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3039  * @hw:   pointer to the HW structure
3040  * @mem:  ptr to mem struct to free
3041  **/
3042 enum i40e_status_code
3043 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3044                     struct i40e_dma_mem *mem)
3045 {
3046         if (!mem)
3047                 return I40E_ERR_PARAM;
3048
3049         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3050                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3051                     mem->pa);
3052         rte_memzone_free((const struct rte_memzone *)mem->zone);
3053         mem->zone = NULL;
3054         mem->va = NULL;
3055         mem->pa = (u64)0;
3056
3057         return I40E_SUCCESS;
3058 }
3059
3060 /**
3061  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3062  * @hw:   pointer to the HW structure
3063  * @mem:  pointer to mem struct to fill out
3064  * @size: size of memory requested
3065  **/
3066 enum i40e_status_code
3067 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3068                          struct i40e_virt_mem *mem,
3069                          u32 size)
3070 {
3071         if (!mem)
3072                 return I40E_ERR_PARAM;
3073
3074         mem->size = size;
3075         mem->va = rte_zmalloc("i40e", size, 0);
3076
3077         if (mem->va)
3078                 return I40E_SUCCESS;
3079         else
3080                 return I40E_ERR_NO_MEMORY;
3081 }
3082
3083 /**
3084  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3085  * @hw:   pointer to the HW structure
3086  * @mem:  pointer to mem struct to free
3087  **/
3088 enum i40e_status_code
3089 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3090                      struct i40e_virt_mem *mem)
3091 {
3092         if (!mem)
3093                 return I40E_ERR_PARAM;
3094
3095         rte_free(mem->va);
3096         mem->va = NULL;
3097
3098         return I40E_SUCCESS;
3099 }
3100
3101 void
3102 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3103 {
3104         rte_spinlock_init(&sp->spinlock);
3105 }
3106
3107 void
3108 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3109 {
3110         rte_spinlock_lock(&sp->spinlock);
3111 }
3112
3113 void
3114 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3115 {
3116         rte_spinlock_unlock(&sp->spinlock);
3117 }
3118
3119 void
3120 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3121 {
3122         return;
3123 }
3124
3125 /**
3126  * Get the hardware capabilities, which will be parsed
3127  * and saved into struct i40e_hw.
3128  */
3129 static int
3130 i40e_get_cap(struct i40e_hw *hw)
3131 {
3132         struct i40e_aqc_list_capabilities_element_resp *buf;
3133         uint16_t len, size = 0;
3134         int ret;
3135
3136         /* Calculate a huge enough buff for saving response data temporarily */
3137         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3138                                                 I40E_MAX_CAP_ELE_NUM;
3139         buf = rte_zmalloc("i40e", len, 0);
3140         if (!buf) {
3141                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3142                 return I40E_ERR_NO_MEMORY;
3143         }
3144
3145         /* Get, parse the capabilities and save it to hw */
3146         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3147                         i40e_aqc_opc_list_func_capabilities, NULL);
3148         if (ret != I40E_SUCCESS)
3149                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3150
3151         /* Free the temporary buffer after being used */
3152         rte_free(buf);
3153
3154         return ret;
3155 }
3156
3157 static int
3158 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3159 {
3160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3161         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3162         uint16_t qp_count = 0, vsi_count = 0;
3163
3164         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3165                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3166                 return -EINVAL;
3167         }
3168         /* Add the parameter init for LFC */
3169         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3170         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3171         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3172
3173         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3174         pf->max_num_vsi = hw->func_caps.num_vsis;
3175         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3176         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3177         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3178
3179         /* FDir queue/VSI allocation */
3180         pf->fdir_qp_offset = 0;
3181         if (hw->func_caps.fd) {
3182                 pf->flags |= I40E_FLAG_FDIR;
3183                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3184         } else {
3185                 pf->fdir_nb_qps = 0;
3186         }
3187         qp_count += pf->fdir_nb_qps;
3188         vsi_count += 1;
3189
3190         /* LAN queue/VSI allocation */
3191         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3192         if (!hw->func_caps.rss) {
3193                 pf->lan_nb_qps = 1;
3194         } else {
3195                 pf->flags |= I40E_FLAG_RSS;
3196                 if (hw->mac.type == I40E_MAC_X722)
3197                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3198                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3199         }
3200         qp_count += pf->lan_nb_qps;
3201         vsi_count += 1;
3202
3203         /* VF queue/VSI allocation */
3204         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3205         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3206                 pf->flags |= I40E_FLAG_SRIOV;
3207                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3208                 pf->vf_num = dev->pci_dev->max_vfs;
3209                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3210                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3211                             pf->vf_nb_qps * pf->vf_num);
3212         } else {
3213                 pf->vf_nb_qps = 0;
3214                 pf->vf_num = 0;
3215         }
3216         qp_count += pf->vf_nb_qps * pf->vf_num;
3217         vsi_count += pf->vf_num;
3218
3219         /* VMDq queue/VSI allocation */
3220         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3221         pf->vmdq_nb_qps = 0;
3222         pf->max_nb_vmdq_vsi = 0;
3223         if (hw->func_caps.vmdq) {
3224                 if (qp_count < hw->func_caps.num_tx_qp &&
3225                         vsi_count < hw->func_caps.num_vsis) {
3226                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3227                                 qp_count) / pf->vmdq_nb_qp_max;
3228
3229                         /* Limit the maximum number of VMDq vsi to the maximum
3230                          * ethdev can support
3231                          */
3232                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3233                                 hw->func_caps.num_vsis - vsi_count);
3234                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3235                                 ETH_64_POOLS);
3236                         if (pf->max_nb_vmdq_vsi) {
3237                                 pf->flags |= I40E_FLAG_VMDQ;
3238                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3239                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3240                                             "per VMDQ VSI, in total %u queues",
3241                                             pf->max_nb_vmdq_vsi,
3242                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3243                                             pf->max_nb_vmdq_vsi);
3244                         } else {
3245                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3246                                             "VMDq");
3247                         }
3248                 } else {
3249                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3250                 }
3251         }
3252         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3253         vsi_count += pf->max_nb_vmdq_vsi;
3254
3255         if (hw->func_caps.dcb)
3256                 pf->flags |= I40E_FLAG_DCB;
3257
3258         if (qp_count > hw->func_caps.num_tx_qp) {
3259                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3260                             "the hardware maximum %u", qp_count,
3261                             hw->func_caps.num_tx_qp);
3262                 return -EINVAL;
3263         }
3264         if (vsi_count > hw->func_caps.num_vsis) {
3265                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3266                             "the hardware maximum %u", vsi_count,
3267                             hw->func_caps.num_vsis);
3268                 return -EINVAL;
3269         }
3270
3271         return 0;
3272 }
3273
3274 static int
3275 i40e_pf_get_switch_config(struct i40e_pf *pf)
3276 {
3277         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3278         struct i40e_aqc_get_switch_config_resp *switch_config;
3279         struct i40e_aqc_switch_config_element_resp *element;
3280         uint16_t start_seid = 0, num_reported;
3281         int ret;
3282
3283         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3284                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3285         if (!switch_config) {
3286                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3287                 return -ENOMEM;
3288         }
3289
3290         /* Get the switch configurations */
3291         ret = i40e_aq_get_switch_config(hw, switch_config,
3292                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3293         if (ret != I40E_SUCCESS) {
3294                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3295                 goto fail;
3296         }
3297         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3298         if (num_reported != 1) { /* The number should be 1 */
3299                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3300                 goto fail;
3301         }
3302
3303         /* Parse the switch configuration elements */
3304         element = &(switch_config->element[0]);
3305         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3306                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3307                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3308         } else
3309                 PMD_DRV_LOG(INFO, "Unknown element type");
3310
3311 fail:
3312         rte_free(switch_config);
3313
3314         return ret;
3315 }
3316
3317 static int
3318 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3319                         uint32_t num)
3320 {
3321         struct pool_entry *entry;
3322
3323         if (pool == NULL || num == 0)
3324                 return -EINVAL;
3325
3326         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3327         if (entry == NULL) {
3328                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3329                 return -ENOMEM;
3330         }
3331
3332         /* queue heap initialize */
3333         pool->num_free = num;
3334         pool->num_alloc = 0;
3335         pool->base = base;
3336         LIST_INIT(&pool->alloc_list);
3337         LIST_INIT(&pool->free_list);
3338
3339         /* Initialize element  */
3340         entry->base = 0;
3341         entry->len = num;
3342
3343         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3344         return 0;
3345 }
3346
3347 static void
3348 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3349 {
3350         struct pool_entry *entry;
3351
3352         if (pool == NULL)
3353                 return;
3354
3355         LIST_FOREACH(entry, &pool->alloc_list, next) {
3356                 LIST_REMOVE(entry, next);
3357                 rte_free(entry);
3358         }
3359
3360         LIST_FOREACH(entry, &pool->free_list, next) {
3361                 LIST_REMOVE(entry, next);
3362                 rte_free(entry);
3363         }
3364
3365         pool->num_free = 0;
3366         pool->num_alloc = 0;
3367         pool->base = 0;
3368         LIST_INIT(&pool->alloc_list);
3369         LIST_INIT(&pool->free_list);
3370 }
3371
3372 static int
3373 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3374                        uint32_t base)
3375 {
3376         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3377         uint32_t pool_offset;
3378         int insert;
3379
3380         if (pool == NULL) {
3381                 PMD_DRV_LOG(ERR, "Invalid parameter");
3382                 return -EINVAL;
3383         }
3384
3385         pool_offset = base - pool->base;
3386         /* Lookup in alloc list */
3387         LIST_FOREACH(entry, &pool->alloc_list, next) {
3388                 if (entry->base == pool_offset) {
3389                         valid_entry = entry;
3390                         LIST_REMOVE(entry, next);
3391                         break;
3392                 }
3393         }
3394
3395         /* Not find, return */
3396         if (valid_entry == NULL) {
3397                 PMD_DRV_LOG(ERR, "Failed to find entry");
3398                 return -EINVAL;
3399         }
3400
3401         /**
3402          * Found it, move it to free list  and try to merge.
3403          * In order to make merge easier, always sort it by qbase.
3404          * Find adjacent prev and last entries.
3405          */
3406         prev = next = NULL;
3407         LIST_FOREACH(entry, &pool->free_list, next) {
3408                 if (entry->base > valid_entry->base) {
3409                         next = entry;
3410                         break;
3411                 }
3412                 prev = entry;
3413         }
3414
3415         insert = 0;
3416         /* Try to merge with next one*/
3417         if (next != NULL) {
3418                 /* Merge with next one */
3419                 if (valid_entry->base + valid_entry->len == next->base) {
3420                         next->base = valid_entry->base;
3421                         next->len += valid_entry->len;
3422                         rte_free(valid_entry);
3423                         valid_entry = next;
3424                         insert = 1;
3425                 }
3426         }
3427
3428         if (prev != NULL) {
3429                 /* Merge with previous one */
3430                 if (prev->base + prev->len == valid_entry->base) {
3431                         prev->len += valid_entry->len;
3432                         /* If it merge with next one, remove next node */
3433                         if (insert == 1) {
3434                                 LIST_REMOVE(valid_entry, next);
3435                                 rte_free(valid_entry);
3436                         } else {
3437                                 rte_free(valid_entry);
3438                                 insert = 1;
3439                         }
3440                 }
3441         }
3442
3443         /* Not find any entry to merge, insert */
3444         if (insert == 0) {
3445                 if (prev != NULL)
3446                         LIST_INSERT_AFTER(prev, valid_entry, next);
3447                 else if (next != NULL)
3448                         LIST_INSERT_BEFORE(next, valid_entry, next);
3449                 else /* It's empty list, insert to head */
3450                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3451         }
3452
3453         pool->num_free += valid_entry->len;
3454         pool->num_alloc -= valid_entry->len;
3455
3456         return 0;
3457 }
3458
3459 static int
3460 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3461                        uint16_t num)
3462 {
3463         struct pool_entry *entry, *valid_entry;
3464
3465         if (pool == NULL || num == 0) {
3466                 PMD_DRV_LOG(ERR, "Invalid parameter");
3467                 return -EINVAL;
3468         }
3469
3470         if (pool->num_free < num) {
3471                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3472                             num, pool->num_free);
3473                 return -ENOMEM;
3474         }
3475
3476         valid_entry = NULL;
3477         /* Lookup  in free list and find most fit one */
3478         LIST_FOREACH(entry, &pool->free_list, next) {
3479                 if (entry->len >= num) {
3480                         /* Find best one */
3481                         if (entry->len == num) {
3482                                 valid_entry = entry;
3483                                 break;
3484                         }
3485                         if (valid_entry == NULL || valid_entry->len > entry->len)
3486                                 valid_entry = entry;
3487                 }
3488         }
3489
3490         /* Not find one to satisfy the request, return */
3491         if (valid_entry == NULL) {
3492                 PMD_DRV_LOG(ERR, "No valid entry found");
3493                 return -ENOMEM;
3494         }
3495         /**
3496          * The entry have equal queue number as requested,
3497          * remove it from alloc_list.
3498          */
3499         if (valid_entry->len == num) {
3500                 LIST_REMOVE(valid_entry, next);
3501         } else {
3502                 /**
3503                  * The entry have more numbers than requested,
3504                  * create a new entry for alloc_list and minus its
3505                  * queue base and number in free_list.
3506                  */
3507                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3508                 if (entry == NULL) {
3509                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3510                                     "resource pool");
3511                         return -ENOMEM;
3512                 }
3513                 entry->base = valid_entry->base;
3514                 entry->len = num;
3515                 valid_entry->base += num;
3516                 valid_entry->len -= num;
3517                 valid_entry = entry;
3518         }
3519
3520         /* Insert it into alloc list, not sorted */
3521         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3522
3523         pool->num_free -= valid_entry->len;
3524         pool->num_alloc += valid_entry->len;
3525
3526         return valid_entry->base + pool->base;
3527 }
3528
3529 /**
3530  * bitmap_is_subset - Check whether src2 is subset of src1
3531  **/
3532 static inline int
3533 bitmap_is_subset(uint8_t src1, uint8_t src2)
3534 {
3535         return !((src1 ^ src2) & src2);
3536 }
3537
3538 static enum i40e_status_code
3539 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3540 {
3541         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3542
3543         /* If DCB is not supported, only default TC is supported */
3544         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3545                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3546                 return I40E_NOT_SUPPORTED;
3547         }
3548
3549         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3550                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3551                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3552                             enabled_tcmap);
3553                 return I40E_NOT_SUPPORTED;
3554         }
3555         return I40E_SUCCESS;
3556 }
3557
3558 int
3559 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3560                                 struct i40e_vsi_vlan_pvid_info *info)
3561 {
3562         struct i40e_hw *hw;
3563         struct i40e_vsi_context ctxt;
3564         uint8_t vlan_flags = 0;
3565         int ret;
3566
3567         if (vsi == NULL || info == NULL) {
3568                 PMD_DRV_LOG(ERR, "invalid parameters");
3569                 return I40E_ERR_PARAM;
3570         }
3571
3572         if (info->on) {
3573                 vsi->info.pvid = info->config.pvid;
3574                 /**
3575                  * If insert pvid is enabled, only tagged pkts are
3576                  * allowed to be sent out.
3577                  */
3578                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3579                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3580         } else {
3581                 vsi->info.pvid = 0;
3582                 if (info->config.reject.tagged == 0)
3583                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3584
3585                 if (info->config.reject.untagged == 0)
3586                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3587         }
3588         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3589                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3590         vsi->info.port_vlan_flags |= vlan_flags;
3591         vsi->info.valid_sections =
3592                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3593         memset(&ctxt, 0, sizeof(ctxt));
3594         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3595         ctxt.seid = vsi->seid;
3596
3597         hw = I40E_VSI_TO_HW(vsi);
3598         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3599         if (ret != I40E_SUCCESS)
3600                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3601
3602         return ret;
3603 }
3604
3605 static int
3606 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3607 {
3608         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3609         int i, ret;
3610         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3611
3612         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3613         if (ret != I40E_SUCCESS)
3614                 return ret;
3615
3616         if (!vsi->seid) {
3617                 PMD_DRV_LOG(ERR, "seid not valid");
3618                 return -EINVAL;
3619         }
3620
3621         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3622         tc_bw_data.tc_valid_bits = enabled_tcmap;
3623         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3624                 tc_bw_data.tc_bw_credits[i] =
3625                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3626
3627         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3628         if (ret != I40E_SUCCESS) {
3629                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3630                 return ret;
3631         }
3632
3633         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3634                                         sizeof(vsi->info.qs_handle));
3635         return I40E_SUCCESS;
3636 }
3637
3638 static enum i40e_status_code
3639 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3640                                  struct i40e_aqc_vsi_properties_data *info,
3641                                  uint8_t enabled_tcmap)
3642 {
3643         enum i40e_status_code ret;
3644         int i, total_tc = 0;
3645         uint16_t qpnum_per_tc, bsf, qp_idx;
3646
3647         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3648         if (ret != I40E_SUCCESS)
3649                 return ret;
3650
3651         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3652                 if (enabled_tcmap & (1 << i))
3653                         total_tc++;
3654         vsi->enabled_tc = enabled_tcmap;
3655
3656         /* Number of queues per enabled TC */
3657         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3658         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3659         bsf = rte_bsf32(qpnum_per_tc);
3660
3661         /* Adjust the queue number to actual queues that can be applied */
3662         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3663                 vsi->nb_qps = qpnum_per_tc * total_tc;
3664
3665         /**
3666          * Configure TC and queue mapping parameters, for enabled TC,
3667          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3668          * default queue will serve it.
3669          */
3670         qp_idx = 0;
3671         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3672                 if (vsi->enabled_tc & (1 << i)) {
3673                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3674                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3675                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3676                         qp_idx += qpnum_per_tc;
3677                 } else
3678                         info->tc_mapping[i] = 0;
3679         }
3680
3681         /* Associate queue number with VSI */
3682         if (vsi->type == I40E_VSI_SRIOV) {
3683                 info->mapping_flags |=
3684                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3685                 for (i = 0; i < vsi->nb_qps; i++)
3686                         info->queue_mapping[i] =
3687                                 rte_cpu_to_le_16(vsi->base_queue + i);
3688         } else {
3689                 info->mapping_flags |=
3690                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3691                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3692         }
3693         info->valid_sections |=
3694                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3695
3696         return I40E_SUCCESS;
3697 }
3698
3699 static int
3700 i40e_veb_release(struct i40e_veb *veb)
3701 {
3702         struct i40e_vsi *vsi;
3703         struct i40e_hw *hw;
3704
3705         if (veb == NULL || veb->associate_vsi == NULL)
3706                 return -EINVAL;
3707
3708         if (!TAILQ_EMPTY(&veb->head)) {
3709                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3710                 return -EACCES;
3711         }
3712
3713         vsi = veb->associate_vsi;
3714         hw = I40E_VSI_TO_HW(vsi);
3715
3716         vsi->uplink_seid = veb->uplink_seid;
3717         i40e_aq_delete_element(hw, veb->seid, NULL);
3718         rte_free(veb);
3719         vsi->veb = NULL;
3720         return I40E_SUCCESS;
3721 }
3722
3723 /* Setup a veb */
3724 static struct i40e_veb *
3725 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3726 {
3727         struct i40e_veb *veb;
3728         int ret;
3729         struct i40e_hw *hw;
3730
3731         if (NULL == pf || vsi == NULL) {
3732                 PMD_DRV_LOG(ERR, "veb setup failed, "
3733                             "associated VSI shouldn't null");
3734                 return NULL;
3735         }
3736         hw = I40E_PF_TO_HW(pf);
3737
3738         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3739         if (!veb) {
3740                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3741                 goto fail;
3742         }
3743
3744         veb->associate_vsi = vsi;
3745         TAILQ_INIT(&veb->head);
3746         veb->uplink_seid = vsi->uplink_seid;
3747
3748         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3749                 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3750
3751         if (ret != I40E_SUCCESS) {
3752                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3753                             hw->aq.asq_last_status);
3754                 goto fail;
3755         }
3756
3757         /* get statistics index */
3758         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3759                                 &veb->stats_idx, NULL, NULL, NULL);
3760         if (ret != I40E_SUCCESS) {
3761                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3762                             hw->aq.asq_last_status);
3763                 goto fail;
3764         }
3765
3766         /* Get VEB bandwidth, to be implemented */
3767         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3768         vsi->uplink_seid = veb->seid;
3769
3770         return veb;
3771 fail:
3772         rte_free(veb);
3773         return NULL;
3774 }
3775
3776 int
3777 i40e_vsi_release(struct i40e_vsi *vsi)
3778 {
3779         struct i40e_pf *pf;
3780         struct i40e_hw *hw;
3781         struct i40e_vsi_list *vsi_list;
3782         int ret;
3783         struct i40e_mac_filter *f;
3784
3785         if (!vsi)
3786                 return I40E_SUCCESS;
3787
3788         pf = I40E_VSI_TO_PF(vsi);
3789         hw = I40E_VSI_TO_HW(vsi);
3790
3791         /* VSI has child to attach, release child first */
3792         if (vsi->veb) {
3793                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3794                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3795                                 return -1;
3796                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3797                 }
3798                 i40e_veb_release(vsi->veb);
3799         }
3800
3801         /* Remove all macvlan filters of the VSI */
3802         i40e_vsi_remove_all_macvlan_filter(vsi);
3803         TAILQ_FOREACH(f, &vsi->mac_list, next)
3804                 rte_free(f);
3805
3806         if (vsi->type != I40E_VSI_MAIN) {
3807                 /* Remove vsi from parent's sibling list */
3808                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3809                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3810                         return I40E_ERR_PARAM;
3811                 }
3812                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3813                                 &vsi->sib_vsi_list, list);
3814
3815                 /* Remove all switch element of the VSI */
3816                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3817                 if (ret != I40E_SUCCESS)
3818                         PMD_DRV_LOG(ERR, "Failed to delete element");
3819         }
3820         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3821
3822         if (vsi->type != I40E_VSI_SRIOV)
3823                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3824         rte_free(vsi);
3825
3826         return I40E_SUCCESS;
3827 }
3828
3829 static int
3830 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3831 {
3832         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3833         struct i40e_aqc_remove_macvlan_element_data def_filter;
3834         struct i40e_mac_filter_info filter;
3835         int ret;
3836
3837         if (vsi->type != I40E_VSI_MAIN)
3838                 return I40E_ERR_CONFIG;
3839         memset(&def_filter, 0, sizeof(def_filter));
3840         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3841                                         ETH_ADDR_LEN);
3842         def_filter.vlan_tag = 0;
3843         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3844                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3845         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3846         if (ret != I40E_SUCCESS) {
3847                 struct i40e_mac_filter *f;
3848                 struct ether_addr *mac;
3849
3850                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3851                             "macvlan filter");
3852                 /* It needs to add the permanent mac into mac list */
3853                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3854                 if (f == NULL) {
3855                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3856                         return I40E_ERR_NO_MEMORY;
3857                 }
3858                 mac = &f->mac_info.mac_addr;
3859                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3860                                 ETH_ADDR_LEN);
3861                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3862                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3863                 vsi->mac_num++;
3864
3865                 return ret;
3866         }
3867         (void)rte_memcpy(&filter.mac_addr,
3868                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3869         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3870         return i40e_vsi_add_mac(vsi, &filter);
3871 }
3872
3873 /*
3874  * i40e_vsi_get_bw_config - Query VSI BW Information
3875  * @vsi: the VSI to be queried
3876  *
3877  * Returns 0 on success, negative value on failure
3878  */
3879 static enum i40e_status_code
3880 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3881 {
3882         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3883         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3884         struct i40e_hw *hw = &vsi->adapter->hw;
3885         i40e_status ret;
3886         int i;
3887         uint32_t bw_max;
3888
3889         memset(&bw_config, 0, sizeof(bw_config));
3890         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3891         if (ret != I40E_SUCCESS) {
3892                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3893                             hw->aq.asq_last_status);
3894                 return ret;
3895         }
3896
3897         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3898         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3899                                         &ets_sla_config, NULL);
3900         if (ret != I40E_SUCCESS) {
3901                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3902                             "configuration %u", hw->aq.asq_last_status);
3903                 return ret;
3904         }
3905
3906         /* store and print out BW info */
3907         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3908         vsi->bw_info.bw_max = bw_config.max_bw;
3909         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3910         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3911         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3912                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3913                      I40E_16_BIT_WIDTH);
3914         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3915                 vsi->bw_info.bw_ets_share_credits[i] =
3916                                 ets_sla_config.share_credits[i];
3917                 vsi->bw_info.bw_ets_credits[i] =
3918                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3919                 /* 4 bits per TC, 4th bit is reserved */
3920                 vsi->bw_info.bw_ets_max[i] =
3921                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3922                                   RTE_LEN2MASK(3, uint8_t));
3923                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3924                             vsi->bw_info.bw_ets_share_credits[i]);
3925                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3926                             vsi->bw_info.bw_ets_credits[i]);
3927                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3928                             vsi->bw_info.bw_ets_max[i]);
3929         }
3930
3931         return I40E_SUCCESS;
3932 }
3933
3934 /* i40e_enable_pf_lb
3935  * @pf: pointer to the pf structure
3936  *
3937  * allow loopback on pf
3938  */
3939 static inline void
3940 i40e_enable_pf_lb(struct i40e_pf *pf)
3941 {
3942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3943         struct i40e_vsi_context ctxt;
3944         int ret;
3945
3946         /* Use the FW API if FW >= v5.0 */
3947         if (hw->aq.fw_maj_ver < 5) {
3948                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
3949                 return;
3950         }
3951
3952         memset(&ctxt, 0, sizeof(ctxt));
3953         ctxt.seid = pf->main_vsi_seid;
3954         ctxt.pf_num = hw->pf_id;
3955         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3956         if (ret) {
3957                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
3958                             ret, hw->aq.asq_last_status);
3959                 return;
3960         }
3961         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3962         ctxt.info.valid_sections =
3963                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3964         ctxt.info.switch_id |=
3965                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3966
3967         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3968         if (ret)
3969                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
3970                             hw->aq.asq_last_status);
3971 }
3972
3973 /* Setup a VSI */
3974 struct i40e_vsi *
3975 i40e_vsi_setup(struct i40e_pf *pf,
3976                enum i40e_vsi_type type,
3977                struct i40e_vsi *uplink_vsi,
3978                uint16_t user_param)
3979 {
3980         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3981         struct i40e_vsi *vsi;
3982         struct i40e_mac_filter_info filter;
3983         int ret;
3984         struct i40e_vsi_context ctxt;
3985         struct ether_addr broadcast =
3986                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3987
3988         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3989                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3990                             "VSI link shouldn't be NULL");
3991                 return NULL;
3992         }
3993
3994         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3995                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3996                             "uplink VSI should be NULL");
3997                 return NULL;
3998         }
3999
4000         /* If uplink vsi didn't setup VEB, create one first */
4001         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4002                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4003
4004                 if (NULL == uplink_vsi->veb) {
4005                         PMD_DRV_LOG(ERR, "VEB setup failed");
4006                         return NULL;
4007                 }
4008                 /* set ALLOWLOOPBACk on pf, when veb is created */
4009                 i40e_enable_pf_lb(pf);
4010         }
4011
4012         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4013         if (!vsi) {
4014                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4015                 return NULL;
4016         }
4017         TAILQ_INIT(&vsi->mac_list);
4018         vsi->type = type;
4019         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4020         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4021         vsi->parent_vsi = uplink_vsi;
4022         vsi->user_param = user_param;
4023         /* Allocate queues */
4024         switch (vsi->type) {
4025         case I40E_VSI_MAIN  :
4026                 vsi->nb_qps = pf->lan_nb_qps;
4027                 break;
4028         case I40E_VSI_SRIOV :
4029                 vsi->nb_qps = pf->vf_nb_qps;
4030                 break;
4031         case I40E_VSI_VMDQ2:
4032                 vsi->nb_qps = pf->vmdq_nb_qps;
4033                 break;
4034         case I40E_VSI_FDIR:
4035                 vsi->nb_qps = pf->fdir_nb_qps;
4036                 break;
4037         default:
4038                 goto fail_mem;
4039         }
4040         /*
4041          * The filter status descriptor is reported in rx queue 0,
4042          * while the tx queue for fdir filter programming has no
4043          * such constraints, can be non-zero queues.
4044          * To simplify it, choose FDIR vsi use queue 0 pair.
4045          * To make sure it will use queue 0 pair, queue allocation
4046          * need be done before this function is called
4047          */
4048         if (type != I40E_VSI_FDIR) {
4049                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4050                         if (ret < 0) {
4051                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4052                                                 vsi->seid, ret);
4053                                 goto fail_mem;
4054                         }
4055                         vsi->base_queue = ret;
4056         } else
4057                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4058
4059         /* VF has MSIX interrupt in VF range, don't allocate here */
4060         if (type == I40E_VSI_MAIN) {
4061                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4062                                           RTE_MIN(vsi->nb_qps,
4063                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4064                 if (ret < 0) {
4065                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4066                                     vsi->seid, ret);
4067                         goto fail_queue_alloc;
4068                 }
4069                 vsi->msix_intr = ret;
4070                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4071         } else if (type != I40E_VSI_SRIOV) {
4072                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4073                 if (ret < 0) {
4074                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4075                         goto fail_queue_alloc;
4076                 }
4077                 vsi->msix_intr = ret;
4078                 vsi->nb_msix = 1;
4079         } else {
4080                 vsi->msix_intr = 0;
4081                 vsi->nb_msix = 0;
4082         }
4083
4084         /* Add VSI */
4085         if (type == I40E_VSI_MAIN) {
4086                 /* For main VSI, no need to add since it's default one */
4087                 vsi->uplink_seid = pf->mac_seid;
4088                 vsi->seid = pf->main_vsi_seid;
4089                 /* Bind queues with specific MSIX interrupt */
4090                 /**
4091                  * Needs 2 interrupt at least, one for misc cause which will
4092                  * enabled from OS side, Another for queues binding the
4093                  * interrupt from device side only.
4094                  */
4095
4096                 /* Get default VSI parameters from hardware */
4097                 memset(&ctxt, 0, sizeof(ctxt));
4098                 ctxt.seid = vsi->seid;
4099                 ctxt.pf_num = hw->pf_id;
4100                 ctxt.uplink_seid = vsi->uplink_seid;
4101                 ctxt.vf_num = 0;
4102                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4103                 if (ret != I40E_SUCCESS) {
4104                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4105                         goto fail_msix_alloc;
4106                 }
4107                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4108                         sizeof(struct i40e_aqc_vsi_properties_data));
4109                 vsi->vsi_id = ctxt.vsi_number;
4110                 vsi->info.valid_sections = 0;
4111
4112                 /* Configure tc, enabled TC0 only */
4113                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4114                         I40E_SUCCESS) {
4115                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4116                         goto fail_msix_alloc;
4117                 }
4118
4119                 /* TC, queue mapping */
4120                 memset(&ctxt, 0, sizeof(ctxt));
4121                 vsi->info.valid_sections |=
4122                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4123                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4124                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4125                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4126                         sizeof(struct i40e_aqc_vsi_properties_data));
4127                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4128                                                 I40E_DEFAULT_TCMAP);
4129                 if (ret != I40E_SUCCESS) {
4130                         PMD_DRV_LOG(ERR, "Failed to configure "
4131                                     "TC queue mapping");
4132                         goto fail_msix_alloc;
4133                 }
4134                 ctxt.seid = vsi->seid;
4135                 ctxt.pf_num = hw->pf_id;
4136                 ctxt.uplink_seid = vsi->uplink_seid;
4137                 ctxt.vf_num = 0;
4138
4139                 /* Update VSI parameters */
4140                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4141                 if (ret != I40E_SUCCESS) {
4142                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4143                         goto fail_msix_alloc;
4144                 }
4145
4146                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4147                                                 sizeof(vsi->info.tc_mapping));
4148                 (void)rte_memcpy(&vsi->info.queue_mapping,
4149                                 &ctxt.info.queue_mapping,
4150                         sizeof(vsi->info.queue_mapping));
4151                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4152                 vsi->info.valid_sections = 0;
4153
4154                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4155                                 ETH_ADDR_LEN);
4156
4157                 /**
4158                  * Updating default filter settings are necessary to prevent
4159                  * reception of tagged packets.
4160                  * Some old firmware configurations load a default macvlan
4161                  * filter which accepts both tagged and untagged packets.
4162                  * The updating is to use a normal filter instead if needed.
4163                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4164                  * The firmware with correct configurations load the default
4165                  * macvlan filter which is expected and cannot be removed.
4166                  */
4167                 i40e_update_default_filter_setting(vsi);
4168                 i40e_config_qinq(hw, vsi);
4169         } else if (type == I40E_VSI_SRIOV) {
4170                 memset(&ctxt, 0, sizeof(ctxt));
4171                 /**
4172                  * For other VSI, the uplink_seid equals to uplink VSI's
4173                  * uplink_seid since they share same VEB
4174                  */
4175                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4176                 ctxt.pf_num = hw->pf_id;
4177                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4178                 ctxt.uplink_seid = vsi->uplink_seid;
4179                 ctxt.connection_type = 0x1;
4180                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4181
4182                 /* Use the VEB configuration if FW >= v5.0 */
4183                 if (hw->aq.fw_maj_ver >= 5) {
4184                         /* Configure switch ID */
4185                         ctxt.info.valid_sections |=
4186                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4187                         ctxt.info.switch_id =
4188                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4189                 }
4190
4191                 /* Configure port/vlan */
4192                 ctxt.info.valid_sections |=
4193                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4194                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4195                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4196                                                 I40E_DEFAULT_TCMAP);
4197                 if (ret != I40E_SUCCESS) {
4198                         PMD_DRV_LOG(ERR, "Failed to configure "
4199                                     "TC queue mapping");
4200                         goto fail_msix_alloc;
4201                 }
4202                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4203                 ctxt.info.valid_sections |=
4204                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4205                 /**
4206                  * Since VSI is not created yet, only configure parameter,
4207                  * will add vsi below.
4208                  */
4209
4210                 i40e_config_qinq(hw, vsi);
4211         } else if (type == I40E_VSI_VMDQ2) {
4212                 memset(&ctxt, 0, sizeof(ctxt));
4213                 /*
4214                  * For other VSI, the uplink_seid equals to uplink VSI's
4215                  * uplink_seid since they share same VEB
4216                  */
4217                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4218                 ctxt.pf_num = hw->pf_id;
4219                 ctxt.vf_num = 0;
4220                 ctxt.uplink_seid = vsi->uplink_seid;
4221                 ctxt.connection_type = 0x1;
4222                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4223
4224                 ctxt.info.valid_sections |=
4225                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4226                 /* user_param carries flag to enable loop back */
4227                 if (user_param) {
4228                         ctxt.info.switch_id =
4229                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4230                         ctxt.info.switch_id |=
4231                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4232                 }
4233
4234                 /* Configure port/vlan */
4235                 ctxt.info.valid_sections |=
4236                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4237                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4238                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4239                                                 I40E_DEFAULT_TCMAP);
4240                 if (ret != I40E_SUCCESS) {
4241                         PMD_DRV_LOG(ERR, "Failed to configure "
4242                                         "TC queue mapping");
4243                         goto fail_msix_alloc;
4244                 }
4245                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4246                 ctxt.info.valid_sections |=
4247                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4248         } else if (type == I40E_VSI_FDIR) {
4249                 memset(&ctxt, 0, sizeof(ctxt));
4250                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4251                 ctxt.pf_num = hw->pf_id;
4252                 ctxt.vf_num = 0;
4253                 ctxt.uplink_seid = vsi->uplink_seid;
4254                 ctxt.connection_type = 0x1;     /* regular data port */
4255                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4256                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4257                                                 I40E_DEFAULT_TCMAP);
4258                 if (ret != I40E_SUCCESS) {
4259                         PMD_DRV_LOG(ERR, "Failed to configure "
4260                                         "TC queue mapping.");
4261                         goto fail_msix_alloc;
4262                 }
4263                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4264                 ctxt.info.valid_sections |=
4265                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4266         } else {
4267                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4268                 goto fail_msix_alloc;
4269         }
4270
4271         if (vsi->type != I40E_VSI_MAIN) {
4272                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4273                 if (ret != I40E_SUCCESS) {
4274                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4275                                     hw->aq.asq_last_status);
4276                         goto fail_msix_alloc;
4277                 }
4278                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4279                 vsi->info.valid_sections = 0;
4280                 vsi->seid = ctxt.seid;
4281                 vsi->vsi_id = ctxt.vsi_number;
4282                 vsi->sib_vsi_list.vsi = vsi;
4283                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4284                                 &vsi->sib_vsi_list, list);
4285         }
4286
4287         /* MAC/VLAN configuration */
4288         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4289         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4290
4291         ret = i40e_vsi_add_mac(vsi, &filter);
4292         if (ret != I40E_SUCCESS) {
4293                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4294                 goto fail_msix_alloc;
4295         }
4296
4297         /* Get VSI BW information */
4298         i40e_vsi_get_bw_config(vsi);
4299         return vsi;
4300 fail_msix_alloc:
4301         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4302 fail_queue_alloc:
4303         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4304 fail_mem:
4305         rte_free(vsi);
4306         return NULL;
4307 }
4308
4309 /* Configure vlan filter on or off */
4310 int
4311 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4312 {
4313         int i, num;
4314         struct i40e_mac_filter *f;
4315         struct i40e_mac_filter_info *mac_filter;
4316         enum rte_mac_filter_type desired_filter;
4317         int ret = I40E_SUCCESS;
4318
4319         if (on) {
4320                 /* Filter to match MAC and VLAN */
4321                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4322         } else {
4323                 /* Filter to match only MAC */
4324                 desired_filter = RTE_MAC_PERFECT_MATCH;
4325         }
4326
4327         num = vsi->mac_num;
4328
4329         mac_filter = rte_zmalloc("mac_filter_info_data",
4330                                  num * sizeof(*mac_filter), 0);
4331         if (mac_filter == NULL) {
4332                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4333                 return I40E_ERR_NO_MEMORY;
4334         }
4335
4336         i = 0;
4337
4338         /* Remove all existing mac */
4339         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4340                 mac_filter[i] = f->mac_info;
4341                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4342                 if (ret) {
4343                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4344                                     on ? "enable" : "disable");
4345                         goto DONE;
4346                 }
4347                 i++;
4348         }
4349
4350         /* Override with new filter */
4351         for (i = 0; i < num; i++) {
4352                 mac_filter[i].filter_type = desired_filter;
4353                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4354                 if (ret) {
4355                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4356                                     on ? "enable" : "disable");
4357                         goto DONE;
4358                 }
4359         }
4360
4361 DONE:
4362         rte_free(mac_filter);
4363         return ret;
4364 }
4365
4366 /* Configure vlan stripping on or off */
4367 int
4368 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4369 {
4370         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4371         struct i40e_vsi_context ctxt;
4372         uint8_t vlan_flags;
4373         int ret = I40E_SUCCESS;
4374
4375         /* Check if it has been already on or off */
4376         if (vsi->info.valid_sections &
4377                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4378                 if (on) {
4379                         if ((vsi->info.port_vlan_flags &
4380                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4381                                 return 0; /* already on */
4382                 } else {
4383                         if ((vsi->info.port_vlan_flags &
4384                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4385                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4386                                 return 0; /* already off */
4387                 }
4388         }
4389
4390         if (on)
4391                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4392         else
4393                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4394         vsi->info.valid_sections =
4395                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4396         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4397         vsi->info.port_vlan_flags |= vlan_flags;
4398         ctxt.seid = vsi->seid;
4399         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4400         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401         if (ret)
4402                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4403                             on ? "enable" : "disable");
4404
4405         return ret;
4406 }
4407
4408 static int
4409 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4410 {
4411         struct rte_eth_dev_data *data = dev->data;
4412         int ret;
4413         int mask = 0;
4414
4415         /* Apply vlan offload setting */
4416         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4417         i40e_vlan_offload_set(dev, mask);
4418
4419         /* Apply double-vlan setting, not implemented yet */
4420
4421         /* Apply pvid setting */
4422         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4423                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4424         if (ret)
4425                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4426
4427         return ret;
4428 }
4429
4430 static int
4431 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4432 {
4433         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4434
4435         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4436 }
4437
4438 static int
4439 i40e_update_flow_control(struct i40e_hw *hw)
4440 {
4441 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4442         struct i40e_link_status link_status;
4443         uint32_t rxfc = 0, txfc = 0, reg;
4444         uint8_t an_info;
4445         int ret;
4446
4447         memset(&link_status, 0, sizeof(link_status));
4448         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4449         if (ret != I40E_SUCCESS) {
4450                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4451                 goto write_reg; /* Disable flow control */
4452         }
4453
4454         an_info = hw->phy.link_info.an_info;
4455         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4456                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4457                 ret = I40E_ERR_NOT_READY;
4458                 goto write_reg; /* Disable flow control */
4459         }
4460         /**
4461          * If link auto negotiation is enabled, flow control needs to
4462          * be configured according to it
4463          */
4464         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4465         case I40E_LINK_PAUSE_RXTX:
4466                 rxfc = 1;
4467                 txfc = 1;
4468                 hw->fc.current_mode = I40E_FC_FULL;
4469                 break;
4470         case I40E_AQ_LINK_PAUSE_RX:
4471                 rxfc = 1;
4472                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4473                 break;
4474         case I40E_AQ_LINK_PAUSE_TX:
4475                 txfc = 1;
4476                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4477                 break;
4478         default:
4479                 hw->fc.current_mode = I40E_FC_NONE;
4480                 break;
4481         }
4482
4483 write_reg:
4484         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4485                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4486         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4487         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4488         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4489         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4490
4491         return ret;
4492 }
4493
4494 /* PF setup */
4495 static int
4496 i40e_pf_setup(struct i40e_pf *pf)
4497 {
4498         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4499         struct i40e_filter_control_settings settings;
4500         struct i40e_vsi *vsi;
4501         int ret;
4502
4503         /* Clear all stats counters */
4504         pf->offset_loaded = FALSE;
4505         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4506         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4507
4508         ret = i40e_pf_get_switch_config(pf);
4509         if (ret != I40E_SUCCESS) {
4510                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4511                 return ret;
4512         }
4513         if (pf->flags & I40E_FLAG_FDIR) {
4514                 /* make queue allocated first, let FDIR use queue pair 0*/
4515                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4516                 if (ret != I40E_FDIR_QUEUE_ID) {
4517                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4518                                     " ret =%d", ret);
4519                         pf->flags &= ~I40E_FLAG_FDIR;
4520                 }
4521         }
4522         /*  main VSI setup */
4523         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4524         if (!vsi) {
4525                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4526                 return I40E_ERR_NOT_READY;
4527         }
4528         pf->main_vsi = vsi;
4529
4530         /* Configure filter control */
4531         memset(&settings, 0, sizeof(settings));
4532         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4533                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4534         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4535                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4536         else {
4537                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4538                                                 hw->func_caps.rss_table_size);
4539                 return I40E_ERR_PARAM;
4540         }
4541         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4542                         "size: %u\n", hw->func_caps.rss_table_size);
4543         pf->hash_lut_size = hw->func_caps.rss_table_size;
4544
4545         /* Enable ethtype and macvlan filters */
4546         settings.enable_ethtype = TRUE;
4547         settings.enable_macvlan = TRUE;
4548         ret = i40e_set_filter_control(hw, &settings);
4549         if (ret)
4550                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4551                                                                 ret);
4552
4553         /* Update flow control according to the auto negotiation */
4554         i40e_update_flow_control(hw);
4555
4556         return I40E_SUCCESS;
4557 }
4558
4559 int
4560 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4561 {
4562         uint32_t reg;
4563         uint16_t j;
4564
4565         /**
4566          * Set or clear TX Queue Disable flags,
4567          * which is required by hardware.
4568          */
4569         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4570         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4571
4572         /* Wait until the request is finished */
4573         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4574                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4575                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4576                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4577                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4578                                                         & 0x1))) {
4579                         break;
4580                 }
4581         }
4582         if (on) {
4583                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4584                         return I40E_SUCCESS; /* already on, skip next steps */
4585
4586                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4587                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4588         } else {
4589                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4590                         return I40E_SUCCESS; /* already off, skip next steps */
4591                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4592         }
4593         /* Write the register */
4594         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4595         /* Check the result */
4596         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4597                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4598                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4599                 if (on) {
4600                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4601                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4602                                 break;
4603                 } else {
4604                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4605                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4606                                 break;
4607                 }
4608         }
4609         /* Check if it is timeout */
4610         if (j >= I40E_CHK_Q_ENA_COUNT) {
4611                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4612                             (on ? "enable" : "disable"), q_idx);
4613                 return I40E_ERR_TIMEOUT;
4614         }
4615
4616         return I40E_SUCCESS;
4617 }
4618
4619 /* Swith on or off the tx queues */
4620 static int
4621 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4622 {
4623         struct rte_eth_dev_data *dev_data = pf->dev_data;
4624         struct i40e_tx_queue *txq;
4625         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4626         uint16_t i;
4627         int ret;
4628
4629         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4630                 txq = dev_data->tx_queues[i];
4631                 /* Don't operate the queue if not configured or
4632                  * if starting only per queue */
4633                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4634                         continue;
4635                 if (on)
4636                         ret = i40e_dev_tx_queue_start(dev, i);
4637                 else
4638                         ret = i40e_dev_tx_queue_stop(dev, i);
4639                 if ( ret != I40E_SUCCESS)
4640                         return ret;
4641         }
4642
4643         return I40E_SUCCESS;
4644 }
4645
4646 int
4647 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4648 {
4649         uint32_t reg;
4650         uint16_t j;
4651
4652         /* Wait until the request is finished */
4653         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4654                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4655                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4656                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4657                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4658                         break;
4659         }
4660
4661         if (on) {
4662                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4663                         return I40E_SUCCESS; /* Already on, skip next steps */
4664                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4665         } else {
4666                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4667                         return I40E_SUCCESS; /* Already off, skip next steps */
4668                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4669         }
4670
4671         /* Write the register */
4672         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4673         /* Check the result */
4674         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4675                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4676                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4677                 if (on) {
4678                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4679                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4680                                 break;
4681                 } else {
4682                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4683                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4684                                 break;
4685                 }
4686         }
4687
4688         /* Check if it is timeout */
4689         if (j >= I40E_CHK_Q_ENA_COUNT) {
4690                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4691                             (on ? "enable" : "disable"), q_idx);
4692                 return I40E_ERR_TIMEOUT;
4693         }
4694
4695         return I40E_SUCCESS;
4696 }
4697 /* Switch on or off the rx queues */
4698 static int
4699 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4700 {
4701         struct rte_eth_dev_data *dev_data = pf->dev_data;
4702         struct i40e_rx_queue *rxq;
4703         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4704         uint16_t i;
4705         int ret;
4706
4707         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4708                 rxq = dev_data->rx_queues[i];
4709                 /* Don't operate the queue if not configured or
4710                  * if starting only per queue */
4711                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4712                         continue;
4713                 if (on)
4714                         ret = i40e_dev_rx_queue_start(dev, i);
4715                 else
4716                         ret = i40e_dev_rx_queue_stop(dev, i);
4717                 if (ret != I40E_SUCCESS)
4718                         return ret;
4719         }
4720
4721         return I40E_SUCCESS;
4722 }
4723
4724 /* Switch on or off all the rx/tx queues */
4725 int
4726 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4727 {
4728         int ret;
4729
4730         if (on) {
4731                 /* enable rx queues before enabling tx queues */
4732                 ret = i40e_dev_switch_rx_queues(pf, on);
4733                 if (ret) {
4734                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4735                         return ret;
4736                 }
4737                 ret = i40e_dev_switch_tx_queues(pf, on);
4738         } else {
4739                 /* Stop tx queues before stopping rx queues */
4740                 ret = i40e_dev_switch_tx_queues(pf, on);
4741                 if (ret) {
4742                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4743                         return ret;
4744                 }
4745                 ret = i40e_dev_switch_rx_queues(pf, on);
4746         }
4747
4748         return ret;
4749 }
4750
4751 /* Initialize VSI for TX */
4752 static int
4753 i40e_dev_tx_init(struct i40e_pf *pf)
4754 {
4755         struct rte_eth_dev_data *data = pf->dev_data;
4756         uint16_t i;
4757         uint32_t ret = I40E_SUCCESS;
4758         struct i40e_tx_queue *txq;
4759
4760         for (i = 0; i < data->nb_tx_queues; i++) {
4761                 txq = data->tx_queues[i];
4762                 if (!txq || !txq->q_set)
4763                         continue;
4764                 ret = i40e_tx_queue_init(txq);
4765                 if (ret != I40E_SUCCESS)
4766                         break;
4767         }
4768         if (ret == I40E_SUCCESS)
4769                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4770                                      ->eth_dev);
4771
4772         return ret;
4773 }
4774
4775 /* Initialize VSI for RX */
4776 static int
4777 i40e_dev_rx_init(struct i40e_pf *pf)
4778 {
4779         struct rte_eth_dev_data *data = pf->dev_data;
4780         int ret = I40E_SUCCESS;
4781         uint16_t i;
4782         struct i40e_rx_queue *rxq;
4783
4784         i40e_pf_config_mq_rx(pf);
4785         for (i = 0; i < data->nb_rx_queues; i++) {
4786                 rxq = data->rx_queues[i];
4787                 if (!rxq || !rxq->q_set)
4788                         continue;
4789
4790                 ret = i40e_rx_queue_init(rxq);
4791                 if (ret != I40E_SUCCESS) {
4792                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4793                                     "initialization");
4794                         break;
4795                 }
4796         }
4797         if (ret == I40E_SUCCESS)
4798                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4799                                      ->eth_dev);
4800
4801         return ret;
4802 }
4803
4804 static int
4805 i40e_dev_rxtx_init(struct i40e_pf *pf)
4806 {
4807         int err;
4808
4809         err = i40e_dev_tx_init(pf);
4810         if (err) {
4811                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4812                 return err;
4813         }
4814         err = i40e_dev_rx_init(pf);
4815         if (err) {
4816                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4817                 return err;
4818         }
4819
4820         return err;
4821 }
4822
4823 static int
4824 i40e_vmdq_setup(struct rte_eth_dev *dev)
4825 {
4826         struct rte_eth_conf *conf = &dev->data->dev_conf;
4827         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4828         int i, err, conf_vsis, j, loop;
4829         struct i40e_vsi *vsi;
4830         struct i40e_vmdq_info *vmdq_info;
4831         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4832         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4833
4834         /*
4835          * Disable interrupt to avoid message from VF. Furthermore, it will
4836          * avoid race condition in VSI creation/destroy.
4837          */
4838         i40e_pf_disable_irq0(hw);
4839
4840         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4841                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4842                 return -ENOTSUP;
4843         }
4844
4845         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4846         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4847                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4848                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4849                         pf->max_nb_vmdq_vsi);
4850                 return -ENOTSUP;
4851         }
4852
4853         if (pf->vmdq != NULL) {
4854                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4855                 return 0;
4856         }
4857
4858         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4859                                 sizeof(*vmdq_info) * conf_vsis, 0);
4860
4861         if (pf->vmdq == NULL) {
4862                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4863                 return -ENOMEM;
4864         }
4865
4866         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4867
4868         /* Create VMDQ VSI */
4869         for (i = 0; i < conf_vsis; i++) {
4870                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4871                                 vmdq_conf->enable_loop_back);
4872                 if (vsi == NULL) {
4873                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4874                         err = -1;
4875                         goto err_vsi_setup;
4876                 }
4877                 vmdq_info = &pf->vmdq[i];
4878                 vmdq_info->pf = pf;
4879                 vmdq_info->vsi = vsi;
4880         }
4881         pf->nb_cfg_vmdq_vsi = conf_vsis;
4882
4883         /* Configure Vlan */
4884         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4885         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4886                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4887                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4888                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4889                                         vmdq_conf->pool_map[i].vlan_id, j);
4890
4891                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4892                                                 vmdq_conf->pool_map[i].vlan_id);
4893                                 if (err) {
4894                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4895                                         err = -1;
4896                                         goto err_vsi_setup;
4897                                 }
4898                         }
4899                 }
4900         }
4901
4902         i40e_pf_enable_irq0(hw);
4903
4904         return 0;
4905
4906 err_vsi_setup:
4907         for (i = 0; i < conf_vsis; i++)
4908                 if (pf->vmdq[i].vsi == NULL)
4909                         break;
4910                 else
4911                         i40e_vsi_release(pf->vmdq[i].vsi);
4912
4913         rte_free(pf->vmdq);
4914         pf->vmdq = NULL;
4915         i40e_pf_enable_irq0(hw);
4916         return err;
4917 }
4918
4919 static void
4920 i40e_stat_update_32(struct i40e_hw *hw,
4921                    uint32_t reg,
4922                    bool offset_loaded,
4923                    uint64_t *offset,
4924                    uint64_t *stat)
4925 {
4926         uint64_t new_data;
4927
4928         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4929         if (!offset_loaded)
4930                 *offset = new_data;
4931
4932         if (new_data >= *offset)
4933                 *stat = (uint64_t)(new_data - *offset);
4934         else
4935                 *stat = (uint64_t)((new_data +
4936                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4937 }
4938
4939 static void
4940 i40e_stat_update_48(struct i40e_hw *hw,
4941                    uint32_t hireg,
4942                    uint32_t loreg,
4943                    bool offset_loaded,
4944                    uint64_t *offset,
4945                    uint64_t *stat)
4946 {
4947         uint64_t new_data;
4948
4949         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4950         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4951                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4952
4953         if (!offset_loaded)
4954                 *offset = new_data;
4955
4956         if (new_data >= *offset)
4957                 *stat = new_data - *offset;
4958         else
4959                 *stat = (uint64_t)((new_data +
4960                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4961
4962         *stat &= I40E_48_BIT_MASK;
4963 }
4964
4965 /* Disable IRQ0 */
4966 void
4967 i40e_pf_disable_irq0(struct i40e_hw *hw)
4968 {
4969         /* Disable all interrupt types */
4970         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4971         I40E_WRITE_FLUSH(hw);
4972 }
4973
4974 /* Enable IRQ0 */
4975 void
4976 i40e_pf_enable_irq0(struct i40e_hw *hw)
4977 {
4978         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4979                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4980                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4981                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4982         I40E_WRITE_FLUSH(hw);
4983 }
4984
4985 static void
4986 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4987 {
4988         /* read pending request and disable first */
4989         i40e_pf_disable_irq0(hw);
4990         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4991         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4992                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4993
4994         if (no_queue)
4995                 /* Link no queues with irq0 */
4996                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4997                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4998 }
4999
5000 static void
5001 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5002 {
5003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5005         int i;
5006         uint16_t abs_vf_id;
5007         uint32_t index, offset, val;
5008
5009         if (!pf->vfs)
5010                 return;
5011         /**
5012          * Try to find which VF trigger a reset, use absolute VF id to access
5013          * since the reg is global register.
5014          */
5015         for (i = 0; i < pf->vf_num; i++) {
5016                 abs_vf_id = hw->func_caps.vf_base_id + i;
5017                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5018                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5019                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5020                 /* VFR event occured */
5021                 if (val & (0x1 << offset)) {
5022                         int ret;
5023
5024                         /* Clear the event first */
5025                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5026                                                         (0x1 << offset));
5027                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5028                         /**
5029                          * Only notify a VF reset event occured,
5030                          * don't trigger another SW reset
5031                          */
5032                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5033                         if (ret != I40E_SUCCESS)
5034                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5035                 }
5036         }
5037 }
5038
5039 static void
5040 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5041 {
5042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043         struct i40e_arq_event_info info;
5044         uint16_t pending, opcode;
5045         int ret;
5046
5047         info.buf_len = I40E_AQ_BUF_SZ;
5048         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5049         if (!info.msg_buf) {
5050                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5051                 return;
5052         }
5053
5054         pending = 1;
5055         while (pending) {
5056                 ret = i40e_clean_arq_element(hw, &info, &pending);
5057
5058                 if (ret != I40E_SUCCESS) {
5059                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5060                                     "aq_err: %u", hw->aq.asq_last_status);
5061                         break;
5062                 }
5063                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5064
5065                 switch (opcode) {
5066                 case i40e_aqc_opc_send_msg_to_pf:
5067                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5068                         i40e_pf_host_handle_vf_msg(dev,
5069                                         rte_le_to_cpu_16(info.desc.retval),
5070                                         rte_le_to_cpu_32(info.desc.cookie_high),
5071                                         rte_le_to_cpu_32(info.desc.cookie_low),
5072                                         info.msg_buf,
5073                                         info.msg_len);
5074                         break;
5075                 default:
5076                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5077                                     opcode);
5078                         break;
5079                 }
5080         }
5081         rte_free(info.msg_buf);
5082 }
5083
5084 /*
5085  * Interrupt handler is registered as the alarm callback for handling LSC
5086  * interrupt in a definite of time, in order to wait the NIC into a stable
5087  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5088  * no need for link down interrupt.
5089  */
5090 static void
5091 i40e_dev_interrupt_delayed_handler(void *param)
5092 {
5093         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5094         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5095         uint32_t icr0;
5096
5097         /* read interrupt causes again */
5098         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5099
5100 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5101         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5102                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5103         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5104                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5105         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5106                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5107         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5108                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5109         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5110                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5111                                                                 "state\n");
5112         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5113                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5114         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5115                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5116 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5117
5118         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5119                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5120                 i40e_dev_handle_vfr_event(dev);
5121         }
5122         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5123                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5124                 i40e_dev_handle_aq_msg(dev);
5125         }
5126
5127         /* handle the link up interrupt in an alarm callback */
5128         i40e_dev_link_update(dev, 0);
5129         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5130
5131         i40e_pf_enable_irq0(hw);
5132         rte_intr_enable(&(dev->pci_dev->intr_handle));
5133 }
5134
5135 /**
5136  * Interrupt handler triggered by NIC  for handling
5137  * specific interrupt.
5138  *
5139  * @param handle
5140  *  Pointer to interrupt handle.
5141  * @param param
5142  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5143  *
5144  * @return
5145  *  void
5146  */
5147 static void
5148 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5149                            void *param)
5150 {
5151         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5152         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153         uint32_t icr0;
5154
5155         /* Disable interrupt */
5156         i40e_pf_disable_irq0(hw);
5157
5158         /* read out interrupt causes */
5159         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5160
5161         /* No interrupt event indicated */
5162         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5163                 PMD_DRV_LOG(INFO, "No interrupt event");
5164                 goto done;
5165         }
5166 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5167         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5168                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5169         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5170                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5171         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5172                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5173         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5174                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5175         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5176                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5177         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5178                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5179         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5180                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5181 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5182
5183         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5184                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5185                 i40e_dev_handle_vfr_event(dev);
5186         }
5187         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5188                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5189                 i40e_dev_handle_aq_msg(dev);
5190         }
5191
5192         /* Link Status Change interrupt */
5193         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5194 #define I40E_US_PER_SECOND 1000000
5195                 struct rte_eth_link link;
5196
5197                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5198                 memset(&link, 0, sizeof(link));
5199                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5200                 i40e_dev_link_update(dev, 0);
5201
5202                 /*
5203                  * For link up interrupt, it needs to wait 1 second to let the
5204                  * hardware be a stable state. Otherwise several consecutive
5205                  * interrupts can be observed.
5206                  * For link down interrupt, no need to wait.
5207                  */
5208                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5209                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5210                         return;
5211                 else
5212                         _rte_eth_dev_callback_process(dev,
5213                                 RTE_ETH_EVENT_INTR_LSC);
5214         }
5215
5216 done:
5217         /* Enable interrupt */
5218         i40e_pf_enable_irq0(hw);
5219         rte_intr_enable(&(dev->pci_dev->intr_handle));
5220 }
5221
5222 static int
5223 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5224                          struct i40e_macvlan_filter *filter,
5225                          int total)
5226 {
5227         int ele_num, ele_buff_size;
5228         int num, actual_num, i;
5229         uint16_t flags;
5230         int ret = I40E_SUCCESS;
5231         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5232         struct i40e_aqc_add_macvlan_element_data *req_list;
5233
5234         if (filter == NULL  || total == 0)
5235                 return I40E_ERR_PARAM;
5236         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5237         ele_buff_size = hw->aq.asq_buf_size;
5238
5239         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5240         if (req_list == NULL) {
5241                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5242                 return I40E_ERR_NO_MEMORY;
5243         }
5244
5245         num = 0;
5246         do {
5247                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5248                 memset(req_list, 0, ele_buff_size);
5249
5250                 for (i = 0; i < actual_num; i++) {
5251                         (void)rte_memcpy(req_list[i].mac_addr,
5252                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5253                         req_list[i].vlan_tag =
5254                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5255
5256                         switch (filter[num + i].filter_type) {
5257                         case RTE_MAC_PERFECT_MATCH:
5258                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5259                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5260                                 break;
5261                         case RTE_MACVLAN_PERFECT_MATCH:
5262                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5263                                 break;
5264                         case RTE_MAC_HASH_MATCH:
5265                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5266                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5267                                 break;
5268                         case RTE_MACVLAN_HASH_MATCH:
5269                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5270                                 break;
5271                         default:
5272                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5273                                 ret = I40E_ERR_PARAM;
5274                                 goto DONE;
5275                         }
5276
5277                         req_list[i].queue_number = 0;
5278
5279                         req_list[i].flags = rte_cpu_to_le_16(flags);
5280                 }
5281
5282                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5283                                                 actual_num, NULL);
5284                 if (ret != I40E_SUCCESS) {
5285                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5286                         goto DONE;
5287                 }
5288                 num += actual_num;
5289         } while (num < total);
5290
5291 DONE:
5292         rte_free(req_list);
5293         return ret;
5294 }
5295
5296 static int
5297 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5298                             struct i40e_macvlan_filter *filter,
5299                             int total)
5300 {
5301         int ele_num, ele_buff_size;
5302         int num, actual_num, i;
5303         uint16_t flags;
5304         int ret = I40E_SUCCESS;
5305         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5306         struct i40e_aqc_remove_macvlan_element_data *req_list;
5307
5308         if (filter == NULL  || total == 0)
5309                 return I40E_ERR_PARAM;
5310
5311         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5312         ele_buff_size = hw->aq.asq_buf_size;
5313
5314         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5315         if (req_list == NULL) {
5316                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5317                 return I40E_ERR_NO_MEMORY;
5318         }
5319
5320         num = 0;
5321         do {
5322                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5323                 memset(req_list, 0, ele_buff_size);
5324
5325                 for (i = 0; i < actual_num; i++) {
5326                         (void)rte_memcpy(req_list[i].mac_addr,
5327                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5328                         req_list[i].vlan_tag =
5329                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5330
5331                         switch (filter[num + i].filter_type) {
5332                         case RTE_MAC_PERFECT_MATCH:
5333                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5334                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5335                                 break;
5336                         case RTE_MACVLAN_PERFECT_MATCH:
5337                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5338                                 break;
5339                         case RTE_MAC_HASH_MATCH:
5340                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5341                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5342                                 break;
5343                         case RTE_MACVLAN_HASH_MATCH:
5344                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5345                                 break;
5346                         default:
5347                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5348                                 ret = I40E_ERR_PARAM;
5349                                 goto DONE;
5350                         }
5351                         req_list[i].flags = rte_cpu_to_le_16(flags);
5352                 }
5353
5354                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5355                                                 actual_num, NULL);
5356                 if (ret != I40E_SUCCESS) {
5357                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5358                         goto DONE;
5359                 }
5360                 num += actual_num;
5361         } while (num < total);
5362
5363 DONE:
5364         rte_free(req_list);
5365         return ret;
5366 }
5367
5368 /* Find out specific MAC filter */
5369 static struct i40e_mac_filter *
5370 i40e_find_mac_filter(struct i40e_vsi *vsi,
5371                          struct ether_addr *macaddr)
5372 {
5373         struct i40e_mac_filter *f;
5374
5375         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5376                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5377                         return f;
5378         }
5379
5380         return NULL;
5381 }
5382
5383 static bool
5384 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5385                          uint16_t vlan_id)
5386 {
5387         uint32_t vid_idx, vid_bit;
5388
5389         if (vlan_id > ETH_VLAN_ID_MAX)
5390                 return 0;
5391
5392         vid_idx = I40E_VFTA_IDX(vlan_id);
5393         vid_bit = I40E_VFTA_BIT(vlan_id);
5394
5395         if (vsi->vfta[vid_idx] & vid_bit)
5396                 return 1;
5397         else
5398                 return 0;
5399 }
5400
5401 static void
5402 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5403                          uint16_t vlan_id, bool on)
5404 {
5405         uint32_t vid_idx, vid_bit;
5406
5407         if (vlan_id > ETH_VLAN_ID_MAX)
5408                 return;
5409
5410         vid_idx = I40E_VFTA_IDX(vlan_id);
5411         vid_bit = I40E_VFTA_BIT(vlan_id);
5412
5413         if (on)
5414                 vsi->vfta[vid_idx] |= vid_bit;
5415         else
5416                 vsi->vfta[vid_idx] &= ~vid_bit;
5417 }
5418
5419 /**
5420  * Find all vlan options for specific mac addr,
5421  * return with actual vlan found.
5422  */
5423 static inline int
5424 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5425                            struct i40e_macvlan_filter *mv_f,
5426                            int num, struct ether_addr *addr)
5427 {
5428         int i;
5429         uint32_t j, k;
5430
5431         /**
5432          * Not to use i40e_find_vlan_filter to decrease the loop time,
5433          * although the code looks complex.
5434           */
5435         if (num < vsi->vlan_num)
5436                 return I40E_ERR_PARAM;
5437
5438         i = 0;
5439         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5440                 if (vsi->vfta[j]) {
5441                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5442                                 if (vsi->vfta[j] & (1 << k)) {
5443                                         if (i > num - 1) {
5444                                                 PMD_DRV_LOG(ERR, "vlan number "
5445                                                             "not match");
5446                                                 return I40E_ERR_PARAM;
5447                                         }
5448                                         (void)rte_memcpy(&mv_f[i].macaddr,
5449                                                         addr, ETH_ADDR_LEN);
5450                                         mv_f[i].vlan_id =
5451                                                 j * I40E_UINT32_BIT_SIZE + k;
5452                                         i++;
5453                                 }
5454                         }
5455                 }
5456         }
5457         return I40E_SUCCESS;
5458 }
5459
5460 static inline int
5461 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5462                            struct i40e_macvlan_filter *mv_f,
5463                            int num,
5464                            uint16_t vlan)
5465 {
5466         int i = 0;
5467         struct i40e_mac_filter *f;
5468
5469         if (num < vsi->mac_num)
5470                 return I40E_ERR_PARAM;
5471
5472         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5473                 if (i > num - 1) {
5474                         PMD_DRV_LOG(ERR, "buffer number not match");
5475                         return I40E_ERR_PARAM;
5476                 }
5477                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5478                                 ETH_ADDR_LEN);
5479                 mv_f[i].vlan_id = vlan;
5480                 mv_f[i].filter_type = f->mac_info.filter_type;
5481                 i++;
5482         }
5483
5484         return I40E_SUCCESS;
5485 }
5486
5487 static int
5488 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5489 {
5490         int i, num;
5491         struct i40e_mac_filter *f;
5492         struct i40e_macvlan_filter *mv_f;
5493         int ret = I40E_SUCCESS;
5494
5495         if (vsi == NULL || vsi->mac_num == 0)
5496                 return I40E_ERR_PARAM;
5497
5498         /* Case that no vlan is set */
5499         if (vsi->vlan_num == 0)
5500                 num = vsi->mac_num;
5501         else
5502                 num = vsi->mac_num * vsi->vlan_num;
5503
5504         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5505         if (mv_f == NULL) {
5506                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5507                 return I40E_ERR_NO_MEMORY;
5508         }
5509
5510         i = 0;
5511         if (vsi->vlan_num == 0) {
5512                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5513                         (void)rte_memcpy(&mv_f[i].macaddr,
5514                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5515                         mv_f[i].vlan_id = 0;
5516                         i++;
5517                 }
5518         } else {
5519                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5520                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5521                                         vsi->vlan_num, &f->mac_info.mac_addr);
5522                         if (ret != I40E_SUCCESS)
5523                                 goto DONE;
5524                         i += vsi->vlan_num;
5525                 }
5526         }
5527
5528         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5529 DONE:
5530         rte_free(mv_f);
5531
5532         return ret;
5533 }
5534
5535 int
5536 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5537 {
5538         struct i40e_macvlan_filter *mv_f;
5539         int mac_num;
5540         int ret = I40E_SUCCESS;
5541
5542         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5543                 return I40E_ERR_PARAM;
5544
5545         /* If it's already set, just return */
5546         if (i40e_find_vlan_filter(vsi,vlan))
5547                 return I40E_SUCCESS;
5548
5549         mac_num = vsi->mac_num;
5550
5551         if (mac_num == 0) {
5552                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5553                 return I40E_ERR_PARAM;
5554         }
5555
5556         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5557
5558         if (mv_f == NULL) {
5559                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5560                 return I40E_ERR_NO_MEMORY;
5561         }
5562
5563         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5564
5565         if (ret != I40E_SUCCESS)
5566                 goto DONE;
5567
5568         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5569
5570         if (ret != I40E_SUCCESS)
5571                 goto DONE;
5572
5573         i40e_set_vlan_filter(vsi, vlan, 1);
5574
5575         vsi->vlan_num++;
5576         ret = I40E_SUCCESS;
5577 DONE:
5578         rte_free(mv_f);
5579         return ret;
5580 }
5581
5582 int
5583 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5584 {
5585         struct i40e_macvlan_filter *mv_f;
5586         int mac_num;
5587         int ret = I40E_SUCCESS;
5588
5589         /**
5590          * Vlan 0 is the generic filter for untagged packets
5591          * and can't be removed.
5592          */
5593         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5594                 return I40E_ERR_PARAM;
5595
5596         /* If can't find it, just return */
5597         if (!i40e_find_vlan_filter(vsi, vlan))
5598                 return I40E_ERR_PARAM;
5599
5600         mac_num = vsi->mac_num;
5601
5602         if (mac_num == 0) {
5603                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5604                 return I40E_ERR_PARAM;
5605         }
5606
5607         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5608
5609         if (mv_f == NULL) {
5610                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5611                 return I40E_ERR_NO_MEMORY;
5612         }
5613
5614         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5615
5616         if (ret != I40E_SUCCESS)
5617                 goto DONE;
5618
5619         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5620
5621         if (ret != I40E_SUCCESS)
5622                 goto DONE;
5623
5624         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5625         if (vsi->vlan_num == 1) {
5626                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5627                 if (ret != I40E_SUCCESS)
5628                         goto DONE;
5629
5630                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5631                 if (ret != I40E_SUCCESS)
5632                         goto DONE;
5633         }
5634
5635         i40e_set_vlan_filter(vsi, vlan, 0);
5636
5637         vsi->vlan_num--;
5638         ret = I40E_SUCCESS;
5639 DONE:
5640         rte_free(mv_f);
5641         return ret;
5642 }
5643
5644 int
5645 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5646 {
5647         struct i40e_mac_filter *f;
5648         struct i40e_macvlan_filter *mv_f;
5649         int i, vlan_num = 0;
5650         int ret = I40E_SUCCESS;
5651
5652         /* If it's add and we've config it, return */
5653         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5654         if (f != NULL)
5655                 return I40E_SUCCESS;
5656         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5657                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5658
5659                 /**
5660                  * If vlan_num is 0, that's the first time to add mac,
5661                  * set mask for vlan_id 0.
5662                  */
5663                 if (vsi->vlan_num == 0) {
5664                         i40e_set_vlan_filter(vsi, 0, 1);
5665                         vsi->vlan_num = 1;
5666                 }
5667                 vlan_num = vsi->vlan_num;
5668         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5669                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5670                 vlan_num = 1;
5671
5672         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5673         if (mv_f == NULL) {
5674                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5675                 return I40E_ERR_NO_MEMORY;
5676         }
5677
5678         for (i = 0; i < vlan_num; i++) {
5679                 mv_f[i].filter_type = mac_filter->filter_type;
5680                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5681                                 ETH_ADDR_LEN);
5682         }
5683
5684         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5685                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5686                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5687                                         &mac_filter->mac_addr);
5688                 if (ret != I40E_SUCCESS)
5689                         goto DONE;
5690         }
5691
5692         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5693         if (ret != I40E_SUCCESS)
5694                 goto DONE;
5695
5696         /* Add the mac addr into mac list */
5697         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5698         if (f == NULL) {
5699                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5700                 ret = I40E_ERR_NO_MEMORY;
5701                 goto DONE;
5702         }
5703         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5704                         ETH_ADDR_LEN);
5705         f->mac_info.filter_type = mac_filter->filter_type;
5706         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5707         vsi->mac_num++;
5708
5709         ret = I40E_SUCCESS;
5710 DONE:
5711         rte_free(mv_f);
5712
5713         return ret;
5714 }
5715
5716 int
5717 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5718 {
5719         struct i40e_mac_filter *f;
5720         struct i40e_macvlan_filter *mv_f;
5721         int i, vlan_num;
5722         enum rte_mac_filter_type filter_type;
5723         int ret = I40E_SUCCESS;
5724
5725         /* Can't find it, return an error */
5726         f = i40e_find_mac_filter(vsi, addr);
5727         if (f == NULL)
5728                 return I40E_ERR_PARAM;
5729
5730         vlan_num = vsi->vlan_num;
5731         filter_type = f->mac_info.filter_type;
5732         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5733                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5734                 if (vlan_num == 0) {
5735                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5736                         return I40E_ERR_PARAM;
5737                 }
5738         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5739                         filter_type == RTE_MAC_HASH_MATCH)
5740                 vlan_num = 1;
5741
5742         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5743         if (mv_f == NULL) {
5744                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5745                 return I40E_ERR_NO_MEMORY;
5746         }
5747
5748         for (i = 0; i < vlan_num; i++) {
5749                 mv_f[i].filter_type = filter_type;
5750                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5751                                 ETH_ADDR_LEN);
5752         }
5753         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5754                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5755                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5756                 if (ret != I40E_SUCCESS)
5757                         goto DONE;
5758         }
5759
5760         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5761         if (ret != I40E_SUCCESS)
5762                 goto DONE;
5763
5764         /* Remove the mac addr into mac list */
5765         TAILQ_REMOVE(&vsi->mac_list, f, next);
5766         rte_free(f);
5767         vsi->mac_num--;
5768
5769         ret = I40E_SUCCESS;
5770 DONE:
5771         rte_free(mv_f);
5772         return ret;
5773 }
5774
5775 /* Configure hash enable flags for RSS */
5776 uint64_t
5777 i40e_config_hena(uint64_t flags)
5778 {
5779         uint64_t hena = 0;
5780
5781         if (!flags)
5782                 return hena;
5783
5784         if (flags & ETH_RSS_FRAG_IPV4)
5785                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5786         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5787                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5788         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5789                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5790         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5791                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5792         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5793                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5794         if (flags & ETH_RSS_FRAG_IPV6)
5795                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5796         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5797                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5798         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5799                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5800         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5801                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5802         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5803                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5804         if (flags & ETH_RSS_L2_PAYLOAD)
5805                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5806
5807         return hena;
5808 }
5809
5810 /* Parse the hash enable flags */
5811 uint64_t
5812 i40e_parse_hena(uint64_t flags)
5813 {
5814         uint64_t rss_hf = 0;
5815
5816         if (!flags)
5817                 return rss_hf;
5818         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5819                 rss_hf |= ETH_RSS_FRAG_IPV4;
5820         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5821                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5822         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5823                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5824         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5825                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5826         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5827                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5828         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5829                 rss_hf |= ETH_RSS_FRAG_IPV6;
5830         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5831                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5832         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5833                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5834         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5835                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5836         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5837                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5838         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5839                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5840
5841         return rss_hf;
5842 }
5843
5844 /* Disable RSS */
5845 static void
5846 i40e_pf_disable_rss(struct i40e_pf *pf)
5847 {
5848         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5849         uint64_t hena;
5850
5851         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5852         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5853         hena &= ~I40E_RSS_HENA_ALL;
5854         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5855         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5856         I40E_WRITE_FLUSH(hw);
5857 }
5858
5859 static int
5860 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5861 {
5862         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5863         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5864         int ret = 0;
5865
5866         if (!key || key_len == 0) {
5867                 PMD_DRV_LOG(DEBUG, "No key to be configured");
5868                 return 0;
5869         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5870                 sizeof(uint32_t)) {
5871                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5872                 return -EINVAL;
5873         }
5874
5875         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5876                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5877                         (struct i40e_aqc_get_set_rss_key_data *)key;
5878
5879                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5880                 if (ret)
5881                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5882                                      "via AQ");
5883         } else {
5884                 uint32_t *hash_key = (uint32_t *)key;
5885                 uint16_t i;
5886
5887                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5888                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5889                 I40E_WRITE_FLUSH(hw);
5890         }
5891
5892         return ret;
5893 }
5894
5895 static int
5896 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5897 {
5898         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5899         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5900         int ret;
5901
5902         if (!key || !key_len)
5903                 return -EINVAL;
5904
5905         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5906                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5907                         (struct i40e_aqc_get_set_rss_key_data *)key);
5908                 if (ret) {
5909                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5910                         return ret;
5911                 }
5912         } else {
5913                 uint32_t *key_dw = (uint32_t *)key;
5914                 uint16_t i;
5915
5916                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5917                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5918         }
5919         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5920
5921         return 0;
5922 }
5923
5924 static int
5925 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5926 {
5927         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5928         uint64_t rss_hf;
5929         uint64_t hena;
5930         int ret;
5931
5932         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5933                                rss_conf->rss_key_len);
5934         if (ret)
5935                 return ret;
5936
5937         rss_hf = rss_conf->rss_hf;
5938         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5939         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5940         hena &= ~I40E_RSS_HENA_ALL;
5941         hena |= i40e_config_hena(rss_hf);
5942         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5943         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5944         I40E_WRITE_FLUSH(hw);
5945
5946         return 0;
5947 }
5948
5949 static int
5950 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5951                          struct rte_eth_rss_conf *rss_conf)
5952 {
5953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5954         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5955         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5956         uint64_t hena;
5957
5958         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5959         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5960         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5961                 if (rss_hf != 0) /* Enable RSS */
5962                         return -EINVAL;
5963                 return 0; /* Nothing to do */
5964         }
5965         /* RSS enabled */
5966         if (rss_hf == 0) /* Disable RSS */
5967                 return -EINVAL;
5968
5969         return i40e_hw_rss_hash_set(pf, rss_conf);
5970 }
5971
5972 static int
5973 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5974                            struct rte_eth_rss_conf *rss_conf)
5975 {
5976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5978         uint64_t hena;
5979
5980         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5981                          &rss_conf->rss_key_len);
5982
5983         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5984         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5985         rss_conf->rss_hf = i40e_parse_hena(hena);
5986
5987         return 0;
5988 }
5989
5990 static int
5991 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5992 {
5993         switch (filter_type) {
5994         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5995                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5996                 break;
5997         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5998                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5999                 break;
6000         case RTE_TUNNEL_FILTER_IMAC_TENID:
6001                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6002                 break;
6003         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6004                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6005                 break;
6006         case ETH_TUNNEL_FILTER_IMAC:
6007                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6008                 break;
6009         case ETH_TUNNEL_FILTER_OIP:
6010                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6011                 break;
6012         case ETH_TUNNEL_FILTER_IIP:
6013                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6014                 break;
6015         default:
6016                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6017                 return -EINVAL;
6018         }
6019
6020         return 0;
6021 }
6022
6023 static int
6024 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6025                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6026                         uint8_t add)
6027 {
6028         uint16_t ip_type;
6029         uint8_t i, tun_type = 0;
6030         /* internal varialbe to convert ipv6 byte order */
6031         uint32_t convert_ipv6[4];
6032         int val, ret = 0;
6033         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6034         struct i40e_vsi *vsi = pf->main_vsi;
6035         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6036         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6037
6038         cld_filter = rte_zmalloc("tunnel_filter",
6039                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6040                 0);
6041
6042         if (NULL == cld_filter) {
6043                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6044                 return -EINVAL;
6045         }
6046         pfilter = cld_filter;
6047
6048         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6049         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6050
6051         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6052         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6053                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6054                 rte_memcpy(&pfilter->ipaddr.v4.data,
6055                                 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
6056                                 sizeof(pfilter->ipaddr.v4.data));
6057         } else {
6058                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6059                 for (i = 0; i < 4; i++) {
6060                         convert_ipv6[i] =
6061                         rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
6062                 }
6063                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6064                                 sizeof(pfilter->ipaddr.v6.data));
6065         }
6066
6067         /* check tunneled type */
6068         switch (tunnel_filter->tunnel_type) {
6069         case RTE_TUNNEL_TYPE_VXLAN:
6070                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6071                 break;
6072         case RTE_TUNNEL_TYPE_NVGRE:
6073                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6074                 break;
6075         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6076                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6077                 break;
6078         default:
6079                 /* Other tunnel types is not supported. */
6080                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6081                 rte_free(cld_filter);
6082                 return -EINVAL;
6083         }
6084
6085         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6086                                                 &pfilter->flags);
6087         if (val < 0) {
6088                 rte_free(cld_filter);
6089                 return -EINVAL;
6090         }
6091
6092         pfilter->flags |= rte_cpu_to_le_16(
6093                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6094                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6095         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6096         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6097
6098         if (add)
6099                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6100         else
6101                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6102                                                 cld_filter, 1);
6103
6104         rte_free(cld_filter);
6105         return ret;
6106 }
6107
6108 static int
6109 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6110 {
6111         uint8_t i;
6112
6113         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6114                 if (pf->vxlan_ports[i] == port)
6115                         return i;
6116         }
6117
6118         return -1;
6119 }
6120
6121 static int
6122 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6123 {
6124         int  idx, ret;
6125         uint8_t filter_idx;
6126         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6127
6128         idx = i40e_get_vxlan_port_idx(pf, port);
6129
6130         /* Check if port already exists */
6131         if (idx >= 0) {
6132                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6133                 return -EINVAL;
6134         }
6135
6136         /* Now check if there is space to add the new port */
6137         idx = i40e_get_vxlan_port_idx(pf, 0);
6138         if (idx < 0) {
6139                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6140                         "not adding port %d", port);
6141                 return -ENOSPC;
6142         }
6143
6144         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6145                                         &filter_idx, NULL);
6146         if (ret < 0) {
6147                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6148                 return -1;
6149         }
6150
6151         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6152                          port,  filter_idx);
6153
6154         /* New port: add it and mark its index in the bitmap */
6155         pf->vxlan_ports[idx] = port;
6156         pf->vxlan_bitmap |= (1 << idx);
6157
6158         if (!(pf->flags & I40E_FLAG_VXLAN))
6159                 pf->flags |= I40E_FLAG_VXLAN;
6160
6161         return 0;
6162 }
6163
6164 static int
6165 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6166 {
6167         int idx;
6168         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6169
6170         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6171                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6172                 return -EINVAL;
6173         }
6174
6175         idx = i40e_get_vxlan_port_idx(pf, port);
6176
6177         if (idx < 0) {
6178                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6179                 return -EINVAL;
6180         }
6181
6182         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6183                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6184                 return -1;
6185         }
6186
6187         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6188                         port, idx);
6189
6190         pf->vxlan_ports[idx] = 0;
6191         pf->vxlan_bitmap &= ~(1 << idx);
6192
6193         if (!pf->vxlan_bitmap)
6194                 pf->flags &= ~I40E_FLAG_VXLAN;
6195
6196         return 0;
6197 }
6198
6199 /* Add UDP tunneling port */
6200 static int
6201 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6202                              struct rte_eth_udp_tunnel *udp_tunnel)
6203 {
6204         int ret = 0;
6205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6206
6207         if (udp_tunnel == NULL)
6208                 return -EINVAL;
6209
6210         switch (udp_tunnel->prot_type) {
6211         case RTE_TUNNEL_TYPE_VXLAN:
6212                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6213                 break;
6214
6215         case RTE_TUNNEL_TYPE_GENEVE:
6216         case RTE_TUNNEL_TYPE_TEREDO:
6217                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6218                 ret = -1;
6219                 break;
6220
6221         default:
6222                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6223                 ret = -1;
6224                 break;
6225         }
6226
6227         return ret;
6228 }
6229
6230 /* Remove UDP tunneling port */
6231 static int
6232 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6233                              struct rte_eth_udp_tunnel *udp_tunnel)
6234 {
6235         int ret = 0;
6236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6237
6238         if (udp_tunnel == NULL)
6239                 return -EINVAL;
6240
6241         switch (udp_tunnel->prot_type) {
6242         case RTE_TUNNEL_TYPE_VXLAN:
6243                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6244                 break;
6245         case RTE_TUNNEL_TYPE_GENEVE:
6246         case RTE_TUNNEL_TYPE_TEREDO:
6247                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6248                 ret = -1;
6249                 break;
6250         default:
6251                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6252                 ret = -1;
6253                 break;
6254         }
6255
6256         return ret;
6257 }
6258
6259 /* Calculate the maximum number of contiguous PF queues that are configured */
6260 static int
6261 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6262 {
6263         struct rte_eth_dev_data *data = pf->dev_data;
6264         int i, num;
6265         struct i40e_rx_queue *rxq;
6266
6267         num = 0;
6268         for (i = 0; i < pf->lan_nb_qps; i++) {
6269                 rxq = data->rx_queues[i];
6270                 if (rxq && rxq->q_set)
6271                         num++;
6272                 else
6273                         break;
6274         }
6275
6276         return num;
6277 }
6278
6279 /* Configure RSS */
6280 static int
6281 i40e_pf_config_rss(struct i40e_pf *pf)
6282 {
6283         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6284         struct rte_eth_rss_conf rss_conf;
6285         uint32_t i, lut = 0;
6286         uint16_t j, num;
6287
6288         /*
6289          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6290          * It's necessary to calulate the actual PF queues that are configured.
6291          */
6292         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6293                 num = i40e_pf_calc_configured_queues_num(pf);
6294         else
6295                 num = pf->dev_data->nb_rx_queues;
6296
6297         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6298         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6299                         num);
6300
6301         if (num == 0) {
6302                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6303                 return -ENOTSUP;
6304         }
6305
6306         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6307                 if (j == num)
6308                         j = 0;
6309                 lut = (lut << 8) | (j & ((0x1 <<
6310                         hw->func_caps.rss_table_entry_width) - 1));
6311                 if ((i & 3) == 3)
6312                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6313         }
6314
6315         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6316         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6317                 i40e_pf_disable_rss(pf);
6318                 return 0;
6319         }
6320         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6321                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6322                 /* Random default keys */
6323                 static uint32_t rss_key_default[] = {0x6b793944,
6324                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6325                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6326                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6327
6328                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6329                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6330                                                         sizeof(uint32_t);
6331         }
6332
6333         return i40e_hw_rss_hash_set(pf, &rss_conf);
6334 }
6335
6336 static int
6337 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6338                                struct rte_eth_tunnel_filter_conf *filter)
6339 {
6340         if (pf == NULL || filter == NULL) {
6341                 PMD_DRV_LOG(ERR, "Invalid parameter");
6342                 return -EINVAL;
6343         }
6344
6345         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6346                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6347                 return -EINVAL;
6348         }
6349
6350         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6351                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6352                 return -EINVAL;
6353         }
6354
6355         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6356                 (is_zero_ether_addr(&filter->outer_mac))) {
6357                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6358                 return -EINVAL;
6359         }
6360
6361         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6362                 (is_zero_ether_addr(&filter->inner_mac))) {
6363                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6364                 return -EINVAL;
6365         }
6366
6367         return 0;
6368 }
6369
6370 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6371 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6372 static int
6373 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6374 {
6375         uint32_t val, reg;
6376         int ret = -EINVAL;
6377
6378         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6379         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6380
6381         if (len == 3) {
6382                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6383         } else if (len == 4) {
6384                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6385         } else {
6386                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6387                 return ret;
6388         }
6389
6390         if (reg != val) {
6391                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6392                                                    reg, NULL);
6393                 if (ret != 0)
6394                         return ret;
6395         } else {
6396                 ret = 0;
6397         }
6398         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6399                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6400
6401         return ret;
6402 }
6403
6404 static int
6405 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6406 {
6407         int ret = -EINVAL;
6408
6409         if (!hw || !cfg)
6410                 return -EINVAL;
6411
6412         switch (cfg->cfg_type) {
6413         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6414                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6415                 break;
6416         default:
6417                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6418                 break;
6419         }
6420
6421         return ret;
6422 }
6423
6424 static int
6425 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6426                                enum rte_filter_op filter_op,
6427                                void *arg)
6428 {
6429         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430         int ret = I40E_ERR_PARAM;
6431
6432         switch (filter_op) {
6433         case RTE_ETH_FILTER_SET:
6434                 ret = i40e_dev_global_config_set(hw,
6435                         (struct rte_eth_global_cfg *)arg);
6436                 break;
6437         default:
6438                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6439                 break;
6440         }
6441
6442         return ret;
6443 }
6444
6445 static int
6446 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6447                           enum rte_filter_op filter_op,
6448                           void *arg)
6449 {
6450         struct rte_eth_tunnel_filter_conf *filter;
6451         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6452         int ret = I40E_SUCCESS;
6453
6454         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6455
6456         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6457                 return I40E_ERR_PARAM;
6458
6459         switch (filter_op) {
6460         case RTE_ETH_FILTER_NOP:
6461                 if (!(pf->flags & I40E_FLAG_VXLAN))
6462                         ret = I40E_NOT_SUPPORTED;
6463                 break;
6464         case RTE_ETH_FILTER_ADD:
6465                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6466                 break;
6467         case RTE_ETH_FILTER_DELETE:
6468                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6469                 break;
6470         default:
6471                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6472                 ret = I40E_ERR_PARAM;
6473                 break;
6474         }
6475
6476         return ret;
6477 }
6478
6479 static int
6480 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6481 {
6482         int ret = 0;
6483         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6484
6485         /* RSS setup */
6486         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6487                 ret = i40e_pf_config_rss(pf);
6488         else
6489                 i40e_pf_disable_rss(pf);
6490
6491         return ret;
6492 }
6493
6494 /* Get the symmetric hash enable configurations per port */
6495 static void
6496 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6497 {
6498         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6499
6500         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6501 }
6502
6503 /* Set the symmetric hash enable configurations per port */
6504 static void
6505 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6506 {
6507         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6508
6509         if (enable > 0) {
6510                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6511                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6512                                                         "been enabled");
6513                         return;
6514                 }
6515                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6516         } else {
6517                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6518                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6519                                                         "been disabled");
6520                         return;
6521                 }
6522                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6523         }
6524         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6525         I40E_WRITE_FLUSH(hw);
6526 }
6527
6528 /*
6529  * Get global configurations of hash function type and symmetric hash enable
6530  * per flow type (pctype). Note that global configuration means it affects all
6531  * the ports on the same NIC.
6532  */
6533 static int
6534 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6535                                    struct rte_eth_hash_global_conf *g_cfg)
6536 {
6537         uint32_t reg, mask = I40E_FLOW_TYPES;
6538         uint16_t i;
6539         enum i40e_filter_pctype pctype;
6540
6541         memset(g_cfg, 0, sizeof(*g_cfg));
6542         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6543         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6544                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6545         else
6546                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6547         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6548                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6549
6550         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6551                 if (!(mask & (1UL << i)))
6552                         continue;
6553                 mask &= ~(1UL << i);
6554                 /* Bit set indicats the coresponding flow type is supported */
6555                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6556                 pctype = i40e_flowtype_to_pctype(i);
6557                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6558                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6559                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6560         }
6561
6562         return 0;
6563 }
6564
6565 static int
6566 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6567 {
6568         uint32_t i;
6569         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6570
6571         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6572                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6573                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6574                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6575                                                 g_cfg->hash_func);
6576                 return -EINVAL;
6577         }
6578
6579         /*
6580          * As i40e supports less than 32 flow types, only first 32 bits need to
6581          * be checked.
6582          */
6583         mask0 = g_cfg->valid_bit_mask[0];
6584         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6585                 if (i == 0) {
6586                         /* Check if any unsupported flow type configured */
6587                         if ((mask0 | i40e_mask) ^ i40e_mask)
6588                                 goto mask_err;
6589                 } else {
6590                         if (g_cfg->valid_bit_mask[i])
6591                                 goto mask_err;
6592                 }
6593         }
6594
6595         return 0;
6596
6597 mask_err:
6598         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6599
6600         return -EINVAL;
6601 }
6602
6603 /*
6604  * Set global configurations of hash function type and symmetric hash enable
6605  * per flow type (pctype). Note any modifying global configuration will affect
6606  * all the ports on the same NIC.
6607  */
6608 static int
6609 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6610                                    struct rte_eth_hash_global_conf *g_cfg)
6611 {
6612         int ret;
6613         uint16_t i;
6614         uint32_t reg;
6615         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6616         enum i40e_filter_pctype pctype;
6617
6618         /* Check the input parameters */
6619         ret = i40e_hash_global_config_check(g_cfg);
6620         if (ret < 0)
6621                 return ret;
6622
6623         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6624                 if (!(mask0 & (1UL << i)))
6625                         continue;
6626                 mask0 &= ~(1UL << i);
6627                 pctype = i40e_flowtype_to_pctype(i);
6628                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6629                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6630                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6631         }
6632
6633         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6634         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6635                 /* Toeplitz */
6636                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6637                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6638                                                                 "Toeplitz");
6639                         goto out;
6640                 }
6641                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6642         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6643                 /* Simple XOR */
6644                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6645                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6646                                                         "Simple XOR");
6647                         goto out;
6648                 }
6649                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6650         } else
6651                 /* Use the default, and keep it as it is */
6652                 goto out;
6653
6654         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6655
6656 out:
6657         I40E_WRITE_FLUSH(hw);
6658
6659         return 0;
6660 }
6661
6662 /**
6663  * Valid input sets for hash and flow director filters per PCTYPE
6664  */
6665 static uint64_t
6666 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6667                 enum rte_filter_type filter)
6668 {
6669         uint64_t valid;
6670
6671         static const uint64_t valid_hash_inset_table[] = {
6672                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6673                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6674                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6675                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6676                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6677                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6678                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6679                         I40E_INSET_FLEX_PAYLOAD,
6680                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6681                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6682                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6683                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6684                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6685                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6686                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6687                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6688                         I40E_INSET_FLEX_PAYLOAD,
6689                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6690                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6691                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6692                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6693                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6694                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6695                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6696                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6697                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6698                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6699                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6700                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6701                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6702                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6703                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6704                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6705                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6706                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6707                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6708                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6709                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6710                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6711                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6712                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6713                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6714                         I40E_INSET_FLEX_PAYLOAD,
6715                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6716                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6717                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6718                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6719                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6720                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6721                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6722                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6723                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6724                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6725                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6726                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6727                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6728                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6729                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6730                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6731                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6732                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6733                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6734                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6735                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6736                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6737                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6738                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6739                         I40E_INSET_FLEX_PAYLOAD,
6740                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6741                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6742                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6743                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6744                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6745                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6746                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6747                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6748                         I40E_INSET_FLEX_PAYLOAD,
6749                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6750                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6751                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6752                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6753                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6754                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6755                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6756                         I40E_INSET_FLEX_PAYLOAD,
6757                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6758                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6759                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6760                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6761                         I40E_INSET_FLEX_PAYLOAD,
6762         };
6763
6764         /**
6765          * Flow director supports only fields defined in
6766          * union rte_eth_fdir_flow.
6767          */
6768         static const uint64_t valid_fdir_inset_table[] = {
6769                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6770                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6771                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6772                 I40E_INSET_IPV4_TTL,
6773                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6774                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6775                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6776                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6777                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6778                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6779                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6780                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6781                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6782                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6783                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6784                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6785                 I40E_INSET_SCTP_VT,
6786                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6787                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6788                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6789                 I40E_INSET_IPV4_TTL,
6790                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6791                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6792                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6793                 I40E_INSET_IPV6_HOP_LIMIT,
6794                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6795                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6796                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6797                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6798                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6799                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6800                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6801                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6802                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6803                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6804                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6805                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6806                 I40E_INSET_SCTP_VT,
6807                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6808                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6809                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6810                 I40E_INSET_IPV6_HOP_LIMIT,
6811                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6812                 I40E_INSET_LAST_ETHER_TYPE,
6813         };
6814
6815         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6816                 return 0;
6817         if (filter == RTE_ETH_FILTER_HASH)
6818                 valid = valid_hash_inset_table[pctype];
6819         else
6820                 valid = valid_fdir_inset_table[pctype];
6821
6822         return valid;
6823 }
6824
6825 /**
6826  * Validate if the input set is allowed for a specific PCTYPE
6827  */
6828 static int
6829 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6830                 enum rte_filter_type filter, uint64_t inset)
6831 {
6832         uint64_t valid;
6833
6834         valid = i40e_get_valid_input_set(pctype, filter);
6835         if (inset & (~valid))
6836                 return -EINVAL;
6837
6838         return 0;
6839 }
6840
6841 /* default input set fields combination per pctype */
6842 static uint64_t
6843 i40e_get_default_input_set(uint16_t pctype)
6844 {
6845         static const uint64_t default_inset_table[] = {
6846                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6847                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6848                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6849                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6850                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6851                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6852                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6853                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6854                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6855                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6856                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6857                         I40E_INSET_SCTP_VT,
6858                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6859                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6860                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6861                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6862                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6863                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6864                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6865                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6866                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6867                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6868                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6869                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6870                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6871                         I40E_INSET_SCTP_VT,
6872                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6873                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6874                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6875                         I40E_INSET_LAST_ETHER_TYPE,
6876         };
6877
6878         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6879                 return 0;
6880
6881         return default_inset_table[pctype];
6882 }
6883
6884 /**
6885  * Parse the input set from index to logical bit masks
6886  */
6887 static int
6888 i40e_parse_input_set(uint64_t *inset,
6889                      enum i40e_filter_pctype pctype,
6890                      enum rte_eth_input_set_field *field,
6891                      uint16_t size)
6892 {
6893         uint16_t i, j;
6894         int ret = -EINVAL;
6895
6896         static const struct {
6897                 enum rte_eth_input_set_field field;
6898                 uint64_t inset;
6899         } inset_convert_table[] = {
6900                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6901                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6902                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6903                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6904                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6905                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6906                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6907                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6908                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6909                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6910                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
6911                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6912                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6913                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6914                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6915                         I40E_INSET_IPV6_NEXT_HDR},
6916                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
6917                         I40E_INSET_IPV6_HOP_LIMIT},
6918                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6919                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6920                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6921                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6922                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6923                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6924                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6925                         I40E_INSET_SCTP_VT},
6926                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6927                         I40E_INSET_TUNNEL_DMAC},
6928                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6929                         I40E_INSET_VLAN_TUNNEL},
6930                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6931                         I40E_INSET_TUNNEL_ID},
6932                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6933                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6934                         I40E_INSET_FLEX_PAYLOAD_W1},
6935                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6936                         I40E_INSET_FLEX_PAYLOAD_W2},
6937                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6938                         I40E_INSET_FLEX_PAYLOAD_W3},
6939                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6940                         I40E_INSET_FLEX_PAYLOAD_W4},
6941                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6942                         I40E_INSET_FLEX_PAYLOAD_W5},
6943                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6944                         I40E_INSET_FLEX_PAYLOAD_W6},
6945                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6946                         I40E_INSET_FLEX_PAYLOAD_W7},
6947                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6948                         I40E_INSET_FLEX_PAYLOAD_W8},
6949         };
6950
6951         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6952                 return ret;
6953
6954         /* Only one item allowed for default or all */
6955         if (size == 1) {
6956                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6957                         *inset = i40e_get_default_input_set(pctype);
6958                         return 0;
6959                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6960                         *inset = I40E_INSET_NONE;
6961                         return 0;
6962                 }
6963         }
6964
6965         for (i = 0, *inset = 0; i < size; i++) {
6966                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6967                         if (field[i] == inset_convert_table[j].field) {
6968                                 *inset |= inset_convert_table[j].inset;
6969                                 break;
6970                         }
6971                 }
6972
6973                 /* It contains unsupported input set, return immediately */
6974                 if (j == RTE_DIM(inset_convert_table))
6975                         return ret;
6976         }
6977
6978         return 0;
6979 }
6980
6981 /**
6982  * Translate the input set from bit masks to register aware bit masks
6983  * and vice versa
6984  */
6985 static uint64_t
6986 i40e_translate_input_set_reg(uint64_t input)
6987 {
6988         uint64_t val = 0;
6989         uint16_t i;
6990
6991         static const struct {
6992                 uint64_t inset;
6993                 uint64_t inset_reg;
6994         } inset_map[] = {
6995                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6996                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6997                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6998                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6999                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7000                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7001                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7002                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7003                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7004                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7005                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7006                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7007                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7008                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7009                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7010                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7011                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7012                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7013                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7014                 {I40E_INSET_TUNNEL_DMAC,
7015                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7016                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7017                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7018                 {I40E_INSET_TUNNEL_SRC_PORT,
7019                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7020                 {I40E_INSET_TUNNEL_DST_PORT,
7021                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7022                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7023                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7024                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7025                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7026                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7027                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7028                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7029                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7030                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7031         };
7032
7033         if (input == 0)
7034                 return val;
7035
7036         /* Translate input set to register aware inset */
7037         for (i = 0; i < RTE_DIM(inset_map); i++) {
7038                 if (input & inset_map[i].inset)
7039                         val |= inset_map[i].inset_reg;
7040         }
7041
7042         return val;
7043 }
7044
7045 static int
7046 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7047 {
7048         uint8_t i, idx = 0;
7049         uint64_t inset_need_mask = inset;
7050
7051         static const struct {
7052                 uint64_t inset;
7053                 uint32_t mask;
7054         } inset_mask_map[] = {
7055                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7056                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7057                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7058                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7059                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7060                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7061                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7062                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7063         };
7064
7065         if (!inset || !mask || !nb_elem)
7066                 return 0;
7067
7068         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7069                 /* Clear the inset bit, if no MASK is required,
7070                  * for example proto + ttl
7071                  */
7072                 if ((inset & inset_mask_map[i].inset) ==
7073                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7074                         inset_need_mask &= ~inset_mask_map[i].inset;
7075                 if (!inset_need_mask)
7076                         return 0;
7077         }
7078         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7079                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7080                     inset_mask_map[i].inset) {
7081                         if (idx >= nb_elem) {
7082                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7083                                 return -EINVAL;
7084                         }
7085                         mask[idx] = inset_mask_map[i].mask;
7086                         idx++;
7087                 }
7088         }
7089
7090         return idx;
7091 }
7092
7093 static void
7094 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7095 {
7096         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7097
7098         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7099         if (reg != val)
7100                 i40e_write_rx_ctl(hw, addr, val);
7101         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7102                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7103 }
7104
7105 static void
7106 i40e_filter_input_set_init(struct i40e_pf *pf)
7107 {
7108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7109         enum i40e_filter_pctype pctype;
7110         uint64_t input_set, inset_reg;
7111         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7112         int num, i;
7113
7114         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7115              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7116                 if (!I40E_VALID_PCTYPE(pctype))
7117                         continue;
7118                 input_set = i40e_get_default_input_set(pctype);
7119
7120                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7121                                                    I40E_INSET_MASK_NUM_REG);
7122                 if (num < 0)
7123                         return;
7124                 inset_reg = i40e_translate_input_set_reg(input_set);
7125
7126                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7127                                       (uint32_t)(inset_reg & UINT32_MAX));
7128                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7129                                      (uint32_t)((inset_reg >>
7130                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7131                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7132                                       (uint32_t)(inset_reg & UINT32_MAX));
7133                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7134                                      (uint32_t)((inset_reg >>
7135                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7136
7137                 for (i = 0; i < num; i++) {
7138                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7139                                              mask_reg[i]);
7140                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7141                                              mask_reg[i]);
7142                 }
7143                 /*clear unused mask registers of the pctype */
7144                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7145                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7146                                              0);
7147                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7148                                              0);
7149                 }
7150                 I40E_WRITE_FLUSH(hw);
7151
7152                 /* store the default input set */
7153                 pf->hash_input_set[pctype] = input_set;
7154                 pf->fdir.input_set[pctype] = input_set;
7155         }
7156 }
7157
7158 int
7159 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7160                          struct rte_eth_input_set_conf *conf)
7161 {
7162         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7163         enum i40e_filter_pctype pctype;
7164         uint64_t input_set, inset_reg = 0;
7165         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7166         int ret, i, num;
7167
7168         if (!conf) {
7169                 PMD_DRV_LOG(ERR, "Invalid pointer");
7170                 return -EFAULT;
7171         }
7172         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7173             conf->op != RTE_ETH_INPUT_SET_ADD) {
7174                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7175                 return -EINVAL;
7176         }
7177
7178         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7179         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7180                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7181                             conf->flow_type);
7182                 return -EINVAL;
7183         }
7184
7185         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7186                                    conf->inset_size);
7187         if (ret) {
7188                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7189                 return -EINVAL;
7190         }
7191         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7192                                     input_set) != 0) {
7193                 PMD_DRV_LOG(ERR, "Invalid input set");
7194                 return -EINVAL;
7195         }
7196         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7197                 /* get inset value in register */
7198                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7199                 inset_reg <<= I40E_32_BIT_WIDTH;
7200                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7201                 input_set |= pf->hash_input_set[pctype];
7202         }
7203         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7204                                            I40E_INSET_MASK_NUM_REG);
7205         if (num < 0)
7206                 return -EINVAL;
7207
7208         inset_reg |= i40e_translate_input_set_reg(input_set);
7209
7210         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7211                               (uint32_t)(inset_reg & UINT32_MAX));
7212         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7213                              (uint32_t)((inset_reg >>
7214                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7215
7216         for (i = 0; i < num; i++)
7217                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7218                                      mask_reg[i]);
7219         /*clear unused mask registers of the pctype */
7220         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7221                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7222                                      0);
7223         I40E_WRITE_FLUSH(hw);
7224
7225         pf->hash_input_set[pctype] = input_set;
7226         return 0;
7227 }
7228
7229 int
7230 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7231                          struct rte_eth_input_set_conf *conf)
7232 {
7233         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7234         enum i40e_filter_pctype pctype;
7235         uint64_t input_set, inset_reg = 0;
7236         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7237         int ret, i, num;
7238
7239         if (!hw || !conf) {
7240                 PMD_DRV_LOG(ERR, "Invalid pointer");
7241                 return -EFAULT;
7242         }
7243         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7244             conf->op != RTE_ETH_INPUT_SET_ADD) {
7245                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7246                 return -EINVAL;
7247         }
7248
7249         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7250         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7251                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7252                             conf->flow_type);
7253                 return -EINVAL;
7254         }
7255         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7256                                    conf->inset_size);
7257         if (ret) {
7258                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7259                 return -EINVAL;
7260         }
7261         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7262                                     input_set) != 0) {
7263                 PMD_DRV_LOG(ERR, "Invalid input set");
7264                 return -EINVAL;
7265         }
7266
7267         /* get inset value in register */
7268         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7269         inset_reg <<= I40E_32_BIT_WIDTH;
7270         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7271
7272         /* Can not change the inset reg for flex payload for fdir,
7273          * it is done by writing I40E_PRTQF_FD_FLXINSET
7274          * in i40e_set_flex_mask_on_pctype.
7275          */
7276         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7277                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7278         else
7279                 input_set |= pf->fdir.input_set[pctype];
7280         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7281                                            I40E_INSET_MASK_NUM_REG);
7282         if (num < 0)
7283                 return -EINVAL;
7284
7285         inset_reg |= i40e_translate_input_set_reg(input_set);
7286
7287         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7288                               (uint32_t)(inset_reg & UINT32_MAX));
7289         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7290                              (uint32_t)((inset_reg >>
7291                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7292
7293         for (i = 0; i < num; i++)
7294                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7295                                      mask_reg[i]);
7296         /*clear unused mask registers of the pctype */
7297         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7298                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7299                                      0);
7300         I40E_WRITE_FLUSH(hw);
7301
7302         pf->fdir.input_set[pctype] = input_set;
7303         return 0;
7304 }
7305
7306 static int
7307 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7308 {
7309         int ret = 0;
7310
7311         if (!hw || !info) {
7312                 PMD_DRV_LOG(ERR, "Invalid pointer");
7313                 return -EFAULT;
7314         }
7315
7316         switch (info->info_type) {
7317         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7318                 i40e_get_symmetric_hash_enable_per_port(hw,
7319                                         &(info->info.enable));
7320                 break;
7321         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7322                 ret = i40e_get_hash_filter_global_config(hw,
7323                                 &(info->info.global_conf));
7324                 break;
7325         default:
7326                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7327                                                         info->info_type);
7328                 ret = -EINVAL;
7329                 break;
7330         }
7331
7332         return ret;
7333 }
7334
7335 static int
7336 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7337 {
7338         int ret = 0;
7339
7340         if (!hw || !info) {
7341                 PMD_DRV_LOG(ERR, "Invalid pointer");
7342                 return -EFAULT;
7343         }
7344
7345         switch (info->info_type) {
7346         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7347                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7348                 break;
7349         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7350                 ret = i40e_set_hash_filter_global_config(hw,
7351                                 &(info->info.global_conf));
7352                 break;
7353         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7354                 ret = i40e_hash_filter_inset_select(hw,
7355                                                &(info->info.input_set_conf));
7356                 break;
7357
7358         default:
7359                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7360                                                         info->info_type);
7361                 ret = -EINVAL;
7362                 break;
7363         }
7364
7365         return ret;
7366 }
7367
7368 /* Operations for hash function */
7369 static int
7370 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7371                       enum rte_filter_op filter_op,
7372                       void *arg)
7373 {
7374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7375         int ret = 0;
7376
7377         switch (filter_op) {
7378         case RTE_ETH_FILTER_NOP:
7379                 break;
7380         case RTE_ETH_FILTER_GET:
7381                 ret = i40e_hash_filter_get(hw,
7382                         (struct rte_eth_hash_filter_info *)arg);
7383                 break;
7384         case RTE_ETH_FILTER_SET:
7385                 ret = i40e_hash_filter_set(hw,
7386                         (struct rte_eth_hash_filter_info *)arg);
7387                 break;
7388         default:
7389                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7390                                                                 filter_op);
7391                 ret = -ENOTSUP;
7392                 break;
7393         }
7394
7395         return ret;
7396 }
7397
7398 /*
7399  * Configure ethertype filter, which can director packet by filtering
7400  * with mac address and ether_type or only ether_type
7401  */
7402 static int
7403 i40e_ethertype_filter_set(struct i40e_pf *pf,
7404                         struct rte_eth_ethertype_filter *filter,
7405                         bool add)
7406 {
7407         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7408         struct i40e_control_filter_stats stats;
7409         uint16_t flags = 0;
7410         int ret;
7411
7412         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7413                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7414                 return -EINVAL;
7415         }
7416         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7417                 filter->ether_type == ETHER_TYPE_IPv6) {
7418                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7419                         " control packet filter.", filter->ether_type);
7420                 return -EINVAL;
7421         }
7422         if (filter->ether_type == ETHER_TYPE_VLAN)
7423                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7424                         " not supported.");
7425
7426         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7427                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7428         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7429                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7430         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7431
7432         memset(&stats, 0, sizeof(stats));
7433         ret = i40e_aq_add_rem_control_packet_filter(hw,
7434                         filter->mac_addr.addr_bytes,
7435                         filter->ether_type, flags,
7436                         pf->main_vsi->seid,
7437                         filter->queue, add, &stats, NULL);
7438
7439         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7440                          " mac_etype_used = %u, etype_used = %u,"
7441                          " mac_etype_free = %u, etype_free = %u\n",
7442                          ret, stats.mac_etype_used, stats.etype_used,
7443                          stats.mac_etype_free, stats.etype_free);
7444         if (ret < 0)
7445                 return -ENOSYS;
7446         return 0;
7447 }
7448
7449 /*
7450  * Handle operations for ethertype filter.
7451  */
7452 static int
7453 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7454                                 enum rte_filter_op filter_op,
7455                                 void *arg)
7456 {
7457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7458         int ret = 0;
7459
7460         if (filter_op == RTE_ETH_FILTER_NOP)
7461                 return ret;
7462
7463         if (arg == NULL) {
7464                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7465                             filter_op);
7466                 return -EINVAL;
7467         }
7468
7469         switch (filter_op) {
7470         case RTE_ETH_FILTER_ADD:
7471                 ret = i40e_ethertype_filter_set(pf,
7472                         (struct rte_eth_ethertype_filter *)arg,
7473                         TRUE);
7474                 break;
7475         case RTE_ETH_FILTER_DELETE:
7476                 ret = i40e_ethertype_filter_set(pf,
7477                         (struct rte_eth_ethertype_filter *)arg,
7478                         FALSE);
7479                 break;
7480         default:
7481                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7482                 ret = -ENOSYS;
7483                 break;
7484         }
7485         return ret;
7486 }
7487
7488 static int
7489 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7490                      enum rte_filter_type filter_type,
7491                      enum rte_filter_op filter_op,
7492                      void *arg)
7493 {
7494         int ret = 0;
7495
7496         if (dev == NULL)
7497                 return -EINVAL;
7498
7499         switch (filter_type) {
7500         case RTE_ETH_FILTER_NONE:
7501                 /* For global configuration */
7502                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7503                 break;
7504         case RTE_ETH_FILTER_HASH:
7505                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7506                 break;
7507         case RTE_ETH_FILTER_MACVLAN:
7508                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7509                 break;
7510         case RTE_ETH_FILTER_ETHERTYPE:
7511                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7512                 break;
7513         case RTE_ETH_FILTER_TUNNEL:
7514                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7515                 break;
7516         case RTE_ETH_FILTER_FDIR:
7517                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7518                 break;
7519         default:
7520                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7521                                                         filter_type);
7522                 ret = -EINVAL;
7523                 break;
7524         }
7525
7526         return ret;
7527 }
7528
7529 /*
7530  * Check and enable Extended Tag.
7531  * Enabling Extended Tag is important for 40G performance.
7532  */
7533 static void
7534 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7535 {
7536         uint32_t buf = 0;
7537         int ret;
7538
7539         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7540                                       PCI_DEV_CAP_REG);
7541         if (ret < 0) {
7542                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7543                             PCI_DEV_CAP_REG);
7544                 return;
7545         }
7546         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7547                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7548                 return;
7549         }
7550
7551         buf = 0;
7552         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7553                                       PCI_DEV_CTRL_REG);
7554         if (ret < 0) {
7555                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7556                             PCI_DEV_CTRL_REG);
7557                 return;
7558         }
7559         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7560                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7561                 return;
7562         }
7563         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7564         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7565                                        PCI_DEV_CTRL_REG);
7566         if (ret < 0) {
7567                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7568                             PCI_DEV_CTRL_REG);
7569                 return;
7570         }
7571 }
7572
7573 /*
7574  * As some registers wouldn't be reset unless a global hardware reset,
7575  * hardware initialization is needed to put those registers into an
7576  * expected initial state.
7577  */
7578 static void
7579 i40e_hw_init(struct rte_eth_dev *dev)
7580 {
7581         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7582
7583         i40e_enable_extended_tag(dev);
7584
7585         /* clear the PF Queue Filter control register */
7586         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7587
7588         /* Disable symmetric hash per port */
7589         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7590 }
7591
7592 enum i40e_filter_pctype
7593 i40e_flowtype_to_pctype(uint16_t flow_type)
7594 {
7595         static const enum i40e_filter_pctype pctype_table[] = {
7596                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7597                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7598                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7599                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7600                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7601                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7602                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7603                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7604                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7605                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7606                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7607                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7608                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7609                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7610                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7611                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7612                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7613                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7614                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7615         };
7616
7617         return pctype_table[flow_type];
7618 }
7619
7620 uint16_t
7621 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7622 {
7623         static const uint16_t flowtype_table[] = {
7624                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7625                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7626                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7627                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7628                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7629                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7630                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7631                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7632                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7633                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7634                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7635                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7636                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7637                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7638                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7639                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7640                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7641                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7642                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7643         };
7644
7645         return flowtype_table[pctype];
7646 }
7647
7648 /*
7649  * On X710, performance number is far from the expectation on recent firmware
7650  * versions; on XL710, performance number is also far from the expectation on
7651  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7652  * mode is enabled and port MAC address is equal to the packet destination MAC
7653  * address. The fix for this issue may not be integrated in the following
7654  * firmware version. So the workaround in software driver is needed. It needs
7655  * to modify the initial values of 3 internal only registers for both X710 and
7656  * XL710. Note that the values for X710 or XL710 could be different, and the
7657  * workaround can be removed when it is fixed in firmware in the future.
7658  */
7659
7660 /* For both X710 and XL710 */
7661 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7662 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7663
7664 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7665 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7666
7667 /* For X710 */
7668 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7669 /* For XL710 */
7670 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7671 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7672
7673 static void
7674 i40e_configure_registers(struct i40e_hw *hw)
7675 {
7676         static struct {
7677                 uint32_t addr;
7678                 uint64_t val;
7679         } reg_table[] = {
7680                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7681                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7682                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7683         };
7684         uint64_t reg;
7685         uint32_t i;
7686         int ret;
7687
7688         for (i = 0; i < RTE_DIM(reg_table); i++) {
7689                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7690                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7691                                 reg_table[i].val =
7692                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7693                         else /* For X710 */
7694                                 reg_table[i].val =
7695                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7696                 }
7697
7698                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7699                                                         &reg, NULL);
7700                 if (ret < 0) {
7701                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7702                                                         reg_table[i].addr);
7703                         break;
7704                 }
7705                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7706                                                 reg_table[i].addr, reg);
7707                 if (reg == reg_table[i].val)
7708                         continue;
7709
7710                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7711                                                 reg_table[i].val, NULL);
7712                 if (ret < 0) {
7713                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7714                                 "address of 0x%"PRIx32, reg_table[i].val,
7715                                                         reg_table[i].addr);
7716                         break;
7717                 }
7718                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7719                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7720         }
7721 }
7722
7723 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7724 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7725 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7726 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7727 static int
7728 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7729 {
7730         uint32_t reg;
7731         int ret;
7732
7733         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7734                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7735                 return -EINVAL;
7736         }
7737
7738         /* Configure for double VLAN RX stripping */
7739         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7740         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7741                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7742                 ret = i40e_aq_debug_write_register(hw,
7743                                                    I40E_VSI_TSR(vsi->vsi_id),
7744                                                    reg, NULL);
7745                 if (ret < 0) {
7746                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7747                                     vsi->vsi_id);
7748                         return I40E_ERR_CONFIG;
7749                 }
7750         }
7751
7752         /* Configure for double VLAN TX insertion */
7753         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7754         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7755                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7756                 ret = i40e_aq_debug_write_register(hw,
7757                                                    I40E_VSI_L2TAGSTXVALID(
7758                                                    vsi->vsi_id), reg, NULL);
7759                 if (ret < 0) {
7760                         PMD_DRV_LOG(ERR, "Failed to update "
7761                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7762                         return I40E_ERR_CONFIG;
7763                 }
7764         }
7765
7766         return 0;
7767 }
7768
7769 /**
7770  * i40e_aq_add_mirror_rule
7771  * @hw: pointer to the hardware structure
7772  * @seid: VEB seid to add mirror rule to
7773  * @dst_id: destination vsi seid
7774  * @entries: Buffer which contains the entities to be mirrored
7775  * @count: number of entities contained in the buffer
7776  * @rule_id:the rule_id of the rule to be added
7777  *
7778  * Add a mirror rule for a given veb.
7779  *
7780  **/
7781 static enum i40e_status_code
7782 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7783                         uint16_t seid, uint16_t dst_id,
7784                         uint16_t rule_type, uint16_t *entries,
7785                         uint16_t count, uint16_t *rule_id)
7786 {
7787         struct i40e_aq_desc desc;
7788         struct i40e_aqc_add_delete_mirror_rule cmd;
7789         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7790                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7791                 &desc.params.raw;
7792         uint16_t buff_len;
7793         enum i40e_status_code status;
7794
7795         i40e_fill_default_direct_cmd_desc(&desc,
7796                                           i40e_aqc_opc_add_mirror_rule);
7797         memset(&cmd, 0, sizeof(cmd));
7798
7799         buff_len = sizeof(uint16_t) * count;
7800         desc.datalen = rte_cpu_to_le_16(buff_len);
7801         if (buff_len > 0)
7802                 desc.flags |= rte_cpu_to_le_16(
7803                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7804         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7805                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7806         cmd.num_entries = rte_cpu_to_le_16(count);
7807         cmd.seid = rte_cpu_to_le_16(seid);
7808         cmd.destination = rte_cpu_to_le_16(dst_id);
7809
7810         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7811         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7812         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7813                          "rule_id = %u"
7814                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7815                          hw->aq.asq_last_status, resp->rule_id,
7816                          resp->mirror_rules_used, resp->mirror_rules_free);
7817         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7818
7819         return status;
7820 }
7821
7822 /**
7823  * i40e_aq_del_mirror_rule
7824  * @hw: pointer to the hardware structure
7825  * @seid: VEB seid to add mirror rule to
7826  * @entries: Buffer which contains the entities to be mirrored
7827  * @count: number of entities contained in the buffer
7828  * @rule_id:the rule_id of the rule to be delete
7829  *
7830  * Delete a mirror rule for a given veb.
7831  *
7832  **/
7833 static enum i40e_status_code
7834 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7835                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7836                 uint16_t count, uint16_t rule_id)
7837 {
7838         struct i40e_aq_desc desc;
7839         struct i40e_aqc_add_delete_mirror_rule cmd;
7840         uint16_t buff_len = 0;
7841         enum i40e_status_code status;
7842         void *buff = NULL;
7843
7844         i40e_fill_default_direct_cmd_desc(&desc,
7845                                           i40e_aqc_opc_delete_mirror_rule);
7846         memset(&cmd, 0, sizeof(cmd));
7847         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7848                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7849                                                           I40E_AQ_FLAG_RD));
7850                 cmd.num_entries = count;
7851                 buff_len = sizeof(uint16_t) * count;
7852                 desc.datalen = rte_cpu_to_le_16(buff_len);
7853                 buff = (void *)entries;
7854         } else
7855                 /* rule id is filled in destination field for deleting mirror rule */
7856                 cmd.destination = rte_cpu_to_le_16(rule_id);
7857
7858         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7859                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7860         cmd.seid = rte_cpu_to_le_16(seid);
7861
7862         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7863         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7864
7865         return status;
7866 }
7867
7868 /**
7869  * i40e_mirror_rule_set
7870  * @dev: pointer to the hardware structure
7871  * @mirror_conf: mirror rule info
7872  * @sw_id: mirror rule's sw_id
7873  * @on: enable/disable
7874  *
7875  * set a mirror rule.
7876  *
7877  **/
7878 static int
7879 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7880                         struct rte_eth_mirror_conf *mirror_conf,
7881                         uint8_t sw_id, uint8_t on)
7882 {
7883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7885         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7886         struct i40e_mirror_rule *parent = NULL;
7887         uint16_t seid, dst_seid, rule_id;
7888         uint16_t i, j = 0;
7889         int ret;
7890
7891         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7892
7893         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7894                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7895                         " without veb or vfs.");
7896                 return -ENOSYS;
7897         }
7898         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7899                 PMD_DRV_LOG(ERR, "mirror table is full.");
7900                 return -ENOSPC;
7901         }
7902         if (mirror_conf->dst_pool > pf->vf_num) {
7903                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7904                                  mirror_conf->dst_pool);
7905                 return -EINVAL;
7906         }
7907
7908         seid = pf->main_vsi->veb->seid;
7909
7910         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7911                 if (sw_id <= it->index) {
7912                         mirr_rule = it;
7913                         break;
7914                 }
7915                 parent = it;
7916         }
7917         if (mirr_rule && sw_id == mirr_rule->index) {
7918                 if (on) {
7919                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7920                         return -EEXIST;
7921                 } else {
7922                         ret = i40e_aq_del_mirror_rule(hw, seid,
7923                                         mirr_rule->rule_type,
7924                                         mirr_rule->entries,
7925                                         mirr_rule->num_entries, mirr_rule->id);
7926                         if (ret < 0) {
7927                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7928                                                    " ret = %d, aq_err = %d.",
7929                                                    ret, hw->aq.asq_last_status);
7930                                 return -ENOSYS;
7931                         }
7932                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7933                         rte_free(mirr_rule);
7934                         pf->nb_mirror_rule--;
7935                         return 0;
7936                 }
7937         } else if (!on) {
7938                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7939                 return -ENOENT;
7940         }
7941
7942         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7943                                 sizeof(struct i40e_mirror_rule) , 0);
7944         if (!mirr_rule) {
7945                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7946                 return I40E_ERR_NO_MEMORY;
7947         }
7948         switch (mirror_conf->rule_type) {
7949         case ETH_MIRROR_VLAN:
7950                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7951                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7952                                 mirr_rule->entries[j] =
7953                                         mirror_conf->vlan.vlan_id[i];
7954                                 j++;
7955                         }
7956                 }
7957                 if (j == 0) {
7958                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7959                         rte_free(mirr_rule);
7960                         return -EINVAL;
7961                 }
7962                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7963                 break;
7964         case ETH_MIRROR_VIRTUAL_POOL_UP:
7965         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7966                 /* check if the specified pool bit is out of range */
7967                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7968                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7969                         rte_free(mirr_rule);
7970                         return -EINVAL;
7971                 }
7972                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7973                         if (mirror_conf->pool_mask & (1ULL << i)) {
7974                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7975                                 j++;
7976                         }
7977                 }
7978                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7979                         /* add pf vsi to entries */
7980                         mirr_rule->entries[j] = pf->main_vsi_seid;
7981                         j++;
7982                 }
7983                 if (j == 0) {
7984                         PMD_DRV_LOG(ERR, "pool is not specified.");
7985                         rte_free(mirr_rule);
7986                         return -EINVAL;
7987                 }
7988                 /* egress and ingress in aq commands means from switch but not port */
7989                 mirr_rule->rule_type =
7990                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7991                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7992                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7993                 break;
7994         case ETH_MIRROR_UPLINK_PORT:
7995                 /* egress and ingress in aq commands means from switch but not port*/
7996                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7997                 break;
7998         case ETH_MIRROR_DOWNLINK_PORT:
7999                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8000                 break;
8001         default:
8002                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8003                         mirror_conf->rule_type);
8004                 rte_free(mirr_rule);
8005                 return -EINVAL;
8006         }
8007
8008         /* If the dst_pool is equal to vf_num, consider it as PF */
8009         if (mirror_conf->dst_pool == pf->vf_num)
8010                 dst_seid = pf->main_vsi_seid;
8011         else
8012                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8013
8014         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8015                                       mirr_rule->rule_type, mirr_rule->entries,
8016                                       j, &rule_id);
8017         if (ret < 0) {
8018                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8019                                    " ret = %d, aq_err = %d.",
8020                                    ret, hw->aq.asq_last_status);
8021                 rte_free(mirr_rule);
8022                 return -ENOSYS;
8023         }
8024
8025         mirr_rule->index = sw_id;
8026         mirr_rule->num_entries = j;
8027         mirr_rule->id = rule_id;
8028         mirr_rule->dst_vsi_seid = dst_seid;
8029
8030         if (parent)
8031                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8032         else
8033                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8034
8035         pf->nb_mirror_rule++;
8036         return 0;
8037 }
8038
8039 /**
8040  * i40e_mirror_rule_reset
8041  * @dev: pointer to the device
8042  * @sw_id: mirror rule's sw_id
8043  *
8044  * reset a mirror rule.
8045  *
8046  **/
8047 static int
8048 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8049 {
8050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8052         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8053         uint16_t seid;
8054         int ret;
8055
8056         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8057
8058         seid = pf->main_vsi->veb->seid;
8059
8060         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8061                 if (sw_id == it->index) {
8062                         mirr_rule = it;
8063                         break;
8064                 }
8065         }
8066         if (mirr_rule) {
8067                 ret = i40e_aq_del_mirror_rule(hw, seid,
8068                                 mirr_rule->rule_type,
8069                                 mirr_rule->entries,
8070                                 mirr_rule->num_entries, mirr_rule->id);
8071                 if (ret < 0) {
8072                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8073                                            " status = %d, aq_err = %d.",
8074                                            ret, hw->aq.asq_last_status);
8075                         return -ENOSYS;
8076                 }
8077                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8078                 rte_free(mirr_rule);
8079                 pf->nb_mirror_rule--;
8080         } else {
8081                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8082                 return -ENOENT;
8083         }
8084         return 0;
8085 }
8086
8087 static uint64_t
8088 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8089 {
8090         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8091         uint64_t systim_cycles;
8092
8093         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8094         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8095                         << 32;
8096
8097         return systim_cycles;
8098 }
8099
8100 static uint64_t
8101 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8102 {
8103         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8104         uint64_t rx_tstamp;
8105
8106         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8107         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8108                         << 32;
8109
8110         return rx_tstamp;
8111 }
8112
8113 static uint64_t
8114 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8115 {
8116         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8117         uint64_t tx_tstamp;
8118
8119         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8120         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8121                         << 32;
8122
8123         return tx_tstamp;
8124 }
8125
8126 static void
8127 i40e_start_timecounters(struct rte_eth_dev *dev)
8128 {
8129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8130         struct i40e_adapter *adapter =
8131                         (struct i40e_adapter *)dev->data->dev_private;
8132         struct rte_eth_link link;
8133         uint32_t tsync_inc_l;
8134         uint32_t tsync_inc_h;
8135
8136         /* Get current link speed. */
8137         memset(&link, 0, sizeof(link));
8138         i40e_dev_link_update(dev, 1);
8139         rte_i40e_dev_atomic_read_link_status(dev, &link);
8140
8141         switch (link.link_speed) {
8142         case ETH_LINK_SPEED_40G:
8143                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8144                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8145                 break;
8146         case ETH_LINK_SPEED_10G:
8147                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8148                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8149                 break;
8150         case ETH_LINK_SPEED_1000:
8151                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8152                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8153                 break;
8154         default:
8155                 tsync_inc_l = 0x0;
8156                 tsync_inc_h = 0x0;
8157         }
8158
8159         /* Set the timesync increment value. */
8160         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8161         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8162
8163         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8164         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8165         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8166
8167         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8168         adapter->systime_tc.cc_shift = 0;
8169         adapter->systime_tc.nsec_mask = 0;
8170
8171         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8172         adapter->rx_tstamp_tc.cc_shift = 0;
8173         adapter->rx_tstamp_tc.nsec_mask = 0;
8174
8175         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8176         adapter->tx_tstamp_tc.cc_shift = 0;
8177         adapter->tx_tstamp_tc.nsec_mask = 0;
8178 }
8179
8180 static int
8181 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8182 {
8183         struct i40e_adapter *adapter =
8184                         (struct i40e_adapter *)dev->data->dev_private;
8185
8186         adapter->systime_tc.nsec += delta;
8187         adapter->rx_tstamp_tc.nsec += delta;
8188         adapter->tx_tstamp_tc.nsec += delta;
8189
8190         return 0;
8191 }
8192
8193 static int
8194 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8195 {
8196         uint64_t ns;
8197         struct i40e_adapter *adapter =
8198                         (struct i40e_adapter *)dev->data->dev_private;
8199
8200         ns = rte_timespec_to_ns(ts);
8201
8202         /* Set the timecounters to a new value. */
8203         adapter->systime_tc.nsec = ns;
8204         adapter->rx_tstamp_tc.nsec = ns;
8205         adapter->tx_tstamp_tc.nsec = ns;
8206
8207         return 0;
8208 }
8209
8210 static int
8211 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8212 {
8213         uint64_t ns, systime_cycles;
8214         struct i40e_adapter *adapter =
8215                         (struct i40e_adapter *)dev->data->dev_private;
8216
8217         systime_cycles = i40e_read_systime_cyclecounter(dev);
8218         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8219         *ts = rte_ns_to_timespec(ns);
8220
8221         return 0;
8222 }
8223
8224 static int
8225 i40e_timesync_enable(struct rte_eth_dev *dev)
8226 {
8227         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8228         uint32_t tsync_ctl_l;
8229         uint32_t tsync_ctl_h;
8230
8231         /* Stop the timesync system time. */
8232         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8233         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8234         /* Reset the timesync system time value. */
8235         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8236         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8237
8238         i40e_start_timecounters(dev);
8239
8240         /* Clear timesync registers. */
8241         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8242         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8243         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8244         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8245         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8246         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8247
8248         /* Enable timestamping of PTP packets. */
8249         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8250         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8251
8252         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8253         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8254         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8255
8256         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8257         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8258
8259         return 0;
8260 }
8261
8262 static int
8263 i40e_timesync_disable(struct rte_eth_dev *dev)
8264 {
8265         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8266         uint32_t tsync_ctl_l;
8267         uint32_t tsync_ctl_h;
8268
8269         /* Disable timestamping of transmitted PTP packets. */
8270         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8271         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8272
8273         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8274         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8275
8276         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8277         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8278
8279         /* Reset the timesync increment value. */
8280         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8281         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8282
8283         return 0;
8284 }
8285
8286 static int
8287 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8288                                 struct timespec *timestamp, uint32_t flags)
8289 {
8290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8291         struct i40e_adapter *adapter =
8292                 (struct i40e_adapter *)dev->data->dev_private;
8293
8294         uint32_t sync_status;
8295         uint32_t index = flags & 0x03;
8296         uint64_t rx_tstamp_cycles;
8297         uint64_t ns;
8298
8299         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8300         if ((sync_status & (1 << index)) == 0)
8301                 return -EINVAL;
8302
8303         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8304         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8305         *timestamp = rte_ns_to_timespec(ns);
8306
8307         return 0;
8308 }
8309
8310 static int
8311 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8312                                 struct timespec *timestamp)
8313 {
8314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8315         struct i40e_adapter *adapter =
8316                 (struct i40e_adapter *)dev->data->dev_private;
8317
8318         uint32_t sync_status;
8319         uint64_t tx_tstamp_cycles;
8320         uint64_t ns;
8321
8322         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8323         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8324                 return -EINVAL;
8325
8326         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8327         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8328         *timestamp = rte_ns_to_timespec(ns);
8329
8330         return 0;
8331 }
8332
8333 /*
8334  * i40e_parse_dcb_configure - parse dcb configure from user
8335  * @dev: the device being configured
8336  * @dcb_cfg: pointer of the result of parse
8337  * @*tc_map: bit map of enabled traffic classes
8338  *
8339  * Returns 0 on success, negative value on failure
8340  */
8341 static int
8342 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8343                          struct i40e_dcbx_config *dcb_cfg,
8344                          uint8_t *tc_map)
8345 {
8346         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8347         uint8_t i, tc_bw, bw_lf;
8348
8349         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8350
8351         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8352         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8353                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8354                 return -EINVAL;
8355         }
8356
8357         /* assume each tc has the same bw */
8358         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8359         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8360                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8361         /* to ensure the sum of tcbw is equal to 100 */
8362         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8363         for (i = 0; i < bw_lf; i++)
8364                 dcb_cfg->etscfg.tcbwtable[i]++;
8365
8366         /* assume each tc has the same Transmission Selection Algorithm */
8367         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8368                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8369
8370         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8371                 dcb_cfg->etscfg.prioritytable[i] =
8372                                 dcb_rx_conf->dcb_tc[i];
8373
8374         /* FW needs one App to configure HW */
8375         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8376         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8377         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8378         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8379
8380         if (dcb_rx_conf->nb_tcs == 0)
8381                 *tc_map = 1; /* tc0 only */
8382         else
8383                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8384
8385         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8386                 dcb_cfg->pfc.willing = 0;
8387                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8388                 dcb_cfg->pfc.pfcenable = *tc_map;
8389         }
8390         return 0;
8391 }
8392
8393
8394 static enum i40e_status_code
8395 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8396                               struct i40e_aqc_vsi_properties_data *info,
8397                               uint8_t enabled_tcmap)
8398 {
8399         enum i40e_status_code ret;
8400         int i, total_tc = 0;
8401         uint16_t qpnum_per_tc, bsf, qp_idx;
8402         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8403         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8404         uint16_t used_queues;
8405
8406         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8407         if (ret != I40E_SUCCESS)
8408                 return ret;
8409
8410         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8411                 if (enabled_tcmap & (1 << i))
8412                         total_tc++;
8413         }
8414         if (total_tc == 0)
8415                 total_tc = 1;
8416         vsi->enabled_tc = enabled_tcmap;
8417
8418         /* different VSI has different queues assigned */
8419         if (vsi->type == I40E_VSI_MAIN)
8420                 used_queues = dev_data->nb_rx_queues -
8421                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8422         else if (vsi->type == I40E_VSI_VMDQ2)
8423                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8424         else {
8425                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8426                 return I40E_ERR_NO_AVAILABLE_VSI;
8427         }
8428
8429         qpnum_per_tc = used_queues / total_tc;
8430         /* Number of queues per enabled TC */
8431         if (qpnum_per_tc == 0) {
8432                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8433                 return I40E_ERR_INVALID_QP_ID;
8434         }
8435         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8436                                 I40E_MAX_Q_PER_TC);
8437         bsf = rte_bsf32(qpnum_per_tc);
8438
8439         /**
8440          * Configure TC and queue mapping parameters, for enabled TC,
8441          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8442          * default queue will serve it.
8443          */
8444         qp_idx = 0;
8445         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8446                 if (vsi->enabled_tc & (1 << i)) {
8447                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8448                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8449                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8450                         qp_idx += qpnum_per_tc;
8451                 } else
8452                         info->tc_mapping[i] = 0;
8453         }
8454
8455         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8456         if (vsi->type == I40E_VSI_SRIOV) {
8457                 info->mapping_flags |=
8458                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8459                 for (i = 0; i < vsi->nb_qps; i++)
8460                         info->queue_mapping[i] =
8461                                 rte_cpu_to_le_16(vsi->base_queue + i);
8462         } else {
8463                 info->mapping_flags |=
8464                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8465                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8466         }
8467         info->valid_sections |=
8468                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8469
8470         return I40E_SUCCESS;
8471 }
8472
8473 /*
8474  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8475  * @veb: VEB to be configured
8476  * @tc_map: enabled TC bitmap
8477  *
8478  * Returns 0 on success, negative value on failure
8479  */
8480 static enum i40e_status_code
8481 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8482 {
8483         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8484         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8485         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8486         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8487         enum i40e_status_code ret = I40E_SUCCESS;
8488         int i;
8489         uint32_t bw_max;
8490
8491         /* Check if enabled_tc is same as existing or new TCs */
8492         if (veb->enabled_tc == tc_map)
8493                 return ret;
8494
8495         /* configure tc bandwidth */
8496         memset(&veb_bw, 0, sizeof(veb_bw));
8497         veb_bw.tc_valid_bits = tc_map;
8498         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8499         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8500                 if (tc_map & BIT_ULL(i))
8501                         veb_bw.tc_bw_share_credits[i] = 1;
8502         }
8503         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8504                                                    &veb_bw, NULL);
8505         if (ret) {
8506                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8507                                   " per TC failed = %d",
8508                                   hw->aq.asq_last_status);
8509                 return ret;
8510         }
8511
8512         memset(&ets_query, 0, sizeof(ets_query));
8513         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8514                                                    &ets_query, NULL);
8515         if (ret != I40E_SUCCESS) {
8516                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8517                                  " configuration %u", hw->aq.asq_last_status);
8518                 return ret;
8519         }
8520         memset(&bw_query, 0, sizeof(bw_query));
8521         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8522                                                   &bw_query, NULL);
8523         if (ret != I40E_SUCCESS) {
8524                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8525                                  " configuration %u", hw->aq.asq_last_status);
8526                 return ret;
8527         }
8528
8529         /* store and print out BW info */
8530         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8531         veb->bw_info.bw_max = ets_query.tc_bw_max;
8532         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8533         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8534         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8535                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8536                      I40E_16_BIT_WIDTH);
8537         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8538                 veb->bw_info.bw_ets_share_credits[i] =
8539                                 bw_query.tc_bw_share_credits[i];
8540                 veb->bw_info.bw_ets_credits[i] =
8541                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8542                 /* 4 bits per TC, 4th bit is reserved */
8543                 veb->bw_info.bw_ets_max[i] =
8544                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8545                                   RTE_LEN2MASK(3, uint8_t));
8546                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8547                             veb->bw_info.bw_ets_share_credits[i]);
8548                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8549                             veb->bw_info.bw_ets_credits[i]);
8550                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8551                             veb->bw_info.bw_ets_max[i]);
8552         }
8553
8554         veb->enabled_tc = tc_map;
8555
8556         return ret;
8557 }
8558
8559
8560 /*
8561  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8562  * @vsi: VSI to be configured
8563  * @tc_map: enabled TC bitmap
8564  *
8565  * Returns 0 on success, negative value on failure
8566  */
8567 static enum i40e_status_code
8568 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8569 {
8570         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8571         struct i40e_vsi_context ctxt;
8572         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8573         enum i40e_status_code ret = I40E_SUCCESS;
8574         int i;
8575
8576         /* Check if enabled_tc is same as existing or new TCs */
8577         if (vsi->enabled_tc == tc_map)
8578                 return ret;
8579
8580         /* configure tc bandwidth */
8581         memset(&bw_data, 0, sizeof(bw_data));
8582         bw_data.tc_valid_bits = tc_map;
8583         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8584         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8585                 if (tc_map & BIT_ULL(i))
8586                         bw_data.tc_bw_credits[i] = 1;
8587         }
8588         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8589         if (ret) {
8590                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8591                         " per TC failed = %d",
8592                         hw->aq.asq_last_status);
8593                 goto out;
8594         }
8595         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8596                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8597
8598         /* Update Queue Pairs Mapping for currently enabled UPs */
8599         ctxt.seid = vsi->seid;
8600         ctxt.pf_num = hw->pf_id;
8601         ctxt.vf_num = 0;
8602         ctxt.uplink_seid = vsi->uplink_seid;
8603         ctxt.info = vsi->info;
8604         i40e_get_cap(hw);
8605         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8606         if (ret)
8607                 goto out;
8608
8609         /* Update the VSI after updating the VSI queue-mapping information */
8610         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8611         if (ret) {
8612                 PMD_INIT_LOG(ERR, "Failed to configure "
8613                             "TC queue mapping = %d",
8614                             hw->aq.asq_last_status);
8615                 goto out;
8616         }
8617         /* update the local VSI info with updated queue map */
8618         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8619                                         sizeof(vsi->info.tc_mapping));
8620         (void)rte_memcpy(&vsi->info.queue_mapping,
8621                         &ctxt.info.queue_mapping,
8622                 sizeof(vsi->info.queue_mapping));
8623         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8624         vsi->info.valid_sections = 0;
8625
8626         /* query and update current VSI BW information */
8627         ret = i40e_vsi_get_bw_config(vsi);
8628         if (ret) {
8629                 PMD_INIT_LOG(ERR,
8630                          "Failed updating vsi bw info, err %s aq_err %s",
8631                          i40e_stat_str(hw, ret),
8632                          i40e_aq_str(hw, hw->aq.asq_last_status));
8633                 goto out;
8634         }
8635
8636         vsi->enabled_tc = tc_map;
8637
8638 out:
8639         return ret;
8640 }
8641
8642 /*
8643  * i40e_dcb_hw_configure - program the dcb setting to hw
8644  * @pf: pf the configuration is taken on
8645  * @new_cfg: new configuration
8646  * @tc_map: enabled TC bitmap
8647  *
8648  * Returns 0 on success, negative value on failure
8649  */
8650 static enum i40e_status_code
8651 i40e_dcb_hw_configure(struct i40e_pf *pf,
8652                       struct i40e_dcbx_config *new_cfg,
8653                       uint8_t tc_map)
8654 {
8655         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8656         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8657         struct i40e_vsi *main_vsi = pf->main_vsi;
8658         struct i40e_vsi_list *vsi_list;
8659         enum i40e_status_code ret;
8660         int i;
8661         uint32_t val;
8662
8663         /* Use the FW API if FW > v4.4*/
8664         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8665               (hw->aq.fw_maj_ver >= 5))) {
8666                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8667                                   " to configure DCB");
8668                 return I40E_ERR_FIRMWARE_API_VERSION;
8669         }
8670
8671         /* Check if need reconfiguration */
8672         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8673                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8674                 return I40E_SUCCESS;
8675         }
8676
8677         /* Copy the new config to the current config */
8678         *old_cfg = *new_cfg;
8679         old_cfg->etsrec = old_cfg->etscfg;
8680         ret = i40e_set_dcb_config(hw);
8681         if (ret) {
8682                 PMD_INIT_LOG(ERR,
8683                          "Set DCB Config failed, err %s aq_err %s\n",
8684                          i40e_stat_str(hw, ret),
8685                          i40e_aq_str(hw, hw->aq.asq_last_status));
8686                 return ret;
8687         }
8688         /* set receive Arbiter to RR mode and ETS scheme by default */
8689         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8690                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8691                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8692                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8693                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8694                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8695                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8696                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8697                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8698                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8699                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8700                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8701                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8702         }
8703         /* get local mib to check whether it is configured correctly */
8704         /* IEEE mode */
8705         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8706         /* Get Local DCB Config */
8707         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8708                                      &hw->local_dcbx_config);
8709
8710         /* if Veb is created, need to update TC of it at first */
8711         if (main_vsi->veb) {
8712                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8713                 if (ret)
8714                         PMD_INIT_LOG(WARNING,
8715                                  "Failed configuring TC for VEB seid=%d\n",
8716                                  main_vsi->veb->seid);
8717         }
8718         /* Update each VSI */
8719         i40e_vsi_config_tc(main_vsi, tc_map);
8720         if (main_vsi->veb) {
8721                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8722                         /* Beside main VSI and VMDQ VSIs, only enable default
8723                          * TC for other VSIs
8724                          */
8725                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8726                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8727                                                          tc_map);
8728                         else
8729                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
8730                                                          I40E_DEFAULT_TCMAP);
8731                         if (ret)
8732                                 PMD_INIT_LOG(WARNING,
8733                                          "Failed configuring TC for VSI seid=%d\n",
8734                                          vsi_list->vsi->seid);
8735                         /* continue */
8736                 }
8737         }
8738         return I40E_SUCCESS;
8739 }
8740
8741 /*
8742  * i40e_dcb_init_configure - initial dcb config
8743  * @dev: device being configured
8744  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8745  *
8746  * Returns 0 on success, negative value on failure
8747  */
8748 static int
8749 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8750 {
8751         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8752         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8753         int ret = 0;
8754
8755         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8756                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8757                 return -ENOTSUP;
8758         }
8759
8760         /* DCB initialization:
8761          * Update DCB configuration from the Firmware and configure
8762          * LLDP MIB change event.
8763          */
8764         if (sw_dcb == TRUE) {
8765                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8766                 if (ret != I40E_SUCCESS)
8767                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8768
8769                 ret = i40e_init_dcb(hw);
8770                 /* if sw_dcb, lldp agent is stopped, the return from
8771                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8772                  * adminq status.
8773                  */
8774                 if (ret != I40E_SUCCESS &&
8775                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8776                         memset(&hw->local_dcbx_config, 0,
8777                                 sizeof(struct i40e_dcbx_config));
8778                         /* set dcb default configuration */
8779                         hw->local_dcbx_config.etscfg.willing = 0;
8780                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8781                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8782                         hw->local_dcbx_config.etscfg.tsatable[0] =
8783                                                 I40E_IEEE_TSA_ETS;
8784                         hw->local_dcbx_config.etsrec =
8785                                 hw->local_dcbx_config.etscfg;
8786                         hw->local_dcbx_config.pfc.willing = 0;
8787                         hw->local_dcbx_config.pfc.pfccap =
8788                                                 I40E_MAX_TRAFFIC_CLASS;
8789                         /* FW needs one App to configure HW */
8790                         hw->local_dcbx_config.numapps = 1;
8791                         hw->local_dcbx_config.app[0].selector =
8792                                                 I40E_APP_SEL_ETHTYPE;
8793                         hw->local_dcbx_config.app[0].priority = 3;
8794                         hw->local_dcbx_config.app[0].protocolid =
8795                                                 I40E_APP_PROTOID_FCOE;
8796                         ret = i40e_set_dcb_config(hw);
8797                         if (ret) {
8798                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8799                                         " err = %d, aq_err = %d.", ret,
8800                                           hw->aq.asq_last_status);
8801                                 return -ENOSYS;
8802                         }
8803                 } else {
8804                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8805                                           " aq_err = %d.", ret,
8806                                           hw->aq.asq_last_status);
8807                         return -ENOTSUP;
8808                 }
8809         } else {
8810                 ret = i40e_aq_start_lldp(hw, NULL);
8811                 if (ret != I40E_SUCCESS)
8812                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8813
8814                 ret = i40e_init_dcb(hw);
8815                 if (!ret) {
8816                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8817                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8818                                                   " DCBX offload.");
8819                                 return -ENOTSUP;
8820                         }
8821                 } else {
8822                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8823                                           " aq_err = %d.", ret,
8824                                           hw->aq.asq_last_status);
8825                         return -ENOTSUP;
8826                 }
8827         }
8828         return 0;
8829 }
8830
8831 /*
8832  * i40e_dcb_setup - setup dcb related config
8833  * @dev: device being configured
8834  *
8835  * Returns 0 on success, negative value on failure
8836  */
8837 static int
8838 i40e_dcb_setup(struct rte_eth_dev *dev)
8839 {
8840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8841         struct i40e_dcbx_config dcb_cfg;
8842         uint8_t tc_map = 0;
8843         int ret = 0;
8844
8845         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8846                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8847                 return -ENOTSUP;
8848         }
8849
8850         if (pf->vf_num != 0)
8851                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8852
8853         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8854         if (ret) {
8855                 PMD_INIT_LOG(ERR, "invalid dcb config");
8856                 return -EINVAL;
8857         }
8858         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8859         if (ret) {
8860                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8861                 return -ENOSYS;
8862         }
8863
8864         return 0;
8865 }
8866
8867 static int
8868 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8869                       struct rte_eth_dcb_info *dcb_info)
8870 {
8871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8873         struct i40e_vsi *vsi = pf->main_vsi;
8874         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8875         uint16_t bsf, tc_mapping;
8876         int i, j;
8877
8878         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8879                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8880         else
8881                 dcb_info->nb_tcs = 1;
8882         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8883                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8884         for (i = 0; i < dcb_info->nb_tcs; i++)
8885                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8886
8887         j = 0;
8888         do {
8889                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8890                         if (!(vsi->enabled_tc & (1 << i)))
8891                                 continue;
8892                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8893                         /* only main vsi support multi TCs */
8894                         dcb_info->tc_queue.tc_rxq[j][i].base =
8895                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8896                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8897                         dcb_info->tc_queue.tc_txq[j][i].base =
8898                                 dcb_info->tc_queue.tc_rxq[j][i].base;
8899                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8900                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8901                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8902                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8903                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8904                 }
8905                 vsi = pf->vmdq[j].vsi;
8906                 j++;
8907         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8908         return 0;
8909 }
8910
8911 static int
8912 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8913 {
8914         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8916         uint16_t interval =
8917                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8918         uint16_t msix_intr;
8919
8920         msix_intr = intr_handle->intr_vec[queue_id];
8921         if (msix_intr == I40E_MISC_VEC_ID)
8922                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8923                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8924                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8925                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8926                                (interval <<
8927                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8928         else
8929                 I40E_WRITE_REG(hw,
8930                                I40E_PFINT_DYN_CTLN(msix_intr -
8931                                                    I40E_RX_VEC_START),
8932                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8933                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8934                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8935                                (interval <<
8936                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8937
8938         I40E_WRITE_FLUSH(hw);
8939         rte_intr_enable(&dev->pci_dev->intr_handle);
8940
8941         return 0;
8942 }
8943
8944 static int
8945 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8946 {
8947         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8949         uint16_t msix_intr;
8950
8951         msix_intr = intr_handle->intr_vec[queue_id];
8952         if (msix_intr == I40E_MISC_VEC_ID)
8953                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8954         else
8955                 I40E_WRITE_REG(hw,
8956                                I40E_PFINT_DYN_CTLN(msix_intr -
8957                                                    I40E_RX_VEC_START),
8958                                0);
8959         I40E_WRITE_FLUSH(hw);
8960
8961         return 0;
8962 }
8963
8964 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
8965 {
8966         /* Highest base addr + 32-bit word */
8967         return I40E_GLGEN_STAT_CLEAR + 4;
8968 }
8969
8970 static int i40e_get_regs(struct rte_eth_dev *dev,
8971                          struct rte_dev_reg_info *regs)
8972 {
8973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8974         uint32_t *ptr_data = regs->data;
8975         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
8976         const struct i40e_reg_info *reg_info;
8977
8978         /* The first few registers have to be read using AQ operations */
8979         reg_idx = 0;
8980         while (i40e_regs_adminq[reg_idx].name) {
8981                 reg_info = &i40e_regs_adminq[reg_idx++];
8982                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8983                         for (arr_idx2 = 0;
8984                                         arr_idx2 <= reg_info->count2;
8985                                         arr_idx2++) {
8986                                 reg_offset = arr_idx * reg_info->stride1 +
8987                                         arr_idx2 * reg_info->stride2;
8988                                 ptr_data[reg_offset >> 2] =
8989                                         i40e_read_rx_ctl(hw, reg_offset);
8990                         }
8991         }
8992
8993         /* The remaining registers can be read using primitives */
8994         reg_idx = 0;
8995         while (i40e_regs_others[reg_idx].name) {
8996                 reg_info = &i40e_regs_others[reg_idx++];
8997                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
8998                         for (arr_idx2 = 0;
8999                                         arr_idx2 <= reg_info->count2;
9000                                         arr_idx2++) {
9001                                 reg_offset = arr_idx * reg_info->stride1 +
9002                                         arr_idx2 * reg_info->stride2;
9003                                 ptr_data[reg_offset >> 2] =
9004                                         I40E_READ_REG(hw, reg_offset);
9005                         }
9006         }
9007
9008         return 0;
9009 }
9010
9011 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9012 {
9013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9014
9015         /* Convert word count to byte count */
9016         return hw->nvm.sr_size << 1;
9017 }
9018
9019 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9020                            struct rte_dev_eeprom_info *eeprom)
9021 {
9022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9023         uint16_t *data = eeprom->data;
9024         uint16_t offset, length, cnt_words;
9025         int ret_code;
9026
9027         offset = eeprom->offset >> 1;
9028         length = eeprom->length >> 1;
9029         cnt_words = length;
9030
9031         if (offset > hw->nvm.sr_size ||
9032                 offset + length > hw->nvm.sr_size) {
9033                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9034                 return -EINVAL;
9035         }
9036
9037         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9038
9039         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9040         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9041                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9042                 return -EIO;
9043         }
9044
9045         return 0;
9046 }
9047
9048 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9049                                       struct ether_addr *mac_addr)
9050 {
9051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9052
9053         if (!is_valid_assigned_ether_addr(mac_addr)) {
9054                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9055                 return;
9056         }
9057
9058         /* Flags: 0x3 updates port address */
9059         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9060 }