drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64
  65 /* Maximun number of MAC addresses */
  66 #define I40E_NUM_MACADDR_MAX       64
  67 #define I40E_CLEAR_PXE_WAIT_MS     200
  68
  69 /* Maximun number of capability elements */
  70 #define I40E_MAX_CAP_ELE_NUM       128
  71
  72 /* Wait count and inteval */
  73 #define I40E_CHK_Q_ENA_COUNT       1000
  74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  75
  76 /* Maximun number of VSI */
  77 #define I40E_MAX_NUM_VSIS          (384UL)
  78
  79 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  80
  81 /* Flow control default timer */
  82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  83
  84 /* Flow control default high water */
  85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  86
  87 /* Flow control default low water */
  88 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  89
  90 /* Flow control enable fwd bit */
  91 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  92
  93 /* Receive Packet Buffer size */
  94 #define I40E_RXPBSIZE (968 * 1024)
  95
  96 /* Kilobytes shift */
  97 #define I40E_KILOSHIFT 10
  98
  99 /* Receive Average Packet Size in Byte*/
 100 #define I40E_PACKET_AVERAGE_SIZE 128
 101
 102 /* Mask of PF interrupt causes */
 103 #define I40E_PFINT_ICR0_ENA_MASK ( \
 104                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 105                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 106                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 107                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 108                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 110                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 112                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 114
 115 #define I40E_FLOW_TYPES ( \
 116         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 117         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 118         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 121         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 126         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 127
 128 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 129 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 130 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 131 #define I40E_PRTTSYN_TSYNENA  0x80000000
 132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 133
 134 #define I40E_MAX_PERCENT            100
 135 #define I40E_DEFAULT_DCB_APP_NUM    1
 136 #define I40E_DEFAULT_DCB_APP_PRIO   3
 137
 138 #define I40E_PRTQF_FD_INSET(_i, _j)  (0x00250000 + ((_i) * 64 + (_j) * 32))
 139 #define I40E_GLQF_FD_MSK(_i, _j)     (0x00267200 + ((_i) * 4 + (_j) * 8))
 140 #define I40E_GLQF_FD_MSK_FIELD       0x0000FFFF
 141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
 142 #define I40E_GLQF_HASH_MSK(_i, _j)   (0x00267A00 + ((_i) * 4 + (_j) * 8))
 143 #define I40E_GLQF_HASH_MSK_FIELD      0x0000FFFF
 144
 145 #define I40E_INSET_NONE            0x00000000000000000ULL
 146
 147 /* bit0 ~ bit 7 */
 148 #define I40E_INSET_DMAC            0x0000000000000001ULL
 149 #define I40E_INSET_SMAC            0x0000000000000002ULL
 150 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 151 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 152 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 153
 154 /* bit 8 ~ bit 15 */
 155 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 156 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 157 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 158 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 159 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 160 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 161 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 162
 163 /* bit 16 ~ bit 31 */
 164 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 165 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 166 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 167 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 168 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 169 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 170 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 171 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 172
 173 /* bit 32 ~ bit 47, tunnel fields */
 174 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 175 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 176 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 177 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 178 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 179 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 180
 181 /* bit 48 ~ bit 55 */
 182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 183
 184 /* bit 56 ~ bit 63, Flex Payload */
 185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 193 #define I40E_INSET_FLEX_PAYLOAD \
 194         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 195         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
 196         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 197         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 198
 199 /**
 200  * Below are values for writing un-exposed registers suggested
 201  * by silicon experts
 202  */
 203 /* Destination MAC address */
 204 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 205 /* Source MAC address */
 206 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 207 /* VLAN tag in the outer L2 header */
 208 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000000800000ULL
 209 /* VLAN tag in the inner L2 header */
 210 #define I40E_REG_INSET_L2_INNER_VLAN             0x0000000001000000ULL
 211 /* Source IPv4 address */
 212 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 213 /* Destination IPv4 address */
 214 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 215 /* IPv4 Type of Service (TOS) */
 216 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 217 /* IPv4 Protocol */
 218 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 219 /* Source IPv6 address */
 220 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 221 /* Destination IPv6 address */
 222 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 223 /* IPv6 Traffic Class (TC) */
 224 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 225 /* IPv6 Next Header */
 226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 227 /* Source L4 port */
 228 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 229 /* Destination L4 port */
 230 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 231 /* SCTP verification tag */
 232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 235 /* Source port of tunneling UDP */
 236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 237 /* Destination port of tunneling UDP */
 238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 239 /* UDP Tunneling ID, NVGRE/GRE key */
 240 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 241 /* Last ether type */
 242 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 243 /* Tunneling outer destination IPv4 address */
 244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 245 /* Tunneling outer destination IPv6 address */
 246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 247 /* 1st word of flex payload */
 248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 249 /* 2nd word of flex payload */
 250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 251 /* 3rd word of flex payload */
 252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 253 /* 4th word of flex payload */
 254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 255 /* 5th word of flex payload */
 256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 257 /* 6th word of flex payload */
 258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 259 /* 7th word of flex payload */
 260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 261 /* 8th word of flex payload */
 262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 263
 264 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 265
 266 #define I40E_TRANSLATE_INSET 0
 267 #define I40E_TRANSLATE_REG   1
 268
 269 #define I40E_INSET_IPV4_TOS_MASK      0x0009FF00UL
 270 #define I40E_INSET_IPV4_PROTO_MASK    0x000DFF00UL
 271 #define I40E_INSET_IPV6_TC_MASK       0x0009F00FUL
 272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
 273
 274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 276 static int i40e_dev_configure(struct rte_eth_dev *dev);
 277 static int i40e_dev_start(struct rte_eth_dev *dev);
 278 static void i40e_dev_stop(struct rte_eth_dev *dev);
 279 static void i40e_dev_close(struct rte_eth_dev *dev);
 280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 287                                struct rte_eth_stats *stats);
 288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 289                                struct rte_eth_xstats *xstats, unsigned n);
 290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 291 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 292                                             uint16_t queue_id,
 293                                             uint8_t stat_idx,
 294                                             uint8_t is_rx);
 295 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 296                               struct rte_eth_dev_info *dev_info);
 297 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 298                                 uint16_t vlan_id,
 299                                 int on);
 300 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 301 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 302 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 303                                       uint16_t queue,
 304                                       int on);
 305 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 306 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 307 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 308 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 309                               struct rte_eth_fc_conf *fc_conf);
 310 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 311                               struct rte_eth_fc_conf *fc_conf);
 312 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 313                                        struct rte_eth_pfc_conf *pfc_conf);
 314 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 315                           struct ether_addr *mac_addr,
 316                           uint32_t index,
 317                           uint32_t pool);
 318 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 319 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 320                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 321                                     uint16_t reta_size);
 322 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 323                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 324                                    uint16_t reta_size);
 325
 326 static int i40e_get_cap(struct i40e_hw *hw);
 327 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 328 static int i40e_pf_setup(struct i40e_pf *pf);
 329 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 330 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 331 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 332 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 333 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 334                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 335 static void i40e_stat_update_48(struct i40e_hw *hw,
 336                                uint32_t hireg,
 337                                uint32_t loreg,
 338                                bool offset_loaded,
 339                                uint64_t *offset,
 340                                uint64_t *stat);
 341 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 342 static void i40e_dev_interrupt_handler(
 343                 __rte_unused struct rte_intr_handle *handle, void *param);
 344 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 345                                 uint32_t base, uint32_t num);
 346 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 347 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 348                         uint32_t base);
 349 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 350                         uint16_t num);
 351 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 352 static int i40e_veb_release(struct i40e_veb *veb);
 353 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 354                                                 struct i40e_vsi *vsi);
 355 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 356 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 357 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 358                                              struct i40e_macvlan_filter *mv_f,
 359                                              int num,
 360                                              struct ether_addr *addr);
 361 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 362                                              struct i40e_macvlan_filter *mv_f,
 363                                              int num,
 364                                              uint16_t vlan);
 365 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 366 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 367                                     struct rte_eth_rss_conf *rss_conf);
 368 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 369                                       struct rte_eth_rss_conf *rss_conf);
 370 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 371                                 struct rte_eth_udp_tunnel *udp_tunnel);
 372 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 373                                 struct rte_eth_udp_tunnel *udp_tunnel);
 374 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 375                         struct rte_eth_ethertype_filter *filter,
 376                         bool add);
 377 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 378                                 enum rte_filter_op filter_op,
 379                                 void *arg);
 380 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 381                                 enum rte_filter_type filter_type,
 382                                 enum rte_filter_op filter_op,
 383                                 void *arg);
 384 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 385                                   struct rte_eth_dcb_info *dcb_info);
 386 static void i40e_configure_registers(struct i40e_hw *hw);
 387 static void i40e_hw_init(struct i40e_hw *hw);
 388 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 389 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 390                         struct rte_eth_mirror_conf *mirror_conf,
 391                         uint8_t sw_id, uint8_t on);
 392 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 393
 394 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 395 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 396 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 397                                            struct timespec *timestamp,
 398                                            uint32_t flags);
 399 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 400                                            struct timespec *timestamp);
 401 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 402 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 403                                          uint16_t queue_id);
 404 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 405                                           uint16_t queue_id);
 406
 407 static const struct rte_pci_id pci_id_i40e_map[] = {
 408 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 409 #include "rte_pci_dev_ids.h"
 410 { .vendor_id = 0, /* sentinel */ },
 411 };
 412
 413 static const struct eth_dev_ops i40e_eth_dev_ops = {
 414         .dev_configure                = i40e_dev_configure,
 415         .dev_start                    = i40e_dev_start,
 416         .dev_stop                     = i40e_dev_stop,
 417         .dev_close                    = i40e_dev_close,
 418         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 419         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 420         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 421         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 422         .dev_set_link_up              = i40e_dev_set_link_up,
 423         .dev_set_link_down            = i40e_dev_set_link_down,
 424         .link_update                  = i40e_dev_link_update,
 425         .stats_get                    = i40e_dev_stats_get,
 426         .xstats_get                   = i40e_dev_xstats_get,
 427         .stats_reset                  = i40e_dev_stats_reset,
 428         .xstats_reset                 = i40e_dev_stats_reset,
 429         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 430         .dev_infos_get                = i40e_dev_info_get,
 431         .vlan_filter_set              = i40e_vlan_filter_set,
 432         .vlan_tpid_set                = i40e_vlan_tpid_set,
 433         .vlan_offload_set             = i40e_vlan_offload_set,
 434         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 435         .vlan_pvid_set                = i40e_vlan_pvid_set,
 436         .rx_queue_start               = i40e_dev_rx_queue_start,
 437         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 438         .tx_queue_start               = i40e_dev_tx_queue_start,
 439         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 440         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 441         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 443         .rx_queue_release             = i40e_dev_rx_queue_release,
 444         .rx_queue_count               = i40e_dev_rx_queue_count,
 445         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 446         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 447         .tx_queue_release             = i40e_dev_tx_queue_release,
 448         .dev_led_on                   = i40e_dev_led_on,
 449         .dev_led_off                  = i40e_dev_led_off,
 450         .flow_ctrl_get                = i40e_flow_ctrl_get,
 451         .flow_ctrl_set                = i40e_flow_ctrl_set,
 452         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 453         .mac_addr_add                 = i40e_macaddr_add,
 454         .mac_addr_remove              = i40e_macaddr_remove,
 455         .reta_update                  = i40e_dev_rss_reta_update,
 456         .reta_query                   = i40e_dev_rss_reta_query,
 457         .rss_hash_update              = i40e_dev_rss_hash_update,
 458         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 459         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 460         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 461         .filter_ctrl                  = i40e_dev_filter_ctrl,
 462         .rxq_info_get                 = i40e_rxq_info_get,
 463         .txq_info_get                 = i40e_txq_info_get,
 464         .mirror_rule_set              = i40e_mirror_rule_set,
 465         .mirror_rule_reset            = i40e_mirror_rule_reset,
 466         .timesync_enable              = i40e_timesync_enable,
 467         .timesync_disable             = i40e_timesync_disable,
 468         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 469         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 470         .get_dcb_info                 = i40e_dev_get_dcb_info,
 471 };
 472
 473 /* store statistics names and its offset in stats structure */
 474 struct rte_i40e_xstats_name_off {
 475         char name[RTE_ETH_XSTATS_NAME_SIZE];
 476         unsigned offset;
 477 };
 478
 479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 480         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 481         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 482         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 483         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 484         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 485                 rx_unknown_protocol)},
 486         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 487         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 488         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 489         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 490 };
 491
 492 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 493                 sizeof(rte_i40e_stats_strings[0]))
 494
 495 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 496         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 497                 tx_dropped_link_down)},
 498         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 499         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 500                 illegal_bytes)},
 501         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 502         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 503                 mac_local_faults)},
 504         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 505                 mac_remote_faults)},
 506         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 507                 rx_length_errors)},
 508         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 509         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 510         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 511         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 512         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 513         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 514                 rx_size_127)},
 515         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 516                 rx_size_255)},
 517         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 518                 rx_size_511)},
 519         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 520                 rx_size_1023)},
 521         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 522                 rx_size_1522)},
 523         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 524                 rx_size_big)},
 525         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 526                 rx_undersize)},
 527         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 528                 rx_oversize)},
 529         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 530                 mac_short_packet_dropped)},
 531         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_fragments)},
 533         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 534         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 535         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 536                 tx_size_127)},
 537         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 538                 tx_size_255)},
 539         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 540                 tx_size_511)},
 541         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 542                 tx_size_1023)},
 543         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 544                 tx_size_1522)},
 545         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 546                 tx_size_big)},
 547         {"rx_flow_director_atr_match_packets",
 548                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 549         {"rx_flow_director_sb_match_packets",
 550                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 551         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 552                 tx_lpi_status)},
 553         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 554                 rx_lpi_status)},
 555         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 556                 tx_lpi_count)},
 557         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 558                 rx_lpi_count)},
 559 };
 560
 561 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 562                 sizeof(rte_i40e_hw_port_strings[0]))
 563
 564 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 565         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 566                 priority_xon_rx)},
 567         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 568                 priority_xoff_rx)},
 569 };
 570
 571 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 572                 sizeof(rte_i40e_rxq_prio_strings[0]))
 573
 574 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 575         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 576                 priority_xon_tx)},
 577         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 578                 priority_xoff_tx)},
 579         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 580                 priority_xon_2_xoff)},
 581 };
 582
 583 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 584                 sizeof(rte_i40e_txq_prio_strings[0]))
 585
 586 static struct eth_driver rte_i40e_pmd = {
 587         .pci_drv = {
 588                 .name = "rte_i40e_pmd",
 589                 .id_table = pci_id_i40e_map,
 590                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 591                         RTE_PCI_DRV_DETACHABLE,
 592         },
 593         .eth_dev_init = eth_i40e_dev_init,
 594         .eth_dev_uninit = eth_i40e_dev_uninit,
 595         .dev_private_size = sizeof(struct i40e_adapter),
 596 };
 597
 598 static inline int
 599 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 600                                      struct rte_eth_link *link)
 601 {
 602         struct rte_eth_link *dst = link;
 603         struct rte_eth_link *src = &(dev->data->dev_link);
 604
 605         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 606                                         *(uint64_t *)src) == 0)
 607                 return -1;
 608
 609         return 0;
 610 }
 611
 612 static inline int
 613 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 614                                       struct rte_eth_link *link)
 615 {
 616         struct rte_eth_link *dst = &(dev->data->dev_link);
 617         struct rte_eth_link *src = link;
 618
 619         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 620                                         *(uint64_t *)src) == 0)
 621                 return -1;
 622
 623         return 0;
 624 }
 625
 626 /*
 627  * Driver initialization routine.
 628  * Invoked once at EAL init time.
 629  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 630  */
 631 static int
 632 rte_i40e_pmd_init(const char *name __rte_unused,
 633                   const char *params __rte_unused)
 634 {
 635         PMD_INIT_FUNC_TRACE();
 636         rte_eth_driver_register(&rte_i40e_pmd);
 637
 638         return 0;
 639 }
 640
 641 static struct rte_driver rte_i40e_driver = {
 642         .type = PMD_PDEV,
 643         .init = rte_i40e_pmd_init,
 644 };
 645
 646 PMD_REGISTER_DRIVER(rte_i40e_driver);
 647
 648 /*
 649  * Initialize registers for flexible payload, which should be set by NVM.
 650  * This should be removed from code once it is fixed in NVM.
 651  */
 652 #ifndef I40E_GLQF_ORT
 653 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 654 #endif
 655 #ifndef I40E_GLQF_PIT
 656 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 657 #endif
 658
 659 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 660 {
 661         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 662         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 663         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 664         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 665         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 666         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 667         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 668         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 669         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 670         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 671
 672         /* GLQF_PIT Registers */
 673         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 674         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 675 }
 676
 677 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 678
 679 /*
 680  * Add a ethertype filter to drop all flow control frames transmitted
 681  * from VSIs.
 682 */
 683 static void
 684 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 685 {
 686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 687         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 688                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 689                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 690         int ret;
 691
 692         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 693                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 694                                 pf->main_vsi_seid, 0,
 695                                 TRUE, NULL, NULL);
 696         if (ret)
 697                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 698                                   " frames from VSIs.");
 699 }
 700
 701 static int
 702 eth_i40e_dev_init(struct rte_eth_dev *dev)
 703 {
 704         struct rte_pci_device *pci_dev;
 705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 707         struct i40e_vsi *vsi;
 708         int ret;
 709         uint32_t len;
 710         uint8_t aq_fail = 0;
 711
 712         PMD_INIT_FUNC_TRACE();
 713
 714         dev->dev_ops = &i40e_eth_dev_ops;
 715         dev->rx_pkt_burst = i40e_recv_pkts;
 716         dev->tx_pkt_burst = i40e_xmit_pkts;
 717
 718         /* for secondary processes, we don't initialise any further as primary
 719          * has already done this work. Only check we don't need a different
 720          * RX function */
 721         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 722                 i40e_set_rx_function(dev);
 723                 i40e_set_tx_function(dev);
 724                 return 0;
 725         }
 726         pci_dev = dev->pci_dev;
 727
 728         rte_eth_copy_pci_info(dev, pci_dev);
 729
 730         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 731         pf->adapter->eth_dev = dev;
 732         pf->dev_data = dev->data;
 733
 734         hw->back = I40E_PF_TO_ADAPTER(pf);
 735         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 736         if (!hw->hw_addr) {
 737                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 738                              "as address is NULL");
 739                 return -ENODEV;
 740         }
 741
 742         hw->vendor_id = pci_dev->id.vendor_id;
 743         hw->device_id = pci_dev->id.device_id;
 744         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 745         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 746         hw->bus.device = pci_dev->addr.devid;
 747         hw->bus.func = pci_dev->addr.function;
 748         hw->adapter_stopped = 0;
 749
 750         /* Make sure all is clean before doing PF reset */
 751         i40e_clear_hw(hw);
 752
 753         /* Initialize the hardware */
 754         i40e_hw_init(hw);
 755
 756         /* Reset here to make sure all is clean for each PF */
 757         ret = i40e_pf_reset(hw);
 758         if (ret) {
 759                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 760                 return ret;
 761         }
 762
 763         /* Initialize the shared code (base driver) */
 764         ret = i40e_init_shared_code(hw);
 765         if (ret) {
 766                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 767                 return ret;
 768         }
 769
 770         /*
 771          * To work around the NVM issue,initialize registers
 772          * for flexible payload by software.
 773          * It should be removed once issues are fixed in NVM.
 774          */
 775         i40e_flex_payload_reg_init(hw);
 776
 777         /* Initialize the parameters for adminq */
 778         i40e_init_adminq_parameter(hw);
 779         ret = i40e_init_adminq(hw);
 780         if (ret != I40E_SUCCESS) {
 781                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 782                 return -EIO;
 783         }
 784         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 785                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 786                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 787                      ((hw->nvm.version >> 12) & 0xf),
 788                      ((hw->nvm.version >> 4) & 0xff),
 789                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 790
 791         /* Clear PXE mode */
 792         i40e_clear_pxe_mode(hw);
 793
 794         /*
 795          * On X710, performance number is far from the expectation on recent
 796          * firmware versions. The fix for this issue may not be integrated in
 797          * the following firmware version. So the workaround in software driver
 798          * is needed. It needs to modify the initial values of 3 internal only
 799          * registers. Note that the workaround can be removed when it is fixed
 800          * in firmware in the future.
 801          */
 802         i40e_configure_registers(hw);
 803
 804         /* Get hw capabilities */
 805         ret = i40e_get_cap(hw);
 806         if (ret != I40E_SUCCESS) {
 807                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 808                 goto err_get_capabilities;
 809         }
 810
 811         /* Initialize parameters for PF */
 812         ret = i40e_pf_parameter_init(dev);
 813         if (ret != 0) {
 814                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 815                 goto err_parameter_init;
 816         }
 817
 818         /* Initialize the queue management */
 819         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 820         if (ret < 0) {
 821                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 822                 goto err_qp_pool_init;
 823         }
 824         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 825                                 hw->func_caps.num_msix_vectors - 1);
 826         if (ret < 0) {
 827                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 828                 goto err_msix_pool_init;
 829         }
 830
 831         /* Initialize lan hmc */
 832         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 833                                 hw->func_caps.num_rx_qp, 0, 0);
 834         if (ret != I40E_SUCCESS) {
 835                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 836                 goto err_init_lan_hmc;
 837         }
 838
 839         /* Configure lan hmc */
 840         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 841         if (ret != I40E_SUCCESS) {
 842                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 843                 goto err_configure_lan_hmc;
 844         }
 845
 846         /* Get and check the mac address */
 847         i40e_get_mac_addr(hw, hw->mac.addr);
 848         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 849                 PMD_INIT_LOG(ERR, "mac address is not valid");
 850                 ret = -EIO;
 851                 goto err_get_mac_addr;
 852         }
 853         /* Copy the permanent MAC address */
 854         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 855                         (struct ether_addr *) hw->mac.perm_addr);
 856
 857         /* Disable flow control */
 858         hw->fc.requested_mode = I40E_FC_NONE;
 859         i40e_set_fc(hw, &aq_fail, TRUE);
 860
 861         /* PF setup, which includes VSI setup */
 862         ret = i40e_pf_setup(pf);
 863         if (ret) {
 864                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 865                 goto err_setup_pf_switch;
 866         }
 867
 868         vsi = pf->main_vsi;
 869
 870         /* Disable double vlan by default */
 871         i40e_vsi_config_double_vlan(vsi, FALSE);
 872
 873         if (!vsi->max_macaddrs)
 874                 len = ETHER_ADDR_LEN;
 875         else
 876                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 877
 878         /* Should be after VSI initialized */
 879         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 880         if (!dev->data->mac_addrs) {
 881                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 882                                         "for storing mac address");
 883                 goto err_mac_alloc;
 884         }
 885         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 886                                         &dev->data->mac_addrs[0]);
 887
 888         /* initialize pf host driver to setup SRIOV resource if applicable */
 889         i40e_pf_host_init(dev);
 890
 891         /* register callback func to eal lib */
 892         rte_intr_callback_register(&(pci_dev->intr_handle),
 893                 i40e_dev_interrupt_handler, (void *)dev);
 894
 895         /* configure and enable device interrupt */
 896         i40e_pf_config_irq0(hw, TRUE);
 897         i40e_pf_enable_irq0(hw);
 898
 899         /* enable uio intr after callback register */
 900         rte_intr_enable(&(pci_dev->intr_handle));
 901         /*
 902          * Add an ethertype filter to drop all flow control frames transmitted
 903          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 904          * frames to wire.
 905          */
 906         i40e_add_tx_flow_control_drop_filter(pf);
 907
 908         /* initialize mirror rule list */
 909         TAILQ_INIT(&pf->mirror_list);
 910
 911         /* Init dcb to sw mode by default */
 912         ret = i40e_dcb_init_configure(dev, TRUE);
 913         if (ret != I40E_SUCCESS) {
 914                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
 915                 pf->flags &= ~I40E_FLAG_DCB;
 916         }
 917
 918         return 0;
 919
 920 err_mac_alloc:
 921         i40e_vsi_release(pf->main_vsi);
 922 err_setup_pf_switch:
 923 err_get_mac_addr:
 924 err_configure_lan_hmc:
 925         (void)i40e_shutdown_lan_hmc(hw);
 926 err_init_lan_hmc:
 927         i40e_res_pool_destroy(&pf->msix_pool);
 928 err_msix_pool_init:
 929         i40e_res_pool_destroy(&pf->qp_pool);
 930 err_qp_pool_init:
 931 err_parameter_init:
 932 err_get_capabilities:
 933         (void)i40e_shutdown_adminq(hw);
 934
 935         return ret;
 936 }
 937
 938 static int
 939 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct i40e_hw *hw;
 943         struct i40e_filter_control_settings settings;
 944         int ret;
 945         uint8_t aq_fail = 0;
 946
 947         PMD_INIT_FUNC_TRACE();
 948
 949         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 950                 return 0;
 951
 952         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 953         pci_dev = dev->pci_dev;
 954
 955         if (hw->adapter_stopped == 0)
 956                 i40e_dev_close(dev);
 957
 958         dev->dev_ops = NULL;
 959         dev->rx_pkt_burst = NULL;
 960         dev->tx_pkt_burst = NULL;
 961
 962         /* Disable LLDP */
 963         ret = i40e_aq_stop_lldp(hw, true, NULL);
 964         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 965                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 966
 967         /* Clear PXE mode */
 968         i40e_clear_pxe_mode(hw);
 969
 970         /* Unconfigure filter control */
 971         memset(&settings, 0, sizeof(settings));
 972         ret = i40e_set_filter_control(hw, &settings);
 973         if (ret)
 974                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 975                                         ret);
 976
 977         /* Disable flow control */
 978         hw->fc.requested_mode = I40E_FC_NONE;
 979         i40e_set_fc(hw, &aq_fail, TRUE);
 980
 981         /* uninitialize pf host driver */
 982         i40e_pf_host_uninit(dev);
 983
 984         rte_free(dev->data->mac_addrs);
 985         dev->data->mac_addrs = NULL;
 986
 987         /* disable uio intr before callback unregister */
 988         rte_intr_disable(&(pci_dev->intr_handle));
 989
 990         /* register callback func to eal lib */
 991         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 992                 i40e_dev_interrupt_handler, (void *)dev);
 993
 994         return 0;
 995 }
 996
 997 static int
 998 i40e_dev_configure(struct rte_eth_dev *dev)
 999 {
1000         struct i40e_adapter *ad =
1001                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1004         int i, ret;
1005
1006         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1007          * bulk allocation or vector Rx preconditions we will reset it.
1008          */
1009         ad->rx_bulk_alloc_allowed = true;
1010         ad->rx_vec_allowed = true;
1011         ad->tx_simple_allowed = true;
1012         ad->tx_vec_allowed = true;
1013
1014         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1015                 ret = i40e_fdir_setup(pf);
1016                 if (ret != I40E_SUCCESS) {
1017                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1018                         return -ENOTSUP;
1019                 }
1020                 ret = i40e_fdir_configure(dev);
1021                 if (ret < 0) {
1022                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1023                         goto err;
1024                 }
1025         } else
1026                 i40e_fdir_teardown(pf);
1027
1028         ret = i40e_dev_init_vlan(dev);
1029         if (ret < 0)
1030                 goto err;
1031
1032         /* VMDQ setup.
1033          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1034          *  RSS setting have different requirements.
1035          *  General PMD driver call sequence are NIC init, configure,
1036          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1037          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1038          *  applicable. So, VMDQ setting has to be done before
1039          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1040          *  For RSS setting, it will try to calculate actual configured RX queue
1041          *  number, which will be available after rx_queue_setup(). dev_start()
1042          *  function is good to place RSS setup.
1043          */
1044         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1045                 ret = i40e_vmdq_setup(dev);
1046                 if (ret)
1047                         goto err;
1048         }
1049
1050         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1051                 ret = i40e_dcb_setup(dev);
1052                 if (ret) {
1053                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1054                         goto err_dcb;
1055                 }
1056         }
1057
1058         return 0;
1059
1060 err_dcb:
1061         /* need to release vmdq resource if exists */
1062         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1063                 i40e_vsi_release(pf->vmdq[i].vsi);
1064                 pf->vmdq[i].vsi = NULL;
1065         }
1066         rte_free(pf->vmdq);
1067         pf->vmdq = NULL;
1068 err:
1069         /* need to release fdir resource if exists */
1070         i40e_fdir_teardown(pf);
1071         return ret;
1072 }
1073
1074 void
1075 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1076 {
1077         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1078         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1080         uint16_t msix_vect = vsi->msix_intr;
1081         uint16_t i;
1082
1083         for (i = 0; i < vsi->nb_qps; i++) {
1084                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1085                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1086                 rte_wmb();
1087         }
1088
1089         if (vsi->type != I40E_VSI_SRIOV) {
1090                 if (!rte_intr_allow_others(intr_handle)) {
1091                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1092                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1093                         I40E_WRITE_REG(hw,
1094                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1095                                        0);
1096                 } else {
1097                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1098                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1099                         I40E_WRITE_REG(hw,
1100                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1101                                                        msix_vect - 1), 0);
1102                 }
1103         } else {
1104                 uint32_t reg;
1105                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1106                         vsi->user_param + (msix_vect - 1);
1107
1108                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1109                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1110         }
1111         I40E_WRITE_FLUSH(hw);
1112 }
1113
1114 static void
1115 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1116                        int base_queue, int nb_queue)
1117 {
1118         int i;
1119         uint32_t val;
1120         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1121
1122         /* Bind all RX queues to allocated MSIX interrupt */
1123         for (i = 0; i < nb_queue; i++) {
1124                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1125                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1126                         ((base_queue + i + 1) <<
1127                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1128                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1129                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1130
1131                 if (i == nb_queue - 1)
1132                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1133                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1134         }
1135
1136         /* Write first RX queue to Link list register as the head element */
1137         if (vsi->type != I40E_VSI_SRIOV) {
1138                 uint16_t interval =
1139                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1140
1141                 if (msix_vect == I40E_MISC_VEC_ID) {
1142                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1143                                        (base_queue <<
1144                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1145                                        (0x0 <<
1146                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1147                         I40E_WRITE_REG(hw,
1148                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1149                                        interval);
1150                 } else {
1151                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1152                                        (base_queue <<
1153                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1154                                        (0x0 <<
1155                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1156                         I40E_WRITE_REG(hw,
1157                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1158                                                        msix_vect - 1),
1159                                        interval);
1160                 }
1161         } else {
1162                 uint32_t reg;
1163
1164                 if (msix_vect == I40E_MISC_VEC_ID) {
1165                         I40E_WRITE_REG(hw,
1166                                        I40E_VPINT_LNKLST0(vsi->user_param),
1167                                        (base_queue <<
1168                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1169                                        (0x0 <<
1170                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1171                 } else {
1172                         /* num_msix_vectors_vf needs to minus irq0 */
1173                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1174                                 vsi->user_param + (msix_vect - 1);
1175
1176                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1177                                        (base_queue <<
1178                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1179                                        (0x0 <<
1180                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1181                 }
1182         }
1183
1184         I40E_WRITE_FLUSH(hw);
1185 }
1186
1187 void
1188 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1189 {
1190         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1191         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1192         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1193         uint16_t msix_vect = vsi->msix_intr;
1194         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1195         uint16_t queue_idx = 0;
1196         int record = 0;
1197         uint32_t val;
1198         int i;
1199
1200         for (i = 0; i < vsi->nb_qps; i++) {
1201                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1202                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1203         }
1204
1205         /* INTENA flag is not auto-cleared for interrupt */
1206         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1207         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1208                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1209                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1210         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1211
1212         /* VF bind interrupt */
1213         if (vsi->type == I40E_VSI_SRIOV) {
1214                 __vsi_queues_bind_intr(vsi, msix_vect,
1215                                        vsi->base_queue, vsi->nb_qps);
1216                 return;
1217         }
1218
1219         /* PF & VMDq bind interrupt */
1220         if (rte_intr_dp_is_en(intr_handle)) {
1221                 if (vsi->type == I40E_VSI_MAIN) {
1222                         queue_idx = 0;
1223                         record = 1;
1224                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1225                         struct i40e_vsi *main_vsi =
1226                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1227                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1228                         record = 1;
1229                 }
1230         }
1231
1232         for (i = 0; i < vsi->nb_used_qps; i++) {
1233                 if (nb_msix <= 1) {
1234                         if (!rte_intr_allow_others(intr_handle))
1235                                 /* allow to share MISC_VEC_ID */
1236                                 msix_vect = I40E_MISC_VEC_ID;
1237
1238                         /* no enough msix_vect, map all to one */
1239                         __vsi_queues_bind_intr(vsi, msix_vect,
1240                                                vsi->base_queue + i,
1241                                                vsi->nb_used_qps - i);
1242                         for (; !!record && i < vsi->nb_used_qps; i++)
1243                                 intr_handle->intr_vec[queue_idx + i] =
1244                                         msix_vect;
1245                         break;
1246                 }
1247                 /* 1:1 queue/msix_vect mapping */
1248                 __vsi_queues_bind_intr(vsi, msix_vect,
1249                                        vsi->base_queue + i, 1);
1250                 if (!!record)
1251                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1252
1253                 msix_vect++;
1254                 nb_msix--;
1255         }
1256 }
1257
1258 static void
1259 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1260 {
1261         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1262         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1263         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1264         uint16_t interval = i40e_calc_itr_interval(\
1265                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1266         uint16_t msix_intr, i;
1267
1268         if (rte_intr_allow_others(intr_handle))
1269                 for (i = 0; i < vsi->nb_msix; i++) {
1270                         msix_intr = vsi->msix_intr + i;
1271                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1272                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1273                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1274                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1275                                 (interval <<
1276                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1277                 }
1278         else
1279                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1280                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1281                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1282                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1283                                (interval <<
1284                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1285
1286         I40E_WRITE_FLUSH(hw);
1287 }
1288
1289 static void
1290 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1291 {
1292         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1293         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1294         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1295         uint16_t msix_intr, i;
1296
1297         if (rte_intr_allow_others(intr_handle))
1298                 for (i = 0; i < vsi->nb_msix; i++) {
1299                         msix_intr = vsi->msix_intr + i;
1300                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1301                                        0);
1302                 }
1303         else
1304                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1305
1306         I40E_WRITE_FLUSH(hw);
1307 }
1308
1309 static inline uint8_t
1310 i40e_parse_link_speed(uint16_t eth_link_speed)
1311 {
1312         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1313
1314         switch (eth_link_speed) {
1315         case ETH_LINK_SPEED_40G:
1316                 link_speed = I40E_LINK_SPEED_40GB;
1317                 break;
1318         case ETH_LINK_SPEED_20G:
1319                 link_speed = I40E_LINK_SPEED_20GB;
1320                 break;
1321         case ETH_LINK_SPEED_10G:
1322                 link_speed = I40E_LINK_SPEED_10GB;
1323                 break;
1324         case ETH_LINK_SPEED_1000:
1325                 link_speed = I40E_LINK_SPEED_1GB;
1326                 break;
1327         case ETH_LINK_SPEED_100:
1328                 link_speed = I40E_LINK_SPEED_100MB;
1329                 break;
1330         }
1331
1332         return link_speed;
1333 }
1334
1335 static int
1336 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1337 {
1338         enum i40e_status_code status;
1339         struct i40e_aq_get_phy_abilities_resp phy_ab;
1340         struct i40e_aq_set_phy_config phy_conf;
1341         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1342                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1343                         I40E_AQ_PHY_FLAG_LOW_POWER;
1344         const uint8_t advt = I40E_LINK_SPEED_40GB |
1345                         I40E_LINK_SPEED_10GB |
1346                         I40E_LINK_SPEED_1GB |
1347                         I40E_LINK_SPEED_100MB;
1348         int ret = -ENOTSUP;
1349
1350         /* Skip it on 40G interfaces, as a workaround for the link issue */
1351         if (i40e_is_40G_device(hw->device_id))
1352                 return I40E_SUCCESS;
1353
1354         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1355                                               NULL);
1356         if (status)
1357                 return ret;
1358
1359         memset(&phy_conf, 0, sizeof(phy_conf));
1360
1361         /* bits 0-2 use the values from get_phy_abilities_resp */
1362         abilities &= ~mask;
1363         abilities |= phy_ab.abilities & mask;
1364
1365         /* update ablities and speed */
1366         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1367                 phy_conf.link_speed = advt;
1368         else
1369                 phy_conf.link_speed = force_speed;
1370
1371         phy_conf.abilities = abilities;
1372
1373         /* use get_phy_abilities_resp value for the rest */
1374         phy_conf.phy_type = phy_ab.phy_type;
1375         phy_conf.eee_capability = phy_ab.eee_capability;
1376         phy_conf.eeer = phy_ab.eeer_val;
1377         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1378
1379         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1380                     phy_ab.abilities, phy_ab.link_speed);
1381         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1382                     phy_conf.abilities, phy_conf.link_speed);
1383
1384         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1385         if (status)
1386                 return ret;
1387
1388         return I40E_SUCCESS;
1389 }
1390
1391 static int
1392 i40e_apply_link_speed(struct rte_eth_dev *dev)
1393 {
1394         uint8_t speed;
1395         uint8_t abilities = 0;
1396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397         struct rte_eth_conf *conf = &dev->data->dev_conf;
1398
1399         speed = i40e_parse_link_speed(conf->link_speed);
1400         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1401         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1402                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1403         else
1404                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1405
1406         return i40e_phy_conf_link(hw, abilities, speed);
1407 }
1408
1409 static int
1410 i40e_dev_start(struct rte_eth_dev *dev)
1411 {
1412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1413         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1414         struct i40e_vsi *main_vsi = pf->main_vsi;
1415         int ret, i;
1416         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1417         uint32_t intr_vector = 0;
1418
1419         hw->adapter_stopped = 0;
1420
1421         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1422                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1423                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1424                              dev->data->dev_conf.link_duplex,
1425                              dev->data->port_id);
1426                 return -EINVAL;
1427         }
1428
1429         rte_intr_disable(intr_handle);
1430
1431         if ((rte_intr_cap_multiple(intr_handle) ||
1432              !RTE_ETH_DEV_SRIOV(dev).active) &&
1433             dev->data->dev_conf.intr_conf.rxq != 0) {
1434                 intr_vector = dev->data->nb_rx_queues;
1435                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1436                         return -1;
1437         }
1438
1439         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1440                 intr_handle->intr_vec =
1441                         rte_zmalloc("intr_vec",
1442                                     dev->data->nb_rx_queues * sizeof(int),
1443                                     0);
1444                 if (!intr_handle->intr_vec) {
1445                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1446                                      " intr_vec\n", dev->data->nb_rx_queues);
1447                         return -ENOMEM;
1448                 }
1449         }
1450
1451         /* Initialize VSI */
1452         ret = i40e_dev_rxtx_init(pf);
1453         if (ret != I40E_SUCCESS) {
1454                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1455                 goto err_up;
1456         }
1457
1458         /* Map queues with MSIX interrupt */
1459         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1460                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1461         i40e_vsi_queues_bind_intr(main_vsi);
1462         i40e_vsi_enable_queues_intr(main_vsi);
1463
1464         /* Map VMDQ VSI queues with MSIX interrupt */
1465         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1466                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1467                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1468                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1469         }
1470
1471         /* enable FDIR MSIX interrupt */
1472         if (pf->fdir.fdir_vsi) {
1473                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1474                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1475         }
1476
1477         /* Enable all queues which have been configured */
1478         ret = i40e_dev_switch_queues(pf, TRUE);
1479         if (ret != I40E_SUCCESS) {
1480                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1481                 goto err_up;
1482         }
1483
1484         /* Enable receiving broadcast packets */
1485         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1486         if (ret != I40E_SUCCESS)
1487                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1488
1489         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1490                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1491                                                 true, NULL);
1492                 if (ret != I40E_SUCCESS)
1493                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1494         }
1495
1496         /* Apply link configure */
1497         ret = i40e_apply_link_speed(dev);
1498         if (I40E_SUCCESS != ret) {
1499                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1500                 goto err_up;
1501         }
1502
1503         if (!rte_intr_allow_others(intr_handle)) {
1504                 rte_intr_callback_unregister(intr_handle,
1505                                              i40e_dev_interrupt_handler,
1506                                              (void *)dev);
1507                 /* configure and enable device interrupt */
1508                 i40e_pf_config_irq0(hw, FALSE);
1509                 i40e_pf_enable_irq0(hw);
1510
1511                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1512                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1513                                      " no intr multiplex\n");
1514         }
1515
1516         /* enable uio intr after callback register */
1517         rte_intr_enable(intr_handle);
1518
1519         return I40E_SUCCESS;
1520
1521 err_up:
1522         i40e_dev_switch_queues(pf, FALSE);
1523         i40e_dev_clear_queues(dev);
1524
1525         return ret;
1526 }
1527
1528 static void
1529 i40e_dev_stop(struct rte_eth_dev *dev)
1530 {
1531         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1532         struct i40e_vsi *main_vsi = pf->main_vsi;
1533         struct i40e_mirror_rule *p_mirror;
1534         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1535         int i;
1536
1537         /* Disable all queues */
1538         i40e_dev_switch_queues(pf, FALSE);
1539
1540         /* un-map queues with interrupt registers */
1541         i40e_vsi_disable_queues_intr(main_vsi);
1542         i40e_vsi_queues_unbind_intr(main_vsi);
1543
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1546                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1547         }
1548
1549         if (pf->fdir.fdir_vsi) {
1550                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1551                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1552         }
1553         /* Clear all queues and release memory */
1554         i40e_dev_clear_queues(dev);
1555
1556         /* Set link down */
1557         i40e_dev_set_link_down(dev);
1558
1559         /* Remove all mirror rules */
1560         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1561                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1562                 rte_free(p_mirror);
1563         }
1564         pf->nb_mirror_rule = 0;
1565
1566         if (!rte_intr_allow_others(intr_handle))
1567                 /* resume to the default handler */
1568                 rte_intr_callback_register(intr_handle,
1569                                            i40e_dev_interrupt_handler,
1570                                            (void *)dev);
1571
1572         /* Clean datapath event and queue/vec mapping */
1573         rte_intr_efd_disable(intr_handle);
1574         if (intr_handle->intr_vec) {
1575                 rte_free(intr_handle->intr_vec);
1576                 intr_handle->intr_vec = NULL;
1577         }
1578 }
1579
1580 static void
1581 i40e_dev_close(struct rte_eth_dev *dev)
1582 {
1583         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1585         uint32_t reg;
1586         int i;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         i40e_dev_stop(dev);
1591         hw->adapter_stopped = 1;
1592         i40e_dev_free_queues(dev);
1593
1594         /* Disable interrupt */
1595         i40e_pf_disable_irq0(hw);
1596         rte_intr_disable(&(dev->pci_dev->intr_handle));
1597
1598         /* shutdown and destroy the HMC */
1599         i40e_shutdown_lan_hmc(hw);
1600
1601         /* release all the existing VSIs and VEBs */
1602         i40e_fdir_teardown(pf);
1603         i40e_vsi_release(pf->main_vsi);
1604
1605         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1606                 i40e_vsi_release(pf->vmdq[i].vsi);
1607                 pf->vmdq[i].vsi = NULL;
1608         }
1609
1610         rte_free(pf->vmdq);
1611         pf->vmdq = NULL;
1612
1613         /* shutdown the adminq */
1614         i40e_aq_queue_shutdown(hw, true);
1615         i40e_shutdown_adminq(hw);
1616
1617         i40e_res_pool_destroy(&pf->qp_pool);
1618         i40e_res_pool_destroy(&pf->msix_pool);
1619
1620         /* force a PF reset to clean anything leftover */
1621         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1622         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1623                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1624         I40E_WRITE_FLUSH(hw);
1625 }
1626
1627 static void
1628 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1629 {
1630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632         struct i40e_vsi *vsi = pf->main_vsi;
1633         int status;
1634
1635         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1636                                                         true, NULL);
1637         if (status != I40E_SUCCESS)
1638                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1639
1640         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1641                                                         TRUE, NULL);
1642         if (status != I40E_SUCCESS)
1643                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1644
1645 }
1646
1647 static void
1648 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1649 {
1650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1651         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1652         struct i40e_vsi *vsi = pf->main_vsi;
1653         int status;
1654
1655         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1656                                                         false, NULL);
1657         if (status != I40E_SUCCESS)
1658                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1659
1660         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1661                                                         false, NULL);
1662         if (status != I40E_SUCCESS)
1663                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1664 }
1665
1666 static void
1667 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1668 {
1669         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1670         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671         struct i40e_vsi *vsi = pf->main_vsi;
1672         int ret;
1673
1674         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1675         if (ret != I40E_SUCCESS)
1676                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1677 }
1678
1679 static void
1680 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1681 {
1682         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1683         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1684         struct i40e_vsi *vsi = pf->main_vsi;
1685         int ret;
1686
1687         if (dev->data->promiscuous == 1)
1688                 return; /* must remain in all_multicast mode */
1689
1690         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1691                                 vsi->seid, FALSE, NULL);
1692         if (ret != I40E_SUCCESS)
1693                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1694 }
1695
1696 /*
1697  * Set device link up.
1698  */
1699 static int
1700 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1701 {
1702         /* re-apply link speed setting */
1703         return i40e_apply_link_speed(dev);
1704 }
1705
1706 /*
1707  * Set device link down.
1708  */
1709 static int
1710 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1711 {
1712         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1713         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1715
1716         return i40e_phy_conf_link(hw, abilities, speed);
1717 }
1718
1719 int
1720 i40e_dev_link_update(struct rte_eth_dev *dev,
1721                      int wait_to_complete)
1722 {
1723 #define CHECK_INTERVAL 100  /* 100ms */
1724 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726         struct i40e_link_status link_status;
1727         struct rte_eth_link link, old;
1728         int status;
1729         unsigned rep_cnt = MAX_REPEAT_TIME;
1730
1731         memset(&link, 0, sizeof(link));
1732         memset(&old, 0, sizeof(old));
1733         memset(&link_status, 0, sizeof(link_status));
1734         rte_i40e_dev_atomic_read_link_status(dev, &old);
1735
1736         do {
1737                 /* Get link status information from hardware */
1738                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1739                 if (status != I40E_SUCCESS) {
1740                         link.link_speed = ETH_LINK_SPEED_100;
1741                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1742                         PMD_DRV_LOG(ERR, "Failed to get link info");
1743                         goto out;
1744                 }
1745
1746                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1747                 if (!wait_to_complete)
1748                         break;
1749
1750                 rte_delay_ms(CHECK_INTERVAL);
1751         } while (!link.link_status && rep_cnt--);
1752
1753         if (!link.link_status)
1754                 goto out;
1755
1756         /* i40e uses full duplex only */
1757         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1758
1759         /* Parse the link status */
1760         switch (link_status.link_speed) {
1761         case I40E_LINK_SPEED_100MB:
1762                 link.link_speed = ETH_LINK_SPEED_100;
1763                 break;
1764         case I40E_LINK_SPEED_1GB:
1765                 link.link_speed = ETH_LINK_SPEED_1000;
1766                 break;
1767         case I40E_LINK_SPEED_10GB:
1768                 link.link_speed = ETH_LINK_SPEED_10G;
1769                 break;
1770         case I40E_LINK_SPEED_20GB:
1771                 link.link_speed = ETH_LINK_SPEED_20G;
1772                 break;
1773         case I40E_LINK_SPEED_40GB:
1774                 link.link_speed = ETH_LINK_SPEED_40G;
1775                 break;
1776         default:
1777                 link.link_speed = ETH_LINK_SPEED_100;
1778                 break;
1779         }
1780
1781 out:
1782         rte_i40e_dev_atomic_write_link_status(dev, &link);
1783         if (link.link_status == old.link_status)
1784                 return -1;
1785
1786         return 0;
1787 }
1788
1789 /* Get all the statistics of a VSI */
1790 void
1791 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1792 {
1793         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1794         struct i40e_eth_stats *nes = &vsi->eth_stats;
1795         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1796         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1797
1798         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1799                             vsi->offset_loaded, &oes->rx_bytes,
1800                             &nes->rx_bytes);
1801         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1802                             vsi->offset_loaded, &oes->rx_unicast,
1803                             &nes->rx_unicast);
1804         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1805                             vsi->offset_loaded, &oes->rx_multicast,
1806                             &nes->rx_multicast);
1807         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1808                             vsi->offset_loaded, &oes->rx_broadcast,
1809                             &nes->rx_broadcast);
1810         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1811                             &oes->rx_discards, &nes->rx_discards);
1812         /* GLV_REPC not supported */
1813         /* GLV_RMPC not supported */
1814         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1815                             &oes->rx_unknown_protocol,
1816                             &nes->rx_unknown_protocol);
1817         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1818                             vsi->offset_loaded, &oes->tx_bytes,
1819                             &nes->tx_bytes);
1820         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1821                             vsi->offset_loaded, &oes->tx_unicast,
1822                             &nes->tx_unicast);
1823         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1824                             vsi->offset_loaded, &oes->tx_multicast,
1825                             &nes->tx_multicast);
1826         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1827                             vsi->offset_loaded,  &oes->tx_broadcast,
1828                             &nes->tx_broadcast);
1829         /* GLV_TDPC not supported */
1830         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1831                             &oes->tx_errors, &nes->tx_errors);
1832         vsi->offset_loaded = true;
1833
1834         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1835                     vsi->vsi_id);
1836         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1837         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1838         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1839         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1840         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1841         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1842                     nes->rx_unknown_protocol);
1843         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1844         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1845         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1846         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1847         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1848         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1849         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1850                     vsi->vsi_id);
1851 }
1852
1853 static void
1854 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1855 {
1856         unsigned int i;
1857         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1858         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1859         /* Get statistics of struct i40e_eth_stats */
1860         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1861                             I40E_GLPRT_GORCL(hw->port),
1862                             pf->offset_loaded, &os->eth.rx_bytes,
1863                             &ns->eth.rx_bytes);
1864         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1865                             I40E_GLPRT_UPRCL(hw->port),
1866                             pf->offset_loaded, &os->eth.rx_unicast,
1867                             &ns->eth.rx_unicast);
1868         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1869                             I40E_GLPRT_MPRCL(hw->port),
1870                             pf->offset_loaded, &os->eth.rx_multicast,
1871                             &ns->eth.rx_multicast);
1872         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1873                             I40E_GLPRT_BPRCL(hw->port),
1874                             pf->offset_loaded, &os->eth.rx_broadcast,
1875                             &ns->eth.rx_broadcast);
1876         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1877                             pf->offset_loaded, &os->eth.rx_discards,
1878                             &ns->eth.rx_discards);
1879         /* GLPRT_REPC not supported */
1880         /* GLPRT_RMPC not supported */
1881         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1882                             pf->offset_loaded,
1883                             &os->eth.rx_unknown_protocol,
1884                             &ns->eth.rx_unknown_protocol);
1885         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1886                             I40E_GLPRT_GOTCL(hw->port),
1887                             pf->offset_loaded, &os->eth.tx_bytes,
1888                             &ns->eth.tx_bytes);
1889         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1890                             I40E_GLPRT_UPTCL(hw->port),
1891                             pf->offset_loaded, &os->eth.tx_unicast,
1892                             &ns->eth.tx_unicast);
1893         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1894                             I40E_GLPRT_MPTCL(hw->port),
1895                             pf->offset_loaded, &os->eth.tx_multicast,
1896                             &ns->eth.tx_multicast);
1897         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1898                             I40E_GLPRT_BPTCL(hw->port),
1899                             pf->offset_loaded, &os->eth.tx_broadcast,
1900                             &ns->eth.tx_broadcast);
1901         /* GLPRT_TEPC not supported */
1902
1903         /* additional port specific stats */
1904         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1905                             pf->offset_loaded, &os->tx_dropped_link_down,
1906                             &ns->tx_dropped_link_down);
1907         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1908                             pf->offset_loaded, &os->crc_errors,
1909                             &ns->crc_errors);
1910         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1911                             pf->offset_loaded, &os->illegal_bytes,
1912                             &ns->illegal_bytes);
1913         /* GLPRT_ERRBC not supported */
1914         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1915                             pf->offset_loaded, &os->mac_local_faults,
1916                             &ns->mac_local_faults);
1917         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1918                             pf->offset_loaded, &os->mac_remote_faults,
1919                             &ns->mac_remote_faults);
1920         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1921                             pf->offset_loaded, &os->rx_length_errors,
1922                             &ns->rx_length_errors);
1923         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1924                             pf->offset_loaded, &os->link_xon_rx,
1925                             &ns->link_xon_rx);
1926         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1927                             pf->offset_loaded, &os->link_xoff_rx,
1928                             &ns->link_xoff_rx);
1929         for (i = 0; i < 8; i++) {
1930                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1931                                     pf->offset_loaded,
1932                                     &os->priority_xon_rx[i],
1933                                     &ns->priority_xon_rx[i]);
1934                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1935                                     pf->offset_loaded,
1936                                     &os->priority_xoff_rx[i],
1937                                     &ns->priority_xoff_rx[i]);
1938         }
1939         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1940                             pf->offset_loaded, &os->link_xon_tx,
1941                             &ns->link_xon_tx);
1942         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1943                             pf->offset_loaded, &os->link_xoff_tx,
1944                             &ns->link_xoff_tx);
1945         for (i = 0; i < 8; i++) {
1946                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1947                                     pf->offset_loaded,
1948                                     &os->priority_xon_tx[i],
1949                                     &ns->priority_xon_tx[i]);
1950                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1951                                     pf->offset_loaded,
1952                                     &os->priority_xoff_tx[i],
1953                                     &ns->priority_xoff_tx[i]);
1954                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1955                                     pf->offset_loaded,
1956                                     &os->priority_xon_2_xoff[i],
1957                                     &ns->priority_xon_2_xoff[i]);
1958         }
1959         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1960                             I40E_GLPRT_PRC64L(hw->port),
1961                             pf->offset_loaded, &os->rx_size_64,
1962                             &ns->rx_size_64);
1963         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1964                             I40E_GLPRT_PRC127L(hw->port),
1965                             pf->offset_loaded, &os->rx_size_127,
1966                             &ns->rx_size_127);
1967         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1968                             I40E_GLPRT_PRC255L(hw->port),
1969                             pf->offset_loaded, &os->rx_size_255,
1970                             &ns->rx_size_255);
1971         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1972                             I40E_GLPRT_PRC511L(hw->port),
1973                             pf->offset_loaded, &os->rx_size_511,
1974                             &ns->rx_size_511);
1975         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1976                             I40E_GLPRT_PRC1023L(hw->port),
1977                             pf->offset_loaded, &os->rx_size_1023,
1978                             &ns->rx_size_1023);
1979         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1980                             I40E_GLPRT_PRC1522L(hw->port),
1981                             pf->offset_loaded, &os->rx_size_1522,
1982                             &ns->rx_size_1522);
1983         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1984                             I40E_GLPRT_PRC9522L(hw->port),
1985                             pf->offset_loaded, &os->rx_size_big,
1986                             &ns->rx_size_big);
1987         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1988                             pf->offset_loaded, &os->rx_undersize,
1989                             &ns->rx_undersize);
1990         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1991                             pf->offset_loaded, &os->rx_fragments,
1992                             &ns->rx_fragments);
1993         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1994                             pf->offset_loaded, &os->rx_oversize,
1995                             &ns->rx_oversize);
1996         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1997                             pf->offset_loaded, &os->rx_jabber,
1998                             &ns->rx_jabber);
1999         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2000                             I40E_GLPRT_PTC64L(hw->port),
2001                             pf->offset_loaded, &os->tx_size_64,
2002                             &ns->tx_size_64);
2003         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2004                             I40E_GLPRT_PTC127L(hw->port),
2005                             pf->offset_loaded, &os->tx_size_127,
2006                             &ns->tx_size_127);
2007         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2008                             I40E_GLPRT_PTC255L(hw->port),
2009                             pf->offset_loaded, &os->tx_size_255,
2010                             &ns->tx_size_255);
2011         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2012                             I40E_GLPRT_PTC511L(hw->port),
2013                             pf->offset_loaded, &os->tx_size_511,
2014                             &ns->tx_size_511);
2015         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2016                             I40E_GLPRT_PTC1023L(hw->port),
2017                             pf->offset_loaded, &os->tx_size_1023,
2018                             &ns->tx_size_1023);
2019         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2020                             I40E_GLPRT_PTC1522L(hw->port),
2021                             pf->offset_loaded, &os->tx_size_1522,
2022                             &ns->tx_size_1522);
2023         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2024                             I40E_GLPRT_PTC9522L(hw->port),
2025                             pf->offset_loaded, &os->tx_size_big,
2026                             &ns->tx_size_big);
2027         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2028                            pf->offset_loaded,
2029                            &os->fd_sb_match, &ns->fd_sb_match);
2030         /* GLPRT_MSPDC not supported */
2031         /* GLPRT_XEC not supported */
2032
2033         pf->offset_loaded = true;
2034
2035         if (pf->main_vsi)
2036                 i40e_update_vsi_stats(pf->main_vsi);
2037 }
2038
2039 /* Get all statistics of a port */
2040 static void
2041 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2042 {
2043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2046         unsigned i;
2047
2048         /* call read registers - updates values, now write them to struct */
2049         i40e_read_stats_registers(pf, hw);
2050
2051         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2052                         pf->main_vsi->eth_stats.rx_multicast +
2053                         pf->main_vsi->eth_stats.rx_broadcast -
2054                         pf->main_vsi->eth_stats.rx_discards;
2055         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2056                         pf->main_vsi->eth_stats.tx_multicast +
2057                         pf->main_vsi->eth_stats.tx_broadcast;
2058         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
2059         stats->obytes   = pf->main_vsi->eth_stats.tx_bytes;
2060         stats->oerrors  = ns->eth.tx_errors +
2061                         pf->main_vsi->eth_stats.tx_errors;
2062         stats->imcasts  = pf->main_vsi->eth_stats.rx_multicast;
2063
2064         /* Rx Errors */
2065         stats->imissed  = ns->eth.rx_discards +
2066                         pf->main_vsi->eth_stats.rx_discards;
2067         stats->ierrors  = ns->crc_errors +
2068                         ns->rx_length_errors + ns->rx_undersize +
2069                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2070                         stats->imissed;
2071
2072         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2073         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2074         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2075         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2076         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2077         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2078         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2079                     ns->eth.rx_unknown_protocol);
2080         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2081         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2082         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2083         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2084         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2085         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2086
2087         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2088                     ns->tx_dropped_link_down);
2089         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2090         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2091                     ns->illegal_bytes);
2092         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2093         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2094                     ns->mac_local_faults);
2095         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2096                     ns->mac_remote_faults);
2097         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2098                     ns->rx_length_errors);
2099         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2100         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2101         for (i = 0; i < 8; i++) {
2102                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2103                                 i, ns->priority_xon_rx[i]);
2104                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2105                                 i, ns->priority_xoff_rx[i]);
2106         }
2107         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2108         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2109         for (i = 0; i < 8; i++) {
2110                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2111                                 i, ns->priority_xon_tx[i]);
2112                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2113                                 i, ns->priority_xoff_tx[i]);
2114                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2115                                 i, ns->priority_xon_2_xoff[i]);
2116         }
2117         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2118         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2119         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2120         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2121         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2122         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2123         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2124         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2125         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2126         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2127         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2128         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2129         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2130         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2131         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2132         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2133         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2134         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2135         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2136                         ns->mac_short_packet_dropped);
2137         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2138                     ns->checksum_error);
2139         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2140         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2141 }
2142
2143 /* Reset the statistics */
2144 static void
2145 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2146 {
2147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149
2150         /* Mark PF and VSI stats to update the offset, aka "reset" */
2151         pf->offset_loaded = false;
2152         if (pf->main_vsi)
2153                 pf->main_vsi->offset_loaded = false;
2154
2155         /* read the stats, reading current register values into offset */
2156         i40e_read_stats_registers(pf, hw);
2157 }
2158
2159 static uint32_t
2160 i40e_xstats_calc_num(void)
2161 {
2162         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2163                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2164                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2165 }
2166
2167 static int
2168 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2169                     unsigned n)
2170 {
2171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2172         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         unsigned i, count, prio;
2174         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2175
2176         count = i40e_xstats_calc_num();
2177         if (n < count)
2178                 return count;
2179
2180         i40e_read_stats_registers(pf, hw);
2181
2182         if (xstats == NULL)
2183                 return 0;
2184
2185         count = 0;
2186
2187         /* Get stats from i40e_eth_stats struct */
2188         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2189                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2190                          "%s", rte_i40e_stats_strings[i].name);
2191                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2192                         rte_i40e_stats_strings[i].offset);
2193                 count++;
2194         }
2195
2196         /* Get individiual stats from i40e_hw_port struct */
2197         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2198                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2199                          "%s", rte_i40e_hw_port_strings[i].name);
2200                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2201                                 rte_i40e_hw_port_strings[i].offset);
2202                 count++;
2203         }
2204
2205         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2206                 for (prio = 0; prio < 8; prio++) {
2207                         snprintf(xstats[count].name,
2208                                  sizeof(xstats[count].name),
2209                                  "rx_priority%u_%s", prio,
2210                                  rte_i40e_rxq_prio_strings[i].name);
2211                         xstats[count].value =
2212                                 *(uint64_t *)(((char *)hw_stats) +
2213                                 rte_i40e_rxq_prio_strings[i].offset +
2214                                 (sizeof(uint64_t) * prio));
2215                         count++;
2216                 }
2217         }
2218
2219         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2220                 for (prio = 0; prio < 8; prio++) {
2221                         snprintf(xstats[count].name,
2222                                  sizeof(xstats[count].name),
2223                                  "tx_priority%u_%s", prio,
2224                                  rte_i40e_txq_prio_strings[i].name);
2225                         xstats[count].value =
2226                                 *(uint64_t *)(((char *)hw_stats) +
2227                                 rte_i40e_txq_prio_strings[i].offset +
2228                                 (sizeof(uint64_t) * prio));
2229                         count++;
2230                 }
2231         }
2232
2233         return count;
2234 }
2235
2236 static int
2237 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2238                                  __rte_unused uint16_t queue_id,
2239                                  __rte_unused uint8_t stat_idx,
2240                                  __rte_unused uint8_t is_rx)
2241 {
2242         PMD_INIT_FUNC_TRACE();
2243
2244         return -ENOSYS;
2245 }
2246
2247 static void
2248 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2249 {
2250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2251         struct i40e_vsi *vsi = pf->main_vsi;
2252
2253         dev_info->max_rx_queues = vsi->nb_qps;
2254         dev_info->max_tx_queues = vsi->nb_qps;
2255         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2256         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2257         dev_info->max_mac_addrs = vsi->max_macaddrs;
2258         dev_info->max_vfs = dev->pci_dev->max_vfs;
2259         dev_info->rx_offload_capa =
2260                 DEV_RX_OFFLOAD_VLAN_STRIP |
2261                 DEV_RX_OFFLOAD_QINQ_STRIP |
2262                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2263                 DEV_RX_OFFLOAD_UDP_CKSUM |
2264                 DEV_RX_OFFLOAD_TCP_CKSUM;
2265         dev_info->tx_offload_capa =
2266                 DEV_TX_OFFLOAD_VLAN_INSERT |
2267                 DEV_TX_OFFLOAD_QINQ_INSERT |
2268                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2269                 DEV_TX_OFFLOAD_UDP_CKSUM |
2270                 DEV_TX_OFFLOAD_TCP_CKSUM |
2271                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2272                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2273                 DEV_TX_OFFLOAD_TCP_TSO;
2274         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2275                                                 sizeof(uint32_t);
2276         dev_info->reta_size = pf->hash_lut_size;
2277         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2278
2279         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2280                 .rx_thresh = {
2281                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2282                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2283                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2284                 },
2285                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2286                 .rx_drop_en = 0,
2287         };
2288
2289         dev_info->default_txconf = (struct rte_eth_txconf) {
2290                 .tx_thresh = {
2291                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2292                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2293                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2294                 },
2295                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2296                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2297                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2298                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2299         };
2300
2301         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2302                 .nb_max = I40E_MAX_RING_DESC,
2303                 .nb_min = I40E_MIN_RING_DESC,
2304                 .nb_align = I40E_ALIGN_RING_DESC,
2305         };
2306
2307         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2308                 .nb_max = I40E_MAX_RING_DESC,
2309                 .nb_min = I40E_MIN_RING_DESC,
2310                 .nb_align = I40E_ALIGN_RING_DESC,
2311         };
2312
2313         if (pf->flags & I40E_FLAG_VMDQ) {
2314                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2315                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2316                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2317                                                 pf->max_nb_vmdq_vsi;
2318                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2319                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2320                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2321         }
2322 }
2323
2324 static int
2325 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2326 {
2327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2328         struct i40e_vsi *vsi = pf->main_vsi;
2329         PMD_INIT_FUNC_TRACE();
2330
2331         if (on)
2332                 return i40e_vsi_add_vlan(vsi, vlan_id);
2333         else
2334                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2335 }
2336
2337 static void
2338 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2339                    __rte_unused uint16_t tpid)
2340 {
2341         PMD_INIT_FUNC_TRACE();
2342 }
2343
2344 static void
2345 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2346 {
2347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2348         struct i40e_vsi *vsi = pf->main_vsi;
2349
2350         if (mask & ETH_VLAN_STRIP_MASK) {
2351                 /* Enable or disable VLAN stripping */
2352                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2353                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2354                 else
2355                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2356         }
2357
2358         if (mask & ETH_VLAN_EXTEND_MASK) {
2359                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2360                         i40e_vsi_config_double_vlan(vsi, TRUE);
2361                 else
2362                         i40e_vsi_config_double_vlan(vsi, FALSE);
2363         }
2364 }
2365
2366 static void
2367 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2368                           __rte_unused uint16_t queue,
2369                           __rte_unused int on)
2370 {
2371         PMD_INIT_FUNC_TRACE();
2372 }
2373
2374 static int
2375 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2376 {
2377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2378         struct i40e_vsi *vsi = pf->main_vsi;
2379         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2380         struct i40e_vsi_vlan_pvid_info info;
2381
2382         memset(&info, 0, sizeof(info));
2383         info.on = on;
2384         if (info.on)
2385                 info.config.pvid = pvid;
2386         else {
2387                 info.config.reject.tagged =
2388                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2389                 info.config.reject.untagged =
2390                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2391         }
2392
2393         return i40e_vsi_vlan_pvid_set(vsi, &info);
2394 }
2395
2396 static int
2397 i40e_dev_led_on(struct rte_eth_dev *dev)
2398 {
2399         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2400         uint32_t mode = i40e_led_get(hw);
2401
2402         if (mode == 0)
2403                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2404
2405         return 0;
2406 }
2407
2408 static int
2409 i40e_dev_led_off(struct rte_eth_dev *dev)
2410 {
2411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2412         uint32_t mode = i40e_led_get(hw);
2413
2414         if (mode != 0)
2415                 i40e_led_set(hw, 0, false);
2416
2417         return 0;
2418 }
2419
2420 static int
2421 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2422 {
2423         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2425
2426         fc_conf->pause_time = pf->fc_conf.pause_time;
2427         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2428         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2429
2430          /* Return current mode according to actual setting*/
2431         switch (hw->fc.current_mode) {
2432         case I40E_FC_FULL:
2433                 fc_conf->mode = RTE_FC_FULL;
2434                 break;
2435         case I40E_FC_TX_PAUSE:
2436                 fc_conf->mode = RTE_FC_TX_PAUSE;
2437                 break;
2438         case I40E_FC_RX_PAUSE:
2439                 fc_conf->mode = RTE_FC_RX_PAUSE;
2440                 break;
2441         case I40E_FC_NONE:
2442         default:
2443                 fc_conf->mode = RTE_FC_NONE;
2444         };
2445
2446         return 0;
2447 }
2448
2449 static int
2450 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2451 {
2452         uint32_t mflcn_reg, fctrl_reg, reg;
2453         uint32_t max_high_water;
2454         uint8_t i, aq_failure;
2455         int err;
2456         struct i40e_hw *hw;
2457         struct i40e_pf *pf;
2458         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2459                 [RTE_FC_NONE] = I40E_FC_NONE,
2460                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2461                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2462                 [RTE_FC_FULL] = I40E_FC_FULL
2463         };
2464
2465         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2466
2467         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2468         if ((fc_conf->high_water > max_high_water) ||
2469                         (fc_conf->high_water < fc_conf->low_water)) {
2470                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2471                         "High_water must <= %d.", max_high_water);
2472                 return -EINVAL;
2473         }
2474
2475         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2477         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2478
2479         pf->fc_conf.pause_time = fc_conf->pause_time;
2480         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2481         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2482
2483         PMD_INIT_FUNC_TRACE();
2484
2485         /* All the link flow control related enable/disable register
2486          * configuration is handle by the F/W
2487          */
2488         err = i40e_set_fc(hw, &aq_failure, true);
2489         if (err < 0)
2490                 return -ENOSYS;
2491
2492         if (i40e_is_40G_device(hw->device_id)) {
2493                 /* Configure flow control refresh threshold,
2494                  * the value for stat_tx_pause_refresh_timer[8]
2495                  * is used for global pause operation.
2496                  */
2497
2498                 I40E_WRITE_REG(hw,
2499                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2500                                pf->fc_conf.pause_time);
2501
2502                 /* configure the timer value included in transmitted pause
2503                  * frame,
2504                  * the value for stat_tx_pause_quanta[8] is used for global
2505                  * pause operation
2506                  */
2507                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2508                                pf->fc_conf.pause_time);
2509
2510                 fctrl_reg = I40E_READ_REG(hw,
2511                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2512
2513                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2514                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2515                 else
2516                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2517
2518                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2519                                fctrl_reg);
2520         } else {
2521                 /* Configure pause time (2 TCs per register) */
2522                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2523                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2524                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2525
2526                 /* Configure flow control refresh threshold value */
2527                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2528                                pf->fc_conf.pause_time / 2);
2529
2530                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2531
2532                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2533                  *depending on configuration
2534                  */
2535                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2536                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2537                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2538                 } else {
2539                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2540                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2541                 }
2542
2543                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2544         }
2545
2546         /* config the water marker both based on the packets and bytes */
2547         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2548                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2549                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2550         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2551                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2552                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2553         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2554                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2555                        << I40E_KILOSHIFT);
2556         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2557                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2558                        << I40E_KILOSHIFT);
2559
2560         I40E_WRITE_FLUSH(hw);
2561
2562         return 0;
2563 }
2564
2565 static int
2566 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2567                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2568 {
2569         PMD_INIT_FUNC_TRACE();
2570
2571         return -ENOSYS;
2572 }
2573
2574 /* Add a MAC address, and update filters */
2575 static void
2576 i40e_macaddr_add(struct rte_eth_dev *dev,
2577                  struct ether_addr *mac_addr,
2578                  __rte_unused uint32_t index,
2579                  uint32_t pool)
2580 {
2581         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2582         struct i40e_mac_filter_info mac_filter;
2583         struct i40e_vsi *vsi;
2584         int ret;
2585
2586         /* If VMDQ not enabled or configured, return */
2587         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2588                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2589                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2590                         pool);
2591                 return;
2592         }
2593
2594         if (pool > pf->nb_cfg_vmdq_vsi) {
2595                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2596                                 pool, pf->nb_cfg_vmdq_vsi);
2597                 return;
2598         }
2599
2600         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2601         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2602
2603         if (pool == 0)
2604                 vsi = pf->main_vsi;
2605         else
2606                 vsi = pf->vmdq[pool - 1].vsi;
2607
2608         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2609         if (ret != I40E_SUCCESS) {
2610                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2611                 return;
2612         }
2613 }
2614
2615 /* Remove a MAC address, and update filters */
2616 static void
2617 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2618 {
2619         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2620         struct i40e_vsi *vsi;
2621         struct rte_eth_dev_data *data = dev->data;
2622         struct ether_addr *macaddr;
2623         int ret;
2624         uint32_t i;
2625         uint64_t pool_sel;
2626
2627         macaddr = &(data->mac_addrs[index]);
2628
2629         pool_sel = dev->data->mac_pool_sel[index];
2630
2631         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2632                 if (pool_sel & (1ULL << i)) {
2633                         if (i == 0)
2634                                 vsi = pf->main_vsi;
2635                         else {
2636                                 /* No VMDQ pool enabled or configured */
2637                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2638                                         (i > pf->nb_cfg_vmdq_vsi)) {
2639                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2640                                                         "/configured");
2641                                         return;
2642                                 }
2643                                 vsi = pf->vmdq[i - 1].vsi;
2644                         }
2645                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2646
2647                         if (ret) {
2648                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2649                                 return;
2650                         }
2651                 }
2652         }
2653 }
2654
2655 /* Set perfect match or hash match of MAC and VLAN for a VF */
2656 static int
2657 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2658                  struct rte_eth_mac_filter *filter,
2659                  bool add)
2660 {
2661         struct i40e_hw *hw;
2662         struct i40e_mac_filter_info mac_filter;
2663         struct ether_addr old_mac;
2664         struct ether_addr *new_mac;
2665         struct i40e_pf_vf *vf = NULL;
2666         uint16_t vf_id;
2667         int ret;
2668
2669         if (pf == NULL) {
2670                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2671                 return -EINVAL;
2672         }
2673         hw = I40E_PF_TO_HW(pf);
2674
2675         if (filter == NULL) {
2676                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2677                 return -EINVAL;
2678         }
2679
2680         new_mac = &filter->mac_addr;
2681
2682         if (is_zero_ether_addr(new_mac)) {
2683                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2684                 return -EINVAL;
2685         }
2686
2687         vf_id = filter->dst_id;
2688
2689         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2690                 PMD_DRV_LOG(ERR, "Invalid argument.");
2691                 return -EINVAL;
2692         }
2693         vf = &pf->vfs[vf_id];
2694
2695         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2696                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2697                 return -EINVAL;
2698         }
2699
2700         if (add) {
2701                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2702                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2703                                 ETHER_ADDR_LEN);
2704                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2705                                  ETHER_ADDR_LEN);
2706
2707                 mac_filter.filter_type = filter->filter_type;
2708                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2709                 if (ret != I40E_SUCCESS) {
2710                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2711                         return -1;
2712                 }
2713                 ether_addr_copy(new_mac, &pf->dev_addr);
2714         } else {
2715                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2716                                 ETHER_ADDR_LEN);
2717                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2718                 if (ret != I40E_SUCCESS) {
2719                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2720                         return -1;
2721                 }
2722
2723                 /* Clear device address as it has been removed */
2724                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2725                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2726         }
2727
2728         return 0;
2729 }
2730
2731 /* MAC filter handle */
2732 static int
2733 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2734                 void *arg)
2735 {
2736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737         struct rte_eth_mac_filter *filter;
2738         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2739         int ret = I40E_NOT_SUPPORTED;
2740
2741         filter = (struct rte_eth_mac_filter *)(arg);
2742
2743         switch (filter_op) {
2744         case RTE_ETH_FILTER_NOP:
2745                 ret = I40E_SUCCESS;
2746                 break;
2747         case RTE_ETH_FILTER_ADD:
2748                 i40e_pf_disable_irq0(hw);
2749                 if (filter->is_vf)
2750                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2751                 i40e_pf_enable_irq0(hw);
2752                 break;
2753         case RTE_ETH_FILTER_DELETE:
2754                 i40e_pf_disable_irq0(hw);
2755                 if (filter->is_vf)
2756                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2757                 i40e_pf_enable_irq0(hw);
2758                 break;
2759         default:
2760                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2761                 ret = I40E_ERR_PARAM;
2762                 break;
2763         }
2764
2765         return ret;
2766 }
2767
2768 static int
2769 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2770 {
2771         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2772         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2773         int ret;
2774
2775         if (!lut)
2776                 return -EINVAL;
2777
2778         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2779                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2780                                           lut, lut_size);
2781                 if (ret) {
2782                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2783                         return ret;
2784                 }
2785         } else {
2786                 uint32_t *lut_dw = (uint32_t *)lut;
2787                 uint16_t i, lut_size_dw = lut_size / 4;
2788
2789                 for (i = 0; i < lut_size_dw; i++)
2790                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2791         }
2792
2793         return 0;
2794 }
2795
2796 static int
2797 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2798 {
2799         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2800         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2801         int ret;
2802
2803         if (!vsi || !lut)
2804                 return -EINVAL;
2805
2806         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2807                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2808                                           lut, lut_size);
2809                 if (ret) {
2810                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2811                         return ret;
2812                 }
2813         } else {
2814                 uint32_t *lut_dw = (uint32_t *)lut;
2815                 uint16_t i, lut_size_dw = lut_size / 4;
2816
2817                 for (i = 0; i < lut_size_dw; i++)
2818                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2819                 I40E_WRITE_FLUSH(hw);
2820         }
2821
2822         return 0;
2823 }
2824
2825 static int
2826 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2827                          struct rte_eth_rss_reta_entry64 *reta_conf,
2828                          uint16_t reta_size)
2829 {
2830         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2831         uint16_t i, lut_size = pf->hash_lut_size;
2832         uint16_t idx, shift;
2833         uint8_t *lut;
2834         int ret;
2835
2836         if (reta_size != lut_size ||
2837                 reta_size > ETH_RSS_RETA_SIZE_512) {
2838                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2839                         "(%d) doesn't match the number hardware can supported "
2840                                         "(%d)\n", reta_size, lut_size);
2841                 return -EINVAL;
2842         }
2843
2844         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2845         if (!lut) {
2846                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2847                 return -ENOMEM;
2848         }
2849         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2850         if (ret)
2851                 goto out;
2852         for (i = 0; i < reta_size; i++) {
2853                 idx = i / RTE_RETA_GROUP_SIZE;
2854                 shift = i % RTE_RETA_GROUP_SIZE;
2855                 if (reta_conf[idx].mask & (1ULL << shift))
2856                         lut[i] = reta_conf[idx].reta[shift];
2857         }
2858         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2859
2860 out:
2861         rte_free(lut);
2862
2863         return ret;
2864 }
2865
2866 static int
2867 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2868                         struct rte_eth_rss_reta_entry64 *reta_conf,
2869                         uint16_t reta_size)
2870 {
2871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2872         uint16_t i, lut_size = pf->hash_lut_size;
2873         uint16_t idx, shift;
2874         uint8_t *lut;
2875         int ret;
2876
2877         if (reta_size != lut_size ||
2878                 reta_size > ETH_RSS_RETA_SIZE_512) {
2879                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2880                         "(%d) doesn't match the number hardware can supported "
2881                                         "(%d)\n", reta_size, lut_size);
2882                 return -EINVAL;
2883         }
2884
2885         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2886         if (!lut) {
2887                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2888                 return -ENOMEM;
2889         }
2890
2891         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2892         if (ret)
2893                 goto out;
2894         for (i = 0; i < reta_size; i++) {
2895                 idx = i / RTE_RETA_GROUP_SIZE;
2896                 shift = i % RTE_RETA_GROUP_SIZE;
2897                 if (reta_conf[idx].mask & (1ULL << shift))
2898                         reta_conf[idx].reta[shift] = lut[i];
2899         }
2900
2901 out:
2902         rte_free(lut);
2903
2904         return ret;
2905 }
2906
2907 /**
2908  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2909  * @hw:   pointer to the HW structure
2910  * @mem:  pointer to mem struct to fill out
2911  * @size: size of memory requested
2912  * @alignment: what to align the allocation to
2913  **/
2914 enum i40e_status_code
2915 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2916                         struct i40e_dma_mem *mem,
2917                         u64 size,
2918                         u32 alignment)
2919 {
2920         const struct rte_memzone *mz = NULL;
2921         char z_name[RTE_MEMZONE_NAMESIZE];
2922
2923         if (!mem)
2924                 return I40E_ERR_PARAM;
2925
2926         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2927         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2928                                          alignment, RTE_PGSIZE_2M);
2929         if (!mz)
2930                 return I40E_ERR_NO_MEMORY;
2931
2932         mem->size = size;
2933         mem->va = mz->addr;
2934         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2935         mem->zone = (const void *)mz;
2936         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
2937                     "%"PRIu64, mz->name, mem->pa);
2938
2939         return I40E_SUCCESS;
2940 }
2941
2942 /**
2943  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2944  * @hw:   pointer to the HW structure
2945  * @mem:  ptr to mem struct to free
2946  **/
2947 enum i40e_status_code
2948 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2949                     struct i40e_dma_mem *mem)
2950 {
2951         if (!mem)
2952                 return I40E_ERR_PARAM;
2953
2954         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
2955                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
2956                     mem->pa);
2957         rte_memzone_free((const struct rte_memzone *)mem->zone);
2958         mem->zone = NULL;
2959         mem->va = NULL;
2960         mem->pa = (u64)0;
2961
2962         return I40E_SUCCESS;
2963 }
2964
2965 /**
2966  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2967  * @hw:   pointer to the HW structure
2968  * @mem:  pointer to mem struct to fill out
2969  * @size: size of memory requested
2970  **/
2971 enum i40e_status_code
2972 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2973                          struct i40e_virt_mem *mem,
2974                          u32 size)
2975 {
2976         if (!mem)
2977                 return I40E_ERR_PARAM;
2978
2979         mem->size = size;
2980         mem->va = rte_zmalloc("i40e", size, 0);
2981
2982         if (mem->va)
2983                 return I40E_SUCCESS;
2984         else
2985                 return I40E_ERR_NO_MEMORY;
2986 }
2987
2988 /**
2989  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2990  * @hw:   pointer to the HW structure
2991  * @mem:  pointer to mem struct to free
2992  **/
2993 enum i40e_status_code
2994 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2995                      struct i40e_virt_mem *mem)
2996 {
2997         if (!mem)
2998                 return I40E_ERR_PARAM;
2999
3000         rte_free(mem->va);
3001         mem->va = NULL;
3002
3003         return I40E_SUCCESS;
3004 }
3005
3006 void
3007 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3008 {
3009         rte_spinlock_init(&sp->spinlock);
3010 }
3011
3012 void
3013 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3014 {
3015         rte_spinlock_lock(&sp->spinlock);
3016 }
3017
3018 void
3019 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3020 {
3021         rte_spinlock_unlock(&sp->spinlock);
3022 }
3023
3024 void
3025 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3026 {
3027         return;
3028 }
3029
3030 /**
3031  * Get the hardware capabilities, which will be parsed
3032  * and saved into struct i40e_hw.
3033  */
3034 static int
3035 i40e_get_cap(struct i40e_hw *hw)
3036 {
3037         struct i40e_aqc_list_capabilities_element_resp *buf;
3038         uint16_t len, size = 0;
3039         int ret;
3040
3041         /* Calculate a huge enough buff for saving response data temporarily */
3042         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3043                                                 I40E_MAX_CAP_ELE_NUM;
3044         buf = rte_zmalloc("i40e", len, 0);
3045         if (!buf) {
3046                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3047                 return I40E_ERR_NO_MEMORY;
3048         }
3049
3050         /* Get, parse the capabilities and save it to hw */
3051         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3052                         i40e_aqc_opc_list_func_capabilities, NULL);
3053         if (ret != I40E_SUCCESS)
3054                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3055
3056         /* Free the temporary buffer after being used */
3057         rte_free(buf);
3058
3059         return ret;
3060 }
3061
3062 static int
3063 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3064 {
3065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3066         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3067         uint16_t qp_count = 0, vsi_count = 0;
3068
3069         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3070                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3071                 return -EINVAL;
3072         }
3073         /* Add the parameter init for LFC */
3074         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3075         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3076         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3077
3078         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3079         pf->max_num_vsi = hw->func_caps.num_vsis;
3080         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3081         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3082         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3083
3084         /* FDir queue/VSI allocation */
3085         pf->fdir_qp_offset = 0;
3086         if (hw->func_caps.fd) {
3087                 pf->flags |= I40E_FLAG_FDIR;
3088                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3089         } else {
3090                 pf->fdir_nb_qps = 0;
3091         }
3092         qp_count += pf->fdir_nb_qps;
3093         vsi_count += 1;
3094
3095         /* LAN queue/VSI allocation */
3096         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3097         if (!hw->func_caps.rss) {
3098                 pf->lan_nb_qps = 1;
3099         } else {
3100                 pf->flags |= I40E_FLAG_RSS;
3101                 if (hw->mac.type == I40E_MAC_X722)
3102                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3103                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3104         }
3105         qp_count += pf->lan_nb_qps;
3106         vsi_count += 1;
3107
3108         /* VF queue/VSI allocation */
3109         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3110         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3111                 pf->flags |= I40E_FLAG_SRIOV;
3112                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3113                 pf->vf_num = dev->pci_dev->max_vfs;
3114                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3115                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3116                             pf->vf_nb_qps * pf->vf_num);
3117         } else {
3118                 pf->vf_nb_qps = 0;
3119                 pf->vf_num = 0;
3120         }
3121         qp_count += pf->vf_nb_qps * pf->vf_num;
3122         vsi_count += pf->vf_num;
3123
3124         /* VMDq queue/VSI allocation */
3125         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3126         pf->vmdq_nb_qps = 0;
3127         pf->max_nb_vmdq_vsi = 0;
3128         if (hw->func_caps.vmdq) {
3129                 if (qp_count < hw->func_caps.num_tx_qp &&
3130                         vsi_count < hw->func_caps.num_vsis) {
3131                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3132                                 qp_count) / pf->vmdq_nb_qp_max;
3133
3134                         /* Limit the maximum number of VMDq vsi to the maximum
3135                          * ethdev can support
3136                          */
3137                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3138                                 hw->func_caps.num_vsis - vsi_count);
3139                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3140                                 ETH_64_POOLS);
3141                         if (pf->max_nb_vmdq_vsi) {
3142                                 pf->flags |= I40E_FLAG_VMDQ;
3143                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3144                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3145                                             "per VMDQ VSI, in total %u queues",
3146                                             pf->max_nb_vmdq_vsi,
3147                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3148                                             pf->max_nb_vmdq_vsi);
3149                         } else {
3150                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3151                                             "VMDq");
3152                         }
3153                 } else {
3154                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3155                 }
3156         }
3157         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3158         vsi_count += pf->max_nb_vmdq_vsi;
3159
3160         if (hw->func_caps.dcb)
3161                 pf->flags |= I40E_FLAG_DCB;
3162
3163         if (qp_count > hw->func_caps.num_tx_qp) {
3164                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3165                             "the hardware maximum %u", qp_count,
3166                             hw->func_caps.num_tx_qp);
3167                 return -EINVAL;
3168         }
3169         if (vsi_count > hw->func_caps.num_vsis) {
3170                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3171                             "the hardware maximum %u", vsi_count,
3172                             hw->func_caps.num_vsis);
3173                 return -EINVAL;
3174         }
3175
3176         return 0;
3177 }
3178
3179 static int
3180 i40e_pf_get_switch_config(struct i40e_pf *pf)
3181 {
3182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3183         struct i40e_aqc_get_switch_config_resp *switch_config;
3184         struct i40e_aqc_switch_config_element_resp *element;
3185         uint16_t start_seid = 0, num_reported;
3186         int ret;
3187
3188         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3189                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3190         if (!switch_config) {
3191                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3192                 return -ENOMEM;
3193         }
3194
3195         /* Get the switch configurations */
3196         ret = i40e_aq_get_switch_config(hw, switch_config,
3197                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3198         if (ret != I40E_SUCCESS) {
3199                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3200                 goto fail;
3201         }
3202         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3203         if (num_reported != 1) { /* The number should be 1 */
3204                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3205                 goto fail;
3206         }
3207
3208         /* Parse the switch configuration elements */
3209         element = &(switch_config->element[0]);
3210         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3211                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3212                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3213         } else
3214                 PMD_DRV_LOG(INFO, "Unknown element type");
3215
3216 fail:
3217         rte_free(switch_config);
3218
3219         return ret;
3220 }
3221
3222 static int
3223 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3224                         uint32_t num)
3225 {
3226         struct pool_entry *entry;
3227
3228         if (pool == NULL || num == 0)
3229                 return -EINVAL;
3230
3231         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3232         if (entry == NULL) {
3233                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3234                 return -ENOMEM;
3235         }
3236
3237         /* queue heap initialize */
3238         pool->num_free = num;
3239         pool->num_alloc = 0;
3240         pool->base = base;
3241         LIST_INIT(&pool->alloc_list);
3242         LIST_INIT(&pool->free_list);
3243
3244         /* Initialize element  */
3245         entry->base = 0;
3246         entry->len = num;
3247
3248         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3249         return 0;
3250 }
3251
3252 static void
3253 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3254 {
3255         struct pool_entry *entry;
3256
3257         if (pool == NULL)
3258                 return;
3259
3260         LIST_FOREACH(entry, &pool->alloc_list, next) {
3261                 LIST_REMOVE(entry, next);
3262                 rte_free(entry);
3263         }
3264
3265         LIST_FOREACH(entry, &pool->free_list, next) {
3266                 LIST_REMOVE(entry, next);
3267                 rte_free(entry);
3268         }
3269
3270         pool->num_free = 0;
3271         pool->num_alloc = 0;
3272         pool->base = 0;
3273         LIST_INIT(&pool->alloc_list);
3274         LIST_INIT(&pool->free_list);
3275 }
3276
3277 static int
3278 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3279                        uint32_t base)
3280 {
3281         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3282         uint32_t pool_offset;
3283         int insert;
3284
3285         if (pool == NULL) {
3286                 PMD_DRV_LOG(ERR, "Invalid parameter");
3287                 return -EINVAL;
3288         }
3289
3290         pool_offset = base - pool->base;
3291         /* Lookup in alloc list */
3292         LIST_FOREACH(entry, &pool->alloc_list, next) {
3293                 if (entry->base == pool_offset) {
3294                         valid_entry = entry;
3295                         LIST_REMOVE(entry, next);
3296                         break;
3297                 }
3298         }
3299
3300         /* Not find, return */
3301         if (valid_entry == NULL) {
3302                 PMD_DRV_LOG(ERR, "Failed to find entry");
3303                 return -EINVAL;
3304         }
3305
3306         /**
3307          * Found it, move it to free list  and try to merge.
3308          * In order to make merge easier, always sort it by qbase.
3309          * Find adjacent prev and last entries.
3310          */
3311         prev = next = NULL;
3312         LIST_FOREACH(entry, &pool->free_list, next) {
3313                 if (entry->base > valid_entry->base) {
3314                         next = entry;
3315                         break;
3316                 }
3317                 prev = entry;
3318         }
3319
3320         insert = 0;
3321         /* Try to merge with next one*/
3322         if (next != NULL) {
3323                 /* Merge with next one */
3324                 if (valid_entry->base + valid_entry->len == next->base) {
3325                         next->base = valid_entry->base;
3326                         next->len += valid_entry->len;
3327                         rte_free(valid_entry);
3328                         valid_entry = next;
3329                         insert = 1;
3330                 }
3331         }
3332
3333         if (prev != NULL) {
3334                 /* Merge with previous one */
3335                 if (prev->base + prev->len == valid_entry->base) {
3336                         prev->len += valid_entry->len;
3337                         /* If it merge with next one, remove next node */
3338                         if (insert == 1) {
3339                                 LIST_REMOVE(valid_entry, next);
3340                                 rte_free(valid_entry);
3341                         } else {
3342                                 rte_free(valid_entry);
3343                                 insert = 1;
3344                         }
3345                 }
3346         }
3347
3348         /* Not find any entry to merge, insert */
3349         if (insert == 0) {
3350                 if (prev != NULL)
3351                         LIST_INSERT_AFTER(prev, valid_entry, next);
3352                 else if (next != NULL)
3353                         LIST_INSERT_BEFORE(next, valid_entry, next);
3354                 else /* It's empty list, insert to head */
3355                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3356         }
3357
3358         pool->num_free += valid_entry->len;
3359         pool->num_alloc -= valid_entry->len;
3360
3361         return 0;
3362 }
3363
3364 static int
3365 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3366                        uint16_t num)
3367 {
3368         struct pool_entry *entry, *valid_entry;
3369
3370         if (pool == NULL || num == 0) {
3371                 PMD_DRV_LOG(ERR, "Invalid parameter");
3372                 return -EINVAL;
3373         }
3374
3375         if (pool->num_free < num) {
3376                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3377                             num, pool->num_free);
3378                 return -ENOMEM;
3379         }
3380
3381         valid_entry = NULL;
3382         /* Lookup  in free list and find most fit one */
3383         LIST_FOREACH(entry, &pool->free_list, next) {
3384                 if (entry->len >= num) {
3385                         /* Find best one */
3386                         if (entry->len == num) {
3387                                 valid_entry = entry;
3388                                 break;
3389                         }
3390                         if (valid_entry == NULL || valid_entry->len > entry->len)
3391                                 valid_entry = entry;
3392                 }
3393         }
3394
3395         /* Not find one to satisfy the request, return */
3396         if (valid_entry == NULL) {
3397                 PMD_DRV_LOG(ERR, "No valid entry found");
3398                 return -ENOMEM;
3399         }
3400         /**
3401          * The entry have equal queue number as requested,
3402          * remove it from alloc_list.
3403          */
3404         if (valid_entry->len == num) {
3405                 LIST_REMOVE(valid_entry, next);
3406         } else {
3407                 /**
3408                  * The entry have more numbers than requested,
3409                  * create a new entry for alloc_list and minus its
3410                  * queue base and number in free_list.
3411                  */
3412                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3413                 if (entry == NULL) {
3414                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3415                                     "resource pool");
3416                         return -ENOMEM;
3417                 }
3418                 entry->base = valid_entry->base;
3419                 entry->len = num;
3420                 valid_entry->base += num;
3421                 valid_entry->len -= num;
3422                 valid_entry = entry;
3423         }
3424
3425         /* Insert it into alloc list, not sorted */
3426         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3427
3428         pool->num_free -= valid_entry->len;
3429         pool->num_alloc += valid_entry->len;
3430
3431         return (valid_entry->base + pool->base);
3432 }
3433
3434 /**
3435  * bitmap_is_subset - Check whether src2 is subset of src1
3436  **/
3437 static inline int
3438 bitmap_is_subset(uint8_t src1, uint8_t src2)
3439 {
3440         return !((src1 ^ src2) & src2);
3441 }
3442
3443 static enum i40e_status_code
3444 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3445 {
3446         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3447
3448         /* If DCB is not supported, only default TC is supported */
3449         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3450                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3451                 return I40E_NOT_SUPPORTED;
3452         }
3453
3454         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3455                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3456                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3457                             enabled_tcmap);
3458                 return I40E_NOT_SUPPORTED;
3459         }
3460         return I40E_SUCCESS;
3461 }
3462
3463 int
3464 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3465                                 struct i40e_vsi_vlan_pvid_info *info)
3466 {
3467         struct i40e_hw *hw;
3468         struct i40e_vsi_context ctxt;
3469         uint8_t vlan_flags = 0;
3470         int ret;
3471
3472         if (vsi == NULL || info == NULL) {
3473                 PMD_DRV_LOG(ERR, "invalid parameters");
3474                 return I40E_ERR_PARAM;
3475         }
3476
3477         if (info->on) {
3478                 vsi->info.pvid = info->config.pvid;
3479                 /**
3480                  * If insert pvid is enabled, only tagged pkts are
3481                  * allowed to be sent out.
3482                  */
3483                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3484                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3485         } else {
3486                 vsi->info.pvid = 0;
3487                 if (info->config.reject.tagged == 0)
3488                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3489
3490                 if (info->config.reject.untagged == 0)
3491                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3492         }
3493         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3494                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3495         vsi->info.port_vlan_flags |= vlan_flags;
3496         vsi->info.valid_sections =
3497                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3498         memset(&ctxt, 0, sizeof(ctxt));
3499         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3500         ctxt.seid = vsi->seid;
3501
3502         hw = I40E_VSI_TO_HW(vsi);
3503         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3504         if (ret != I40E_SUCCESS)
3505                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3506
3507         return ret;
3508 }
3509
3510 static int
3511 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3512 {
3513         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3514         int i, ret;
3515         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3516
3517         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3518         if (ret != I40E_SUCCESS)
3519                 return ret;
3520
3521         if (!vsi->seid) {
3522                 PMD_DRV_LOG(ERR, "seid not valid");
3523                 return -EINVAL;
3524         }
3525
3526         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3527         tc_bw_data.tc_valid_bits = enabled_tcmap;
3528         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3529                 tc_bw_data.tc_bw_credits[i] =
3530                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3531
3532         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3533         if (ret != I40E_SUCCESS) {
3534                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3535                 return ret;
3536         }
3537
3538         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3539                                         sizeof(vsi->info.qs_handle));
3540         return I40E_SUCCESS;
3541 }
3542
3543 static enum i40e_status_code
3544 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3545                                  struct i40e_aqc_vsi_properties_data *info,
3546                                  uint8_t enabled_tcmap)
3547 {
3548         enum i40e_status_code ret;
3549         int i, total_tc = 0;
3550         uint16_t qpnum_per_tc, bsf, qp_idx;
3551
3552         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3553         if (ret != I40E_SUCCESS)
3554                 return ret;
3555
3556         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3557                 if (enabled_tcmap & (1 << i))
3558                         total_tc++;
3559         vsi->enabled_tc = enabled_tcmap;
3560
3561         /* Number of queues per enabled TC */
3562         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3563         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3564         bsf = rte_bsf32(qpnum_per_tc);
3565
3566         /* Adjust the queue number to actual queues that can be applied */
3567         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3568                 vsi->nb_qps = qpnum_per_tc * total_tc;
3569
3570         /**
3571          * Configure TC and queue mapping parameters, for enabled TC,
3572          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3573          * default queue will serve it.
3574          */
3575         qp_idx = 0;
3576         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3577                 if (vsi->enabled_tc & (1 << i)) {
3578                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3579                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3580                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3581                         qp_idx += qpnum_per_tc;
3582                 } else
3583                         info->tc_mapping[i] = 0;
3584         }
3585
3586         /* Associate queue number with VSI */
3587         if (vsi->type == I40E_VSI_SRIOV) {
3588                 info->mapping_flags |=
3589                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3590                 for (i = 0; i < vsi->nb_qps; i++)
3591                         info->queue_mapping[i] =
3592                                 rte_cpu_to_le_16(vsi->base_queue + i);
3593         } else {
3594                 info->mapping_flags |=
3595                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3596                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3597         }
3598         info->valid_sections |=
3599                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3600
3601         return I40E_SUCCESS;
3602 }
3603
3604 static int
3605 i40e_veb_release(struct i40e_veb *veb)
3606 {
3607         struct i40e_vsi *vsi;
3608         struct i40e_hw *hw;
3609
3610         if (veb == NULL || veb->associate_vsi == NULL)
3611                 return -EINVAL;
3612
3613         if (!TAILQ_EMPTY(&veb->head)) {
3614                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3615                 return -EACCES;
3616         }
3617
3618         vsi = veb->associate_vsi;
3619         hw = I40E_VSI_TO_HW(vsi);
3620
3621         vsi->uplink_seid = veb->uplink_seid;
3622         i40e_aq_delete_element(hw, veb->seid, NULL);
3623         rte_free(veb);
3624         vsi->veb = NULL;
3625         return I40E_SUCCESS;
3626 }
3627
3628 /* Setup a veb */
3629 static struct i40e_veb *
3630 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3631 {
3632         struct i40e_veb *veb;
3633         int ret;
3634         struct i40e_hw *hw;
3635
3636         if (NULL == pf || vsi == NULL) {
3637                 PMD_DRV_LOG(ERR, "veb setup failed, "
3638                             "associated VSI shouldn't null");
3639                 return NULL;
3640         }
3641         hw = I40E_PF_TO_HW(pf);
3642
3643         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3644         if (!veb) {
3645                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3646                 goto fail;
3647         }
3648
3649         veb->associate_vsi = vsi;
3650         TAILQ_INIT(&veb->head);
3651         veb->uplink_seid = vsi->uplink_seid;
3652
3653         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3654                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3655
3656         if (ret != I40E_SUCCESS) {
3657                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3658                             hw->aq.asq_last_status);
3659                 goto fail;
3660         }
3661
3662         /* get statistics index */
3663         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3664                                 &veb->stats_idx, NULL, NULL, NULL);
3665         if (ret != I40E_SUCCESS) {
3666                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3667                             hw->aq.asq_last_status);
3668                 goto fail;
3669         }
3670
3671         /* Get VEB bandwidth, to be implemented */
3672         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3673         vsi->uplink_seid = veb->seid;
3674
3675         return veb;
3676 fail:
3677         rte_free(veb);
3678         return NULL;
3679 }
3680
3681 int
3682 i40e_vsi_release(struct i40e_vsi *vsi)
3683 {
3684         struct i40e_pf *pf;
3685         struct i40e_hw *hw;
3686         struct i40e_vsi_list *vsi_list;
3687         int ret;
3688         struct i40e_mac_filter *f;
3689
3690         if (!vsi)
3691                 return I40E_SUCCESS;
3692
3693         pf = I40E_VSI_TO_PF(vsi);
3694         hw = I40E_VSI_TO_HW(vsi);
3695
3696         /* VSI has child to attach, release child first */
3697         if (vsi->veb) {
3698                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3699                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3700                                 return -1;
3701                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3702                 }
3703                 i40e_veb_release(vsi->veb);
3704         }
3705
3706         /* Remove all macvlan filters of the VSI */
3707         i40e_vsi_remove_all_macvlan_filter(vsi);
3708         TAILQ_FOREACH(f, &vsi->mac_list, next)
3709                 rte_free(f);
3710
3711         if (vsi->type != I40E_VSI_MAIN) {
3712                 /* Remove vsi from parent's sibling list */
3713                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3714                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3715                         return I40E_ERR_PARAM;
3716                 }
3717                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3718                                 &vsi->sib_vsi_list, list);
3719
3720                 /* Remove all switch element of the VSI */
3721                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3722                 if (ret != I40E_SUCCESS)
3723                         PMD_DRV_LOG(ERR, "Failed to delete element");
3724         }
3725         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3726
3727         if (vsi->type != I40E_VSI_SRIOV)
3728                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3729         rte_free(vsi);
3730
3731         return I40E_SUCCESS;
3732 }
3733
3734 static int
3735 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3736 {
3737         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3738         struct i40e_aqc_remove_macvlan_element_data def_filter;
3739         struct i40e_mac_filter_info filter;
3740         int ret;
3741
3742         if (vsi->type != I40E_VSI_MAIN)
3743                 return I40E_ERR_CONFIG;
3744         memset(&def_filter, 0, sizeof(def_filter));
3745         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3746                                         ETH_ADDR_LEN);
3747         def_filter.vlan_tag = 0;
3748         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3749                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3750         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3751         if (ret != I40E_SUCCESS) {
3752                 struct i40e_mac_filter *f;
3753                 struct ether_addr *mac;
3754
3755                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3756                             "macvlan filter");
3757                 /* It needs to add the permanent mac into mac list */
3758                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3759                 if (f == NULL) {
3760                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3761                         return I40E_ERR_NO_MEMORY;
3762                 }
3763                 mac = &f->mac_info.mac_addr;
3764                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3765                                 ETH_ADDR_LEN);
3766                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3767                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3768                 vsi->mac_num++;
3769
3770                 return ret;
3771         }
3772         (void)rte_memcpy(&filter.mac_addr,
3773                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3774         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3775         return i40e_vsi_add_mac(vsi, &filter);
3776 }
3777
3778 static int
3779 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3780 {
3781         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3782         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3783         struct i40e_hw *hw = &vsi->adapter->hw;
3784         i40e_status ret;
3785         int i;
3786
3787         memset(&bw_config, 0, sizeof(bw_config));
3788         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3789         if (ret != I40E_SUCCESS) {
3790                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3791                             hw->aq.asq_last_status);
3792                 return ret;
3793         }
3794
3795         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3796         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3797                                         &ets_sla_config, NULL);
3798         if (ret != I40E_SUCCESS) {
3799                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3800                             "configuration %u", hw->aq.asq_last_status);
3801                 return ret;
3802         }
3803
3804         /* Not store the info yet, just print out */
3805         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3806         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3807         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3808                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3809                             ets_sla_config.share_credits[i]);
3810                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3811                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3812                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3813                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3814                             (i * 4));
3815         }
3816
3817         return 0;
3818 }
3819
3820 /* Setup a VSI */
3821 struct i40e_vsi *
3822 i40e_vsi_setup(struct i40e_pf *pf,
3823                enum i40e_vsi_type type,
3824                struct i40e_vsi *uplink_vsi,
3825                uint16_t user_param)
3826 {
3827         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3828         struct i40e_vsi *vsi;
3829         struct i40e_mac_filter_info filter;
3830         int ret;
3831         struct i40e_vsi_context ctxt;
3832         struct ether_addr broadcast =
3833                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3834
3835         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3836                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3837                             "VSI link shouldn't be NULL");
3838                 return NULL;
3839         }
3840
3841         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3842                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3843                             "uplink VSI should be NULL");
3844                 return NULL;
3845         }
3846
3847         /* If uplink vsi didn't setup VEB, create one first */
3848         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3849                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3850
3851                 if (NULL == uplink_vsi->veb) {
3852                         PMD_DRV_LOG(ERR, "VEB setup failed");
3853                         return NULL;
3854                 }
3855         }
3856
3857         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3858         if (!vsi) {
3859                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3860                 return NULL;
3861         }
3862         TAILQ_INIT(&vsi->mac_list);
3863         vsi->type = type;
3864         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3865         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3866         vsi->parent_vsi = uplink_vsi;
3867         vsi->user_param = user_param;
3868         /* Allocate queues */
3869         switch (vsi->type) {
3870         case I40E_VSI_MAIN  :
3871                 vsi->nb_qps = pf->lan_nb_qps;
3872                 break;
3873         case I40E_VSI_SRIOV :
3874                 vsi->nb_qps = pf->vf_nb_qps;
3875                 break;
3876         case I40E_VSI_VMDQ2:
3877                 vsi->nb_qps = pf->vmdq_nb_qps;
3878                 break;
3879         case I40E_VSI_FDIR:
3880                 vsi->nb_qps = pf->fdir_nb_qps;
3881                 break;
3882         default:
3883                 goto fail_mem;
3884         }
3885         /*
3886          * The filter status descriptor is reported in rx queue 0,
3887          * while the tx queue for fdir filter programming has no
3888          * such constraints, can be non-zero queues.
3889          * To simplify it, choose FDIR vsi use queue 0 pair.
3890          * To make sure it will use queue 0 pair, queue allocation
3891          * need be done before this function is called
3892          */
3893         if (type != I40E_VSI_FDIR) {
3894                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3895                         if (ret < 0) {
3896                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3897                                                 vsi->seid, ret);
3898                                 goto fail_mem;
3899                         }
3900                         vsi->base_queue = ret;
3901         } else
3902                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3903
3904         /* VF has MSIX interrupt in VF range, don't allocate here */
3905         if (type == I40E_VSI_MAIN) {
3906                 ret = i40e_res_pool_alloc(&pf->msix_pool,
3907                                           RTE_MIN(vsi->nb_qps,
3908                                                   RTE_MAX_RXTX_INTR_VEC_ID));
3909                 if (ret < 0) {
3910                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3911                                     vsi->seid, ret);
3912                         goto fail_queue_alloc;
3913                 }
3914                 vsi->msix_intr = ret;
3915                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3916         } else if (type != I40E_VSI_SRIOV) {
3917                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3918                 if (ret < 0) {
3919                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3920                         goto fail_queue_alloc;
3921                 }
3922                 vsi->msix_intr = ret;
3923                 vsi->nb_msix = 1;
3924         } else {
3925                 vsi->msix_intr = 0;
3926                 vsi->nb_msix = 0;
3927         }
3928
3929         /* Add VSI */
3930         if (type == I40E_VSI_MAIN) {
3931                 /* For main VSI, no need to add since it's default one */
3932                 vsi->uplink_seid = pf->mac_seid;
3933                 vsi->seid = pf->main_vsi_seid;
3934                 /* Bind queues with specific MSIX interrupt */
3935                 /**
3936                  * Needs 2 interrupt at least, one for misc cause which will
3937                  * enabled from OS side, Another for queues binding the
3938                  * interrupt from device side only.
3939                  */
3940
3941                 /* Get default VSI parameters from hardware */
3942                 memset(&ctxt, 0, sizeof(ctxt));
3943                 ctxt.seid = vsi->seid;
3944                 ctxt.pf_num = hw->pf_id;
3945                 ctxt.uplink_seid = vsi->uplink_seid;
3946                 ctxt.vf_num = 0;
3947                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3948                 if (ret != I40E_SUCCESS) {
3949                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3950                         goto fail_msix_alloc;
3951                 }
3952                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3953                         sizeof(struct i40e_aqc_vsi_properties_data));
3954                 vsi->vsi_id = ctxt.vsi_number;
3955                 vsi->info.valid_sections = 0;
3956
3957                 /* Configure tc, enabled TC0 only */
3958                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3959                         I40E_SUCCESS) {
3960                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3961                         goto fail_msix_alloc;
3962                 }
3963
3964                 /* TC, queue mapping */
3965                 memset(&ctxt, 0, sizeof(ctxt));
3966                 vsi->info.valid_sections |=
3967                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3968                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3969                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3970                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3971                         sizeof(struct i40e_aqc_vsi_properties_data));
3972                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3973                                                 I40E_DEFAULT_TCMAP);
3974                 if (ret != I40E_SUCCESS) {
3975                         PMD_DRV_LOG(ERR, "Failed to configure "
3976                                     "TC queue mapping");
3977                         goto fail_msix_alloc;
3978                 }
3979                 ctxt.seid = vsi->seid;
3980                 ctxt.pf_num = hw->pf_id;
3981                 ctxt.uplink_seid = vsi->uplink_seid;
3982                 ctxt.vf_num = 0;
3983
3984                 /* Update VSI parameters */
3985                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3986                 if (ret != I40E_SUCCESS) {
3987                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3988                         goto fail_msix_alloc;
3989                 }
3990
3991                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3992                                                 sizeof(vsi->info.tc_mapping));
3993                 (void)rte_memcpy(&vsi->info.queue_mapping,
3994                                 &ctxt.info.queue_mapping,
3995                         sizeof(vsi->info.queue_mapping));
3996                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3997                 vsi->info.valid_sections = 0;
3998
3999                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4000                                 ETH_ADDR_LEN);
4001
4002                 /**
4003                  * Updating default filter settings are necessary to prevent
4004                  * reception of tagged packets.
4005                  * Some old firmware configurations load a default macvlan
4006                  * filter which accepts both tagged and untagged packets.
4007                  * The updating is to use a normal filter instead if needed.
4008                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4009                  * The firmware with correct configurations load the default
4010                  * macvlan filter which is expected and cannot be removed.
4011                  */
4012                 i40e_update_default_filter_setting(vsi);
4013                 i40e_config_qinq(hw, vsi);
4014         } else if (type == I40E_VSI_SRIOV) {
4015                 memset(&ctxt, 0, sizeof(ctxt));
4016                 /**
4017                  * For other VSI, the uplink_seid equals to uplink VSI's
4018                  * uplink_seid since they share same VEB
4019                  */
4020                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4021                 ctxt.pf_num = hw->pf_id;
4022                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4023                 ctxt.uplink_seid = vsi->uplink_seid;
4024                 ctxt.connection_type = 0x1;
4025                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4026
4027                 /**
4028                  * Do not configure switch ID to enable VEB switch by
4029                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4030                  * if the source mac address of packet sent from VF is not
4031                  * listed in the VEB's mac table, the VEB will switch the
4032                  * packet back to the VF. Need to enable it when HW issue
4033                  * is fixed.
4034                  */
4035
4036                 /* Configure port/vlan */
4037                 ctxt.info.valid_sections |=
4038                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4039                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4040                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4041                                                 I40E_DEFAULT_TCMAP);
4042                 if (ret != I40E_SUCCESS) {
4043                         PMD_DRV_LOG(ERR, "Failed to configure "
4044                                     "TC queue mapping");
4045                         goto fail_msix_alloc;
4046                 }
4047                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4048                 ctxt.info.valid_sections |=
4049                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4050                 /**
4051                  * Since VSI is not created yet, only configure parameter,
4052                  * will add vsi below.
4053                  */
4054
4055                 i40e_config_qinq(hw, vsi);
4056         } else if (type == I40E_VSI_VMDQ2) {
4057                 memset(&ctxt, 0, sizeof(ctxt));
4058                 /*
4059                  * For other VSI, the uplink_seid equals to uplink VSI's
4060                  * uplink_seid since they share same VEB
4061                  */
4062                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4063                 ctxt.pf_num = hw->pf_id;
4064                 ctxt.vf_num = 0;
4065                 ctxt.uplink_seid = vsi->uplink_seid;
4066                 ctxt.connection_type = 0x1;
4067                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4068
4069                 ctxt.info.valid_sections |=
4070                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4071                 /* user_param carries flag to enable loop back */
4072                 if (user_param) {
4073                         ctxt.info.switch_id =
4074                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4075                         ctxt.info.switch_id |=
4076                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4077                 }
4078
4079                 /* Configure port/vlan */
4080                 ctxt.info.valid_sections |=
4081                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4082                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4083                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4084                                                 I40E_DEFAULT_TCMAP);
4085                 if (ret != I40E_SUCCESS) {
4086                         PMD_DRV_LOG(ERR, "Failed to configure "
4087                                         "TC queue mapping");
4088                         goto fail_msix_alloc;
4089                 }
4090                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4091                 ctxt.info.valid_sections |=
4092                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4093         } else if (type == I40E_VSI_FDIR) {
4094                 memset(&ctxt, 0, sizeof(ctxt));
4095                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4096                 ctxt.pf_num = hw->pf_id;
4097                 ctxt.vf_num = 0;
4098                 ctxt.uplink_seid = vsi->uplink_seid;
4099                 ctxt.connection_type = 0x1;     /* regular data port */
4100                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4101                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4102                                                 I40E_DEFAULT_TCMAP);
4103                 if (ret != I40E_SUCCESS) {
4104                         PMD_DRV_LOG(ERR, "Failed to configure "
4105                                         "TC queue mapping.");
4106                         goto fail_msix_alloc;
4107                 }
4108                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4109                 ctxt.info.valid_sections |=
4110                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4111         } else {
4112                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4113                 goto fail_msix_alloc;
4114         }
4115
4116         if (vsi->type != I40E_VSI_MAIN) {
4117                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4118                 if (ret != I40E_SUCCESS) {
4119                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4120                                     hw->aq.asq_last_status);
4121                         goto fail_msix_alloc;
4122                 }
4123                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4124                 vsi->info.valid_sections = 0;
4125                 vsi->seid = ctxt.seid;
4126                 vsi->vsi_id = ctxt.vsi_number;
4127                 vsi->sib_vsi_list.vsi = vsi;
4128                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4129                                 &vsi->sib_vsi_list, list);
4130         }
4131
4132         /* MAC/VLAN configuration */
4133         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4134         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4135
4136         ret = i40e_vsi_add_mac(vsi, &filter);
4137         if (ret != I40E_SUCCESS) {
4138                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4139                 goto fail_msix_alloc;
4140         }
4141
4142         /* Get VSI BW information */
4143         i40e_vsi_dump_bw_config(vsi);
4144         return vsi;
4145 fail_msix_alloc:
4146         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4147 fail_queue_alloc:
4148         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4149 fail_mem:
4150         rte_free(vsi);
4151         return NULL;
4152 }
4153
4154 /* Configure vlan stripping on or off */
4155 int
4156 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4157 {
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159         struct i40e_vsi_context ctxt;
4160         uint8_t vlan_flags;
4161         int ret = I40E_SUCCESS;
4162
4163         /* Check if it has been already on or off */
4164         if (vsi->info.valid_sections &
4165                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4166                 if (on) {
4167                         if ((vsi->info.port_vlan_flags &
4168                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4169                                 return 0; /* already on */
4170                 } else {
4171                         if ((vsi->info.port_vlan_flags &
4172                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4173                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4174                                 return 0; /* already off */
4175                 }
4176         }
4177
4178         if (on)
4179                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4180         else
4181                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4182         vsi->info.valid_sections =
4183                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4184         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4185         vsi->info.port_vlan_flags |= vlan_flags;
4186         ctxt.seid = vsi->seid;
4187         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4188         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4189         if (ret)
4190                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4191                             on ? "enable" : "disable");
4192
4193         return ret;
4194 }
4195
4196 static int
4197 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4198 {
4199         struct rte_eth_dev_data *data = dev->data;
4200         int ret;
4201
4202         /* Apply vlan offload setting */
4203         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4204
4205         /* Apply double-vlan setting, not implemented yet */
4206
4207         /* Apply pvid setting */
4208         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4209                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4210         if (ret)
4211                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4212
4213         return ret;
4214 }
4215
4216 static int
4217 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4218 {
4219         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4220
4221         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4222 }
4223
4224 static int
4225 i40e_update_flow_control(struct i40e_hw *hw)
4226 {
4227 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4228         struct i40e_link_status link_status;
4229         uint32_t rxfc = 0, txfc = 0, reg;
4230         uint8_t an_info;
4231         int ret;
4232
4233         memset(&link_status, 0, sizeof(link_status));
4234         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4235         if (ret != I40E_SUCCESS) {
4236                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4237                 goto write_reg; /* Disable flow control */
4238         }
4239
4240         an_info = hw->phy.link_info.an_info;
4241         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4242                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4243                 ret = I40E_ERR_NOT_READY;
4244                 goto write_reg; /* Disable flow control */
4245         }
4246         /**
4247          * If link auto negotiation is enabled, flow control needs to
4248          * be configured according to it
4249          */
4250         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4251         case I40E_LINK_PAUSE_RXTX:
4252                 rxfc = 1;
4253                 txfc = 1;
4254                 hw->fc.current_mode = I40E_FC_FULL;
4255                 break;
4256         case I40E_AQ_LINK_PAUSE_RX:
4257                 rxfc = 1;
4258                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4259                 break;
4260         case I40E_AQ_LINK_PAUSE_TX:
4261                 txfc = 1;
4262                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4263                 break;
4264         default:
4265                 hw->fc.current_mode = I40E_FC_NONE;
4266                 break;
4267         }
4268
4269 write_reg:
4270         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4271                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4272         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4273         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4274         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4275         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4276
4277         return ret;
4278 }
4279
4280 /* PF setup */
4281 static int
4282 i40e_pf_setup(struct i40e_pf *pf)
4283 {
4284         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4285         struct i40e_filter_control_settings settings;
4286         struct i40e_vsi *vsi;
4287         int ret;
4288
4289         /* Clear all stats counters */
4290         pf->offset_loaded = FALSE;
4291         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4292         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4293
4294         ret = i40e_pf_get_switch_config(pf);
4295         if (ret != I40E_SUCCESS) {
4296                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4297                 return ret;
4298         }
4299         if (pf->flags & I40E_FLAG_FDIR) {
4300                 /* make queue allocated first, let FDIR use queue pair 0*/
4301                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4302                 if (ret != I40E_FDIR_QUEUE_ID) {
4303                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4304                                     " ret =%d", ret);
4305                         pf->flags &= ~I40E_FLAG_FDIR;
4306                 }
4307         }
4308         /*  main VSI setup */
4309         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4310         if (!vsi) {
4311                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4312                 return I40E_ERR_NOT_READY;
4313         }
4314         pf->main_vsi = vsi;
4315
4316         /* Configure filter control */
4317         memset(&settings, 0, sizeof(settings));
4318         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4319                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4320         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4321                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4322         else {
4323                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4324                                                 hw->func_caps.rss_table_size);
4325                 return I40E_ERR_PARAM;
4326         }
4327         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4328                         "size: %u\n", hw->func_caps.rss_table_size);
4329         pf->hash_lut_size = hw->func_caps.rss_table_size;
4330
4331         /* Enable ethtype and macvlan filters */
4332         settings.enable_ethtype = TRUE;
4333         settings.enable_macvlan = TRUE;
4334         ret = i40e_set_filter_control(hw, &settings);
4335         if (ret)
4336                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4337                                                                 ret);
4338
4339         /* Update flow control according to the auto negotiation */
4340         i40e_update_flow_control(hw);
4341
4342         return I40E_SUCCESS;
4343 }
4344
4345 int
4346 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4347 {
4348         uint32_t reg;
4349         uint16_t j;
4350
4351         /**
4352          * Set or clear TX Queue Disable flags,
4353          * which is required by hardware.
4354          */
4355         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4356         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4357
4358         /* Wait until the request is finished */
4359         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4360                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4361                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4362                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4363                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4364                                                         & 0x1))) {
4365                         break;
4366                 }
4367         }
4368         if (on) {
4369                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4370                         return I40E_SUCCESS; /* already on, skip next steps */
4371
4372                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4373                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4374         } else {
4375                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4376                         return I40E_SUCCESS; /* already off, skip next steps */
4377                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4378         }
4379         /* Write the register */
4380         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4381         /* Check the result */
4382         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4383                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4384                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4385                 if (on) {
4386                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4387                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4388                                 break;
4389                 } else {
4390                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4391                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4392                                 break;
4393                 }
4394         }
4395         /* Check if it is timeout */
4396         if (j >= I40E_CHK_Q_ENA_COUNT) {
4397                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4398                             (on ? "enable" : "disable"), q_idx);
4399                 return I40E_ERR_TIMEOUT;
4400         }
4401
4402         return I40E_SUCCESS;
4403 }
4404
4405 /* Swith on or off the tx queues */
4406 static int
4407 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4408 {
4409         struct rte_eth_dev_data *dev_data = pf->dev_data;
4410         struct i40e_tx_queue *txq;
4411         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4412         uint16_t i;
4413         int ret;
4414
4415         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4416                 txq = dev_data->tx_queues[i];
4417                 /* Don't operate the queue if not configured or
4418                  * if starting only per queue */
4419                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4420                         continue;
4421                 if (on)
4422                         ret = i40e_dev_tx_queue_start(dev, i);
4423                 else
4424                         ret = i40e_dev_tx_queue_stop(dev, i);
4425                 if ( ret != I40E_SUCCESS)
4426                         return ret;
4427         }
4428
4429         return I40E_SUCCESS;
4430 }
4431
4432 int
4433 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4434 {
4435         uint32_t reg;
4436         uint16_t j;
4437
4438         /* Wait until the request is finished */
4439         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4440                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4441                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4442                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4443                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4444                         break;
4445         }
4446
4447         if (on) {
4448                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4449                         return I40E_SUCCESS; /* Already on, skip next steps */
4450                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4451         } else {
4452                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4453                         return I40E_SUCCESS; /* Already off, skip next steps */
4454                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4455         }
4456
4457         /* Write the register */
4458         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4459         /* Check the result */
4460         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4461                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4462                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4463                 if (on) {
4464                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4465                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4466                                 break;
4467                 } else {
4468                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4469                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4470                                 break;
4471                 }
4472         }
4473
4474         /* Check if it is timeout */
4475         if (j >= I40E_CHK_Q_ENA_COUNT) {
4476                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4477                             (on ? "enable" : "disable"), q_idx);
4478                 return I40E_ERR_TIMEOUT;
4479         }
4480
4481         return I40E_SUCCESS;
4482 }
4483 /* Switch on or off the rx queues */
4484 static int
4485 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4486 {
4487         struct rte_eth_dev_data *dev_data = pf->dev_data;
4488         struct i40e_rx_queue *rxq;
4489         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4490         uint16_t i;
4491         int ret;
4492
4493         for (i = 0; i < dev_data->nb_rx_queues; i++) {
4494                 rxq = dev_data->rx_queues[i];
4495                 /* Don't operate the queue if not configured or
4496                  * if starting only per queue */
4497                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4498                         continue;
4499                 if (on)
4500                         ret = i40e_dev_rx_queue_start(dev, i);
4501                 else
4502                         ret = i40e_dev_rx_queue_stop(dev, i);
4503                 if (ret != I40E_SUCCESS)
4504                         return ret;
4505         }
4506
4507         return I40E_SUCCESS;
4508 }
4509
4510 /* Switch on or off all the rx/tx queues */
4511 int
4512 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4513 {
4514         int ret;
4515
4516         if (on) {
4517                 /* enable rx queues before enabling tx queues */
4518                 ret = i40e_dev_switch_rx_queues(pf, on);
4519                 if (ret) {
4520                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4521                         return ret;
4522                 }
4523                 ret = i40e_dev_switch_tx_queues(pf, on);
4524         } else {
4525                 /* Stop tx queues before stopping rx queues */
4526                 ret = i40e_dev_switch_tx_queues(pf, on);
4527                 if (ret) {
4528                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4529                         return ret;
4530                 }
4531                 ret = i40e_dev_switch_rx_queues(pf, on);
4532         }
4533
4534         return ret;
4535 }
4536
4537 /* Initialize VSI for TX */
4538 static int
4539 i40e_dev_tx_init(struct i40e_pf *pf)
4540 {
4541         struct rte_eth_dev_data *data = pf->dev_data;
4542         uint16_t i;
4543         uint32_t ret = I40E_SUCCESS;
4544         struct i40e_tx_queue *txq;
4545
4546         for (i = 0; i < data->nb_tx_queues; i++) {
4547                 txq = data->tx_queues[i];
4548                 if (!txq || !txq->q_set)
4549                         continue;
4550                 ret = i40e_tx_queue_init(txq);
4551                 if (ret != I40E_SUCCESS)
4552                         break;
4553         }
4554         if (ret == I40E_SUCCESS)
4555                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4556                                      ->eth_dev);
4557
4558         return ret;
4559 }
4560
4561 /* Initialize VSI for RX */
4562 static int
4563 i40e_dev_rx_init(struct i40e_pf *pf)
4564 {
4565         struct rte_eth_dev_data *data = pf->dev_data;
4566         int ret = I40E_SUCCESS;
4567         uint16_t i;
4568         struct i40e_rx_queue *rxq;
4569
4570         i40e_pf_config_mq_rx(pf);
4571         for (i = 0; i < data->nb_rx_queues; i++) {
4572                 rxq = data->rx_queues[i];
4573                 if (!rxq || !rxq->q_set)
4574                         continue;
4575
4576                 ret = i40e_rx_queue_init(rxq);
4577                 if (ret != I40E_SUCCESS) {
4578                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
4579                                     "initialization");
4580                         break;
4581                 }
4582         }
4583         if (ret == I40E_SUCCESS)
4584                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4585                                      ->eth_dev);
4586
4587         return ret;
4588 }
4589
4590 static int
4591 i40e_dev_rxtx_init(struct i40e_pf *pf)
4592 {
4593         int err;
4594
4595         err = i40e_dev_tx_init(pf);
4596         if (err) {
4597                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4598                 return err;
4599         }
4600         err = i40e_dev_rx_init(pf);
4601         if (err) {
4602                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4603                 return err;
4604         }
4605
4606         return err;
4607 }
4608
4609 static int
4610 i40e_vmdq_setup(struct rte_eth_dev *dev)
4611 {
4612         struct rte_eth_conf *conf = &dev->data->dev_conf;
4613         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4614         int i, err, conf_vsis, j, loop;
4615         struct i40e_vsi *vsi;
4616         struct i40e_vmdq_info *vmdq_info;
4617         struct rte_eth_vmdq_rx_conf *vmdq_conf;
4618         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4619
4620         /*
4621          * Disable interrupt to avoid message from VF. Furthermore, it will
4622          * avoid race condition in VSI creation/destroy.
4623          */
4624         i40e_pf_disable_irq0(hw);
4625
4626         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4627                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4628                 return -ENOTSUP;
4629         }
4630
4631         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4632         if (conf_vsis > pf->max_nb_vmdq_vsi) {
4633                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4634                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4635                         pf->max_nb_vmdq_vsi);
4636                 return -ENOTSUP;
4637         }
4638
4639         if (pf->vmdq != NULL) {
4640                 PMD_INIT_LOG(INFO, "VMDQ already configured");
4641                 return 0;
4642         }
4643
4644         pf->vmdq = rte_zmalloc("vmdq_info_struct",
4645                                 sizeof(*vmdq_info) * conf_vsis, 0);
4646
4647         if (pf->vmdq == NULL) {
4648                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4649                 return -ENOMEM;
4650         }
4651
4652         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4653
4654         /* Create VMDQ VSI */
4655         for (i = 0; i < conf_vsis; i++) {
4656                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4657                                 vmdq_conf->enable_loop_back);
4658                 if (vsi == NULL) {
4659                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4660                         err = -1;
4661                         goto err_vsi_setup;
4662                 }
4663                 vmdq_info = &pf->vmdq[i];
4664                 vmdq_info->pf = pf;
4665                 vmdq_info->vsi = vsi;
4666         }
4667         pf->nb_cfg_vmdq_vsi = conf_vsis;
4668
4669         /* Configure Vlan */
4670         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4671         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4672                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4673                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4674                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4675                                         vmdq_conf->pool_map[i].vlan_id, j);
4676
4677                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4678                                                 vmdq_conf->pool_map[i].vlan_id);
4679                                 if (err) {
4680                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4681                                         err = -1;
4682                                         goto err_vsi_setup;
4683                                 }
4684                         }
4685                 }
4686         }
4687
4688         i40e_pf_enable_irq0(hw);
4689
4690         return 0;
4691
4692 err_vsi_setup:
4693         for (i = 0; i < conf_vsis; i++)
4694                 if (pf->vmdq[i].vsi == NULL)
4695                         break;
4696                 else
4697                         i40e_vsi_release(pf->vmdq[i].vsi);
4698
4699         rte_free(pf->vmdq);
4700         pf->vmdq = NULL;
4701         i40e_pf_enable_irq0(hw);
4702         return err;
4703 }
4704
4705 static void
4706 i40e_stat_update_32(struct i40e_hw *hw,
4707                    uint32_t reg,
4708                    bool offset_loaded,
4709                    uint64_t *offset,
4710                    uint64_t *stat)
4711 {
4712         uint64_t new_data;
4713
4714         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4715         if (!offset_loaded)
4716                 *offset = new_data;
4717
4718         if (new_data >= *offset)
4719                 *stat = (uint64_t)(new_data - *offset);
4720         else
4721                 *stat = (uint64_t)((new_data +
4722                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4723 }
4724
4725 static void
4726 i40e_stat_update_48(struct i40e_hw *hw,
4727                    uint32_t hireg,
4728                    uint32_t loreg,
4729                    bool offset_loaded,
4730                    uint64_t *offset,
4731                    uint64_t *stat)
4732 {
4733         uint64_t new_data;
4734
4735         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4736         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4737                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4738
4739         if (!offset_loaded)
4740                 *offset = new_data;
4741
4742         if (new_data >= *offset)
4743                 *stat = new_data - *offset;
4744         else
4745                 *stat = (uint64_t)((new_data +
4746                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4747
4748         *stat &= I40E_48_BIT_MASK;
4749 }
4750
4751 /* Disable IRQ0 */
4752 void
4753 i40e_pf_disable_irq0(struct i40e_hw *hw)
4754 {
4755         /* Disable all interrupt types */
4756         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4757         I40E_WRITE_FLUSH(hw);
4758 }
4759
4760 /* Enable IRQ0 */
4761 void
4762 i40e_pf_enable_irq0(struct i40e_hw *hw)
4763 {
4764         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4765                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4766                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4767                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4768         I40E_WRITE_FLUSH(hw);
4769 }
4770
4771 static void
4772 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4773 {
4774         /* read pending request and disable first */
4775         i40e_pf_disable_irq0(hw);
4776         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4777         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4778                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4779
4780         if (no_queue)
4781                 /* Link no queues with irq0 */
4782                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4783                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4784 }
4785
4786 static void
4787 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4788 {
4789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4791         int i;
4792         uint16_t abs_vf_id;
4793         uint32_t index, offset, val;
4794
4795         if (!pf->vfs)
4796                 return;
4797         /**
4798          * Try to find which VF trigger a reset, use absolute VF id to access
4799          * since the reg is global register.
4800          */
4801         for (i = 0; i < pf->vf_num; i++) {
4802                 abs_vf_id = hw->func_caps.vf_base_id + i;
4803                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4804                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4805                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4806                 /* VFR event occured */
4807                 if (val & (0x1 << offset)) {
4808                         int ret;
4809
4810                         /* Clear the event first */
4811                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4812                                                         (0x1 << offset));
4813                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4814                         /**
4815                          * Only notify a VF reset event occured,
4816                          * don't trigger another SW reset
4817                          */
4818                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4819                         if (ret != I40E_SUCCESS)
4820                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4821                 }
4822         }
4823 }
4824
4825 static void
4826 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4827 {
4828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4829         struct i40e_arq_event_info info;
4830         uint16_t pending, opcode;
4831         int ret;
4832
4833         info.buf_len = I40E_AQ_BUF_SZ;
4834         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4835         if (!info.msg_buf) {
4836                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4837                 return;
4838         }
4839
4840         pending = 1;
4841         while (pending) {
4842                 ret = i40e_clean_arq_element(hw, &info, &pending);
4843
4844                 if (ret != I40E_SUCCESS) {
4845                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4846                                     "aq_err: %u", hw->aq.asq_last_status);
4847                         break;
4848                 }
4849                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4850
4851                 switch (opcode) {
4852                 case i40e_aqc_opc_send_msg_to_pf:
4853                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4854                         i40e_pf_host_handle_vf_msg(dev,
4855                                         rte_le_to_cpu_16(info.desc.retval),
4856                                         rte_le_to_cpu_32(info.desc.cookie_high),
4857                                         rte_le_to_cpu_32(info.desc.cookie_low),
4858                                         info.msg_buf,
4859                                         info.msg_len);
4860                         break;
4861                 default:
4862                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4863                                     opcode);
4864                         break;
4865                 }
4866         }
4867         rte_free(info.msg_buf);
4868 }
4869
4870 /*
4871  * Interrupt handler is registered as the alarm callback for handling LSC
4872  * interrupt in a definite of time, in order to wait the NIC into a stable
4873  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4874  * no need for link down interrupt.
4875  */
4876 static void
4877 i40e_dev_interrupt_delayed_handler(void *param)
4878 {
4879         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4880         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4881         uint32_t icr0;
4882
4883         /* read interrupt causes again */
4884         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4885
4886 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4887         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4888                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4889         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4890                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4891         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4892                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4893         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4894                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4895         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4896                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4897                                                                 "state\n");
4898         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4899                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4900         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4901                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4902 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4903
4904         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4905                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4906                 i40e_dev_handle_vfr_event(dev);
4907         }
4908         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4909                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4910                 i40e_dev_handle_aq_msg(dev);
4911         }
4912
4913         /* handle the link up interrupt in an alarm callback */
4914         i40e_dev_link_update(dev, 0);
4915         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4916
4917         i40e_pf_enable_irq0(hw);
4918         rte_intr_enable(&(dev->pci_dev->intr_handle));
4919 }
4920
4921 /**
4922  * Interrupt handler triggered by NIC  for handling
4923  * specific interrupt.
4924  *
4925  * @param handle
4926  *  Pointer to interrupt handle.
4927  * @param param
4928  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4929  *
4930  * @return
4931  *  void
4932  */
4933 static void
4934 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4935                            void *param)
4936 {
4937         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint32_t icr0;
4940
4941         /* Disable interrupt */
4942         i40e_pf_disable_irq0(hw);
4943
4944         /* read out interrupt causes */
4945         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4946
4947         /* No interrupt event indicated */
4948         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4949                 PMD_DRV_LOG(INFO, "No interrupt event");
4950                 goto done;
4951         }
4952 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4953         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4954                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4955         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4956                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4957         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4958                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4959         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4960                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4961         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4962                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4963         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4964                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4965         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4966                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4967 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4968
4969         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4970                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4971                 i40e_dev_handle_vfr_event(dev);
4972         }
4973         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4974                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4975                 i40e_dev_handle_aq_msg(dev);
4976         }
4977
4978         /* Link Status Change interrupt */
4979         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4980 #define I40E_US_PER_SECOND 1000000
4981                 struct rte_eth_link link;
4982
4983                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4984                 memset(&link, 0, sizeof(link));
4985                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4986                 i40e_dev_link_update(dev, 0);
4987
4988                 /*
4989                  * For link up interrupt, it needs to wait 1 second to let the
4990                  * hardware be a stable state. Otherwise several consecutive
4991                  * interrupts can be observed.
4992                  * For link down interrupt, no need to wait.
4993                  */
4994                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4995                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4996                         return;
4997                 else
4998                         _rte_eth_dev_callback_process(dev,
4999                                 RTE_ETH_EVENT_INTR_LSC);
5000         }
5001
5002 done:
5003         /* Enable interrupt */
5004         i40e_pf_enable_irq0(hw);
5005         rte_intr_enable(&(dev->pci_dev->intr_handle));
5006 }
5007
5008 static int
5009 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5010                          struct i40e_macvlan_filter *filter,
5011                          int total)
5012 {
5013         int ele_num, ele_buff_size;
5014         int num, actual_num, i;
5015         uint16_t flags;
5016         int ret = I40E_SUCCESS;
5017         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5018         struct i40e_aqc_add_macvlan_element_data *req_list;
5019
5020         if (filter == NULL  || total == 0)
5021                 return I40E_ERR_PARAM;
5022         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5023         ele_buff_size = hw->aq.asq_buf_size;
5024
5025         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5026         if (req_list == NULL) {
5027                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5028                 return I40E_ERR_NO_MEMORY;
5029         }
5030
5031         num = 0;
5032         do {
5033                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5034                 memset(req_list, 0, ele_buff_size);
5035
5036                 for (i = 0; i < actual_num; i++) {
5037                         (void)rte_memcpy(req_list[i].mac_addr,
5038                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5039                         req_list[i].vlan_tag =
5040                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5041
5042                         switch (filter[num + i].filter_type) {
5043                         case RTE_MAC_PERFECT_MATCH:
5044                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5045                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5046                                 break;
5047                         case RTE_MACVLAN_PERFECT_MATCH:
5048                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5049                                 break;
5050                         case RTE_MAC_HASH_MATCH:
5051                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5052                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5053                                 break;
5054                         case RTE_MACVLAN_HASH_MATCH:
5055                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5056                                 break;
5057                         default:
5058                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5059                                 ret = I40E_ERR_PARAM;
5060                                 goto DONE;
5061                         }
5062
5063                         req_list[i].queue_number = 0;
5064
5065                         req_list[i].flags = rte_cpu_to_le_16(flags);
5066                 }
5067
5068                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5069                                                 actual_num, NULL);
5070                 if (ret != I40E_SUCCESS) {
5071                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5072                         goto DONE;
5073                 }
5074                 num += actual_num;
5075         } while (num < total);
5076
5077 DONE:
5078         rte_free(req_list);
5079         return ret;
5080 }
5081
5082 static int
5083 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5084                             struct i40e_macvlan_filter *filter,
5085                             int total)
5086 {
5087         int ele_num, ele_buff_size;
5088         int num, actual_num, i;
5089         uint16_t flags;
5090         int ret = I40E_SUCCESS;
5091         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5092         struct i40e_aqc_remove_macvlan_element_data *req_list;
5093
5094         if (filter == NULL  || total == 0)
5095                 return I40E_ERR_PARAM;
5096
5097         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5098         ele_buff_size = hw->aq.asq_buf_size;
5099
5100         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5101         if (req_list == NULL) {
5102                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5103                 return I40E_ERR_NO_MEMORY;
5104         }
5105
5106         num = 0;
5107         do {
5108                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5109                 memset(req_list, 0, ele_buff_size);
5110
5111                 for (i = 0; i < actual_num; i++) {
5112                         (void)rte_memcpy(req_list[i].mac_addr,
5113                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5114                         req_list[i].vlan_tag =
5115                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5116
5117                         switch (filter[num + i].filter_type) {
5118                         case RTE_MAC_PERFECT_MATCH:
5119                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5120                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5121                                 break;
5122                         case RTE_MACVLAN_PERFECT_MATCH:
5123                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5124                                 break;
5125                         case RTE_MAC_HASH_MATCH:
5126                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5127                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5128                                 break;
5129                         case RTE_MACVLAN_HASH_MATCH:
5130                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5131                                 break;
5132                         default:
5133                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5134                                 ret = I40E_ERR_PARAM;
5135                                 goto DONE;
5136                         }
5137                         req_list[i].flags = rte_cpu_to_le_16(flags);
5138                 }
5139
5140                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5141                                                 actual_num, NULL);
5142                 if (ret != I40E_SUCCESS) {
5143                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5144                         goto DONE;
5145                 }
5146                 num += actual_num;
5147         } while (num < total);
5148
5149 DONE:
5150         rte_free(req_list);
5151         return ret;
5152 }
5153
5154 /* Find out specific MAC filter */
5155 static struct i40e_mac_filter *
5156 i40e_find_mac_filter(struct i40e_vsi *vsi,
5157                          struct ether_addr *macaddr)
5158 {
5159         struct i40e_mac_filter *f;
5160
5161         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5162                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5163                         return f;
5164         }
5165
5166         return NULL;
5167 }
5168
5169 static bool
5170 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5171                          uint16_t vlan_id)
5172 {
5173         uint32_t vid_idx, vid_bit;
5174
5175         if (vlan_id > ETH_VLAN_ID_MAX)
5176                 return 0;
5177
5178         vid_idx = I40E_VFTA_IDX(vlan_id);
5179         vid_bit = I40E_VFTA_BIT(vlan_id);
5180
5181         if (vsi->vfta[vid_idx] & vid_bit)
5182                 return 1;
5183         else
5184                 return 0;
5185 }
5186
5187 static void
5188 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5189                          uint16_t vlan_id, bool on)
5190 {
5191         uint32_t vid_idx, vid_bit;
5192
5193         if (vlan_id > ETH_VLAN_ID_MAX)
5194                 return;
5195
5196         vid_idx = I40E_VFTA_IDX(vlan_id);
5197         vid_bit = I40E_VFTA_BIT(vlan_id);
5198
5199         if (on)
5200                 vsi->vfta[vid_idx] |= vid_bit;
5201         else
5202                 vsi->vfta[vid_idx] &= ~vid_bit;
5203 }
5204
5205 /**
5206  * Find all vlan options for specific mac addr,
5207  * return with actual vlan found.
5208  */
5209 static inline int
5210 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5211                            struct i40e_macvlan_filter *mv_f,
5212                            int num, struct ether_addr *addr)
5213 {
5214         int i;
5215         uint32_t j, k;
5216
5217         /**
5218          * Not to use i40e_find_vlan_filter to decrease the loop time,
5219          * although the code looks complex.
5220           */
5221         if (num < vsi->vlan_num)
5222                 return I40E_ERR_PARAM;
5223
5224         i = 0;
5225         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5226                 if (vsi->vfta[j]) {
5227                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5228                                 if (vsi->vfta[j] & (1 << k)) {
5229                                         if (i > num - 1) {
5230                                                 PMD_DRV_LOG(ERR, "vlan number "
5231                                                             "not match");
5232                                                 return I40E_ERR_PARAM;
5233                                         }
5234                                         (void)rte_memcpy(&mv_f[i].macaddr,
5235                                                         addr, ETH_ADDR_LEN);
5236                                         mv_f[i].vlan_id =
5237                                                 j * I40E_UINT32_BIT_SIZE + k;
5238                                         i++;
5239                                 }
5240                         }
5241                 }
5242         }
5243         return I40E_SUCCESS;
5244 }
5245
5246 static inline int
5247 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5248                            struct i40e_macvlan_filter *mv_f,
5249                            int num,
5250                            uint16_t vlan)
5251 {
5252         int i = 0;
5253         struct i40e_mac_filter *f;
5254
5255         if (num < vsi->mac_num)
5256                 return I40E_ERR_PARAM;
5257
5258         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5259                 if (i > num - 1) {
5260                         PMD_DRV_LOG(ERR, "buffer number not match");
5261                         return I40E_ERR_PARAM;
5262                 }
5263                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5264                                 ETH_ADDR_LEN);
5265                 mv_f[i].vlan_id = vlan;
5266                 mv_f[i].filter_type = f->mac_info.filter_type;
5267                 i++;
5268         }
5269
5270         return I40E_SUCCESS;
5271 }
5272
5273 static int
5274 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5275 {
5276         int i, num;
5277         struct i40e_mac_filter *f;
5278         struct i40e_macvlan_filter *mv_f;
5279         int ret = I40E_SUCCESS;
5280
5281         if (vsi == NULL || vsi->mac_num == 0)
5282                 return I40E_ERR_PARAM;
5283
5284         /* Case that no vlan is set */
5285         if (vsi->vlan_num == 0)
5286                 num = vsi->mac_num;
5287         else
5288                 num = vsi->mac_num * vsi->vlan_num;
5289
5290         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5291         if (mv_f == NULL) {
5292                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5293                 return I40E_ERR_NO_MEMORY;
5294         }
5295
5296         i = 0;
5297         if (vsi->vlan_num == 0) {
5298                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5299                         (void)rte_memcpy(&mv_f[i].macaddr,
5300                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5301                         mv_f[i].vlan_id = 0;
5302                         i++;
5303                 }
5304         } else {
5305                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5306                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5307                                         vsi->vlan_num, &f->mac_info.mac_addr);
5308                         if (ret != I40E_SUCCESS)
5309                                 goto DONE;
5310                         i += vsi->vlan_num;
5311                 }
5312         }
5313
5314         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5315 DONE:
5316         rte_free(mv_f);
5317
5318         return ret;
5319 }
5320
5321 int
5322 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5323 {
5324         struct i40e_macvlan_filter *mv_f;
5325         int mac_num;
5326         int ret = I40E_SUCCESS;
5327
5328         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5329                 return I40E_ERR_PARAM;
5330
5331         /* If it's already set, just return */
5332         if (i40e_find_vlan_filter(vsi,vlan))
5333                 return I40E_SUCCESS;
5334
5335         mac_num = vsi->mac_num;
5336
5337         if (mac_num == 0) {
5338                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5339                 return I40E_ERR_PARAM;
5340         }
5341
5342         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5343
5344         if (mv_f == NULL) {
5345                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5346                 return I40E_ERR_NO_MEMORY;
5347         }
5348
5349         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5350
5351         if (ret != I40E_SUCCESS)
5352                 goto DONE;
5353
5354         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5355
5356         if (ret != I40E_SUCCESS)
5357                 goto DONE;
5358
5359         i40e_set_vlan_filter(vsi, vlan, 1);
5360
5361         vsi->vlan_num++;
5362         ret = I40E_SUCCESS;
5363 DONE:
5364         rte_free(mv_f);
5365         return ret;
5366 }
5367
5368 int
5369 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5370 {
5371         struct i40e_macvlan_filter *mv_f;
5372         int mac_num;
5373         int ret = I40E_SUCCESS;
5374
5375         /**
5376          * Vlan 0 is the generic filter for untagged packets
5377          * and can't be removed.
5378          */
5379         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5380                 return I40E_ERR_PARAM;
5381
5382         /* If can't find it, just return */
5383         if (!i40e_find_vlan_filter(vsi, vlan))
5384                 return I40E_ERR_PARAM;
5385
5386         mac_num = vsi->mac_num;
5387
5388         if (mac_num == 0) {
5389                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5390                 return I40E_ERR_PARAM;
5391         }
5392
5393         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5394
5395         if (mv_f == NULL) {
5396                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5397                 return I40E_ERR_NO_MEMORY;
5398         }
5399
5400         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5401
5402         if (ret != I40E_SUCCESS)
5403                 goto DONE;
5404
5405         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5406
5407         if (ret != I40E_SUCCESS)
5408                 goto DONE;
5409
5410         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5411         if (vsi->vlan_num == 1) {
5412                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5413                 if (ret != I40E_SUCCESS)
5414                         goto DONE;
5415
5416                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5417                 if (ret != I40E_SUCCESS)
5418                         goto DONE;
5419         }
5420
5421         i40e_set_vlan_filter(vsi, vlan, 0);
5422
5423         vsi->vlan_num--;
5424         ret = I40E_SUCCESS;
5425 DONE:
5426         rte_free(mv_f);
5427         return ret;
5428 }
5429
5430 int
5431 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5432 {
5433         struct i40e_mac_filter *f;
5434         struct i40e_macvlan_filter *mv_f;
5435         int i, vlan_num = 0;
5436         int ret = I40E_SUCCESS;
5437
5438         /* If it's add and we've config it, return */
5439         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5440         if (f != NULL)
5441                 return I40E_SUCCESS;
5442         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5443                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5444
5445                 /**
5446                  * If vlan_num is 0, that's the first time to add mac,
5447                  * set mask for vlan_id 0.
5448                  */
5449                 if (vsi->vlan_num == 0) {
5450                         i40e_set_vlan_filter(vsi, 0, 1);
5451                         vsi->vlan_num = 1;
5452                 }
5453                 vlan_num = vsi->vlan_num;
5454         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5455                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5456                 vlan_num = 1;
5457
5458         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5459         if (mv_f == NULL) {
5460                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5461                 return I40E_ERR_NO_MEMORY;
5462         }
5463
5464         for (i = 0; i < vlan_num; i++) {
5465                 mv_f[i].filter_type = mac_filter->filter_type;
5466                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5467                                 ETH_ADDR_LEN);
5468         }
5469
5470         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5471                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5472                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5473                                         &mac_filter->mac_addr);
5474                 if (ret != I40E_SUCCESS)
5475                         goto DONE;
5476         }
5477
5478         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5479         if (ret != I40E_SUCCESS)
5480                 goto DONE;
5481
5482         /* Add the mac addr into mac list */
5483         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5484         if (f == NULL) {
5485                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5486                 ret = I40E_ERR_NO_MEMORY;
5487                 goto DONE;
5488         }
5489         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5490                         ETH_ADDR_LEN);
5491         f->mac_info.filter_type = mac_filter->filter_type;
5492         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5493         vsi->mac_num++;
5494
5495         ret = I40E_SUCCESS;
5496 DONE:
5497         rte_free(mv_f);
5498
5499         return ret;
5500 }
5501
5502 int
5503 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5504 {
5505         struct i40e_mac_filter *f;
5506         struct i40e_macvlan_filter *mv_f;
5507         int i, vlan_num;
5508         enum rte_mac_filter_type filter_type;
5509         int ret = I40E_SUCCESS;
5510
5511         /* Can't find it, return an error */
5512         f = i40e_find_mac_filter(vsi, addr);
5513         if (f == NULL)
5514                 return I40E_ERR_PARAM;
5515
5516         vlan_num = vsi->vlan_num;
5517         filter_type = f->mac_info.filter_type;
5518         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5519                 filter_type == RTE_MACVLAN_HASH_MATCH) {
5520                 if (vlan_num == 0) {
5521                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5522                         return I40E_ERR_PARAM;
5523                 }
5524         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5525                         filter_type == RTE_MAC_HASH_MATCH)
5526                 vlan_num = 1;
5527
5528         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5529         if (mv_f == NULL) {
5530                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5531                 return I40E_ERR_NO_MEMORY;
5532         }
5533
5534         for (i = 0; i < vlan_num; i++) {
5535                 mv_f[i].filter_type = filter_type;
5536                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5537                                 ETH_ADDR_LEN);
5538         }
5539         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5540                         filter_type == RTE_MACVLAN_HASH_MATCH) {
5541                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5542                 if (ret != I40E_SUCCESS)
5543                         goto DONE;
5544         }
5545
5546         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5547         if (ret != I40E_SUCCESS)
5548                 goto DONE;
5549
5550         /* Remove the mac addr into mac list */
5551         TAILQ_REMOVE(&vsi->mac_list, f, next);
5552         rte_free(f);
5553         vsi->mac_num--;
5554
5555         ret = I40E_SUCCESS;
5556 DONE:
5557         rte_free(mv_f);
5558         return ret;
5559 }
5560
5561 /* Configure hash enable flags for RSS */
5562 uint64_t
5563 i40e_config_hena(uint64_t flags)
5564 {
5565         uint64_t hena = 0;
5566
5567         if (!flags)
5568                 return hena;
5569
5570         if (flags & ETH_RSS_FRAG_IPV4)
5571                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5572         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5573                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5574         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5575                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5576         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5577                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5578         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5579                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5580         if (flags & ETH_RSS_FRAG_IPV6)
5581                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5582         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5583                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5584         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5585                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5586         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5587                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5588         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5589                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5590         if (flags & ETH_RSS_L2_PAYLOAD)
5591                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5592
5593         return hena;
5594 }
5595
5596 /* Parse the hash enable flags */
5597 uint64_t
5598 i40e_parse_hena(uint64_t flags)
5599 {
5600         uint64_t rss_hf = 0;
5601
5602         if (!flags)
5603                 return rss_hf;
5604         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5605                 rss_hf |= ETH_RSS_FRAG_IPV4;
5606         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5607                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5608         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5609                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5610         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5611                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5612         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5613                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5614         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5615                 rss_hf |= ETH_RSS_FRAG_IPV6;
5616         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5617                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5618         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5619                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5620         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5621                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5622         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5623                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5624         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5625                 rss_hf |= ETH_RSS_L2_PAYLOAD;
5626
5627         return rss_hf;
5628 }
5629
5630 /* Disable RSS */
5631 static void
5632 i40e_pf_disable_rss(struct i40e_pf *pf)
5633 {
5634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5635         uint64_t hena;
5636
5637         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5638         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5639         hena &= ~I40E_RSS_HENA_ALL;
5640         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5641         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5642         I40E_WRITE_FLUSH(hw);
5643 }
5644
5645 static int
5646 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5647 {
5648         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5649         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5650         int ret = 0;
5651
5652         if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5653                 sizeof(uint32_t)))
5654                 return -EINVAL;
5655
5656         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5657                 struct i40e_aqc_get_set_rss_key_data *key_dw =
5658                         (struct i40e_aqc_get_set_rss_key_data *)key;
5659
5660                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5661                 if (ret)
5662                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5663                                      "via AQ");
5664         } else {
5665                 uint32_t *hash_key = (uint32_t *)key;
5666                 uint16_t i;
5667
5668                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5669                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5670                 I40E_WRITE_FLUSH(hw);
5671         }
5672
5673         return ret;
5674 }
5675
5676 static int
5677 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5678 {
5679         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5680         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5681         int ret;
5682
5683         if (!key || !key_len)
5684                 return -EINVAL;
5685
5686         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5687                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5688                         (struct i40e_aqc_get_set_rss_key_data *)key);
5689                 if (ret) {
5690                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5691                         return ret;
5692                 }
5693         } else {
5694                 uint32_t *key_dw = (uint32_t *)key;
5695                 uint16_t i;
5696
5697                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5698                         key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5699         }
5700         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5701
5702         return 0;
5703 }
5704
5705 static int
5706 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5707 {
5708         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5709         uint64_t rss_hf;
5710         uint64_t hena;
5711         int ret;
5712
5713         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5714                                rss_conf->rss_key_len);
5715         if (ret)
5716                 return ret;
5717
5718         rss_hf = rss_conf->rss_hf;
5719         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5720         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5721         hena &= ~I40E_RSS_HENA_ALL;
5722         hena |= i40e_config_hena(rss_hf);
5723         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5724         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5725         I40E_WRITE_FLUSH(hw);
5726
5727         return 0;
5728 }
5729
5730 static int
5731 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5732                          struct rte_eth_rss_conf *rss_conf)
5733 {
5734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5736         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5737         uint64_t hena;
5738
5739         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5740         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5741         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5742                 if (rss_hf != 0) /* Enable RSS */
5743                         return -EINVAL;
5744                 return 0; /* Nothing to do */
5745         }
5746         /* RSS enabled */
5747         if (rss_hf == 0) /* Disable RSS */
5748                 return -EINVAL;
5749
5750         return i40e_hw_rss_hash_set(pf, rss_conf);
5751 }
5752
5753 static int
5754 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5755                            struct rte_eth_rss_conf *rss_conf)
5756 {
5757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5759         uint64_t hena;
5760
5761         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5762                          &rss_conf->rss_key_len);
5763
5764         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5765         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5766         rss_conf->rss_hf = i40e_parse_hena(hena);
5767
5768         return 0;
5769 }
5770
5771 static int
5772 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5773 {
5774         switch (filter_type) {
5775         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5776                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5777                 break;
5778         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5779                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5780                 break;
5781         case RTE_TUNNEL_FILTER_IMAC_TENID:
5782                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5783                 break;
5784         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5785                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5786                 break;
5787         case ETH_TUNNEL_FILTER_IMAC:
5788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5789                 break;
5790         default:
5791                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5792                 return -EINVAL;
5793         }
5794
5795         return 0;
5796 }
5797
5798 static int
5799 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5800                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5801                         uint8_t add)
5802 {
5803         uint16_t ip_type;
5804         uint8_t tun_type = 0;
5805         int val, ret = 0;
5806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5807         struct i40e_vsi *vsi = pf->main_vsi;
5808         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5809         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5810
5811         cld_filter = rte_zmalloc("tunnel_filter",
5812                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5813                 0);
5814
5815         if (NULL == cld_filter) {
5816                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5817                 return -EINVAL;
5818         }
5819         pfilter = cld_filter;
5820
5821         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5822                         sizeof(struct ether_addr));
5823         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5824                         sizeof(struct ether_addr));
5825
5826         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5827         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5828                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5829                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5830                                 &tunnel_filter->ip_addr,
5831                                 sizeof(pfilter->ipaddr.v4.data));
5832         } else {
5833                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5834                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5835                                 &tunnel_filter->ip_addr,
5836                                 sizeof(pfilter->ipaddr.v6.data));
5837         }
5838
5839         /* check tunneled type */
5840         switch (tunnel_filter->tunnel_type) {
5841         case RTE_TUNNEL_TYPE_VXLAN:
5842                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5843                 break;
5844         case RTE_TUNNEL_TYPE_NVGRE:
5845                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5846                 break;
5847         default:
5848                 /* Other tunnel types is not supported. */
5849                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5850                 rte_free(cld_filter);
5851                 return -EINVAL;
5852         }
5853
5854         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5855                                                 &pfilter->flags);
5856         if (val < 0) {
5857                 rte_free(cld_filter);
5858                 return -EINVAL;
5859         }
5860
5861         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5862                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5863         pfilter->tenant_id = tunnel_filter->tenant_id;
5864         pfilter->queue_number = tunnel_filter->queue_id;
5865
5866         if (add)
5867                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5868         else
5869                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5870                                                 cld_filter, 1);
5871
5872         rte_free(cld_filter);
5873         return ret;
5874 }
5875
5876 static int
5877 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5878 {
5879         uint8_t i;
5880
5881         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5882                 if (pf->vxlan_ports[i] == port)
5883                         return i;
5884         }
5885
5886         return -1;
5887 }
5888
5889 static int
5890 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5891 {
5892         int  idx, ret;
5893         uint8_t filter_idx;
5894         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5895
5896         idx = i40e_get_vxlan_port_idx(pf, port);
5897
5898         /* Check if port already exists */
5899         if (idx >= 0) {
5900                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5901                 return -EINVAL;
5902         }
5903
5904         /* Now check if there is space to add the new port */
5905         idx = i40e_get_vxlan_port_idx(pf, 0);
5906         if (idx < 0) {
5907                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5908                         "not adding port %d", port);
5909                 return -ENOSPC;
5910         }
5911
5912         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5913                                         &filter_idx, NULL);
5914         if (ret < 0) {
5915                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5916                 return -1;
5917         }
5918
5919         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5920                          port,  filter_idx);
5921
5922         /* New port: add it and mark its index in the bitmap */
5923         pf->vxlan_ports[idx] = port;
5924         pf->vxlan_bitmap |= (1 << idx);
5925
5926         if (!(pf->flags & I40E_FLAG_VXLAN))
5927                 pf->flags |= I40E_FLAG_VXLAN;
5928
5929         return 0;
5930 }
5931
5932 static int
5933 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5934 {
5935         int idx;
5936         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5937
5938         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5939                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5940                 return -EINVAL;
5941         }
5942
5943         idx = i40e_get_vxlan_port_idx(pf, port);
5944
5945         if (idx < 0) {
5946                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5947                 return -EINVAL;
5948         }
5949
5950         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5951                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5952                 return -1;
5953         }
5954
5955         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5956                         port, idx);
5957
5958         pf->vxlan_ports[idx] = 0;
5959         pf->vxlan_bitmap &= ~(1 << idx);
5960
5961         if (!pf->vxlan_bitmap)
5962                 pf->flags &= ~I40E_FLAG_VXLAN;
5963
5964         return 0;
5965 }
5966
5967 /* Add UDP tunneling port */
5968 static int
5969 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5970                         struct rte_eth_udp_tunnel *udp_tunnel)
5971 {
5972         int ret = 0;
5973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5974
5975         if (udp_tunnel == NULL)
5976                 return -EINVAL;
5977
5978         switch (udp_tunnel->prot_type) {
5979         case RTE_TUNNEL_TYPE_VXLAN:
5980                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5981                 break;
5982
5983         case RTE_TUNNEL_TYPE_GENEVE:
5984         case RTE_TUNNEL_TYPE_TEREDO:
5985                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5986                 ret = -1;
5987                 break;
5988
5989         default:
5990                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5991                 ret = -1;
5992                 break;
5993         }
5994
5995         return ret;
5996 }
5997
5998 /* Remove UDP tunneling port */
5999 static int
6000 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
6001                         struct rte_eth_udp_tunnel *udp_tunnel)
6002 {
6003         int ret = 0;
6004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6005
6006         if (udp_tunnel == NULL)
6007                 return -EINVAL;
6008
6009         switch (udp_tunnel->prot_type) {
6010         case RTE_TUNNEL_TYPE_VXLAN:
6011                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6012                 break;
6013         case RTE_TUNNEL_TYPE_GENEVE:
6014         case RTE_TUNNEL_TYPE_TEREDO:
6015                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6016                 ret = -1;
6017                 break;
6018         default:
6019                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6020                 ret = -1;
6021                 break;
6022         }
6023
6024         return ret;
6025 }
6026
6027 /* Calculate the maximum number of contiguous PF queues that are configured */
6028 static int
6029 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6030 {
6031         struct rte_eth_dev_data *data = pf->dev_data;
6032         int i, num;
6033         struct i40e_rx_queue *rxq;
6034
6035         num = 0;
6036         for (i = 0; i < pf->lan_nb_qps; i++) {
6037                 rxq = data->rx_queues[i];
6038                 if (rxq && rxq->q_set)
6039                         num++;
6040                 else
6041                         break;
6042         }
6043
6044         return num;
6045 }
6046
6047 /* Configure RSS */
6048 static int
6049 i40e_pf_config_rss(struct i40e_pf *pf)
6050 {
6051         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6052         struct rte_eth_rss_conf rss_conf;
6053         uint32_t i, lut = 0;
6054         uint16_t j, num;
6055
6056         /*
6057          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6058          * It's necessary to calulate the actual PF queues that are configured.
6059          */
6060         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6061                 num = i40e_pf_calc_configured_queues_num(pf);
6062         else
6063                 num = pf->dev_data->nb_rx_queues;
6064
6065         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6066         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6067                         num);
6068
6069         if (num == 0) {
6070                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6071                 return -ENOTSUP;
6072         }
6073
6074         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6075                 if (j == num)
6076                         j = 0;
6077                 lut = (lut << 8) | (j & ((0x1 <<
6078                         hw->func_caps.rss_table_entry_width) - 1));
6079                 if ((i & 3) == 3)
6080                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6081         }
6082
6083         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6084         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6085                 i40e_pf_disable_rss(pf);
6086                 return 0;
6087         }
6088         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6089                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6090                 /* Random default keys */
6091                 static uint32_t rss_key_default[] = {0x6b793944,
6092                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6093                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6094                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6095
6096                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6097                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6098                                                         sizeof(uint32_t);
6099         }
6100
6101         return i40e_hw_rss_hash_set(pf, &rss_conf);
6102 }
6103
6104 static int
6105 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6106                                struct rte_eth_tunnel_filter_conf *filter)
6107 {
6108         if (pf == NULL || filter == NULL) {
6109                 PMD_DRV_LOG(ERR, "Invalid parameter");
6110                 return -EINVAL;
6111         }
6112
6113         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6114                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6115                 return -EINVAL;
6116         }
6117
6118         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6119                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6120                 return -EINVAL;
6121         }
6122
6123         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6124                 (is_zero_ether_addr(filter->outer_mac))) {
6125                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6126                 return -EINVAL;
6127         }
6128
6129         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6130                 (is_zero_ether_addr(filter->inner_mac))) {
6131                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6132                 return -EINVAL;
6133         }
6134
6135         return 0;
6136 }
6137
6138 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6139 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6140 static int
6141 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6142 {
6143         uint32_t val, reg;
6144         int ret = -EINVAL;
6145
6146         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6147         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6148
6149         if (len == 3) {
6150                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6151         } else if (len == 4) {
6152                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6153         } else {
6154                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6155                 return ret;
6156         }
6157
6158         if (reg != val) {
6159                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6160                                                    reg, NULL);
6161                 if (ret != 0)
6162                         return ret;
6163         } else {
6164                 ret = 0;
6165         }
6166         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6167                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6168
6169         return ret;
6170 }
6171
6172 static int
6173 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6174 {
6175         int ret = -EINVAL;
6176
6177         if (!hw || !cfg)
6178                 return -EINVAL;
6179
6180         switch (cfg->cfg_type) {
6181         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6182                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6183                 break;
6184         default:
6185                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6186                 break;
6187         }
6188
6189         return ret;
6190 }
6191
6192 static int
6193 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6194                                enum rte_filter_op filter_op,
6195                                void *arg)
6196 {
6197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6198         int ret = I40E_ERR_PARAM;
6199
6200         switch (filter_op) {
6201         case RTE_ETH_FILTER_SET:
6202                 ret = i40e_dev_global_config_set(hw,
6203                         (struct rte_eth_global_cfg *)arg);
6204                 break;
6205         default:
6206                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6207                 break;
6208         }
6209
6210         return ret;
6211 }
6212
6213 static int
6214 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6215                           enum rte_filter_op filter_op,
6216                           void *arg)
6217 {
6218         struct rte_eth_tunnel_filter_conf *filter;
6219         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6220         int ret = I40E_SUCCESS;
6221
6222         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6223
6224         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6225                 return I40E_ERR_PARAM;
6226
6227         switch (filter_op) {
6228         case RTE_ETH_FILTER_NOP:
6229                 if (!(pf->flags & I40E_FLAG_VXLAN))
6230                         ret = I40E_NOT_SUPPORTED;
6231                 break;
6232         case RTE_ETH_FILTER_ADD:
6233                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6234                 break;
6235         case RTE_ETH_FILTER_DELETE:
6236                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6237                 break;
6238         default:
6239                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6240                 ret = I40E_ERR_PARAM;
6241                 break;
6242         }
6243
6244         return ret;
6245 }
6246
6247 static int
6248 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6249 {
6250         int ret = 0;
6251         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6252
6253         /* RSS setup */
6254         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6255                 ret = i40e_pf_config_rss(pf);
6256         else
6257                 i40e_pf_disable_rss(pf);
6258
6259         return ret;
6260 }
6261
6262 /* Get the symmetric hash enable configurations per port */
6263 static void
6264 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6265 {
6266         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6267
6268         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6269 }
6270
6271 /* Set the symmetric hash enable configurations per port */
6272 static void
6273 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6274 {
6275         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6276
6277         if (enable > 0) {
6278                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6279                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6280                                                         "been enabled");
6281                         return;
6282                 }
6283                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6284         } else {
6285                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6286                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6287                                                         "been disabled");
6288                         return;
6289                 }
6290                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6291         }
6292         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6293         I40E_WRITE_FLUSH(hw);
6294 }
6295
6296 /*
6297  * Get global configurations of hash function type and symmetric hash enable
6298  * per flow type (pctype). Note that global configuration means it affects all
6299  * the ports on the same NIC.
6300  */
6301 static int
6302 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6303                                    struct rte_eth_hash_global_conf *g_cfg)
6304 {
6305         uint32_t reg, mask = I40E_FLOW_TYPES;
6306         uint16_t i;
6307         enum i40e_filter_pctype pctype;
6308
6309         memset(g_cfg, 0, sizeof(*g_cfg));
6310         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6311         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6312                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6313         else
6314                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6315         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6316                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6317
6318         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6319                 if (!(mask & (1UL << i)))
6320                         continue;
6321                 mask &= ~(1UL << i);
6322                 /* Bit set indicats the coresponding flow type is supported */
6323                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6324                 pctype = i40e_flowtype_to_pctype(i);
6325                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6326                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6327                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6328         }
6329
6330         return 0;
6331 }
6332
6333 static int
6334 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6335 {
6336         uint32_t i;
6337         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6338
6339         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6340                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6341                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6342                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6343                                                 g_cfg->hash_func);
6344                 return -EINVAL;
6345         }
6346
6347         /*
6348          * As i40e supports less than 32 flow types, only first 32 bits need to
6349          * be checked.
6350          */
6351         mask0 = g_cfg->valid_bit_mask[0];
6352         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6353                 if (i == 0) {
6354                         /* Check if any unsupported flow type configured */
6355                         if ((mask0 | i40e_mask) ^ i40e_mask)
6356                                 goto mask_err;
6357                 } else {
6358                         if (g_cfg->valid_bit_mask[i])
6359                                 goto mask_err;
6360                 }
6361         }
6362
6363         return 0;
6364
6365 mask_err:
6366         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6367
6368         return -EINVAL;
6369 }
6370
6371 /*
6372  * Set global configurations of hash function type and symmetric hash enable
6373  * per flow type (pctype). Note any modifying global configuration will affect
6374  * all the ports on the same NIC.
6375  */
6376 static int
6377 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6378                                    struct rte_eth_hash_global_conf *g_cfg)
6379 {
6380         int ret;
6381         uint16_t i;
6382         uint32_t reg;
6383         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6384         enum i40e_filter_pctype pctype;
6385
6386         /* Check the input parameters */
6387         ret = i40e_hash_global_config_check(g_cfg);
6388         if (ret < 0)
6389                 return ret;
6390
6391         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6392                 if (!(mask0 & (1UL << i)))
6393                         continue;
6394                 mask0 &= ~(1UL << i);
6395                 pctype = i40e_flowtype_to_pctype(i);
6396                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6397                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6398                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6399         }
6400
6401         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6402         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6403                 /* Toeplitz */
6404                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6405                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6406                                                                 "Toeplitz");
6407                         goto out;
6408                 }
6409                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6410         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6411                 /* Simple XOR */
6412                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6413                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6414                                                         "Simple XOR");
6415                         goto out;
6416                 }
6417                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6418         } else
6419                 /* Use the default, and keep it as it is */
6420                 goto out;
6421
6422         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6423
6424 out:
6425         I40E_WRITE_FLUSH(hw);
6426
6427         return 0;
6428 }
6429
6430 /**
6431  * Valid input sets for hash and flow director filters per PCTYPE
6432  */
6433 static uint64_t
6434 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6435                 enum rte_filter_type filter)
6436 {
6437         uint64_t valid;
6438
6439         static const uint64_t valid_hash_inset_table[] = {
6440                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6441                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6442                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6443                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6444                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6445                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6446                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6447                         I40E_INSET_FLEX_PAYLOAD,
6448                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6449                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6450                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6451                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6452                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6453                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6454                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6455                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6456                         I40E_INSET_FLEX_PAYLOAD,
6457                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6458                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6459                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6460                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6461                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6462                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6463                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6464                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6465                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6466                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6467                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6468                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6469                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6470                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6471                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6472                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6473                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6474                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6475                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6476                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6477                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6478                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6479                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6480                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6481                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6482                         I40E_INSET_FLEX_PAYLOAD,
6483                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6484                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6485                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6486                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6487                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6488                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6489                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6490                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6491                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6492                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6493                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6494                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6495                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6496                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6497                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6498                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6499                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6503                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6504                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6505                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6506                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6507                         I40E_INSET_FLEX_PAYLOAD,
6508                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6509                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6510                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6511                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6512                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6513                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6514                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6515                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6516                         I40E_INSET_FLEX_PAYLOAD,
6517                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6521                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6522                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6523                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6524                         I40E_INSET_FLEX_PAYLOAD,
6525                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6526                         I40E_INSET_DMAC | I40E_INSET_SMAC |
6527                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6528                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6529                         I40E_INSET_FLEX_PAYLOAD,
6530         };
6531
6532         /**
6533          * Flow director supports only fields defined in
6534          * union rte_eth_fdir_flow.
6535          */
6536         static const uint64_t valid_fdir_inset_table[] = {
6537                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6538                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6539                 I40E_INSET_FLEX_PAYLOAD,
6540                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6541                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6542                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6543                 I40E_INSET_FLEX_PAYLOAD,
6544                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6545                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6546                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6547                 I40E_INSET_FLEX_PAYLOAD,
6548                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6549                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6550                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6551                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6552                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6553                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6554                 I40E_INSET_FLEX_PAYLOAD,
6555                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6556                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6557                 I40E_INSET_FLEX_PAYLOAD,
6558                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6559                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6560                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6561                 I40E_INSET_FLEX_PAYLOAD,
6562                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6563                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6564                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6565                 I40E_INSET_FLEX_PAYLOAD,
6566                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6567                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6568                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6569                 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6570                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6571                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6572                 I40E_INSET_FLEX_PAYLOAD,
6573                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6574                 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6575         };
6576
6577         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6578                 return 0;
6579         if (filter == RTE_ETH_FILTER_HASH)
6580                 valid = valid_hash_inset_table[pctype];
6581         else
6582                 valid = valid_fdir_inset_table[pctype];
6583
6584         return valid;
6585 }
6586
6587 /**
6588  * Validate if the input set is allowed for a specific PCTYPE
6589  */
6590 static int
6591 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6592                 enum rte_filter_type filter, uint64_t inset)
6593 {
6594         uint64_t valid;
6595
6596         valid = i40e_get_valid_input_set(pctype, filter);
6597         if (inset & (~valid))
6598                 return -EINVAL;
6599
6600         return 0;
6601 }
6602
6603 /* default input set fields combination per pctype */
6604 static uint64_t
6605 i40e_get_default_input_set(uint16_t pctype)
6606 {
6607         static const uint64_t default_inset_table[] = {
6608                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6609                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6610                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6611                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6612                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6613                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6614                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6615                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6616                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6617                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6618                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6619                         I40E_INSET_SCTP_VT,
6620                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6621                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6622                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6623                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6624                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6625                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6626                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6627                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6628                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6629                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6630                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6631                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6632                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6633                         I40E_INSET_SCTP_VT,
6634                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6635                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6636                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6637                         I40E_INSET_LAST_ETHER_TYPE,
6638         };
6639
6640         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6641                 return 0;
6642
6643         return default_inset_table[pctype];
6644 }
6645
6646 /**
6647  * Parse the input set from index to logical bit masks
6648  */
6649 static int
6650 i40e_parse_input_set(uint64_t *inset,
6651                      enum i40e_filter_pctype pctype,
6652                      enum rte_eth_input_set_field *field,
6653                      uint16_t size)
6654 {
6655         uint16_t i, j;
6656         int ret = -EINVAL;
6657
6658         static const struct {
6659                 enum rte_eth_input_set_field field;
6660                 uint64_t inset;
6661         } inset_convert_table[] = {
6662                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6663                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6664                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6665                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6666                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6667                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6668                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6669                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6670                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6671                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6672                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6673                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6674                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6675                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6676                         I40E_INSET_IPV6_NEXT_HDR},
6677                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6678                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6679                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6680                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6681                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6682                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6683                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6684                         I40E_INSET_SCTP_VT},
6685                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6686                         I40E_INSET_TUNNEL_DMAC},
6687                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6688                         I40E_INSET_VLAN_TUNNEL},
6689                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6690                         I40E_INSET_TUNNEL_ID},
6691                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6692                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6693                         I40E_INSET_FLEX_PAYLOAD_W1},
6694                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6695                         I40E_INSET_FLEX_PAYLOAD_W2},
6696                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6697                         I40E_INSET_FLEX_PAYLOAD_W3},
6698                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6699                         I40E_INSET_FLEX_PAYLOAD_W4},
6700                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6701                         I40E_INSET_FLEX_PAYLOAD_W5},
6702                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6703                         I40E_INSET_FLEX_PAYLOAD_W6},
6704                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6705                         I40E_INSET_FLEX_PAYLOAD_W7},
6706                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6707                         I40E_INSET_FLEX_PAYLOAD_W8},
6708         };
6709
6710         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6711                 return ret;
6712
6713         /* Only one item allowed for default or all */
6714         if (size == 1) {
6715                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6716                         *inset = i40e_get_default_input_set(pctype);
6717                         return 0;
6718                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6719                         *inset = I40E_INSET_NONE;
6720                         return 0;
6721                 }
6722         }
6723
6724         for (i = 0, *inset = 0; i < size; i++) {
6725                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6726                         if (field[i] == inset_convert_table[j].field) {
6727                                 *inset |= inset_convert_table[j].inset;
6728                                 break;
6729                         }
6730                 }
6731
6732                 /* It contains unsupported input set, return immediately */
6733                 if (j == RTE_DIM(inset_convert_table))
6734                         return ret;
6735         }
6736
6737         return 0;
6738 }
6739
6740 /**
6741  * Translate the input set from bit masks to register aware bit masks
6742  * and vice versa
6743  */
6744 static uint64_t
6745 i40e_translate_input_set_reg(uint64_t input)
6746 {
6747         uint64_t val = 0;
6748         uint16_t i;
6749
6750         static const struct {
6751                 uint64_t inset;
6752                 uint64_t inset_reg;
6753         } inset_map[] = {
6754                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6755                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6756                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6757                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6758                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6759                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6760                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6761                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6762                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6763                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6764                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6765                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6766                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6767                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6768                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6769                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6770                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6771                 {I40E_INSET_TUNNEL_DMAC,
6772                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6773                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6774                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6775                 {I40E_INSET_TUNNEL_SRC_PORT,
6776                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6777                 {I40E_INSET_TUNNEL_DST_PORT,
6778                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6779                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6780                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6781                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6782                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6783                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6784                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6785                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6786                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6787                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6788         };
6789
6790         if (input == 0)
6791                 return val;
6792
6793         /* Translate input set to register aware inset */
6794         for (i = 0; i < RTE_DIM(inset_map); i++) {
6795                 if (input & inset_map[i].inset)
6796                         val |= inset_map[i].inset_reg;
6797         }
6798
6799         return val;
6800 }
6801
6802 static uint8_t
6803 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6804 {
6805         uint8_t i, idx = 0;
6806
6807         static const struct {
6808                 uint64_t inset;
6809                 uint32_t mask;
6810         } inset_mask_map[] = {
6811                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6812                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6813                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6814                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6815         };
6816
6817         if (!inset || !mask || !nb_elem)
6818                 return 0;
6819
6820         if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6821                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6822                         mask[i] = 0;
6823                 return I40E_INSET_MASK_NUM_REG;
6824         }
6825
6826         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6827                 if (idx >= nb_elem)
6828                         break;
6829                 if (inset & inset_mask_map[i].inset) {
6830                         mask[idx] = inset_mask_map[i].mask;
6831                         idx++;
6832                 }
6833         }
6834
6835         return idx;
6836 }
6837
6838 static uint64_t
6839 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6840                             enum i40e_filter_pctype pctype)
6841 {
6842         uint64_t reg = 0;
6843
6844         if (filter == RTE_ETH_FILTER_HASH) {
6845                 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6846                 reg <<= I40E_32_BIT_WIDTH;
6847                 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6848         } else if (filter == RTE_ETH_FILTER_FDIR) {
6849                 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6850                 reg <<= I40E_32_BIT_WIDTH;
6851                 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6852         }
6853
6854         return reg;
6855 }
6856
6857 static void
6858 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6859 {
6860         uint32_t reg = I40E_READ_REG(hw, addr);
6861
6862         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6863         if (reg != val)
6864                 I40E_WRITE_REG(hw, addr, val);
6865         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6866                     (uint32_t)I40E_READ_REG(hw, addr));
6867 }
6868
6869 static int
6870 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6871                          enum i40e_filter_pctype pctype,
6872                          enum rte_filter_input_set_op op,
6873                          uint32_t *mask_reg,
6874                          uint8_t num)
6875 {
6876         uint32_t reg;
6877         uint8_t i;
6878
6879         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6880                 return -EINVAL;
6881
6882         if (op == RTE_ETH_INPUT_SET_SELECT) {
6883                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6884                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6885                                              0);
6886                         if (i >= num)
6887                                 continue;
6888                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6889                                              mask_reg[i]);
6890                 }
6891         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6892                 uint8_t j, count = 0;
6893
6894                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6895                         reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6896                         if (reg & I40E_GLQF_HASH_MSK_FIELD)
6897                                 count++;
6898                 }
6899                 if (count + num > I40E_INSET_MASK_NUM_REG)
6900                         return -EINVAL;
6901
6902                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6903                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6904                                              mask_reg[j]);
6905         }
6906
6907         return 0;
6908 }
6909
6910 static int
6911 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6912                        enum i40e_filter_pctype pctype,
6913                        enum rte_filter_input_set_op op,
6914                        uint32_t *mask_reg,
6915                        uint8_t num)
6916 {
6917         uint32_t reg;
6918         uint8_t i;
6919
6920         if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6921                 return -EINVAL;
6922
6923         if (op == RTE_ETH_INPUT_SET_SELECT) {
6924                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6925                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6926                                              0);
6927                         if (i >= num)
6928                                 continue;
6929                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6930                                              mask_reg[i]);
6931                 }
6932         } else if (op == RTE_ETH_INPUT_SET_ADD) {
6933                 uint8_t j, count = 0;
6934
6935                 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6936                         reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6937                         if (reg & I40E_GLQF_FD_MSK_FIELD)
6938                                 count++;
6939                 }
6940                 if (count + num > I40E_INSET_MASK_NUM_REG)
6941                         return -EINVAL;
6942
6943                 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6944                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6945                                              mask_reg[j]);
6946         }
6947
6948         return 0;
6949 }
6950
6951 int
6952 i40e_filter_inset_select(struct i40e_hw *hw,
6953                          struct rte_eth_input_set_conf *conf,
6954                          enum rte_filter_type filter)
6955 {
6956         enum i40e_filter_pctype pctype;
6957         uint64_t inset_reg = 0, input_set;
6958         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6959         uint8_t num;
6960         int ret;
6961
6962         if (!hw || !conf) {
6963                 PMD_DRV_LOG(ERR, "Invalid pointer");
6964                 return -EFAULT;
6965         }
6966
6967         pctype = i40e_flowtype_to_pctype(conf->flow_type);
6968         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6969                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6970                             conf->flow_type);
6971                 return -EINVAL;
6972         }
6973         if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6974                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6975                 return -EINVAL;
6976         }
6977
6978         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6979                                    conf->inset_size);
6980         if (ret) {
6981                 PMD_DRV_LOG(ERR, "Failed to parse input set");
6982                 return -EINVAL;
6983         }
6984         if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6985                 PMD_DRV_LOG(ERR, "Invalid input set");
6986                 return -EINVAL;
6987         }
6988
6989         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6990                 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6991         } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6992                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6993                 return -EINVAL;
6994         }
6995         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6996                                            I40E_INSET_MASK_NUM_REG);
6997         inset_reg |= i40e_translate_input_set_reg(input_set);
6998
6999         if (filter == RTE_ETH_FILTER_HASH) {
7000                 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7001                                                num);
7002                 if (ret)
7003                         return -EINVAL;
7004
7005                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7006                                       (uint32_t)(inset_reg & UINT32_MAX));
7007                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7008                                      (uint32_t)((inset_reg >>
7009                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7010         } else if (filter == RTE_ETH_FILTER_FDIR) {
7011                 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7012                                              num);
7013                 if (ret)
7014                         return -EINVAL;
7015
7016                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7017                                       (uint32_t)(inset_reg & UINT32_MAX));
7018                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7019                                      (uint32_t)((inset_reg >>
7020                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7021         } else {
7022                 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7023                 return -EINVAL;
7024         }
7025         I40E_WRITE_FLUSH(hw);
7026
7027         return 0;
7028 }
7029
7030 static int
7031 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7032 {
7033         int ret = 0;
7034
7035         if (!hw || !info) {
7036                 PMD_DRV_LOG(ERR, "Invalid pointer");
7037                 return -EFAULT;
7038         }
7039
7040         switch (info->info_type) {
7041         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7042                 i40e_get_symmetric_hash_enable_per_port(hw,
7043                                         &(info->info.enable));
7044                 break;
7045         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7046                 ret = i40e_get_hash_filter_global_config(hw,
7047                                 &(info->info.global_conf));
7048                 break;
7049         default:
7050                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7051                                                         info->info_type);
7052                 ret = -EINVAL;
7053                 break;
7054         }
7055
7056         return ret;
7057 }
7058
7059 static int
7060 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7061 {
7062         int ret = 0;
7063
7064         if (!hw || !info) {
7065                 PMD_DRV_LOG(ERR, "Invalid pointer");
7066                 return -EFAULT;
7067         }
7068
7069         switch (info->info_type) {
7070         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7071                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7072                 break;
7073         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7074                 ret = i40e_set_hash_filter_global_config(hw,
7075                                 &(info->info.global_conf));
7076                 break;
7077         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7078                 ret = i40e_filter_inset_select(hw,
7079                                                &(info->info.input_set_conf),
7080                                                RTE_ETH_FILTER_HASH);
7081                 break;
7082
7083         default:
7084                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7085                                                         info->info_type);
7086                 ret = -EINVAL;
7087                 break;
7088         }
7089
7090         return ret;
7091 }
7092
7093 /* Operations for hash function */
7094 static int
7095 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7096                       enum rte_filter_op filter_op,
7097                       void *arg)
7098 {
7099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7100         int ret = 0;
7101
7102         switch (filter_op) {
7103         case RTE_ETH_FILTER_NOP:
7104                 break;
7105         case RTE_ETH_FILTER_GET:
7106                 ret = i40e_hash_filter_get(hw,
7107                         (struct rte_eth_hash_filter_info *)arg);
7108                 break;
7109         case RTE_ETH_FILTER_SET:
7110                 ret = i40e_hash_filter_set(hw,
7111                         (struct rte_eth_hash_filter_info *)arg);
7112                 break;
7113         default:
7114                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7115                                                                 filter_op);
7116                 ret = -ENOTSUP;
7117                 break;
7118         }
7119
7120         return ret;
7121 }
7122
7123 /*
7124  * Configure ethertype filter, which can director packet by filtering
7125  * with mac address and ether_type or only ether_type
7126  */
7127 static int
7128 i40e_ethertype_filter_set(struct i40e_pf *pf,
7129                         struct rte_eth_ethertype_filter *filter,
7130                         bool add)
7131 {
7132         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7133         struct i40e_control_filter_stats stats;
7134         uint16_t flags = 0;
7135         int ret;
7136
7137         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7138                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7139                 return -EINVAL;
7140         }
7141         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7142                 filter->ether_type == ETHER_TYPE_IPv6) {
7143                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7144                         " control packet filter.", filter->ether_type);
7145                 return -EINVAL;
7146         }
7147         if (filter->ether_type == ETHER_TYPE_VLAN)
7148                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7149                         " not supported.");
7150
7151         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7152                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7153         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7154                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7155         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7156
7157         memset(&stats, 0, sizeof(stats));
7158         ret = i40e_aq_add_rem_control_packet_filter(hw,
7159                         filter->mac_addr.addr_bytes,
7160                         filter->ether_type, flags,
7161                         pf->main_vsi->seid,
7162                         filter->queue, add, &stats, NULL);
7163
7164         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7165                          " mac_etype_used = %u, etype_used = %u,"
7166                          " mac_etype_free = %u, etype_free = %u\n",
7167                          ret, stats.mac_etype_used, stats.etype_used,
7168                          stats.mac_etype_free, stats.etype_free);
7169         if (ret < 0)
7170                 return -ENOSYS;
7171         return 0;
7172 }
7173
7174 /*
7175  * Handle operations for ethertype filter.
7176  */
7177 static int
7178 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7179                                 enum rte_filter_op filter_op,
7180                                 void *arg)
7181 {
7182         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7183         int ret = 0;
7184
7185         if (filter_op == RTE_ETH_FILTER_NOP)
7186                 return ret;
7187
7188         if (arg == NULL) {
7189                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7190                             filter_op);
7191                 return -EINVAL;
7192         }
7193
7194         switch (filter_op) {
7195         case RTE_ETH_FILTER_ADD:
7196                 ret = i40e_ethertype_filter_set(pf,
7197                         (struct rte_eth_ethertype_filter *)arg,
7198                         TRUE);
7199                 break;
7200         case RTE_ETH_FILTER_DELETE:
7201                 ret = i40e_ethertype_filter_set(pf,
7202                         (struct rte_eth_ethertype_filter *)arg,
7203                         FALSE);
7204                 break;
7205         default:
7206                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7207                 ret = -ENOSYS;
7208                 break;
7209         }
7210         return ret;
7211 }
7212
7213 static int
7214 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7215                      enum rte_filter_type filter_type,
7216                      enum rte_filter_op filter_op,
7217                      void *arg)
7218 {
7219         int ret = 0;
7220
7221         if (dev == NULL)
7222                 return -EINVAL;
7223
7224         switch (filter_type) {
7225         case RTE_ETH_FILTER_NONE:
7226                 /* For global configuration */
7227                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7228                 break;
7229         case RTE_ETH_FILTER_HASH:
7230                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7231                 break;
7232         case RTE_ETH_FILTER_MACVLAN:
7233                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7234                 break;
7235         case RTE_ETH_FILTER_ETHERTYPE:
7236                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7237                 break;
7238         case RTE_ETH_FILTER_TUNNEL:
7239                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7240                 break;
7241         case RTE_ETH_FILTER_FDIR:
7242                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7243                 break;
7244         default:
7245                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7246                                                         filter_type);
7247                 ret = -EINVAL;
7248                 break;
7249         }
7250
7251         return ret;
7252 }
7253
7254 /*
7255  * As some registers wouldn't be reset unless a global hardware reset,
7256  * hardware initialization is needed to put those registers into an
7257  * expected initial state.
7258  */
7259 static void
7260 i40e_hw_init(struct i40e_hw *hw)
7261 {
7262         /* clear the PF Queue Filter control register */
7263         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7264
7265         /* Disable symmetric hash per port */
7266         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7267 }
7268
7269 enum i40e_filter_pctype
7270 i40e_flowtype_to_pctype(uint16_t flow_type)
7271 {
7272         static const enum i40e_filter_pctype pctype_table[] = {
7273                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7274                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7275                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7276                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7277                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7278                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7279                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7280                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7281                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7282                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7283                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7284                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7285                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7286                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7287                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7288                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7289                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7290                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7291                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7292         };
7293
7294         return pctype_table[flow_type];
7295 }
7296
7297 uint16_t
7298 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7299 {
7300         static const uint16_t flowtype_table[] = {
7301                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7302                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7303                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7304                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7305                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7306                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7307                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7308                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7309                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7310                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7311                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7312                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7313                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7314                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7315                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7316                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7317                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7318                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7319                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7320         };
7321
7322         return flowtype_table[pctype];
7323 }
7324
7325 /*
7326  * On X710, performance number is far from the expectation on recent firmware
7327  * versions; on XL710, performance number is also far from the expectation on
7328  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7329  * mode is enabled and port MAC address is equal to the packet destination MAC
7330  * address. The fix for this issue may not be integrated in the following
7331  * firmware version. So the workaround in software driver is needed. It needs
7332  * to modify the initial values of 3 internal only registers for both X710 and
7333  * XL710. Note that the values for X710 or XL710 could be different, and the
7334  * workaround can be removed when it is fixed in firmware in the future.
7335  */
7336
7337 /* For both X710 and XL710 */
7338 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7339 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
7340
7341 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7342 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
7343
7344 /* For X710 */
7345 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
7346 /* For XL710 */
7347 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
7348 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
7349
7350 static void
7351 i40e_configure_registers(struct i40e_hw *hw)
7352 {
7353         static struct {
7354                 uint32_t addr;
7355                 uint64_t val;
7356         } reg_table[] = {
7357                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7358                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7359                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7360         };
7361         uint64_t reg;
7362         uint32_t i;
7363         int ret;
7364
7365         for (i = 0; i < RTE_DIM(reg_table); i++) {
7366                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7367                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7368                                 reg_table[i].val =
7369                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7370                         else /* For X710 */
7371                                 reg_table[i].val =
7372                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7373                 }
7374
7375                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7376                                                         &reg, NULL);
7377                 if (ret < 0) {
7378                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7379                                                         reg_table[i].addr);
7380                         break;
7381                 }
7382                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7383                                                 reg_table[i].addr, reg);
7384                 if (reg == reg_table[i].val)
7385                         continue;
7386
7387                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7388                                                 reg_table[i].val, NULL);
7389                 if (ret < 0) {
7390                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7391                                 "address of 0x%"PRIx32, reg_table[i].val,
7392                                                         reg_table[i].addr);
7393                         break;
7394                 }
7395                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7396                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7397         }
7398 }
7399
7400 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
7401 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
7402 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
7403 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7404 static int
7405 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7406 {
7407         uint32_t reg;
7408         int ret;
7409
7410         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7411                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7412                 return -EINVAL;
7413         }
7414
7415         /* Configure for double VLAN RX stripping */
7416         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7417         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7418                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7419                 ret = i40e_aq_debug_write_register(hw,
7420                                                    I40E_VSI_TSR(vsi->vsi_id),
7421                                                    reg, NULL);
7422                 if (ret < 0) {
7423                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7424                                     vsi->vsi_id);
7425                         return I40E_ERR_CONFIG;
7426                 }
7427         }
7428
7429         /* Configure for double VLAN TX insertion */
7430         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7431         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7432                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7433                 ret = i40e_aq_debug_write_register(hw,
7434                                                    I40E_VSI_L2TAGSTXVALID(
7435                                                    vsi->vsi_id), reg, NULL);
7436                 if (ret < 0) {
7437                         PMD_DRV_LOG(ERR, "Failed to update "
7438                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7439                         return I40E_ERR_CONFIG;
7440                 }
7441         }
7442
7443         return 0;
7444 }
7445
7446 /**
7447  * i40e_aq_add_mirror_rule
7448  * @hw: pointer to the hardware structure
7449  * @seid: VEB seid to add mirror rule to
7450  * @dst_id: destination vsi seid
7451  * @entries: Buffer which contains the entities to be mirrored
7452  * @count: number of entities contained in the buffer
7453  * @rule_id:the rule_id of the rule to be added
7454  *
7455  * Add a mirror rule for a given veb.
7456  *
7457  **/
7458 static enum i40e_status_code
7459 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7460                         uint16_t seid, uint16_t dst_id,
7461                         uint16_t rule_type, uint16_t *entries,
7462                         uint16_t count, uint16_t *rule_id)
7463 {
7464         struct i40e_aq_desc desc;
7465         struct i40e_aqc_add_delete_mirror_rule cmd;
7466         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7467                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7468                 &desc.params.raw;
7469         uint16_t buff_len;
7470         enum i40e_status_code status;
7471
7472         i40e_fill_default_direct_cmd_desc(&desc,
7473                                           i40e_aqc_opc_add_mirror_rule);
7474         memset(&cmd, 0, sizeof(cmd));
7475
7476         buff_len = sizeof(uint16_t) * count;
7477         desc.datalen = rte_cpu_to_le_16(buff_len);
7478         if (buff_len > 0)
7479                 desc.flags |= rte_cpu_to_le_16(
7480                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7481         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7482                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7483         cmd.num_entries = rte_cpu_to_le_16(count);
7484         cmd.seid = rte_cpu_to_le_16(seid);
7485         cmd.destination = rte_cpu_to_le_16(dst_id);
7486
7487         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7488         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7489         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7490                          "rule_id = %u"
7491                          " mirror_rules_used = %u, mirror_rules_free = %u,",
7492                          hw->aq.asq_last_status, resp->rule_id,
7493                          resp->mirror_rules_used, resp->mirror_rules_free);
7494         *rule_id = rte_le_to_cpu_16(resp->rule_id);
7495
7496         return status;
7497 }
7498
7499 /**
7500  * i40e_aq_del_mirror_rule
7501  * @hw: pointer to the hardware structure
7502  * @seid: VEB seid to add mirror rule to
7503  * @entries: Buffer which contains the entities to be mirrored
7504  * @count: number of entities contained in the buffer
7505  * @rule_id:the rule_id of the rule to be delete
7506  *
7507  * Delete a mirror rule for a given veb.
7508  *
7509  **/
7510 static enum i40e_status_code
7511 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7512                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7513                 uint16_t count, uint16_t rule_id)
7514 {
7515         struct i40e_aq_desc desc;
7516         struct i40e_aqc_add_delete_mirror_rule cmd;
7517         uint16_t buff_len = 0;
7518         enum i40e_status_code status;
7519         void *buff = NULL;
7520
7521         i40e_fill_default_direct_cmd_desc(&desc,
7522                                           i40e_aqc_opc_delete_mirror_rule);
7523         memset(&cmd, 0, sizeof(cmd));
7524         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7525                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7526                                                           I40E_AQ_FLAG_RD));
7527                 cmd.num_entries = count;
7528                 buff_len = sizeof(uint16_t) * count;
7529                 desc.datalen = rte_cpu_to_le_16(buff_len);
7530                 buff = (void *)entries;
7531         } else
7532                 /* rule id is filled in destination field for deleting mirror rule */
7533                 cmd.destination = rte_cpu_to_le_16(rule_id);
7534
7535         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7536                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7537         cmd.seid = rte_cpu_to_le_16(seid);
7538
7539         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7540         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7541
7542         return status;
7543 }
7544
7545 /**
7546  * i40e_mirror_rule_set
7547  * @dev: pointer to the hardware structure
7548  * @mirror_conf: mirror rule info
7549  * @sw_id: mirror rule's sw_id
7550  * @on: enable/disable
7551  *
7552  * set a mirror rule.
7553  *
7554  **/
7555 static int
7556 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7557                         struct rte_eth_mirror_conf *mirror_conf,
7558                         uint8_t sw_id, uint8_t on)
7559 {
7560         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7561         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7562         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7563         struct i40e_mirror_rule *parent = NULL;
7564         uint16_t seid, dst_seid, rule_id;
7565         uint16_t i, j = 0;
7566         int ret;
7567
7568         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7569
7570         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7571                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7572                         " without veb or vfs.");
7573                 return -ENOSYS;
7574         }
7575         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7576                 PMD_DRV_LOG(ERR, "mirror table is full.");
7577                 return -ENOSPC;
7578         }
7579         if (mirror_conf->dst_pool > pf->vf_num) {
7580                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7581                                  mirror_conf->dst_pool);
7582                 return -EINVAL;
7583         }
7584
7585         seid = pf->main_vsi->veb->seid;
7586
7587         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7588                 if (sw_id <= it->index) {
7589                         mirr_rule = it;
7590                         break;
7591                 }
7592                 parent = it;
7593         }
7594         if (mirr_rule && sw_id == mirr_rule->index) {
7595                 if (on) {
7596                         PMD_DRV_LOG(ERR, "mirror rule exists.");
7597                         return -EEXIST;
7598                 } else {
7599                         ret = i40e_aq_del_mirror_rule(hw, seid,
7600                                         mirr_rule->rule_type,
7601                                         mirr_rule->entries,
7602                                         mirr_rule->num_entries, mirr_rule->id);
7603                         if (ret < 0) {
7604                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7605                                                    " ret = %d, aq_err = %d.",
7606                                                    ret, hw->aq.asq_last_status);
7607                                 return -ENOSYS;
7608                         }
7609                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7610                         rte_free(mirr_rule);
7611                         pf->nb_mirror_rule--;
7612                         return 0;
7613                 }
7614         } else if (!on) {
7615                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7616                 return -ENOENT;
7617         }
7618
7619         mirr_rule = rte_zmalloc("i40e_mirror_rule",
7620                                 sizeof(struct i40e_mirror_rule) , 0);
7621         if (!mirr_rule) {
7622                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7623                 return I40E_ERR_NO_MEMORY;
7624         }
7625         switch (mirror_conf->rule_type) {
7626         case ETH_MIRROR_VLAN:
7627                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7628                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7629                                 mirr_rule->entries[j] =
7630                                         mirror_conf->vlan.vlan_id[i];
7631                                 j++;
7632                         }
7633                 }
7634                 if (j == 0) {
7635                         PMD_DRV_LOG(ERR, "vlan is not specified.");
7636                         rte_free(mirr_rule);
7637                         return -EINVAL;
7638                 }
7639                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7640                 break;
7641         case ETH_MIRROR_VIRTUAL_POOL_UP:
7642         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7643                 /* check if the specified pool bit is out of range */
7644                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7645                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
7646                         rte_free(mirr_rule);
7647                         return -EINVAL;
7648                 }
7649                 for (i = 0, j = 0; i < pf->vf_num; i++) {
7650                         if (mirror_conf->pool_mask & (1ULL << i)) {
7651                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7652                                 j++;
7653                         }
7654                 }
7655                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7656                         /* add pf vsi to entries */
7657                         mirr_rule->entries[j] = pf->main_vsi_seid;
7658                         j++;
7659                 }
7660                 if (j == 0) {
7661                         PMD_DRV_LOG(ERR, "pool is not specified.");
7662                         rte_free(mirr_rule);
7663                         return -EINVAL;
7664                 }
7665                 /* egress and ingress in aq commands means from switch but not port */
7666                 mirr_rule->rule_type =
7667                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7668                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7669                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7670                 break;
7671         case ETH_MIRROR_UPLINK_PORT:
7672                 /* egress and ingress in aq commands means from switch but not port*/
7673                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7674                 break;
7675         case ETH_MIRROR_DOWNLINK_PORT:
7676                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7677                 break;
7678         default:
7679                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7680                         mirror_conf->rule_type);
7681                 rte_free(mirr_rule);
7682                 return -EINVAL;
7683         }
7684
7685         /* If the dst_pool is equal to vf_num, consider it as PF */
7686         if (mirror_conf->dst_pool == pf->vf_num)
7687                 dst_seid = pf->main_vsi_seid;
7688         else
7689                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7690
7691         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7692                                       mirr_rule->rule_type, mirr_rule->entries,
7693                                       j, &rule_id);
7694         if (ret < 0) {
7695                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7696                                    " ret = %d, aq_err = %d.",
7697                                    ret, hw->aq.asq_last_status);
7698                 rte_free(mirr_rule);
7699                 return -ENOSYS;
7700         }
7701
7702         mirr_rule->index = sw_id;
7703         mirr_rule->num_entries = j;
7704         mirr_rule->id = rule_id;
7705         mirr_rule->dst_vsi_seid = dst_seid;
7706
7707         if (parent)
7708                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7709         else
7710                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7711
7712         pf->nb_mirror_rule++;
7713         return 0;
7714 }
7715
7716 /**
7717  * i40e_mirror_rule_reset
7718  * @dev: pointer to the device
7719  * @sw_id: mirror rule's sw_id
7720  *
7721  * reset a mirror rule.
7722  *
7723  **/
7724 static int
7725 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7726 {
7727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7728         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7729         struct i40e_mirror_rule *it, *mirr_rule = NULL;
7730         uint16_t seid;
7731         int ret;
7732
7733         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7734
7735         seid = pf->main_vsi->veb->seid;
7736
7737         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7738                 if (sw_id == it->index) {
7739                         mirr_rule = it;
7740                         break;
7741                 }
7742         }
7743         if (mirr_rule) {
7744                 ret = i40e_aq_del_mirror_rule(hw, seid,
7745                                 mirr_rule->rule_type,
7746                                 mirr_rule->entries,
7747                                 mirr_rule->num_entries, mirr_rule->id);
7748                 if (ret < 0) {
7749                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7750                                            " status = %d, aq_err = %d.",
7751                                            ret, hw->aq.asq_last_status);
7752                         return -ENOSYS;
7753                 }
7754                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7755                 rte_free(mirr_rule);
7756                 pf->nb_mirror_rule--;
7757         } else {
7758                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7759                 return -ENOENT;
7760         }
7761         return 0;
7762 }
7763
7764 static int
7765 i40e_timesync_enable(struct rte_eth_dev *dev)
7766 {
7767         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7768         struct rte_eth_link *link = &dev->data->dev_link;
7769         uint32_t tsync_ctl_l;
7770         uint32_t tsync_ctl_h;
7771         uint32_t tsync_inc_l;
7772         uint32_t tsync_inc_h;
7773
7774         switch (link->link_speed) {
7775         case ETH_LINK_SPEED_40G:
7776                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7777                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7778                 break;
7779         case ETH_LINK_SPEED_10G:
7780                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7781                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7782                 break;
7783         case ETH_LINK_SPEED_1000:
7784                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7785                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7786                 break;
7787         default:
7788                 tsync_inc_l = 0x0;
7789                 tsync_inc_h = 0x0;
7790         }
7791
7792         /* Clear timesync registers. */
7793         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7794         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7795         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7796         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7797         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7798         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7799         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7800
7801         /* Set the timesync increment value. */
7802         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7803         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7804
7805         /* Enable timestamping of PTP packets. */
7806         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7807         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7808
7809         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7810         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7811         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7812
7813         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7814         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7815
7816         return 0;
7817 }
7818
7819 static int
7820 i40e_timesync_disable(struct rte_eth_dev *dev)
7821 {
7822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7823         uint32_t tsync_ctl_l;
7824         uint32_t tsync_ctl_h;
7825
7826         /* Disable timestamping of transmitted PTP packets. */
7827         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7828         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7829
7830         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7831         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7832
7833         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7834         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7835
7836         /* Set the timesync increment value. */
7837         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7838         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7839
7840         return 0;
7841 }
7842
7843 static int
7844 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7845                                 struct timespec *timestamp, uint32_t flags)
7846 {
7847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7848         uint32_t sync_status;
7849         uint32_t rx_stmpl;
7850         uint32_t rx_stmph;
7851         uint32_t index = flags & 0x03;
7852
7853         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7854         if ((sync_status & (1 << index)) == 0)
7855                 return -EINVAL;
7856
7857         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7858         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7859
7860         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7861         timestamp->tv_nsec = 0;
7862
7863         return  0;
7864 }
7865
7866 static int
7867 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7868                                 struct timespec *timestamp)
7869 {
7870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7871         uint32_t sync_status;
7872         uint32_t tx_stmpl;
7873         uint32_t tx_stmph;
7874
7875         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7876         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7877                 return -EINVAL;
7878
7879         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7880         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7881
7882         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7883         timestamp->tv_nsec = 0;
7884
7885         return  0;
7886 }
7887
7888 /*
7889  * i40e_parse_dcb_configure - parse dcb configure from user
7890  * @dev: the device being configured
7891  * @dcb_cfg: pointer of the result of parse
7892  * @*tc_map: bit map of enabled traffic classes
7893  *
7894  * Returns 0 on success, negative value on failure
7895  */
7896 static int
7897 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7898                          struct i40e_dcbx_config *dcb_cfg,
7899                          uint8_t *tc_map)
7900 {
7901         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7902         uint8_t i, tc_bw, bw_lf;
7903
7904         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7905
7906         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7907         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7908                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7909                 return -EINVAL;
7910         }
7911
7912         /* assume each tc has the same bw */
7913         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7914         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7915                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7916         /* to ensure the sum of tcbw is equal to 100 */
7917         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7918         for (i = 0; i < bw_lf; i++)
7919                 dcb_cfg->etscfg.tcbwtable[i]++;
7920
7921         /* assume each tc has the same Transmission Selection Algorithm */
7922         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7923                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7924
7925         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7926                 dcb_cfg->etscfg.prioritytable[i] =
7927                                 dcb_rx_conf->dcb_tc[i];
7928
7929         /* FW needs one App to configure HW */
7930         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7931         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7932         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7933         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7934
7935         if (dcb_rx_conf->nb_tcs == 0)
7936                 *tc_map = 1; /* tc0 only */
7937         else
7938                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7939
7940         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7941                 dcb_cfg->pfc.willing = 0;
7942                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7943                 dcb_cfg->pfc.pfcenable = *tc_map;
7944         }
7945         return 0;
7946 }
7947
7948 /*
7949  * i40e_vsi_get_bw_info - Query VSI BW Information
7950  * @vsi: the VSI being queried
7951  *
7952  * Returns 0 on success, negative value on failure
7953  */
7954 static enum i40e_status_code
7955 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7956 {
7957         struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7958         struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7959         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7960         enum i40e_status_code ret;
7961         int i;
7962         uint32_t tc_bw_max;
7963
7964         /* Get the VSI level BW configuration */
7965         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7966         if (ret) {
7967                 PMD_INIT_LOG(ERR,
7968                          "couldn't get PF vsi bw config, err %s aq_err %s\n",
7969                          i40e_stat_str(hw, ret),
7970                          i40e_aq_str(hw, hw->aq.asq_last_status));
7971                 return ret;
7972         }
7973
7974         /* Get the VSI level BW configuration per TC */
7975         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7976                                                   NULL);
7977         if (ret) {
7978                 PMD_INIT_LOG(ERR,
7979                          "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7980                          i40e_stat_str(hw, ret),
7981                          i40e_aq_str(hw, hw->aq.asq_last_status));
7982                 return ret;
7983         }
7984
7985         if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7986                 PMD_INIT_LOG(WARNING,
7987                          "Enabled TCs mismatch from querying VSI BW info"
7988                          " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7989                          bw_ets_config.tc_valid_bits);
7990                 /* Still continuing */
7991         }
7992
7993         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7994         vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7995         tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7996                     (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7997         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7998                 vsi->bw_info.bw_ets_share_credits[i] =
7999                                 bw_ets_config.share_credits[i];
8000                 vsi->bw_info.bw_ets_limit_credits[i] =
8001                                 rte_le_to_cpu_16(bw_ets_config.credits[i]);
8002                 /* 3 bits out of 4 for each TC */
8003                 vsi->bw_info.bw_ets_max_quanta[i] =
8004                         (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
8005                 PMD_INIT_LOG(DEBUG,
8006                          "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
8007                          __func__, vsi->seid, i, bw_config.qs_handles[i]);
8008         }
8009
8010         return ret;
8011 }
8012
8013 static enum i40e_status_code
8014 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8015                               struct i40e_aqc_vsi_properties_data *info,
8016                               uint8_t enabled_tcmap)
8017 {
8018         enum i40e_status_code ret;
8019         int i, total_tc = 0;
8020         uint16_t qpnum_per_tc, bsf, qp_idx;
8021         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8022
8023         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8024         if (ret != I40E_SUCCESS)
8025                 return ret;
8026
8027         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8028                 if (enabled_tcmap & (1 << i))
8029                         total_tc++;
8030         }
8031         if (total_tc == 0)
8032                 total_tc = 1;
8033         vsi->enabled_tc = enabled_tcmap;
8034
8035         qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8036         /* Number of queues per enabled TC */
8037         if (qpnum_per_tc == 0) {
8038                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8039                 return I40E_ERR_INVALID_QP_ID;
8040         }
8041         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8042                                 I40E_MAX_Q_PER_TC);
8043         bsf = rte_bsf32(qpnum_per_tc);
8044
8045         /**
8046          * Configure TC and queue mapping parameters, for enabled TC,
8047          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8048          * default queue will serve it.
8049          */
8050         qp_idx = 0;
8051         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8052                 if (vsi->enabled_tc & (1 << i)) {
8053                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8054                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8055                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8056                         qp_idx += qpnum_per_tc;
8057                 } else
8058                         info->tc_mapping[i] = 0;
8059         }
8060
8061         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8062         if (vsi->type == I40E_VSI_SRIOV) {
8063                 info->mapping_flags |=
8064                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8065                 for (i = 0; i < vsi->nb_qps; i++)
8066                         info->queue_mapping[i] =
8067                                 rte_cpu_to_le_16(vsi->base_queue + i);
8068         } else {
8069                 info->mapping_flags |=
8070                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8071                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8072         }
8073         info->valid_sections |=
8074                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8075
8076         return I40E_SUCCESS;
8077 }
8078
8079 /*
8080  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8081  * @vsi: VSI to be configured
8082  * @tc_map: enabled TC bitmap
8083  *
8084  * Returns 0 on success, negative value on failure
8085  */
8086 static enum i40e_status_code
8087 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8088 {
8089         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8090         struct i40e_vsi_context ctxt;
8091         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8092         enum i40e_status_code ret = I40E_SUCCESS;
8093         int i;
8094
8095         /* Check if enabled_tc is same as existing or new TCs */
8096         if (vsi->enabled_tc == tc_map)
8097                 return ret;
8098
8099         /* configure tc bandwidth */
8100         memset(&bw_data, 0, sizeof(bw_data));
8101         bw_data.tc_valid_bits = tc_map;
8102         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8103         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8104                 if (tc_map & BIT_ULL(i))
8105                         bw_data.tc_bw_credits[i] = 1;
8106         }
8107         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8108         if (ret) {
8109                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8110                         " per TC failed = %d",
8111                         hw->aq.asq_last_status);
8112                 goto out;
8113         }
8114         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8115                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8116
8117         /* Update Queue Pairs Mapping for currently enabled UPs */
8118         ctxt.seid = vsi->seid;
8119         ctxt.pf_num = hw->pf_id;
8120         ctxt.vf_num = 0;
8121         ctxt.uplink_seid = vsi->uplink_seid;
8122         ctxt.info = vsi->info;
8123         i40e_get_cap(hw);
8124         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8125         if (ret)
8126                 goto out;
8127
8128         /* Update the VSI after updating the VSI queue-mapping information */
8129         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8130         if (ret) {
8131                 PMD_INIT_LOG(ERR, "Failed to configure "
8132                             "TC queue mapping = %d",
8133                             hw->aq.asq_last_status);
8134                 goto out;
8135         }
8136         /* update the local VSI info with updated queue map */
8137         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8138                                         sizeof(vsi->info.tc_mapping));
8139         (void)rte_memcpy(&vsi->info.queue_mapping,
8140                         &ctxt.info.queue_mapping,
8141                 sizeof(vsi->info.queue_mapping));
8142         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8143         vsi->info.valid_sections = 0;
8144
8145         /* Update current VSI BW information */
8146         ret = i40e_vsi_get_bw_info(vsi);
8147         if (ret) {
8148                 PMD_INIT_LOG(ERR,
8149                          "Failed updating vsi bw info, err %s aq_err %s",
8150                          i40e_stat_str(hw, ret),
8151                          i40e_aq_str(hw, hw->aq.asq_last_status));
8152                 goto out;
8153         }
8154
8155         vsi->enabled_tc = tc_map;
8156
8157 out:
8158         return ret;
8159 }
8160
8161 /*
8162  * i40e_dcb_hw_configure - program the dcb setting to hw
8163  * @pf: pf the configuration is taken on
8164  * @new_cfg: new configuration
8165  * @tc_map: enabled TC bitmap
8166  *
8167  * Returns 0 on success, negative value on failure
8168  */
8169 static enum i40e_status_code
8170 i40e_dcb_hw_configure(struct i40e_pf *pf,
8171                       struct i40e_dcbx_config *new_cfg,
8172                       uint8_t tc_map)
8173 {
8174         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8175         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8176         struct i40e_vsi *main_vsi = pf->main_vsi;
8177         struct i40e_vsi_list *vsi_list;
8178         enum i40e_status_code ret;
8179         int i;
8180         uint32_t val;
8181
8182         /* Use the FW API if FW > v4.4*/
8183         if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8184                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8185                                   " to configure DCB");
8186                 return I40E_ERR_FIRMWARE_API_VERSION;
8187         }
8188
8189         /* Check if need reconfiguration */
8190         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8191                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8192                 return I40E_SUCCESS;
8193         }
8194
8195         /* Copy the new config to the current config */
8196         *old_cfg = *new_cfg;
8197         old_cfg->etsrec = old_cfg->etscfg;
8198         ret = i40e_set_dcb_config(hw);
8199         if (ret) {
8200                 PMD_INIT_LOG(ERR,
8201                          "Set DCB Config failed, err %s aq_err %s\n",
8202                          i40e_stat_str(hw, ret),
8203                          i40e_aq_str(hw, hw->aq.asq_last_status));
8204                 return ret;
8205         }
8206         /* set receive Arbiter to RR mode and ETS scheme by default */
8207         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8208                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8209                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
8210                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8211                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8212                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8213                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8214                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8215                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8216                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8217                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8218                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8219                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8220         }
8221         /* get local mib to check whether it is configured correctly */
8222         /* IEEE mode */
8223         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8224         /* Get Local DCB Config */
8225         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8226                                      &hw->local_dcbx_config);
8227
8228         /* Update each VSI */
8229         i40e_vsi_config_tc(main_vsi, tc_map);
8230         if (main_vsi->veb) {
8231                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8232                         /* Beside main VSI, only enable default
8233                          * TC for other VSIs
8234                          */
8235                         ret = i40e_vsi_config_tc(vsi_list->vsi,
8236                                                 I40E_DEFAULT_TCMAP);
8237                         if (ret)
8238                                 PMD_INIT_LOG(WARNING,
8239                                          "Failed configuring TC for VSI seid=%d\n",
8240                                          vsi_list->vsi->seid);
8241                         /* continue */
8242                 }
8243         }
8244         return I40E_SUCCESS;
8245 }
8246
8247 /*
8248  * i40e_dcb_init_configure - initial dcb config
8249  * @dev: device being configured
8250  * @sw_dcb: indicate whether dcb is sw configured or hw offload
8251  *
8252  * Returns 0 on success, negative value on failure
8253  */
8254 static int
8255 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8256 {
8257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8259         int ret = 0;
8260
8261         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8262                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8263                 return -ENOTSUP;
8264         }
8265
8266         /* DCB initialization:
8267          * Update DCB configuration from the Firmware and configure
8268          * LLDP MIB change event.
8269          */
8270         if (sw_dcb == TRUE) {
8271                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8272                 if (ret != I40E_SUCCESS)
8273                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8274
8275                 ret = i40e_init_dcb(hw);
8276                 /* if sw_dcb, lldp agent is stopped, the return from
8277                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8278                  * adminq status.
8279                  */
8280                 if (ret != I40E_SUCCESS &&
8281                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8282                         memset(&hw->local_dcbx_config, 0,
8283                                 sizeof(struct i40e_dcbx_config));
8284                         /* set dcb default configuration */
8285                         hw->local_dcbx_config.etscfg.willing = 0;
8286                         hw->local_dcbx_config.etscfg.maxtcs = 0;
8287                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8288                         hw->local_dcbx_config.etscfg.tsatable[0] =
8289                                                 I40E_IEEE_TSA_ETS;
8290                         hw->local_dcbx_config.etsrec =
8291                                 hw->local_dcbx_config.etscfg;
8292                         hw->local_dcbx_config.pfc.willing = 0;
8293                         hw->local_dcbx_config.pfc.pfccap =
8294                                                 I40E_MAX_TRAFFIC_CLASS;
8295                         /* FW needs one App to configure HW */
8296                         hw->local_dcbx_config.numapps = 1;
8297                         hw->local_dcbx_config.app[0].selector =
8298                                                 I40E_APP_SEL_ETHTYPE;
8299                         hw->local_dcbx_config.app[0].priority = 3;
8300                         hw->local_dcbx_config.app[0].protocolid =
8301                                                 I40E_APP_PROTOID_FCOE;
8302                         ret = i40e_set_dcb_config(hw);
8303                         if (ret) {
8304                                 PMD_INIT_LOG(ERR, "default dcb config fails."
8305                                         " err = %d, aq_err = %d.", ret,
8306                                           hw->aq.asq_last_status);
8307                                 return -ENOSYS;
8308                         }
8309                 } else {
8310                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8311                                           " aq_err = %d.", ret,
8312                                           hw->aq.asq_last_status);
8313                         return -ENOTSUP;
8314                 }
8315         } else {
8316                 ret = i40e_aq_start_lldp(hw, NULL);
8317                 if (ret != I40E_SUCCESS)
8318                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8319
8320                 ret = i40e_init_dcb(hw);
8321                 if (!ret) {
8322                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8323                                 PMD_INIT_LOG(ERR, "HW doesn't support"
8324                                                   " DCBX offload.");
8325                                 return -ENOTSUP;
8326                         }
8327                 } else {
8328                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8329                                           " aq_err = %d.", ret,
8330                                           hw->aq.asq_last_status);
8331                         return -ENOTSUP;
8332                 }
8333         }
8334         return 0;
8335 }
8336
8337 /*
8338  * i40e_dcb_setup - setup dcb related config
8339  * @dev: device being configured
8340  *
8341  * Returns 0 on success, negative value on failure
8342  */
8343 static int
8344 i40e_dcb_setup(struct rte_eth_dev *dev)
8345 {
8346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8347         struct i40e_dcbx_config dcb_cfg;
8348         uint8_t tc_map = 0;
8349         int ret = 0;
8350
8351         if ((pf->flags & I40E_FLAG_DCB) == 0) {
8352                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8353                 return -ENOTSUP;
8354         }
8355
8356         if (pf->vf_num != 0 ||
8357             (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8358                 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8359
8360         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8361         if (ret) {
8362                 PMD_INIT_LOG(ERR, "invalid dcb config");
8363                 return -EINVAL;
8364         }
8365         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8366         if (ret) {
8367                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8368                 return -ENOSYS;
8369         }
8370
8371         return 0;
8372 }
8373
8374 static int
8375 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8376                       struct rte_eth_dcb_info *dcb_info)
8377 {
8378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8380         struct i40e_vsi *vsi = pf->main_vsi;
8381         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8382         uint16_t bsf, tc_mapping;
8383         int i;
8384
8385         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8386                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8387         else
8388                 dcb_info->nb_tcs = 1;
8389         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8390                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8391         for (i = 0; i < dcb_info->nb_tcs; i++)
8392                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8393
8394         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8395                 if (vsi->enabled_tc & (1 << i)) {
8396                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8397                         /* only main vsi support multi TCs */
8398                         dcb_info->tc_queue.tc_rxq[0][i].base =
8399                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8400                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8401                         dcb_info->tc_queue.tc_txq[0][i].base =
8402                                 dcb_info->tc_queue.tc_rxq[0][i].base;
8403                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8404                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8405                         dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8406                         dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8407                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8408                 }
8409         }
8410
8411         return 0;
8412 }
8413
8414 static int
8415 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8416 {
8417         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8419         uint16_t interval =
8420                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8421         uint16_t msix_intr;
8422
8423         msix_intr = intr_handle->intr_vec[queue_id];
8424         if (msix_intr == I40E_MISC_VEC_ID)
8425                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8426                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8427                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8428                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8429                                (interval <<
8430                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8431         else
8432                 I40E_WRITE_REG(hw,
8433                                I40E_PFINT_DYN_CTLN(msix_intr -
8434                                                    I40E_RX_VEC_START),
8435                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
8436                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8437                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8438                                (interval <<
8439                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8440
8441         I40E_WRITE_FLUSH(hw);
8442         rte_intr_enable(&dev->pci_dev->intr_handle);
8443
8444         return 0;
8445 }
8446
8447 static int
8448 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8449 {
8450         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8452         uint16_t msix_intr;
8453
8454         msix_intr = intr_handle->intr_vec[queue_id];
8455         if (msix_intr == I40E_MISC_VEC_ID)
8456                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8457         else
8458                 I40E_WRITE_REG(hw,
8459                                I40E_PFINT_DYN_CTLN(msix_intr -
8460                                                    I40E_RX_VEC_START),
8461                                0);
8462         I40E_WRITE_FLUSH(hw);
8463
8464         return 0;
8465 }