drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_get_module_info(struct rte_eth_dev *dev,
 373                                 struct rte_eth_dev_module_info *modinfo);
 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 375                                   struct rte_dev_eeprom_info *info);
 376
 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 378                                       struct ether_addr *mac_addr);
 379
 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 381
 382 static int i40e_ethertype_filter_convert(
 383         const struct rte_eth_ethertype_filter *input,
 384         struct i40e_ethertype_filter *filter);
 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 386                                    struct i40e_ethertype_filter *filter);
 387
 388 static int i40e_tunnel_filter_convert(
 389         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 390         struct i40e_tunnel_filter *tunnel_filter);
 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 392                                 struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 394
 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 397 static void i40e_filter_restore(struct i40e_pf *pf);
 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 399
 400 int i40e_logtype_init;
 401 int i40e_logtype_driver;
 402
 403 static const struct rte_pci_id pci_id_i40e_map[] = {
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 424         { .vendor_id = 0, /* sentinel */ },
 425 };
 426
 427 static const struct eth_dev_ops i40e_eth_dev_ops = {
 428         .dev_configure                = i40e_dev_configure,
 429         .dev_start                    = i40e_dev_start,
 430         .dev_stop                     = i40e_dev_stop,
 431         .dev_close                    = i40e_dev_close,
 432         .dev_reset                    = i40e_dev_reset,
 433         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 434         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 435         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 436         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 437         .dev_set_link_up              = i40e_dev_set_link_up,
 438         .dev_set_link_down            = i40e_dev_set_link_down,
 439         .link_update                  = i40e_dev_link_update,
 440         .stats_get                    = i40e_dev_stats_get,
 441         .xstats_get                   = i40e_dev_xstats_get,
 442         .xstats_get_names             = i40e_dev_xstats_get_names,
 443         .stats_reset                  = i40e_dev_stats_reset,
 444         .xstats_reset                 = i40e_dev_stats_reset,
 445         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 446         .fw_version_get               = i40e_fw_version_get,
 447         .dev_infos_get                = i40e_dev_info_get,
 448         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 449         .vlan_filter_set              = i40e_vlan_filter_set,
 450         .vlan_tpid_set                = i40e_vlan_tpid_set,
 451         .vlan_offload_set             = i40e_vlan_offload_set,
 452         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 453         .vlan_pvid_set                = i40e_vlan_pvid_set,
 454         .rx_queue_start               = i40e_dev_rx_queue_start,
 455         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 456         .tx_queue_start               = i40e_dev_tx_queue_start,
 457         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 458         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 459         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 460         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 461         .rx_queue_release             = i40e_dev_rx_queue_release,
 462         .rx_queue_count               = i40e_dev_rx_queue_count,
 463         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 464         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 465         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 466         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 467         .tx_queue_release             = i40e_dev_tx_queue_release,
 468         .dev_led_on                   = i40e_dev_led_on,
 469         .dev_led_off                  = i40e_dev_led_off,
 470         .flow_ctrl_get                = i40e_flow_ctrl_get,
 471         .flow_ctrl_set                = i40e_flow_ctrl_set,
 472         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 473         .mac_addr_add                 = i40e_macaddr_add,
 474         .mac_addr_remove              = i40e_macaddr_remove,
 475         .reta_update                  = i40e_dev_rss_reta_update,
 476         .reta_query                   = i40e_dev_rss_reta_query,
 477         .rss_hash_update              = i40e_dev_rss_hash_update,
 478         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 479         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 480         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 481         .filter_ctrl                  = i40e_dev_filter_ctrl,
 482         .rxq_info_get                 = i40e_rxq_info_get,
 483         .txq_info_get                 = i40e_txq_info_get,
 484         .mirror_rule_set              = i40e_mirror_rule_set,
 485         .mirror_rule_reset            = i40e_mirror_rule_reset,
 486         .timesync_enable              = i40e_timesync_enable,
 487         .timesync_disable             = i40e_timesync_disable,
 488         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 489         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 490         .get_dcb_info                 = i40e_dev_get_dcb_info,
 491         .timesync_adjust_time         = i40e_timesync_adjust_time,
 492         .timesync_read_time           = i40e_timesync_read_time,
 493         .timesync_write_time          = i40e_timesync_write_time,
 494         .get_reg                      = i40e_get_regs,
 495         .get_eeprom_length            = i40e_get_eeprom_length,
 496         .get_eeprom                   = i40e_get_eeprom,
 497         .get_module_info              = i40e_get_module_info,
 498         .get_module_eeprom            = i40e_get_module_eeprom,
 499         .mac_addr_set                 = i40e_set_default_mac_addr,
 500         .mtu_set                      = i40e_dev_mtu_set,
 501         .tm_ops_get                   = i40e_tm_ops_get,
 502 };
 503
 504 /* store statistics names and its offset in stats structure */
 505 struct rte_i40e_xstats_name_off {
 506         char name[RTE_ETH_XSTATS_NAME_SIZE];
 507         unsigned offset;
 508 };
 509
 510 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 511         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 512         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 513         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 514         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 515         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 516                 rx_unknown_protocol)},
 517         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 518         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 519         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 520         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 521 };
 522
 523 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 524                 sizeof(rte_i40e_stats_strings[0]))
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 527         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 528                 tx_dropped_link_down)},
 529         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 530         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 531                 illegal_bytes)},
 532         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 533         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 534                 mac_local_faults)},
 535         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 536                 mac_remote_faults)},
 537         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 538                 rx_length_errors)},
 539         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 540         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 541         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 542         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 543         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 544         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_127)},
 546         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_255)},
 548         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_511)},
 550         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 551                 rx_size_1023)},
 552         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 553                 rx_size_1522)},
 554         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 555                 rx_size_big)},
 556         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_undersize)},
 558         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 559                 rx_oversize)},
 560         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 561                 mac_short_packet_dropped)},
 562         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 563                 rx_fragments)},
 564         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 565         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 566         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_127)},
 568         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_255)},
 570         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_511)},
 572         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 573                 tx_size_1023)},
 574         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 575                 tx_size_1522)},
 576         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 577                 tx_size_big)},
 578         {"rx_flow_director_atr_match_packets",
 579                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 580         {"rx_flow_director_sb_match_packets",
 581                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 582         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 583                 tx_lpi_status)},
 584         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 585                 rx_lpi_status)},
 586         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 587                 tx_lpi_count)},
 588         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 589                 rx_lpi_count)},
 590 };
 591
 592 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 593                 sizeof(rte_i40e_hw_port_strings[0]))
 594
 595 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 596         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 597                 priority_xon_rx)},
 598         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 599                 priority_xoff_rx)},
 600 };
 601
 602 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 603                 sizeof(rte_i40e_rxq_prio_strings[0]))
 604
 605 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 606         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 607                 priority_xon_tx)},
 608         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xoff_tx)},
 610         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 611                 priority_xon_2_xoff)},
 612 };
 613
 614 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 615                 sizeof(rte_i40e_txq_prio_strings[0]))
 616
 617 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 618         struct rte_pci_device *pci_dev)
 619 {
 620         return rte_eth_dev_pci_generic_probe(pci_dev,
 621                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 622 }
 623
 624 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 625 {
 626         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 627 }
 628
 629 static struct rte_pci_driver rte_i40e_pmd = {
 630         .id_table = pci_id_i40e_map,
 631         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 632                      RTE_PCI_DRV_IOVA_AS_VA,
 633         .probe = eth_i40e_pci_probe,
 634         .remove = eth_i40e_pci_remove,
 635 };
 636
 637 static inline void
 638 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 639 {
 640         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 641         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 642                     "with value 0x%08x",
 643                     reg_addr, reg_val);
 644 }
 645
 646 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 647 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 648 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 649
 650 #ifndef I40E_GLQF_ORT
 651 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 652 #endif
 653 #ifndef I40E_GLQF_PIT
 654 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 655 #endif
 656 #ifndef I40E_GLQF_L3_MAP
 657 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 658 #endif
 659
 660 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 661 {
 662         /*
 663          * Initialize registers for parsing packet type of QinQ
 664          * This should be removed from code once proper
 665          * configuration API is added to avoid configuration conflicts
 666          * between ports of the same device.
 667          */
 668         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 669         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 670         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 671 }
 672
 673 static inline void i40e_config_automask(struct i40e_pf *pf)
 674 {
 675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 676         uint32_t val;
 677
 678         /* INTENA flag is not auto-cleared for interrupt */
 679         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 680         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 681                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 682
 683         /* If support multi-driver, PF will use INT0. */
 684         if (!pf->support_multi_driver)
 685                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 686
 687         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 688 }
 689
 690 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 691
 692 /*
 693  * Add a ethertype filter to drop all flow control frames transmitted
 694  * from VSIs.
 695 */
 696 static void
 697 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 698 {
 699         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 700         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 701                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 702                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 703         int ret;
 704
 705         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 706                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 707                                 pf->main_vsi_seid, 0,
 708                                 TRUE, NULL, NULL);
 709         if (ret)
 710                 PMD_INIT_LOG(ERR,
 711                         "Failed to add filter to drop flow control frames from VSIs.");
 712 }
 713
 714 static int
 715 floating_veb_list_handler(__rte_unused const char *key,
 716                           const char *floating_veb_value,
 717                           void *opaque)
 718 {
 719         int idx = 0;
 720         unsigned int count = 0;
 721         char *end = NULL;
 722         int min, max;
 723         bool *vf_floating_veb = opaque;
 724
 725         while (isblank(*floating_veb_value))
 726                 floating_veb_value++;
 727
 728         /* Reset floating VEB configuration for VFs */
 729         for (idx = 0; idx < I40E_MAX_VF; idx++)
 730                 vf_floating_veb[idx] = false;
 731
 732         min = I40E_MAX_VF;
 733         do {
 734                 while (isblank(*floating_veb_value))
 735                         floating_veb_value++;
 736                 if (*floating_veb_value == '\0')
 737                         return -1;
 738                 errno = 0;
 739                 idx = strtoul(floating_veb_value, &end, 10);
 740                 if (errno || end == NULL)
 741                         return -1;
 742                 while (isblank(*end))
 743                         end++;
 744                 if (*end == '-') {
 745                         min = idx;
 746                 } else if ((*end == ';') || (*end == '\0')) {
 747                         max = idx;
 748                         if (min == I40E_MAX_VF)
 749                                 min = idx;
 750                         if (max >= I40E_MAX_VF)
 751                                 max = I40E_MAX_VF - 1;
 752                         for (idx = min; idx <= max; idx++) {
 753                                 vf_floating_veb[idx] = true;
 754                                 count++;
 755                         }
 756                         min = I40E_MAX_VF;
 757                 } else {
 758                         return -1;
 759                 }
 760                 floating_veb_value = end + 1;
 761         } while (*end != '\0');
 762
 763         if (count == 0)
 764                 return -1;
 765
 766         return 0;
 767 }
 768
 769 static void
 770 config_vf_floating_veb(struct rte_devargs *devargs,
 771                        uint16_t floating_veb,
 772                        bool *vf_floating_veb)
 773 {
 774         struct rte_kvargs *kvlist;
 775         int i;
 776         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 777
 778         if (!floating_veb)
 779                 return;
 780         /* All the VFs attach to the floating VEB by default
 781          * when the floating VEB is enabled.
 782          */
 783         for (i = 0; i < I40E_MAX_VF; i++)
 784                 vf_floating_veb[i] = true;
 785
 786         if (devargs == NULL)
 787                 return;
 788
 789         kvlist = rte_kvargs_parse(devargs->args, NULL);
 790         if (kvlist == NULL)
 791                 return;
 792
 793         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 794                 rte_kvargs_free(kvlist);
 795                 return;
 796         }
 797         /* When the floating_veb_list parameter exists, all the VFs
 798          * will attach to the legacy VEB firstly, then configure VFs
 799          * to the floating VEB according to the floating_veb_list.
 800          */
 801         if (rte_kvargs_process(kvlist, floating_veb_list,
 802                                floating_veb_list_handler,
 803                                vf_floating_veb) < 0) {
 804                 rte_kvargs_free(kvlist);
 805                 return;
 806         }
 807         rte_kvargs_free(kvlist);
 808 }
 809
 810 static int
 811 i40e_check_floating_handler(__rte_unused const char *key,
 812                             const char *value,
 813                             __rte_unused void *opaque)
 814 {
 815         if (strcmp(value, "1"))
 816                 return -1;
 817
 818         return 0;
 819 }
 820
 821 static int
 822 is_floating_veb_supported(struct rte_devargs *devargs)
 823 {
 824         struct rte_kvargs *kvlist;
 825         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 826
 827         if (devargs == NULL)
 828                 return 0;
 829
 830         kvlist = rte_kvargs_parse(devargs->args, NULL);
 831         if (kvlist == NULL)
 832                 return 0;
 833
 834         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 835                 rte_kvargs_free(kvlist);
 836                 return 0;
 837         }
 838         /* Floating VEB is enabled when there's key-value:
 839          * enable_floating_veb=1
 840          */
 841         if (rte_kvargs_process(kvlist, floating_veb_key,
 842                                i40e_check_floating_handler, NULL) < 0) {
 843                 rte_kvargs_free(kvlist);
 844                 return 0;
 845         }
 846         rte_kvargs_free(kvlist);
 847
 848         return 1;
 849 }
 850
 851 static void
 852 config_floating_veb(struct rte_eth_dev *dev)
 853 {
 854         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 856         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 857
 858         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 859
 860         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 861                 pf->floating_veb =
 862                         is_floating_veb_supported(pci_dev->device.devargs);
 863                 config_vf_floating_veb(pci_dev->device.devargs,
 864                                        pf->floating_veb,
 865                                        pf->floating_veb_list);
 866         } else {
 867                 pf->floating_veb = false;
 868         }
 869 }
 870
 871 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 872 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 873
 874 static int
 875 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 876 {
 877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 878         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 879         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 880         int ret;
 881
 882         struct rte_hash_parameters ethertype_hash_params = {
 883                 .name = ethertype_hash_name,
 884                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 885                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 886                 .hash_func = rte_hash_crc,
 887                 .hash_func_init_val = 0,
 888                 .socket_id = rte_socket_id(),
 889         };
 890
 891         /* Initialize ethertype filter rule list and hash */
 892         TAILQ_INIT(&ethertype_rule->ethertype_list);
 893         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 894                  "ethertype_%s", dev->device->name);
 895         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 896         if (!ethertype_rule->hash_table) {
 897                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 898                 return -EINVAL;
 899         }
 900         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 901                                        sizeof(struct i40e_ethertype_filter *) *
 902                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 903                                        0);
 904         if (!ethertype_rule->hash_map) {
 905                 PMD_INIT_LOG(ERR,
 906                              "Failed to allocate memory for ethertype hash map!");
 907                 ret = -ENOMEM;
 908                 goto err_ethertype_hash_map_alloc;
 909         }
 910
 911         return 0;
 912
 913 err_ethertype_hash_map_alloc:
 914         rte_hash_free(ethertype_rule->hash_table);
 915
 916         return ret;
 917 }
 918
 919 static int
 920 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 921 {
 922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 923         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 924         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 925         int ret;
 926
 927         struct rte_hash_parameters tunnel_hash_params = {
 928                 .name = tunnel_hash_name,
 929                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 930                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 931                 .hash_func = rte_hash_crc,
 932                 .hash_func_init_val = 0,
 933                 .socket_id = rte_socket_id(),
 934         };
 935
 936         /* Initialize tunnel filter rule list and hash */
 937         TAILQ_INIT(&tunnel_rule->tunnel_list);
 938         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 939                  "tunnel_%s", dev->device->name);
 940         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 941         if (!tunnel_rule->hash_table) {
 942                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 943                 return -EINVAL;
 944         }
 945         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 946                                     sizeof(struct i40e_tunnel_filter *) *
 947                                     I40E_MAX_TUNNEL_FILTER_NUM,
 948                                     0);
 949         if (!tunnel_rule->hash_map) {
 950                 PMD_INIT_LOG(ERR,
 951                              "Failed to allocate memory for tunnel hash map!");
 952                 ret = -ENOMEM;
 953                 goto err_tunnel_hash_map_alloc;
 954         }
 955
 956         return 0;
 957
 958 err_tunnel_hash_map_alloc:
 959         rte_hash_free(tunnel_rule->hash_table);
 960
 961         return ret;
 962 }
 963
 964 static int
 965 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 966 {
 967         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 968         struct i40e_fdir_info *fdir_info = &pf->fdir;
 969         char fdir_hash_name[RTE_HASH_NAMESIZE];
 970         int ret;
 971
 972         struct rte_hash_parameters fdir_hash_params = {
 973                 .name = fdir_hash_name,
 974                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 975                 .key_len = sizeof(struct i40e_fdir_input),
 976                 .hash_func = rte_hash_crc,
 977                 .hash_func_init_val = 0,
 978                 .socket_id = rte_socket_id(),
 979         };
 980
 981         /* Initialize flow director filter rule list and hash */
 982         TAILQ_INIT(&fdir_info->fdir_list);
 983         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 984                  "fdir_%s", dev->device->name);
 985         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 986         if (!fdir_info->hash_table) {
 987                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 988                 return -EINVAL;
 989         }
 990         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 991                                           sizeof(struct i40e_fdir_filter *) *
 992                                           I40E_MAX_FDIR_FILTER_NUM,
 993                                           0);
 994         if (!fdir_info->hash_map) {
 995                 PMD_INIT_LOG(ERR,
 996                              "Failed to allocate memory for fdir hash map!");
 997                 ret = -ENOMEM;
 998                 goto err_fdir_hash_map_alloc;
 999         }
1000         return 0;
1001
1002 err_fdir_hash_map_alloc:
1003         rte_hash_free(fdir_info->hash_table);
1004
1005         return ret;
1006 }
1007
1008 static void
1009 i40e_init_customized_info(struct i40e_pf *pf)
1010 {
1011         int i;
1012
1013         /* Initialize customized pctype */
1014         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1015                 pf->customized_pctype[i].index = i;
1016                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1017                 pf->customized_pctype[i].valid = false;
1018         }
1019
1020         pf->gtp_support = false;
1021 }
1022
1023 void
1024 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1025 {
1026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1028         struct i40e_queue_regions *info = &pf->queue_region;
1029         uint16_t i;
1030
1031         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1032                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1033
1034         memset(info, 0, sizeof(struct i40e_queue_regions));
1035 }
1036
1037 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1038
1039 static int
1040 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1041                                const char *value,
1042                                void *opaque)
1043 {
1044         struct i40e_pf *pf;
1045         unsigned long support_multi_driver;
1046         char *end;
1047
1048         pf = (struct i40e_pf *)opaque;
1049
1050         errno = 0;
1051         support_multi_driver = strtoul(value, &end, 10);
1052         if (errno != 0 || end == value || *end != 0) {
1053                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1054                 return -(EINVAL);
1055         }
1056
1057         if (support_multi_driver == 1 || support_multi_driver == 0)
1058                 pf->support_multi_driver = (bool)support_multi_driver;
1059         else
1060                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1061                             "enable global configuration by default."
1062                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1063         return 0;
1064 }
1065
1066 static int
1067 i40e_support_multi_driver(struct rte_eth_dev *dev)
1068 {
1069         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1070         static const char *const valid_keys[] = {
1071                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1072         struct rte_kvargs *kvlist;
1073
1074         /* Enable global configuration by default */
1075         pf->support_multi_driver = false;
1076
1077         if (!dev->device->devargs)
1078                 return 0;
1079
1080         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1081         if (!kvlist)
1082                 return -EINVAL;
1083
1084         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1085                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1086                             "the first invalid or last valid one is used !",
1087                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1088
1089         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1090                                i40e_parse_multi_drv_handler, pf) < 0) {
1091                 rte_kvargs_free(kvlist);
1092                 return -EINVAL;
1093         }
1094
1095         rte_kvargs_free(kvlist);
1096         return 0;
1097 }
1098
1099 static int
1100 eth_i40e_dev_init(struct rte_eth_dev *dev)
1101 {
1102         struct rte_pci_device *pci_dev;
1103         struct rte_intr_handle *intr_handle;
1104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1106         struct i40e_vsi *vsi;
1107         int ret;
1108         uint32_t len;
1109         uint8_t aq_fail = 0;
1110
1111         PMD_INIT_FUNC_TRACE();
1112
1113         dev->dev_ops = &i40e_eth_dev_ops;
1114         dev->rx_pkt_burst = i40e_recv_pkts;
1115         dev->tx_pkt_burst = i40e_xmit_pkts;
1116         dev->tx_pkt_prepare = i40e_prep_pkts;
1117
1118         /* for secondary processes, we don't initialise any further as primary
1119          * has already done this work. Only check we don't need a different
1120          * RX function */
1121         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1122                 i40e_set_rx_function(dev);
1123                 i40e_set_tx_function(dev);
1124                 return 0;
1125         }
1126         i40e_set_default_ptype_table(dev);
1127         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1128         intr_handle = &pci_dev->intr_handle;
1129
1130         rte_eth_copy_pci_info(dev, pci_dev);
1131
1132         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1133         pf->adapter->eth_dev = dev;
1134         pf->dev_data = dev->data;
1135
1136         hw->back = I40E_PF_TO_ADAPTER(pf);
1137         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1138         if (!hw->hw_addr) {
1139                 PMD_INIT_LOG(ERR,
1140                         "Hardware is not available, as address is NULL");
1141                 return -ENODEV;
1142         }
1143
1144         hw->vendor_id = pci_dev->id.vendor_id;
1145         hw->device_id = pci_dev->id.device_id;
1146         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1147         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1148         hw->bus.device = pci_dev->addr.devid;
1149         hw->bus.func = pci_dev->addr.function;
1150         hw->adapter_stopped = 0;
1151
1152         /* Check if need to support multi-driver */
1153         i40e_support_multi_driver(dev);
1154
1155         /* Make sure all is clean before doing PF reset */
1156         i40e_clear_hw(hw);
1157
1158         /* Initialize the hardware */
1159         i40e_hw_init(dev);
1160
1161         /* Reset here to make sure all is clean for each PF */
1162         ret = i40e_pf_reset(hw);
1163         if (ret) {
1164                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1165                 return ret;
1166         }
1167
1168         /* Initialize the shared code (base driver) */
1169         ret = i40e_init_shared_code(hw);
1170         if (ret) {
1171                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1172                 return ret;
1173         }
1174
1175         i40e_config_automask(pf);
1176
1177         i40e_set_default_pctype_table(dev);
1178
1179         /*
1180          * To work around the NVM issue, initialize registers
1181          * for packet type of QinQ by software.
1182          * It should be removed once issues are fixed in NVM.
1183          */
1184         if (!pf->support_multi_driver)
1185                 i40e_GLQF_reg_init(hw);
1186
1187         /* Initialize the input set for filters (hash and fd) to default value */
1188         i40e_filter_input_set_init(pf);
1189
1190         /* Initialize the parameters for adminq */
1191         i40e_init_adminq_parameter(hw);
1192         ret = i40e_init_adminq(hw);
1193         if (ret != I40E_SUCCESS) {
1194                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1195                 return -EIO;
1196         }
1197         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1198                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1199                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1200                      ((hw->nvm.version >> 12) & 0xf),
1201                      ((hw->nvm.version >> 4) & 0xff),
1202                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1203
1204         /* initialise the L3_MAP register */
1205         if (!pf->support_multi_driver) {
1206                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1207                                                    0x00000028,  NULL);
1208                 if (ret)
1209                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1210                                      ret);
1211                 PMD_INIT_LOG(DEBUG,
1212                              "Global register 0x%08x is changed with 0x28",
1213                              I40E_GLQF_L3_MAP(40));
1214                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1215         }
1216
1217         /* Need the special FW version to support floating VEB */
1218         config_floating_veb(dev);
1219         /* Clear PXE mode */
1220         i40e_clear_pxe_mode(hw);
1221         i40e_dev_sync_phy_type(hw);
1222
1223         /*
1224          * On X710, performance number is far from the expectation on recent
1225          * firmware versions. The fix for this issue may not be integrated in
1226          * the following firmware version. So the workaround in software driver
1227          * is needed. It needs to modify the initial values of 3 internal only
1228          * registers. Note that the workaround can be removed when it is fixed
1229          * in firmware in the future.
1230          */
1231         i40e_configure_registers(hw);
1232
1233         /* Get hw capabilities */
1234         ret = i40e_get_cap(hw);
1235         if (ret != I40E_SUCCESS) {
1236                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1237                 goto err_get_capabilities;
1238         }
1239
1240         /* Initialize parameters for PF */
1241         ret = i40e_pf_parameter_init(dev);
1242         if (ret != 0) {
1243                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1244                 goto err_parameter_init;
1245         }
1246
1247         /* Initialize the queue management */
1248         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1249         if (ret < 0) {
1250                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1251                 goto err_qp_pool_init;
1252         }
1253         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1254                                 hw->func_caps.num_msix_vectors - 1);
1255         if (ret < 0) {
1256                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1257                 goto err_msix_pool_init;
1258         }
1259
1260         /* Initialize lan hmc */
1261         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1262                                 hw->func_caps.num_rx_qp, 0, 0);
1263         if (ret != I40E_SUCCESS) {
1264                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1265                 goto err_init_lan_hmc;
1266         }
1267
1268         /* Configure lan hmc */
1269         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1270         if (ret != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1272                 goto err_configure_lan_hmc;
1273         }
1274
1275         /* Get and check the mac address */
1276         i40e_get_mac_addr(hw, hw->mac.addr);
1277         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1278                 PMD_INIT_LOG(ERR, "mac address is not valid");
1279                 ret = -EIO;
1280                 goto err_get_mac_addr;
1281         }
1282         /* Copy the permanent MAC address */
1283         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1284                         (struct ether_addr *) hw->mac.perm_addr);
1285
1286         /* Disable flow control */
1287         hw->fc.requested_mode = I40E_FC_NONE;
1288         i40e_set_fc(hw, &aq_fail, TRUE);
1289
1290         /* Set the global registers with default ether type value */
1291         if (!pf->support_multi_driver) {
1292                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1293                                          ETHER_TYPE_VLAN);
1294                 if (ret != I40E_SUCCESS) {
1295                         PMD_INIT_LOG(ERR,
1296                                      "Failed to set the default outer "
1297                                      "VLAN ether type");
1298                         goto err_setup_pf_switch;
1299                 }
1300         }
1301
1302         /* PF setup, which includes VSI setup */
1303         ret = i40e_pf_setup(pf);
1304         if (ret) {
1305                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1306                 goto err_setup_pf_switch;
1307         }
1308
1309         /* reset all stats of the device, including pf and main vsi */
1310         i40e_dev_stats_reset(dev);
1311
1312         vsi = pf->main_vsi;
1313
1314         /* Disable double vlan by default */
1315         i40e_vsi_config_double_vlan(vsi, FALSE);
1316
1317         /* Disable S-TAG identification when floating_veb is disabled */
1318         if (!pf->floating_veb) {
1319                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1320                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1321                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1322                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1323                 }
1324         }
1325
1326         if (!vsi->max_macaddrs)
1327                 len = ETHER_ADDR_LEN;
1328         else
1329                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1330
1331         /* Should be after VSI initialized */
1332         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1333         if (!dev->data->mac_addrs) {
1334                 PMD_INIT_LOG(ERR,
1335                         "Failed to allocated memory for storing mac address");
1336                 goto err_mac_alloc;
1337         }
1338         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1339                                         &dev->data->mac_addrs[0]);
1340
1341         /* Init dcb to sw mode by default */
1342         ret = i40e_dcb_init_configure(dev, TRUE);
1343         if (ret != I40E_SUCCESS) {
1344                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1345                 pf->flags &= ~I40E_FLAG_DCB;
1346         }
1347         /* Update HW struct after DCB configuration */
1348         i40e_get_cap(hw);
1349
1350         /* initialize pf host driver to setup SRIOV resource if applicable */
1351         i40e_pf_host_init(dev);
1352
1353         /* register callback func to eal lib */
1354         rte_intr_callback_register(intr_handle,
1355                                    i40e_dev_interrupt_handler, dev);
1356
1357         /* configure and enable device interrupt */
1358         i40e_pf_config_irq0(hw, TRUE);
1359         i40e_pf_enable_irq0(hw);
1360
1361         /* enable uio intr after callback register */
1362         rte_intr_enable(intr_handle);
1363
1364         /* By default disable flexible payload in global configuration */
1365         if (!pf->support_multi_driver)
1366                 i40e_flex_payload_reg_set_default(hw);
1367
1368         /*
1369          * Add an ethertype filter to drop all flow control frames transmitted
1370          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1371          * frames to wire.
1372          */
1373         i40e_add_tx_flow_control_drop_filter(pf);
1374
1375         /* Set the max frame size to 0x2600 by default,
1376          * in case other drivers changed the default value.
1377          */
1378         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1379
1380         /* initialize mirror rule list */
1381         TAILQ_INIT(&pf->mirror_list);
1382
1383         /* initialize Traffic Manager configuration */
1384         i40e_tm_conf_init(dev);
1385
1386         /* Initialize customized information */
1387         i40e_init_customized_info(pf);
1388
1389         ret = i40e_init_ethtype_filter_list(dev);
1390         if (ret < 0)
1391                 goto err_init_ethtype_filter_list;
1392         ret = i40e_init_tunnel_filter_list(dev);
1393         if (ret < 0)
1394                 goto err_init_tunnel_filter_list;
1395         ret = i40e_init_fdir_filter_list(dev);
1396         if (ret < 0)
1397                 goto err_init_fdir_filter_list;
1398
1399         /* initialize queue region configuration */
1400         i40e_init_queue_region_conf(dev);
1401
1402         /* initialize rss configuration from rte_flow */
1403         memset(&pf->rss_info, 0,
1404                 sizeof(struct i40e_rte_flow_rss_conf));
1405
1406         return 0;
1407
1408 err_init_fdir_filter_list:
1409         rte_free(pf->tunnel.hash_table);
1410         rte_free(pf->tunnel.hash_map);
1411 err_init_tunnel_filter_list:
1412         rte_free(pf->ethertype.hash_table);
1413         rte_free(pf->ethertype.hash_map);
1414 err_init_ethtype_filter_list:
1415         rte_free(dev->data->mac_addrs);
1416 err_mac_alloc:
1417         i40e_vsi_release(pf->main_vsi);
1418 err_setup_pf_switch:
1419 err_get_mac_addr:
1420 err_configure_lan_hmc:
1421         (void)i40e_shutdown_lan_hmc(hw);
1422 err_init_lan_hmc:
1423         i40e_res_pool_destroy(&pf->msix_pool);
1424 err_msix_pool_init:
1425         i40e_res_pool_destroy(&pf->qp_pool);
1426 err_qp_pool_init:
1427 err_parameter_init:
1428 err_get_capabilities:
1429         (void)i40e_shutdown_adminq(hw);
1430
1431         return ret;
1432 }
1433
1434 static void
1435 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1436 {
1437         struct i40e_ethertype_filter *p_ethertype;
1438         struct i40e_ethertype_rule *ethertype_rule;
1439
1440         ethertype_rule = &pf->ethertype;
1441         /* Remove all ethertype filter rules and hash */
1442         if (ethertype_rule->hash_map)
1443                 rte_free(ethertype_rule->hash_map);
1444         if (ethertype_rule->hash_table)
1445                 rte_hash_free(ethertype_rule->hash_table);
1446
1447         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1448                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1449                              p_ethertype, rules);
1450                 rte_free(p_ethertype);
1451         }
1452 }
1453
1454 static void
1455 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1456 {
1457         struct i40e_tunnel_filter *p_tunnel;
1458         struct i40e_tunnel_rule *tunnel_rule;
1459
1460         tunnel_rule = &pf->tunnel;
1461         /* Remove all tunnel director rules and hash */
1462         if (tunnel_rule->hash_map)
1463                 rte_free(tunnel_rule->hash_map);
1464         if (tunnel_rule->hash_table)
1465                 rte_hash_free(tunnel_rule->hash_table);
1466
1467         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1468                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1469                 rte_free(p_tunnel);
1470         }
1471 }
1472
1473 static void
1474 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1475 {
1476         struct i40e_fdir_filter *p_fdir;
1477         struct i40e_fdir_info *fdir_info;
1478
1479         fdir_info = &pf->fdir;
1480         /* Remove all flow director rules and hash */
1481         if (fdir_info->hash_map)
1482                 rte_free(fdir_info->hash_map);
1483         if (fdir_info->hash_table)
1484                 rte_hash_free(fdir_info->hash_table);
1485
1486         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1487                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1488                 rte_free(p_fdir);
1489         }
1490 }
1491
1492 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1493 {
1494         /*
1495          * Disable by default flexible payload
1496          * for corresponding L2/L3/L4 layers.
1497          */
1498         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1499         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1500         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1501         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1502 }
1503
1504 static int
1505 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1506 {
1507         struct i40e_pf *pf;
1508         struct rte_pci_device *pci_dev;
1509         struct rte_intr_handle *intr_handle;
1510         struct i40e_hw *hw;
1511         struct i40e_filter_control_settings settings;
1512         struct rte_flow *p_flow;
1513         int ret;
1514         uint8_t aq_fail = 0;
1515         int retries = 0;
1516
1517         PMD_INIT_FUNC_TRACE();
1518
1519         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1520                 return 0;
1521
1522         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1523         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1525         intr_handle = &pci_dev->intr_handle;
1526
1527         if (hw->adapter_stopped == 0)
1528                 i40e_dev_close(dev);
1529
1530         dev->dev_ops = NULL;
1531         dev->rx_pkt_burst = NULL;
1532         dev->tx_pkt_burst = NULL;
1533
1534         /* Clear PXE mode */
1535         i40e_clear_pxe_mode(hw);
1536
1537         /* Unconfigure filter control */
1538         memset(&settings, 0, sizeof(settings));
1539         ret = i40e_set_filter_control(hw, &settings);
1540         if (ret)
1541                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1542                                         ret);
1543
1544         /* Disable flow control */
1545         hw->fc.requested_mode = I40E_FC_NONE;
1546         i40e_set_fc(hw, &aq_fail, TRUE);
1547
1548         /* uninitialize pf host driver */
1549         i40e_pf_host_uninit(dev);
1550
1551         rte_free(dev->data->mac_addrs);
1552         dev->data->mac_addrs = NULL;
1553
1554         /* disable uio intr before callback unregister */
1555         rte_intr_disable(intr_handle);
1556
1557         /* unregister callback func to eal lib */
1558         do {
1559                 ret = rte_intr_callback_unregister(intr_handle,
1560                                 i40e_dev_interrupt_handler, dev);
1561                 if (ret >= 0) {
1562                         break;
1563                 } else if (ret != -EAGAIN) {
1564                         PMD_INIT_LOG(ERR,
1565                                  "intr callback unregister failed: %d",
1566                                  ret);
1567                         return ret;
1568                 }
1569                 i40e_msec_delay(500);
1570         } while (retries++ < 5);
1571
1572         i40e_rm_ethtype_filter_list(pf);
1573         i40e_rm_tunnel_filter_list(pf);
1574         i40e_rm_fdir_filter_list(pf);
1575
1576         /* Remove all flows */
1577         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1578                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1579                 rte_free(p_flow);
1580         }
1581
1582         /* Remove all Traffic Manager configuration */
1583         i40e_tm_conf_uninit(dev);
1584
1585         return 0;
1586 }
1587
1588 static int
1589 i40e_dev_configure(struct rte_eth_dev *dev)
1590 {
1591         struct i40e_adapter *ad =
1592                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1593         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1596         int i, ret;
1597
1598         ret = i40e_dev_sync_phy_type(hw);
1599         if (ret)
1600                 return ret;
1601
1602         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1603          * bulk allocation or vector Rx preconditions we will reset it.
1604          */
1605         ad->rx_bulk_alloc_allowed = true;
1606         ad->rx_vec_allowed = true;
1607         ad->tx_simple_allowed = true;
1608         ad->tx_vec_allowed = true;
1609
1610         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1611                 ret = i40e_fdir_setup(pf);
1612                 if (ret != I40E_SUCCESS) {
1613                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1614                         return -ENOTSUP;
1615                 }
1616                 ret = i40e_fdir_configure(dev);
1617                 if (ret < 0) {
1618                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1619                         goto err;
1620                 }
1621         } else
1622                 i40e_fdir_teardown(pf);
1623
1624         ret = i40e_dev_init_vlan(dev);
1625         if (ret < 0)
1626                 goto err;
1627
1628         /* VMDQ setup.
1629          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1630          *  RSS setting have different requirements.
1631          *  General PMD driver call sequence are NIC init, configure,
1632          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1633          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1634          *  applicable. So, VMDQ setting has to be done before
1635          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1636          *  For RSS setting, it will try to calculate actual configured RX queue
1637          *  number, which will be available after rx_queue_setup(). dev_start()
1638          *  function is good to place RSS setup.
1639          */
1640         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1641                 ret = i40e_vmdq_setup(dev);
1642                 if (ret)
1643                         goto err;
1644         }
1645
1646         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1647                 ret = i40e_dcb_setup(dev);
1648                 if (ret) {
1649                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1650                         goto err_dcb;
1651                 }
1652         }
1653
1654         TAILQ_INIT(&pf->flow_list);
1655
1656         return 0;
1657
1658 err_dcb:
1659         /* need to release vmdq resource if exists */
1660         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1661                 i40e_vsi_release(pf->vmdq[i].vsi);
1662                 pf->vmdq[i].vsi = NULL;
1663         }
1664         rte_free(pf->vmdq);
1665         pf->vmdq = NULL;
1666 err:
1667         /* need to release fdir resource if exists */
1668         i40e_fdir_teardown(pf);
1669         return ret;
1670 }
1671
1672 void
1673 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1674 {
1675         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1676         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1677         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1678         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1679         uint16_t msix_vect = vsi->msix_intr;
1680         uint16_t i;
1681
1682         for (i = 0; i < vsi->nb_qps; i++) {
1683                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1684                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1685                 rte_wmb();
1686         }
1687
1688         if (vsi->type != I40E_VSI_SRIOV) {
1689                 if (!rte_intr_allow_others(intr_handle)) {
1690                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1691                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1692                         I40E_WRITE_REG(hw,
1693                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1694                                        0);
1695                 } else {
1696                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1697                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1698                         I40E_WRITE_REG(hw,
1699                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1700                                                        msix_vect - 1), 0);
1701                 }
1702         } else {
1703                 uint32_t reg;
1704                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1705                         vsi->user_param + (msix_vect - 1);
1706
1707                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1708                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1709         }
1710         I40E_WRITE_FLUSH(hw);
1711 }
1712
1713 static void
1714 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1715                        int base_queue, int nb_queue,
1716                        uint16_t itr_idx)
1717 {
1718         int i;
1719         uint32_t val;
1720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1721         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1722
1723         /* Bind all RX queues to allocated MSIX interrupt */
1724         for (i = 0; i < nb_queue; i++) {
1725                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1726                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1727                         ((base_queue + i + 1) <<
1728                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1729                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1730                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1731
1732                 if (i == nb_queue - 1)
1733                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1734                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1735         }
1736
1737         /* Write first RX queue to Link list register as the head element */
1738         if (vsi->type != I40E_VSI_SRIOV) {
1739                 uint16_t interval =
1740                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1741                                                pf->support_multi_driver);
1742
1743                 if (msix_vect == I40E_MISC_VEC_ID) {
1744                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1745                                        (base_queue <<
1746                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1747                                        (0x0 <<
1748                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1749                         I40E_WRITE_REG(hw,
1750                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1751                                        interval);
1752                 } else {
1753                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1754                                        (base_queue <<
1755                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1756                                        (0x0 <<
1757                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1758                         I40E_WRITE_REG(hw,
1759                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1760                                                        msix_vect - 1),
1761                                        interval);
1762                 }
1763         } else {
1764                 uint32_t reg;
1765
1766                 if (msix_vect == I40E_MISC_VEC_ID) {
1767                         I40E_WRITE_REG(hw,
1768                                        I40E_VPINT_LNKLST0(vsi->user_param),
1769                                        (base_queue <<
1770                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1771                                        (0x0 <<
1772                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1773                 } else {
1774                         /* num_msix_vectors_vf needs to minus irq0 */
1775                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1776                                 vsi->user_param + (msix_vect - 1);
1777
1778                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1779                                        (base_queue <<
1780                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1781                                        (0x0 <<
1782                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1783                 }
1784         }
1785
1786         I40E_WRITE_FLUSH(hw);
1787 }
1788
1789 void
1790 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1791 {
1792         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1793         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1794         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1795         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1796         uint16_t msix_vect = vsi->msix_intr;
1797         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1798         uint16_t queue_idx = 0;
1799         int record = 0;
1800         int i;
1801
1802         for (i = 0; i < vsi->nb_qps; i++) {
1803                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1804                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1805         }
1806
1807         /* VF bind interrupt */
1808         if (vsi->type == I40E_VSI_SRIOV) {
1809                 __vsi_queues_bind_intr(vsi, msix_vect,
1810                                        vsi->base_queue, vsi->nb_qps,
1811                                        itr_idx);
1812                 return;
1813         }
1814
1815         /* PF & VMDq bind interrupt */
1816         if (rte_intr_dp_is_en(intr_handle)) {
1817                 if (vsi->type == I40E_VSI_MAIN) {
1818                         queue_idx = 0;
1819                         record = 1;
1820                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1821                         struct i40e_vsi *main_vsi =
1822                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1823                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1824                         record = 1;
1825                 }
1826         }
1827
1828         for (i = 0; i < vsi->nb_used_qps; i++) {
1829                 if (nb_msix <= 1) {
1830                         if (!rte_intr_allow_others(intr_handle))
1831                                 /* allow to share MISC_VEC_ID */
1832                                 msix_vect = I40E_MISC_VEC_ID;
1833
1834                         /* no enough msix_vect, map all to one */
1835                         __vsi_queues_bind_intr(vsi, msix_vect,
1836                                                vsi->base_queue + i,
1837                                                vsi->nb_used_qps - i,
1838                                                itr_idx);
1839                         for (; !!record && i < vsi->nb_used_qps; i++)
1840                                 intr_handle->intr_vec[queue_idx + i] =
1841                                         msix_vect;
1842                         break;
1843                 }
1844                 /* 1:1 queue/msix_vect mapping */
1845                 __vsi_queues_bind_intr(vsi, msix_vect,
1846                                        vsi->base_queue + i, 1,
1847                                        itr_idx);
1848                 if (!!record)
1849                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1850
1851                 msix_vect++;
1852                 nb_msix--;
1853         }
1854 }
1855
1856 static void
1857 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1858 {
1859         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1860         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1861         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1862         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1863         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1864         uint16_t msix_intr, i;
1865
1866         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1867                 for (i = 0; i < vsi->nb_msix; i++) {
1868                         msix_intr = vsi->msix_intr + i;
1869                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1870                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1871                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1872                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1873                 }
1874         else
1875                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1876                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1877                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1878                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1879
1880         I40E_WRITE_FLUSH(hw);
1881 }
1882
1883 static void
1884 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1885 {
1886         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1887         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1888         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1889         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1890         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1891         uint16_t msix_intr, i;
1892
1893         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1894                 for (i = 0; i < vsi->nb_msix; i++) {
1895                         msix_intr = vsi->msix_intr + i;
1896                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1897                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1898                 }
1899         else
1900                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1901                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1902
1903         I40E_WRITE_FLUSH(hw);
1904 }
1905
1906 static inline uint8_t
1907 i40e_parse_link_speeds(uint16_t link_speeds)
1908 {
1909         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1910
1911         if (link_speeds & ETH_LINK_SPEED_40G)
1912                 link_speed |= I40E_LINK_SPEED_40GB;
1913         if (link_speeds & ETH_LINK_SPEED_25G)
1914                 link_speed |= I40E_LINK_SPEED_25GB;
1915         if (link_speeds & ETH_LINK_SPEED_20G)
1916                 link_speed |= I40E_LINK_SPEED_20GB;
1917         if (link_speeds & ETH_LINK_SPEED_10G)
1918                 link_speed |= I40E_LINK_SPEED_10GB;
1919         if (link_speeds & ETH_LINK_SPEED_1G)
1920                 link_speed |= I40E_LINK_SPEED_1GB;
1921         if (link_speeds & ETH_LINK_SPEED_100M)
1922                 link_speed |= I40E_LINK_SPEED_100MB;
1923
1924         return link_speed;
1925 }
1926
1927 static int
1928 i40e_phy_conf_link(struct i40e_hw *hw,
1929                    uint8_t abilities,
1930                    uint8_t force_speed,
1931                    bool is_up)
1932 {
1933         enum i40e_status_code status;
1934         struct i40e_aq_get_phy_abilities_resp phy_ab;
1935         struct i40e_aq_set_phy_config phy_conf;
1936         enum i40e_aq_phy_type cnt;
1937         uint32_t phy_type_mask = 0;
1938
1939         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1940                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1941                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1942                         I40E_AQ_PHY_FLAG_LOW_POWER;
1943         const uint8_t advt = I40E_LINK_SPEED_40GB |
1944                         I40E_LINK_SPEED_25GB |
1945                         I40E_LINK_SPEED_10GB |
1946                         I40E_LINK_SPEED_1GB |
1947                         I40E_LINK_SPEED_100MB;
1948         int ret = -ENOTSUP;
1949
1950
1951         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1952                                               NULL);
1953         if (status)
1954                 return ret;
1955
1956         /* If link already up, no need to set up again */
1957         if (is_up && phy_ab.phy_type != 0)
1958                 return I40E_SUCCESS;
1959
1960         memset(&phy_conf, 0, sizeof(phy_conf));
1961
1962         /* bits 0-2 use the values from get_phy_abilities_resp */
1963         abilities &= ~mask;
1964         abilities |= phy_ab.abilities & mask;
1965
1966         /* update ablities and speed */
1967         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1968                 phy_conf.link_speed = advt;
1969         else
1970                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1971
1972         phy_conf.abilities = abilities;
1973
1974
1975
1976         /* To enable link, phy_type mask needs to include each type */
1977         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1978                 phy_type_mask |= 1 << cnt;
1979
1980         /* use get_phy_abilities_resp value for the rest */
1981         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1982         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1983                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1984                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1985         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1986         phy_conf.eee_capability = phy_ab.eee_capability;
1987         phy_conf.eeer = phy_ab.eeer_val;
1988         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1989
1990         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1991                     phy_ab.abilities, phy_ab.link_speed);
1992         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1993                     phy_conf.abilities, phy_conf.link_speed);
1994
1995         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1996         if (status)
1997                 return ret;
1998
1999         return I40E_SUCCESS;
2000 }
2001
2002 static int
2003 i40e_apply_link_speed(struct rte_eth_dev *dev)
2004 {
2005         uint8_t speed;
2006         uint8_t abilities = 0;
2007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2008         struct rte_eth_conf *conf = &dev->data->dev_conf;
2009
2010         speed = i40e_parse_link_speeds(conf->link_speeds);
2011         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2012         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2013                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2014         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2015
2016         return i40e_phy_conf_link(hw, abilities, speed, true);
2017 }
2018
2019 static int
2020 i40e_dev_start(struct rte_eth_dev *dev)
2021 {
2022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2023         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2024         struct i40e_vsi *main_vsi = pf->main_vsi;
2025         int ret, i;
2026         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2027         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2028         uint32_t intr_vector = 0;
2029         struct i40e_vsi *vsi;
2030
2031         hw->adapter_stopped = 0;
2032
2033         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2034                 PMD_INIT_LOG(ERR,
2035                 "Invalid link_speeds for port %u, autonegotiation disabled",
2036                               dev->data->port_id);
2037                 return -EINVAL;
2038         }
2039
2040         rte_intr_disable(intr_handle);
2041
2042         if ((rte_intr_cap_multiple(intr_handle) ||
2043              !RTE_ETH_DEV_SRIOV(dev).active) &&
2044             dev->data->dev_conf.intr_conf.rxq != 0) {
2045                 intr_vector = dev->data->nb_rx_queues;
2046                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2047                 if (ret)
2048                         return ret;
2049         }
2050
2051         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2052                 intr_handle->intr_vec =
2053                         rte_zmalloc("intr_vec",
2054                                     dev->data->nb_rx_queues * sizeof(int),
2055                                     0);
2056                 if (!intr_handle->intr_vec) {
2057                         PMD_INIT_LOG(ERR,
2058                                 "Failed to allocate %d rx_queues intr_vec",
2059                                 dev->data->nb_rx_queues);
2060                         return -ENOMEM;
2061                 }
2062         }
2063
2064         /* Initialize VSI */
2065         ret = i40e_dev_rxtx_init(pf);
2066         if (ret != I40E_SUCCESS) {
2067                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2068                 goto err_up;
2069         }
2070
2071         /* Map queues with MSIX interrupt */
2072         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2073                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2074         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2075         i40e_vsi_enable_queues_intr(main_vsi);
2076
2077         /* Map VMDQ VSI queues with MSIX interrupt */
2078         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2079                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2080                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2081                                           I40E_ITR_INDEX_DEFAULT);
2082                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2083         }
2084
2085         /* enable FDIR MSIX interrupt */
2086         if (pf->fdir.fdir_vsi) {
2087                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2088                                           I40E_ITR_INDEX_NONE);
2089                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2090         }
2091
2092         /* Enable all queues which have been configured */
2093         ret = i40e_dev_switch_queues(pf, TRUE);
2094         if (ret != I40E_SUCCESS) {
2095                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2096                 goto err_up;
2097         }
2098
2099         /* Enable receiving broadcast packets */
2100         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2101         if (ret != I40E_SUCCESS)
2102                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2103
2104         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2105                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2106                                                 true, NULL);
2107                 if (ret != I40E_SUCCESS)
2108                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2109         }
2110
2111         /* Enable the VLAN promiscuous mode. */
2112         if (pf->vfs) {
2113                 for (i = 0; i < pf->vf_num; i++) {
2114                         vsi = pf->vfs[i].vsi;
2115                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2116                                                      true, NULL);
2117                 }
2118         }
2119
2120         /* Enable mac loopback mode */
2121         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2122             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2123                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2124                 if (ret != I40E_SUCCESS) {
2125                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2126                         goto err_up;
2127                 }
2128         }
2129
2130         /* Apply link configure */
2131         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2132                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2133                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2134                                 ETH_LINK_SPEED_40G)) {
2135                 PMD_DRV_LOG(ERR, "Invalid link setting");
2136                 goto err_up;
2137         }
2138         ret = i40e_apply_link_speed(dev);
2139         if (I40E_SUCCESS != ret) {
2140                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2141                 goto err_up;
2142         }
2143
2144         if (!rte_intr_allow_others(intr_handle)) {
2145                 rte_intr_callback_unregister(intr_handle,
2146                                              i40e_dev_interrupt_handler,
2147                                              (void *)dev);
2148                 /* configure and enable device interrupt */
2149                 i40e_pf_config_irq0(hw, FALSE);
2150                 i40e_pf_enable_irq0(hw);
2151
2152                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2153                         PMD_INIT_LOG(INFO,
2154                                 "lsc won't enable because of no intr multiplex");
2155         } else {
2156                 ret = i40e_aq_set_phy_int_mask(hw,
2157                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2158                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2159                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2160                 if (ret != I40E_SUCCESS)
2161                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2162
2163                 /* Call get_link_info aq commond to enable/disable LSE */
2164                 i40e_dev_link_update(dev, 0);
2165         }
2166
2167         /* enable uio intr after callback register */
2168         rte_intr_enable(intr_handle);
2169
2170         i40e_filter_restore(pf);
2171
2172         if (pf->tm_conf.root && !pf->tm_conf.committed)
2173                 PMD_DRV_LOG(WARNING,
2174                             "please call hierarchy_commit() "
2175                             "before starting the port");
2176
2177         return I40E_SUCCESS;
2178
2179 err_up:
2180         i40e_dev_switch_queues(pf, FALSE);
2181         i40e_dev_clear_queues(dev);
2182
2183         return ret;
2184 }
2185
2186 static void
2187 i40e_dev_stop(struct rte_eth_dev *dev)
2188 {
2189         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2190         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2191         struct i40e_vsi *main_vsi = pf->main_vsi;
2192         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2193         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2194         int i;
2195
2196         if (hw->adapter_stopped == 1)
2197                 return;
2198         /* Disable all queues */
2199         i40e_dev_switch_queues(pf, FALSE);
2200
2201         /* un-map queues with interrupt registers */
2202         i40e_vsi_disable_queues_intr(main_vsi);
2203         i40e_vsi_queues_unbind_intr(main_vsi);
2204
2205         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2206                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2207                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2208         }
2209
2210         if (pf->fdir.fdir_vsi) {
2211                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2212                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2213         }
2214         /* Clear all queues and release memory */
2215         i40e_dev_clear_queues(dev);
2216
2217         /* Set link down */
2218         i40e_dev_set_link_down(dev);
2219
2220         if (!rte_intr_allow_others(intr_handle))
2221                 /* resume to the default handler */
2222                 rte_intr_callback_register(intr_handle,
2223                                            i40e_dev_interrupt_handler,
2224                                            (void *)dev);
2225
2226         /* Clean datapath event and queue/vec mapping */
2227         rte_intr_efd_disable(intr_handle);
2228         if (intr_handle->intr_vec) {
2229                 rte_free(intr_handle->intr_vec);
2230                 intr_handle->intr_vec = NULL;
2231         }
2232
2233         /* reset hierarchy commit */
2234         pf->tm_conf.committed = false;
2235
2236         hw->adapter_stopped = 1;
2237 }
2238
2239 static void
2240 i40e_dev_close(struct rte_eth_dev *dev)
2241 {
2242         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2245         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2246         struct i40e_mirror_rule *p_mirror;
2247         uint32_t reg;
2248         int i;
2249         int ret;
2250
2251         PMD_INIT_FUNC_TRACE();
2252
2253         i40e_dev_stop(dev);
2254
2255         /* Remove all mirror rules */
2256         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2257                 ret = i40e_aq_del_mirror_rule(hw,
2258                                               pf->main_vsi->veb->seid,
2259                                               p_mirror->rule_type,
2260                                               p_mirror->entries,
2261                                               p_mirror->num_entries,
2262                                               p_mirror->id);
2263                 if (ret < 0)
2264                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2265                                     "status = %d, aq_err = %d.", ret,
2266                                     hw->aq.asq_last_status);
2267
2268                 /* remove mirror software resource anyway */
2269                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2270                 rte_free(p_mirror);
2271                 pf->nb_mirror_rule--;
2272         }
2273
2274         i40e_dev_free_queues(dev);
2275
2276         /* Disable interrupt */
2277         i40e_pf_disable_irq0(hw);
2278         rte_intr_disable(intr_handle);
2279
2280         /* shutdown and destroy the HMC */
2281         i40e_shutdown_lan_hmc(hw);
2282
2283         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2284                 i40e_vsi_release(pf->vmdq[i].vsi);
2285                 pf->vmdq[i].vsi = NULL;
2286         }
2287         rte_free(pf->vmdq);
2288         pf->vmdq = NULL;
2289
2290         /* release all the existing VSIs and VEBs */
2291         i40e_fdir_teardown(pf);
2292         i40e_vsi_release(pf->main_vsi);
2293
2294         /* shutdown the adminq */
2295         i40e_aq_queue_shutdown(hw, true);
2296         i40e_shutdown_adminq(hw);
2297
2298         i40e_res_pool_destroy(&pf->qp_pool);
2299         i40e_res_pool_destroy(&pf->msix_pool);
2300
2301         /* Disable flexible payload in global configuration */
2302         if (!pf->support_multi_driver)
2303                 i40e_flex_payload_reg_set_default(hw);
2304
2305         /* force a PF reset to clean anything leftover */
2306         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2307         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2308                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2309         I40E_WRITE_FLUSH(hw);
2310 }
2311
2312 /*
2313  * Reset PF device only to re-initialize resources in PMD layer
2314  */
2315 static int
2316 i40e_dev_reset(struct rte_eth_dev *dev)
2317 {
2318         int ret;
2319
2320         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2321          * its VF to make them align with it. The detailed notification
2322          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2323          * To avoid unexpected behavior in VF, currently reset of PF with
2324          * SR-IOV activation is not supported. It might be supported later.
2325          */
2326         if (dev->data->sriov.active)
2327                 return -ENOTSUP;
2328
2329         ret = eth_i40e_dev_uninit(dev);
2330         if (ret)
2331                 return ret;
2332
2333         ret = eth_i40e_dev_init(dev);
2334
2335         return ret;
2336 }
2337
2338 static void
2339 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2340 {
2341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2343         struct i40e_vsi *vsi = pf->main_vsi;
2344         int status;
2345
2346         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2347                                                      true, NULL, true);
2348         if (status != I40E_SUCCESS)
2349                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2350
2351         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2352                                                         TRUE, NULL);
2353         if (status != I40E_SUCCESS)
2354                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2355
2356 }
2357
2358 static void
2359 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2360 {
2361         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2362         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2363         struct i40e_vsi *vsi = pf->main_vsi;
2364         int status;
2365
2366         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2367                                                      false, NULL, true);
2368         if (status != I40E_SUCCESS)
2369                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2370
2371         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2372                                                         false, NULL);
2373         if (status != I40E_SUCCESS)
2374                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2375 }
2376
2377 static void
2378 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2379 {
2380         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2381         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382         struct i40e_vsi *vsi = pf->main_vsi;
2383         int ret;
2384
2385         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2386         if (ret != I40E_SUCCESS)
2387                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2388 }
2389
2390 static void
2391 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2392 {
2393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2395         struct i40e_vsi *vsi = pf->main_vsi;
2396         int ret;
2397
2398         if (dev->data->promiscuous == 1)
2399                 return; /* must remain in all_multicast mode */
2400
2401         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2402                                 vsi->seid, FALSE, NULL);
2403         if (ret != I40E_SUCCESS)
2404                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2405 }
2406
2407 /*
2408  * Set device link up.
2409  */
2410 static int
2411 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2412 {
2413         /* re-apply link speed setting */
2414         return i40e_apply_link_speed(dev);
2415 }
2416
2417 /*
2418  * Set device link down.
2419  */
2420 static int
2421 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2422 {
2423         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2424         uint8_t abilities = 0;
2425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426
2427         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2428         return i40e_phy_conf_link(hw, abilities, speed, false);
2429 }
2430
2431 static __rte_always_inline void
2432 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2433 {
2434 /* Link status registers and values*/
2435 #define I40E_PRTMAC_LINKSTA             0x001E2420
2436 #define I40E_REG_LINK_UP                0x40000080
2437 #define I40E_PRTMAC_MACC                0x001E24E0
2438 #define I40E_REG_MACC_25GB              0x00020000
2439 #define I40E_REG_SPEED_MASK             0x38000000
2440 #define I40E_REG_SPEED_100MB            0x00000000
2441 #define I40E_REG_SPEED_1GB              0x08000000
2442 #define I40E_REG_SPEED_10GB             0x10000000
2443 #define I40E_REG_SPEED_20GB             0x20000000
2444 #define I40E_REG_SPEED_25_40GB          0x18000000
2445         uint32_t link_speed;
2446         uint32_t reg_val;
2447
2448         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2449         link_speed = reg_val & I40E_REG_SPEED_MASK;
2450         reg_val &= I40E_REG_LINK_UP;
2451         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2452
2453         if (unlikely(link->link_status != 0))
2454                 return;
2455
2456         /* Parse the link status */
2457         switch (link_speed) {
2458         case I40E_REG_SPEED_100MB:
2459                 link->link_speed = ETH_SPEED_NUM_100M;
2460                 break;
2461         case I40E_REG_SPEED_1GB:
2462                 link->link_speed = ETH_SPEED_NUM_1G;
2463                 break;
2464         case I40E_REG_SPEED_10GB:
2465                 link->link_speed = ETH_SPEED_NUM_10G;
2466                 break;
2467         case I40E_REG_SPEED_20GB:
2468                 link->link_speed = ETH_SPEED_NUM_20G;
2469                 break;
2470         case I40E_REG_SPEED_25_40GB:
2471                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2472
2473                 if (reg_val & I40E_REG_MACC_25GB)
2474                         link->link_speed = ETH_SPEED_NUM_25G;
2475                 else
2476                         link->link_speed = ETH_SPEED_NUM_40G;
2477
2478                 break;
2479         default:
2480                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2481                 break;
2482         }
2483 }
2484
2485 static __rte_always_inline void
2486 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2487         bool enable_lse)
2488 {
2489 #define CHECK_INTERVAL             100  /* 100ms */
2490 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2491         uint32_t rep_cnt = MAX_REPEAT_TIME;
2492         struct i40e_link_status link_status;
2493         int status;
2494
2495         memset(&link_status, 0, sizeof(link_status));
2496
2497         do {
2498                 memset(&link_status, 0, sizeof(link_status));
2499
2500                 /* Get link status information from hardware */
2501                 status = i40e_aq_get_link_info(hw, enable_lse,
2502                                                 &link_status, NULL);
2503                 if (unlikely(status != I40E_SUCCESS)) {
2504                         link->link_speed = ETH_SPEED_NUM_100M;
2505                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2506                         PMD_DRV_LOG(ERR, "Failed to get link info");
2507                         return;
2508                 }
2509
2510                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2511                 if (unlikely(link->link_status != 0))
2512                         return;
2513
2514                 rte_delay_ms(CHECK_INTERVAL);
2515         } while (--rep_cnt);
2516
2517         /* Parse the link status */
2518         switch (link_status.link_speed) {
2519         case I40E_LINK_SPEED_100MB:
2520                 link->link_speed = ETH_SPEED_NUM_100M;
2521                 break;
2522         case I40E_LINK_SPEED_1GB:
2523                 link->link_speed = ETH_SPEED_NUM_1G;
2524                 break;
2525         case I40E_LINK_SPEED_10GB:
2526                 link->link_speed = ETH_SPEED_NUM_10G;
2527                 break;
2528         case I40E_LINK_SPEED_20GB:
2529                 link->link_speed = ETH_SPEED_NUM_20G;
2530                 break;
2531         case I40E_LINK_SPEED_25GB:
2532                 link->link_speed = ETH_SPEED_NUM_25G;
2533                 break;
2534         case I40E_LINK_SPEED_40GB:
2535                 link->link_speed = ETH_SPEED_NUM_40G;
2536                 break;
2537         default:
2538                 link->link_speed = ETH_SPEED_NUM_100M;
2539                 break;
2540         }
2541 }
2542
2543 int
2544 i40e_dev_link_update(struct rte_eth_dev *dev,
2545                      int wait_to_complete)
2546 {
2547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         struct rte_eth_link link;
2549         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2550         int ret;
2551
2552         memset(&link, 0, sizeof(link));
2553
2554         /* i40e uses full duplex only */
2555         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2556         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2557                         ETH_LINK_SPEED_FIXED);
2558
2559         if (!wait_to_complete)
2560                 update_link_no_wait(hw, &link);
2561         else
2562                 update_link_wait(hw, &link, enable_lse);
2563
2564         ret = rte_eth_linkstatus_set(dev, &link);
2565         i40e_notify_all_vfs_link_status(dev);
2566
2567         return ret;
2568 }
2569
2570 /* Get all the statistics of a VSI */
2571 void
2572 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2573 {
2574         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2575         struct i40e_eth_stats *nes = &vsi->eth_stats;
2576         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2577         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2578
2579         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2580                             vsi->offset_loaded, &oes->rx_bytes,
2581                             &nes->rx_bytes);
2582         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2583                             vsi->offset_loaded, &oes->rx_unicast,
2584                             &nes->rx_unicast);
2585         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2586                             vsi->offset_loaded, &oes->rx_multicast,
2587                             &nes->rx_multicast);
2588         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2589                             vsi->offset_loaded, &oes->rx_broadcast,
2590                             &nes->rx_broadcast);
2591         /* exclude CRC bytes */
2592         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2593                 nes->rx_broadcast) * ETHER_CRC_LEN;
2594
2595         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2596                             &oes->rx_discards, &nes->rx_discards);
2597         /* GLV_REPC not supported */
2598         /* GLV_RMPC not supported */
2599         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2600                             &oes->rx_unknown_protocol,
2601                             &nes->rx_unknown_protocol);
2602         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2603                             vsi->offset_loaded, &oes->tx_bytes,
2604                             &nes->tx_bytes);
2605         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2606                             vsi->offset_loaded, &oes->tx_unicast,
2607                             &nes->tx_unicast);
2608         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2609                             vsi->offset_loaded, &oes->tx_multicast,
2610                             &nes->tx_multicast);
2611         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2612                             vsi->offset_loaded,  &oes->tx_broadcast,
2613                             &nes->tx_broadcast);
2614         /* GLV_TDPC not supported */
2615         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2616                             &oes->tx_errors, &nes->tx_errors);
2617         vsi->offset_loaded = true;
2618
2619         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2620                     vsi->vsi_id);
2621         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2622         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2623         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2624         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2625         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2626         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2627                     nes->rx_unknown_protocol);
2628         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2629         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2630         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2631         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2632         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2633         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2634         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2635                     vsi->vsi_id);
2636 }
2637
2638 static void
2639 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2640 {
2641         unsigned int i;
2642         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2643         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2644
2645         /* Get rx/tx bytes of internal transfer packets */
2646         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2647                         I40E_GLV_GORCL(hw->port),
2648                         pf->offset_loaded,
2649                         &pf->internal_stats_offset.rx_bytes,
2650                         &pf->internal_stats.rx_bytes);
2651
2652         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2653                         I40E_GLV_GOTCL(hw->port),
2654                         pf->offset_loaded,
2655                         &pf->internal_stats_offset.tx_bytes,
2656                         &pf->internal_stats.tx_bytes);
2657         /* Get total internal rx packet count */
2658         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2659                             I40E_GLV_UPRCL(hw->port),
2660                             pf->offset_loaded,
2661                             &pf->internal_stats_offset.rx_unicast,
2662                             &pf->internal_stats.rx_unicast);
2663         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2664                             I40E_GLV_MPRCL(hw->port),
2665                             pf->offset_loaded,
2666                             &pf->internal_stats_offset.rx_multicast,
2667                             &pf->internal_stats.rx_multicast);
2668         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2669                             I40E_GLV_BPRCL(hw->port),
2670                             pf->offset_loaded,
2671                             &pf->internal_stats_offset.rx_broadcast,
2672                             &pf->internal_stats.rx_broadcast);
2673         /* Get total internal tx packet count */
2674         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2675                             I40E_GLV_UPTCL(hw->port),
2676                             pf->offset_loaded,
2677                             &pf->internal_stats_offset.tx_unicast,
2678                             &pf->internal_stats.tx_unicast);
2679         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2680                             I40E_GLV_MPTCL(hw->port),
2681                             pf->offset_loaded,
2682                             &pf->internal_stats_offset.tx_multicast,
2683                             &pf->internal_stats.tx_multicast);
2684         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2685                             I40E_GLV_BPTCL(hw->port),
2686                             pf->offset_loaded,
2687                             &pf->internal_stats_offset.tx_broadcast,
2688                             &pf->internal_stats.tx_broadcast);
2689
2690         /* exclude CRC size */
2691         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2692                 pf->internal_stats.rx_multicast +
2693                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2694
2695         /* Get statistics of struct i40e_eth_stats */
2696         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2697                             I40E_GLPRT_GORCL(hw->port),
2698                             pf->offset_loaded, &os->eth.rx_bytes,
2699                             &ns->eth.rx_bytes);
2700         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2701                             I40E_GLPRT_UPRCL(hw->port),
2702                             pf->offset_loaded, &os->eth.rx_unicast,
2703                             &ns->eth.rx_unicast);
2704         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2705                             I40E_GLPRT_MPRCL(hw->port),
2706                             pf->offset_loaded, &os->eth.rx_multicast,
2707                             &ns->eth.rx_multicast);
2708         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2709                             I40E_GLPRT_BPRCL(hw->port),
2710                             pf->offset_loaded, &os->eth.rx_broadcast,
2711                             &ns->eth.rx_broadcast);
2712         /* Workaround: CRC size should not be included in byte statistics,
2713          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2714          */
2715         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2716                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2717
2718         /* exclude internal rx bytes
2719          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2720          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2721          * value.
2722          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2723          */
2724         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2725                 ns->eth.rx_bytes = 0;
2726         else
2727                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2728
2729         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2730                 ns->eth.rx_unicast = 0;
2731         else
2732                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2733
2734         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2735                 ns->eth.rx_multicast = 0;
2736         else
2737                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2738
2739         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2740                 ns->eth.rx_broadcast = 0;
2741         else
2742                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2743
2744         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2745                             pf->offset_loaded, &os->eth.rx_discards,
2746                             &ns->eth.rx_discards);
2747         /* GLPRT_REPC not supported */
2748         /* GLPRT_RMPC not supported */
2749         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2750                             pf->offset_loaded,
2751                             &os->eth.rx_unknown_protocol,
2752                             &ns->eth.rx_unknown_protocol);
2753         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2754                             I40E_GLPRT_GOTCL(hw->port),
2755                             pf->offset_loaded, &os->eth.tx_bytes,
2756                             &ns->eth.tx_bytes);
2757         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2758                             I40E_GLPRT_UPTCL(hw->port),
2759                             pf->offset_loaded, &os->eth.tx_unicast,
2760                             &ns->eth.tx_unicast);
2761         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2762                             I40E_GLPRT_MPTCL(hw->port),
2763                             pf->offset_loaded, &os->eth.tx_multicast,
2764                             &ns->eth.tx_multicast);
2765         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2766                             I40E_GLPRT_BPTCL(hw->port),
2767                             pf->offset_loaded, &os->eth.tx_broadcast,
2768                             &ns->eth.tx_broadcast);
2769         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2770                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2771
2772         /* exclude internal tx bytes
2773          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2774          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2775          * value.
2776          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2777          */
2778         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2779                 ns->eth.tx_bytes = 0;
2780         else
2781                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2782
2783         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2784                 ns->eth.tx_unicast = 0;
2785         else
2786                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2787
2788         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2789                 ns->eth.tx_multicast = 0;
2790         else
2791                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2792
2793         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2794                 ns->eth.tx_broadcast = 0;
2795         else
2796                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2797
2798         /* GLPRT_TEPC not supported */
2799
2800         /* additional port specific stats */
2801         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2802                             pf->offset_loaded, &os->tx_dropped_link_down,
2803                             &ns->tx_dropped_link_down);
2804         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2805                             pf->offset_loaded, &os->crc_errors,
2806                             &ns->crc_errors);
2807         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2808                             pf->offset_loaded, &os->illegal_bytes,
2809                             &ns->illegal_bytes);
2810         /* GLPRT_ERRBC not supported */
2811         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2812                             pf->offset_loaded, &os->mac_local_faults,
2813                             &ns->mac_local_faults);
2814         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2815                             pf->offset_loaded, &os->mac_remote_faults,
2816                             &ns->mac_remote_faults);
2817         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2818                             pf->offset_loaded, &os->rx_length_errors,
2819                             &ns->rx_length_errors);
2820         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2821                             pf->offset_loaded, &os->link_xon_rx,
2822                             &ns->link_xon_rx);
2823         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2824                             pf->offset_loaded, &os->link_xoff_rx,
2825                             &ns->link_xoff_rx);
2826         for (i = 0; i < 8; i++) {
2827                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2828                                     pf->offset_loaded,
2829                                     &os->priority_xon_rx[i],
2830                                     &ns->priority_xon_rx[i]);
2831                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2832                                     pf->offset_loaded,
2833                                     &os->priority_xoff_rx[i],
2834                                     &ns->priority_xoff_rx[i]);
2835         }
2836         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2837                             pf->offset_loaded, &os->link_xon_tx,
2838                             &ns->link_xon_tx);
2839         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2840                             pf->offset_loaded, &os->link_xoff_tx,
2841                             &ns->link_xoff_tx);
2842         for (i = 0; i < 8; i++) {
2843                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2844                                     pf->offset_loaded,
2845                                     &os->priority_xon_tx[i],
2846                                     &ns->priority_xon_tx[i]);
2847                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2848                                     pf->offset_loaded,
2849                                     &os->priority_xoff_tx[i],
2850                                     &ns->priority_xoff_tx[i]);
2851                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2852                                     pf->offset_loaded,
2853                                     &os->priority_xon_2_xoff[i],
2854                                     &ns->priority_xon_2_xoff[i]);
2855         }
2856         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2857                             I40E_GLPRT_PRC64L(hw->port),
2858                             pf->offset_loaded, &os->rx_size_64,
2859                             &ns->rx_size_64);
2860         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2861                             I40E_GLPRT_PRC127L(hw->port),
2862                             pf->offset_loaded, &os->rx_size_127,
2863                             &ns->rx_size_127);
2864         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2865                             I40E_GLPRT_PRC255L(hw->port),
2866                             pf->offset_loaded, &os->rx_size_255,
2867                             &ns->rx_size_255);
2868         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2869                             I40E_GLPRT_PRC511L(hw->port),
2870                             pf->offset_loaded, &os->rx_size_511,
2871                             &ns->rx_size_511);
2872         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2873                             I40E_GLPRT_PRC1023L(hw->port),
2874                             pf->offset_loaded, &os->rx_size_1023,
2875                             &ns->rx_size_1023);
2876         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2877                             I40E_GLPRT_PRC1522L(hw->port),
2878                             pf->offset_loaded, &os->rx_size_1522,
2879                             &ns->rx_size_1522);
2880         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2881                             I40E_GLPRT_PRC9522L(hw->port),
2882                             pf->offset_loaded, &os->rx_size_big,
2883                             &ns->rx_size_big);
2884         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2885                             pf->offset_loaded, &os->rx_undersize,
2886                             &ns->rx_undersize);
2887         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2888                             pf->offset_loaded, &os->rx_fragments,
2889                             &ns->rx_fragments);
2890         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2891                             pf->offset_loaded, &os->rx_oversize,
2892                             &ns->rx_oversize);
2893         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2894                             pf->offset_loaded, &os->rx_jabber,
2895                             &ns->rx_jabber);
2896         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2897                             I40E_GLPRT_PTC64L(hw->port),
2898                             pf->offset_loaded, &os->tx_size_64,
2899                             &ns->tx_size_64);
2900         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2901                             I40E_GLPRT_PTC127L(hw->port),
2902                             pf->offset_loaded, &os->tx_size_127,
2903                             &ns->tx_size_127);
2904         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2905                             I40E_GLPRT_PTC255L(hw->port),
2906                             pf->offset_loaded, &os->tx_size_255,
2907                             &ns->tx_size_255);
2908         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2909                             I40E_GLPRT_PTC511L(hw->port),
2910                             pf->offset_loaded, &os->tx_size_511,
2911                             &ns->tx_size_511);
2912         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2913                             I40E_GLPRT_PTC1023L(hw->port),
2914                             pf->offset_loaded, &os->tx_size_1023,
2915                             &ns->tx_size_1023);
2916         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2917                             I40E_GLPRT_PTC1522L(hw->port),
2918                             pf->offset_loaded, &os->tx_size_1522,
2919                             &ns->tx_size_1522);
2920         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2921                             I40E_GLPRT_PTC9522L(hw->port),
2922                             pf->offset_loaded, &os->tx_size_big,
2923                             &ns->tx_size_big);
2924         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2925                            pf->offset_loaded,
2926                            &os->fd_sb_match, &ns->fd_sb_match);
2927         /* GLPRT_MSPDC not supported */
2928         /* GLPRT_XEC not supported */
2929
2930         pf->offset_loaded = true;
2931
2932         if (pf->main_vsi)
2933                 i40e_update_vsi_stats(pf->main_vsi);
2934 }
2935
2936 /* Get all statistics of a port */
2937 static int
2938 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2939 {
2940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2942         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2943         unsigned i;
2944
2945         /* call read registers - updates values, now write them to struct */
2946         i40e_read_stats_registers(pf, hw);
2947
2948         stats->ipackets = ns->eth.rx_unicast +
2949                         ns->eth.rx_multicast +
2950                         ns->eth.rx_broadcast -
2951                         ns->eth.rx_discards -
2952                         pf->main_vsi->eth_stats.rx_discards;
2953         stats->opackets = ns->eth.tx_unicast +
2954                         ns->eth.tx_multicast +
2955                         ns->eth.tx_broadcast;
2956         stats->ibytes   = ns->eth.rx_bytes;
2957         stats->obytes   = ns->eth.tx_bytes;
2958         stats->oerrors  = ns->eth.tx_errors +
2959                         pf->main_vsi->eth_stats.tx_errors;
2960
2961         /* Rx Errors */
2962         stats->imissed  = ns->eth.rx_discards +
2963                         pf->main_vsi->eth_stats.rx_discards;
2964         stats->ierrors  = ns->crc_errors +
2965                         ns->rx_length_errors + ns->rx_undersize +
2966                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2967
2968         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2969         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2970         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2971         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2972         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2973         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2974         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2975                     ns->eth.rx_unknown_protocol);
2976         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2977         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2978         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2979         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2980         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2981         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2982
2983         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2984                     ns->tx_dropped_link_down);
2985         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2986         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2987                     ns->illegal_bytes);
2988         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2989         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2990                     ns->mac_local_faults);
2991         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2992                     ns->mac_remote_faults);
2993         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2994                     ns->rx_length_errors);
2995         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2996         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2997         for (i = 0; i < 8; i++) {
2998                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2999                                 i, ns->priority_xon_rx[i]);
3000                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3001                                 i, ns->priority_xoff_rx[i]);
3002         }
3003         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3004         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3005         for (i = 0; i < 8; i++) {
3006                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3007                                 i, ns->priority_xon_tx[i]);
3008                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3009                                 i, ns->priority_xoff_tx[i]);
3010                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3011                                 i, ns->priority_xon_2_xoff[i]);
3012         }
3013         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3014         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3015         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3016         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3017         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3018         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3019         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3020         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3021         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3022         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3023         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3024         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3025         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3026         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3027         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3028         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3029         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3030         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3031         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3032                         ns->mac_short_packet_dropped);
3033         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3034                     ns->checksum_error);
3035         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3036         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3037         return 0;
3038 }
3039
3040 /* Reset the statistics */
3041 static void
3042 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3043 {
3044         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3046
3047         /* Mark PF and VSI stats to update the offset, aka "reset" */
3048         pf->offset_loaded = false;
3049         if (pf->main_vsi)
3050                 pf->main_vsi->offset_loaded = false;
3051
3052         /* read the stats, reading current register values into offset */
3053         i40e_read_stats_registers(pf, hw);
3054 }
3055
3056 static uint32_t
3057 i40e_xstats_calc_num(void)
3058 {
3059         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3060                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3061                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3062 }
3063
3064 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3065                                      struct rte_eth_xstat_name *xstats_names,
3066                                      __rte_unused unsigned limit)
3067 {
3068         unsigned count = 0;
3069         unsigned i, prio;
3070
3071         if (xstats_names == NULL)
3072                 return i40e_xstats_calc_num();
3073
3074         /* Note: limit checked in rte_eth_xstats_names() */
3075
3076         /* Get stats from i40e_eth_stats struct */
3077         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3078                 snprintf(xstats_names[count].name,
3079                          sizeof(xstats_names[count].name),
3080                          "%s", rte_i40e_stats_strings[i].name);
3081                 count++;
3082         }
3083
3084         /* Get individiual stats from i40e_hw_port struct */
3085         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3086                 snprintf(xstats_names[count].name,
3087                         sizeof(xstats_names[count].name),
3088                          "%s", rte_i40e_hw_port_strings[i].name);
3089                 count++;
3090         }
3091
3092         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3093                 for (prio = 0; prio < 8; prio++) {
3094                         snprintf(xstats_names[count].name,
3095                                  sizeof(xstats_names[count].name),
3096                                  "rx_priority%u_%s", prio,
3097                                  rte_i40e_rxq_prio_strings[i].name);
3098                         count++;
3099                 }
3100         }
3101
3102         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3103                 for (prio = 0; prio < 8; prio++) {
3104                         snprintf(xstats_names[count].name,
3105                                  sizeof(xstats_names[count].name),
3106                                  "tx_priority%u_%s", prio,
3107                                  rte_i40e_txq_prio_strings[i].name);
3108                         count++;
3109                 }
3110         }
3111         return count;
3112 }
3113
3114 static int
3115 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3116                     unsigned n)
3117 {
3118         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3120         unsigned i, count, prio;
3121         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3122
3123         count = i40e_xstats_calc_num();
3124         if (n < count)
3125                 return count;
3126
3127         i40e_read_stats_registers(pf, hw);
3128
3129         if (xstats == NULL)
3130                 return 0;
3131
3132         count = 0;
3133
3134         /* Get stats from i40e_eth_stats struct */
3135         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3136                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3137                         rte_i40e_stats_strings[i].offset);
3138                 xstats[count].id = count;
3139                 count++;
3140         }
3141
3142         /* Get individiual stats from i40e_hw_port struct */
3143         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3144                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3145                         rte_i40e_hw_port_strings[i].offset);
3146                 xstats[count].id = count;
3147                 count++;
3148         }
3149
3150         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3151                 for (prio = 0; prio < 8; prio++) {
3152                         xstats[count].value =
3153                                 *(uint64_t *)(((char *)hw_stats) +
3154                                 rte_i40e_rxq_prio_strings[i].offset +
3155                                 (sizeof(uint64_t) * prio));
3156                         xstats[count].id = count;
3157                         count++;
3158                 }
3159         }
3160
3161         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3162                 for (prio = 0; prio < 8; prio++) {
3163                         xstats[count].value =
3164                                 *(uint64_t *)(((char *)hw_stats) +
3165                                 rte_i40e_txq_prio_strings[i].offset +
3166                                 (sizeof(uint64_t) * prio));
3167                         xstats[count].id = count;
3168                         count++;
3169                 }
3170         }
3171
3172         return count;
3173 }
3174
3175 static int
3176 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3177                                  __rte_unused uint16_t queue_id,
3178                                  __rte_unused uint8_t stat_idx,
3179                                  __rte_unused uint8_t is_rx)
3180 {
3181         PMD_INIT_FUNC_TRACE();
3182
3183         return -ENOSYS;
3184 }
3185
3186 static int
3187 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3188 {
3189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3190         u32 full_ver;
3191         u8 ver, patch;
3192         u16 build;
3193         int ret;
3194
3195         full_ver = hw->nvm.oem_ver;
3196         ver = (u8)(full_ver >> 24);
3197         build = (u16)((full_ver >> 8) & 0xffff);
3198         patch = (u8)(full_ver & 0xff);
3199
3200         ret = snprintf(fw_version, fw_size,
3201                  "%d.%d%d 0x%08x %d.%d.%d",
3202                  ((hw->nvm.version >> 12) & 0xf),
3203                  ((hw->nvm.version >> 4) & 0xff),
3204                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3205                  ver, build, patch);
3206
3207         ret += 1; /* add the size of '\0' */
3208         if (fw_size < (u32)ret)
3209                 return ret;
3210         else
3211                 return 0;
3212 }
3213
3214 static void
3215 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3216 {
3217         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3218         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3219         struct i40e_vsi *vsi = pf->main_vsi;
3220         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3221
3222         dev_info->max_rx_queues = vsi->nb_qps;
3223         dev_info->max_tx_queues = vsi->nb_qps;
3224         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3225         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3226         dev_info->max_mac_addrs = vsi->max_macaddrs;
3227         dev_info->max_vfs = pci_dev->max_vfs;
3228         dev_info->rx_queue_offload_capa = 0;
3229         dev_info->rx_offload_capa =
3230                 DEV_RX_OFFLOAD_VLAN_STRIP |
3231                 DEV_RX_OFFLOAD_QINQ_STRIP |
3232                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3233                 DEV_RX_OFFLOAD_UDP_CKSUM |
3234                 DEV_RX_OFFLOAD_TCP_CKSUM |
3235                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3236                 DEV_RX_OFFLOAD_CRC_STRIP |
3237                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3238                 DEV_RX_OFFLOAD_VLAN_FILTER;
3239
3240         dev_info->tx_queue_offload_capa = 0;
3241         dev_info->tx_offload_capa =
3242                 DEV_TX_OFFLOAD_VLAN_INSERT |
3243                 DEV_TX_OFFLOAD_QINQ_INSERT |
3244                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3245                 DEV_TX_OFFLOAD_UDP_CKSUM |
3246                 DEV_TX_OFFLOAD_TCP_CKSUM |
3247                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3248                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3249                 DEV_TX_OFFLOAD_TCP_TSO |
3250                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3251                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3252                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3253                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3254         dev_info->dev_capa =
3255                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3256                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3257
3258         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3259                                                 sizeof(uint32_t);
3260         dev_info->reta_size = pf->hash_lut_size;
3261         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3262
3263         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3264                 .rx_thresh = {
3265                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3266                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3267                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3268                 },
3269                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3270                 .rx_drop_en = 0,
3271                 .offloads = 0,
3272         };
3273
3274         dev_info->default_txconf = (struct rte_eth_txconf) {
3275                 .tx_thresh = {
3276                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3277                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3278                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3279                 },
3280                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3281                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3282                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3283                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3284         };
3285
3286         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3287                 .nb_max = I40E_MAX_RING_DESC,
3288                 .nb_min = I40E_MIN_RING_DESC,
3289                 .nb_align = I40E_ALIGN_RING_DESC,
3290         };
3291
3292         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3293                 .nb_max = I40E_MAX_RING_DESC,
3294                 .nb_min = I40E_MIN_RING_DESC,
3295                 .nb_align = I40E_ALIGN_RING_DESC,
3296                 .nb_seg_max = I40E_TX_MAX_SEG,
3297                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3298         };
3299
3300         if (pf->flags & I40E_FLAG_VMDQ) {
3301                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3302                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3303                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3304                                                 pf->max_nb_vmdq_vsi;
3305                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3306                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3307                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3308         }
3309
3310         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3311                 /* For XL710 */
3312                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3313                 dev_info->default_rxportconf.nb_queues = 2;
3314                 dev_info->default_txportconf.nb_queues = 2;
3315                 if (dev->data->nb_rx_queues == 1)
3316                         dev_info->default_rxportconf.ring_size = 2048;
3317                 else
3318                         dev_info->default_rxportconf.ring_size = 1024;
3319                 if (dev->data->nb_tx_queues == 1)
3320                         dev_info->default_txportconf.ring_size = 1024;
3321                 else
3322                         dev_info->default_txportconf.ring_size = 512;
3323
3324         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3325                 /* For XXV710 */
3326                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3327                 dev_info->default_rxportconf.nb_queues = 1;
3328                 dev_info->default_txportconf.nb_queues = 1;
3329                 dev_info->default_rxportconf.ring_size = 256;
3330                 dev_info->default_txportconf.ring_size = 256;
3331         } else {
3332                 /* For X710 */
3333                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3334                 dev_info->default_rxportconf.nb_queues = 1;
3335                 dev_info->default_txportconf.nb_queues = 1;
3336                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3337                         dev_info->default_rxportconf.ring_size = 512;
3338                         dev_info->default_txportconf.ring_size = 256;
3339                 } else {
3340                         dev_info->default_rxportconf.ring_size = 256;
3341                         dev_info->default_txportconf.ring_size = 256;
3342                 }
3343         }
3344         dev_info->default_rxportconf.burst_size = 32;
3345         dev_info->default_txportconf.burst_size = 32;
3346 }
3347
3348 static int
3349 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3350 {
3351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3352         struct i40e_vsi *vsi = pf->main_vsi;
3353         PMD_INIT_FUNC_TRACE();
3354
3355         if (on)
3356                 return i40e_vsi_add_vlan(vsi, vlan_id);
3357         else
3358                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3359 }
3360
3361 static int
3362 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3363                                 enum rte_vlan_type vlan_type,
3364                                 uint16_t tpid, int qinq)
3365 {
3366         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3367         uint64_t reg_r = 0;
3368         uint64_t reg_w = 0;
3369         uint16_t reg_id = 3;
3370         int ret;
3371
3372         if (qinq) {
3373                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3374                         reg_id = 2;
3375         }
3376
3377         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3378                                           &reg_r, NULL);
3379         if (ret != I40E_SUCCESS) {
3380                 PMD_DRV_LOG(ERR,
3381                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3382                            reg_id);
3383                 return -EIO;
3384         }
3385         PMD_DRV_LOG(DEBUG,
3386                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3387                     reg_id, reg_r);
3388
3389         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3390         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3391         if (reg_r == reg_w) {
3392                 PMD_DRV_LOG(DEBUG, "No need to write");
3393                 return 0;
3394         }
3395
3396         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3397                                            reg_w, NULL);
3398         if (ret != I40E_SUCCESS) {
3399                 PMD_DRV_LOG(ERR,
3400                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3401                             reg_id);
3402                 return -EIO;
3403         }
3404         PMD_DRV_LOG(DEBUG,
3405                     "Global register 0x%08x is changed with value 0x%08x",
3406                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3407
3408         return 0;
3409 }
3410
3411 static int
3412 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3413                    enum rte_vlan_type vlan_type,
3414                    uint16_t tpid)
3415 {
3416         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         int qinq = dev->data->dev_conf.rxmode.offloads &
3419                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3420         int ret = 0;
3421
3422         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3423              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3424             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3425                 PMD_DRV_LOG(ERR,
3426                             "Unsupported vlan type.");
3427                 return -EINVAL;
3428         }
3429
3430         if (pf->support_multi_driver) {
3431                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3432                 return -ENOTSUP;
3433         }
3434
3435         /* 802.1ad frames ability is added in NVM API 1.7*/
3436         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3437                 if (qinq) {
3438                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3439                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3440                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3441                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3442                 } else {
3443                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3444                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3445                 }
3446                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3447                 if (ret != I40E_SUCCESS) {
3448                         PMD_DRV_LOG(ERR,
3449                                     "Set switch config failed aq_err: %d",
3450                                     hw->aq.asq_last_status);
3451                         ret = -EIO;
3452                 }
3453         } else
3454                 /* If NVM API < 1.7, keep the register setting */
3455                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3456                                                       tpid, qinq);
3457         i40e_global_cfg_warning(I40E_WARNING_TPID);
3458
3459         return ret;
3460 }
3461
3462 static int
3463 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3464 {
3465         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466         struct i40e_vsi *vsi = pf->main_vsi;
3467         struct rte_eth_rxmode *rxmode;
3468
3469         rxmode = &dev->data->dev_conf.rxmode;
3470         if (mask & ETH_VLAN_FILTER_MASK) {
3471                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3472                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3473                 else
3474                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3475         }
3476
3477         if (mask & ETH_VLAN_STRIP_MASK) {
3478                 /* Enable or disable VLAN stripping */
3479                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3480                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3481                 else
3482                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3483         }
3484
3485         if (mask & ETH_VLAN_EXTEND_MASK) {
3486                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3487                         i40e_vsi_config_double_vlan(vsi, TRUE);
3488                         /* Set global registers with default ethertype. */
3489                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3490                                            ETHER_TYPE_VLAN);
3491                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3492                                            ETHER_TYPE_VLAN);
3493                 }
3494                 else
3495                         i40e_vsi_config_double_vlan(vsi, FALSE);
3496         }
3497
3498         return 0;
3499 }
3500
3501 static void
3502 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3503                           __rte_unused uint16_t queue,
3504                           __rte_unused int on)
3505 {
3506         PMD_INIT_FUNC_TRACE();
3507 }
3508
3509 static int
3510 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3511 {
3512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3513         struct i40e_vsi *vsi = pf->main_vsi;
3514         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3515         struct i40e_vsi_vlan_pvid_info info;
3516
3517         memset(&info, 0, sizeof(info));
3518         info.on = on;
3519         if (info.on)
3520                 info.config.pvid = pvid;
3521         else {
3522                 info.config.reject.tagged =
3523                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3524                 info.config.reject.untagged =
3525                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3526         }
3527
3528         return i40e_vsi_vlan_pvid_set(vsi, &info);
3529 }
3530
3531 static int
3532 i40e_dev_led_on(struct rte_eth_dev *dev)
3533 {
3534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3535         uint32_t mode = i40e_led_get(hw);
3536
3537         if (mode == 0)
3538                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3539
3540         return 0;
3541 }
3542
3543 static int
3544 i40e_dev_led_off(struct rte_eth_dev *dev)
3545 {
3546         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3547         uint32_t mode = i40e_led_get(hw);
3548
3549         if (mode != 0)
3550                 i40e_led_set(hw, 0, false);
3551
3552         return 0;
3553 }
3554
3555 static int
3556 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3557 {
3558         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3559         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3560
3561         fc_conf->pause_time = pf->fc_conf.pause_time;
3562
3563         /* read out from register, in case they are modified by other port */
3564         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3565                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3566         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3567                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3568
3569         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3570         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3571
3572          /* Return current mode according to actual setting*/
3573         switch (hw->fc.current_mode) {
3574         case I40E_FC_FULL:
3575                 fc_conf->mode = RTE_FC_FULL;
3576                 break;
3577         case I40E_FC_TX_PAUSE:
3578                 fc_conf->mode = RTE_FC_TX_PAUSE;
3579                 break;
3580         case I40E_FC_RX_PAUSE:
3581                 fc_conf->mode = RTE_FC_RX_PAUSE;
3582                 break;
3583         case I40E_FC_NONE:
3584         default:
3585                 fc_conf->mode = RTE_FC_NONE;
3586         };
3587
3588         return 0;
3589 }
3590
3591 static int
3592 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3593 {
3594         uint32_t mflcn_reg, fctrl_reg, reg;
3595         uint32_t max_high_water;
3596         uint8_t i, aq_failure;
3597         int err;
3598         struct i40e_hw *hw;
3599         struct i40e_pf *pf;
3600         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3601                 [RTE_FC_NONE] = I40E_FC_NONE,
3602                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3603                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3604                 [RTE_FC_FULL] = I40E_FC_FULL
3605         };
3606
3607         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3608
3609         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3610         if ((fc_conf->high_water > max_high_water) ||
3611                         (fc_conf->high_water < fc_conf->low_water)) {
3612                 PMD_INIT_LOG(ERR,
3613                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3614                         max_high_water);
3615                 return -EINVAL;
3616         }
3617
3618         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3619         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3620         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3621
3622         pf->fc_conf.pause_time = fc_conf->pause_time;
3623         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3624         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3625
3626         PMD_INIT_FUNC_TRACE();
3627
3628         /* All the link flow control related enable/disable register
3629          * configuration is handle by the F/W
3630          */
3631         err = i40e_set_fc(hw, &aq_failure, true);
3632         if (err < 0)
3633                 return -ENOSYS;
3634
3635         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3636                 /* Configure flow control refresh threshold,
3637                  * the value for stat_tx_pause_refresh_timer[8]
3638                  * is used for global pause operation.
3639                  */
3640
3641                 I40E_WRITE_REG(hw,
3642                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3643                                pf->fc_conf.pause_time);
3644
3645                 /* configure the timer value included in transmitted pause
3646                  * frame,
3647                  * the value for stat_tx_pause_quanta[8] is used for global
3648                  * pause operation
3649                  */
3650                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3651                                pf->fc_conf.pause_time);
3652
3653                 fctrl_reg = I40E_READ_REG(hw,
3654                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3655
3656                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3657                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3658                 else
3659                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3660
3661                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3662                                fctrl_reg);
3663         } else {
3664                 /* Configure pause time (2 TCs per register) */
3665                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3666                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3667                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3668
3669                 /* Configure flow control refresh threshold value */
3670                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3671                                pf->fc_conf.pause_time / 2);
3672
3673                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3674
3675                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3676                  *depending on configuration
3677                  */
3678                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3679                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3680                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3681                 } else {
3682                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3683                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3684                 }
3685
3686                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3687         }
3688
3689         if (!pf->support_multi_driver) {
3690                 /* config water marker both based on the packets and bytes */
3691                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3692                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3693                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3694                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3695                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3696                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3697                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3698                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3699                                   << I40E_KILOSHIFT);
3700                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3701                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3702                                    << I40E_KILOSHIFT);
3703                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3704         } else {
3705                 PMD_DRV_LOG(ERR,
3706                             "Water marker configuration is not supported.");
3707         }
3708
3709         I40E_WRITE_FLUSH(hw);
3710
3711         return 0;
3712 }
3713
3714 static int
3715 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3716                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3717 {
3718         PMD_INIT_FUNC_TRACE();
3719
3720         return -ENOSYS;
3721 }
3722
3723 /* Add a MAC address, and update filters */
3724 static int
3725 i40e_macaddr_add(struct rte_eth_dev *dev,
3726                  struct ether_addr *mac_addr,
3727                  __rte_unused uint32_t index,
3728                  uint32_t pool)
3729 {
3730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3731         struct i40e_mac_filter_info mac_filter;
3732         struct i40e_vsi *vsi;
3733         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3734         int ret;
3735
3736         /* If VMDQ not enabled or configured, return */
3737         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3738                           !pf->nb_cfg_vmdq_vsi)) {
3739                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3740                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3741                         pool);
3742                 return -ENOTSUP;
3743         }
3744
3745         if (pool > pf->nb_cfg_vmdq_vsi) {
3746                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3747                                 pool, pf->nb_cfg_vmdq_vsi);
3748                 return -EINVAL;
3749         }
3750
3751         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3752         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3753                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3754         else
3755                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3756
3757         if (pool == 0)
3758                 vsi = pf->main_vsi;
3759         else
3760                 vsi = pf->vmdq[pool - 1].vsi;
3761
3762         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3763         if (ret != I40E_SUCCESS) {
3764                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3765                 return -ENODEV;
3766         }
3767         return 0;
3768 }
3769
3770 /* Remove a MAC address, and update filters */
3771 static void
3772 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3773 {
3774         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3775         struct i40e_vsi *vsi;
3776         struct rte_eth_dev_data *data = dev->data;
3777         struct ether_addr *macaddr;
3778         int ret;
3779         uint32_t i;
3780         uint64_t pool_sel;
3781
3782         macaddr = &(data->mac_addrs[index]);
3783
3784         pool_sel = dev->data->mac_pool_sel[index];
3785
3786         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3787                 if (pool_sel & (1ULL << i)) {
3788                         if (i == 0)
3789                                 vsi = pf->main_vsi;
3790                         else {
3791                                 /* No VMDQ pool enabled or configured */
3792                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3793                                         (i > pf->nb_cfg_vmdq_vsi)) {
3794                                         PMD_DRV_LOG(ERR,
3795                                                 "No VMDQ pool enabled/configured");
3796                                         return;
3797                                 }
3798                                 vsi = pf->vmdq[i - 1].vsi;
3799                         }
3800                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3801
3802                         if (ret) {
3803                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3804                                 return;
3805                         }
3806                 }
3807         }
3808 }
3809
3810 /* Set perfect match or hash match of MAC and VLAN for a VF */
3811 static int
3812 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3813                  struct rte_eth_mac_filter *filter,
3814                  bool add)
3815 {
3816         struct i40e_hw *hw;
3817         struct i40e_mac_filter_info mac_filter;
3818         struct ether_addr old_mac;
3819         struct ether_addr *new_mac;
3820         struct i40e_pf_vf *vf = NULL;
3821         uint16_t vf_id;
3822         int ret;
3823
3824         if (pf == NULL) {
3825                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3826                 return -EINVAL;
3827         }
3828         hw = I40E_PF_TO_HW(pf);
3829
3830         if (filter == NULL) {
3831                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3832                 return -EINVAL;
3833         }
3834
3835         new_mac = &filter->mac_addr;
3836
3837         if (is_zero_ether_addr(new_mac)) {
3838                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3839                 return -EINVAL;
3840         }
3841
3842         vf_id = filter->dst_id;
3843
3844         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3845                 PMD_DRV_LOG(ERR, "Invalid argument.");
3846                 return -EINVAL;
3847         }
3848         vf = &pf->vfs[vf_id];
3849
3850         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3851                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3852                 return -EINVAL;
3853         }
3854
3855         if (add) {
3856                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3857                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3858                                 ETHER_ADDR_LEN);
3859                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3860                                  ETHER_ADDR_LEN);
3861
3862                 mac_filter.filter_type = filter->filter_type;
3863                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3864                 if (ret != I40E_SUCCESS) {
3865                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3866                         return -1;
3867                 }
3868                 ether_addr_copy(new_mac, &pf->dev_addr);
3869         } else {
3870                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3871                                 ETHER_ADDR_LEN);
3872                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3873                 if (ret != I40E_SUCCESS) {
3874                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3875                         return -1;
3876                 }
3877
3878                 /* Clear device address as it has been removed */
3879                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3880                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3881         }
3882
3883         return 0;
3884 }
3885
3886 /* MAC filter handle */
3887 static int
3888 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3889                 void *arg)
3890 {
3891         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3892         struct rte_eth_mac_filter *filter;
3893         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3894         int ret = I40E_NOT_SUPPORTED;
3895
3896         filter = (struct rte_eth_mac_filter *)(arg);
3897
3898         switch (filter_op) {
3899         case RTE_ETH_FILTER_NOP:
3900                 ret = I40E_SUCCESS;
3901                 break;
3902         case RTE_ETH_FILTER_ADD:
3903                 i40e_pf_disable_irq0(hw);
3904                 if (filter->is_vf)
3905                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3906                 i40e_pf_enable_irq0(hw);
3907                 break;
3908         case RTE_ETH_FILTER_DELETE:
3909                 i40e_pf_disable_irq0(hw);
3910                 if (filter->is_vf)
3911                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3912                 i40e_pf_enable_irq0(hw);
3913                 break;
3914         default:
3915                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3916                 ret = I40E_ERR_PARAM;
3917                 break;
3918         }
3919
3920         return ret;
3921 }
3922
3923 static int
3924 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3925 {
3926         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3927         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3928         uint32_t reg;
3929         int ret;
3930
3931         if (!lut)
3932                 return -EINVAL;
3933
3934         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3935                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3936                                           lut, lut_size);
3937                 if (ret) {
3938                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3939                         return ret;
3940                 }
3941         } else {
3942                 uint32_t *lut_dw = (uint32_t *)lut;
3943                 uint16_t i, lut_size_dw = lut_size / 4;
3944
3945                 if (vsi->type == I40E_VSI_SRIOV) {
3946                         for (i = 0; i <= lut_size_dw; i++) {
3947                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3948                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3949                         }
3950                 } else {
3951                         for (i = 0; i < lut_size_dw; i++)
3952                                 lut_dw[i] = I40E_READ_REG(hw,
3953                                                           I40E_PFQF_HLUT(i));
3954                 }
3955         }
3956
3957         return 0;
3958 }
3959
3960 int
3961 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3962 {
3963         struct i40e_pf *pf;
3964         struct i40e_hw *hw;
3965         int ret;
3966
3967         if (!vsi || !lut)
3968                 return -EINVAL;
3969
3970         pf = I40E_VSI_TO_PF(vsi);
3971         hw = I40E_VSI_TO_HW(vsi);
3972
3973         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3974                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3975                                           lut, lut_size);
3976                 if (ret) {
3977                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3978                         return ret;
3979                 }
3980         } else {
3981                 uint32_t *lut_dw = (uint32_t *)lut;
3982                 uint16_t i, lut_size_dw = lut_size / 4;
3983
3984                 if (vsi->type == I40E_VSI_SRIOV) {
3985                         for (i = 0; i < lut_size_dw; i++)
3986                                 I40E_WRITE_REG(
3987                                         hw,
3988                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3989                                         lut_dw[i]);
3990                 } else {
3991                         for (i = 0; i < lut_size_dw; i++)
3992                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3993                                                lut_dw[i]);
3994                 }
3995                 I40E_WRITE_FLUSH(hw);
3996         }
3997
3998         return 0;
3999 }
4000
4001 static int
4002 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4003                          struct rte_eth_rss_reta_entry64 *reta_conf,
4004                          uint16_t reta_size)
4005 {
4006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4007         uint16_t i, lut_size = pf->hash_lut_size;
4008         uint16_t idx, shift;
4009         uint8_t *lut;
4010         int ret;
4011
4012         if (reta_size != lut_size ||
4013                 reta_size > ETH_RSS_RETA_SIZE_512) {
4014                 PMD_DRV_LOG(ERR,
4015                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4016                         reta_size, lut_size);
4017                 return -EINVAL;
4018         }
4019
4020         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4021         if (!lut) {
4022                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4023                 return -ENOMEM;
4024         }
4025         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4026         if (ret)
4027                 goto out;
4028         for (i = 0; i < reta_size; i++) {
4029                 idx = i / RTE_RETA_GROUP_SIZE;
4030                 shift = i % RTE_RETA_GROUP_SIZE;
4031                 if (reta_conf[idx].mask & (1ULL << shift))
4032                         lut[i] = reta_conf[idx].reta[shift];
4033         }
4034         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4035
4036 out:
4037         rte_free(lut);
4038
4039         return ret;
4040 }
4041
4042 static int
4043 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4044                         struct rte_eth_rss_reta_entry64 *reta_conf,
4045                         uint16_t reta_size)
4046 {
4047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4048         uint16_t i, lut_size = pf->hash_lut_size;
4049         uint16_t idx, shift;
4050         uint8_t *lut;
4051         int ret;
4052
4053         if (reta_size != lut_size ||
4054                 reta_size > ETH_RSS_RETA_SIZE_512) {
4055                 PMD_DRV_LOG(ERR,
4056                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4057                         reta_size, lut_size);
4058                 return -EINVAL;
4059         }
4060
4061         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4062         if (!lut) {
4063                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4064                 return -ENOMEM;
4065         }
4066
4067         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4068         if (ret)
4069                 goto out;
4070         for (i = 0; i < reta_size; i++) {
4071                 idx = i / RTE_RETA_GROUP_SIZE;
4072                 shift = i % RTE_RETA_GROUP_SIZE;
4073                 if (reta_conf[idx].mask & (1ULL << shift))
4074                         reta_conf[idx].reta[shift] = lut[i];
4075         }
4076
4077 out:
4078         rte_free(lut);
4079
4080         return ret;
4081 }
4082
4083 /**
4084  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4085  * @hw:   pointer to the HW structure
4086  * @mem:  pointer to mem struct to fill out
4087  * @size: size of memory requested
4088  * @alignment: what to align the allocation to
4089  **/
4090 enum i40e_status_code
4091 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4092                         struct i40e_dma_mem *mem,
4093                         u64 size,
4094                         u32 alignment)
4095 {
4096         const struct rte_memzone *mz = NULL;
4097         char z_name[RTE_MEMZONE_NAMESIZE];
4098
4099         if (!mem)
4100                 return I40E_ERR_PARAM;
4101
4102         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4103         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4104                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4105         if (!mz)
4106                 return I40E_ERR_NO_MEMORY;
4107
4108         mem->size = size;
4109         mem->va = mz->addr;
4110         mem->pa = mz->iova;
4111         mem->zone = (const void *)mz;
4112         PMD_DRV_LOG(DEBUG,
4113                 "memzone %s allocated with physical address: %"PRIu64,
4114                 mz->name, mem->pa);
4115
4116         return I40E_SUCCESS;
4117 }
4118
4119 /**
4120  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4121  * @hw:   pointer to the HW structure
4122  * @mem:  ptr to mem struct to free
4123  **/
4124 enum i40e_status_code
4125 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4126                     struct i40e_dma_mem *mem)
4127 {
4128         if (!mem)
4129                 return I40E_ERR_PARAM;
4130
4131         PMD_DRV_LOG(DEBUG,
4132                 "memzone %s to be freed with physical address: %"PRIu64,
4133                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4134         rte_memzone_free((const struct rte_memzone *)mem->zone);
4135         mem->zone = NULL;
4136         mem->va = NULL;
4137         mem->pa = (u64)0;
4138
4139         return I40E_SUCCESS;
4140 }
4141
4142 /**
4143  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4144  * @hw:   pointer to the HW structure
4145  * @mem:  pointer to mem struct to fill out
4146  * @size: size of memory requested
4147  **/
4148 enum i40e_status_code
4149 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4150                          struct i40e_virt_mem *mem,
4151                          u32 size)
4152 {
4153         if (!mem)
4154                 return I40E_ERR_PARAM;
4155
4156         mem->size = size;
4157         mem->va = rte_zmalloc("i40e", size, 0);
4158
4159         if (mem->va)
4160                 return I40E_SUCCESS;
4161         else
4162                 return I40E_ERR_NO_MEMORY;
4163 }
4164
4165 /**
4166  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4167  * @hw:   pointer to the HW structure
4168  * @mem:  pointer to mem struct to free
4169  **/
4170 enum i40e_status_code
4171 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4172                      struct i40e_virt_mem *mem)
4173 {
4174         if (!mem)
4175                 return I40E_ERR_PARAM;
4176
4177         rte_free(mem->va);
4178         mem->va = NULL;
4179
4180         return I40E_SUCCESS;
4181 }
4182
4183 void
4184 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4185 {
4186         rte_spinlock_init(&sp->spinlock);
4187 }
4188
4189 void
4190 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4191 {
4192         rte_spinlock_lock(&sp->spinlock);
4193 }
4194
4195 void
4196 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4197 {
4198         rte_spinlock_unlock(&sp->spinlock);
4199 }
4200
4201 void
4202 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4203 {
4204         return;
4205 }
4206
4207 /**
4208  * Get the hardware capabilities, which will be parsed
4209  * and saved into struct i40e_hw.
4210  */
4211 static int
4212 i40e_get_cap(struct i40e_hw *hw)
4213 {
4214         struct i40e_aqc_list_capabilities_element_resp *buf;
4215         uint16_t len, size = 0;
4216         int ret;
4217
4218         /* Calculate a huge enough buff for saving response data temporarily */
4219         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4220                                                 I40E_MAX_CAP_ELE_NUM;
4221         buf = rte_zmalloc("i40e", len, 0);
4222         if (!buf) {
4223                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4224                 return I40E_ERR_NO_MEMORY;
4225         }
4226
4227         /* Get, parse the capabilities and save it to hw */
4228         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4229                         i40e_aqc_opc_list_func_capabilities, NULL);
4230         if (ret != I40E_SUCCESS)
4231                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4232
4233         /* Free the temporary buffer after being used */
4234         rte_free(buf);
4235
4236         return ret;
4237 }
4238
4239 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4240 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4241
4242 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4243                 const char *value,
4244                 void *opaque)
4245 {
4246         struct i40e_pf *pf;
4247         unsigned long num;
4248         char *end;
4249
4250         pf = (struct i40e_pf *)opaque;
4251         RTE_SET_USED(key);
4252
4253         errno = 0;
4254         num = strtoul(value, &end, 0);
4255         if (errno != 0 || end == value || *end != 0) {
4256                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4257                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4258                 return -(EINVAL);
4259         }
4260
4261         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4262                 pf->vf_nb_qp_max = (uint16_t)num;
4263         else
4264                 /* here return 0 to make next valid same argument work */
4265                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4266                             "power of 2 and equal or less than 16 !, Now it is "
4267                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4268
4269         return 0;
4270 }
4271
4272 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4273 {
4274         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4276         struct rte_kvargs *kvlist;
4277
4278         /* set default queue number per VF as 4 */
4279         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4280
4281         if (dev->device->devargs == NULL)
4282                 return 0;
4283
4284         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4285         if (kvlist == NULL)
4286                 return -(EINVAL);
4287
4288         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4289                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4290                             "the first invalid or last valid one is used !",
4291                             QUEUE_NUM_PER_VF_ARG);
4292
4293         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4294                            i40e_pf_parse_vf_queue_number_handler, pf);
4295
4296         rte_kvargs_free(kvlist);
4297
4298         return 0;
4299 }
4300
4301 static int
4302 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4303 {
4304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4306         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4307         uint16_t qp_count = 0, vsi_count = 0;
4308
4309         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4310                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4311                 return -EINVAL;
4312         }
4313
4314         i40e_pf_config_vf_rxq_number(dev);
4315
4316         /* Add the parameter init for LFC */
4317         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4318         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4319         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4320
4321         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4322         pf->max_num_vsi = hw->func_caps.num_vsis;
4323         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4324         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4325
4326         /* FDir queue/VSI allocation */
4327         pf->fdir_qp_offset = 0;
4328         if (hw->func_caps.fd) {
4329                 pf->flags |= I40E_FLAG_FDIR;
4330                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4331         } else {
4332                 pf->fdir_nb_qps = 0;
4333         }
4334         qp_count += pf->fdir_nb_qps;
4335         vsi_count += 1;
4336
4337         /* LAN queue/VSI allocation */
4338         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4339         if (!hw->func_caps.rss) {
4340                 pf->lan_nb_qps = 1;
4341         } else {
4342                 pf->flags |= I40E_FLAG_RSS;
4343                 if (hw->mac.type == I40E_MAC_X722)
4344                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4345                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4346         }
4347         qp_count += pf->lan_nb_qps;
4348         vsi_count += 1;
4349
4350         /* VF queue/VSI allocation */
4351         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4352         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4353                 pf->flags |= I40E_FLAG_SRIOV;
4354                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4355                 pf->vf_num = pci_dev->max_vfs;
4356                 PMD_DRV_LOG(DEBUG,
4357                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4358                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4359         } else {
4360                 pf->vf_nb_qps = 0;
4361                 pf->vf_num = 0;
4362         }
4363         qp_count += pf->vf_nb_qps * pf->vf_num;
4364         vsi_count += pf->vf_num;
4365
4366         /* VMDq queue/VSI allocation */
4367         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4368         pf->vmdq_nb_qps = 0;
4369         pf->max_nb_vmdq_vsi = 0;
4370         if (hw->func_caps.vmdq) {
4371                 if (qp_count < hw->func_caps.num_tx_qp &&
4372                         vsi_count < hw->func_caps.num_vsis) {
4373                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4374                                 qp_count) / pf->vmdq_nb_qp_max;
4375
4376                         /* Limit the maximum number of VMDq vsi to the maximum
4377                          * ethdev can support
4378                          */
4379                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4380                                 hw->func_caps.num_vsis - vsi_count);
4381                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4382                                 ETH_64_POOLS);
4383                         if (pf->max_nb_vmdq_vsi) {
4384                                 pf->flags |= I40E_FLAG_VMDQ;
4385                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4386                                 PMD_DRV_LOG(DEBUG,
4387                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4388                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4389                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4390                         } else {
4391                                 PMD_DRV_LOG(INFO,
4392                                         "No enough queues left for VMDq");
4393                         }
4394                 } else {
4395                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4396                 }
4397         }
4398         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4399         vsi_count += pf->max_nb_vmdq_vsi;
4400
4401         if (hw->func_caps.dcb)
4402                 pf->flags |= I40E_FLAG_DCB;
4403
4404         if (qp_count > hw->func_caps.num_tx_qp) {
4405                 PMD_DRV_LOG(ERR,
4406                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4407                         qp_count, hw->func_caps.num_tx_qp);
4408                 return -EINVAL;
4409         }
4410         if (vsi_count > hw->func_caps.num_vsis) {
4411                 PMD_DRV_LOG(ERR,
4412                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4413                         vsi_count, hw->func_caps.num_vsis);
4414                 return -EINVAL;
4415         }
4416
4417         return 0;
4418 }
4419
4420 static int
4421 i40e_pf_get_switch_config(struct i40e_pf *pf)
4422 {
4423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4424         struct i40e_aqc_get_switch_config_resp *switch_config;
4425         struct i40e_aqc_switch_config_element_resp *element;
4426         uint16_t start_seid = 0, num_reported;
4427         int ret;
4428
4429         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4430                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4431         if (!switch_config) {
4432                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4433                 return -ENOMEM;
4434         }
4435
4436         /* Get the switch configurations */
4437         ret = i40e_aq_get_switch_config(hw, switch_config,
4438                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4439         if (ret != I40E_SUCCESS) {
4440                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4441                 goto fail;
4442         }
4443         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4444         if (num_reported != 1) { /* The number should be 1 */
4445                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4446                 goto fail;
4447         }
4448
4449         /* Parse the switch configuration elements */
4450         element = &(switch_config->element[0]);
4451         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4452                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4453                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4454         } else
4455                 PMD_DRV_LOG(INFO, "Unknown element type");
4456
4457 fail:
4458         rte_free(switch_config);
4459
4460         return ret;
4461 }
4462
4463 static int
4464 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4465                         uint32_t num)
4466 {
4467         struct pool_entry *entry;
4468
4469         if (pool == NULL || num == 0)
4470                 return -EINVAL;
4471
4472         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4473         if (entry == NULL) {
4474                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4475                 return -ENOMEM;
4476         }
4477
4478         /* queue heap initialize */
4479         pool->num_free = num;
4480         pool->num_alloc = 0;
4481         pool->base = base;
4482         LIST_INIT(&pool->alloc_list);
4483         LIST_INIT(&pool->free_list);
4484
4485         /* Initialize element  */
4486         entry->base = 0;
4487         entry->len = num;
4488
4489         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4490         return 0;
4491 }
4492
4493 static void
4494 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4495 {
4496         struct pool_entry *entry, *next_entry;
4497
4498         if (pool == NULL)
4499                 return;
4500
4501         for (entry = LIST_FIRST(&pool->alloc_list);
4502                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4503                         entry = next_entry) {
4504                 LIST_REMOVE(entry, next);
4505                 rte_free(entry);
4506         }
4507
4508         for (entry = LIST_FIRST(&pool->free_list);
4509                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4510                         entry = next_entry) {
4511                 LIST_REMOVE(entry, next);
4512                 rte_free(entry);
4513         }
4514
4515         pool->num_free = 0;
4516         pool->num_alloc = 0;
4517         pool->base = 0;
4518         LIST_INIT(&pool->alloc_list);
4519         LIST_INIT(&pool->free_list);
4520 }
4521
4522 static int
4523 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4524                        uint32_t base)
4525 {
4526         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4527         uint32_t pool_offset;
4528         int insert;
4529
4530         if (pool == NULL) {
4531                 PMD_DRV_LOG(ERR, "Invalid parameter");
4532                 return -EINVAL;
4533         }
4534
4535         pool_offset = base - pool->base;
4536         /* Lookup in alloc list */
4537         LIST_FOREACH(entry, &pool->alloc_list, next) {
4538                 if (entry->base == pool_offset) {
4539                         valid_entry = entry;
4540                         LIST_REMOVE(entry, next);
4541                         break;
4542                 }
4543         }
4544
4545         /* Not find, return */
4546         if (valid_entry == NULL) {
4547                 PMD_DRV_LOG(ERR, "Failed to find entry");
4548                 return -EINVAL;
4549         }
4550
4551         /**
4552          * Found it, move it to free list  and try to merge.
4553          * In order to make merge easier, always sort it by qbase.
4554          * Find adjacent prev and last entries.
4555          */
4556         prev = next = NULL;
4557         LIST_FOREACH(entry, &pool->free_list, next) {
4558                 if (entry->base > valid_entry->base) {
4559                         next = entry;
4560                         break;
4561                 }
4562                 prev = entry;
4563         }
4564
4565         insert = 0;
4566         /* Try to merge with next one*/
4567         if (next != NULL) {
4568                 /* Merge with next one */
4569                 if (valid_entry->base + valid_entry->len == next->base) {
4570                         next->base = valid_entry->base;
4571                         next->len += valid_entry->len;
4572                         rte_free(valid_entry);
4573                         valid_entry = next;
4574                         insert = 1;
4575                 }
4576         }
4577
4578         if (prev != NULL) {
4579                 /* Merge with previous one */
4580                 if (prev->base + prev->len == valid_entry->base) {
4581                         prev->len += valid_entry->len;
4582                         /* If it merge with next one, remove next node */
4583                         if (insert == 1) {
4584                                 LIST_REMOVE(valid_entry, next);
4585                                 rte_free(valid_entry);
4586                         } else {
4587                                 rte_free(valid_entry);
4588                                 insert = 1;
4589                         }
4590                 }
4591         }
4592
4593         /* Not find any entry to merge, insert */
4594         if (insert == 0) {
4595                 if (prev != NULL)
4596                         LIST_INSERT_AFTER(prev, valid_entry, next);
4597                 else if (next != NULL)
4598                         LIST_INSERT_BEFORE(next, valid_entry, next);
4599                 else /* It's empty list, insert to head */
4600                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4601         }
4602
4603         pool->num_free += valid_entry->len;
4604         pool->num_alloc -= valid_entry->len;
4605
4606         return 0;
4607 }
4608
4609 static int
4610 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4611                        uint16_t num)
4612 {
4613         struct pool_entry *entry, *valid_entry;
4614
4615         if (pool == NULL || num == 0) {
4616                 PMD_DRV_LOG(ERR, "Invalid parameter");
4617                 return -EINVAL;
4618         }
4619
4620         if (pool->num_free < num) {
4621                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4622                             num, pool->num_free);
4623                 return -ENOMEM;
4624         }
4625
4626         valid_entry = NULL;
4627         /* Lookup  in free list and find most fit one */
4628         LIST_FOREACH(entry, &pool->free_list, next) {
4629                 if (entry->len >= num) {
4630                         /* Find best one */
4631                         if (entry->len == num) {
4632                                 valid_entry = entry;
4633                                 break;
4634                         }
4635                         if (valid_entry == NULL || valid_entry->len > entry->len)
4636                                 valid_entry = entry;
4637                 }
4638         }
4639
4640         /* Not find one to satisfy the request, return */
4641         if (valid_entry == NULL) {
4642                 PMD_DRV_LOG(ERR, "No valid entry found");
4643                 return -ENOMEM;
4644         }
4645         /**
4646          * The entry have equal queue number as requested,
4647          * remove it from alloc_list.
4648          */
4649         if (valid_entry->len == num) {
4650                 LIST_REMOVE(valid_entry, next);
4651         } else {
4652                 /**
4653                  * The entry have more numbers than requested,
4654                  * create a new entry for alloc_list and minus its
4655                  * queue base and number in free_list.
4656                  */
4657                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4658                 if (entry == NULL) {
4659                         PMD_DRV_LOG(ERR,
4660                                 "Failed to allocate memory for resource pool");
4661                         return -ENOMEM;
4662                 }
4663                 entry->base = valid_entry->base;
4664                 entry->len = num;
4665                 valid_entry->base += num;
4666                 valid_entry->len -= num;
4667                 valid_entry = entry;
4668         }
4669
4670         /* Insert it into alloc list, not sorted */
4671         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4672
4673         pool->num_free -= valid_entry->len;
4674         pool->num_alloc += valid_entry->len;
4675
4676         return valid_entry->base + pool->base;
4677 }
4678
4679 /**
4680  * bitmap_is_subset - Check whether src2 is subset of src1
4681  **/
4682 static inline int
4683 bitmap_is_subset(uint8_t src1, uint8_t src2)
4684 {
4685         return !((src1 ^ src2) & src2);
4686 }
4687
4688 static enum i40e_status_code
4689 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4690 {
4691         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4692
4693         /* If DCB is not supported, only default TC is supported */
4694         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4695                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4696                 return I40E_NOT_SUPPORTED;
4697         }
4698
4699         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4700                 PMD_DRV_LOG(ERR,
4701                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4702                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4703                 return I40E_NOT_SUPPORTED;
4704         }
4705         return I40E_SUCCESS;
4706 }
4707
4708 int
4709 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4710                                 struct i40e_vsi_vlan_pvid_info *info)
4711 {
4712         struct i40e_hw *hw;
4713         struct i40e_vsi_context ctxt;
4714         uint8_t vlan_flags = 0;
4715         int ret;
4716
4717         if (vsi == NULL || info == NULL) {
4718                 PMD_DRV_LOG(ERR, "invalid parameters");
4719                 return I40E_ERR_PARAM;
4720         }
4721
4722         if (info->on) {
4723                 vsi->info.pvid = info->config.pvid;
4724                 /**
4725                  * If insert pvid is enabled, only tagged pkts are
4726                  * allowed to be sent out.
4727                  */
4728                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4729                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4730         } else {
4731                 vsi->info.pvid = 0;
4732                 if (info->config.reject.tagged == 0)
4733                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4734
4735                 if (info->config.reject.untagged == 0)
4736                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4737         }
4738         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4739                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4740         vsi->info.port_vlan_flags |= vlan_flags;
4741         vsi->info.valid_sections =
4742                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4743         memset(&ctxt, 0, sizeof(ctxt));
4744         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4745         ctxt.seid = vsi->seid;
4746
4747         hw = I40E_VSI_TO_HW(vsi);
4748         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4749         if (ret != I40E_SUCCESS)
4750                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4751
4752         return ret;
4753 }
4754
4755 static int
4756 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4757 {
4758         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4759         int i, ret;
4760         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4761
4762         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4763         if (ret != I40E_SUCCESS)
4764                 return ret;
4765
4766         if (!vsi->seid) {
4767                 PMD_DRV_LOG(ERR, "seid not valid");
4768                 return -EINVAL;
4769         }
4770
4771         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4772         tc_bw_data.tc_valid_bits = enabled_tcmap;
4773         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4774                 tc_bw_data.tc_bw_credits[i] =
4775                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4776
4777         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4778         if (ret != I40E_SUCCESS) {
4779                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4780                 return ret;
4781         }
4782
4783         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4784                                         sizeof(vsi->info.qs_handle));
4785         return I40E_SUCCESS;
4786 }
4787
4788 static enum i40e_status_code
4789 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4790                                  struct i40e_aqc_vsi_properties_data *info,
4791                                  uint8_t enabled_tcmap)
4792 {
4793         enum i40e_status_code ret;
4794         int i, total_tc = 0;
4795         uint16_t qpnum_per_tc, bsf, qp_idx;
4796
4797         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4798         if (ret != I40E_SUCCESS)
4799                 return ret;
4800
4801         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4802                 if (enabled_tcmap & (1 << i))
4803                         total_tc++;
4804         if (total_tc == 0)
4805                 total_tc = 1;
4806         vsi->enabled_tc = enabled_tcmap;
4807
4808         /* Number of queues per enabled TC */
4809         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4810         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4811         bsf = rte_bsf32(qpnum_per_tc);
4812
4813         /* Adjust the queue number to actual queues that can be applied */
4814         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4815                 vsi->nb_qps = qpnum_per_tc * total_tc;
4816
4817         /**
4818          * Configure TC and queue mapping parameters, for enabled TC,
4819          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4820          * default queue will serve it.
4821          */
4822         qp_idx = 0;
4823         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4824                 if (vsi->enabled_tc & (1 << i)) {
4825                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4826                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4827                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4828                         qp_idx += qpnum_per_tc;
4829                 } else
4830                         info->tc_mapping[i] = 0;
4831         }
4832
4833         /* Associate queue number with VSI */
4834         if (vsi->type == I40E_VSI_SRIOV) {
4835                 info->mapping_flags |=
4836                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4837                 for (i = 0; i < vsi->nb_qps; i++)
4838                         info->queue_mapping[i] =
4839                                 rte_cpu_to_le_16(vsi->base_queue + i);
4840         } else {
4841                 info->mapping_flags |=
4842                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4843                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4844         }
4845         info->valid_sections |=
4846                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4847
4848         return I40E_SUCCESS;
4849 }
4850
4851 static int
4852 i40e_veb_release(struct i40e_veb *veb)
4853 {
4854         struct i40e_vsi *vsi;
4855         struct i40e_hw *hw;
4856
4857         if (veb == NULL)
4858                 return -EINVAL;
4859
4860         if (!TAILQ_EMPTY(&veb->head)) {
4861                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4862                 return -EACCES;
4863         }
4864         /* associate_vsi field is NULL for floating VEB */
4865         if (veb->associate_vsi != NULL) {
4866                 vsi = veb->associate_vsi;
4867                 hw = I40E_VSI_TO_HW(vsi);
4868
4869                 vsi->uplink_seid = veb->uplink_seid;
4870                 vsi->veb = NULL;
4871         } else {
4872                 veb->associate_pf->main_vsi->floating_veb = NULL;
4873                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4874         }
4875
4876         i40e_aq_delete_element(hw, veb->seid, NULL);
4877         rte_free(veb);
4878         return I40E_SUCCESS;
4879 }
4880
4881 /* Setup a veb */
4882 static struct i40e_veb *
4883 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4884 {
4885         struct i40e_veb *veb;
4886         int ret;
4887         struct i40e_hw *hw;
4888
4889         if (pf == NULL) {
4890                 PMD_DRV_LOG(ERR,
4891                             "veb setup failed, associated PF shouldn't null");
4892                 return NULL;
4893         }
4894         hw = I40E_PF_TO_HW(pf);
4895
4896         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4897         if (!veb) {
4898                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4899                 goto fail;
4900         }
4901
4902         veb->associate_vsi = vsi;
4903         veb->associate_pf = pf;
4904         TAILQ_INIT(&veb->head);
4905         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4906
4907         /* create floating veb if vsi is NULL */
4908         if (vsi != NULL) {
4909                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4910                                       I40E_DEFAULT_TCMAP, false,
4911                                       &veb->seid, false, NULL);
4912         } else {
4913                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4914                                       true, &veb->seid, false, NULL);
4915         }
4916
4917         if (ret != I40E_SUCCESS) {
4918                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4919                             hw->aq.asq_last_status);
4920                 goto fail;
4921         }
4922         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4923
4924         /* get statistics index */
4925         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4926                                 &veb->stats_idx, NULL, NULL, NULL);
4927         if (ret != I40E_SUCCESS) {
4928                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4929                             hw->aq.asq_last_status);
4930                 goto fail;
4931         }
4932         /* Get VEB bandwidth, to be implemented */
4933         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4934         if (vsi)
4935                 vsi->uplink_seid = veb->seid;
4936
4937         return veb;
4938 fail:
4939         rte_free(veb);
4940         return NULL;
4941 }
4942
4943 int
4944 i40e_vsi_release(struct i40e_vsi *vsi)
4945 {
4946         struct i40e_pf *pf;
4947         struct i40e_hw *hw;
4948         struct i40e_vsi_list *vsi_list;
4949         void *temp;
4950         int ret;
4951         struct i40e_mac_filter *f;
4952         uint16_t user_param;
4953
4954         if (!vsi)
4955                 return I40E_SUCCESS;
4956
4957         if (!vsi->adapter)
4958                 return -EFAULT;
4959
4960         user_param = vsi->user_param;
4961
4962         pf = I40E_VSI_TO_PF(vsi);
4963         hw = I40E_VSI_TO_HW(vsi);
4964
4965         /* VSI has child to attach, release child first */
4966         if (vsi->veb) {
4967                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4968                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4969                                 return -1;
4970                 }
4971                 i40e_veb_release(vsi->veb);
4972         }
4973
4974         if (vsi->floating_veb) {
4975                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4976                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4977                                 return -1;
4978                 }
4979         }
4980
4981         /* Remove all macvlan filters of the VSI */
4982         i40e_vsi_remove_all_macvlan_filter(vsi);
4983         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4984                 rte_free(f);
4985
4986         if (vsi->type != I40E_VSI_MAIN &&
4987             ((vsi->type != I40E_VSI_SRIOV) ||
4988             !pf->floating_veb_list[user_param])) {
4989                 /* Remove vsi from parent's sibling list */
4990                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4991                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4992                         return I40E_ERR_PARAM;
4993                 }
4994                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4995                                 &vsi->sib_vsi_list, list);
4996
4997                 /* Remove all switch element of the VSI */
4998                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4999                 if (ret != I40E_SUCCESS)
5000                         PMD_DRV_LOG(ERR, "Failed to delete element");
5001         }
5002
5003         if ((vsi->type == I40E_VSI_SRIOV) &&
5004             pf->floating_veb_list[user_param]) {
5005                 /* Remove vsi from parent's sibling list */
5006                 if (vsi->parent_vsi == NULL ||
5007                     vsi->parent_vsi->floating_veb == NULL) {
5008                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5009                         return I40E_ERR_PARAM;
5010                 }
5011                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5012                              &vsi->sib_vsi_list, list);
5013
5014                 /* Remove all switch element of the VSI */
5015                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5016                 if (ret != I40E_SUCCESS)
5017                         PMD_DRV_LOG(ERR, "Failed to delete element");
5018         }
5019
5020         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5021
5022         if (vsi->type != I40E_VSI_SRIOV)
5023                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5024         rte_free(vsi);
5025
5026         return I40E_SUCCESS;
5027 }
5028
5029 static int
5030 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5031 {
5032         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5033         struct i40e_aqc_remove_macvlan_element_data def_filter;
5034         struct i40e_mac_filter_info filter;
5035         int ret;
5036
5037         if (vsi->type != I40E_VSI_MAIN)
5038                 return I40E_ERR_CONFIG;
5039         memset(&def_filter, 0, sizeof(def_filter));
5040         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5041                                         ETH_ADDR_LEN);
5042         def_filter.vlan_tag = 0;
5043         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5044                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5045         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5046         if (ret != I40E_SUCCESS) {
5047                 struct i40e_mac_filter *f;
5048                 struct ether_addr *mac;
5049
5050                 PMD_DRV_LOG(DEBUG,
5051                             "Cannot remove the default macvlan filter");
5052                 /* It needs to add the permanent mac into mac list */
5053                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5054                 if (f == NULL) {
5055                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5056                         return I40E_ERR_NO_MEMORY;
5057                 }
5058                 mac = &f->mac_info.mac_addr;
5059                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5060                                 ETH_ADDR_LEN);
5061                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5062                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5063                 vsi->mac_num++;
5064
5065                 return ret;
5066         }
5067         rte_memcpy(&filter.mac_addr,
5068                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5069         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5070         return i40e_vsi_add_mac(vsi, &filter);
5071 }
5072
5073 /*
5074  * i40e_vsi_get_bw_config - Query VSI BW Information
5075  * @vsi: the VSI to be queried
5076  *
5077  * Returns 0 on success, negative value on failure
5078  */
5079 static enum i40e_status_code
5080 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5081 {
5082         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5083         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5084         struct i40e_hw *hw = &vsi->adapter->hw;
5085         i40e_status ret;
5086         int i;
5087         uint32_t bw_max;
5088
5089         memset(&bw_config, 0, sizeof(bw_config));
5090         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5091         if (ret != I40E_SUCCESS) {
5092                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5093                             hw->aq.asq_last_status);
5094                 return ret;
5095         }
5096
5097         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5098         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5099                                         &ets_sla_config, NULL);
5100         if (ret != I40E_SUCCESS) {
5101                 PMD_DRV_LOG(ERR,
5102                         "VSI failed to get TC bandwdith configuration %u",
5103                         hw->aq.asq_last_status);
5104                 return ret;
5105         }
5106
5107         /* store and print out BW info */
5108         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5109         vsi->bw_info.bw_max = bw_config.max_bw;
5110         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5111         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5112         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5113                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5114                      I40E_16_BIT_WIDTH);
5115         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5116                 vsi->bw_info.bw_ets_share_credits[i] =
5117                                 ets_sla_config.share_credits[i];
5118                 vsi->bw_info.bw_ets_credits[i] =
5119                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5120                 /* 4 bits per TC, 4th bit is reserved */
5121                 vsi->bw_info.bw_ets_max[i] =
5122                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5123                                   RTE_LEN2MASK(3, uint8_t));
5124                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5125                             vsi->bw_info.bw_ets_share_credits[i]);
5126                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5127                             vsi->bw_info.bw_ets_credits[i]);
5128                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5129                             vsi->bw_info.bw_ets_max[i]);
5130         }
5131
5132         return I40E_SUCCESS;
5133 }
5134
5135 /* i40e_enable_pf_lb
5136  * @pf: pointer to the pf structure
5137  *
5138  * allow loopback on pf
5139  */
5140 static inline void
5141 i40e_enable_pf_lb(struct i40e_pf *pf)
5142 {
5143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5144         struct i40e_vsi_context ctxt;
5145         int ret;
5146
5147         /* Use the FW API if FW >= v5.0 */
5148         if (hw->aq.fw_maj_ver < 5) {
5149                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5150                 return;
5151         }
5152
5153         memset(&ctxt, 0, sizeof(ctxt));
5154         ctxt.seid = pf->main_vsi_seid;
5155         ctxt.pf_num = hw->pf_id;
5156         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5157         if (ret) {
5158                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5159                             ret, hw->aq.asq_last_status);
5160                 return;
5161         }
5162         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5163         ctxt.info.valid_sections =
5164                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5165         ctxt.info.switch_id |=
5166                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5167
5168         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5169         if (ret)
5170                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5171                             hw->aq.asq_last_status);
5172 }
5173
5174 /* Setup a VSI */
5175 struct i40e_vsi *
5176 i40e_vsi_setup(struct i40e_pf *pf,
5177                enum i40e_vsi_type type,
5178                struct i40e_vsi *uplink_vsi,
5179                uint16_t user_param)
5180 {
5181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5182         struct i40e_vsi *vsi;
5183         struct i40e_mac_filter_info filter;
5184         int ret;
5185         struct i40e_vsi_context ctxt;
5186         struct ether_addr broadcast =
5187                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5188
5189         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5190             uplink_vsi == NULL) {
5191                 PMD_DRV_LOG(ERR,
5192                         "VSI setup failed, VSI link shouldn't be NULL");
5193                 return NULL;
5194         }
5195
5196         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5197                 PMD_DRV_LOG(ERR,
5198                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5199                 return NULL;
5200         }
5201
5202         /* two situations
5203          * 1.type is not MAIN and uplink vsi is not NULL
5204          * If uplink vsi didn't setup VEB, create one first under veb field
5205          * 2.type is SRIOV and the uplink is NULL
5206          * If floating VEB is NULL, create one veb under floating veb field
5207          */
5208
5209         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5210             uplink_vsi->veb == NULL) {
5211                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5212
5213                 if (uplink_vsi->veb == NULL) {
5214                         PMD_DRV_LOG(ERR, "VEB setup failed");
5215                         return NULL;
5216                 }
5217                 /* set ALLOWLOOPBACk on pf, when veb is created */
5218                 i40e_enable_pf_lb(pf);
5219         }
5220
5221         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5222             pf->main_vsi->floating_veb == NULL) {
5223                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5224
5225                 if (pf->main_vsi->floating_veb == NULL) {
5226                         PMD_DRV_LOG(ERR, "VEB setup failed");
5227                         return NULL;
5228                 }
5229         }
5230
5231         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5232         if (!vsi) {
5233                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5234                 return NULL;
5235         }
5236         TAILQ_INIT(&vsi->mac_list);
5237         vsi->type = type;
5238         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5239         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5240         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5241         vsi->user_param = user_param;
5242         vsi->vlan_anti_spoof_on = 0;
5243         vsi->vlan_filter_on = 0;
5244         /* Allocate queues */
5245         switch (vsi->type) {
5246         case I40E_VSI_MAIN  :
5247                 vsi->nb_qps = pf->lan_nb_qps;
5248                 break;
5249         case I40E_VSI_SRIOV :
5250                 vsi->nb_qps = pf->vf_nb_qps;
5251                 break;
5252         case I40E_VSI_VMDQ2:
5253                 vsi->nb_qps = pf->vmdq_nb_qps;
5254                 break;
5255         case I40E_VSI_FDIR:
5256                 vsi->nb_qps = pf->fdir_nb_qps;
5257                 break;
5258         default:
5259                 goto fail_mem;
5260         }
5261         /*
5262          * The filter status descriptor is reported in rx queue 0,
5263          * while the tx queue for fdir filter programming has no
5264          * such constraints, can be non-zero queues.
5265          * To simplify it, choose FDIR vsi use queue 0 pair.
5266          * To make sure it will use queue 0 pair, queue allocation
5267          * need be done before this function is called
5268          */
5269         if (type != I40E_VSI_FDIR) {
5270                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5271                         if (ret < 0) {
5272                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5273                                                 vsi->seid, ret);
5274                                 goto fail_mem;
5275                         }
5276                         vsi->base_queue = ret;
5277         } else
5278                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5279
5280         /* VF has MSIX interrupt in VF range, don't allocate here */
5281         if (type == I40E_VSI_MAIN) {
5282                 if (pf->support_multi_driver) {
5283                         /* If support multi-driver, need to use INT0 instead of
5284                          * allocating from msix pool. The Msix pool is init from
5285                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5286                          * to 1 without calling i40e_res_pool_alloc.
5287                          */
5288                         vsi->msix_intr = 0;
5289                         vsi->nb_msix = 1;
5290                 } else {
5291                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5292                                                   RTE_MIN(vsi->nb_qps,
5293                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5294                         if (ret < 0) {
5295                                 PMD_DRV_LOG(ERR,
5296                                             "VSI MAIN %d get heap failed %d",
5297                                             vsi->seid, ret);
5298                                 goto fail_queue_alloc;
5299                         }
5300                         vsi->msix_intr = ret;
5301                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5302                                                RTE_MAX_RXTX_INTR_VEC_ID);
5303                 }
5304         } else if (type != I40E_VSI_SRIOV) {
5305                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5306                 if (ret < 0) {
5307                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5308                         goto fail_queue_alloc;
5309                 }
5310                 vsi->msix_intr = ret;
5311                 vsi->nb_msix = 1;
5312         } else {
5313                 vsi->msix_intr = 0;
5314                 vsi->nb_msix = 0;
5315         }
5316
5317         /* Add VSI */
5318         if (type == I40E_VSI_MAIN) {
5319                 /* For main VSI, no need to add since it's default one */
5320                 vsi->uplink_seid = pf->mac_seid;
5321                 vsi->seid = pf->main_vsi_seid;
5322                 /* Bind queues with specific MSIX interrupt */
5323                 /**
5324                  * Needs 2 interrupt at least, one for misc cause which will
5325                  * enabled from OS side, Another for queues binding the
5326                  * interrupt from device side only.
5327                  */
5328
5329                 /* Get default VSI parameters from hardware */
5330                 memset(&ctxt, 0, sizeof(ctxt));
5331                 ctxt.seid = vsi->seid;
5332                 ctxt.pf_num = hw->pf_id;
5333                 ctxt.uplink_seid = vsi->uplink_seid;
5334                 ctxt.vf_num = 0;
5335                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5336                 if (ret != I40E_SUCCESS) {
5337                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5338                         goto fail_msix_alloc;
5339                 }
5340                 rte_memcpy(&vsi->info, &ctxt.info,
5341                         sizeof(struct i40e_aqc_vsi_properties_data));
5342                 vsi->vsi_id = ctxt.vsi_number;
5343                 vsi->info.valid_sections = 0;
5344
5345                 /* Configure tc, enabled TC0 only */
5346                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5347                         I40E_SUCCESS) {
5348                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5349                         goto fail_msix_alloc;
5350                 }
5351
5352                 /* TC, queue mapping */
5353                 memset(&ctxt, 0, sizeof(ctxt));
5354                 vsi->info.valid_sections |=
5355                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5356                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5357                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5358                 rte_memcpy(&ctxt.info, &vsi->info,
5359                         sizeof(struct i40e_aqc_vsi_properties_data));
5360                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5361                                                 I40E_DEFAULT_TCMAP);
5362                 if (ret != I40E_SUCCESS) {
5363                         PMD_DRV_LOG(ERR,
5364                                 "Failed to configure TC queue mapping");
5365                         goto fail_msix_alloc;
5366                 }
5367                 ctxt.seid = vsi->seid;
5368                 ctxt.pf_num = hw->pf_id;
5369                 ctxt.uplink_seid = vsi->uplink_seid;
5370                 ctxt.vf_num = 0;
5371
5372                 /* Update VSI parameters */
5373                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5374                 if (ret != I40E_SUCCESS) {
5375                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5376                         goto fail_msix_alloc;
5377                 }
5378
5379                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5380                                                 sizeof(vsi->info.tc_mapping));
5381                 rte_memcpy(&vsi->info.queue_mapping,
5382                                 &ctxt.info.queue_mapping,
5383                         sizeof(vsi->info.queue_mapping));
5384                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5385                 vsi->info.valid_sections = 0;
5386
5387                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5388                                 ETH_ADDR_LEN);
5389
5390                 /**
5391                  * Updating default filter settings are necessary to prevent
5392                  * reception of tagged packets.
5393                  * Some old firmware configurations load a default macvlan
5394                  * filter which accepts both tagged and untagged packets.
5395                  * The updating is to use a normal filter instead if needed.
5396                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5397                  * The firmware with correct configurations load the default
5398                  * macvlan filter which is expected and cannot be removed.
5399                  */
5400                 i40e_update_default_filter_setting(vsi);
5401                 i40e_config_qinq(hw, vsi);
5402         } else if (type == I40E_VSI_SRIOV) {
5403                 memset(&ctxt, 0, sizeof(ctxt));
5404                 /**
5405                  * For other VSI, the uplink_seid equals to uplink VSI's
5406                  * uplink_seid since they share same VEB
5407                  */
5408                 if (uplink_vsi == NULL)
5409                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5410                 else
5411                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5412                 ctxt.pf_num = hw->pf_id;
5413                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5414                 ctxt.uplink_seid = vsi->uplink_seid;
5415                 ctxt.connection_type = 0x1;
5416                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5417
5418                 /* Use the VEB configuration if FW >= v5.0 */
5419                 if (hw->aq.fw_maj_ver >= 5) {
5420                         /* Configure switch ID */
5421                         ctxt.info.valid_sections |=
5422                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5423                         ctxt.info.switch_id =
5424                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5425                 }
5426
5427                 /* Configure port/vlan */
5428                 ctxt.info.valid_sections |=
5429                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5430                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5431                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5432                                                 hw->func_caps.enabled_tcmap);
5433                 if (ret != I40E_SUCCESS) {
5434                         PMD_DRV_LOG(ERR,
5435                                 "Failed to configure TC queue mapping");
5436                         goto fail_msix_alloc;
5437                 }
5438
5439                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5440                 ctxt.info.valid_sections |=
5441                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5442                 /**
5443                  * Since VSI is not created yet, only configure parameter,
5444                  * will add vsi below.
5445                  */
5446
5447                 i40e_config_qinq(hw, vsi);
5448         } else if (type == I40E_VSI_VMDQ2) {
5449                 memset(&ctxt, 0, sizeof(ctxt));
5450                 /*
5451                  * For other VSI, the uplink_seid equals to uplink VSI's
5452                  * uplink_seid since they share same VEB
5453                  */
5454                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5455                 ctxt.pf_num = hw->pf_id;
5456                 ctxt.vf_num = 0;
5457                 ctxt.uplink_seid = vsi->uplink_seid;
5458                 ctxt.connection_type = 0x1;
5459                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5460
5461                 ctxt.info.valid_sections |=
5462                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5463                 /* user_param carries flag to enable loop back */
5464                 if (user_param) {
5465                         ctxt.info.switch_id =
5466                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5467                         ctxt.info.switch_id |=
5468                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5469                 }
5470
5471                 /* Configure port/vlan */
5472                 ctxt.info.valid_sections |=
5473                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5474                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5475                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5476                                                 I40E_DEFAULT_TCMAP);
5477                 if (ret != I40E_SUCCESS) {
5478                         PMD_DRV_LOG(ERR,
5479                                 "Failed to configure TC queue mapping");
5480                         goto fail_msix_alloc;
5481                 }
5482                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5483                 ctxt.info.valid_sections |=
5484                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5485         } else if (type == I40E_VSI_FDIR) {
5486                 memset(&ctxt, 0, sizeof(ctxt));
5487                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5488                 ctxt.pf_num = hw->pf_id;
5489                 ctxt.vf_num = 0;
5490                 ctxt.uplink_seid = vsi->uplink_seid;
5491                 ctxt.connection_type = 0x1;     /* regular data port */
5492                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5493                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5494                                                 I40E_DEFAULT_TCMAP);
5495                 if (ret != I40E_SUCCESS) {
5496                         PMD_DRV_LOG(ERR,
5497                                 "Failed to configure TC queue mapping.");
5498                         goto fail_msix_alloc;
5499                 }
5500                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5501                 ctxt.info.valid_sections |=
5502                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5503         } else {
5504                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5505                 goto fail_msix_alloc;
5506         }
5507
5508         if (vsi->type != I40E_VSI_MAIN) {
5509                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5510                 if (ret != I40E_SUCCESS) {
5511                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5512                                     hw->aq.asq_last_status);
5513                         goto fail_msix_alloc;
5514                 }
5515                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5516                 vsi->info.valid_sections = 0;
5517                 vsi->seid = ctxt.seid;
5518                 vsi->vsi_id = ctxt.vsi_number;
5519                 vsi->sib_vsi_list.vsi = vsi;
5520                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5521                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5522                                           &vsi->sib_vsi_list, list);
5523                 } else {
5524                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5525                                           &vsi->sib_vsi_list, list);
5526                 }
5527         }
5528
5529         /* MAC/VLAN configuration */
5530         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5531         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5532
5533         ret = i40e_vsi_add_mac(vsi, &filter);
5534         if (ret != I40E_SUCCESS) {
5535                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5536                 goto fail_msix_alloc;
5537         }
5538
5539         /* Get VSI BW information */
5540         i40e_vsi_get_bw_config(vsi);
5541         return vsi;
5542 fail_msix_alloc:
5543         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5544 fail_queue_alloc:
5545         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5546 fail_mem:
5547         rte_free(vsi);
5548         return NULL;
5549 }
5550
5551 /* Configure vlan filter on or off */
5552 int
5553 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5554 {
5555         int i, num;
5556         struct i40e_mac_filter *f;
5557         void *temp;
5558         struct i40e_mac_filter_info *mac_filter;
5559         enum rte_mac_filter_type desired_filter;
5560         int ret = I40E_SUCCESS;
5561
5562         if (on) {
5563                 /* Filter to match MAC and VLAN */
5564                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5565         } else {
5566                 /* Filter to match only MAC */
5567                 desired_filter = RTE_MAC_PERFECT_MATCH;
5568         }
5569
5570         num = vsi->mac_num;
5571
5572         mac_filter = rte_zmalloc("mac_filter_info_data",
5573                                  num * sizeof(*mac_filter), 0);
5574         if (mac_filter == NULL) {
5575                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5576                 return I40E_ERR_NO_MEMORY;
5577         }
5578
5579         i = 0;
5580
5581         /* Remove all existing mac */
5582         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5583                 mac_filter[i] = f->mac_info;
5584                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5585                 if (ret) {
5586                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5587                                     on ? "enable" : "disable");
5588                         goto DONE;
5589                 }
5590                 i++;
5591         }
5592
5593         /* Override with new filter */
5594         for (i = 0; i < num; i++) {
5595                 mac_filter[i].filter_type = desired_filter;
5596                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5597                 if (ret) {
5598                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5599                                     on ? "enable" : "disable");
5600                         goto DONE;
5601                 }
5602         }
5603
5604 DONE:
5605         rte_free(mac_filter);
5606         return ret;
5607 }
5608
5609 /* Configure vlan stripping on or off */
5610 int
5611 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5612 {
5613         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5614         struct i40e_vsi_context ctxt;
5615         uint8_t vlan_flags;
5616         int ret = I40E_SUCCESS;
5617
5618         /* Check if it has been already on or off */
5619         if (vsi->info.valid_sections &
5620                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5621                 if (on) {
5622                         if ((vsi->info.port_vlan_flags &
5623                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5624                                 return 0; /* already on */
5625                 } else {
5626                         if ((vsi->info.port_vlan_flags &
5627                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5628                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5629                                 return 0; /* already off */
5630                 }
5631         }
5632
5633         if (on)
5634                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5635         else
5636                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5637         vsi->info.valid_sections =
5638                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5639         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5640         vsi->info.port_vlan_flags |= vlan_flags;
5641         ctxt.seid = vsi->seid;
5642         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5643         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5644         if (ret)
5645                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5646                             on ? "enable" : "disable");
5647
5648         return ret;
5649 }
5650
5651 static int
5652 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5653 {
5654         struct rte_eth_dev_data *data = dev->data;
5655         int ret;
5656         int mask = 0;
5657
5658         /* Apply vlan offload setting */
5659         mask = ETH_VLAN_STRIP_MASK |
5660                ETH_VLAN_FILTER_MASK |
5661                ETH_VLAN_EXTEND_MASK;
5662         ret = i40e_vlan_offload_set(dev, mask);
5663         if (ret) {
5664                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5665                 return ret;
5666         }
5667
5668         /* Apply pvid setting */
5669         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5670                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5671         if (ret)
5672                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5673
5674         return ret;
5675 }
5676
5677 static int
5678 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5679 {
5680         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5681
5682         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5683 }
5684
5685 static int
5686 i40e_update_flow_control(struct i40e_hw *hw)
5687 {
5688 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5689         struct i40e_link_status link_status;
5690         uint32_t rxfc = 0, txfc = 0, reg;
5691         uint8_t an_info;
5692         int ret;
5693
5694         memset(&link_status, 0, sizeof(link_status));
5695         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5696         if (ret != I40E_SUCCESS) {
5697                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5698                 goto write_reg; /* Disable flow control */
5699         }
5700
5701         an_info = hw->phy.link_info.an_info;
5702         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5703                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5704                 ret = I40E_ERR_NOT_READY;
5705                 goto write_reg; /* Disable flow control */
5706         }
5707         /**
5708          * If link auto negotiation is enabled, flow control needs to
5709          * be configured according to it
5710          */
5711         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5712         case I40E_LINK_PAUSE_RXTX:
5713                 rxfc = 1;
5714                 txfc = 1;
5715                 hw->fc.current_mode = I40E_FC_FULL;
5716                 break;
5717         case I40E_AQ_LINK_PAUSE_RX:
5718                 rxfc = 1;
5719                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5720                 break;
5721         case I40E_AQ_LINK_PAUSE_TX:
5722                 txfc = 1;
5723                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5724                 break;
5725         default:
5726                 hw->fc.current_mode = I40E_FC_NONE;
5727                 break;
5728         }
5729
5730 write_reg:
5731         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5732                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5733         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5734         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5735         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5736         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5737
5738         return ret;
5739 }
5740
5741 /* PF setup */
5742 static int
5743 i40e_pf_setup(struct i40e_pf *pf)
5744 {
5745         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5746         struct i40e_filter_control_settings settings;
5747         struct i40e_vsi *vsi;
5748         int ret;
5749
5750         /* Clear all stats counters */
5751         pf->offset_loaded = FALSE;
5752         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5753         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5754         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5755         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5756
5757         ret = i40e_pf_get_switch_config(pf);
5758         if (ret != I40E_SUCCESS) {
5759                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5760                 return ret;
5761         }
5762         if (pf->flags & I40E_FLAG_FDIR) {
5763                 /* make queue allocated first, let FDIR use queue pair 0*/
5764                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5765                 if (ret != I40E_FDIR_QUEUE_ID) {
5766                         PMD_DRV_LOG(ERR,
5767                                 "queue allocation fails for FDIR: ret =%d",
5768                                 ret);
5769                         pf->flags &= ~I40E_FLAG_FDIR;
5770                 }
5771         }
5772         /*  main VSI setup */
5773         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5774         if (!vsi) {
5775                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5776                 return I40E_ERR_NOT_READY;
5777         }
5778         pf->main_vsi = vsi;
5779
5780         /* Configure filter control */
5781         memset(&settings, 0, sizeof(settings));
5782         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5783                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5784         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5785                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5786         else {
5787                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5788                         hw->func_caps.rss_table_size);
5789                 return I40E_ERR_PARAM;
5790         }
5791         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5792                 hw->func_caps.rss_table_size);
5793         pf->hash_lut_size = hw->func_caps.rss_table_size;
5794
5795         /* Enable ethtype and macvlan filters */
5796         settings.enable_ethtype = TRUE;
5797         settings.enable_macvlan = TRUE;
5798         ret = i40e_set_filter_control(hw, &settings);
5799         if (ret)
5800                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5801                                                                 ret);
5802
5803         /* Update flow control according to the auto negotiation */
5804         i40e_update_flow_control(hw);
5805
5806         return I40E_SUCCESS;
5807 }
5808
5809 int
5810 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5811 {
5812         uint32_t reg;
5813         uint16_t j;
5814
5815         /**
5816          * Set or clear TX Queue Disable flags,
5817          * which is required by hardware.
5818          */
5819         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5820         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5821
5822         /* Wait until the request is finished */
5823         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5824                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5825                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5826                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5827                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5828                                                         & 0x1))) {
5829                         break;
5830                 }
5831         }
5832         if (on) {
5833                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5834                         return I40E_SUCCESS; /* already on, skip next steps */
5835
5836                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5837                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5838         } else {
5839                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5840                         return I40E_SUCCESS; /* already off, skip next steps */
5841                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5842         }
5843         /* Write the register */
5844         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5845         /* Check the result */
5846         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5847                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5848                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5849                 if (on) {
5850                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5851                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5852                                 break;
5853                 } else {
5854                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5855                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5856                                 break;
5857                 }
5858         }
5859         /* Check if it is timeout */
5860         if (j >= I40E_CHK_Q_ENA_COUNT) {
5861                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5862                             (on ? "enable" : "disable"), q_idx);
5863                 return I40E_ERR_TIMEOUT;
5864         }
5865
5866         return I40E_SUCCESS;
5867 }
5868
5869 /* Swith on or off the tx queues */
5870 static int
5871 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5872 {
5873         struct rte_eth_dev_data *dev_data = pf->dev_data;
5874         struct i40e_tx_queue *txq;
5875         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5876         uint16_t i;
5877         int ret;
5878
5879         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5880                 txq = dev_data->tx_queues[i];
5881                 /* Don't operate the queue if not configured or
5882                  * if starting only per queue */
5883                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5884                         continue;
5885                 if (on)
5886                         ret = i40e_dev_tx_queue_start(dev, i);
5887                 else
5888                         ret = i40e_dev_tx_queue_stop(dev, i);
5889                 if ( ret != I40E_SUCCESS)
5890                         return ret;
5891         }
5892
5893         return I40E_SUCCESS;
5894 }
5895
5896 int
5897 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5898 {
5899         uint32_t reg;
5900         uint16_t j;
5901
5902         /* Wait until the request is finished */
5903         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5904                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5905                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5906                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5907                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5908                         break;
5909         }
5910
5911         if (on) {
5912                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5913                         return I40E_SUCCESS; /* Already on, skip next steps */
5914                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5915         } else {
5916                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5917                         return I40E_SUCCESS; /* Already off, skip next steps */
5918                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5919         }
5920
5921         /* Write the register */
5922         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5923         /* Check the result */
5924         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5925                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5926                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5927                 if (on) {
5928                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5929                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5930                                 break;
5931                 } else {
5932                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5933                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5934                                 break;
5935                 }
5936         }
5937
5938         /* Check if it is timeout */
5939         if (j >= I40E_CHK_Q_ENA_COUNT) {
5940                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5941                             (on ? "enable" : "disable"), q_idx);
5942                 return I40E_ERR_TIMEOUT;
5943         }
5944
5945         return I40E_SUCCESS;
5946 }
5947 /* Switch on or off the rx queues */
5948 static int
5949 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5950 {
5951         struct rte_eth_dev_data *dev_data = pf->dev_data;
5952         struct i40e_rx_queue *rxq;
5953         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5954         uint16_t i;
5955         int ret;
5956
5957         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5958                 rxq = dev_data->rx_queues[i];
5959                 /* Don't operate the queue if not configured or
5960                  * if starting only per queue */
5961                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5962                         continue;
5963                 if (on)
5964                         ret = i40e_dev_rx_queue_start(dev, i);
5965                 else
5966                         ret = i40e_dev_rx_queue_stop(dev, i);
5967                 if (ret != I40E_SUCCESS)
5968                         return ret;
5969         }
5970
5971         return I40E_SUCCESS;
5972 }
5973
5974 /* Switch on or off all the rx/tx queues */
5975 int
5976 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5977 {
5978         int ret;
5979
5980         if (on) {
5981                 /* enable rx queues before enabling tx queues */
5982                 ret = i40e_dev_switch_rx_queues(pf, on);
5983                 if (ret) {
5984                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5985                         return ret;
5986                 }
5987                 ret = i40e_dev_switch_tx_queues(pf, on);
5988         } else {
5989                 /* Stop tx queues before stopping rx queues */
5990                 ret = i40e_dev_switch_tx_queues(pf, on);
5991                 if (ret) {
5992                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5993                         return ret;
5994                 }
5995                 ret = i40e_dev_switch_rx_queues(pf, on);
5996         }
5997
5998         return ret;
5999 }
6000
6001 /* Initialize VSI for TX */
6002 static int
6003 i40e_dev_tx_init(struct i40e_pf *pf)
6004 {
6005         struct rte_eth_dev_data *data = pf->dev_data;
6006         uint16_t i;
6007         uint32_t ret = I40E_SUCCESS;
6008         struct i40e_tx_queue *txq;
6009
6010         for (i = 0; i < data->nb_tx_queues; i++) {
6011                 txq = data->tx_queues[i];
6012                 if (!txq || !txq->q_set)
6013                         continue;
6014                 ret = i40e_tx_queue_init(txq);
6015                 if (ret != I40E_SUCCESS)
6016                         break;
6017         }
6018         if (ret == I40E_SUCCESS)
6019                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6020                                      ->eth_dev);
6021
6022         return ret;
6023 }
6024
6025 /* Initialize VSI for RX */
6026 static int
6027 i40e_dev_rx_init(struct i40e_pf *pf)
6028 {
6029         struct rte_eth_dev_data *data = pf->dev_data;
6030         int ret = I40E_SUCCESS;
6031         uint16_t i;
6032         struct i40e_rx_queue *rxq;
6033
6034         i40e_pf_config_mq_rx(pf);
6035         for (i = 0; i < data->nb_rx_queues; i++) {
6036                 rxq = data->rx_queues[i];
6037                 if (!rxq || !rxq->q_set)
6038                         continue;
6039
6040                 ret = i40e_rx_queue_init(rxq);
6041                 if (ret != I40E_SUCCESS) {
6042                         PMD_DRV_LOG(ERR,
6043                                 "Failed to do RX queue initialization");
6044                         break;
6045                 }
6046         }
6047         if (ret == I40E_SUCCESS)
6048                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6049                                      ->eth_dev);
6050
6051         return ret;
6052 }
6053
6054 static int
6055 i40e_dev_rxtx_init(struct i40e_pf *pf)
6056 {
6057         int err;
6058
6059         err = i40e_dev_tx_init(pf);
6060         if (err) {
6061                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6062                 return err;
6063         }
6064         err = i40e_dev_rx_init(pf);
6065         if (err) {
6066                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6067                 return err;
6068         }
6069
6070         return err;
6071 }
6072
6073 static int
6074 i40e_vmdq_setup(struct rte_eth_dev *dev)
6075 {
6076         struct rte_eth_conf *conf = &dev->data->dev_conf;
6077         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6078         int i, err, conf_vsis, j, loop;
6079         struct i40e_vsi *vsi;
6080         struct i40e_vmdq_info *vmdq_info;
6081         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6082         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6083
6084         /*
6085          * Disable interrupt to avoid message from VF. Furthermore, it will
6086          * avoid race condition in VSI creation/destroy.
6087          */
6088         i40e_pf_disable_irq0(hw);
6089
6090         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6091                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6092                 return -ENOTSUP;
6093         }
6094
6095         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6096         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6097                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6098                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6099                         pf->max_nb_vmdq_vsi);
6100                 return -ENOTSUP;
6101         }
6102
6103         if (pf->vmdq != NULL) {
6104                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6105                 return 0;
6106         }
6107
6108         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6109                                 sizeof(*vmdq_info) * conf_vsis, 0);
6110
6111         if (pf->vmdq == NULL) {
6112                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6113                 return -ENOMEM;
6114         }
6115
6116         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6117
6118         /* Create VMDQ VSI */
6119         for (i = 0; i < conf_vsis; i++) {
6120                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6121                                 vmdq_conf->enable_loop_back);
6122                 if (vsi == NULL) {
6123                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6124                         err = -1;
6125                         goto err_vsi_setup;
6126                 }
6127                 vmdq_info = &pf->vmdq[i];
6128                 vmdq_info->pf = pf;
6129                 vmdq_info->vsi = vsi;
6130         }
6131         pf->nb_cfg_vmdq_vsi = conf_vsis;
6132
6133         /* Configure Vlan */
6134         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6135         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6136                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6137                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6138                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6139                                         vmdq_conf->pool_map[i].vlan_id, j);
6140
6141                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6142                                                 vmdq_conf->pool_map[i].vlan_id);
6143                                 if (err) {
6144                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6145                                         err = -1;
6146                                         goto err_vsi_setup;
6147                                 }
6148                         }
6149                 }
6150         }
6151
6152         i40e_pf_enable_irq0(hw);
6153
6154         return 0;
6155
6156 err_vsi_setup:
6157         for (i = 0; i < conf_vsis; i++)
6158                 if (pf->vmdq[i].vsi == NULL)
6159                         break;
6160                 else
6161                         i40e_vsi_release(pf->vmdq[i].vsi);
6162
6163         rte_free(pf->vmdq);
6164         pf->vmdq = NULL;
6165         i40e_pf_enable_irq0(hw);
6166         return err;
6167 }
6168
6169 static void
6170 i40e_stat_update_32(struct i40e_hw *hw,
6171                    uint32_t reg,
6172                    bool offset_loaded,
6173                    uint64_t *offset,
6174                    uint64_t *stat)
6175 {
6176         uint64_t new_data;
6177
6178         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6179         if (!offset_loaded)
6180                 *offset = new_data;
6181
6182         if (new_data >= *offset)
6183                 *stat = (uint64_t)(new_data - *offset);
6184         else
6185                 *stat = (uint64_t)((new_data +
6186                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6187 }
6188
6189 static void
6190 i40e_stat_update_48(struct i40e_hw *hw,
6191                    uint32_t hireg,
6192                    uint32_t loreg,
6193                    bool offset_loaded,
6194                    uint64_t *offset,
6195                    uint64_t *stat)
6196 {
6197         uint64_t new_data;
6198
6199         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6200         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6201                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6202
6203         if (!offset_loaded)
6204                 *offset = new_data;
6205
6206         if (new_data >= *offset)
6207                 *stat = new_data - *offset;
6208         else
6209                 *stat = (uint64_t)((new_data +
6210                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6211
6212         *stat &= I40E_48_BIT_MASK;
6213 }
6214
6215 /* Disable IRQ0 */
6216 void
6217 i40e_pf_disable_irq0(struct i40e_hw *hw)
6218 {
6219         /* Disable all interrupt types */
6220         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6221                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6222         I40E_WRITE_FLUSH(hw);
6223 }
6224
6225 /* Enable IRQ0 */
6226 void
6227 i40e_pf_enable_irq0(struct i40e_hw *hw)
6228 {
6229         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6230                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6231                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6232                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6233         I40E_WRITE_FLUSH(hw);
6234 }
6235
6236 static void
6237 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6238 {
6239         /* read pending request and disable first */
6240         i40e_pf_disable_irq0(hw);
6241         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6242         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6243                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6244
6245         if (no_queue)
6246                 /* Link no queues with irq0 */
6247                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6248                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6249 }
6250
6251 static void
6252 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6253 {
6254         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6255         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6256         int i;
6257         uint16_t abs_vf_id;
6258         uint32_t index, offset, val;
6259
6260         if (!pf->vfs)
6261                 return;
6262         /**
6263          * Try to find which VF trigger a reset, use absolute VF id to access
6264          * since the reg is global register.
6265          */
6266         for (i = 0; i < pf->vf_num; i++) {
6267                 abs_vf_id = hw->func_caps.vf_base_id + i;
6268                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6269                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6270                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6271                 /* VFR event occurred */
6272                 if (val & (0x1 << offset)) {
6273                         int ret;
6274
6275                         /* Clear the event first */
6276                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6277                                                         (0x1 << offset));
6278                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6279                         /**
6280                          * Only notify a VF reset event occurred,
6281                          * don't trigger another SW reset
6282                          */
6283                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6284                         if (ret != I40E_SUCCESS)
6285                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6286                 }
6287         }
6288 }
6289
6290 static void
6291 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6292 {
6293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6294         int i;
6295
6296         for (i = 0; i < pf->vf_num; i++)
6297                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6298 }
6299
6300 static void
6301 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6302 {
6303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6304         struct i40e_arq_event_info info;
6305         uint16_t pending, opcode;
6306         int ret;
6307
6308         info.buf_len = I40E_AQ_BUF_SZ;
6309         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6310         if (!info.msg_buf) {
6311                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6312                 return;
6313         }
6314
6315         pending = 1;
6316         while (pending) {
6317                 ret = i40e_clean_arq_element(hw, &info, &pending);
6318
6319                 if (ret != I40E_SUCCESS) {
6320                         PMD_DRV_LOG(INFO,
6321                                 "Failed to read msg from AdminQ, aq_err: %u",
6322                                 hw->aq.asq_last_status);
6323                         break;
6324                 }
6325                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6326
6327                 switch (opcode) {
6328                 case i40e_aqc_opc_send_msg_to_pf:
6329                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6330                         i40e_pf_host_handle_vf_msg(dev,
6331                                         rte_le_to_cpu_16(info.desc.retval),
6332                                         rte_le_to_cpu_32(info.desc.cookie_high),
6333                                         rte_le_to_cpu_32(info.desc.cookie_low),
6334                                         info.msg_buf,
6335                                         info.msg_len);
6336                         break;
6337                 case i40e_aqc_opc_get_link_status:
6338                         ret = i40e_dev_link_update(dev, 0);
6339                         if (!ret)
6340                                 _rte_eth_dev_callback_process(dev,
6341                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6342                         break;
6343                 default:
6344                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6345                                     opcode);
6346                         break;
6347                 }
6348         }
6349         rte_free(info.msg_buf);
6350 }
6351
6352 /**
6353  * Interrupt handler triggered by NIC  for handling
6354  * specific interrupt.
6355  *
6356  * @param handle
6357  *  Pointer to interrupt handle.
6358  * @param param
6359  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6360  *
6361  * @return
6362  *  void
6363  */
6364 static void
6365 i40e_dev_interrupt_handler(void *param)
6366 {
6367         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6369         uint32_t icr0;
6370
6371         /* Disable interrupt */
6372         i40e_pf_disable_irq0(hw);
6373
6374         /* read out interrupt causes */
6375         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6376
6377         /* No interrupt event indicated */
6378         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6379                 PMD_DRV_LOG(INFO, "No interrupt event");
6380                 goto done;
6381         }
6382         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6383                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6384         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6385                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6386         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6387                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6388         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6389                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6390         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6391                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6392         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6393                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6394         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6395                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6396
6397         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6398                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6399                 i40e_dev_handle_vfr_event(dev);
6400         }
6401         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6402                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6403                 i40e_dev_handle_aq_msg(dev);
6404         }
6405
6406 done:
6407         /* Enable interrupt */
6408         i40e_pf_enable_irq0(hw);
6409         rte_intr_enable(dev->intr_handle);
6410 }
6411
6412 int
6413 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6414                          struct i40e_macvlan_filter *filter,
6415                          int total)
6416 {
6417         int ele_num, ele_buff_size;
6418         int num, actual_num, i;
6419         uint16_t flags;
6420         int ret = I40E_SUCCESS;
6421         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6422         struct i40e_aqc_add_macvlan_element_data *req_list;
6423
6424         if (filter == NULL  || total == 0)
6425                 return I40E_ERR_PARAM;
6426         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6427         ele_buff_size = hw->aq.asq_buf_size;
6428
6429         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6430         if (req_list == NULL) {
6431                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6432                 return I40E_ERR_NO_MEMORY;
6433         }
6434
6435         num = 0;
6436         do {
6437                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6438                 memset(req_list, 0, ele_buff_size);
6439
6440                 for (i = 0; i < actual_num; i++) {
6441                         rte_memcpy(req_list[i].mac_addr,
6442                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6443                         req_list[i].vlan_tag =
6444                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6445
6446                         switch (filter[num + i].filter_type) {
6447                         case RTE_MAC_PERFECT_MATCH:
6448                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6449                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6450                                 break;
6451                         case RTE_MACVLAN_PERFECT_MATCH:
6452                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6453                                 break;
6454                         case RTE_MAC_HASH_MATCH:
6455                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6456                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6457                                 break;
6458                         case RTE_MACVLAN_HASH_MATCH:
6459                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6460                                 break;
6461                         default:
6462                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6463                                 ret = I40E_ERR_PARAM;
6464                                 goto DONE;
6465                         }
6466
6467                         req_list[i].queue_number = 0;
6468
6469                         req_list[i].flags = rte_cpu_to_le_16(flags);
6470                 }
6471
6472                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6473                                                 actual_num, NULL);
6474                 if (ret != I40E_SUCCESS) {
6475                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6476                         goto DONE;
6477                 }
6478                 num += actual_num;
6479         } while (num < total);
6480
6481 DONE:
6482         rte_free(req_list);
6483         return ret;
6484 }
6485
6486 int
6487 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6488                             struct i40e_macvlan_filter *filter,
6489                             int total)
6490 {
6491         int ele_num, ele_buff_size;
6492         int num, actual_num, i;
6493         uint16_t flags;
6494         int ret = I40E_SUCCESS;
6495         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6496         struct i40e_aqc_remove_macvlan_element_data *req_list;
6497
6498         if (filter == NULL  || total == 0)
6499                 return I40E_ERR_PARAM;
6500
6501         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6502         ele_buff_size = hw->aq.asq_buf_size;
6503
6504         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6505         if (req_list == NULL) {
6506                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6507                 return I40E_ERR_NO_MEMORY;
6508         }
6509
6510         num = 0;
6511         do {
6512                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6513                 memset(req_list, 0, ele_buff_size);
6514
6515                 for (i = 0; i < actual_num; i++) {
6516                         rte_memcpy(req_list[i].mac_addr,
6517                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6518                         req_list[i].vlan_tag =
6519                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6520
6521                         switch (filter[num + i].filter_type) {
6522                         case RTE_MAC_PERFECT_MATCH:
6523                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6524                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6525                                 break;
6526                         case RTE_MACVLAN_PERFECT_MATCH:
6527                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6528                                 break;
6529                         case RTE_MAC_HASH_MATCH:
6530                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6531                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6532                                 break;
6533                         case RTE_MACVLAN_HASH_MATCH:
6534                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6535                                 break;
6536                         default:
6537                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6538                                 ret = I40E_ERR_PARAM;
6539                                 goto DONE;
6540                         }
6541                         req_list[i].flags = rte_cpu_to_le_16(flags);
6542                 }
6543
6544                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6545                                                 actual_num, NULL);
6546                 if (ret != I40E_SUCCESS) {
6547                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6548                         goto DONE;
6549                 }
6550                 num += actual_num;
6551         } while (num < total);
6552
6553 DONE:
6554         rte_free(req_list);
6555         return ret;
6556 }
6557
6558 /* Find out specific MAC filter */
6559 static struct i40e_mac_filter *
6560 i40e_find_mac_filter(struct i40e_vsi *vsi,
6561                          struct ether_addr *macaddr)
6562 {
6563         struct i40e_mac_filter *f;
6564
6565         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6566                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6567                         return f;
6568         }
6569
6570         return NULL;
6571 }
6572
6573 static bool
6574 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6575                          uint16_t vlan_id)
6576 {
6577         uint32_t vid_idx, vid_bit;
6578
6579         if (vlan_id > ETH_VLAN_ID_MAX)
6580                 return 0;
6581
6582         vid_idx = I40E_VFTA_IDX(vlan_id);
6583         vid_bit = I40E_VFTA_BIT(vlan_id);
6584
6585         if (vsi->vfta[vid_idx] & vid_bit)
6586                 return 1;
6587         else
6588                 return 0;
6589 }
6590
6591 static void
6592 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6593                        uint16_t vlan_id, bool on)
6594 {
6595         uint32_t vid_idx, vid_bit;
6596
6597         vid_idx = I40E_VFTA_IDX(vlan_id);
6598         vid_bit = I40E_VFTA_BIT(vlan_id);
6599
6600         if (on)
6601                 vsi->vfta[vid_idx] |= vid_bit;
6602         else
6603                 vsi->vfta[vid_idx] &= ~vid_bit;
6604 }
6605
6606 void
6607 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6608                      uint16_t vlan_id, bool on)
6609 {
6610         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6611         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6612         int ret;
6613
6614         if (vlan_id > ETH_VLAN_ID_MAX)
6615                 return;
6616
6617         i40e_store_vlan_filter(vsi, vlan_id, on);
6618
6619         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6620                 return;
6621
6622         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6623
6624         if (on) {
6625                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6626                                        &vlan_data, 1, NULL);
6627                 if (ret != I40E_SUCCESS)
6628                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6629         } else {
6630                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6631                                           &vlan_data, 1, NULL);
6632                 if (ret != I40E_SUCCESS)
6633                         PMD_DRV_LOG(ERR,
6634                                     "Failed to remove vlan filter");
6635         }
6636 }
6637
6638 /**
6639  * Find all vlan options for specific mac addr,
6640  * return with actual vlan found.
6641  */
6642 int
6643 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6644                            struct i40e_macvlan_filter *mv_f,
6645                            int num, struct ether_addr *addr)
6646 {
6647         int i;
6648         uint32_t j, k;
6649
6650         /**
6651          * Not to use i40e_find_vlan_filter to decrease the loop time,
6652          * although the code looks complex.
6653           */
6654         if (num < vsi->vlan_num)
6655                 return I40E_ERR_PARAM;
6656
6657         i = 0;
6658         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6659                 if (vsi->vfta[j]) {
6660                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6661                                 if (vsi->vfta[j] & (1 << k)) {
6662                                         if (i > num - 1) {
6663                                                 PMD_DRV_LOG(ERR,
6664                                                         "vlan number doesn't match");
6665                                                 return I40E_ERR_PARAM;
6666                                         }
6667                                         rte_memcpy(&mv_f[i].macaddr,
6668                                                         addr, ETH_ADDR_LEN);
6669                                         mv_f[i].vlan_id =
6670                                                 j * I40E_UINT32_BIT_SIZE + k;
6671                                         i++;
6672                                 }
6673                         }
6674                 }
6675         }
6676         return I40E_SUCCESS;
6677 }
6678
6679 static inline int
6680 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6681                            struct i40e_macvlan_filter *mv_f,
6682                            int num,
6683                            uint16_t vlan)
6684 {
6685         int i = 0;
6686         struct i40e_mac_filter *f;
6687
6688         if (num < vsi->mac_num)
6689                 return I40E_ERR_PARAM;
6690
6691         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6692                 if (i > num - 1) {
6693                         PMD_DRV_LOG(ERR, "buffer number not match");
6694                         return I40E_ERR_PARAM;
6695                 }
6696                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6697                                 ETH_ADDR_LEN);
6698                 mv_f[i].vlan_id = vlan;
6699                 mv_f[i].filter_type = f->mac_info.filter_type;
6700                 i++;
6701         }
6702
6703         return I40E_SUCCESS;
6704 }
6705
6706 static int
6707 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6708 {
6709         int i, j, num;
6710         struct i40e_mac_filter *f;
6711         struct i40e_macvlan_filter *mv_f;
6712         int ret = I40E_SUCCESS;
6713
6714         if (vsi == NULL || vsi->mac_num == 0)
6715                 return I40E_ERR_PARAM;
6716
6717         /* Case that no vlan is set */
6718         if (vsi->vlan_num == 0)
6719                 num = vsi->mac_num;
6720         else
6721                 num = vsi->mac_num * vsi->vlan_num;
6722
6723         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6724         if (mv_f == NULL) {
6725                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6726                 return I40E_ERR_NO_MEMORY;
6727         }
6728
6729         i = 0;
6730         if (vsi->vlan_num == 0) {
6731                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6732                         rte_memcpy(&mv_f[i].macaddr,
6733                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6734                         mv_f[i].filter_type = f->mac_info.filter_type;
6735                         mv_f[i].vlan_id = 0;
6736                         i++;
6737                 }
6738         } else {
6739                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6740                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6741                                         vsi->vlan_num, &f->mac_info.mac_addr);
6742                         if (ret != I40E_SUCCESS)
6743                                 goto DONE;
6744                         for (j = i; j < i + vsi->vlan_num; j++)
6745                                 mv_f[j].filter_type = f->mac_info.filter_type;
6746                         i += vsi->vlan_num;
6747                 }
6748         }
6749
6750         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6751 DONE:
6752         rte_free(mv_f);
6753
6754         return ret;
6755 }
6756
6757 int
6758 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6759 {
6760         struct i40e_macvlan_filter *mv_f;
6761         int mac_num;
6762         int ret = I40E_SUCCESS;
6763
6764         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6765                 return I40E_ERR_PARAM;
6766
6767         /* If it's already set, just return */
6768         if (i40e_find_vlan_filter(vsi,vlan))
6769                 return I40E_SUCCESS;
6770
6771         mac_num = vsi->mac_num;
6772
6773         if (mac_num == 0) {
6774                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6775                 return I40E_ERR_PARAM;
6776         }
6777
6778         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6779
6780         if (mv_f == NULL) {
6781                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6782                 return I40E_ERR_NO_MEMORY;
6783         }
6784
6785         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6786
6787         if (ret != I40E_SUCCESS)
6788                 goto DONE;
6789
6790         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6791
6792         if (ret != I40E_SUCCESS)
6793                 goto DONE;
6794
6795         i40e_set_vlan_filter(vsi, vlan, 1);
6796
6797         vsi->vlan_num++;
6798         ret = I40E_SUCCESS;
6799 DONE:
6800         rte_free(mv_f);
6801         return ret;
6802 }
6803
6804 int
6805 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6806 {
6807         struct i40e_macvlan_filter *mv_f;
6808         int mac_num;
6809         int ret = I40E_SUCCESS;
6810
6811         /**
6812          * Vlan 0 is the generic filter for untagged packets
6813          * and can't be removed.
6814          */
6815         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6816                 return I40E_ERR_PARAM;
6817
6818         /* If can't find it, just return */
6819         if (!i40e_find_vlan_filter(vsi, vlan))
6820                 return I40E_ERR_PARAM;
6821
6822         mac_num = vsi->mac_num;
6823
6824         if (mac_num == 0) {
6825                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6826                 return I40E_ERR_PARAM;
6827         }
6828
6829         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6830
6831         if (mv_f == NULL) {
6832                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6833                 return I40E_ERR_NO_MEMORY;
6834         }
6835
6836         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6837
6838         if (ret != I40E_SUCCESS)
6839                 goto DONE;
6840
6841         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6842
6843         if (ret != I40E_SUCCESS)
6844                 goto DONE;
6845
6846         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6847         if (vsi->vlan_num == 1) {
6848                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6849                 if (ret != I40E_SUCCESS)
6850                         goto DONE;
6851
6852                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6853                 if (ret != I40E_SUCCESS)
6854                         goto DONE;
6855         }
6856
6857         i40e_set_vlan_filter(vsi, vlan, 0);
6858
6859         vsi->vlan_num--;
6860         ret = I40E_SUCCESS;
6861 DONE:
6862         rte_free(mv_f);
6863         return ret;
6864 }
6865
6866 int
6867 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6868 {
6869         struct i40e_mac_filter *f;
6870         struct i40e_macvlan_filter *mv_f;
6871         int i, vlan_num = 0;
6872         int ret = I40E_SUCCESS;
6873
6874         /* If it's add and we've config it, return */
6875         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6876         if (f != NULL)
6877                 return I40E_SUCCESS;
6878         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6879                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6880
6881                 /**
6882                  * If vlan_num is 0, that's the first time to add mac,
6883                  * set mask for vlan_id 0.
6884                  */
6885                 if (vsi->vlan_num == 0) {
6886                         i40e_set_vlan_filter(vsi, 0, 1);
6887                         vsi->vlan_num = 1;
6888                 }
6889                 vlan_num = vsi->vlan_num;
6890         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6891                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6892                 vlan_num = 1;
6893
6894         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6895         if (mv_f == NULL) {
6896                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6897                 return I40E_ERR_NO_MEMORY;
6898         }
6899
6900         for (i = 0; i < vlan_num; i++) {
6901                 mv_f[i].filter_type = mac_filter->filter_type;
6902                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6903                                 ETH_ADDR_LEN);
6904         }
6905
6906         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6907                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6908                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6909                                         &mac_filter->mac_addr);
6910                 if (ret != I40E_SUCCESS)
6911                         goto DONE;
6912         }
6913
6914         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6915         if (ret != I40E_SUCCESS)
6916                 goto DONE;
6917
6918         /* Add the mac addr into mac list */
6919         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6920         if (f == NULL) {
6921                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6922                 ret = I40E_ERR_NO_MEMORY;
6923                 goto DONE;
6924         }
6925         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6926                         ETH_ADDR_LEN);
6927         f->mac_info.filter_type = mac_filter->filter_type;
6928         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6929         vsi->mac_num++;
6930
6931         ret = I40E_SUCCESS;
6932 DONE:
6933         rte_free(mv_f);
6934
6935         return ret;
6936 }
6937
6938 int
6939 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6940 {
6941         struct i40e_mac_filter *f;
6942         struct i40e_macvlan_filter *mv_f;
6943         int i, vlan_num;
6944         enum rte_mac_filter_type filter_type;
6945         int ret = I40E_SUCCESS;
6946
6947         /* Can't find it, return an error */
6948         f = i40e_find_mac_filter(vsi, addr);
6949         if (f == NULL)
6950                 return I40E_ERR_PARAM;
6951
6952         vlan_num = vsi->vlan_num;
6953         filter_type = f->mac_info.filter_type;
6954         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6955                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6956                 if (vlan_num == 0) {
6957                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6958                         return I40E_ERR_PARAM;
6959                 }
6960         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6961                         filter_type == RTE_MAC_HASH_MATCH)
6962                 vlan_num = 1;
6963
6964         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6965         if (mv_f == NULL) {
6966                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6967                 return I40E_ERR_NO_MEMORY;
6968         }
6969
6970         for (i = 0; i < vlan_num; i++) {
6971                 mv_f[i].filter_type = filter_type;
6972                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6973                                 ETH_ADDR_LEN);
6974         }
6975         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6976                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6977                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6978                 if (ret != I40E_SUCCESS)
6979                         goto DONE;
6980         }
6981
6982         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6983         if (ret != I40E_SUCCESS)
6984                 goto DONE;
6985
6986         /* Remove the mac addr into mac list */
6987         TAILQ_REMOVE(&vsi->mac_list, f, next);
6988         rte_free(f);
6989         vsi->mac_num--;
6990
6991         ret = I40E_SUCCESS;
6992 DONE:
6993         rte_free(mv_f);
6994         return ret;
6995 }
6996
6997 /* Configure hash enable flags for RSS */
6998 uint64_t
6999 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7000 {
7001         uint64_t hena = 0;
7002         int i;
7003
7004         if (!flags)
7005                 return hena;
7006
7007         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7008                 if (flags & (1ULL << i))
7009                         hena |= adapter->pctypes_tbl[i];
7010         }
7011
7012         return hena;
7013 }
7014
7015 /* Parse the hash enable flags */
7016 uint64_t
7017 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7018 {
7019         uint64_t rss_hf = 0;
7020
7021         if (!flags)
7022                 return rss_hf;
7023         int i;
7024
7025         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7026                 if (flags & adapter->pctypes_tbl[i])
7027                         rss_hf |= (1ULL << i);
7028         }
7029         return rss_hf;
7030 }
7031
7032 /* Disable RSS */
7033 static void
7034 i40e_pf_disable_rss(struct i40e_pf *pf)
7035 {
7036         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7037
7038         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7039         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7040         I40E_WRITE_FLUSH(hw);
7041 }
7042
7043 int
7044 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7045 {
7046         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7047         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7048         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7049                            I40E_VFQF_HKEY_MAX_INDEX :
7050                            I40E_PFQF_HKEY_MAX_INDEX;
7051         int ret = 0;
7052
7053         if (!key || key_len == 0) {
7054                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7055                 return 0;
7056         } else if (key_len != (key_idx + 1) *
7057                 sizeof(uint32_t)) {
7058                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7059                 return -EINVAL;
7060         }
7061
7062         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7063                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7064                         (struct i40e_aqc_get_set_rss_key_data *)key;
7065
7066                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7067                 if (ret)
7068                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7069         } else {
7070                 uint32_t *hash_key = (uint32_t *)key;
7071                 uint16_t i;
7072
7073                 if (vsi->type == I40E_VSI_SRIOV) {
7074                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7075                                 I40E_WRITE_REG(
7076                                         hw,
7077                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7078                                         hash_key[i]);
7079
7080                 } else {
7081                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7082                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7083                                                hash_key[i]);
7084                 }
7085                 I40E_WRITE_FLUSH(hw);
7086         }
7087
7088         return ret;
7089 }
7090
7091 static int
7092 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7093 {
7094         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7095         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7096         uint32_t reg;
7097         int ret;
7098
7099         if (!key || !key_len)
7100                 return -EINVAL;
7101
7102         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7103                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7104                         (struct i40e_aqc_get_set_rss_key_data *)key);
7105                 if (ret) {
7106                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7107                         return ret;
7108                 }
7109         } else {
7110                 uint32_t *key_dw = (uint32_t *)key;
7111                 uint16_t i;
7112
7113                 if (vsi->type == I40E_VSI_SRIOV) {
7114                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7115                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7116                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7117                         }
7118                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7119                                    sizeof(uint32_t);
7120                 } else {
7121                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7122                                 reg = I40E_PFQF_HKEY(i);
7123                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7124                         }
7125                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7126                                    sizeof(uint32_t);
7127                 }
7128         }
7129         return 0;
7130 }
7131
7132 static int
7133 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7134 {
7135         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7136         uint64_t hena;
7137         int ret;
7138
7139         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7140                                rss_conf->rss_key_len);
7141         if (ret)
7142                 return ret;
7143
7144         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7145         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7146         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7147         I40E_WRITE_FLUSH(hw);
7148
7149         return 0;
7150 }
7151
7152 static int
7153 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7154                          struct rte_eth_rss_conf *rss_conf)
7155 {
7156         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7158         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7159         uint64_t hena;
7160
7161         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7162         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7163
7164         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7165                 if (rss_hf != 0) /* Enable RSS */
7166                         return -EINVAL;
7167                 return 0; /* Nothing to do */
7168         }
7169         /* RSS enabled */
7170         if (rss_hf == 0) /* Disable RSS */
7171                 return -EINVAL;
7172
7173         return i40e_hw_rss_hash_set(pf, rss_conf);
7174 }
7175
7176 static int
7177 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7178                            struct rte_eth_rss_conf *rss_conf)
7179 {
7180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7182         uint64_t hena;
7183
7184         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7185                          &rss_conf->rss_key_len);
7186
7187         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7188         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7189         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7190
7191         return 0;
7192 }
7193
7194 static int
7195 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7196 {
7197         switch (filter_type) {
7198         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7199                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7200                 break;
7201         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7202                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7203                 break;
7204         case RTE_TUNNEL_FILTER_IMAC_TENID:
7205                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7206                 break;
7207         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7208                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7209                 break;
7210         case ETH_TUNNEL_FILTER_IMAC:
7211                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7212                 break;
7213         case ETH_TUNNEL_FILTER_OIP:
7214                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7215                 break;
7216         case ETH_TUNNEL_FILTER_IIP:
7217                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7218                 break;
7219         default:
7220                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7221                 return -EINVAL;
7222         }
7223
7224         return 0;
7225 }
7226
7227 /* Convert tunnel filter structure */
7228 static int
7229 i40e_tunnel_filter_convert(
7230         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7231         struct i40e_tunnel_filter *tunnel_filter)
7232 {
7233         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7234                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7235         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7236                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7237         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7238         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7239              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7240             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7241                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7242         else
7243                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7244         tunnel_filter->input.flags = cld_filter->element.flags;
7245         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7246         tunnel_filter->queue = cld_filter->element.queue_number;
7247         rte_memcpy(tunnel_filter->input.general_fields,
7248                    cld_filter->general_fields,
7249                    sizeof(cld_filter->general_fields));
7250
7251         return 0;
7252 }
7253
7254 /* Check if there exists the tunnel filter */
7255 struct i40e_tunnel_filter *
7256 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7257                              const struct i40e_tunnel_filter_input *input)
7258 {
7259         int ret;
7260
7261         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7262         if (ret < 0)
7263                 return NULL;
7264
7265         return tunnel_rule->hash_map[ret];
7266 }
7267
7268 /* Add a tunnel filter into the SW list */
7269 static int
7270 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7271                              struct i40e_tunnel_filter *tunnel_filter)
7272 {
7273         struct i40e_tunnel_rule *rule = &pf->tunnel;
7274         int ret;
7275
7276         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7277         if (ret < 0) {
7278                 PMD_DRV_LOG(ERR,
7279                             "Failed to insert tunnel filter to hash table %d!",
7280                             ret);
7281                 return ret;
7282         }
7283         rule->hash_map[ret] = tunnel_filter;
7284
7285         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7286
7287         return 0;
7288 }
7289
7290 /* Delete a tunnel filter from the SW list */
7291 int
7292 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7293                           struct i40e_tunnel_filter_input *input)
7294 {
7295         struct i40e_tunnel_rule *rule = &pf->tunnel;
7296         struct i40e_tunnel_filter *tunnel_filter;
7297         int ret;
7298
7299         ret = rte_hash_del_key(rule->hash_table, input);
7300         if (ret < 0) {
7301                 PMD_DRV_LOG(ERR,
7302                             "Failed to delete tunnel filter to hash table %d!",
7303                             ret);
7304                 return ret;
7305         }
7306         tunnel_filter = rule->hash_map[ret];
7307         rule->hash_map[ret] = NULL;
7308
7309         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7310         rte_free(tunnel_filter);
7311
7312         return 0;
7313 }
7314
7315 int
7316 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7317                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7318                         uint8_t add)
7319 {
7320         uint16_t ip_type;
7321         uint32_t ipv4_addr, ipv4_addr_le;
7322         uint8_t i, tun_type = 0;
7323         /* internal varialbe to convert ipv6 byte order */
7324         uint32_t convert_ipv6[4];
7325         int val, ret = 0;
7326         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7327         struct i40e_vsi *vsi = pf->main_vsi;
7328         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7329         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7330         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7331         struct i40e_tunnel_filter *tunnel, *node;
7332         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7333
7334         cld_filter = rte_zmalloc("tunnel_filter",
7335                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7336         0);
7337
7338         if (NULL == cld_filter) {
7339                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7340                 return -ENOMEM;
7341         }
7342         pfilter = cld_filter;
7343
7344         ether_addr_copy(&tunnel_filter->outer_mac,
7345                         (struct ether_addr *)&pfilter->element.outer_mac);
7346         ether_addr_copy(&tunnel_filter->inner_mac,
7347                         (struct ether_addr *)&pfilter->element.inner_mac);
7348
7349         pfilter->element.inner_vlan =
7350                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7351         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7352                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7353                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7354                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7355                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7356                                 &ipv4_addr_le,
7357                                 sizeof(pfilter->element.ipaddr.v4.data));
7358         } else {
7359                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7360                 for (i = 0; i < 4; i++) {
7361                         convert_ipv6[i] =
7362                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7363                 }
7364                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7365                            &convert_ipv6,
7366                            sizeof(pfilter->element.ipaddr.v6.data));
7367         }
7368
7369         /* check tunneled type */
7370         switch (tunnel_filter->tunnel_type) {
7371         case RTE_TUNNEL_TYPE_VXLAN:
7372                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7373                 break;
7374         case RTE_TUNNEL_TYPE_NVGRE:
7375                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7376                 break;
7377         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7378                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7379                 break;
7380         default:
7381                 /* Other tunnel types is not supported. */
7382                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7383                 rte_free(cld_filter);
7384                 return -EINVAL;
7385         }
7386
7387         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7388                                        &pfilter->element.flags);
7389         if (val < 0) {
7390                 rte_free(cld_filter);
7391                 return -EINVAL;
7392         }
7393
7394         pfilter->element.flags |= rte_cpu_to_le_16(
7395                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7396                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7397         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7398         pfilter->element.queue_number =
7399                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7400
7401         /* Check if there is the filter in SW list */
7402         memset(&check_filter, 0, sizeof(check_filter));
7403         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7404         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7405         if (add && node) {
7406                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7407                 rte_free(cld_filter);
7408                 return -EINVAL;
7409         }
7410
7411         if (!add && !node) {
7412                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7413                 rte_free(cld_filter);
7414                 return -EINVAL;
7415         }
7416
7417         if (add) {
7418                 ret = i40e_aq_add_cloud_filters(hw,
7419                                         vsi->seid, &cld_filter->element, 1);
7420                 if (ret < 0) {
7421                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7422                         rte_free(cld_filter);
7423                         return -ENOTSUP;
7424                 }
7425                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7426                 if (tunnel == NULL) {
7427                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7428                         rte_free(cld_filter);
7429                         return -ENOMEM;
7430                 }
7431
7432                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7433                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7434                 if (ret < 0)
7435                         rte_free(tunnel);
7436         } else {
7437                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7438                                                    &cld_filter->element, 1);
7439                 if (ret < 0) {
7440                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7441                         rte_free(cld_filter);
7442                         return -ENOTSUP;
7443                 }
7444                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7445         }
7446
7447         rte_free(cld_filter);
7448         return ret;
7449 }
7450
7451 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7452 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7453 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7454 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7455 #define I40E_TR_GRE_KEY_MASK                    0x400
7456 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7457 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7458
7459 static enum
7460 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7461 {
7462         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7463         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7464         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7465         enum i40e_status_code status = I40E_SUCCESS;
7466
7467         if (pf->support_multi_driver) {
7468                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7469                 return I40E_NOT_SUPPORTED;
7470         }
7471
7472         memset(&filter_replace, 0,
7473                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7474         memset(&filter_replace_buf, 0,
7475                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7476
7477         /* create L1 filter */
7478         filter_replace.old_filter_type =
7479                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7480         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7481         filter_replace.tr_bit = 0;
7482
7483         /* Prepare the buffer, 3 entries */
7484         filter_replace_buf.data[0] =
7485                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7486         filter_replace_buf.data[0] |=
7487                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7488         filter_replace_buf.data[2] = 0xFF;
7489         filter_replace_buf.data[3] = 0xFF;
7490         filter_replace_buf.data[4] =
7491                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7492         filter_replace_buf.data[4] |=
7493                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7494         filter_replace_buf.data[7] = 0xF0;
7495         filter_replace_buf.data[8]
7496                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7497         filter_replace_buf.data[8] |=
7498                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7499         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7500                 I40E_TR_GENEVE_KEY_MASK |
7501                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7502         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7503                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7504                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7505
7506         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7507                                                &filter_replace_buf);
7508         if (!status) {
7509                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7510                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7511                             "cloud l1 type is changed from 0x%x to 0x%x",
7512                             filter_replace.old_filter_type,
7513                             filter_replace.new_filter_type);
7514         }
7515         return status;
7516 }
7517
7518 static enum
7519 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7520 {
7521         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7522         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7523         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7524         enum i40e_status_code status = I40E_SUCCESS;
7525
7526         if (pf->support_multi_driver) {
7527                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7528                 return I40E_NOT_SUPPORTED;
7529         }
7530
7531         /* For MPLSoUDP */
7532         memset(&filter_replace, 0,
7533                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7534         memset(&filter_replace_buf, 0,
7535                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7536         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7537                 I40E_AQC_MIRROR_CLOUD_FILTER;
7538         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7539         filter_replace.new_filter_type =
7540                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7541         /* Prepare the buffer, 2 entries */
7542         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7543         filter_replace_buf.data[0] |=
7544                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7545         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7546         filter_replace_buf.data[4] |=
7547                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7548         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7549                                                &filter_replace_buf);
7550         if (status < 0)
7551                 return status;
7552         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7553                     "cloud filter type is changed from 0x%x to 0x%x",
7554                     filter_replace.old_filter_type,
7555                     filter_replace.new_filter_type);
7556
7557         /* For MPLSoGRE */
7558         memset(&filter_replace, 0,
7559                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7560         memset(&filter_replace_buf, 0,
7561                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7562
7563         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7564                 I40E_AQC_MIRROR_CLOUD_FILTER;
7565         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7566         filter_replace.new_filter_type =
7567                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7568         /* Prepare the buffer, 2 entries */
7569         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7570         filter_replace_buf.data[0] |=
7571                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7572         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7573         filter_replace_buf.data[4] |=
7574                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7575
7576         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7577                                                &filter_replace_buf);
7578         if (!status) {
7579                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7580                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7581                             "cloud filter type is changed from 0x%x to 0x%x",
7582                             filter_replace.old_filter_type,
7583                             filter_replace.new_filter_type);
7584         }
7585         return status;
7586 }
7587
7588 static enum i40e_status_code
7589 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7590 {
7591         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7592         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7593         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7594         enum i40e_status_code status = I40E_SUCCESS;
7595
7596         if (pf->support_multi_driver) {
7597                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7598                 return I40E_NOT_SUPPORTED;
7599         }
7600
7601         /* For GTP-C */
7602         memset(&filter_replace, 0,
7603                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7604         memset(&filter_replace_buf, 0,
7605                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7606         /* create L1 filter */
7607         filter_replace.old_filter_type =
7608                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7609         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7610         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7611                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7612         /* Prepare the buffer, 2 entries */
7613         filter_replace_buf.data[0] =
7614                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7615         filter_replace_buf.data[0] |=
7616                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7617         filter_replace_buf.data[2] = 0xFF;
7618         filter_replace_buf.data[3] = 0xFF;
7619         filter_replace_buf.data[4] =
7620                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7621         filter_replace_buf.data[4] |=
7622                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7623         filter_replace_buf.data[6] = 0xFF;
7624         filter_replace_buf.data[7] = 0xFF;
7625         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7626                                                &filter_replace_buf);
7627         if (status < 0)
7628                 return status;
7629         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7630                     "cloud l1 type is changed from 0x%x to 0x%x",
7631                     filter_replace.old_filter_type,
7632                     filter_replace.new_filter_type);
7633
7634         /* for GTP-U */
7635         memset(&filter_replace, 0,
7636                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7637         memset(&filter_replace_buf, 0,
7638                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7639         /* create L1 filter */
7640         filter_replace.old_filter_type =
7641                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7642         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7643         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7644                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7645         /* Prepare the buffer, 2 entries */
7646         filter_replace_buf.data[0] =
7647                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7648         filter_replace_buf.data[0] |=
7649                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7650         filter_replace_buf.data[2] = 0xFF;
7651         filter_replace_buf.data[3] = 0xFF;
7652         filter_replace_buf.data[4] =
7653                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7654         filter_replace_buf.data[4] |=
7655                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7656         filter_replace_buf.data[6] = 0xFF;
7657         filter_replace_buf.data[7] = 0xFF;
7658
7659         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7660                                                &filter_replace_buf);
7661         if (!status) {
7662                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7663                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7664                             "cloud l1 type is changed from 0x%x to 0x%x",
7665                             filter_replace.old_filter_type,
7666                             filter_replace.new_filter_type);
7667         }
7668         return status;
7669 }
7670
7671 static enum
7672 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7673 {
7674         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7675         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7676         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7677         enum i40e_status_code status = I40E_SUCCESS;
7678
7679         if (pf->support_multi_driver) {
7680                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7681                 return I40E_NOT_SUPPORTED;
7682         }
7683
7684         /* for GTP-C */
7685         memset(&filter_replace, 0,
7686                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7687         memset(&filter_replace_buf, 0,
7688                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7689         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7690         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7691         filter_replace.new_filter_type =
7692                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7693         /* Prepare the buffer, 2 entries */
7694         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7695         filter_replace_buf.data[0] |=
7696                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7697         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7698         filter_replace_buf.data[4] |=
7699                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7700         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7701                                                &filter_replace_buf);
7702         if (status < 0)
7703                 return status;
7704         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7705                     "cloud filter type is changed from 0x%x to 0x%x",
7706                     filter_replace.old_filter_type,
7707                     filter_replace.new_filter_type);
7708
7709         /* for GTP-U */
7710         memset(&filter_replace, 0,
7711                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7712         memset(&filter_replace_buf, 0,
7713                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7714         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7715         filter_replace.old_filter_type =
7716                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7717         filter_replace.new_filter_type =
7718                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7719         /* Prepare the buffer, 2 entries */
7720         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7721         filter_replace_buf.data[0] |=
7722                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7723         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7724         filter_replace_buf.data[4] |=
7725                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7726
7727         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7728                                                &filter_replace_buf);
7729         if (!status) {
7730                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7731                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7732                             "cloud filter type is changed from 0x%x to 0x%x",
7733                             filter_replace.old_filter_type,
7734                             filter_replace.new_filter_type);
7735         }
7736         return status;
7737 }
7738
7739 int
7740 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7741                       struct i40e_tunnel_filter_conf *tunnel_filter,
7742                       uint8_t add)
7743 {
7744         uint16_t ip_type;
7745         uint32_t ipv4_addr, ipv4_addr_le;
7746         uint8_t i, tun_type = 0;
7747         /* internal variable to convert ipv6 byte order */
7748         uint32_t convert_ipv6[4];
7749         int val, ret = 0;
7750         struct i40e_pf_vf *vf = NULL;
7751         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7752         struct i40e_vsi *vsi;
7753         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7754         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7755         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7756         struct i40e_tunnel_filter *tunnel, *node;
7757         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7758         uint32_t teid_le;
7759         bool big_buffer = 0;
7760
7761         cld_filter = rte_zmalloc("tunnel_filter",
7762                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7763                          0);
7764
7765         if (cld_filter == NULL) {
7766                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7767                 return -ENOMEM;
7768         }
7769         pfilter = cld_filter;
7770
7771         ether_addr_copy(&tunnel_filter->outer_mac,
7772                         (struct ether_addr *)&pfilter->element.outer_mac);
7773         ether_addr_copy(&tunnel_filter->inner_mac,
7774                         (struct ether_addr *)&pfilter->element.inner_mac);
7775
7776         pfilter->element.inner_vlan =
7777                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7778         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7779                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7780                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7781                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7782                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7783                                 &ipv4_addr_le,
7784                                 sizeof(pfilter->element.ipaddr.v4.data));
7785         } else {
7786                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7787                 for (i = 0; i < 4; i++) {
7788                         convert_ipv6[i] =
7789                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7790                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7791                 }
7792                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7793                            &convert_ipv6,
7794                            sizeof(pfilter->element.ipaddr.v6.data));
7795         }
7796
7797         /* check tunneled type */
7798         switch (tunnel_filter->tunnel_type) {
7799         case I40E_TUNNEL_TYPE_VXLAN:
7800                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7801                 break;
7802         case I40E_TUNNEL_TYPE_NVGRE:
7803                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7804                 break;
7805         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7806                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7807                 break;
7808         case I40E_TUNNEL_TYPE_MPLSoUDP:
7809                 if (!pf->mpls_replace_flag) {
7810                         i40e_replace_mpls_l1_filter(pf);
7811                         i40e_replace_mpls_cloud_filter(pf);
7812                         pf->mpls_replace_flag = 1;
7813                 }
7814                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7815                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7816                         teid_le >> 4;
7817                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7818                         (teid_le & 0xF) << 12;
7819                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7820                         0x40;
7821                 big_buffer = 1;
7822                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7823                 break;
7824         case I40E_TUNNEL_TYPE_MPLSoGRE:
7825                 if (!pf->mpls_replace_flag) {
7826                         i40e_replace_mpls_l1_filter(pf);
7827                         i40e_replace_mpls_cloud_filter(pf);
7828                         pf->mpls_replace_flag = 1;
7829                 }
7830                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7831                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7832                         teid_le >> 4;
7833                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7834                         (teid_le & 0xF) << 12;
7835                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7836                         0x0;
7837                 big_buffer = 1;
7838                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7839                 break;
7840         case I40E_TUNNEL_TYPE_GTPC:
7841                 if (!pf->gtp_replace_flag) {
7842                         i40e_replace_gtp_l1_filter(pf);
7843                         i40e_replace_gtp_cloud_filter(pf);
7844                         pf->gtp_replace_flag = 1;
7845                 }
7846                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7847                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7848                         (teid_le >> 16) & 0xFFFF;
7849                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7850                         teid_le & 0xFFFF;
7851                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7852                         0x0;
7853                 big_buffer = 1;
7854                 break;
7855         case I40E_TUNNEL_TYPE_GTPU:
7856                 if (!pf->gtp_replace_flag) {
7857                         i40e_replace_gtp_l1_filter(pf);
7858                         i40e_replace_gtp_cloud_filter(pf);
7859                         pf->gtp_replace_flag = 1;
7860                 }
7861                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7862                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7863                         (teid_le >> 16) & 0xFFFF;
7864                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7865                         teid_le & 0xFFFF;
7866                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7867                         0x0;
7868                 big_buffer = 1;
7869                 break;
7870         case I40E_TUNNEL_TYPE_QINQ:
7871                 if (!pf->qinq_replace_flag) {
7872                         ret = i40e_cloud_filter_qinq_create(pf);
7873                         if (ret < 0)
7874                                 PMD_DRV_LOG(DEBUG,
7875                                             "QinQ tunnel filter already created.");
7876                         pf->qinq_replace_flag = 1;
7877                 }
7878                 /*      Add in the General fields the values of
7879                  *      the Outer and Inner VLAN
7880                  *      Big Buffer should be set, see changes in
7881                  *      i40e_aq_add_cloud_filters
7882                  */
7883                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7884                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7885                 big_buffer = 1;
7886                 break;
7887         default:
7888                 /* Other tunnel types is not supported. */
7889                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7890                 rte_free(cld_filter);
7891                 return -EINVAL;
7892         }
7893
7894         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7895                 pfilter->element.flags =
7896                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7897         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7898                 pfilter->element.flags =
7899                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7900         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7901                 pfilter->element.flags =
7902                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7903         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7904                 pfilter->element.flags =
7905                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7906         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7907                 pfilter->element.flags |=
7908                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7909         else {
7910                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7911                                                 &pfilter->element.flags);
7912                 if (val < 0) {
7913                         rte_free(cld_filter);
7914                         return -EINVAL;
7915                 }
7916         }
7917
7918         pfilter->element.flags |= rte_cpu_to_le_16(
7919                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7920                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7921         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7922         pfilter->element.queue_number =
7923                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7924
7925         if (!tunnel_filter->is_to_vf)
7926                 vsi = pf->main_vsi;
7927         else {
7928                 if (tunnel_filter->vf_id >= pf->vf_num) {
7929                         PMD_DRV_LOG(ERR, "Invalid argument.");
7930                         rte_free(cld_filter);
7931                         return -EINVAL;
7932                 }
7933                 vf = &pf->vfs[tunnel_filter->vf_id];
7934                 vsi = vf->vsi;
7935         }
7936
7937         /* Check if there is the filter in SW list */
7938         memset(&check_filter, 0, sizeof(check_filter));
7939         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7940         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7941         check_filter.vf_id = tunnel_filter->vf_id;
7942         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7943         if (add && node) {
7944                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7945                 rte_free(cld_filter);
7946                 return -EINVAL;
7947         }
7948
7949         if (!add && !node) {
7950                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7951                 rte_free(cld_filter);
7952                 return -EINVAL;
7953         }
7954
7955         if (add) {
7956                 if (big_buffer)
7957                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7958                                                    vsi->seid, cld_filter, 1);
7959                 else
7960                         ret = i40e_aq_add_cloud_filters(hw,
7961                                         vsi->seid, &cld_filter->element, 1);
7962                 if (ret < 0) {
7963                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7964                         rte_free(cld_filter);
7965                         return -ENOTSUP;
7966                 }
7967                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7968                 if (tunnel == NULL) {
7969                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7970                         rte_free(cld_filter);
7971                         return -ENOMEM;
7972                 }
7973
7974                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7975                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7976                 if (ret < 0)
7977                         rte_free(tunnel);
7978         } else {
7979                 if (big_buffer)
7980                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7981                                 hw, vsi->seid, cld_filter, 1);
7982                 else
7983                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7984                                                    &cld_filter->element, 1);
7985                 if (ret < 0) {
7986                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7987                         rte_free(cld_filter);
7988                         return -ENOTSUP;
7989                 }
7990                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7991         }
7992
7993         rte_free(cld_filter);
7994         return ret;
7995 }
7996
7997 static int
7998 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7999 {
8000         uint8_t i;
8001
8002         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8003                 if (pf->vxlan_ports[i] == port)
8004                         return i;
8005         }
8006
8007         return -1;
8008 }
8009
8010 static int
8011 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8012 {
8013         int  idx, ret;
8014         uint8_t filter_idx;
8015         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8016
8017         idx = i40e_get_vxlan_port_idx(pf, port);
8018
8019         /* Check if port already exists */
8020         if (idx >= 0) {
8021                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8022                 return -EINVAL;
8023         }
8024
8025         /* Now check if there is space to add the new port */
8026         idx = i40e_get_vxlan_port_idx(pf, 0);
8027         if (idx < 0) {
8028                 PMD_DRV_LOG(ERR,
8029                         "Maximum number of UDP ports reached, not adding port %d",
8030                         port);
8031                 return -ENOSPC;
8032         }
8033
8034         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8035                                         &filter_idx, NULL);
8036         if (ret < 0) {
8037                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8038                 return -1;
8039         }
8040
8041         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8042                          port,  filter_idx);
8043
8044         /* New port: add it and mark its index in the bitmap */
8045         pf->vxlan_ports[idx] = port;
8046         pf->vxlan_bitmap |= (1 << idx);
8047
8048         if (!(pf->flags & I40E_FLAG_VXLAN))
8049                 pf->flags |= I40E_FLAG_VXLAN;
8050
8051         return 0;
8052 }
8053
8054 static int
8055 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8056 {
8057         int idx;
8058         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8059
8060         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8061                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8062                 return -EINVAL;
8063         }
8064
8065         idx = i40e_get_vxlan_port_idx(pf, port);
8066
8067         if (idx < 0) {
8068                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8069                 return -EINVAL;
8070         }
8071
8072         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8073                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8074                 return -1;
8075         }
8076
8077         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8078                         port, idx);
8079
8080         pf->vxlan_ports[idx] = 0;
8081         pf->vxlan_bitmap &= ~(1 << idx);
8082
8083         if (!pf->vxlan_bitmap)
8084                 pf->flags &= ~I40E_FLAG_VXLAN;
8085
8086         return 0;
8087 }
8088
8089 /* Add UDP tunneling port */
8090 static int
8091 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8092                              struct rte_eth_udp_tunnel *udp_tunnel)
8093 {
8094         int ret = 0;
8095         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8096
8097         if (udp_tunnel == NULL)
8098                 return -EINVAL;
8099
8100         switch (udp_tunnel->prot_type) {
8101         case RTE_TUNNEL_TYPE_VXLAN:
8102                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8103                 break;
8104
8105         case RTE_TUNNEL_TYPE_GENEVE:
8106         case RTE_TUNNEL_TYPE_TEREDO:
8107                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8108                 ret = -1;
8109                 break;
8110
8111         default:
8112                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8113                 ret = -1;
8114                 break;
8115         }
8116
8117         return ret;
8118 }
8119
8120 /* Remove UDP tunneling port */
8121 static int
8122 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8123                              struct rte_eth_udp_tunnel *udp_tunnel)
8124 {
8125         int ret = 0;
8126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8127
8128         if (udp_tunnel == NULL)
8129                 return -EINVAL;
8130
8131         switch (udp_tunnel->prot_type) {
8132         case RTE_TUNNEL_TYPE_VXLAN:
8133                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8134                 break;
8135         case RTE_TUNNEL_TYPE_GENEVE:
8136         case RTE_TUNNEL_TYPE_TEREDO:
8137                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8138                 ret = -1;
8139                 break;
8140         default:
8141                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8142                 ret = -1;
8143                 break;
8144         }
8145
8146         return ret;
8147 }
8148
8149 /* Calculate the maximum number of contiguous PF queues that are configured */
8150 static int
8151 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8152 {
8153         struct rte_eth_dev_data *data = pf->dev_data;
8154         int i, num;
8155         struct i40e_rx_queue *rxq;
8156
8157         num = 0;
8158         for (i = 0; i < pf->lan_nb_qps; i++) {
8159                 rxq = data->rx_queues[i];
8160                 if (rxq && rxq->q_set)
8161                         num++;
8162                 else
8163                         break;
8164         }
8165
8166         return num;
8167 }
8168
8169 /* Configure RSS */
8170 static int
8171 i40e_pf_config_rss(struct i40e_pf *pf)
8172 {
8173         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8174         struct rte_eth_rss_conf rss_conf;
8175         uint32_t i, lut = 0;
8176         uint16_t j, num;
8177
8178         /*
8179          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8180          * It's necessary to calculate the actual PF queues that are configured.
8181          */
8182         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8183                 num = i40e_pf_calc_configured_queues_num(pf);
8184         else
8185                 num = pf->dev_data->nb_rx_queues;
8186
8187         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8188         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8189                         num);
8190
8191         if (num == 0) {
8192                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8193                 return -ENOTSUP;
8194         }
8195
8196         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8197                 if (j == num)
8198                         j = 0;
8199                 lut = (lut << 8) | (j & ((0x1 <<
8200                         hw->func_caps.rss_table_entry_width) - 1));
8201                 if ((i & 3) == 3)
8202                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8203         }
8204
8205         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8206         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8207                 i40e_pf_disable_rss(pf);
8208                 return 0;
8209         }
8210         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8211                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8212                 /* Random default keys */
8213                 static uint32_t rss_key_default[] = {0x6b793944,
8214                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8215                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8216                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8217
8218                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8219                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8220                                                         sizeof(uint32_t);
8221         }
8222
8223         return i40e_hw_rss_hash_set(pf, &rss_conf);
8224 }
8225
8226 static int
8227 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8228                                struct rte_eth_tunnel_filter_conf *filter)
8229 {
8230         if (pf == NULL || filter == NULL) {
8231                 PMD_DRV_LOG(ERR, "Invalid parameter");
8232                 return -EINVAL;
8233         }
8234
8235         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8236                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8237                 return -EINVAL;
8238         }
8239
8240         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8241                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8242                 return -EINVAL;
8243         }
8244
8245         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8246                 (is_zero_ether_addr(&filter->outer_mac))) {
8247                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8248                 return -EINVAL;
8249         }
8250
8251         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8252                 (is_zero_ether_addr(&filter->inner_mac))) {
8253                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8254                 return -EINVAL;
8255         }
8256
8257         return 0;
8258 }
8259
8260 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8261 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8262 static int
8263 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8264 {
8265         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8266         uint32_t val, reg;
8267         int ret = -EINVAL;
8268
8269         if (pf->support_multi_driver) {
8270                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8271                 return -ENOTSUP;
8272         }
8273
8274         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8275         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8276
8277         if (len == 3) {
8278                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8279         } else if (len == 4) {
8280                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8281         } else {
8282                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8283                 return ret;
8284         }
8285
8286         if (reg != val) {
8287                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8288                                                    reg, NULL);
8289                 if (ret != 0)
8290                         return ret;
8291                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8292                             "with value 0x%08x",
8293                             I40E_GL_PRS_FVBM(2), reg);
8294                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8295         } else {
8296                 ret = 0;
8297         }
8298         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8299                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8300
8301         return ret;
8302 }
8303
8304 static int
8305 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8306 {
8307         int ret = -EINVAL;
8308
8309         if (!hw || !cfg)
8310                 return -EINVAL;
8311
8312         switch (cfg->cfg_type) {
8313         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8314                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8315                 break;
8316         default:
8317                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8318                 break;
8319         }
8320
8321         return ret;
8322 }
8323
8324 static int
8325 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8326                                enum rte_filter_op filter_op,
8327                                void *arg)
8328 {
8329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8330         int ret = I40E_ERR_PARAM;
8331
8332         switch (filter_op) {
8333         case RTE_ETH_FILTER_SET:
8334                 ret = i40e_dev_global_config_set(hw,
8335                         (struct rte_eth_global_cfg *)arg);
8336                 break;
8337         default:
8338                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8339                 break;
8340         }
8341
8342         return ret;
8343 }
8344
8345 static int
8346 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8347                           enum rte_filter_op filter_op,
8348                           void *arg)
8349 {
8350         struct rte_eth_tunnel_filter_conf *filter;
8351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8352         int ret = I40E_SUCCESS;
8353
8354         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8355
8356         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8357                 return I40E_ERR_PARAM;
8358
8359         switch (filter_op) {
8360         case RTE_ETH_FILTER_NOP:
8361                 if (!(pf->flags & I40E_FLAG_VXLAN))
8362                         ret = I40E_NOT_SUPPORTED;
8363                 break;
8364         case RTE_ETH_FILTER_ADD:
8365                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8366                 break;
8367         case RTE_ETH_FILTER_DELETE:
8368                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8369                 break;
8370         default:
8371                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8372                 ret = I40E_ERR_PARAM;
8373                 break;
8374         }
8375
8376         return ret;
8377 }
8378
8379 static int
8380 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8381 {
8382         int ret = 0;
8383         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8384
8385         /* RSS setup */
8386         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8387                 ret = i40e_pf_config_rss(pf);
8388         else
8389                 i40e_pf_disable_rss(pf);
8390
8391         return ret;
8392 }
8393
8394 /* Get the symmetric hash enable configurations per port */
8395 static void
8396 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8397 {
8398         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8399
8400         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8401 }
8402
8403 /* Set the symmetric hash enable configurations per port */
8404 static void
8405 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8406 {
8407         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8408
8409         if (enable > 0) {
8410                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8411                         PMD_DRV_LOG(INFO,
8412                                 "Symmetric hash has already been enabled");
8413                         return;
8414                 }
8415                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8416         } else {
8417                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8418                         PMD_DRV_LOG(INFO,
8419                                 "Symmetric hash has already been disabled");
8420                         return;
8421                 }
8422                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8423         }
8424         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8425         I40E_WRITE_FLUSH(hw);
8426 }
8427
8428 /*
8429  * Get global configurations of hash function type and symmetric hash enable
8430  * per flow type (pctype). Note that global configuration means it affects all
8431  * the ports on the same NIC.
8432  */
8433 static int
8434 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8435                                    struct rte_eth_hash_global_conf *g_cfg)
8436 {
8437         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8438         uint32_t reg;
8439         uint16_t i, j;
8440
8441         memset(g_cfg, 0, sizeof(*g_cfg));
8442         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8443         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8444                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8445         else
8446                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8447         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8448                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8449
8450         /*
8451          * As i40e supports less than 64 flow types, only first 64 bits need to
8452          * be checked.
8453          */
8454         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8455                 g_cfg->valid_bit_mask[i] = 0ULL;
8456                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8457         }
8458
8459         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8460
8461         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8462                 if (!adapter->pctypes_tbl[i])
8463                         continue;
8464                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8465                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8466                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8467                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8468                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8469                                         g_cfg->sym_hash_enable_mask[0] |=
8470                                                                 (1ULL << i);
8471                                 }
8472                         }
8473                 }
8474         }
8475
8476         return 0;
8477 }
8478
8479 static int
8480 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8481                               const struct rte_eth_hash_global_conf *g_cfg)
8482 {
8483         uint32_t i;
8484         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8485
8486         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8487                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8488                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8489                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8490                                                 g_cfg->hash_func);
8491                 return -EINVAL;
8492         }
8493
8494         /*
8495          * As i40e supports less than 64 flow types, only first 64 bits need to
8496          * be checked.
8497          */
8498         mask0 = g_cfg->valid_bit_mask[0];
8499         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8500                 if (i == 0) {
8501                         /* Check if any unsupported flow type configured */
8502                         if ((mask0 | i40e_mask) ^ i40e_mask)
8503                                 goto mask_err;
8504                 } else {
8505                         if (g_cfg->valid_bit_mask[i])
8506                                 goto mask_err;
8507                 }
8508         }
8509
8510         return 0;
8511
8512 mask_err:
8513         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8514
8515         return -EINVAL;
8516 }
8517
8518 /*
8519  * Set global configurations of hash function type and symmetric hash enable
8520  * per flow type (pctype). Note any modifying global configuration will affect
8521  * all the ports on the same NIC.
8522  */
8523 static int
8524 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8525                                    struct rte_eth_hash_global_conf *g_cfg)
8526 {
8527         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8528         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8529         int ret;
8530         uint16_t i, j;
8531         uint32_t reg;
8532         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8533
8534         if (pf->support_multi_driver) {
8535                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8536                 return -ENOTSUP;
8537         }
8538
8539         /* Check the input parameters */
8540         ret = i40e_hash_global_config_check(adapter, g_cfg);
8541         if (ret < 0)
8542                 return ret;
8543
8544         /*
8545          * As i40e supports less than 64 flow types, only first 64 bits need to
8546          * be configured.
8547          */
8548         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8549                 if (mask0 & (1UL << i)) {
8550                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8551                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8552
8553                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8554                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8555                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8556                                         i40e_write_global_rx_ctl(hw,
8557                                                           I40E_GLQF_HSYM(j),
8558                                                           reg);
8559                         }
8560                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8561                 }
8562         }
8563
8564         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8565         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8566                 /* Toeplitz */
8567                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8568                         PMD_DRV_LOG(DEBUG,
8569                                 "Hash function already set to Toeplitz");
8570                         goto out;
8571                 }
8572                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8573         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8574                 /* Simple XOR */
8575                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8576                         PMD_DRV_LOG(DEBUG,
8577                                 "Hash function already set to Simple XOR");
8578                         goto out;
8579                 }
8580                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8581         } else
8582                 /* Use the default, and keep it as it is */
8583                 goto out;
8584
8585         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8586         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8587
8588 out:
8589         I40E_WRITE_FLUSH(hw);
8590
8591         return 0;
8592 }
8593
8594 /**
8595  * Valid input sets for hash and flow director filters per PCTYPE
8596  */
8597 static uint64_t
8598 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8599                 enum rte_filter_type filter)
8600 {
8601         uint64_t valid;
8602
8603         static const uint64_t valid_hash_inset_table[] = {
8604                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8605                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8606                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8607                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8608                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8609                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8610                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8611                         I40E_INSET_FLEX_PAYLOAD,
8612                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8613                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8614                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8615                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8616                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8617                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8618                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8619                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8620                         I40E_INSET_FLEX_PAYLOAD,
8621                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8622                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8623                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8624                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8625                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8626                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8627                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8628                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8629                         I40E_INSET_FLEX_PAYLOAD,
8630                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8631                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8632                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8633                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8634                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8635                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8636                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8637                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8638                         I40E_INSET_FLEX_PAYLOAD,
8639                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8640                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8641                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8642                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8643                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8644                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8645                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8646                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8647                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8648                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8649                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8650                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8651                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8652                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8653                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8654                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8655                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8656                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8657                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8658                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8659                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8660                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8661                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8662                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8663                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8664                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8665                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8666                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8667                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8668                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8669                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8670                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8671                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8672                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8673                         I40E_INSET_FLEX_PAYLOAD,
8674                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8675                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8676                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8677                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8678                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8679                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8680                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8681                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8682                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8683                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8684                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8685                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8686                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8687                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8688                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8689                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8690                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8691                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8692                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8693                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8694                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8695                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8696                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8697                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8698                         I40E_INSET_FLEX_PAYLOAD,
8699                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8700                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8701                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8702                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8703                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8704                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8705                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8706                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8707                         I40E_INSET_FLEX_PAYLOAD,
8708                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8709                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8710                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8711                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8712                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8713                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8714                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8715                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8716                         I40E_INSET_FLEX_PAYLOAD,
8717                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8718                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8719                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8720                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8721                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8722                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8723                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8724                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8725                         I40E_INSET_FLEX_PAYLOAD,
8726                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8727                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8728                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8729                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8730                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8731                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8732                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8733                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8734                         I40E_INSET_FLEX_PAYLOAD,
8735                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8736                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8737                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8738                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8739                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8740                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8741                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8742                         I40E_INSET_FLEX_PAYLOAD,
8743                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8744                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8745                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8746                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8747                         I40E_INSET_FLEX_PAYLOAD,
8748         };
8749
8750         /**
8751          * Flow director supports only fields defined in
8752          * union rte_eth_fdir_flow.
8753          */
8754         static const uint64_t valid_fdir_inset_table[] = {
8755                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8756                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8757                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8758                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8759                 I40E_INSET_IPV4_TTL,
8760                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8761                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8762                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8763                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8764                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8765                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8766                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8767                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8768                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8769                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8770                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8771                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8772                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8773                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8774                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8775                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8776                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8777                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8778                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8779                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8780                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8781                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8782                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8783                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8784                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8785                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8786                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8787                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8788                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8789                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8790                 I40E_INSET_SCTP_VT,
8791                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8792                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8793                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8794                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8795                 I40E_INSET_IPV4_TTL,
8796                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8797                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8798                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8799                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8800                 I40E_INSET_IPV6_HOP_LIMIT,
8801                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8802                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8803                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8804                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8805                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8806                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8807                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8808                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8809                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8810                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8811                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8812                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8813                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8814                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8815                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8816                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8817                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8818                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8819                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8820                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8821                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8822                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8823                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8824                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8825                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8826                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8827                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8828                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8829                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8830                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8831                 I40E_INSET_SCTP_VT,
8832                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8833                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8834                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8835                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8836                 I40E_INSET_IPV6_HOP_LIMIT,
8837                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8838                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8839                 I40E_INSET_LAST_ETHER_TYPE,
8840         };
8841
8842         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8843                 return 0;
8844         if (filter == RTE_ETH_FILTER_HASH)
8845                 valid = valid_hash_inset_table[pctype];
8846         else
8847                 valid = valid_fdir_inset_table[pctype];
8848
8849         return valid;
8850 }
8851
8852 /**
8853  * Validate if the input set is allowed for a specific PCTYPE
8854  */
8855 int
8856 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8857                 enum rte_filter_type filter, uint64_t inset)
8858 {
8859         uint64_t valid;
8860
8861         valid = i40e_get_valid_input_set(pctype, filter);
8862         if (inset & (~valid))
8863                 return -EINVAL;
8864
8865         return 0;
8866 }
8867
8868 /* default input set fields combination per pctype */
8869 uint64_t
8870 i40e_get_default_input_set(uint16_t pctype)
8871 {
8872         static const uint64_t default_inset_table[] = {
8873                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8874                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8875                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8876                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8877                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8878                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8879                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8880                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8881                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8882                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8883                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8884                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8885                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8886                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8887                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8888                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8889                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8890                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8891                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8892                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8893                         I40E_INSET_SCTP_VT,
8894                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8895                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8896                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8897                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8898                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8899                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8900                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8901                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8902                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8903                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8904                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8905                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8906                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8907                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8908                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8909                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8910                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8911                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8912                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8913                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8914                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8915                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8916                         I40E_INSET_SCTP_VT,
8917                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8918                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8919                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8920                         I40E_INSET_LAST_ETHER_TYPE,
8921         };
8922
8923         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8924                 return 0;
8925
8926         return default_inset_table[pctype];
8927 }
8928
8929 /**
8930  * Parse the input set from index to logical bit masks
8931  */
8932 static int
8933 i40e_parse_input_set(uint64_t *inset,
8934                      enum i40e_filter_pctype pctype,
8935                      enum rte_eth_input_set_field *field,
8936                      uint16_t size)
8937 {
8938         uint16_t i, j;
8939         int ret = -EINVAL;
8940
8941         static const struct {
8942                 enum rte_eth_input_set_field field;
8943                 uint64_t inset;
8944         } inset_convert_table[] = {
8945                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8946                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8947                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8948                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8949                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8950                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8951                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8952                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8953                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8954                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8955                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8956                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8957                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8958                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8959                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8960                         I40E_INSET_IPV6_NEXT_HDR},
8961                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8962                         I40E_INSET_IPV6_HOP_LIMIT},
8963                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8964                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8965                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8966                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8967                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8968                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8969                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8970                         I40E_INSET_SCTP_VT},
8971                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8972                         I40E_INSET_TUNNEL_DMAC},
8973                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8974                         I40E_INSET_VLAN_TUNNEL},
8975                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8976                         I40E_INSET_TUNNEL_ID},
8977                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8978                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8979                         I40E_INSET_FLEX_PAYLOAD_W1},
8980                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8981                         I40E_INSET_FLEX_PAYLOAD_W2},
8982                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8983                         I40E_INSET_FLEX_PAYLOAD_W3},
8984                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8985                         I40E_INSET_FLEX_PAYLOAD_W4},
8986                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8987                         I40E_INSET_FLEX_PAYLOAD_W5},
8988                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8989                         I40E_INSET_FLEX_PAYLOAD_W6},
8990                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8991                         I40E_INSET_FLEX_PAYLOAD_W7},
8992                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8993                         I40E_INSET_FLEX_PAYLOAD_W8},
8994         };
8995
8996         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8997                 return ret;
8998
8999         /* Only one item allowed for default or all */
9000         if (size == 1) {
9001                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9002                         *inset = i40e_get_default_input_set(pctype);
9003                         return 0;
9004                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9005                         *inset = I40E_INSET_NONE;
9006                         return 0;
9007                 }
9008         }
9009
9010         for (i = 0, *inset = 0; i < size; i++) {
9011                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9012                         if (field[i] == inset_convert_table[j].field) {
9013                                 *inset |= inset_convert_table[j].inset;
9014                                 break;
9015                         }
9016                 }
9017
9018                 /* It contains unsupported input set, return immediately */
9019                 if (j == RTE_DIM(inset_convert_table))
9020                         return ret;
9021         }
9022
9023         return 0;
9024 }
9025
9026 /**
9027  * Translate the input set from bit masks to register aware bit masks
9028  * and vice versa
9029  */
9030 uint64_t
9031 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9032 {
9033         uint64_t val = 0;
9034         uint16_t i;
9035
9036         struct inset_map {
9037                 uint64_t inset;
9038                 uint64_t inset_reg;
9039         };
9040
9041         static const struct inset_map inset_map_common[] = {
9042                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9043                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9044                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9045                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9046                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9047                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9048                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9049                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9050                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9051                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9052                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9053                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9054                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9055                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9056                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9057                 {I40E_INSET_TUNNEL_DMAC,
9058                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9059                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9060                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9061                 {I40E_INSET_TUNNEL_SRC_PORT,
9062                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9063                 {I40E_INSET_TUNNEL_DST_PORT,
9064                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9065                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9066                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9067                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9068                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9069                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9070                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9071                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9072                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9073                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9074         };
9075
9076     /* some different registers map in x722*/
9077         static const struct inset_map inset_map_diff_x722[] = {
9078                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9079                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9080                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9081                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9082         };
9083
9084         static const struct inset_map inset_map_diff_not_x722[] = {
9085                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9086                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9087                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9088                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9089         };
9090
9091         if (input == 0)
9092                 return val;
9093
9094         /* Translate input set to register aware inset */
9095         if (type == I40E_MAC_X722) {
9096                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9097                         if (input & inset_map_diff_x722[i].inset)
9098                                 val |= inset_map_diff_x722[i].inset_reg;
9099                 }
9100         } else {
9101                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9102                         if (input & inset_map_diff_not_x722[i].inset)
9103                                 val |= inset_map_diff_not_x722[i].inset_reg;
9104                 }
9105         }
9106
9107         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9108                 if (input & inset_map_common[i].inset)
9109                         val |= inset_map_common[i].inset_reg;
9110         }
9111
9112         return val;
9113 }
9114
9115 int
9116 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9117 {
9118         uint8_t i, idx = 0;
9119         uint64_t inset_need_mask = inset;
9120
9121         static const struct {
9122                 uint64_t inset;
9123                 uint32_t mask;
9124         } inset_mask_map[] = {
9125                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9126                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9127                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9128                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9129                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9130                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9131                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9132                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9133         };
9134
9135         if (!inset || !mask || !nb_elem)
9136                 return 0;
9137
9138         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9139                 /* Clear the inset bit, if no MASK is required,
9140                  * for example proto + ttl
9141                  */
9142                 if ((inset & inset_mask_map[i].inset) ==
9143                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9144                         inset_need_mask &= ~inset_mask_map[i].inset;
9145                 if (!inset_need_mask)
9146                         return 0;
9147         }
9148         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9149                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9150                     inset_mask_map[i].inset) {
9151                         if (idx >= nb_elem) {
9152                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9153                                 return -EINVAL;
9154                         }
9155                         mask[idx] = inset_mask_map[i].mask;
9156                         idx++;
9157                 }
9158         }
9159
9160         return idx;
9161 }
9162
9163 void
9164 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9165 {
9166         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9167
9168         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9169         if (reg != val)
9170                 i40e_write_rx_ctl(hw, addr, val);
9171         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9172                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9173 }
9174
9175 void
9176 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9177 {
9178         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9179
9180         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9181         if (reg != val)
9182                 i40e_write_global_rx_ctl(hw, addr, val);
9183         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9184                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9185 }
9186
9187 static void
9188 i40e_filter_input_set_init(struct i40e_pf *pf)
9189 {
9190         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9191         enum i40e_filter_pctype pctype;
9192         uint64_t input_set, inset_reg;
9193         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9194         int num, i;
9195         uint16_t flow_type;
9196
9197         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9198              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9199                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9200
9201                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9202                         continue;
9203
9204                 input_set = i40e_get_default_input_set(pctype);
9205
9206                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9207                                                    I40E_INSET_MASK_NUM_REG);
9208                 if (num < 0)
9209                         return;
9210                 if (pf->support_multi_driver && num > 0) {
9211                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9212                         return;
9213                 }
9214                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9215                                         input_set);
9216
9217                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9218                                       (uint32_t)(inset_reg & UINT32_MAX));
9219                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9220                                      (uint32_t)((inset_reg >>
9221                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9222                 if (!pf->support_multi_driver) {
9223                         i40e_check_write_global_reg(hw,
9224                                             I40E_GLQF_HASH_INSET(0, pctype),
9225                                             (uint32_t)(inset_reg & UINT32_MAX));
9226                         i40e_check_write_global_reg(hw,
9227                                              I40E_GLQF_HASH_INSET(1, pctype),
9228                                              (uint32_t)((inset_reg >>
9229                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9230
9231                         for (i = 0; i < num; i++) {
9232                                 i40e_check_write_global_reg(hw,
9233                                                     I40E_GLQF_FD_MSK(i, pctype),
9234                                                     mask_reg[i]);
9235                                 i40e_check_write_global_reg(hw,
9236                                                   I40E_GLQF_HASH_MSK(i, pctype),
9237                                                   mask_reg[i]);
9238                         }
9239                         /*clear unused mask registers of the pctype */
9240                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9241                                 i40e_check_write_global_reg(hw,
9242                                                     I40E_GLQF_FD_MSK(i, pctype),
9243                                                     0);
9244                                 i40e_check_write_global_reg(hw,
9245                                                   I40E_GLQF_HASH_MSK(i, pctype),
9246                                                   0);
9247                         }
9248                 } else {
9249                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9250                 }
9251                 I40E_WRITE_FLUSH(hw);
9252
9253                 /* store the default input set */
9254                 if (!pf->support_multi_driver)
9255                         pf->hash_input_set[pctype] = input_set;
9256                 pf->fdir.input_set[pctype] = input_set;
9257         }
9258
9259         if (!pf->support_multi_driver) {
9260                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9261                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9262                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9263         }
9264 }
9265
9266 int
9267 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9268                          struct rte_eth_input_set_conf *conf)
9269 {
9270         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9271         enum i40e_filter_pctype pctype;
9272         uint64_t input_set, inset_reg = 0;
9273         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9274         int ret, i, num;
9275
9276         if (!conf) {
9277                 PMD_DRV_LOG(ERR, "Invalid pointer");
9278                 return -EFAULT;
9279         }
9280         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9281             conf->op != RTE_ETH_INPUT_SET_ADD) {
9282                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9283                 return -EINVAL;
9284         }
9285
9286         if (pf->support_multi_driver) {
9287                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9288                 return -ENOTSUP;
9289         }
9290
9291         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9292         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9293                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9294                 return -EINVAL;
9295         }
9296
9297         if (hw->mac.type == I40E_MAC_X722) {
9298                 /* get translated pctype value in fd pctype register */
9299                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9300                         I40E_GLQF_FD_PCTYPES((int)pctype));
9301         }
9302
9303         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9304                                    conf->inset_size);
9305         if (ret) {
9306                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9307                 return -EINVAL;
9308         }
9309
9310         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9311                 /* get inset value in register */
9312                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9313                 inset_reg <<= I40E_32_BIT_WIDTH;
9314                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9315                 input_set |= pf->hash_input_set[pctype];
9316         }
9317         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9318                                            I40E_INSET_MASK_NUM_REG);
9319         if (num < 0)
9320                 return -EINVAL;
9321
9322         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9323
9324         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9325                                     (uint32_t)(inset_reg & UINT32_MAX));
9326         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9327                                     (uint32_t)((inset_reg >>
9328                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9329         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9330
9331         for (i = 0; i < num; i++)
9332                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9333                                             mask_reg[i]);
9334         /*clear unused mask registers of the pctype */
9335         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9336                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9337                                             0);
9338         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9339         I40E_WRITE_FLUSH(hw);
9340
9341         pf->hash_input_set[pctype] = input_set;
9342         return 0;
9343 }
9344
9345 int
9346 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9347                          struct rte_eth_input_set_conf *conf)
9348 {
9349         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9350         enum i40e_filter_pctype pctype;
9351         uint64_t input_set, inset_reg = 0;
9352         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9353         int ret, i, num;
9354
9355         if (!hw || !conf) {
9356                 PMD_DRV_LOG(ERR, "Invalid pointer");
9357                 return -EFAULT;
9358         }
9359         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9360             conf->op != RTE_ETH_INPUT_SET_ADD) {
9361                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9362                 return -EINVAL;
9363         }
9364
9365         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9366
9367         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9368                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9369                 return -EINVAL;
9370         }
9371
9372         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9373                                    conf->inset_size);
9374         if (ret) {
9375                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9376                 return -EINVAL;
9377         }
9378
9379         /* get inset value in register */
9380         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9381         inset_reg <<= I40E_32_BIT_WIDTH;
9382         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9383
9384         /* Can not change the inset reg for flex payload for fdir,
9385          * it is done by writing I40E_PRTQF_FD_FLXINSET
9386          * in i40e_set_flex_mask_on_pctype.
9387          */
9388         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9389                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9390         else
9391                 input_set |= pf->fdir.input_set[pctype];
9392         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9393                                            I40E_INSET_MASK_NUM_REG);
9394         if (num < 0)
9395                 return -EINVAL;
9396         if (pf->support_multi_driver && num > 0) {
9397                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9398                 return -ENOTSUP;
9399         }
9400
9401         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9402
9403         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9404                               (uint32_t)(inset_reg & UINT32_MAX));
9405         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9406                              (uint32_t)((inset_reg >>
9407                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9408
9409         if (!pf->support_multi_driver) {
9410                 for (i = 0; i < num; i++)
9411                         i40e_check_write_global_reg(hw,
9412                                                     I40E_GLQF_FD_MSK(i, pctype),
9413                                                     mask_reg[i]);
9414                 /*clear unused mask registers of the pctype */
9415                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9416                         i40e_check_write_global_reg(hw,
9417                                                     I40E_GLQF_FD_MSK(i, pctype),
9418                                                     0);
9419                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9420         } else {
9421                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9422         }
9423         I40E_WRITE_FLUSH(hw);
9424
9425         pf->fdir.input_set[pctype] = input_set;
9426         return 0;
9427 }
9428
9429 static int
9430 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9431 {
9432         int ret = 0;
9433
9434         if (!hw || !info) {
9435                 PMD_DRV_LOG(ERR, "Invalid pointer");
9436                 return -EFAULT;
9437         }
9438
9439         switch (info->info_type) {
9440         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9441                 i40e_get_symmetric_hash_enable_per_port(hw,
9442                                         &(info->info.enable));
9443                 break;
9444         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9445                 ret = i40e_get_hash_filter_global_config(hw,
9446                                 &(info->info.global_conf));
9447                 break;
9448         default:
9449                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9450                                                         info->info_type);
9451                 ret = -EINVAL;
9452                 break;
9453         }
9454
9455         return ret;
9456 }
9457
9458 static int
9459 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9460 {
9461         int ret = 0;
9462
9463         if (!hw || !info) {
9464                 PMD_DRV_LOG(ERR, "Invalid pointer");
9465                 return -EFAULT;
9466         }
9467
9468         switch (info->info_type) {
9469         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9470                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9471                 break;
9472         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9473                 ret = i40e_set_hash_filter_global_config(hw,
9474                                 &(info->info.global_conf));
9475                 break;
9476         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9477                 ret = i40e_hash_filter_inset_select(hw,
9478                                                &(info->info.input_set_conf));
9479                 break;
9480
9481         default:
9482                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9483                                                         info->info_type);
9484                 ret = -EINVAL;
9485                 break;
9486         }
9487
9488         return ret;
9489 }
9490
9491 /* Operations for hash function */
9492 static int
9493 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9494                       enum rte_filter_op filter_op,
9495                       void *arg)
9496 {
9497         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9498         int ret = 0;
9499
9500         switch (filter_op) {
9501         case RTE_ETH_FILTER_NOP:
9502                 break;
9503         case RTE_ETH_FILTER_GET:
9504                 ret = i40e_hash_filter_get(hw,
9505                         (struct rte_eth_hash_filter_info *)arg);
9506                 break;
9507         case RTE_ETH_FILTER_SET:
9508                 ret = i40e_hash_filter_set(hw,
9509                         (struct rte_eth_hash_filter_info *)arg);
9510                 break;
9511         default:
9512                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9513                                                                 filter_op);
9514                 ret = -ENOTSUP;
9515                 break;
9516         }
9517
9518         return ret;
9519 }
9520
9521 /* Convert ethertype filter structure */
9522 static int
9523 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9524                               struct i40e_ethertype_filter *filter)
9525 {
9526         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9527         filter->input.ether_type = input->ether_type;
9528         filter->flags = input->flags;
9529         filter->queue = input->queue;
9530
9531         return 0;
9532 }
9533
9534 /* Check if there exists the ehtertype filter */
9535 struct i40e_ethertype_filter *
9536 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9537                                 const struct i40e_ethertype_filter_input *input)
9538 {
9539         int ret;
9540
9541         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9542         if (ret < 0)
9543                 return NULL;
9544
9545         return ethertype_rule->hash_map[ret];
9546 }
9547
9548 /* Add ethertype filter in SW list */
9549 static int
9550 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9551                                 struct i40e_ethertype_filter *filter)
9552 {
9553         struct i40e_ethertype_rule *rule = &pf->ethertype;
9554         int ret;
9555
9556         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9557         if (ret < 0) {
9558                 PMD_DRV_LOG(ERR,
9559                             "Failed to insert ethertype filter"
9560                             " to hash table %d!",
9561                             ret);
9562                 return ret;
9563         }
9564         rule->hash_map[ret] = filter;
9565
9566         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9567
9568         return 0;
9569 }
9570
9571 /* Delete ethertype filter in SW list */
9572 int
9573 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9574                              struct i40e_ethertype_filter_input *input)
9575 {
9576         struct i40e_ethertype_rule *rule = &pf->ethertype;
9577         struct i40e_ethertype_filter *filter;
9578         int ret;
9579
9580         ret = rte_hash_del_key(rule->hash_table, input);
9581         if (ret < 0) {
9582                 PMD_DRV_LOG(ERR,
9583                             "Failed to delete ethertype filter"
9584                             " to hash table %d!",
9585                             ret);
9586                 return ret;
9587         }
9588         filter = rule->hash_map[ret];
9589         rule->hash_map[ret] = NULL;
9590
9591         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9592         rte_free(filter);
9593
9594         return 0;
9595 }
9596
9597 /*
9598  * Configure ethertype filter, which can director packet by filtering
9599  * with mac address and ether_type or only ether_type
9600  */
9601 int
9602 i40e_ethertype_filter_set(struct i40e_pf *pf,
9603                         struct rte_eth_ethertype_filter *filter,
9604                         bool add)
9605 {
9606         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9607         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9608         struct i40e_ethertype_filter *ethertype_filter, *node;
9609         struct i40e_ethertype_filter check_filter;
9610         struct i40e_control_filter_stats stats;
9611         uint16_t flags = 0;
9612         int ret;
9613
9614         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9615                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9616                 return -EINVAL;
9617         }
9618         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9619                 filter->ether_type == ETHER_TYPE_IPv6) {
9620                 PMD_DRV_LOG(ERR,
9621                         "unsupported ether_type(0x%04x) in control packet filter.",
9622                         filter->ether_type);
9623                 return -EINVAL;
9624         }
9625         if (filter->ether_type == ETHER_TYPE_VLAN)
9626                 PMD_DRV_LOG(WARNING,
9627                         "filter vlan ether_type in first tag is not supported.");
9628
9629         /* Check if there is the filter in SW list */
9630         memset(&check_filter, 0, sizeof(check_filter));
9631         i40e_ethertype_filter_convert(filter, &check_filter);
9632         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9633                                                &check_filter.input);
9634         if (add && node) {
9635                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9636                 return -EINVAL;
9637         }
9638
9639         if (!add && !node) {
9640                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9641                 return -EINVAL;
9642         }
9643
9644         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9645                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9646         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9647                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9648         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9649
9650         memset(&stats, 0, sizeof(stats));
9651         ret = i40e_aq_add_rem_control_packet_filter(hw,
9652                         filter->mac_addr.addr_bytes,
9653                         filter->ether_type, flags,
9654                         pf->main_vsi->seid,
9655                         filter->queue, add, &stats, NULL);
9656
9657         PMD_DRV_LOG(INFO,
9658                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9659                 ret, stats.mac_etype_used, stats.etype_used,
9660                 stats.mac_etype_free, stats.etype_free);
9661         if (ret < 0)
9662                 return -ENOSYS;
9663
9664         /* Add or delete a filter in SW list */
9665         if (add) {
9666                 ethertype_filter = rte_zmalloc("ethertype_filter",
9667                                        sizeof(*ethertype_filter), 0);
9668                 if (ethertype_filter == NULL) {
9669                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9670                         return -ENOMEM;
9671                 }
9672
9673                 rte_memcpy(ethertype_filter, &check_filter,
9674                            sizeof(check_filter));
9675                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9676                 if (ret < 0)
9677                         rte_free(ethertype_filter);
9678         } else {
9679                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9680         }
9681
9682         return ret;
9683 }
9684
9685 /*
9686  * Handle operations for ethertype filter.
9687  */
9688 static int
9689 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9690                                 enum rte_filter_op filter_op,
9691                                 void *arg)
9692 {
9693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9694         int ret = 0;
9695
9696         if (filter_op == RTE_ETH_FILTER_NOP)
9697                 return ret;
9698
9699         if (arg == NULL) {
9700                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9701                             filter_op);
9702                 return -EINVAL;
9703         }
9704
9705         switch (filter_op) {
9706         case RTE_ETH_FILTER_ADD:
9707                 ret = i40e_ethertype_filter_set(pf,
9708                         (struct rte_eth_ethertype_filter *)arg,
9709                         TRUE);
9710                 break;
9711         case RTE_ETH_FILTER_DELETE:
9712                 ret = i40e_ethertype_filter_set(pf,
9713                         (struct rte_eth_ethertype_filter *)arg,
9714                         FALSE);
9715                 break;
9716         default:
9717                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9718                 ret = -ENOSYS;
9719                 break;
9720         }
9721         return ret;
9722 }
9723
9724 static int
9725 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9726                      enum rte_filter_type filter_type,
9727                      enum rte_filter_op filter_op,
9728                      void *arg)
9729 {
9730         int ret = 0;
9731
9732         if (dev == NULL)
9733                 return -EINVAL;
9734
9735         switch (filter_type) {
9736         case RTE_ETH_FILTER_NONE:
9737                 /* For global configuration */
9738                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9739                 break;
9740         case RTE_ETH_FILTER_HASH:
9741                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9742                 break;
9743         case RTE_ETH_FILTER_MACVLAN:
9744                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9745                 break;
9746         case RTE_ETH_FILTER_ETHERTYPE:
9747                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9748                 break;
9749         case RTE_ETH_FILTER_TUNNEL:
9750                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9751                 break;
9752         case RTE_ETH_FILTER_FDIR:
9753                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9754                 break;
9755         case RTE_ETH_FILTER_GENERIC:
9756                 if (filter_op != RTE_ETH_FILTER_GET)
9757                         return -EINVAL;
9758                 *(const void **)arg = &i40e_flow_ops;
9759                 break;
9760         default:
9761                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9762                                                         filter_type);
9763                 ret = -EINVAL;
9764                 break;
9765         }
9766
9767         return ret;
9768 }
9769
9770 /*
9771  * Check and enable Extended Tag.
9772  * Enabling Extended Tag is important for 40G performance.
9773  */
9774 static void
9775 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9776 {
9777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9778         uint32_t buf = 0;
9779         int ret;
9780
9781         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9782                                       PCI_DEV_CAP_REG);
9783         if (ret < 0) {
9784                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9785                             PCI_DEV_CAP_REG);
9786                 return;
9787         }
9788         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9789                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9790                 return;
9791         }
9792
9793         buf = 0;
9794         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9795                                       PCI_DEV_CTRL_REG);
9796         if (ret < 0) {
9797                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9798                             PCI_DEV_CTRL_REG);
9799                 return;
9800         }
9801         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9802                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9803                 return;
9804         }
9805         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9806         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9807                                        PCI_DEV_CTRL_REG);
9808         if (ret < 0) {
9809                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9810                             PCI_DEV_CTRL_REG);
9811                 return;
9812         }
9813 }
9814
9815 /*
9816  * As some registers wouldn't be reset unless a global hardware reset,
9817  * hardware initialization is needed to put those registers into an
9818  * expected initial state.
9819  */
9820 static void
9821 i40e_hw_init(struct rte_eth_dev *dev)
9822 {
9823         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9824
9825         i40e_enable_extended_tag(dev);
9826
9827         /* clear the PF Queue Filter control register */
9828         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9829
9830         /* Disable symmetric hash per port */
9831         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9832 }
9833
9834 /*
9835  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9836  * however this function will return only one highest pctype index,
9837  * which is not quite correct. This is known problem of i40e driver
9838  * and needs to be fixed later.
9839  */
9840 enum i40e_filter_pctype
9841 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9842 {
9843         int i;
9844         uint64_t pctype_mask;
9845
9846         if (flow_type < I40E_FLOW_TYPE_MAX) {
9847                 pctype_mask = adapter->pctypes_tbl[flow_type];
9848                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9849                         if (pctype_mask & (1ULL << i))
9850                                 return (enum i40e_filter_pctype)i;
9851                 }
9852         }
9853         return I40E_FILTER_PCTYPE_INVALID;
9854 }
9855
9856 uint16_t
9857 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9858                         enum i40e_filter_pctype pctype)
9859 {
9860         uint16_t flowtype;
9861         uint64_t pctype_mask = 1ULL << pctype;
9862
9863         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9864              flowtype++) {
9865                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9866                         return flowtype;
9867         }
9868
9869         return RTE_ETH_FLOW_UNKNOWN;
9870 }
9871
9872 /*
9873  * On X710, performance number is far from the expectation on recent firmware
9874  * versions; on XL710, performance number is also far from the expectation on
9875  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9876  * mode is enabled and port MAC address is equal to the packet destination MAC
9877  * address. The fix for this issue may not be integrated in the following
9878  * firmware version. So the workaround in software driver is needed. It needs
9879  * to modify the initial values of 3 internal only registers for both X710 and
9880  * XL710. Note that the values for X710 or XL710 could be different, and the
9881  * workaround can be removed when it is fixed in firmware in the future.
9882  */
9883
9884 /* For both X710 and XL710 */
9885 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9886 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9887 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9888
9889 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9890 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9891
9892 /* For X722 */
9893 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9894 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9895
9896 /* For X710 */
9897 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9898 /* For XL710 */
9899 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9900 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9901
9902 static int
9903 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9904 {
9905         enum i40e_status_code status;
9906         struct i40e_aq_get_phy_abilities_resp phy_ab;
9907         int ret = -ENOTSUP;
9908         int retries = 0;
9909
9910         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9911                                               NULL);
9912
9913         while (status) {
9914                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9915                         status);
9916                 retries++;
9917                 rte_delay_us(100000);
9918                 if  (retries < 5)
9919                         status = i40e_aq_get_phy_capabilities(hw, false,
9920                                         true, &phy_ab, NULL);
9921                 else
9922                         return ret;
9923         }
9924         return 0;
9925 }
9926
9927 static void
9928 i40e_configure_registers(struct i40e_hw *hw)
9929 {
9930         static struct {
9931                 uint32_t addr;
9932                 uint64_t val;
9933         } reg_table[] = {
9934                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9935                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9936                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9937         };
9938         uint64_t reg;
9939         uint32_t i;
9940         int ret;
9941
9942         for (i = 0; i < RTE_DIM(reg_table); i++) {
9943                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9944                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9945                                 reg_table[i].val =
9946                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9947                         else /* For X710/XL710/XXV710 */
9948                                 if (hw->aq.fw_maj_ver < 6)
9949                                         reg_table[i].val =
9950                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9951                                 else
9952                                         reg_table[i].val =
9953                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9954                 }
9955
9956                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9957                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9958                                 reg_table[i].val =
9959                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9960                         else /* For X710/XL710/XXV710 */
9961                                 reg_table[i].val =
9962                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9963                 }
9964
9965                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9966                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9967                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9968                                 reg_table[i].val =
9969                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9970                         else /* For X710 */
9971                                 reg_table[i].val =
9972                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9973                 }
9974
9975                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9976                                                         &reg, NULL);
9977                 if (ret < 0) {
9978                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9979                                                         reg_table[i].addr);
9980                         break;
9981                 }
9982                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9983                                                 reg_table[i].addr, reg);
9984                 if (reg == reg_table[i].val)
9985                         continue;
9986
9987                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9988                                                 reg_table[i].val, NULL);
9989                 if (ret < 0) {
9990                         PMD_DRV_LOG(ERR,
9991                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9992                                 reg_table[i].val, reg_table[i].addr);
9993                         break;
9994                 }
9995                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9996                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9997         }
9998 }
9999
10000 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10001 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10002 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10003 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10004 static int
10005 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10006 {
10007         uint32_t reg;
10008         int ret;
10009
10010         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10011                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10012                 return -EINVAL;
10013         }
10014
10015         /* Configure for double VLAN RX stripping */
10016         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10017         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10018                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10019                 ret = i40e_aq_debug_write_register(hw,
10020                                                    I40E_VSI_TSR(vsi->vsi_id),
10021                                                    reg, NULL);
10022                 if (ret < 0) {
10023                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10024                                     vsi->vsi_id);
10025                         return I40E_ERR_CONFIG;
10026                 }
10027         }
10028
10029         /* Configure for double VLAN TX insertion */
10030         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10031         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10032                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10033                 ret = i40e_aq_debug_write_register(hw,
10034                                                    I40E_VSI_L2TAGSTXVALID(
10035                                                    vsi->vsi_id), reg, NULL);
10036                 if (ret < 0) {
10037                         PMD_DRV_LOG(ERR,
10038                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10039                                 vsi->vsi_id);
10040                         return I40E_ERR_CONFIG;
10041                 }
10042         }
10043
10044         return 0;
10045 }
10046
10047 /**
10048  * i40e_aq_add_mirror_rule
10049  * @hw: pointer to the hardware structure
10050  * @seid: VEB seid to add mirror rule to
10051  * @dst_id: destination vsi seid
10052  * @entries: Buffer which contains the entities to be mirrored
10053  * @count: number of entities contained in the buffer
10054  * @rule_id:the rule_id of the rule to be added
10055  *
10056  * Add a mirror rule for a given veb.
10057  *
10058  **/
10059 static enum i40e_status_code
10060 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10061                         uint16_t seid, uint16_t dst_id,
10062                         uint16_t rule_type, uint16_t *entries,
10063                         uint16_t count, uint16_t *rule_id)
10064 {
10065         struct i40e_aq_desc desc;
10066         struct i40e_aqc_add_delete_mirror_rule cmd;
10067         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10068                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10069                 &desc.params.raw;
10070         uint16_t buff_len;
10071         enum i40e_status_code status;
10072
10073         i40e_fill_default_direct_cmd_desc(&desc,
10074                                           i40e_aqc_opc_add_mirror_rule);
10075         memset(&cmd, 0, sizeof(cmd));
10076
10077         buff_len = sizeof(uint16_t) * count;
10078         desc.datalen = rte_cpu_to_le_16(buff_len);
10079         if (buff_len > 0)
10080                 desc.flags |= rte_cpu_to_le_16(
10081                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10082         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10083                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10084         cmd.num_entries = rte_cpu_to_le_16(count);
10085         cmd.seid = rte_cpu_to_le_16(seid);
10086         cmd.destination = rte_cpu_to_le_16(dst_id);
10087
10088         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10089         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10090         PMD_DRV_LOG(INFO,
10091                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10092                 hw->aq.asq_last_status, resp->rule_id,
10093                 resp->mirror_rules_used, resp->mirror_rules_free);
10094         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10095
10096         return status;
10097 }
10098
10099 /**
10100  * i40e_aq_del_mirror_rule
10101  * @hw: pointer to the hardware structure
10102  * @seid: VEB seid to add mirror rule to
10103  * @entries: Buffer which contains the entities to be mirrored
10104  * @count: number of entities contained in the buffer
10105  * @rule_id:the rule_id of the rule to be delete
10106  *
10107  * Delete a mirror rule for a given veb.
10108  *
10109  **/
10110 static enum i40e_status_code
10111 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10112                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10113                 uint16_t count, uint16_t rule_id)
10114 {
10115         struct i40e_aq_desc desc;
10116         struct i40e_aqc_add_delete_mirror_rule cmd;
10117         uint16_t buff_len = 0;
10118         enum i40e_status_code status;
10119         void *buff = NULL;
10120
10121         i40e_fill_default_direct_cmd_desc(&desc,
10122                                           i40e_aqc_opc_delete_mirror_rule);
10123         memset(&cmd, 0, sizeof(cmd));
10124         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10125                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10126                                                           I40E_AQ_FLAG_RD));
10127                 cmd.num_entries = count;
10128                 buff_len = sizeof(uint16_t) * count;
10129                 desc.datalen = rte_cpu_to_le_16(buff_len);
10130                 buff = (void *)entries;
10131         } else
10132                 /* rule id is filled in destination field for deleting mirror rule */
10133                 cmd.destination = rte_cpu_to_le_16(rule_id);
10134
10135         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10136                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10137         cmd.seid = rte_cpu_to_le_16(seid);
10138
10139         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10140         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10141
10142         return status;
10143 }
10144
10145 /**
10146  * i40e_mirror_rule_set
10147  * @dev: pointer to the hardware structure
10148  * @mirror_conf: mirror rule info
10149  * @sw_id: mirror rule's sw_id
10150  * @on: enable/disable
10151  *
10152  * set a mirror rule.
10153  *
10154  **/
10155 static int
10156 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10157                         struct rte_eth_mirror_conf *mirror_conf,
10158                         uint8_t sw_id, uint8_t on)
10159 {
10160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10161         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10162         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10163         struct i40e_mirror_rule *parent = NULL;
10164         uint16_t seid, dst_seid, rule_id;
10165         uint16_t i, j = 0;
10166         int ret;
10167
10168         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10169
10170         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10171                 PMD_DRV_LOG(ERR,
10172                         "mirror rule can not be configured without veb or vfs.");
10173                 return -ENOSYS;
10174         }
10175         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10176                 PMD_DRV_LOG(ERR, "mirror table is full.");
10177                 return -ENOSPC;
10178         }
10179         if (mirror_conf->dst_pool > pf->vf_num) {
10180                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10181                                  mirror_conf->dst_pool);
10182                 return -EINVAL;
10183         }
10184
10185         seid = pf->main_vsi->veb->seid;
10186
10187         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10188                 if (sw_id <= it->index) {
10189                         mirr_rule = it;
10190                         break;
10191                 }
10192                 parent = it;
10193         }
10194         if (mirr_rule && sw_id == mirr_rule->index) {
10195                 if (on) {
10196                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10197                         return -EEXIST;
10198                 } else {
10199                         ret = i40e_aq_del_mirror_rule(hw, seid,
10200                                         mirr_rule->rule_type,
10201                                         mirr_rule->entries,
10202                                         mirr_rule->num_entries, mirr_rule->id);
10203                         if (ret < 0) {
10204                                 PMD_DRV_LOG(ERR,
10205                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10206                                         ret, hw->aq.asq_last_status);
10207                                 return -ENOSYS;
10208                         }
10209                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10210                         rte_free(mirr_rule);
10211                         pf->nb_mirror_rule--;
10212                         return 0;
10213                 }
10214         } else if (!on) {
10215                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10216                 return -ENOENT;
10217         }
10218
10219         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10220                                 sizeof(struct i40e_mirror_rule) , 0);
10221         if (!mirr_rule) {
10222                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10223                 return I40E_ERR_NO_MEMORY;
10224         }
10225         switch (mirror_conf->rule_type) {
10226         case ETH_MIRROR_VLAN:
10227                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10228                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10229                                 mirr_rule->entries[j] =
10230                                         mirror_conf->vlan.vlan_id[i];
10231                                 j++;
10232                         }
10233                 }
10234                 if (j == 0) {
10235                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10236                         rte_free(mirr_rule);
10237                         return -EINVAL;
10238                 }
10239                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10240                 break;
10241         case ETH_MIRROR_VIRTUAL_POOL_UP:
10242         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10243                 /* check if the specified pool bit is out of range */
10244                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10245                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10246                         rte_free(mirr_rule);
10247                         return -EINVAL;
10248                 }
10249                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10250                         if (mirror_conf->pool_mask & (1ULL << i)) {
10251                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10252                                 j++;
10253                         }
10254                 }
10255                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10256                         /* add pf vsi to entries */
10257                         mirr_rule->entries[j] = pf->main_vsi_seid;
10258                         j++;
10259                 }
10260                 if (j == 0) {
10261                         PMD_DRV_LOG(ERR, "pool is not specified.");
10262                         rte_free(mirr_rule);
10263                         return -EINVAL;
10264                 }
10265                 /* egress and ingress in aq commands means from switch but not port */
10266                 mirr_rule->rule_type =
10267                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10268                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10269                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10270                 break;
10271         case ETH_MIRROR_UPLINK_PORT:
10272                 /* egress and ingress in aq commands means from switch but not port*/
10273                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10274                 break;
10275         case ETH_MIRROR_DOWNLINK_PORT:
10276                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10277                 break;
10278         default:
10279                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10280                         mirror_conf->rule_type);
10281                 rte_free(mirr_rule);
10282                 return -EINVAL;
10283         }
10284
10285         /* If the dst_pool is equal to vf_num, consider it as PF */
10286         if (mirror_conf->dst_pool == pf->vf_num)
10287                 dst_seid = pf->main_vsi_seid;
10288         else
10289                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10290
10291         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10292                                       mirr_rule->rule_type, mirr_rule->entries,
10293                                       j, &rule_id);
10294         if (ret < 0) {
10295                 PMD_DRV_LOG(ERR,
10296                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10297                         ret, hw->aq.asq_last_status);
10298                 rte_free(mirr_rule);
10299                 return -ENOSYS;
10300         }
10301
10302         mirr_rule->index = sw_id;
10303         mirr_rule->num_entries = j;
10304         mirr_rule->id = rule_id;
10305         mirr_rule->dst_vsi_seid = dst_seid;
10306
10307         if (parent)
10308                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10309         else
10310                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10311
10312         pf->nb_mirror_rule++;
10313         return 0;
10314 }
10315
10316 /**
10317  * i40e_mirror_rule_reset
10318  * @dev: pointer to the device
10319  * @sw_id: mirror rule's sw_id
10320  *
10321  * reset a mirror rule.
10322  *
10323  **/
10324 static int
10325 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10326 {
10327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10328         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10329         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10330         uint16_t seid;
10331         int ret;
10332
10333         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10334
10335         seid = pf->main_vsi->veb->seid;
10336
10337         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10338                 if (sw_id == it->index) {
10339                         mirr_rule = it;
10340                         break;
10341                 }
10342         }
10343         if (mirr_rule) {
10344                 ret = i40e_aq_del_mirror_rule(hw, seid,
10345                                 mirr_rule->rule_type,
10346                                 mirr_rule->entries,
10347                                 mirr_rule->num_entries, mirr_rule->id);
10348                 if (ret < 0) {
10349                         PMD_DRV_LOG(ERR,
10350                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10351                                 ret, hw->aq.asq_last_status);
10352                         return -ENOSYS;
10353                 }
10354                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10355                 rte_free(mirr_rule);
10356                 pf->nb_mirror_rule--;
10357         } else {
10358                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10359                 return -ENOENT;
10360         }
10361         return 0;
10362 }
10363
10364 static uint64_t
10365 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10366 {
10367         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10368         uint64_t systim_cycles;
10369
10370         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10371         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10372                         << 32;
10373
10374         return systim_cycles;
10375 }
10376
10377 static uint64_t
10378 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10379 {
10380         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10381         uint64_t rx_tstamp;
10382
10383         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10384         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10385                         << 32;
10386
10387         return rx_tstamp;
10388 }
10389
10390 static uint64_t
10391 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10392 {
10393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10394         uint64_t tx_tstamp;
10395
10396         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10397         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10398                         << 32;
10399
10400         return tx_tstamp;
10401 }
10402
10403 static void
10404 i40e_start_timecounters(struct rte_eth_dev *dev)
10405 {
10406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10407         struct i40e_adapter *adapter =
10408                         (struct i40e_adapter *)dev->data->dev_private;
10409         struct rte_eth_link link;
10410         uint32_t tsync_inc_l;
10411         uint32_t tsync_inc_h;
10412
10413         /* Get current link speed. */
10414         i40e_dev_link_update(dev, 1);
10415         rte_eth_linkstatus_get(dev, &link);
10416
10417         switch (link.link_speed) {
10418         case ETH_SPEED_NUM_40G:
10419                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10420                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10421                 break;
10422         case ETH_SPEED_NUM_10G:
10423                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10424                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10425                 break;
10426         case ETH_SPEED_NUM_1G:
10427                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10428                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10429                 break;
10430         default:
10431                 tsync_inc_l = 0x0;
10432                 tsync_inc_h = 0x0;
10433         }
10434
10435         /* Set the timesync increment value. */
10436         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10437         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10438
10439         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10440         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10441         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10442
10443         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10444         adapter->systime_tc.cc_shift = 0;
10445         adapter->systime_tc.nsec_mask = 0;
10446
10447         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10448         adapter->rx_tstamp_tc.cc_shift = 0;
10449         adapter->rx_tstamp_tc.nsec_mask = 0;
10450
10451         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10452         adapter->tx_tstamp_tc.cc_shift = 0;
10453         adapter->tx_tstamp_tc.nsec_mask = 0;
10454 }
10455
10456 static int
10457 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10458 {
10459         struct i40e_adapter *adapter =
10460                         (struct i40e_adapter *)dev->data->dev_private;
10461
10462         adapter->systime_tc.nsec += delta;
10463         adapter->rx_tstamp_tc.nsec += delta;
10464         adapter->tx_tstamp_tc.nsec += delta;
10465
10466         return 0;
10467 }
10468
10469 static int
10470 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10471 {
10472         uint64_t ns;
10473         struct i40e_adapter *adapter =
10474                         (struct i40e_adapter *)dev->data->dev_private;
10475
10476         ns = rte_timespec_to_ns(ts);
10477
10478         /* Set the timecounters to a new value. */
10479         adapter->systime_tc.nsec = ns;
10480         adapter->rx_tstamp_tc.nsec = ns;
10481         adapter->tx_tstamp_tc.nsec = ns;
10482
10483         return 0;
10484 }
10485
10486 static int
10487 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10488 {
10489         uint64_t ns, systime_cycles;
10490         struct i40e_adapter *adapter =
10491                         (struct i40e_adapter *)dev->data->dev_private;
10492
10493         systime_cycles = i40e_read_systime_cyclecounter(dev);
10494         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10495         *ts = rte_ns_to_timespec(ns);
10496
10497         return 0;
10498 }
10499
10500 static int
10501 i40e_timesync_enable(struct rte_eth_dev *dev)
10502 {
10503         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10504         uint32_t tsync_ctl_l;
10505         uint32_t tsync_ctl_h;
10506
10507         /* Stop the timesync system time. */
10508         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10509         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10510         /* Reset the timesync system time value. */
10511         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10512         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10513
10514         i40e_start_timecounters(dev);
10515
10516         /* Clear timesync registers. */
10517         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10518         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10519         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10520         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10521         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10522         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10523
10524         /* Enable timestamping of PTP packets. */
10525         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10526         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10527
10528         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10529         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10530         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10531
10532         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10533         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10534
10535         return 0;
10536 }
10537
10538 static int
10539 i40e_timesync_disable(struct rte_eth_dev *dev)
10540 {
10541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10542         uint32_t tsync_ctl_l;
10543         uint32_t tsync_ctl_h;
10544
10545         /* Disable timestamping of transmitted PTP packets. */
10546         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10547         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10548
10549         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10550         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10551
10552         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10553         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10554
10555         /* Reset the timesync increment value. */
10556         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10557         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10558
10559         return 0;
10560 }
10561
10562 static int
10563 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10564                                 struct timespec *timestamp, uint32_t flags)
10565 {
10566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10567         struct i40e_adapter *adapter =
10568                 (struct i40e_adapter *)dev->data->dev_private;
10569
10570         uint32_t sync_status;
10571         uint32_t index = flags & 0x03;
10572         uint64_t rx_tstamp_cycles;
10573         uint64_t ns;
10574
10575         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10576         if ((sync_status & (1 << index)) == 0)
10577                 return -EINVAL;
10578
10579         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10580         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10581         *timestamp = rte_ns_to_timespec(ns);
10582
10583         return 0;
10584 }
10585
10586 static int
10587 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10588                                 struct timespec *timestamp)
10589 {
10590         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10591         struct i40e_adapter *adapter =
10592                 (struct i40e_adapter *)dev->data->dev_private;
10593
10594         uint32_t sync_status;
10595         uint64_t tx_tstamp_cycles;
10596         uint64_t ns;
10597
10598         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10599         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10600                 return -EINVAL;
10601
10602         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10603         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10604         *timestamp = rte_ns_to_timespec(ns);
10605
10606         return 0;
10607 }
10608
10609 /*
10610  * i40e_parse_dcb_configure - parse dcb configure from user
10611  * @dev: the device being configured
10612  * @dcb_cfg: pointer of the result of parse
10613  * @*tc_map: bit map of enabled traffic classes
10614  *
10615  * Returns 0 on success, negative value on failure
10616  */
10617 static int
10618 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10619                          struct i40e_dcbx_config *dcb_cfg,
10620                          uint8_t *tc_map)
10621 {
10622         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10623         uint8_t i, tc_bw, bw_lf;
10624
10625         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10626
10627         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10628         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10629                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10630                 return -EINVAL;
10631         }
10632
10633         /* assume each tc has the same bw */
10634         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10635         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10636                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10637         /* to ensure the sum of tcbw is equal to 100 */
10638         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10639         for (i = 0; i < bw_lf; i++)
10640                 dcb_cfg->etscfg.tcbwtable[i]++;
10641
10642         /* assume each tc has the same Transmission Selection Algorithm */
10643         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10644                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10645
10646         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10647                 dcb_cfg->etscfg.prioritytable[i] =
10648                                 dcb_rx_conf->dcb_tc[i];
10649
10650         /* FW needs one App to configure HW */
10651         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10652         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10653         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10654         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10655
10656         if (dcb_rx_conf->nb_tcs == 0)
10657                 *tc_map = 1; /* tc0 only */
10658         else
10659                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10660
10661         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10662                 dcb_cfg->pfc.willing = 0;
10663                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10664                 dcb_cfg->pfc.pfcenable = *tc_map;
10665         }
10666         return 0;
10667 }
10668
10669
10670 static enum i40e_status_code
10671 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10672                               struct i40e_aqc_vsi_properties_data *info,
10673                               uint8_t enabled_tcmap)
10674 {
10675         enum i40e_status_code ret;
10676         int i, total_tc = 0;
10677         uint16_t qpnum_per_tc, bsf, qp_idx;
10678         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10679         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10680         uint16_t used_queues;
10681
10682         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10683         if (ret != I40E_SUCCESS)
10684                 return ret;
10685
10686         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10687                 if (enabled_tcmap & (1 << i))
10688                         total_tc++;
10689         }
10690         if (total_tc == 0)
10691                 total_tc = 1;
10692         vsi->enabled_tc = enabled_tcmap;
10693
10694         /* different VSI has different queues assigned */
10695         if (vsi->type == I40E_VSI_MAIN)
10696                 used_queues = dev_data->nb_rx_queues -
10697                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10698         else if (vsi->type == I40E_VSI_VMDQ2)
10699                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10700         else {
10701                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10702                 return I40E_ERR_NO_AVAILABLE_VSI;
10703         }
10704
10705         qpnum_per_tc = used_queues / total_tc;
10706         /* Number of queues per enabled TC */
10707         if (qpnum_per_tc == 0) {
10708                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10709                 return I40E_ERR_INVALID_QP_ID;
10710         }
10711         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10712                                 I40E_MAX_Q_PER_TC);
10713         bsf = rte_bsf32(qpnum_per_tc);
10714
10715         /**
10716          * Configure TC and queue mapping parameters, for enabled TC,
10717          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10718          * default queue will serve it.
10719          */
10720         qp_idx = 0;
10721         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10722                 if (vsi->enabled_tc & (1 << i)) {
10723                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10724                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10725                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10726                         qp_idx += qpnum_per_tc;
10727                 } else
10728                         info->tc_mapping[i] = 0;
10729         }
10730
10731         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10732         if (vsi->type == I40E_VSI_SRIOV) {
10733                 info->mapping_flags |=
10734                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10735                 for (i = 0; i < vsi->nb_qps; i++)
10736                         info->queue_mapping[i] =
10737                                 rte_cpu_to_le_16(vsi->base_queue + i);
10738         } else {
10739                 info->mapping_flags |=
10740                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10741                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10742         }
10743         info->valid_sections |=
10744                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10745
10746         return I40E_SUCCESS;
10747 }
10748
10749 /*
10750  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10751  * @veb: VEB to be configured
10752  * @tc_map: enabled TC bitmap
10753  *
10754  * Returns 0 on success, negative value on failure
10755  */
10756 static enum i40e_status_code
10757 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10758 {
10759         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10760         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10761         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10762         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10763         enum i40e_status_code ret = I40E_SUCCESS;
10764         int i;
10765         uint32_t bw_max;
10766
10767         /* Check if enabled_tc is same as existing or new TCs */
10768         if (veb->enabled_tc == tc_map)
10769                 return ret;
10770
10771         /* configure tc bandwidth */
10772         memset(&veb_bw, 0, sizeof(veb_bw));
10773         veb_bw.tc_valid_bits = tc_map;
10774         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10775         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10776                 if (tc_map & BIT_ULL(i))
10777                         veb_bw.tc_bw_share_credits[i] = 1;
10778         }
10779         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10780                                                    &veb_bw, NULL);
10781         if (ret) {
10782                 PMD_INIT_LOG(ERR,
10783                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10784                         hw->aq.asq_last_status);
10785                 return ret;
10786         }
10787
10788         memset(&ets_query, 0, sizeof(ets_query));
10789         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10790                                                    &ets_query, NULL);
10791         if (ret != I40E_SUCCESS) {
10792                 PMD_DRV_LOG(ERR,
10793                         "Failed to get switch_comp ETS configuration %u",
10794                         hw->aq.asq_last_status);
10795                 return ret;
10796         }
10797         memset(&bw_query, 0, sizeof(bw_query));
10798         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10799                                                   &bw_query, NULL);
10800         if (ret != I40E_SUCCESS) {
10801                 PMD_DRV_LOG(ERR,
10802                         "Failed to get switch_comp bandwidth configuration %u",
10803                         hw->aq.asq_last_status);
10804                 return ret;
10805         }
10806
10807         /* store and print out BW info */
10808         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10809         veb->bw_info.bw_max = ets_query.tc_bw_max;
10810         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10811         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10812         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10813                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10814                      I40E_16_BIT_WIDTH);
10815         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10816                 veb->bw_info.bw_ets_share_credits[i] =
10817                                 bw_query.tc_bw_share_credits[i];
10818                 veb->bw_info.bw_ets_credits[i] =
10819                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10820                 /* 4 bits per TC, 4th bit is reserved */
10821                 veb->bw_info.bw_ets_max[i] =
10822                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10823                                   RTE_LEN2MASK(3, uint8_t));
10824                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10825                             veb->bw_info.bw_ets_share_credits[i]);
10826                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10827                             veb->bw_info.bw_ets_credits[i]);
10828                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10829                             veb->bw_info.bw_ets_max[i]);
10830         }
10831
10832         veb->enabled_tc = tc_map;
10833
10834         return ret;
10835 }
10836
10837
10838 /*
10839  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10840  * @vsi: VSI to be configured
10841  * @tc_map: enabled TC bitmap
10842  *
10843  * Returns 0 on success, negative value on failure
10844  */
10845 static enum i40e_status_code
10846 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10847 {
10848         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10849         struct i40e_vsi_context ctxt;
10850         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10851         enum i40e_status_code ret = I40E_SUCCESS;
10852         int i;
10853
10854         /* Check if enabled_tc is same as existing or new TCs */
10855         if (vsi->enabled_tc == tc_map)
10856                 return ret;
10857
10858         /* configure tc bandwidth */
10859         memset(&bw_data, 0, sizeof(bw_data));
10860         bw_data.tc_valid_bits = tc_map;
10861         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10862         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10863                 if (tc_map & BIT_ULL(i))
10864                         bw_data.tc_bw_credits[i] = 1;
10865         }
10866         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10867         if (ret) {
10868                 PMD_INIT_LOG(ERR,
10869                         "AQ command Config VSI BW allocation per TC failed = %d",
10870                         hw->aq.asq_last_status);
10871                 goto out;
10872         }
10873         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10874                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10875
10876         /* Update Queue Pairs Mapping for currently enabled UPs */
10877         ctxt.seid = vsi->seid;
10878         ctxt.pf_num = hw->pf_id;
10879         ctxt.vf_num = 0;
10880         ctxt.uplink_seid = vsi->uplink_seid;
10881         ctxt.info = vsi->info;
10882         i40e_get_cap(hw);
10883         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10884         if (ret)
10885                 goto out;
10886
10887         /* Update the VSI after updating the VSI queue-mapping information */
10888         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10889         if (ret) {
10890                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10891                         hw->aq.asq_last_status);
10892                 goto out;
10893         }
10894         /* update the local VSI info with updated queue map */
10895         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10896                                         sizeof(vsi->info.tc_mapping));
10897         rte_memcpy(&vsi->info.queue_mapping,
10898                         &ctxt.info.queue_mapping,
10899                 sizeof(vsi->info.queue_mapping));
10900         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10901         vsi->info.valid_sections = 0;
10902
10903         /* query and update current VSI BW information */
10904         ret = i40e_vsi_get_bw_config(vsi);
10905         if (ret) {
10906                 PMD_INIT_LOG(ERR,
10907                          "Failed updating vsi bw info, err %s aq_err %s",
10908                          i40e_stat_str(hw, ret),
10909                          i40e_aq_str(hw, hw->aq.asq_last_status));
10910                 goto out;
10911         }
10912
10913         vsi->enabled_tc = tc_map;
10914
10915 out:
10916         return ret;
10917 }
10918
10919 /*
10920  * i40e_dcb_hw_configure - program the dcb setting to hw
10921  * @pf: pf the configuration is taken on
10922  * @new_cfg: new configuration
10923  * @tc_map: enabled TC bitmap
10924  *
10925  * Returns 0 on success, negative value on failure
10926  */
10927 static enum i40e_status_code
10928 i40e_dcb_hw_configure(struct i40e_pf *pf,
10929                       struct i40e_dcbx_config *new_cfg,
10930                       uint8_t tc_map)
10931 {
10932         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10933         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10934         struct i40e_vsi *main_vsi = pf->main_vsi;
10935         struct i40e_vsi_list *vsi_list;
10936         enum i40e_status_code ret;
10937         int i;
10938         uint32_t val;
10939
10940         /* Use the FW API if FW > v4.4*/
10941         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10942               (hw->aq.fw_maj_ver >= 5))) {
10943                 PMD_INIT_LOG(ERR,
10944                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10945                 return I40E_ERR_FIRMWARE_API_VERSION;
10946         }
10947
10948         /* Check if need reconfiguration */
10949         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10950                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10951                 return I40E_SUCCESS;
10952         }
10953
10954         /* Copy the new config to the current config */
10955         *old_cfg = *new_cfg;
10956         old_cfg->etsrec = old_cfg->etscfg;
10957         ret = i40e_set_dcb_config(hw);
10958         if (ret) {
10959                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10960                          i40e_stat_str(hw, ret),
10961                          i40e_aq_str(hw, hw->aq.asq_last_status));
10962                 return ret;
10963         }
10964         /* set receive Arbiter to RR mode and ETS scheme by default */
10965         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10966                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10967                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10968                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10969                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10970                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10971                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10972                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10973                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10974                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10975                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10976                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10977                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10978         }
10979         /* get local mib to check whether it is configured correctly */
10980         /* IEEE mode */
10981         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10982         /* Get Local DCB Config */
10983         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10984                                      &hw->local_dcbx_config);
10985
10986         /* if Veb is created, need to update TC of it at first */
10987         if (main_vsi->veb) {
10988                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10989                 if (ret)
10990                         PMD_INIT_LOG(WARNING,
10991                                  "Failed configuring TC for VEB seid=%d",
10992                                  main_vsi->veb->seid);
10993         }
10994         /* Update each VSI */
10995         i40e_vsi_config_tc(main_vsi, tc_map);
10996         if (main_vsi->veb) {
10997                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10998                         /* Beside main VSI and VMDQ VSIs, only enable default
10999                          * TC for other VSIs
11000                          */
11001                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11002                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11003                                                          tc_map);
11004                         else
11005                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11006                                                          I40E_DEFAULT_TCMAP);
11007                         if (ret)
11008                                 PMD_INIT_LOG(WARNING,
11009                                         "Failed configuring TC for VSI seid=%d",
11010                                         vsi_list->vsi->seid);
11011                         /* continue */
11012                 }
11013         }
11014         return I40E_SUCCESS;
11015 }
11016
11017 /*
11018  * i40e_dcb_init_configure - initial dcb config
11019  * @dev: device being configured
11020  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11021  *
11022  * Returns 0 on success, negative value on failure
11023  */
11024 int
11025 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11026 {
11027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11029         int i, ret = 0;
11030
11031         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11032                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11033                 return -ENOTSUP;
11034         }
11035
11036         /* DCB initialization:
11037          * Update DCB configuration from the Firmware and configure
11038          * LLDP MIB change event.
11039          */
11040         if (sw_dcb == TRUE) {
11041                 ret = i40e_init_dcb(hw);
11042                 /* If lldp agent is stopped, the return value from
11043                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11044                  * adminq status. Otherwise, it should return success.
11045                  */
11046                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11047                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11048                         memset(&hw->local_dcbx_config, 0,
11049                                 sizeof(struct i40e_dcbx_config));
11050                         /* set dcb default configuration */
11051                         hw->local_dcbx_config.etscfg.willing = 0;
11052                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11053                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11054                         hw->local_dcbx_config.etscfg.tsatable[0] =
11055                                                 I40E_IEEE_TSA_ETS;
11056                         /* all UPs mapping to TC0 */
11057                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11058                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11059                         hw->local_dcbx_config.etsrec =
11060                                 hw->local_dcbx_config.etscfg;
11061                         hw->local_dcbx_config.pfc.willing = 0;
11062                         hw->local_dcbx_config.pfc.pfccap =
11063                                                 I40E_MAX_TRAFFIC_CLASS;
11064                         /* FW needs one App to configure HW */
11065                         hw->local_dcbx_config.numapps = 1;
11066                         hw->local_dcbx_config.app[0].selector =
11067                                                 I40E_APP_SEL_ETHTYPE;
11068                         hw->local_dcbx_config.app[0].priority = 3;
11069                         hw->local_dcbx_config.app[0].protocolid =
11070                                                 I40E_APP_PROTOID_FCOE;
11071                         ret = i40e_set_dcb_config(hw);
11072                         if (ret) {
11073                                 PMD_INIT_LOG(ERR,
11074                                         "default dcb config fails. err = %d, aq_err = %d.",
11075                                         ret, hw->aq.asq_last_status);
11076                                 return -ENOSYS;
11077                         }
11078                 } else {
11079                         PMD_INIT_LOG(ERR,
11080                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11081                                 ret, hw->aq.asq_last_status);
11082                         return -ENOTSUP;
11083                 }
11084         } else {
11085                 ret = i40e_aq_start_lldp(hw, NULL);
11086                 if (ret != I40E_SUCCESS)
11087                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11088
11089                 ret = i40e_init_dcb(hw);
11090                 if (!ret) {
11091                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11092                                 PMD_INIT_LOG(ERR,
11093                                         "HW doesn't support DCBX offload.");
11094                                 return -ENOTSUP;
11095                         }
11096                 } else {
11097                         PMD_INIT_LOG(ERR,
11098                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11099                                 ret, hw->aq.asq_last_status);
11100                         return -ENOTSUP;
11101                 }
11102         }
11103         return 0;
11104 }
11105
11106 /*
11107  * i40e_dcb_setup - setup dcb related config
11108  * @dev: device being configured
11109  *
11110  * Returns 0 on success, negative value on failure
11111  */
11112 static int
11113 i40e_dcb_setup(struct rte_eth_dev *dev)
11114 {
11115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11116         struct i40e_dcbx_config dcb_cfg;
11117         uint8_t tc_map = 0;
11118         int ret = 0;
11119
11120         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11121                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11122                 return -ENOTSUP;
11123         }
11124
11125         if (pf->vf_num != 0)
11126                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11127
11128         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11129         if (ret) {
11130                 PMD_INIT_LOG(ERR, "invalid dcb config");
11131                 return -EINVAL;
11132         }
11133         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11134         if (ret) {
11135                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11136                 return -ENOSYS;
11137         }
11138
11139         return 0;
11140 }
11141
11142 static int
11143 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11144                       struct rte_eth_dcb_info *dcb_info)
11145 {
11146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11147         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11148         struct i40e_vsi *vsi = pf->main_vsi;
11149         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11150         uint16_t bsf, tc_mapping;
11151         int i, j = 0;
11152
11153         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11154                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11155         else
11156                 dcb_info->nb_tcs = 1;
11157         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11158                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11159         for (i = 0; i < dcb_info->nb_tcs; i++)
11160                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11161
11162         /* get queue mapping if vmdq is disabled */
11163         if (!pf->nb_cfg_vmdq_vsi) {
11164                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11165                         if (!(vsi->enabled_tc & (1 << i)))
11166                                 continue;
11167                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11168                         dcb_info->tc_queue.tc_rxq[j][i].base =
11169                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11170                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11171                         dcb_info->tc_queue.tc_txq[j][i].base =
11172                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11173                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11174                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11175                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11176                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11177                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11178                 }
11179                 return 0;
11180         }
11181
11182         /* get queue mapping if vmdq is enabled */
11183         do {
11184                 vsi = pf->vmdq[j].vsi;
11185                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11186                         if (!(vsi->enabled_tc & (1 << i)))
11187                                 continue;
11188                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11189                         dcb_info->tc_queue.tc_rxq[j][i].base =
11190                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11191                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11192                         dcb_info->tc_queue.tc_txq[j][i].base =
11193                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11194                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11195                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11196                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11197                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11198                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11199                 }
11200                 j++;
11201         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11202         return 0;
11203 }
11204
11205 static int
11206 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11207 {
11208         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11209         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11211         uint16_t msix_intr;
11212
11213         msix_intr = intr_handle->intr_vec[queue_id];
11214         if (msix_intr == I40E_MISC_VEC_ID)
11215                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11216                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11217                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11218                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11219         else
11220                 I40E_WRITE_REG(hw,
11221                                I40E_PFINT_DYN_CTLN(msix_intr -
11222                                                    I40E_RX_VEC_START),
11223                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11224                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11225                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11226
11227         I40E_WRITE_FLUSH(hw);
11228         rte_intr_enable(&pci_dev->intr_handle);
11229
11230         return 0;
11231 }
11232
11233 static int
11234 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11235 {
11236         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11237         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11239         uint16_t msix_intr;
11240
11241         msix_intr = intr_handle->intr_vec[queue_id];
11242         if (msix_intr == I40E_MISC_VEC_ID)
11243                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11244                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11245         else
11246                 I40E_WRITE_REG(hw,
11247                                I40E_PFINT_DYN_CTLN(msix_intr -
11248                                                    I40E_RX_VEC_START),
11249                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11250         I40E_WRITE_FLUSH(hw);
11251
11252         return 0;
11253 }
11254
11255 static int i40e_get_regs(struct rte_eth_dev *dev,
11256                          struct rte_dev_reg_info *regs)
11257 {
11258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11259         uint32_t *ptr_data = regs->data;
11260         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11261         const struct i40e_reg_info *reg_info;
11262
11263         if (ptr_data == NULL) {
11264                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11265                 regs->width = sizeof(uint32_t);
11266                 return 0;
11267         }
11268
11269         /* The first few registers have to be read using AQ operations */
11270         reg_idx = 0;
11271         while (i40e_regs_adminq[reg_idx].name) {
11272                 reg_info = &i40e_regs_adminq[reg_idx++];
11273                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11274                         for (arr_idx2 = 0;
11275                                         arr_idx2 <= reg_info->count2;
11276                                         arr_idx2++) {
11277                                 reg_offset = arr_idx * reg_info->stride1 +
11278                                         arr_idx2 * reg_info->stride2;
11279                                 reg_offset += reg_info->base_addr;
11280                                 ptr_data[reg_offset >> 2] =
11281                                         i40e_read_rx_ctl(hw, reg_offset);
11282                         }
11283         }
11284
11285         /* The remaining registers can be read using primitives */
11286         reg_idx = 0;
11287         while (i40e_regs_others[reg_idx].name) {
11288                 reg_info = &i40e_regs_others[reg_idx++];
11289                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11290                         for (arr_idx2 = 0;
11291                                         arr_idx2 <= reg_info->count2;
11292                                         arr_idx2++) {
11293                                 reg_offset = arr_idx * reg_info->stride1 +
11294                                         arr_idx2 * reg_info->stride2;
11295                                 reg_offset += reg_info->base_addr;
11296                                 ptr_data[reg_offset >> 2] =
11297                                         I40E_READ_REG(hw, reg_offset);
11298                         }
11299         }
11300
11301         return 0;
11302 }
11303
11304 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11305 {
11306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11307
11308         /* Convert word count to byte count */
11309         return hw->nvm.sr_size << 1;
11310 }
11311
11312 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11313                            struct rte_dev_eeprom_info *eeprom)
11314 {
11315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11316         uint16_t *data = eeprom->data;
11317         uint16_t offset, length, cnt_words;
11318         int ret_code;
11319
11320         offset = eeprom->offset >> 1;
11321         length = eeprom->length >> 1;
11322         cnt_words = length;
11323
11324         if (offset > hw->nvm.sr_size ||
11325                 offset + length > hw->nvm.sr_size) {
11326                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11327                 return -EINVAL;
11328         }
11329
11330         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11331
11332         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11333         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11334                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11335                 return -EIO;
11336         }
11337
11338         return 0;
11339 }
11340
11341 static int i40e_get_module_info(struct rte_eth_dev *dev,
11342                                 struct rte_eth_dev_module_info *modinfo)
11343 {
11344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11345         uint32_t sff8472_comp = 0;
11346         uint32_t sff8472_swap = 0;
11347         uint32_t sff8636_rev = 0;
11348         i40e_status status;
11349         uint32_t type = 0;
11350
11351         /* Check if firmware supports reading module EEPROM. */
11352         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11353                 PMD_DRV_LOG(ERR,
11354                             "Module EEPROM memory read not supported. "
11355                             "Please update the NVM image.\n");
11356                 return -EINVAL;
11357         }
11358
11359         status = i40e_update_link_info(hw);
11360         if (status)
11361                 return -EIO;
11362
11363         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11364                 PMD_DRV_LOG(ERR,
11365                             "Cannot read module EEPROM memory. "
11366                             "No module connected.\n");
11367                 return -EINVAL;
11368         }
11369
11370         type = hw->phy.link_info.module_type[0];
11371
11372         switch (type) {
11373         case I40E_MODULE_TYPE_SFP:
11374                 status = i40e_aq_get_phy_register(hw,
11375                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11376                                 I40E_I2C_EEPROM_DEV_ADDR,
11377                                 I40E_MODULE_SFF_8472_COMP,
11378                                 &sff8472_comp, NULL);
11379                 if (status)
11380                         return -EIO;
11381
11382                 status = i40e_aq_get_phy_register(hw,
11383                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11384                                 I40E_I2C_EEPROM_DEV_ADDR,
11385                                 I40E_MODULE_SFF_8472_SWAP,
11386                                 &sff8472_swap, NULL);
11387                 if (status)
11388                         return -EIO;
11389
11390                 /* Check if the module requires address swap to access
11391                  * the other EEPROM memory page.
11392                  */
11393                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11394                         PMD_DRV_LOG(WARNING,
11395                                     "Module address swap to access "
11396                                     "page 0xA2 is not supported.\n");
11397                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11398                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11399                 } else if (sff8472_comp == 0x00) {
11400                         /* Module is not SFF-8472 compliant */
11401                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11402                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11403                 } else {
11404                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11405                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11406                 }
11407                 break;
11408         case I40E_MODULE_TYPE_QSFP_PLUS:
11409                 /* Read from memory page 0. */
11410                 status = i40e_aq_get_phy_register(hw,
11411                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11412                                 0,
11413                                 I40E_MODULE_REVISION_ADDR,
11414                                 &sff8636_rev, NULL);
11415                 if (status)
11416                         return -EIO;
11417                 /* Determine revision compliance byte */
11418                 if (sff8636_rev > 0x02) {
11419                         /* Module is SFF-8636 compliant */
11420                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11421                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11422                 } else {
11423                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11424                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11425                 }
11426                 break;
11427         case I40E_MODULE_TYPE_QSFP28:
11428                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11429                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11430                 break;
11431         default:
11432                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11433                 return -EINVAL;
11434         }
11435         return 0;
11436 }
11437
11438 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11439                                   struct rte_dev_eeprom_info *info)
11440 {
11441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11442         bool is_sfp = false;
11443         i40e_status status;
11444         uint8_t *data = info->data;
11445         uint32_t value = 0;
11446         uint32_t i;
11447
11448         if (!info || !info->length || !data)
11449                 return -EINVAL;
11450
11451         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11452                 is_sfp = true;
11453
11454         for (i = 0; i < info->length; i++) {
11455                 u32 offset = i + info->offset;
11456                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11457
11458                 /* Check if we need to access the other memory page */
11459                 if (is_sfp) {
11460                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11461                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11462                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11463                         }
11464                 } else {
11465                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11466                                 /* Compute memory page number and offset. */
11467                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11468                                 addr++;
11469                         }
11470                 }
11471                 status = i40e_aq_get_phy_register(hw,
11472                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11473                                 addr, offset, &value, NULL);
11474                 if (status)
11475                         return -EIO;
11476                 data[i] = (uint8_t)value;
11477         }
11478         return 0;
11479 }
11480
11481 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11482                                      struct ether_addr *mac_addr)
11483 {
11484         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11486         struct i40e_vsi *vsi = pf->main_vsi;
11487         struct i40e_mac_filter_info mac_filter;
11488         struct i40e_mac_filter *f;
11489         int ret;
11490
11491         if (!is_valid_assigned_ether_addr(mac_addr)) {
11492                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11493                 return -EINVAL;
11494         }
11495
11496         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11497                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11498                         break;
11499         }
11500
11501         if (f == NULL) {
11502                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11503                 return -EIO;
11504         }
11505
11506         mac_filter = f->mac_info;
11507         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11508         if (ret != I40E_SUCCESS) {
11509                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11510                 return -EIO;
11511         }
11512         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11513         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11514         if (ret != I40E_SUCCESS) {
11515                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11516                 return -EIO;
11517         }
11518         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11519
11520         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11521                                         mac_addr->addr_bytes, NULL);
11522         if (ret != I40E_SUCCESS) {
11523                 PMD_DRV_LOG(ERR, "Failed to change mac");
11524                 return -EIO;
11525         }
11526
11527         return 0;
11528 }
11529
11530 static int
11531 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11532 {
11533         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11534         struct rte_eth_dev_data *dev_data = pf->dev_data;
11535         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11536         int ret = 0;
11537
11538         /* check if mtu is within the allowed range */
11539         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11540                 return -EINVAL;
11541
11542         /* mtu setting is forbidden if port is start */
11543         if (dev_data->dev_started) {
11544                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11545                             dev_data->port_id);
11546                 return -EBUSY;
11547         }
11548
11549         if (frame_size > ETHER_MAX_LEN)
11550                 dev_data->dev_conf.rxmode.offloads |=
11551                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11552         else
11553                 dev_data->dev_conf.rxmode.offloads &=
11554                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11555
11556         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11557
11558         return ret;
11559 }
11560
11561 /* Restore ethertype filter */
11562 static void
11563 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11564 {
11565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11566         struct i40e_ethertype_filter_list
11567                 *ethertype_list = &pf->ethertype.ethertype_list;
11568         struct i40e_ethertype_filter *f;
11569         struct i40e_control_filter_stats stats;
11570         uint16_t flags;
11571
11572         TAILQ_FOREACH(f, ethertype_list, rules) {
11573                 flags = 0;
11574                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11575                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11576                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11577                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11578                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11579
11580                 memset(&stats, 0, sizeof(stats));
11581                 i40e_aq_add_rem_control_packet_filter(hw,
11582                                             f->input.mac_addr.addr_bytes,
11583                                             f->input.ether_type,
11584                                             flags, pf->main_vsi->seid,
11585                                             f->queue, 1, &stats, NULL);
11586         }
11587         PMD_DRV_LOG(INFO, "Ethertype filter:"
11588                     " mac_etype_used = %u, etype_used = %u,"
11589                     " mac_etype_free = %u, etype_free = %u",
11590                     stats.mac_etype_used, stats.etype_used,
11591                     stats.mac_etype_free, stats.etype_free);
11592 }
11593
11594 /* Restore tunnel filter */
11595 static void
11596 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11597 {
11598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11599         struct i40e_vsi *vsi;
11600         struct i40e_pf_vf *vf;
11601         struct i40e_tunnel_filter_list
11602                 *tunnel_list = &pf->tunnel.tunnel_list;
11603         struct i40e_tunnel_filter *f;
11604         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11605         bool big_buffer = 0;
11606
11607         TAILQ_FOREACH(f, tunnel_list, rules) {
11608                 if (!f->is_to_vf)
11609                         vsi = pf->main_vsi;
11610                 else {
11611                         vf = &pf->vfs[f->vf_id];
11612                         vsi = vf->vsi;
11613                 }
11614                 memset(&cld_filter, 0, sizeof(cld_filter));
11615                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11616                         (struct ether_addr *)&cld_filter.element.outer_mac);
11617                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11618                         (struct ether_addr *)&cld_filter.element.inner_mac);
11619                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11620                 cld_filter.element.flags = f->input.flags;
11621                 cld_filter.element.tenant_id = f->input.tenant_id;
11622                 cld_filter.element.queue_number = f->queue;
11623                 rte_memcpy(cld_filter.general_fields,
11624                            f->input.general_fields,
11625                            sizeof(f->input.general_fields));
11626
11627                 if (((f->input.flags &
11628                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11629                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11630                     ((f->input.flags &
11631                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11632                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11633                     ((f->input.flags &
11634                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11635                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11636                         big_buffer = 1;
11637
11638                 if (big_buffer)
11639                         i40e_aq_add_cloud_filters_big_buffer(hw,
11640                                              vsi->seid, &cld_filter, 1);
11641                 else
11642                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11643                                                   &cld_filter.element, 1);
11644         }
11645 }
11646
11647 /* Restore rss filter */
11648 static inline void
11649 i40e_rss_filter_restore(struct i40e_pf *pf)
11650 {
11651         struct i40e_rte_flow_rss_conf *conf =
11652                                         &pf->rss_info;
11653         if (conf->num)
11654                 i40e_config_rss_filter(pf, conf, TRUE);
11655 }
11656
11657 static void
11658 i40e_filter_restore(struct i40e_pf *pf)
11659 {
11660         i40e_ethertype_filter_restore(pf);
11661         i40e_tunnel_filter_restore(pf);
11662         i40e_fdir_filter_restore(pf);
11663         i40e_rss_filter_restore(pf);
11664 }
11665
11666 static bool
11667 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11668 {
11669         if (strcmp(dev->device->driver->name, drv->driver.name))
11670                 return false;
11671
11672         return true;
11673 }
11674
11675 bool
11676 is_i40e_supported(struct rte_eth_dev *dev)
11677 {
11678         return is_device_supported(dev, &rte_i40e_pmd);
11679 }
11680
11681 struct i40e_customized_pctype*
11682 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11683 {
11684         int i;
11685
11686         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11687                 if (pf->customized_pctype[i].index == index)
11688                         return &pf->customized_pctype[i];
11689         }
11690         return NULL;
11691 }
11692
11693 static int
11694 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11695                               uint32_t pkg_size, uint32_t proto_num,
11696                               struct rte_pmd_i40e_proto_info *proto,
11697                               enum rte_pmd_i40e_package_op op)
11698 {
11699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11700         uint32_t pctype_num;
11701         struct rte_pmd_i40e_ptype_info *pctype;
11702         uint32_t buff_size;
11703         struct i40e_customized_pctype *new_pctype = NULL;
11704         uint8_t proto_id;
11705         uint8_t pctype_value;
11706         char name[64];
11707         uint32_t i, j, n;
11708         int ret;
11709
11710         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11711             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11712                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11713                 return -1;
11714         }
11715
11716         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11717                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11718                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11719         if (ret) {
11720                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11721                 return -1;
11722         }
11723         if (!pctype_num) {
11724                 PMD_DRV_LOG(INFO, "No new pctype added");
11725                 return -1;
11726         }
11727
11728         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11729         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11730         if (!pctype) {
11731                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11732                 return -1;
11733         }
11734         /* get information about new pctype list */
11735         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11736                                         (uint8_t *)pctype, buff_size,
11737                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11738         if (ret) {
11739                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11740                 rte_free(pctype);
11741                 return -1;
11742         }
11743
11744         /* Update customized pctype. */
11745         for (i = 0; i < pctype_num; i++) {
11746                 pctype_value = pctype[i].ptype_id;
11747                 memset(name, 0, sizeof(name));
11748                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11749                         proto_id = pctype[i].protocols[j];
11750                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11751                                 continue;
11752                         for (n = 0; n < proto_num; n++) {
11753                                 if (proto[n].proto_id != proto_id)
11754                                         continue;
11755                                 strcat(name, proto[n].name);
11756                                 strcat(name, "_");
11757                                 break;
11758                         }
11759                 }
11760                 name[strlen(name) - 1] = '\0';
11761                 if (!strcmp(name, "GTPC"))
11762                         new_pctype =
11763                                 i40e_find_customized_pctype(pf,
11764                                                       I40E_CUSTOMIZED_GTPC);
11765                 else if (!strcmp(name, "GTPU_IPV4"))
11766                         new_pctype =
11767                                 i40e_find_customized_pctype(pf,
11768                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11769                 else if (!strcmp(name, "GTPU_IPV6"))
11770                         new_pctype =
11771                                 i40e_find_customized_pctype(pf,
11772                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11773                 else if (!strcmp(name, "GTPU"))
11774                         new_pctype =
11775                                 i40e_find_customized_pctype(pf,
11776                                                       I40E_CUSTOMIZED_GTPU);
11777                 if (new_pctype) {
11778                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11779                                 new_pctype->pctype = pctype_value;
11780                                 new_pctype->valid = true;
11781                         } else {
11782                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11783                                 new_pctype->valid = false;
11784                         }
11785                 }
11786         }
11787
11788         rte_free(pctype);
11789         return 0;
11790 }
11791
11792 static int
11793 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11794                              uint32_t pkg_size, uint32_t proto_num,
11795                              struct rte_pmd_i40e_proto_info *proto,
11796                              enum rte_pmd_i40e_package_op op)
11797 {
11798         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11799         uint16_t port_id = dev->data->port_id;
11800         uint32_t ptype_num;
11801         struct rte_pmd_i40e_ptype_info *ptype;
11802         uint32_t buff_size;
11803         uint8_t proto_id;
11804         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11805         uint32_t i, j, n;
11806         bool in_tunnel;
11807         int ret;
11808
11809         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11810             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11811                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11812                 return -1;
11813         }
11814
11815         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11816                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11817                 return 0;
11818         }
11819
11820         /* get information about new ptype num */
11821         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11822                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11823                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11824         if (ret) {
11825                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11826                 return ret;
11827         }
11828         if (!ptype_num) {
11829                 PMD_DRV_LOG(INFO, "No new ptype added");
11830                 return -1;
11831         }
11832
11833         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11834         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11835         if (!ptype) {
11836                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11837                 return -1;
11838         }
11839
11840         /* get information about new ptype list */
11841         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11842                                         (uint8_t *)ptype, buff_size,
11843                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11844         if (ret) {
11845                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11846                 rte_free(ptype);
11847                 return ret;
11848         }
11849
11850         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11851         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11852         if (!ptype_mapping) {
11853                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11854                 rte_free(ptype);
11855                 return -1;
11856         }
11857
11858         /* Update ptype mapping table. */
11859         for (i = 0; i < ptype_num; i++) {
11860                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11861                 ptype_mapping[i].sw_ptype = 0;
11862                 in_tunnel = false;
11863                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11864                         proto_id = ptype[i].protocols[j];
11865                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11866                                 continue;
11867                         for (n = 0; n < proto_num; n++) {
11868                                 if (proto[n].proto_id != proto_id)
11869                                         continue;
11870                                 memset(name, 0, sizeof(name));
11871                                 strcpy(name, proto[n].name);
11872                                 if (!strncasecmp(name, "PPPOE", 5))
11873                                         ptype_mapping[i].sw_ptype |=
11874                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11875                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11876                                          !in_tunnel) {
11877                                         ptype_mapping[i].sw_ptype |=
11878                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11879                                         ptype_mapping[i].sw_ptype |=
11880                                                 RTE_PTYPE_L4_FRAG;
11881                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11882                                            in_tunnel) {
11883                                         ptype_mapping[i].sw_ptype |=
11884                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11885                                         ptype_mapping[i].sw_ptype |=
11886                                                 RTE_PTYPE_INNER_L4_FRAG;
11887                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11888                                         ptype_mapping[i].sw_ptype |=
11889                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11890                                         in_tunnel = true;
11891                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11892                                            !in_tunnel)
11893                                         ptype_mapping[i].sw_ptype |=
11894                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11895                                 else if (!strncasecmp(name, "IPV4", 4) &&
11896                                          in_tunnel)
11897                                         ptype_mapping[i].sw_ptype |=
11898                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11899                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11900                                          !in_tunnel) {
11901                                         ptype_mapping[i].sw_ptype |=
11902                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11903                                         ptype_mapping[i].sw_ptype |=
11904                                                 RTE_PTYPE_L4_FRAG;
11905                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11906                                            in_tunnel) {
11907                                         ptype_mapping[i].sw_ptype |=
11908                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11909                                         ptype_mapping[i].sw_ptype |=
11910                                                 RTE_PTYPE_INNER_L4_FRAG;
11911                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11912                                         ptype_mapping[i].sw_ptype |=
11913                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11914                                         in_tunnel = true;
11915                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11916                                            !in_tunnel)
11917                                         ptype_mapping[i].sw_ptype |=
11918                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11919                                 else if (!strncasecmp(name, "IPV6", 4) &&
11920                                          in_tunnel)
11921                                         ptype_mapping[i].sw_ptype |=
11922                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11923                                 else if (!strncasecmp(name, "UDP", 3) &&
11924                                          !in_tunnel)
11925                                         ptype_mapping[i].sw_ptype |=
11926                                                 RTE_PTYPE_L4_UDP;
11927                                 else if (!strncasecmp(name, "UDP", 3) &&
11928                                          in_tunnel)
11929                                         ptype_mapping[i].sw_ptype |=
11930                                                 RTE_PTYPE_INNER_L4_UDP;
11931                                 else if (!strncasecmp(name, "TCP", 3) &&
11932                                          !in_tunnel)
11933                                         ptype_mapping[i].sw_ptype |=
11934                                                 RTE_PTYPE_L4_TCP;
11935                                 else if (!strncasecmp(name, "TCP", 3) &&
11936                                          in_tunnel)
11937                                         ptype_mapping[i].sw_ptype |=
11938                                                 RTE_PTYPE_INNER_L4_TCP;
11939                                 else if (!strncasecmp(name, "SCTP", 4) &&
11940                                          !in_tunnel)
11941                                         ptype_mapping[i].sw_ptype |=
11942                                                 RTE_PTYPE_L4_SCTP;
11943                                 else if (!strncasecmp(name, "SCTP", 4) &&
11944                                          in_tunnel)
11945                                         ptype_mapping[i].sw_ptype |=
11946                                                 RTE_PTYPE_INNER_L4_SCTP;
11947                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11948                                           !strncasecmp(name, "ICMPV6", 6)) &&
11949                                          !in_tunnel)
11950                                         ptype_mapping[i].sw_ptype |=
11951                                                 RTE_PTYPE_L4_ICMP;
11952                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11953                                           !strncasecmp(name, "ICMPV6", 6)) &&
11954                                          in_tunnel)
11955                                         ptype_mapping[i].sw_ptype |=
11956                                                 RTE_PTYPE_INNER_L4_ICMP;
11957                                 else if (!strncasecmp(name, "GTPC", 4)) {
11958                                         ptype_mapping[i].sw_ptype |=
11959                                                 RTE_PTYPE_TUNNEL_GTPC;
11960                                         in_tunnel = true;
11961                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11962                                         ptype_mapping[i].sw_ptype |=
11963                                                 RTE_PTYPE_TUNNEL_GTPU;
11964                                         in_tunnel = true;
11965                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11966                                         ptype_mapping[i].sw_ptype |=
11967                                                 RTE_PTYPE_TUNNEL_GRENAT;
11968                                         in_tunnel = true;
11969                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11970                                         ptype_mapping[i].sw_ptype |=
11971                                                 RTE_PTYPE_TUNNEL_L2TP;
11972                                         in_tunnel = true;
11973                                 }
11974
11975                                 break;
11976                         }
11977                 }
11978         }
11979
11980         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11981                                                 ptype_num, 0);
11982         if (ret)
11983                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11984
11985         rte_free(ptype_mapping);
11986         rte_free(ptype);
11987         return ret;
11988 }
11989
11990 void
11991 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11992                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11993 {
11994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11995         uint32_t proto_num;
11996         struct rte_pmd_i40e_proto_info *proto;
11997         uint32_t buff_size;
11998         uint32_t i;
11999         int ret;
12000
12001         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12002             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12003                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12004                 return;
12005         }
12006
12007         /* get information about protocol number */
12008         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12009                                        (uint8_t *)&proto_num, sizeof(proto_num),
12010                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12011         if (ret) {
12012                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12013                 return;
12014         }
12015         if (!proto_num) {
12016                 PMD_DRV_LOG(INFO, "No new protocol added");
12017                 return;
12018         }
12019
12020         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12021         proto = rte_zmalloc("new_proto", buff_size, 0);
12022         if (!proto) {
12023                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12024                 return;
12025         }
12026
12027         /* get information about protocol list */
12028         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12029                                         (uint8_t *)proto, buff_size,
12030                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12031         if (ret) {
12032                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12033                 rte_free(proto);
12034                 return;
12035         }
12036
12037         /* Check if GTP is supported. */
12038         for (i = 0; i < proto_num; i++) {
12039                 if (!strncmp(proto[i].name, "GTP", 3)) {
12040                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12041                                 pf->gtp_support = true;
12042                         else
12043                                 pf->gtp_support = false;
12044                         break;
12045                 }
12046         }
12047
12048         /* Update customized pctype info */
12049         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12050                                             proto_num, proto, op);
12051         if (ret)
12052                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12053
12054         /* Update customized ptype info */
12055         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12056                                            proto_num, proto, op);
12057         if (ret)
12058                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12059
12060         rte_free(proto);
12061 }
12062
12063 /* Create a QinQ cloud filter
12064  *
12065  * The Fortville NIC has limited resources for tunnel filters,
12066  * so we can only reuse existing filters.
12067  *
12068  * In step 1 we define which Field Vector fields can be used for
12069  * filter types.
12070  * As we do not have the inner tag defined as a field,
12071  * we have to define it first, by reusing one of L1 entries.
12072  *
12073  * In step 2 we are replacing one of existing filter types with
12074  * a new one for QinQ.
12075  * As we reusing L1 and replacing L2, some of the default filter
12076  * types will disappear,which depends on L1 and L2 entries we reuse.
12077  *
12078  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12079  *
12080  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12081  *              later when we define the cloud filter.
12082  *      a.      Valid_flags.replace_cloud = 0
12083  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12084  *      c.      New_filter = 0x10
12085  *      d.      TR bit = 0xff (optional, not used here)
12086  *      e.      Buffer – 2 entries:
12087  *              i.      Byte 0 = 8 (outer vlan FV index).
12088  *                      Byte 1 = 0 (rsv)
12089  *                      Byte 2-3 = 0x0fff
12090  *              ii.     Byte 0 = 37 (inner vlan FV index).
12091  *                      Byte 1 =0 (rsv)
12092  *                      Byte 2-3 = 0x0fff
12093  *
12094  * Step 2:
12095  * 2.   Create cloud filter using two L1 filters entries: stag and
12096  *              new filter(outer vlan+ inner vlan)
12097  *      a.      Valid_flags.replace_cloud = 1
12098  *      b.      Old_filter = 1 (instead of outer IP)
12099  *      c.      New_filter = 0x10
12100  *      d.      Buffer – 2 entries:
12101  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12102  *                      Byte 1-3 = 0 (rsv)
12103  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12104  *                      Byte 9-11 = 0 (rsv)
12105  */
12106 static int
12107 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12108 {
12109         int ret = -ENOTSUP;
12110         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12111         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12113
12114         if (pf->support_multi_driver) {
12115                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12116                 return ret;
12117         }
12118
12119         /* Init */
12120         memset(&filter_replace, 0,
12121                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12122         memset(&filter_replace_buf, 0,
12123                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12124
12125         /* create L1 filter */
12126         filter_replace.old_filter_type =
12127                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12128         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12129         filter_replace.tr_bit = 0;
12130
12131         /* Prepare the buffer, 2 entries */
12132         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12133         filter_replace_buf.data[0] |=
12134                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12135         /* Field Vector 12b mask */
12136         filter_replace_buf.data[2] = 0xff;
12137         filter_replace_buf.data[3] = 0x0f;
12138         filter_replace_buf.data[4] =
12139                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12140         filter_replace_buf.data[4] |=
12141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12142         /* Field Vector 12b mask */
12143         filter_replace_buf.data[6] = 0xff;
12144         filter_replace_buf.data[7] = 0x0f;
12145         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12146                         &filter_replace_buf);
12147         if (ret != I40E_SUCCESS)
12148                 return ret;
12149         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12150                     "cloud l1 type is changed from 0x%x to 0x%x",
12151                     filter_replace.old_filter_type,
12152                     filter_replace.new_filter_type);
12153
12154         /* Apply the second L2 cloud filter */
12155         memset(&filter_replace, 0,
12156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12157         memset(&filter_replace_buf, 0,
12158                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12159
12160         /* create L2 filter, input for L2 filter will be L1 filter  */
12161         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12162         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12163         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12164
12165         /* Prepare the buffer, 2 entries */
12166         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12167         filter_replace_buf.data[0] |=
12168                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12169         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12170         filter_replace_buf.data[4] |=
12171                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12172         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12173                         &filter_replace_buf);
12174         if (!ret) {
12175                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12176                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12177                             "cloud filter type is changed from 0x%x to 0x%x",
12178                             filter_replace.old_filter_type,
12179                             filter_replace.new_filter_type);
12180         }
12181         return ret;
12182 }
12183
12184 int
12185 i40e_config_rss_filter(struct i40e_pf *pf,
12186                 struct i40e_rte_flow_rss_conf *conf, bool add)
12187 {
12188         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12189         uint32_t i, lut = 0;
12190         uint16_t j, num;
12191         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
12192         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12193
12194         if (!add) {
12195                 if (memcmp(conf, rss_info,
12196                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
12197                         i40e_pf_disable_rss(pf);
12198                         memset(rss_info, 0,
12199                                 sizeof(struct i40e_rte_flow_rss_conf));
12200                         return 0;
12201                 }
12202                 return -EINVAL;
12203         }
12204
12205         if (rss_info->num)
12206                 return -EINVAL;
12207
12208         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12209          * It's necessary to calculate the actual PF queues that are configured.
12210          */
12211         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12212                 num = i40e_pf_calc_configured_queues_num(pf);
12213         else
12214                 num = pf->dev_data->nb_rx_queues;
12215
12216         num = RTE_MIN(num, conf->num);
12217         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12218                         num);
12219
12220         if (num == 0) {
12221                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12222                 return -ENOTSUP;
12223         }
12224
12225         /* Fill in redirection table */
12226         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12227                 if (j == num)
12228                         j = 0;
12229                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
12230                         hw->func_caps.rss_table_entry_width) - 1));
12231                 if ((i & 3) == 3)
12232                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12233         }
12234
12235         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12236                 i40e_pf_disable_rss(pf);
12237                 return 0;
12238         }
12239         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12240                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12241                 /* Random default keys */
12242                 static uint32_t rss_key_default[] = {0x6b793944,
12243                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12244                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12245                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12246
12247                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12248                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12249                                                         sizeof(uint32_t);
12250         }
12251
12252         i40e_hw_rss_hash_set(pf, &rss_conf);
12253
12254         rte_memcpy(rss_info,
12255                 conf, sizeof(struct i40e_rte_flow_rss_conf));
12256
12257         return 0;
12258 }
12259
12260 RTE_INIT(i40e_init_log);
12261 static void
12262 i40e_init_log(void)
12263 {
12264         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12265         if (i40e_logtype_init >= 0)
12266                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12267         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12268         if (i40e_logtype_driver >= 0)
12269                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12270 }
12271
12272 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12273                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12274                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");