drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "i40e_ethdev.h"
  59 #include "i40e_rxtx.h"
  60 #include "i40e_pf.h"
  61
  62 /* Maximun number of MAC addresses */
  63 #define I40E_NUM_MACADDR_MAX       64
  64 #define I40E_CLEAR_PXE_WAIT_MS     200
  65
  66 /* Maximun number of capability elements */
  67 #define I40E_MAX_CAP_ELE_NUM       128
  68
  69 /* Wait count and inteval */
  70 #define I40E_CHK_Q_ENA_COUNT       1000
  71 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  72
  73 /* Maximun number of VSI */
  74 #define I40E_MAX_NUM_VSIS          (384UL)
  75
  76 /* Default queue interrupt throttling time in microseconds */
  77 #define I40E_ITR_INDEX_DEFAULT          0
  78 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  79 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 110 static int i40e_dev_configure(struct rte_eth_dev *dev);
 111 static int i40e_dev_start(struct rte_eth_dev *dev);
 112 static void i40e_dev_stop(struct rte_eth_dev *dev);
 113 static void i40e_dev_close(struct rte_eth_dev *dev);
 114 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 115 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 116 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 117 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 118 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 119 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 120 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 121                                struct rte_eth_stats *stats);
 122 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 123 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 124                                             uint16_t queue_id,
 125                                             uint8_t stat_idx,
 126                                             uint8_t is_rx);
 127 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 128                               struct rte_eth_dev_info *dev_info);
 129 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 130                                 uint16_t vlan_id,
 131                                 int on);
 132 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 133 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 134 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 135                                       uint16_t queue,
 136                                       int on);
 137 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 138 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 139 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 140 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 141                               struct rte_eth_fc_conf *fc_conf);
 142 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 143                                        struct rte_eth_pfc_conf *pfc_conf);
 144 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 145                           struct ether_addr *mac_addr,
 146                           uint32_t index,
 147                           uint32_t pool);
 148 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 149 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 150                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 151                                     uint16_t reta_size);
 152 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 153                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 154                                    uint16_t reta_size);
 155
 156 static int i40e_get_cap(struct i40e_hw *hw);
 157 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 158 static int i40e_pf_setup(struct i40e_pf *pf);
 159 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 160 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 161 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 162                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 163 static void i40e_stat_update_48(struct i40e_hw *hw,
 164                                uint32_t hireg,
 165                                uint32_t loreg,
 166                                bool offset_loaded,
 167                                uint64_t *offset,
 168                                uint64_t *stat);
 169 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 170 static void i40e_dev_interrupt_handler(
 171                 __rte_unused struct rte_intr_handle *handle, void *param);
 172 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 173                                 uint32_t base, uint32_t num);
 174 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 175 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 176                         uint32_t base);
 177 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 178                         uint16_t num);
 179 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 180 static int i40e_veb_release(struct i40e_veb *veb);
 181 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 182                                                 struct i40e_vsi *vsi);
 183 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 184 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 185 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 186                                              struct i40e_macvlan_filter *mv_f,
 187                                              int num,
 188                                              struct ether_addr *addr);
 189 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 190                                              struct i40e_macvlan_filter *mv_f,
 191                                              int num,
 192                                              uint16_t vlan);
 193 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 194 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 195                                     struct rte_eth_rss_conf *rss_conf);
 196 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 197                                       struct rte_eth_rss_conf *rss_conf);
 198 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 199                                 struct rte_eth_udp_tunnel *udp_tunnel);
 200 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 201                                 struct rte_eth_udp_tunnel *udp_tunnel);
 202 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 203                         struct rte_eth_ethertype_filter *filter,
 204                         bool add);
 205 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 206                                 enum rte_filter_op filter_op,
 207                                 void *arg);
 208 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 209                                 enum rte_filter_type filter_type,
 210                                 enum rte_filter_op filter_op,
 211                                 void *arg);
 212 static void i40e_configure_registers(struct i40e_hw *hw);
 213 static void i40e_hw_init(struct i40e_hw *hw);
 214 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 215 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 216                         struct rte_eth_mirror_conf *mirror_conf,
 217                         uint8_t sw_id, uint8_t on);
 218 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 219
 220 static const struct rte_pci_id pci_id_i40e_map[] = {
 221 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 222 #include "rte_pci_dev_ids.h"
 223 { .vendor_id = 0, /* sentinel */ },
 224 };
 225
 226 static const struct eth_dev_ops i40e_eth_dev_ops = {
 227         .dev_configure                = i40e_dev_configure,
 228         .dev_start                    = i40e_dev_start,
 229         .dev_stop                     = i40e_dev_stop,
 230         .dev_close                    = i40e_dev_close,
 231         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 232         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 233         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 234         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 235         .dev_set_link_up              = i40e_dev_set_link_up,
 236         .dev_set_link_down            = i40e_dev_set_link_down,
 237         .link_update                  = i40e_dev_link_update,
 238         .stats_get                    = i40e_dev_stats_get,
 239         .stats_reset                  = i40e_dev_stats_reset,
 240         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 241         .dev_infos_get                = i40e_dev_info_get,
 242         .vlan_filter_set              = i40e_vlan_filter_set,
 243         .vlan_tpid_set                = i40e_vlan_tpid_set,
 244         .vlan_offload_set             = i40e_vlan_offload_set,
 245         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 246         .vlan_pvid_set                = i40e_vlan_pvid_set,
 247         .rx_queue_start               = i40e_dev_rx_queue_start,
 248         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 249         .tx_queue_start               = i40e_dev_tx_queue_start,
 250         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 251         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 252         .rx_queue_release             = i40e_dev_rx_queue_release,
 253         .rx_queue_count               = i40e_dev_rx_queue_count,
 254         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 255         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 256         .tx_queue_release             = i40e_dev_tx_queue_release,
 257         .dev_led_on                   = i40e_dev_led_on,
 258         .dev_led_off                  = i40e_dev_led_off,
 259         .flow_ctrl_set                = i40e_flow_ctrl_set,
 260         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 261         .mac_addr_add                 = i40e_macaddr_add,
 262         .mac_addr_remove              = i40e_macaddr_remove,
 263         .reta_update                  = i40e_dev_rss_reta_update,
 264         .reta_query                   = i40e_dev_rss_reta_query,
 265         .rss_hash_update              = i40e_dev_rss_hash_update,
 266         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 267         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 268         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 269         .filter_ctrl                  = i40e_dev_filter_ctrl,
 270         .mirror_rule_set              = i40e_mirror_rule_set,
 271         .mirror_rule_reset            = i40e_mirror_rule_reset,
 272 };
 273
 274 static struct eth_driver rte_i40e_pmd = {
 275         .pci_drv = {
 276                 .name = "rte_i40e_pmd",
 277                 .id_table = pci_id_i40e_map,
 278                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 279         },
 280         .eth_dev_init = eth_i40e_dev_init,
 281         .dev_private_size = sizeof(struct i40e_adapter),
 282 };
 283
 284 static inline int
 285 i40e_align_floor(int n)
 286 {
 287         if (n == 0)
 288                 return 0;
 289         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 290 }
 291
 292 static inline int
 293 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 294                                      struct rte_eth_link *link)
 295 {
 296         struct rte_eth_link *dst = link;
 297         struct rte_eth_link *src = &(dev->data->dev_link);
 298
 299         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 300                                         *(uint64_t *)src) == 0)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 static inline int
 307 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 308                                       struct rte_eth_link *link)
 309 {
 310         struct rte_eth_link *dst = &(dev->data->dev_link);
 311         struct rte_eth_link *src = link;
 312
 313         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 314                                         *(uint64_t *)src) == 0)
 315                 return -1;
 316
 317         return 0;
 318 }
 319
 320 /*
 321  * Driver initialization routine.
 322  * Invoked once at EAL init time.
 323  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 324  */
 325 static int
 326 rte_i40e_pmd_init(const char *name __rte_unused,
 327                   const char *params __rte_unused)
 328 {
 329         PMD_INIT_FUNC_TRACE();
 330         rte_eth_driver_register(&rte_i40e_pmd);
 331
 332         return 0;
 333 }
 334
 335 static struct rte_driver rte_i40e_driver = {
 336         .type = PMD_PDEV,
 337         .init = rte_i40e_pmd_init,
 338 };
 339
 340 PMD_REGISTER_DRIVER(rte_i40e_driver);
 341
 342 /*
 343  * Initialize registers for flexible payload, which should be set by NVM.
 344  * This should be removed from code once it is fixed in NVM.
 345  */
 346 #ifndef I40E_GLQF_ORT
 347 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 348 #endif
 349 #ifndef I40E_GLQF_PIT
 350 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 351 #endif
 352
 353 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 354 {
 355         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 356         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 357         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 358         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 359         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 360         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 361         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 362         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 363         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 364         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 365
 366         /* GLQF_PIT Registers */
 367         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 368         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 369 }
 370
 371 static int
 372 eth_i40e_dev_init(struct rte_eth_dev *dev)
 373 {
 374         struct rte_pci_device *pci_dev;
 375         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 376         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 377         struct i40e_vsi *vsi;
 378         int ret;
 379         uint32_t len;
 380         uint8_t aq_fail = 0;
 381
 382         PMD_INIT_FUNC_TRACE();
 383
 384         dev->dev_ops = &i40e_eth_dev_ops;
 385         dev->rx_pkt_burst = i40e_recv_pkts;
 386         dev->tx_pkt_burst = i40e_xmit_pkts;
 387
 388         /* for secondary processes, we don't initialise any further as primary
 389          * has already done this work. Only check we don't need a different
 390          * RX function */
 391         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 392                 if (dev->data->scattered_rx)
 393                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 394                 return 0;
 395         }
 396         pci_dev = dev->pci_dev;
 397         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 398         pf->adapter->eth_dev = dev;
 399         pf->dev_data = dev->data;
 400
 401         hw->back = I40E_PF_TO_ADAPTER(pf);
 402         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 403         if (!hw->hw_addr) {
 404                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 405                              "as address is NULL");
 406                 return -ENODEV;
 407         }
 408
 409         hw->vendor_id = pci_dev->id.vendor_id;
 410         hw->device_id = pci_dev->id.device_id;
 411         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 412         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 413         hw->bus.device = pci_dev->addr.devid;
 414         hw->bus.func = pci_dev->addr.function;
 415
 416         /* Make sure all is clean before doing PF reset */
 417         i40e_clear_hw(hw);
 418
 419         /* Initialize the hardware */
 420         i40e_hw_init(hw);
 421
 422         /* Reset here to make sure all is clean for each PF */
 423         ret = i40e_pf_reset(hw);
 424         if (ret) {
 425                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 426                 return ret;
 427         }
 428
 429         /* Initialize the shared code (base driver) */
 430         ret = i40e_init_shared_code(hw);
 431         if (ret) {
 432                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 433                 return ret;
 434         }
 435
 436         /*
 437          * To work around the NVM issue,initialize registers
 438          * for flexible payload by software.
 439          * It should be removed once issues are fixed in NVM.
 440          */
 441         i40e_flex_payload_reg_init(hw);
 442
 443         /* Initialize the parameters for adminq */
 444         i40e_init_adminq_parameter(hw);
 445         ret = i40e_init_adminq(hw);
 446         if (ret != I40E_SUCCESS) {
 447                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 448                 return -EIO;
 449         }
 450         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 451                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 452                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 453                      ((hw->nvm.version >> 12) & 0xf),
 454                      ((hw->nvm.version >> 4) & 0xff),
 455                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 456
 457         /* Disable LLDP */
 458         ret = i40e_aq_stop_lldp(hw, true, NULL);
 459         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 460                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 461
 462         /* Clear PXE mode */
 463         i40e_clear_pxe_mode(hw);
 464
 465         /*
 466          * On X710, performance number is far from the expectation on recent
 467          * firmware versions. The fix for this issue may not be integrated in
 468          * the following firmware version. So the workaround in software driver
 469          * is needed. It needs to modify the initial values of 3 internal only
 470          * registers. Note that the workaround can be removed when it is fixed
 471          * in firmware in the future.
 472          */
 473         i40e_configure_registers(hw);
 474
 475         /* Get hw capabilities */
 476         ret = i40e_get_cap(hw);
 477         if (ret != I40E_SUCCESS) {
 478                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 479                 goto err_get_capabilities;
 480         }
 481
 482         /* Initialize parameters for PF */
 483         ret = i40e_pf_parameter_init(dev);
 484         if (ret != 0) {
 485                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 486                 goto err_parameter_init;
 487         }
 488
 489         /* Initialize the queue management */
 490         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 491         if (ret < 0) {
 492                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 493                 goto err_qp_pool_init;
 494         }
 495         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 496                                 hw->func_caps.num_msix_vectors - 1);
 497         if (ret < 0) {
 498                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 499                 goto err_msix_pool_init;
 500         }
 501
 502         /* Initialize lan hmc */
 503         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 504                                 hw->func_caps.num_rx_qp, 0, 0);
 505         if (ret != I40E_SUCCESS) {
 506                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 507                 goto err_init_lan_hmc;
 508         }
 509
 510         /* Configure lan hmc */
 511         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 512         if (ret != I40E_SUCCESS) {
 513                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 514                 goto err_configure_lan_hmc;
 515         }
 516
 517         /* Get and check the mac address */
 518         i40e_get_mac_addr(hw, hw->mac.addr);
 519         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 520                 PMD_INIT_LOG(ERR, "mac address is not valid");
 521                 ret = -EIO;
 522                 goto err_get_mac_addr;
 523         }
 524         /* Copy the permanent MAC address */
 525         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 526                         (struct ether_addr *) hw->mac.perm_addr);
 527
 528         /* Disable flow control */
 529         hw->fc.requested_mode = I40E_FC_NONE;
 530         i40e_set_fc(hw, &aq_fail, TRUE);
 531
 532         /* PF setup, which includes VSI setup */
 533         ret = i40e_pf_setup(pf);
 534         if (ret) {
 535                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 536                 goto err_setup_pf_switch;
 537         }
 538
 539         vsi = pf->main_vsi;
 540
 541         /* Disable double vlan by default */
 542         i40e_vsi_config_double_vlan(vsi, FALSE);
 543
 544         if (!vsi->max_macaddrs)
 545                 len = ETHER_ADDR_LEN;
 546         else
 547                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 548
 549         /* Should be after VSI initialized */
 550         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 551         if (!dev->data->mac_addrs) {
 552                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 553                                         "for storing mac address");
 554                 goto err_mac_alloc;
 555         }
 556         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 557                                         &dev->data->mac_addrs[0]);
 558
 559         /* initialize pf host driver to setup SRIOV resource if applicable */
 560         i40e_pf_host_init(dev);
 561
 562         /* register callback func to eal lib */
 563         rte_intr_callback_register(&(pci_dev->intr_handle),
 564                 i40e_dev_interrupt_handler, (void *)dev);
 565
 566         /* configure and enable device interrupt */
 567         i40e_pf_config_irq0(hw);
 568         i40e_pf_enable_irq0(hw);
 569
 570         /* enable uio intr after callback register */
 571         rte_intr_enable(&(pci_dev->intr_handle));
 572
 573         /* initialize mirror rule list */
 574         TAILQ_INIT(&pf->mirror_list);
 575
 576         return 0;
 577
 578 err_mac_alloc:
 579         i40e_vsi_release(pf->main_vsi);
 580 err_setup_pf_switch:
 581 err_get_mac_addr:
 582 err_configure_lan_hmc:
 583         (void)i40e_shutdown_lan_hmc(hw);
 584 err_init_lan_hmc:
 585         i40e_res_pool_destroy(&pf->msix_pool);
 586 err_msix_pool_init:
 587         i40e_res_pool_destroy(&pf->qp_pool);
 588 err_qp_pool_init:
 589 err_parameter_init:
 590 err_get_capabilities:
 591         (void)i40e_shutdown_adminq(hw);
 592
 593         return ret;
 594 }
 595
 596 static int
 597 i40e_dev_configure(struct rte_eth_dev *dev)
 598 {
 599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 600         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 601         int ret;
 602
 603         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 604                 ret = i40e_fdir_setup(pf);
 605                 if (ret != I40E_SUCCESS) {
 606                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 607                         return -ENOTSUP;
 608                 }
 609                 ret = i40e_fdir_configure(dev);
 610                 if (ret < 0) {
 611                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 612                         goto err;
 613                 }
 614         } else
 615                 i40e_fdir_teardown(pf);
 616
 617         ret = i40e_dev_init_vlan(dev);
 618         if (ret < 0)
 619                 goto err;
 620
 621         /* VMDQ setup.
 622          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 623          *  RSS setting have different requirements.
 624          *  General PMD driver call sequence are NIC init, configure,
 625          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 626          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 627          *  applicable. So, VMDQ setting has to be done before
 628          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 629          *  For RSS setting, it will try to calculate actual configured RX queue
 630          *  number, which will be available after rx_queue_setup(). dev_start()
 631          *  function is good to place RSS setup.
 632          */
 633         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 634                 ret = i40e_vmdq_setup(dev);
 635                 if (ret)
 636                         goto err;
 637         }
 638         return 0;
 639 err:
 640         i40e_fdir_teardown(pf);
 641         return ret;
 642 }
 643
 644 void
 645 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 646 {
 647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 648         uint16_t msix_vect = vsi->msix_intr;
 649         uint16_t i;
 650
 651         for (i = 0; i < vsi->nb_qps; i++) {
 652                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 653                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 654                 rte_wmb();
 655         }
 656
 657         if (vsi->type != I40E_VSI_SRIOV) {
 658                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 659                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 660                                 msix_vect - 1), 0);
 661         } else {
 662                 uint32_t reg;
 663                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 664                         vsi->user_param + (msix_vect - 1);
 665
 666                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 667         }
 668         I40E_WRITE_FLUSH(hw);
 669 }
 670
 671 static inline uint16_t
 672 i40e_calc_itr_interval(int16_t interval)
 673 {
 674         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 675                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 676
 677         /* Convert to hardware count, as writing each 1 represents 2 us */
 678         return (interval/2);
 679 }
 680
 681 void
 682 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 683 {
 684         uint32_t val;
 685         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 686         uint16_t msix_vect = vsi->msix_intr;
 687         int i;
 688
 689         for (i = 0; i < vsi->nb_qps; i++)
 690                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 691
 692         /* Bind all RX queues to allocated MSIX interrupt */
 693         for (i = 0; i < vsi->nb_qps; i++) {
 694                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 695                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 696                         ((vsi->base_queue + i + 1) <<
 697                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 698                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 699                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 700
 701                 if (i == vsi->nb_qps - 1)
 702                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 703                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 704         }
 705
 706         /* Write first RX queue to Link list register as the head element */
 707         if (vsi->type != I40E_VSI_SRIOV) {
 708                 uint16_t interval =
 709                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 710
 711                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 712                                                 (vsi->base_queue <<
 713                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 714                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 715
 716                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 717                                                 msix_vect - 1), interval);
 718
 719 #ifndef I40E_GLINT_CTL
 720 #define I40E_GLINT_CTL                     0x0003F800
 721 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 722 #endif
 723                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 724                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 725                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 726         } else {
 727                 uint32_t reg;
 728
 729                 /* num_msix_vectors_vf needs to minus irq0 */
 730                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 731                         vsi->user_param + (msix_vect - 1);
 732
 733                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 734                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 735                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 736         }
 737
 738         I40E_WRITE_FLUSH(hw);
 739 }
 740
 741 static void
 742 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 743 {
 744         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 745         uint16_t interval = i40e_calc_itr_interval(\
 746                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 747
 748         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 749                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 750                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 751                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 752                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 753 }
 754
 755 static void
 756 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 757 {
 758         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 759
 760         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 761 }
 762
 763 static inline uint8_t
 764 i40e_parse_link_speed(uint16_t eth_link_speed)
 765 {
 766         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 767
 768         switch (eth_link_speed) {
 769         case ETH_LINK_SPEED_40G:
 770                 link_speed = I40E_LINK_SPEED_40GB;
 771                 break;
 772         case ETH_LINK_SPEED_20G:
 773                 link_speed = I40E_LINK_SPEED_20GB;
 774                 break;
 775         case ETH_LINK_SPEED_10G:
 776                 link_speed = I40E_LINK_SPEED_10GB;
 777                 break;
 778         case ETH_LINK_SPEED_1000:
 779                 link_speed = I40E_LINK_SPEED_1GB;
 780                 break;
 781         case ETH_LINK_SPEED_100:
 782                 link_speed = I40E_LINK_SPEED_100MB;
 783                 break;
 784         }
 785
 786         return link_speed;
 787 }
 788
 789 static int
 790 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 791 {
 792         enum i40e_status_code status;
 793         struct i40e_aq_get_phy_abilities_resp phy_ab;
 794         struct i40e_aq_set_phy_config phy_conf;
 795         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 796                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 797                         I40E_AQ_PHY_FLAG_LOW_POWER;
 798         const uint8_t advt = I40E_LINK_SPEED_40GB |
 799                         I40E_LINK_SPEED_10GB |
 800                         I40E_LINK_SPEED_1GB |
 801                         I40E_LINK_SPEED_100MB;
 802         int ret = -ENOTSUP;
 803
 804         /* Skip it on 40G interfaces, as a workaround for the link issue */
 805         if (i40e_is_40G_device(hw->device_id))
 806                 return I40E_SUCCESS;
 807
 808         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 809                                               NULL);
 810         if (status)
 811                 return ret;
 812
 813         memset(&phy_conf, 0, sizeof(phy_conf));
 814
 815         /* bits 0-2 use the values from get_phy_abilities_resp */
 816         abilities &= ~mask;
 817         abilities |= phy_ab.abilities & mask;
 818
 819         /* update ablities and speed */
 820         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 821                 phy_conf.link_speed = advt;
 822         else
 823                 phy_conf.link_speed = force_speed;
 824
 825         phy_conf.abilities = abilities;
 826
 827         /* use get_phy_abilities_resp value for the rest */
 828         phy_conf.phy_type = phy_ab.phy_type;
 829         phy_conf.eee_capability = phy_ab.eee_capability;
 830         phy_conf.eeer = phy_ab.eeer_val;
 831         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 832
 833         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 834                     phy_ab.abilities, phy_ab.link_speed);
 835         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 836                     phy_conf.abilities, phy_conf.link_speed);
 837
 838         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 839         if (status)
 840                 return ret;
 841
 842         return I40E_SUCCESS;
 843 }
 844
 845 static int
 846 i40e_apply_link_speed(struct rte_eth_dev *dev)
 847 {
 848         uint8_t speed;
 849         uint8_t abilities = 0;
 850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 851         struct rte_eth_conf *conf = &dev->data->dev_conf;
 852
 853         speed = i40e_parse_link_speed(conf->link_speed);
 854         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 855         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 856                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 857         else
 858                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 859
 860         return i40e_phy_conf_link(hw, abilities, speed);
 861 }
 862
 863 static int
 864 i40e_dev_start(struct rte_eth_dev *dev)
 865 {
 866         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 868         struct i40e_vsi *main_vsi = pf->main_vsi;
 869         int ret, i;
 870
 871         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 872                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 873                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 874                              dev->data->dev_conf.link_duplex,
 875                              dev->data->port_id);
 876                 return -EINVAL;
 877         }
 878
 879         /* Initialize VSI */
 880         ret = i40e_dev_rxtx_init(pf);
 881         if (ret != I40E_SUCCESS) {
 882                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 883                 goto err_up;
 884         }
 885
 886         /* Map queues with MSIX interrupt */
 887         i40e_vsi_queues_bind_intr(main_vsi);
 888         i40e_vsi_enable_queues_intr(main_vsi);
 889
 890         /* Map VMDQ VSI queues with MSIX interrupt */
 891         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 892                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 893                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 894         }
 895
 896         /* enable FDIR MSIX interrupt */
 897         if (pf->fdir.fdir_vsi) {
 898                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 899                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 900         }
 901
 902         /* Enable all queues which have been configured */
 903         ret = i40e_dev_switch_queues(pf, TRUE);
 904         if (ret != I40E_SUCCESS) {
 905                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 906                 goto err_up;
 907         }
 908
 909         /* Enable receiving broadcast packets */
 910         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 911         if (ret != I40E_SUCCESS)
 912                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 913
 914         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 915                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
 916                                                 true, NULL);
 917                 if (ret != I40E_SUCCESS)
 918                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 919         }
 920
 921         /* Apply link configure */
 922         ret = i40e_apply_link_speed(dev);
 923         if (I40E_SUCCESS != ret) {
 924                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
 925                 goto err_up;
 926         }
 927
 928         return I40E_SUCCESS;
 929
 930 err_up:
 931         i40e_dev_switch_queues(pf, FALSE);
 932         i40e_dev_clear_queues(dev);
 933
 934         return ret;
 935 }
 936
 937 static void
 938 i40e_dev_stop(struct rte_eth_dev *dev)
 939 {
 940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 941         struct i40e_vsi *main_vsi = pf->main_vsi;
 942         struct i40e_mirror_rule *p_mirror;
 943         int i;
 944
 945         /* Disable all queues */
 946         i40e_dev_switch_queues(pf, FALSE);
 947
 948         /* un-map queues with interrupt registers */
 949         i40e_vsi_disable_queues_intr(main_vsi);
 950         i40e_vsi_queues_unbind_intr(main_vsi);
 951
 952         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 953                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
 954                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
 955         }
 956
 957         if (pf->fdir.fdir_vsi) {
 958                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 959                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 960         }
 961         /* Clear all queues and release memory */
 962         i40e_dev_clear_queues(dev);
 963
 964         /* Set link down */
 965         i40e_dev_set_link_down(dev);
 966
 967         /* Remove all mirror rules */
 968         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
 969                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
 970                 rte_free(p_mirror);
 971         }
 972         pf->nb_mirror_rule = 0;
 973
 974 }
 975
 976 static void
 977 i40e_dev_close(struct rte_eth_dev *dev)
 978 {
 979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 980         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 981         uint32_t reg;
 982
 983         PMD_INIT_FUNC_TRACE();
 984
 985         i40e_dev_stop(dev);
 986
 987         /* Disable interrupt */
 988         i40e_pf_disable_irq0(hw);
 989         rte_intr_disable(&(dev->pci_dev->intr_handle));
 990
 991         /* shutdown and destroy the HMC */
 992         i40e_shutdown_lan_hmc(hw);
 993
 994         /* release all the existing VSIs and VEBs */
 995         i40e_fdir_teardown(pf);
 996         i40e_vsi_release(pf->main_vsi);
 997
 998         /* shutdown the adminq */
 999         i40e_aq_queue_shutdown(hw, true);
1000         i40e_shutdown_adminq(hw);
1001
1002         i40e_res_pool_destroy(&pf->qp_pool);
1003         i40e_res_pool_destroy(&pf->msix_pool);
1004
1005         /* force a PF reset to clean anything leftover */
1006         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1007         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1008                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1009         I40E_WRITE_FLUSH(hw);
1010 }
1011
1012 static void
1013 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1014 {
1015         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct i40e_vsi *vsi = pf->main_vsi;
1018         int status;
1019
1020         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1021                                                         true, NULL);
1022         if (status != I40E_SUCCESS)
1023                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1024
1025         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1026                                                         TRUE, NULL);
1027         if (status != I40E_SUCCESS)
1028                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1029
1030 }
1031
1032 static void
1033 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1034 {
1035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct i40e_vsi *vsi = pf->main_vsi;
1038         int status;
1039
1040         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1041                                                         false, NULL);
1042         if (status != I40E_SUCCESS)
1043                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1044
1045         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1046                                                         false, NULL);
1047         if (status != I40E_SUCCESS)
1048                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1049 }
1050
1051 static void
1052 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1053 {
1054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1056         struct i40e_vsi *vsi = pf->main_vsi;
1057         int ret;
1058
1059         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1060         if (ret != I40E_SUCCESS)
1061                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1062 }
1063
1064 static void
1065 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1066 {
1067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1069         struct i40e_vsi *vsi = pf->main_vsi;
1070         int ret;
1071
1072         if (dev->data->promiscuous == 1)
1073                 return; /* must remain in all_multicast mode */
1074
1075         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1076                                 vsi->seid, FALSE, NULL);
1077         if (ret != I40E_SUCCESS)
1078                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1079 }
1080
1081 /*
1082  * Set device link up.
1083  */
1084 static int
1085 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1086 {
1087         /* re-apply link speed setting */
1088         return i40e_apply_link_speed(dev);
1089 }
1090
1091 /*
1092  * Set device link down.
1093  */
1094 static int
1095 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1096 {
1097         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1098         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1100
1101         return i40e_phy_conf_link(hw, abilities, speed);
1102 }
1103
1104 int
1105 i40e_dev_link_update(struct rte_eth_dev *dev,
1106                      int wait_to_complete)
1107 {
1108 #define CHECK_INTERVAL 100  /* 100ms */
1109 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         struct i40e_link_status link_status;
1112         struct rte_eth_link link, old;
1113         int status;
1114         unsigned rep_cnt = MAX_REPEAT_TIME;
1115
1116         memset(&link, 0, sizeof(link));
1117         memset(&old, 0, sizeof(old));
1118         memset(&link_status, 0, sizeof(link_status));
1119         rte_i40e_dev_atomic_read_link_status(dev, &old);
1120
1121         do {
1122                 /* Get link status information from hardware */
1123                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1124                 if (status != I40E_SUCCESS) {
1125                         link.link_speed = ETH_LINK_SPEED_100;
1126                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1127                         PMD_DRV_LOG(ERR, "Failed to get link info");
1128                         goto out;
1129                 }
1130
1131                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1132                 if (!wait_to_complete)
1133                         break;
1134
1135                 rte_delay_ms(CHECK_INTERVAL);
1136         } while (!link.link_status && rep_cnt--);
1137
1138         if (!link.link_status)
1139                 goto out;
1140
1141         /* i40e uses full duplex only */
1142         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1143
1144         /* Parse the link status */
1145         switch (link_status.link_speed) {
1146         case I40E_LINK_SPEED_100MB:
1147                 link.link_speed = ETH_LINK_SPEED_100;
1148                 break;
1149         case I40E_LINK_SPEED_1GB:
1150                 link.link_speed = ETH_LINK_SPEED_1000;
1151                 break;
1152         case I40E_LINK_SPEED_10GB:
1153                 link.link_speed = ETH_LINK_SPEED_10G;
1154                 break;
1155         case I40E_LINK_SPEED_20GB:
1156                 link.link_speed = ETH_LINK_SPEED_20G;
1157                 break;
1158         case I40E_LINK_SPEED_40GB:
1159                 link.link_speed = ETH_LINK_SPEED_40G;
1160                 break;
1161         default:
1162                 link.link_speed = ETH_LINK_SPEED_100;
1163                 break;
1164         }
1165
1166 out:
1167         rte_i40e_dev_atomic_write_link_status(dev, &link);
1168         if (link.link_status == old.link_status)
1169                 return -1;
1170
1171         return 0;
1172 }
1173
1174 /* Get all the statistics of a VSI */
1175 void
1176 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1177 {
1178         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1179         struct i40e_eth_stats *nes = &vsi->eth_stats;
1180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1181         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1182
1183         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1184                             vsi->offset_loaded, &oes->rx_bytes,
1185                             &nes->rx_bytes);
1186         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1187                             vsi->offset_loaded, &oes->rx_unicast,
1188                             &nes->rx_unicast);
1189         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1190                             vsi->offset_loaded, &oes->rx_multicast,
1191                             &nes->rx_multicast);
1192         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1193                             vsi->offset_loaded, &oes->rx_broadcast,
1194                             &nes->rx_broadcast);
1195         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1196                             &oes->rx_discards, &nes->rx_discards);
1197         /* GLV_REPC not supported */
1198         /* GLV_RMPC not supported */
1199         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1200                             &oes->rx_unknown_protocol,
1201                             &nes->rx_unknown_protocol);
1202         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1203                             vsi->offset_loaded, &oes->tx_bytes,
1204                             &nes->tx_bytes);
1205         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1206                             vsi->offset_loaded, &oes->tx_unicast,
1207                             &nes->tx_unicast);
1208         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1209                             vsi->offset_loaded, &oes->tx_multicast,
1210                             &nes->tx_multicast);
1211         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1212                             vsi->offset_loaded,  &oes->tx_broadcast,
1213                             &nes->tx_broadcast);
1214         /* GLV_TDPC not supported */
1215         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1216                             &oes->tx_errors, &nes->tx_errors);
1217         vsi->offset_loaded = true;
1218
1219         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1220                     vsi->vsi_id);
1221         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1222         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1223         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1224         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1225         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1226         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1227                     nes->rx_unknown_protocol);
1228         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1229         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1230         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1231         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1232         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1233         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1234         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1235                     vsi->vsi_id);
1236 }
1237
1238 /* Get all statistics of a port */
1239 static void
1240 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1241 {
1242         uint32_t i;
1243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1246         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1247
1248         /* Get statistics of struct i40e_eth_stats */
1249         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1250                             I40E_GLPRT_GORCL(hw->port),
1251                             pf->offset_loaded, &os->eth.rx_bytes,
1252                             &ns->eth.rx_bytes);
1253         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1254                             I40E_GLPRT_UPRCL(hw->port),
1255                             pf->offset_loaded, &os->eth.rx_unicast,
1256                             &ns->eth.rx_unicast);
1257         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1258                             I40E_GLPRT_MPRCL(hw->port),
1259                             pf->offset_loaded, &os->eth.rx_multicast,
1260                             &ns->eth.rx_multicast);
1261         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1262                             I40E_GLPRT_BPRCL(hw->port),
1263                             pf->offset_loaded, &os->eth.rx_broadcast,
1264                             &ns->eth.rx_broadcast);
1265         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1266                             pf->offset_loaded, &os->eth.rx_discards,
1267                             &ns->eth.rx_discards);
1268         /* GLPRT_REPC not supported */
1269         /* GLPRT_RMPC not supported */
1270         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1271                             pf->offset_loaded,
1272                             &os->eth.rx_unknown_protocol,
1273                             &ns->eth.rx_unknown_protocol);
1274         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1275                             I40E_GLPRT_GOTCL(hw->port),
1276                             pf->offset_loaded, &os->eth.tx_bytes,
1277                             &ns->eth.tx_bytes);
1278         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1279                             I40E_GLPRT_UPTCL(hw->port),
1280                             pf->offset_loaded, &os->eth.tx_unicast,
1281                             &ns->eth.tx_unicast);
1282         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1283                             I40E_GLPRT_MPTCL(hw->port),
1284                             pf->offset_loaded, &os->eth.tx_multicast,
1285                             &ns->eth.tx_multicast);
1286         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1287                             I40E_GLPRT_BPTCL(hw->port),
1288                             pf->offset_loaded, &os->eth.tx_broadcast,
1289                             &ns->eth.tx_broadcast);
1290         /* GLPRT_TEPC not supported */
1291
1292         /* additional port specific stats */
1293         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1294                             pf->offset_loaded, &os->tx_dropped_link_down,
1295                             &ns->tx_dropped_link_down);
1296         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1297                             pf->offset_loaded, &os->crc_errors,
1298                             &ns->crc_errors);
1299         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1300                             pf->offset_loaded, &os->illegal_bytes,
1301                             &ns->illegal_bytes);
1302         /* GLPRT_ERRBC not supported */
1303         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1304                             pf->offset_loaded, &os->mac_local_faults,
1305                             &ns->mac_local_faults);
1306         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1307                             pf->offset_loaded, &os->mac_remote_faults,
1308                             &ns->mac_remote_faults);
1309         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1310                             pf->offset_loaded, &os->rx_length_errors,
1311                             &ns->rx_length_errors);
1312         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1313                             pf->offset_loaded, &os->link_xon_rx,
1314                             &ns->link_xon_rx);
1315         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1316                             pf->offset_loaded, &os->link_xoff_rx,
1317                             &ns->link_xoff_rx);
1318         for (i = 0; i < 8; i++) {
1319                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1320                                     pf->offset_loaded,
1321                                     &os->priority_xon_rx[i],
1322                                     &ns->priority_xon_rx[i]);
1323                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1324                                     pf->offset_loaded,
1325                                     &os->priority_xoff_rx[i],
1326                                     &ns->priority_xoff_rx[i]);
1327         }
1328         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1329                             pf->offset_loaded, &os->link_xon_tx,
1330                             &ns->link_xon_tx);
1331         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1332                             pf->offset_loaded, &os->link_xoff_tx,
1333                             &ns->link_xoff_tx);
1334         for (i = 0; i < 8; i++) {
1335                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1336                                     pf->offset_loaded,
1337                                     &os->priority_xon_tx[i],
1338                                     &ns->priority_xon_tx[i]);
1339                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1340                                     pf->offset_loaded,
1341                                     &os->priority_xoff_tx[i],
1342                                     &ns->priority_xoff_tx[i]);
1343                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1344                                     pf->offset_loaded,
1345                                     &os->priority_xon_2_xoff[i],
1346                                     &ns->priority_xon_2_xoff[i]);
1347         }
1348         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1349                             I40E_GLPRT_PRC64L(hw->port),
1350                             pf->offset_loaded, &os->rx_size_64,
1351                             &ns->rx_size_64);
1352         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1353                             I40E_GLPRT_PRC127L(hw->port),
1354                             pf->offset_loaded, &os->rx_size_127,
1355                             &ns->rx_size_127);
1356         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1357                             I40E_GLPRT_PRC255L(hw->port),
1358                             pf->offset_loaded, &os->rx_size_255,
1359                             &ns->rx_size_255);
1360         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1361                             I40E_GLPRT_PRC511L(hw->port),
1362                             pf->offset_loaded, &os->rx_size_511,
1363                             &ns->rx_size_511);
1364         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1365                             I40E_GLPRT_PRC1023L(hw->port),
1366                             pf->offset_loaded, &os->rx_size_1023,
1367                             &ns->rx_size_1023);
1368         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1369                             I40E_GLPRT_PRC1522L(hw->port),
1370                             pf->offset_loaded, &os->rx_size_1522,
1371                             &ns->rx_size_1522);
1372         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1373                             I40E_GLPRT_PRC9522L(hw->port),
1374                             pf->offset_loaded, &os->rx_size_big,
1375                             &ns->rx_size_big);
1376         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1377                             pf->offset_loaded, &os->rx_undersize,
1378                             &ns->rx_undersize);
1379         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1380                             pf->offset_loaded, &os->rx_fragments,
1381                             &ns->rx_fragments);
1382         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1383                             pf->offset_loaded, &os->rx_oversize,
1384                             &ns->rx_oversize);
1385         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1386                             pf->offset_loaded, &os->rx_jabber,
1387                             &ns->rx_jabber);
1388         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1389                             I40E_GLPRT_PTC64L(hw->port),
1390                             pf->offset_loaded, &os->tx_size_64,
1391                             &ns->tx_size_64);
1392         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1393                             I40E_GLPRT_PTC127L(hw->port),
1394                             pf->offset_loaded, &os->tx_size_127,
1395                             &ns->tx_size_127);
1396         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1397                             I40E_GLPRT_PTC255L(hw->port),
1398                             pf->offset_loaded, &os->tx_size_255,
1399                             &ns->tx_size_255);
1400         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1401                             I40E_GLPRT_PTC511L(hw->port),
1402                             pf->offset_loaded, &os->tx_size_511,
1403                             &ns->tx_size_511);
1404         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1405                             I40E_GLPRT_PTC1023L(hw->port),
1406                             pf->offset_loaded, &os->tx_size_1023,
1407                             &ns->tx_size_1023);
1408         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1409                             I40E_GLPRT_PTC1522L(hw->port),
1410                             pf->offset_loaded, &os->tx_size_1522,
1411                             &ns->tx_size_1522);
1412         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1413                             I40E_GLPRT_PTC9522L(hw->port),
1414                             pf->offset_loaded, &os->tx_size_big,
1415                             &ns->tx_size_big);
1416         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1417                            pf->offset_loaded,
1418                            &os->fd_sb_match, &ns->fd_sb_match);
1419         /* GLPRT_MSPDC not supported */
1420         /* GLPRT_XEC not supported */
1421
1422         pf->offset_loaded = true;
1423
1424         if (pf->main_vsi)
1425                 i40e_update_vsi_stats(pf->main_vsi);
1426
1427         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1428                                                 ns->eth.rx_broadcast;
1429         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1430                                                 ns->eth.tx_broadcast;
1431         stats->ibytes   = ns->eth.rx_bytes;
1432         stats->obytes   = ns->eth.tx_bytes;
1433         stats->oerrors  = ns->eth.tx_errors;
1434         stats->imcasts  = ns->eth.rx_multicast;
1435         stats->fdirmatch = ns->fd_sb_match;
1436
1437         /* Rx Errors */
1438         stats->ibadcrc  = ns->crc_errors;
1439         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1440                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1441         stats->imissed  = ns->eth.rx_discards;
1442         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1443
1444         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1445         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1446         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1447         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1448         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1449         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1450         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1451                     ns->eth.rx_unknown_protocol);
1452         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1453         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1454         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1455         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1456         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1457         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1458
1459         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1460                     ns->tx_dropped_link_down);
1461         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1462         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1463                     ns->illegal_bytes);
1464         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1465         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1466                     ns->mac_local_faults);
1467         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1468                     ns->mac_remote_faults);
1469         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1470                     ns->rx_length_errors);
1471         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1472         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1473         for (i = 0; i < 8; i++) {
1474                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1475                                 i, ns->priority_xon_rx[i]);
1476                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1477                                 i, ns->priority_xoff_rx[i]);
1478         }
1479         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1480         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1481         for (i = 0; i < 8; i++) {
1482                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1483                                 i, ns->priority_xon_tx[i]);
1484                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1485                                 i, ns->priority_xoff_tx[i]);
1486                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1487                                 i, ns->priority_xon_2_xoff[i]);
1488         }
1489         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1490         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1491         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1492         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1493         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1494         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1495         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1496         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1497         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1498         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1499         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1500         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1501         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1502         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1503         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1504         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1505         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1506         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1507         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1508                         ns->mac_short_packet_dropped);
1509         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1510                     ns->checksum_error);
1511         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1512         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1513 }
1514
1515 /* Reset the statistics */
1516 static void
1517 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1518 {
1519         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1520
1521         /* It results in reloading the start point of each counter */
1522         pf->offset_loaded = false;
1523 }
1524
1525 static int
1526 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1527                                  __rte_unused uint16_t queue_id,
1528                                  __rte_unused uint8_t stat_idx,
1529                                  __rte_unused uint8_t is_rx)
1530 {
1531         PMD_INIT_FUNC_TRACE();
1532
1533         return -ENOSYS;
1534 }
1535
1536 static void
1537 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1538 {
1539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1540         struct i40e_vsi *vsi = pf->main_vsi;
1541
1542         dev_info->max_rx_queues = vsi->nb_qps;
1543         dev_info->max_tx_queues = vsi->nb_qps;
1544         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1545         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1546         dev_info->max_mac_addrs = vsi->max_macaddrs;
1547         dev_info->max_vfs = dev->pci_dev->max_vfs;
1548         dev_info->rx_offload_capa =
1549                 DEV_RX_OFFLOAD_VLAN_STRIP |
1550                 DEV_RX_OFFLOAD_QINQ_STRIP |
1551                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1552                 DEV_RX_OFFLOAD_UDP_CKSUM |
1553                 DEV_RX_OFFLOAD_TCP_CKSUM;
1554         dev_info->tx_offload_capa =
1555                 DEV_TX_OFFLOAD_VLAN_INSERT |
1556                 DEV_TX_OFFLOAD_QINQ_INSERT |
1557                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1558                 DEV_TX_OFFLOAD_UDP_CKSUM |
1559                 DEV_TX_OFFLOAD_TCP_CKSUM |
1560                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1561                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1562                 DEV_TX_OFFLOAD_TCP_TSO;
1563         dev_info->reta_size = pf->hash_lut_size;
1564         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1565
1566         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1567                 .rx_thresh = {
1568                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1569                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1570                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1571                 },
1572                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1573                 .rx_drop_en = 0,
1574         };
1575
1576         dev_info->default_txconf = (struct rte_eth_txconf) {
1577                 .tx_thresh = {
1578                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1579                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1580                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1581                 },
1582                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1583                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1584                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1585                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1586         };
1587
1588         if (pf->flags & I40E_FLAG_VMDQ) {
1589                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1590                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1591                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1592                                                 pf->max_nb_vmdq_vsi;
1593                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1594                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1595                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1596         }
1597 }
1598
1599 static int
1600 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1601 {
1602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1603         struct i40e_vsi *vsi = pf->main_vsi;
1604         PMD_INIT_FUNC_TRACE();
1605
1606         if (on)
1607                 return i40e_vsi_add_vlan(vsi, vlan_id);
1608         else
1609                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1610 }
1611
1612 static void
1613 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1614                    __rte_unused uint16_t tpid)
1615 {
1616         PMD_INIT_FUNC_TRACE();
1617 }
1618
1619 static void
1620 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1621 {
1622         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1623         struct i40e_vsi *vsi = pf->main_vsi;
1624
1625         if (mask & ETH_VLAN_STRIP_MASK) {
1626                 /* Enable or disable VLAN stripping */
1627                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1628                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1629                 else
1630                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1631         }
1632
1633         if (mask & ETH_VLAN_EXTEND_MASK) {
1634                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1635                         i40e_vsi_config_double_vlan(vsi, TRUE);
1636                 else
1637                         i40e_vsi_config_double_vlan(vsi, FALSE);
1638         }
1639 }
1640
1641 static void
1642 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1643                           __rte_unused uint16_t queue,
1644                           __rte_unused int on)
1645 {
1646         PMD_INIT_FUNC_TRACE();
1647 }
1648
1649 static int
1650 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1651 {
1652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653         struct i40e_vsi *vsi = pf->main_vsi;
1654         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1655         struct i40e_vsi_vlan_pvid_info info;
1656
1657         memset(&info, 0, sizeof(info));
1658         info.on = on;
1659         if (info.on)
1660                 info.config.pvid = pvid;
1661         else {
1662                 info.config.reject.tagged =
1663                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1664                 info.config.reject.untagged =
1665                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1666         }
1667
1668         return i40e_vsi_vlan_pvid_set(vsi, &info);
1669 }
1670
1671 static int
1672 i40e_dev_led_on(struct rte_eth_dev *dev)
1673 {
1674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675         uint32_t mode = i40e_led_get(hw);
1676
1677         if (mode == 0)
1678                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1679
1680         return 0;
1681 }
1682
1683 static int
1684 i40e_dev_led_off(struct rte_eth_dev *dev)
1685 {
1686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687         uint32_t mode = i40e_led_get(hw);
1688
1689         if (mode != 0)
1690                 i40e_led_set(hw, 0, false);
1691
1692         return 0;
1693 }
1694
1695 static int
1696 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1697                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1698 {
1699         PMD_INIT_FUNC_TRACE();
1700
1701         return -ENOSYS;
1702 }
1703
1704 static int
1705 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1706                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1707 {
1708         PMD_INIT_FUNC_TRACE();
1709
1710         return -ENOSYS;
1711 }
1712
1713 /* Add a MAC address, and update filters */
1714 static void
1715 i40e_macaddr_add(struct rte_eth_dev *dev,
1716                  struct ether_addr *mac_addr,
1717                  __rte_unused uint32_t index,
1718                  uint32_t pool)
1719 {
1720         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1721         struct i40e_mac_filter_info mac_filter;
1722         struct i40e_vsi *vsi;
1723         int ret;
1724
1725         /* If VMDQ not enabled or configured, return */
1726         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1727                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1728                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1729                         pool);
1730                 return;
1731         }
1732
1733         if (pool > pf->nb_cfg_vmdq_vsi) {
1734                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1735                                 pool, pf->nb_cfg_vmdq_vsi);
1736                 return;
1737         }
1738
1739         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1740         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1741
1742         if (pool == 0)
1743                 vsi = pf->main_vsi;
1744         else
1745                 vsi = pf->vmdq[pool - 1].vsi;
1746
1747         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1748         if (ret != I40E_SUCCESS) {
1749                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1750                 return;
1751         }
1752 }
1753
1754 /* Remove a MAC address, and update filters */
1755 static void
1756 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1757 {
1758         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1759         struct i40e_vsi *vsi;
1760         struct rte_eth_dev_data *data = dev->data;
1761         struct ether_addr *macaddr;
1762         int ret;
1763         uint32_t i;
1764         uint64_t pool_sel;
1765
1766         macaddr = &(data->mac_addrs[index]);
1767
1768         pool_sel = dev->data->mac_pool_sel[index];
1769
1770         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1771                 if (pool_sel & (1ULL << i)) {
1772                         if (i == 0)
1773                                 vsi = pf->main_vsi;
1774                         else {
1775                                 /* No VMDQ pool enabled or configured */
1776                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1777                                         (i > pf->nb_cfg_vmdq_vsi)) {
1778                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1779                                                         "/configured");
1780                                         return;
1781                                 }
1782                                 vsi = pf->vmdq[i - 1].vsi;
1783                         }
1784                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1785
1786                         if (ret) {
1787                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1788                                 return;
1789                         }
1790                 }
1791         }
1792 }
1793
1794 /* Set perfect match or hash match of MAC and VLAN for a VF */
1795 static int
1796 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1797                  struct rte_eth_mac_filter *filter,
1798                  bool add)
1799 {
1800         struct i40e_hw *hw;
1801         struct i40e_mac_filter_info mac_filter;
1802         struct ether_addr old_mac;
1803         struct ether_addr *new_mac;
1804         struct i40e_pf_vf *vf = NULL;
1805         uint16_t vf_id;
1806         int ret;
1807
1808         if (pf == NULL) {
1809                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1810                 return -EINVAL;
1811         }
1812         hw = I40E_PF_TO_HW(pf);
1813
1814         if (filter == NULL) {
1815                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1816                 return -EINVAL;
1817         }
1818
1819         new_mac = &filter->mac_addr;
1820
1821         if (is_zero_ether_addr(new_mac)) {
1822                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1823                 return -EINVAL;
1824         }
1825
1826         vf_id = filter->dst_id;
1827
1828         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1829                 PMD_DRV_LOG(ERR, "Invalid argument.");
1830                 return -EINVAL;
1831         }
1832         vf = &pf->vfs[vf_id];
1833
1834         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1835                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1836                 return -EINVAL;
1837         }
1838
1839         if (add) {
1840                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1841                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1842                                 ETHER_ADDR_LEN);
1843                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1844                                  ETHER_ADDR_LEN);
1845
1846                 mac_filter.filter_type = filter->filter_type;
1847                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1848                 if (ret != I40E_SUCCESS) {
1849                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1850                         return -1;
1851                 }
1852                 ether_addr_copy(new_mac, &pf->dev_addr);
1853         } else {
1854                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1855                                 ETHER_ADDR_LEN);
1856                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1857                 if (ret != I40E_SUCCESS) {
1858                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1859                         return -1;
1860                 }
1861
1862                 /* Clear device address as it has been removed */
1863                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1864                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1865         }
1866
1867         return 0;
1868 }
1869
1870 /* MAC filter handle */
1871 static int
1872 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1873                 void *arg)
1874 {
1875         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1876         struct rte_eth_mac_filter *filter;
1877         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1878         int ret = I40E_NOT_SUPPORTED;
1879
1880         filter = (struct rte_eth_mac_filter *)(arg);
1881
1882         switch (filter_op) {
1883         case RTE_ETH_FILTER_NOP:
1884                 ret = I40E_SUCCESS;
1885                 break;
1886         case RTE_ETH_FILTER_ADD:
1887                 i40e_pf_disable_irq0(hw);
1888                 if (filter->is_vf)
1889                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1890                 i40e_pf_enable_irq0(hw);
1891                 break;
1892         case RTE_ETH_FILTER_DELETE:
1893                 i40e_pf_disable_irq0(hw);
1894                 if (filter->is_vf)
1895                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1896                 i40e_pf_enable_irq0(hw);
1897                 break;
1898         default:
1899                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1900                 ret = I40E_ERR_PARAM;
1901                 break;
1902         }
1903
1904         return ret;
1905 }
1906
1907 static int
1908 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1909                          struct rte_eth_rss_reta_entry64 *reta_conf,
1910                          uint16_t reta_size)
1911 {
1912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         uint32_t lut, l;
1915         uint16_t i, j, lut_size = pf->hash_lut_size;
1916         uint16_t idx, shift;
1917         uint8_t mask;
1918
1919         if (reta_size != lut_size ||
1920                 reta_size > ETH_RSS_RETA_SIZE_512) {
1921                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1922                         "(%d) doesn't match the number hardware can supported "
1923                                         "(%d)\n", reta_size, lut_size);
1924                 return -EINVAL;
1925         }
1926
1927         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1928                 idx = i / RTE_RETA_GROUP_SIZE;
1929                 shift = i % RTE_RETA_GROUP_SIZE;
1930                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1931                                                 I40E_4_BIT_MASK);
1932                 if (!mask)
1933                         continue;
1934                 if (mask == I40E_4_BIT_MASK)
1935                         l = 0;
1936                 else
1937                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1938                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
1939                         if (mask & (0x1 << j))
1940                                 lut |= reta_conf[idx].reta[shift + j] <<
1941                                                         (CHAR_BIT * j);
1942                         else
1943                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
1944                 }
1945                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
1946         }
1947
1948         return 0;
1949 }
1950
1951 static int
1952 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
1953                         struct rte_eth_rss_reta_entry64 *reta_conf,
1954                         uint16_t reta_size)
1955 {
1956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1958         uint32_t lut;
1959         uint16_t i, j, lut_size = pf->hash_lut_size;
1960         uint16_t idx, shift;
1961         uint8_t mask;
1962
1963         if (reta_size != lut_size ||
1964                 reta_size > ETH_RSS_RETA_SIZE_512) {
1965                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
1966                         "(%d) doesn't match the number hardware can supported "
1967                                         "(%d)\n", reta_size, lut_size);
1968                 return -EINVAL;
1969         }
1970
1971         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
1972                 idx = i / RTE_RETA_GROUP_SIZE;
1973                 shift = i % RTE_RETA_GROUP_SIZE;
1974                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
1975                                                 I40E_4_BIT_MASK);
1976                 if (!mask)
1977                         continue;
1978
1979                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
1980                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
1981                         if (mask & (0x1 << j))
1982                                 reta_conf[idx].reta[shift + j] = ((lut >>
1983                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
1984                 }
1985         }
1986
1987         return 0;
1988 }
1989
1990 /**
1991  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
1992  * @hw:   pointer to the HW structure
1993  * @mem:  pointer to mem struct to fill out
1994  * @size: size of memory requested
1995  * @alignment: what to align the allocation to
1996  **/
1997 enum i40e_status_code
1998 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
1999                         struct i40e_dma_mem *mem,
2000                         u64 size,
2001                         u32 alignment)
2002 {
2003         static uint64_t id = 0;
2004         const struct rte_memzone *mz = NULL;
2005         char z_name[RTE_MEMZONE_NAMESIZE];
2006
2007         if (!mem)
2008                 return I40E_ERR_PARAM;
2009
2010         id++;
2011         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2012 #ifdef RTE_LIBRTE_XEN_DOM0
2013         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2014                                                         RTE_PGSIZE_2M);
2015 #else
2016         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2017 #endif
2018         if (!mz)
2019                 return I40E_ERR_NO_MEMORY;
2020
2021         mem->id = id;
2022         mem->size = size;
2023         mem->va = mz->addr;
2024 #ifdef RTE_LIBRTE_XEN_DOM0
2025         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2026 #else
2027         mem->pa = mz->phys_addr;
2028 #endif
2029
2030         return I40E_SUCCESS;
2031 }
2032
2033 /**
2034  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2035  * @hw:   pointer to the HW structure
2036  * @mem:  ptr to mem struct to free
2037  **/
2038 enum i40e_status_code
2039 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2040                     struct i40e_dma_mem *mem)
2041 {
2042         if (!mem || !mem->va)
2043                 return I40E_ERR_PARAM;
2044
2045         mem->va = NULL;
2046         mem->pa = (u64)0;
2047
2048         return I40E_SUCCESS;
2049 }
2050
2051 /**
2052  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2053  * @hw:   pointer to the HW structure
2054  * @mem:  pointer to mem struct to fill out
2055  * @size: size of memory requested
2056  **/
2057 enum i40e_status_code
2058 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2059                          struct i40e_virt_mem *mem,
2060                          u32 size)
2061 {
2062         if (!mem)
2063                 return I40E_ERR_PARAM;
2064
2065         mem->size = size;
2066         mem->va = rte_zmalloc("i40e", size, 0);
2067
2068         if (mem->va)
2069                 return I40E_SUCCESS;
2070         else
2071                 return I40E_ERR_NO_MEMORY;
2072 }
2073
2074 /**
2075  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2076  * @hw:   pointer to the HW structure
2077  * @mem:  pointer to mem struct to free
2078  **/
2079 enum i40e_status_code
2080 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2081                      struct i40e_virt_mem *mem)
2082 {
2083         if (!mem)
2084                 return I40E_ERR_PARAM;
2085
2086         rte_free(mem->va);
2087         mem->va = NULL;
2088
2089         return I40E_SUCCESS;
2090 }
2091
2092 void
2093 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2094 {
2095         rte_spinlock_init(&sp->spinlock);
2096 }
2097
2098 void
2099 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2100 {
2101         rte_spinlock_lock(&sp->spinlock);
2102 }
2103
2104 void
2105 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2106 {
2107         rte_spinlock_unlock(&sp->spinlock);
2108 }
2109
2110 void
2111 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2112 {
2113         return;
2114 }
2115
2116 /**
2117  * Get the hardware capabilities, which will be parsed
2118  * and saved into struct i40e_hw.
2119  */
2120 static int
2121 i40e_get_cap(struct i40e_hw *hw)
2122 {
2123         struct i40e_aqc_list_capabilities_element_resp *buf;
2124         uint16_t len, size = 0;
2125         int ret;
2126
2127         /* Calculate a huge enough buff for saving response data temporarily */
2128         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2129                                                 I40E_MAX_CAP_ELE_NUM;
2130         buf = rte_zmalloc("i40e", len, 0);
2131         if (!buf) {
2132                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2133                 return I40E_ERR_NO_MEMORY;
2134         }
2135
2136         /* Get, parse the capabilities and save it to hw */
2137         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2138                         i40e_aqc_opc_list_func_capabilities, NULL);
2139         if (ret != I40E_SUCCESS)
2140                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2141
2142         /* Free the temporary buffer after being used */
2143         rte_free(buf);
2144
2145         return ret;
2146 }
2147
2148 static int
2149 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2150 {
2151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2152         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2153         uint16_t sum_queues = 0, sum_vsis, left_queues;
2154
2155         /* First check if FW support SRIOV */
2156         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2157                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2158                 return -EINVAL;
2159         }
2160
2161         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2162         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2163         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2164         /* Allocate queues for pf */
2165         if (hw->func_caps.rss) {
2166                 pf->flags |= I40E_FLAG_RSS;
2167                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2168                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2169                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2170         } else
2171                 pf->lan_nb_qps = 1;
2172         sum_queues = pf->lan_nb_qps;
2173         /* Default VSI is not counted in */
2174         sum_vsis = 0;
2175         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2176
2177         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2178                 pf->flags |= I40E_FLAG_SRIOV;
2179                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2180                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2181                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2182                                      "max supported %u.",
2183                                      dev->pci_dev->max_vfs,
2184                                      hw->func_caps.num_vfs);
2185                         return -EINVAL;
2186                 }
2187                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2188                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2189                                      "max support %u queues.",
2190                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2191                         return -EINVAL;
2192                 }
2193                 pf->vf_num = dev->pci_dev->max_vfs;
2194                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2195                 sum_vsis   += pf->vf_num;
2196                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2197                              pf->vf_num, pf->vf_nb_qps);
2198         } else
2199                 pf->vf_num = 0;
2200
2201         if (hw->func_caps.vmdq) {
2202                 pf->flags |= I40E_FLAG_VMDQ;
2203                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2204                 pf->max_nb_vmdq_vsi = 1;
2205                 /*
2206                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2207                  * later.
2208                  */
2209                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2210                 sum_vsis += pf->max_nb_vmdq_vsi;
2211         } else {
2212                 pf->vmdq_nb_qps = 0;
2213                 pf->max_nb_vmdq_vsi = 0;
2214         }
2215         pf->nb_cfg_vmdq_vsi = 0;
2216
2217         if (hw->func_caps.fd) {
2218                 pf->flags |= I40E_FLAG_FDIR;
2219                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2220                 /**
2221                  * Each flow director consumes one VSI and one queue,
2222                  * but can't calculate out predictably here.
2223                  */
2224         }
2225
2226         if (sum_vsis > pf->max_num_vsi ||
2227                 sum_queues > hw->func_caps.num_rx_qp) {
2228                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2229                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2230                              pf->max_num_vsi, sum_vsis);
2231                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2232                              hw->func_caps.num_rx_qp, sum_queues);
2233                 return -EINVAL;
2234         }
2235
2236         /* Adjust VMDQ setting to support as many VMs as possible */
2237         if (pf->flags & I40E_FLAG_VMDQ) {
2238                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2239
2240                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2241                                         pf->max_num_vsi - sum_vsis);
2242
2243                 /* Limit the max VMDQ number that rte_ether that can support  */
2244                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2245                                         ETH_64_POOLS - 1);
2246
2247                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2248                                 pf->max_nb_vmdq_vsi);
2249                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2250         }
2251
2252         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2253          * cause */
2254         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2255                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2256                              sum_vsis, hw->func_caps.num_msix_vectors);
2257                 return -EINVAL;
2258         }
2259         return I40E_SUCCESS;
2260 }
2261
2262 static int
2263 i40e_pf_get_switch_config(struct i40e_pf *pf)
2264 {
2265         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2266         struct i40e_aqc_get_switch_config_resp *switch_config;
2267         struct i40e_aqc_switch_config_element_resp *element;
2268         uint16_t start_seid = 0, num_reported;
2269         int ret;
2270
2271         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2272                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2273         if (!switch_config) {
2274                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2275                 return -ENOMEM;
2276         }
2277
2278         /* Get the switch configurations */
2279         ret = i40e_aq_get_switch_config(hw, switch_config,
2280                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2281         if (ret != I40E_SUCCESS) {
2282                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2283                 goto fail;
2284         }
2285         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2286         if (num_reported != 1) { /* The number should be 1 */
2287                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2288                 goto fail;
2289         }
2290
2291         /* Parse the switch configuration elements */
2292         element = &(switch_config->element[0]);
2293         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2294                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2295                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2296         } else
2297                 PMD_DRV_LOG(INFO, "Unknown element type");
2298
2299 fail:
2300         rte_free(switch_config);
2301
2302         return ret;
2303 }
2304
2305 static int
2306 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2307                         uint32_t num)
2308 {
2309         struct pool_entry *entry;
2310
2311         if (pool == NULL || num == 0)
2312                 return -EINVAL;
2313
2314         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2315         if (entry == NULL) {
2316                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2317                 return -ENOMEM;
2318         }
2319
2320         /* queue heap initialize */
2321         pool->num_free = num;
2322         pool->num_alloc = 0;
2323         pool->base = base;
2324         LIST_INIT(&pool->alloc_list);
2325         LIST_INIT(&pool->free_list);
2326
2327         /* Initialize element  */
2328         entry->base = 0;
2329         entry->len = num;
2330
2331         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2332         return 0;
2333 }
2334
2335 static void
2336 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2337 {
2338         struct pool_entry *entry;
2339
2340         if (pool == NULL)
2341                 return;
2342
2343         LIST_FOREACH(entry, &pool->alloc_list, next) {
2344                 LIST_REMOVE(entry, next);
2345                 rte_free(entry);
2346         }
2347
2348         LIST_FOREACH(entry, &pool->free_list, next) {
2349                 LIST_REMOVE(entry, next);
2350                 rte_free(entry);
2351         }
2352
2353         pool->num_free = 0;
2354         pool->num_alloc = 0;
2355         pool->base = 0;
2356         LIST_INIT(&pool->alloc_list);
2357         LIST_INIT(&pool->free_list);
2358 }
2359
2360 static int
2361 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2362                        uint32_t base)
2363 {
2364         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2365         uint32_t pool_offset;
2366         int insert;
2367
2368         if (pool == NULL) {
2369                 PMD_DRV_LOG(ERR, "Invalid parameter");
2370                 return -EINVAL;
2371         }
2372
2373         pool_offset = base - pool->base;
2374         /* Lookup in alloc list */
2375         LIST_FOREACH(entry, &pool->alloc_list, next) {
2376                 if (entry->base == pool_offset) {
2377                         valid_entry = entry;
2378                         LIST_REMOVE(entry, next);
2379                         break;
2380                 }
2381         }
2382
2383         /* Not find, return */
2384         if (valid_entry == NULL) {
2385                 PMD_DRV_LOG(ERR, "Failed to find entry");
2386                 return -EINVAL;
2387         }
2388
2389         /**
2390          * Found it, move it to free list  and try to merge.
2391          * In order to make merge easier, always sort it by qbase.
2392          * Find adjacent prev and last entries.
2393          */
2394         prev = next = NULL;
2395         LIST_FOREACH(entry, &pool->free_list, next) {
2396                 if (entry->base > valid_entry->base) {
2397                         next = entry;
2398                         break;
2399                 }
2400                 prev = entry;
2401         }
2402
2403         insert = 0;
2404         /* Try to merge with next one*/
2405         if (next != NULL) {
2406                 /* Merge with next one */
2407                 if (valid_entry->base + valid_entry->len == next->base) {
2408                         next->base = valid_entry->base;
2409                         next->len += valid_entry->len;
2410                         rte_free(valid_entry);
2411                         valid_entry = next;
2412                         insert = 1;
2413                 }
2414         }
2415
2416         if (prev != NULL) {
2417                 /* Merge with previous one */
2418                 if (prev->base + prev->len == valid_entry->base) {
2419                         prev->len += valid_entry->len;
2420                         /* If it merge with next one, remove next node */
2421                         if (insert == 1) {
2422                                 LIST_REMOVE(valid_entry, next);
2423                                 rte_free(valid_entry);
2424                         } else {
2425                                 rte_free(valid_entry);
2426                                 insert = 1;
2427                         }
2428                 }
2429         }
2430
2431         /* Not find any entry to merge, insert */
2432         if (insert == 0) {
2433                 if (prev != NULL)
2434                         LIST_INSERT_AFTER(prev, valid_entry, next);
2435                 else if (next != NULL)
2436                         LIST_INSERT_BEFORE(next, valid_entry, next);
2437                 else /* It's empty list, insert to head */
2438                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2439         }
2440
2441         pool->num_free += valid_entry->len;
2442         pool->num_alloc -= valid_entry->len;
2443
2444         return 0;
2445 }
2446
2447 static int
2448 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2449                        uint16_t num)
2450 {
2451         struct pool_entry *entry, *valid_entry;
2452
2453         if (pool == NULL || num == 0) {
2454                 PMD_DRV_LOG(ERR, "Invalid parameter");
2455                 return -EINVAL;
2456         }
2457
2458         if (pool->num_free < num) {
2459                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2460                             num, pool->num_free);
2461                 return -ENOMEM;
2462         }
2463
2464         valid_entry = NULL;
2465         /* Lookup  in free list and find most fit one */
2466         LIST_FOREACH(entry, &pool->free_list, next) {
2467                 if (entry->len >= num) {
2468                         /* Find best one */
2469                         if (entry->len == num) {
2470                                 valid_entry = entry;
2471                                 break;
2472                         }
2473                         if (valid_entry == NULL || valid_entry->len > entry->len)
2474                                 valid_entry = entry;
2475                 }
2476         }
2477
2478         /* Not find one to satisfy the request, return */
2479         if (valid_entry == NULL) {
2480                 PMD_DRV_LOG(ERR, "No valid entry found");
2481                 return -ENOMEM;
2482         }
2483         /**
2484          * The entry have equal queue number as requested,
2485          * remove it from alloc_list.
2486          */
2487         if (valid_entry->len == num) {
2488                 LIST_REMOVE(valid_entry, next);
2489         } else {
2490                 /**
2491                  * The entry have more numbers than requested,
2492                  * create a new entry for alloc_list and minus its
2493                  * queue base and number in free_list.
2494                  */
2495                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2496                 if (entry == NULL) {
2497                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2498                                     "resource pool");
2499                         return -ENOMEM;
2500                 }
2501                 entry->base = valid_entry->base;
2502                 entry->len = num;
2503                 valid_entry->base += num;
2504                 valid_entry->len -= num;
2505                 valid_entry = entry;
2506         }
2507
2508         /* Insert it into alloc list, not sorted */
2509         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2510
2511         pool->num_free -= valid_entry->len;
2512         pool->num_alloc += valid_entry->len;
2513
2514         return (valid_entry->base + pool->base);
2515 }
2516
2517 /**
2518  * bitmap_is_subset - Check whether src2 is subset of src1
2519  **/
2520 static inline int
2521 bitmap_is_subset(uint8_t src1, uint8_t src2)
2522 {
2523         return !((src1 ^ src2) & src2);
2524 }
2525
2526 static int
2527 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2528 {
2529         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2530
2531         /* If DCB is not supported, only default TC is supported */
2532         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2533                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2534                 return -EINVAL;
2535         }
2536
2537         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2538                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2539                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2540                             enabled_tcmap);
2541                 return -EINVAL;
2542         }
2543         return I40E_SUCCESS;
2544 }
2545
2546 int
2547 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2548                                 struct i40e_vsi_vlan_pvid_info *info)
2549 {
2550         struct i40e_hw *hw;
2551         struct i40e_vsi_context ctxt;
2552         uint8_t vlan_flags = 0;
2553         int ret;
2554
2555         if (vsi == NULL || info == NULL) {
2556                 PMD_DRV_LOG(ERR, "invalid parameters");
2557                 return I40E_ERR_PARAM;
2558         }
2559
2560         if (info->on) {
2561                 vsi->info.pvid = info->config.pvid;
2562                 /**
2563                  * If insert pvid is enabled, only tagged pkts are
2564                  * allowed to be sent out.
2565                  */
2566                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2567                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2568         } else {
2569                 vsi->info.pvid = 0;
2570                 if (info->config.reject.tagged == 0)
2571                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2572
2573                 if (info->config.reject.untagged == 0)
2574                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2575         }
2576         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2577                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2578         vsi->info.port_vlan_flags |= vlan_flags;
2579         vsi->info.valid_sections =
2580                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2581         memset(&ctxt, 0, sizeof(ctxt));
2582         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2583         ctxt.seid = vsi->seid;
2584
2585         hw = I40E_VSI_TO_HW(vsi);
2586         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2587         if (ret != I40E_SUCCESS)
2588                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2589
2590         return ret;
2591 }
2592
2593 static int
2594 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2595 {
2596         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2597         int i, ret;
2598         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2599
2600         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2601         if (ret != I40E_SUCCESS)
2602                 return ret;
2603
2604         if (!vsi->seid) {
2605                 PMD_DRV_LOG(ERR, "seid not valid");
2606                 return -EINVAL;
2607         }
2608
2609         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2610         tc_bw_data.tc_valid_bits = enabled_tcmap;
2611         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2612                 tc_bw_data.tc_bw_credits[i] =
2613                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2614
2615         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2616         if (ret != I40E_SUCCESS) {
2617                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2618                 return ret;
2619         }
2620
2621         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2622                                         sizeof(vsi->info.qs_handle));
2623         return I40E_SUCCESS;
2624 }
2625
2626 static int
2627 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2628                                  struct i40e_aqc_vsi_properties_data *info,
2629                                  uint8_t enabled_tcmap)
2630 {
2631         int ret, total_tc = 0, i;
2632         uint16_t qpnum_per_tc, bsf, qp_idx;
2633
2634         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2635         if (ret != I40E_SUCCESS)
2636                 return ret;
2637
2638         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2639                 if (enabled_tcmap & (1 << i))
2640                         total_tc++;
2641         vsi->enabled_tc = enabled_tcmap;
2642
2643         /* Number of queues per enabled TC */
2644         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2645         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2646         bsf = rte_bsf32(qpnum_per_tc);
2647
2648         /* Adjust the queue number to actual queues that can be applied */
2649         vsi->nb_qps = qpnum_per_tc * total_tc;
2650
2651         /**
2652          * Configure TC and queue mapping parameters, for enabled TC,
2653          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2654          * default queue will serve it.
2655          */
2656         qp_idx = 0;
2657         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2658                 if (vsi->enabled_tc & (1 << i)) {
2659                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2660                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2661                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2662                         qp_idx += qpnum_per_tc;
2663                 } else
2664                         info->tc_mapping[i] = 0;
2665         }
2666
2667         /* Associate queue number with VSI */
2668         if (vsi->type == I40E_VSI_SRIOV) {
2669                 info->mapping_flags |=
2670                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2671                 for (i = 0; i < vsi->nb_qps; i++)
2672                         info->queue_mapping[i] =
2673                                 rte_cpu_to_le_16(vsi->base_queue + i);
2674         } else {
2675                 info->mapping_flags |=
2676                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2677                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2678         }
2679         info->valid_sections |=
2680                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2681
2682         return I40E_SUCCESS;
2683 }
2684
2685 static int
2686 i40e_veb_release(struct i40e_veb *veb)
2687 {
2688         struct i40e_vsi *vsi;
2689         struct i40e_hw *hw;
2690
2691         if (veb == NULL || veb->associate_vsi == NULL)
2692                 return -EINVAL;
2693
2694         if (!TAILQ_EMPTY(&veb->head)) {
2695                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2696                 return -EACCES;
2697         }
2698
2699         vsi = veb->associate_vsi;
2700         hw = I40E_VSI_TO_HW(vsi);
2701
2702         vsi->uplink_seid = veb->uplink_seid;
2703         i40e_aq_delete_element(hw, veb->seid, NULL);
2704         rte_free(veb);
2705         vsi->veb = NULL;
2706         return I40E_SUCCESS;
2707 }
2708
2709 /* Setup a veb */
2710 static struct i40e_veb *
2711 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2712 {
2713         struct i40e_veb *veb;
2714         int ret;
2715         struct i40e_hw *hw;
2716
2717         if (NULL == pf || vsi == NULL) {
2718                 PMD_DRV_LOG(ERR, "veb setup failed, "
2719                             "associated VSI shouldn't null");
2720                 return NULL;
2721         }
2722         hw = I40E_PF_TO_HW(pf);
2723
2724         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2725         if (!veb) {
2726                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2727                 goto fail;
2728         }
2729
2730         veb->associate_vsi = vsi;
2731         TAILQ_INIT(&veb->head);
2732         veb->uplink_seid = vsi->uplink_seid;
2733
2734         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2735                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2736
2737         if (ret != I40E_SUCCESS) {
2738                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2739                             hw->aq.asq_last_status);
2740                 goto fail;
2741         }
2742
2743         /* get statistics index */
2744         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2745                                 &veb->stats_idx, NULL, NULL, NULL);
2746         if (ret != I40E_SUCCESS) {
2747                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2748                             hw->aq.asq_last_status);
2749                 goto fail;
2750         }
2751
2752         /* Get VEB bandwidth, to be implemented */
2753         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2754         vsi->uplink_seid = veb->seid;
2755
2756         return veb;
2757 fail:
2758         rte_free(veb);
2759         return NULL;
2760 }
2761
2762 int
2763 i40e_vsi_release(struct i40e_vsi *vsi)
2764 {
2765         struct i40e_pf *pf;
2766         struct i40e_hw *hw;
2767         struct i40e_vsi_list *vsi_list;
2768         int ret;
2769         struct i40e_mac_filter *f;
2770
2771         if (!vsi)
2772                 return I40E_SUCCESS;
2773
2774         pf = I40E_VSI_TO_PF(vsi);
2775         hw = I40E_VSI_TO_HW(vsi);
2776
2777         /* VSI has child to attach, release child first */
2778         if (vsi->veb) {
2779                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2780                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2781                                 return -1;
2782                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2783                 }
2784                 i40e_veb_release(vsi->veb);
2785         }
2786
2787         /* Remove all macvlan filters of the VSI */
2788         i40e_vsi_remove_all_macvlan_filter(vsi);
2789         TAILQ_FOREACH(f, &vsi->mac_list, next)
2790                 rte_free(f);
2791
2792         if (vsi->type != I40E_VSI_MAIN) {
2793                 /* Remove vsi from parent's sibling list */
2794                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2795                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2796                         return I40E_ERR_PARAM;
2797                 }
2798                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2799                                 &vsi->sib_vsi_list, list);
2800
2801                 /* Remove all switch element of the VSI */
2802                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2803                 if (ret != I40E_SUCCESS)
2804                         PMD_DRV_LOG(ERR, "Failed to delete element");
2805         }
2806         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2807
2808         if (vsi->type != I40E_VSI_SRIOV)
2809                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2810         rte_free(vsi);
2811
2812         return I40E_SUCCESS;
2813 }
2814
2815 static int
2816 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2817 {
2818         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2819         struct i40e_aqc_remove_macvlan_element_data def_filter;
2820         struct i40e_mac_filter_info filter;
2821         int ret;
2822
2823         if (vsi->type != I40E_VSI_MAIN)
2824                 return I40E_ERR_CONFIG;
2825         memset(&def_filter, 0, sizeof(def_filter));
2826         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2827                                         ETH_ADDR_LEN);
2828         def_filter.vlan_tag = 0;
2829         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2830                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2831         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2832         if (ret != I40E_SUCCESS) {
2833                 struct i40e_mac_filter *f;
2834                 struct ether_addr *mac;
2835
2836                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2837                             "macvlan filter");
2838                 /* It needs to add the permanent mac into mac list */
2839                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2840                 if (f == NULL) {
2841                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2842                         return I40E_ERR_NO_MEMORY;
2843                 }
2844                 mac = &f->mac_info.mac_addr;
2845                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2846                                 ETH_ADDR_LEN);
2847                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2848                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2849                 vsi->mac_num++;
2850
2851                 return ret;
2852         }
2853         (void)rte_memcpy(&filter.mac_addr,
2854                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2855         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2856         return i40e_vsi_add_mac(vsi, &filter);
2857 }
2858
2859 static int
2860 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2861 {
2862         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2863         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2864         struct i40e_hw *hw = &vsi->adapter->hw;
2865         i40e_status ret;
2866         int i;
2867
2868         memset(&bw_config, 0, sizeof(bw_config));
2869         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2870         if (ret != I40E_SUCCESS) {
2871                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2872                             hw->aq.asq_last_status);
2873                 return ret;
2874         }
2875
2876         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2877         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2878                                         &ets_sla_config, NULL);
2879         if (ret != I40E_SUCCESS) {
2880                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2881                             "configuration %u", hw->aq.asq_last_status);
2882                 return ret;
2883         }
2884
2885         /* Not store the info yet, just print out */
2886         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2887         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2888         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2889                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2890                             ets_sla_config.share_credits[i]);
2891                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2892                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2893                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2894                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2895                             (i * 4));
2896         }
2897
2898         return 0;
2899 }
2900
2901 /* Setup a VSI */
2902 struct i40e_vsi *
2903 i40e_vsi_setup(struct i40e_pf *pf,
2904                enum i40e_vsi_type type,
2905                struct i40e_vsi *uplink_vsi,
2906                uint16_t user_param)
2907 {
2908         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2909         struct i40e_vsi *vsi;
2910         struct i40e_mac_filter_info filter;
2911         int ret;
2912         struct i40e_vsi_context ctxt;
2913         struct ether_addr broadcast =
2914                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
2915
2916         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
2917                 PMD_DRV_LOG(ERR, "VSI setup failed, "
2918                             "VSI link shouldn't be NULL");
2919                 return NULL;
2920         }
2921
2922         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
2923                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
2924                             "uplink VSI should be NULL");
2925                 return NULL;
2926         }
2927
2928         /* If uplink vsi didn't setup VEB, create one first */
2929         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
2930                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
2931
2932                 if (NULL == uplink_vsi->veb) {
2933                         PMD_DRV_LOG(ERR, "VEB setup failed");
2934                         return NULL;
2935                 }
2936         }
2937
2938         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
2939         if (!vsi) {
2940                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
2941                 return NULL;
2942         }
2943         TAILQ_INIT(&vsi->mac_list);
2944         vsi->type = type;
2945         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
2946         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
2947         vsi->parent_vsi = uplink_vsi;
2948         vsi->user_param = user_param;
2949         /* Allocate queues */
2950         switch (vsi->type) {
2951         case I40E_VSI_MAIN  :
2952                 vsi->nb_qps = pf->lan_nb_qps;
2953                 break;
2954         case I40E_VSI_SRIOV :
2955                 vsi->nb_qps = pf->vf_nb_qps;
2956                 break;
2957         case I40E_VSI_VMDQ2:
2958                 vsi->nb_qps = pf->vmdq_nb_qps;
2959                 break;
2960         case I40E_VSI_FDIR:
2961                 vsi->nb_qps = pf->fdir_nb_qps;
2962                 break;
2963         default:
2964                 goto fail_mem;
2965         }
2966         /*
2967          * The filter status descriptor is reported in rx queue 0,
2968          * while the tx queue for fdir filter programming has no
2969          * such constraints, can be non-zero queues.
2970          * To simplify it, choose FDIR vsi use queue 0 pair.
2971          * To make sure it will use queue 0 pair, queue allocation
2972          * need be done before this function is called
2973          */
2974         if (type != I40E_VSI_FDIR) {
2975                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
2976                         if (ret < 0) {
2977                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
2978                                                 vsi->seid, ret);
2979                                 goto fail_mem;
2980                         }
2981                         vsi->base_queue = ret;
2982         } else
2983                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
2984
2985         /* VF has MSIX interrupt in VF range, don't allocate here */
2986         if (type != I40E_VSI_SRIOV) {
2987                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
2988                 if (ret < 0) {
2989                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
2990                         goto fail_queue_alloc;
2991                 }
2992                 vsi->msix_intr = ret;
2993         } else
2994                 vsi->msix_intr = 0;
2995         /* Add VSI */
2996         if (type == I40E_VSI_MAIN) {
2997                 /* For main VSI, no need to add since it's default one */
2998                 vsi->uplink_seid = pf->mac_seid;
2999                 vsi->seid = pf->main_vsi_seid;
3000                 /* Bind queues with specific MSIX interrupt */
3001                 /**
3002                  * Needs 2 interrupt at least, one for misc cause which will
3003                  * enabled from OS side, Another for queues binding the
3004                  * interrupt from device side only.
3005                  */
3006
3007                 /* Get default VSI parameters from hardware */
3008                 memset(&ctxt, 0, sizeof(ctxt));
3009                 ctxt.seid = vsi->seid;
3010                 ctxt.pf_num = hw->pf_id;
3011                 ctxt.uplink_seid = vsi->uplink_seid;
3012                 ctxt.vf_num = 0;
3013                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3014                 if (ret != I40E_SUCCESS) {
3015                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3016                         goto fail_msix_alloc;
3017                 }
3018                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3019                         sizeof(struct i40e_aqc_vsi_properties_data));
3020                 vsi->vsi_id = ctxt.vsi_number;
3021                 vsi->info.valid_sections = 0;
3022
3023                 /* Configure tc, enabled TC0 only */
3024                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3025                         I40E_SUCCESS) {
3026                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3027                         goto fail_msix_alloc;
3028                 }
3029
3030                 /* TC, queue mapping */
3031                 memset(&ctxt, 0, sizeof(ctxt));
3032                 vsi->info.valid_sections |=
3033                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3034                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3035                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3036                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3037                         sizeof(struct i40e_aqc_vsi_properties_data));
3038                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3039                                                 I40E_DEFAULT_TCMAP);
3040                 if (ret != I40E_SUCCESS) {
3041                         PMD_DRV_LOG(ERR, "Failed to configure "
3042                                     "TC queue mapping");
3043                         goto fail_msix_alloc;
3044                 }
3045                 ctxt.seid = vsi->seid;
3046                 ctxt.pf_num = hw->pf_id;
3047                 ctxt.uplink_seid = vsi->uplink_seid;
3048                 ctxt.vf_num = 0;
3049
3050                 /* Update VSI parameters */
3051                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3052                 if (ret != I40E_SUCCESS) {
3053                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3054                         goto fail_msix_alloc;
3055                 }
3056
3057                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3058                                                 sizeof(vsi->info.tc_mapping));
3059                 (void)rte_memcpy(&vsi->info.queue_mapping,
3060                                 &ctxt.info.queue_mapping,
3061                         sizeof(vsi->info.queue_mapping));
3062                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3063                 vsi->info.valid_sections = 0;
3064
3065                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3066                                 ETH_ADDR_LEN);
3067
3068                 /**
3069                  * Updating default filter settings are necessary to prevent
3070                  * reception of tagged packets.
3071                  * Some old firmware configurations load a default macvlan
3072                  * filter which accepts both tagged and untagged packets.
3073                  * The updating is to use a normal filter instead if needed.
3074                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3075                  * The firmware with correct configurations load the default
3076                  * macvlan filter which is expected and cannot be removed.
3077                  */
3078                 i40e_update_default_filter_setting(vsi);
3079                 i40e_config_qinq(hw, vsi);
3080         } else if (type == I40E_VSI_SRIOV) {
3081                 memset(&ctxt, 0, sizeof(ctxt));
3082                 /**
3083                  * For other VSI, the uplink_seid equals to uplink VSI's
3084                  * uplink_seid since they share same VEB
3085                  */
3086                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3087                 ctxt.pf_num = hw->pf_id;
3088                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3089                 ctxt.uplink_seid = vsi->uplink_seid;
3090                 ctxt.connection_type = 0x1;
3091                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3092
3093                 /**
3094                  * Do not configure switch ID to enable VEB switch by
3095                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3096                  * if the source mac address of packet sent from VF is not
3097                  * listed in the VEB's mac table, the VEB will switch the
3098                  * packet back to the VF. Need to enable it when HW issue
3099                  * is fixed.
3100                  */
3101
3102                 /* Configure port/vlan */
3103                 ctxt.info.valid_sections |=
3104                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3105                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3106                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3107                                                 I40E_DEFAULT_TCMAP);
3108                 if (ret != I40E_SUCCESS) {
3109                         PMD_DRV_LOG(ERR, "Failed to configure "
3110                                     "TC queue mapping");
3111                         goto fail_msix_alloc;
3112                 }
3113                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3114                 ctxt.info.valid_sections |=
3115                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3116                 /**
3117                  * Since VSI is not created yet, only configure parameter,
3118                  * will add vsi below.
3119                  */
3120
3121                 i40e_config_qinq(hw, vsi);
3122         } else if (type == I40E_VSI_VMDQ2) {
3123                 memset(&ctxt, 0, sizeof(ctxt));
3124                 /*
3125                  * For other VSI, the uplink_seid equals to uplink VSI's
3126                  * uplink_seid since they share same VEB
3127                  */
3128                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3129                 ctxt.pf_num = hw->pf_id;
3130                 ctxt.vf_num = 0;
3131                 ctxt.uplink_seid = vsi->uplink_seid;
3132                 ctxt.connection_type = 0x1;
3133                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3134
3135                 ctxt.info.valid_sections |=
3136                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3137                 /* user_param carries flag to enable loop back */
3138                 if (user_param) {
3139                         ctxt.info.switch_id =
3140                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3141                         ctxt.info.switch_id |=
3142                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3143                 }
3144
3145                 /* Configure port/vlan */
3146                 ctxt.info.valid_sections |=
3147                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3148                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3149                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3150                                                 I40E_DEFAULT_TCMAP);
3151                 if (ret != I40E_SUCCESS) {
3152                         PMD_DRV_LOG(ERR, "Failed to configure "
3153                                         "TC queue mapping");
3154                         goto fail_msix_alloc;
3155                 }
3156                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3157                 ctxt.info.valid_sections |=
3158                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3159         } else if (type == I40E_VSI_FDIR) {
3160                 memset(&ctxt, 0, sizeof(ctxt));
3161                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3162                 ctxt.pf_num = hw->pf_id;
3163                 ctxt.vf_num = 0;
3164                 ctxt.uplink_seid = vsi->uplink_seid;
3165                 ctxt.connection_type = 0x1;     /* regular data port */
3166                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3167                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3168                                                 I40E_DEFAULT_TCMAP);
3169                 if (ret != I40E_SUCCESS) {
3170                         PMD_DRV_LOG(ERR, "Failed to configure "
3171                                         "TC queue mapping.");
3172                         goto fail_msix_alloc;
3173                 }
3174                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3175                 ctxt.info.valid_sections |=
3176                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3177         } else {
3178                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3179                 goto fail_msix_alloc;
3180         }
3181
3182         if (vsi->type != I40E_VSI_MAIN) {
3183                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3184                 if (ret != I40E_SUCCESS) {
3185                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3186                                     hw->aq.asq_last_status);
3187                         goto fail_msix_alloc;
3188                 }
3189                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3190                 vsi->info.valid_sections = 0;
3191                 vsi->seid = ctxt.seid;
3192                 vsi->vsi_id = ctxt.vsi_number;
3193                 vsi->sib_vsi_list.vsi = vsi;
3194                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3195                                 &vsi->sib_vsi_list, list);
3196         }
3197
3198         /* MAC/VLAN configuration */
3199         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3200         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3201
3202         ret = i40e_vsi_add_mac(vsi, &filter);
3203         if (ret != I40E_SUCCESS) {
3204                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3205                 goto fail_msix_alloc;
3206         }
3207
3208         /* Get VSI BW information */
3209         i40e_vsi_dump_bw_config(vsi);
3210         return vsi;
3211 fail_msix_alloc:
3212         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3213 fail_queue_alloc:
3214         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3215 fail_mem:
3216         rte_free(vsi);
3217         return NULL;
3218 }
3219
3220 /* Configure vlan stripping on or off */
3221 int
3222 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3223 {
3224         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3225         struct i40e_vsi_context ctxt;
3226         uint8_t vlan_flags;
3227         int ret = I40E_SUCCESS;
3228
3229         /* Check if it has been already on or off */
3230         if (vsi->info.valid_sections &
3231                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3232                 if (on) {
3233                         if ((vsi->info.port_vlan_flags &
3234                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3235                                 return 0; /* already on */
3236                 } else {
3237                         if ((vsi->info.port_vlan_flags &
3238                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3239                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3240                                 return 0; /* already off */
3241                 }
3242         }
3243
3244         if (on)
3245                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3246         else
3247                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3248         vsi->info.valid_sections =
3249                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3250         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3251         vsi->info.port_vlan_flags |= vlan_flags;
3252         ctxt.seid = vsi->seid;
3253         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3254         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3255         if (ret)
3256                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3257                             on ? "enable" : "disable");
3258
3259         return ret;
3260 }
3261
3262 static int
3263 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3264 {
3265         struct rte_eth_dev_data *data = dev->data;
3266         int ret;
3267
3268         /* Apply vlan offload setting */
3269         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3270
3271         /* Apply double-vlan setting, not implemented yet */
3272
3273         /* Apply pvid setting */
3274         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3275                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3276         if (ret)
3277                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3278
3279         return ret;
3280 }
3281
3282 static int
3283 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3284 {
3285         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3286
3287         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3288 }
3289
3290 static int
3291 i40e_update_flow_control(struct i40e_hw *hw)
3292 {
3293 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3294         struct i40e_link_status link_status;
3295         uint32_t rxfc = 0, txfc = 0, reg;
3296         uint8_t an_info;
3297         int ret;
3298
3299         memset(&link_status, 0, sizeof(link_status));
3300         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3301         if (ret != I40E_SUCCESS) {
3302                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3303                 goto write_reg; /* Disable flow control */
3304         }
3305
3306         an_info = hw->phy.link_info.an_info;
3307         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3308                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3309                 ret = I40E_ERR_NOT_READY;
3310                 goto write_reg; /* Disable flow control */
3311         }
3312         /**
3313          * If link auto negotiation is enabled, flow control needs to
3314          * be configured according to it
3315          */
3316         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3317         case I40E_LINK_PAUSE_RXTX:
3318                 rxfc = 1;
3319                 txfc = 1;
3320                 hw->fc.current_mode = I40E_FC_FULL;
3321                 break;
3322         case I40E_AQ_LINK_PAUSE_RX:
3323                 rxfc = 1;
3324                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3325                 break;
3326         case I40E_AQ_LINK_PAUSE_TX:
3327                 txfc = 1;
3328                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3329                 break;
3330         default:
3331                 hw->fc.current_mode = I40E_FC_NONE;
3332                 break;
3333         }
3334
3335 write_reg:
3336         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3337                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3338         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3339         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3340         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3341         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3342
3343         return ret;
3344 }
3345
3346 /* PF setup */
3347 static int
3348 i40e_pf_setup(struct i40e_pf *pf)
3349 {
3350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3351         struct i40e_filter_control_settings settings;
3352         struct i40e_vsi *vsi;
3353         int ret;
3354
3355         /* Clear all stats counters */
3356         pf->offset_loaded = FALSE;
3357         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3358         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3359
3360         ret = i40e_pf_get_switch_config(pf);
3361         if (ret != I40E_SUCCESS) {
3362                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3363                 return ret;
3364         }
3365         if (pf->flags & I40E_FLAG_FDIR) {
3366                 /* make queue allocated first, let FDIR use queue pair 0*/
3367                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3368                 if (ret != I40E_FDIR_QUEUE_ID) {
3369                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3370                                     " ret =%d", ret);
3371                         pf->flags &= ~I40E_FLAG_FDIR;
3372                 }
3373         }
3374         /*  main VSI setup */
3375         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3376         if (!vsi) {
3377                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3378                 return I40E_ERR_NOT_READY;
3379         }
3380         pf->main_vsi = vsi;
3381
3382         /* Configure filter control */
3383         memset(&settings, 0, sizeof(settings));
3384         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3385                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3386         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3387                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3388         else {
3389                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3390                                                 hw->func_caps.rss_table_size);
3391                 return I40E_ERR_PARAM;
3392         }
3393         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3394                         "size: %u\n", hw->func_caps.rss_table_size);
3395         pf->hash_lut_size = hw->func_caps.rss_table_size;
3396
3397         /* Enable ethtype and macvlan filters */
3398         settings.enable_ethtype = TRUE;
3399         settings.enable_macvlan = TRUE;
3400         ret = i40e_set_filter_control(hw, &settings);
3401         if (ret)
3402                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3403                                                                 ret);
3404
3405         /* Update flow control according to the auto negotiation */
3406         i40e_update_flow_control(hw);
3407
3408         return I40E_SUCCESS;
3409 }
3410
3411 int
3412 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3413 {
3414         uint32_t reg;
3415         uint16_t j;
3416
3417         /**
3418          * Set or clear TX Queue Disable flags,
3419          * which is required by hardware.
3420          */
3421         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3422         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3423
3424         /* Wait until the request is finished */
3425         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3426                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3427                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3428                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3429                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3430                                                         & 0x1))) {
3431                         break;
3432                 }
3433         }
3434         if (on) {
3435                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3436                         return I40E_SUCCESS; /* already on, skip next steps */
3437
3438                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3439                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3440         } else {
3441                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3442                         return I40E_SUCCESS; /* already off, skip next steps */
3443                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3444         }
3445         /* Write the register */
3446         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3447         /* Check the result */
3448         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3449                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3450                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3451                 if (on) {
3452                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3453                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3454                                 break;
3455                 } else {
3456                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3457                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3458                                 break;
3459                 }
3460         }
3461         /* Check if it is timeout */
3462         if (j >= I40E_CHK_Q_ENA_COUNT) {
3463                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3464                             (on ? "enable" : "disable"), q_idx);
3465                 return I40E_ERR_TIMEOUT;
3466         }
3467
3468         return I40E_SUCCESS;
3469 }
3470
3471 /* Swith on or off the tx queues */
3472 static int
3473 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3474 {
3475         struct rte_eth_dev_data *dev_data = pf->dev_data;
3476         struct i40e_tx_queue *txq;
3477         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3478         uint16_t i;
3479         int ret;
3480
3481         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3482                 txq = dev_data->tx_queues[i];
3483                 /* Don't operate the queue if not configured or
3484                  * if starting only per queue */
3485                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3486                         continue;
3487                 if (on)
3488                         ret = i40e_dev_tx_queue_start(dev, i);
3489                 else
3490                         ret = i40e_dev_tx_queue_stop(dev, i);
3491                 if ( ret != I40E_SUCCESS)
3492                         return ret;
3493         }
3494
3495         return I40E_SUCCESS;
3496 }
3497
3498 int
3499 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3500 {
3501         uint32_t reg;
3502         uint16_t j;
3503
3504         /* Wait until the request is finished */
3505         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3506                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3507                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3508                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3509                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3510                         break;
3511         }
3512
3513         if (on) {
3514                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3515                         return I40E_SUCCESS; /* Already on, skip next steps */
3516                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3517         } else {
3518                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3519                         return I40E_SUCCESS; /* Already off, skip next steps */
3520                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3521         }
3522
3523         /* Write the register */
3524         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3525         /* Check the result */
3526         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3527                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3528                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3529                 if (on) {
3530                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3531                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3532                                 break;
3533                 } else {
3534                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3535                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3536                                 break;
3537                 }
3538         }
3539
3540         /* Check if it is timeout */
3541         if (j >= I40E_CHK_Q_ENA_COUNT) {
3542                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3543                             (on ? "enable" : "disable"), q_idx);
3544                 return I40E_ERR_TIMEOUT;
3545         }
3546
3547         return I40E_SUCCESS;
3548 }
3549 /* Switch on or off the rx queues */
3550 static int
3551 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3552 {
3553         struct rte_eth_dev_data *dev_data = pf->dev_data;
3554         struct i40e_rx_queue *rxq;
3555         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3556         uint16_t i;
3557         int ret;
3558
3559         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3560                 rxq = dev_data->rx_queues[i];
3561                 /* Don't operate the queue if not configured or
3562                  * if starting only per queue */
3563                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3564                         continue;
3565                 if (on)
3566                         ret = i40e_dev_rx_queue_start(dev, i);
3567                 else
3568                         ret = i40e_dev_rx_queue_stop(dev, i);
3569                 if (ret != I40E_SUCCESS)
3570                         return ret;
3571         }
3572
3573         return I40E_SUCCESS;
3574 }
3575
3576 /* Switch on or off all the rx/tx queues */
3577 int
3578 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3579 {
3580         int ret;
3581
3582         if (on) {
3583                 /* enable rx queues before enabling tx queues */
3584                 ret = i40e_dev_switch_rx_queues(pf, on);
3585                 if (ret) {
3586                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3587                         return ret;
3588                 }
3589                 ret = i40e_dev_switch_tx_queues(pf, on);
3590         } else {
3591                 /* Stop tx queues before stopping rx queues */
3592                 ret = i40e_dev_switch_tx_queues(pf, on);
3593                 if (ret) {
3594                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3595                         return ret;
3596                 }
3597                 ret = i40e_dev_switch_rx_queues(pf, on);
3598         }
3599
3600         return ret;
3601 }
3602
3603 /* Initialize VSI for TX */
3604 static int
3605 i40e_dev_tx_init(struct i40e_pf *pf)
3606 {
3607         struct rte_eth_dev_data *data = pf->dev_data;
3608         uint16_t i;
3609         uint32_t ret = I40E_SUCCESS;
3610         struct i40e_tx_queue *txq;
3611
3612         for (i = 0; i < data->nb_tx_queues; i++) {
3613                 txq = data->tx_queues[i];
3614                 if (!txq || !txq->q_set)
3615                         continue;
3616                 ret = i40e_tx_queue_init(txq);
3617                 if (ret != I40E_SUCCESS)
3618                         break;
3619         }
3620
3621         return ret;
3622 }
3623
3624 /* Initialize VSI for RX */
3625 static int
3626 i40e_dev_rx_init(struct i40e_pf *pf)
3627 {
3628         struct rte_eth_dev_data *data = pf->dev_data;
3629         int ret = I40E_SUCCESS;
3630         uint16_t i;
3631         struct i40e_rx_queue *rxq;
3632
3633         i40e_pf_config_mq_rx(pf);
3634         for (i = 0; i < data->nb_rx_queues; i++) {
3635                 rxq = data->rx_queues[i];
3636                 if (!rxq || !rxq->q_set)
3637                         continue;
3638
3639                 ret = i40e_rx_queue_init(rxq);
3640                 if (ret != I40E_SUCCESS) {
3641                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3642                                     "initialization");
3643                         break;
3644                 }
3645         }
3646
3647         return ret;
3648 }
3649
3650 static int
3651 i40e_dev_rxtx_init(struct i40e_pf *pf)
3652 {
3653         int err;
3654
3655         err = i40e_dev_tx_init(pf);
3656         if (err) {
3657                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3658                 return err;
3659         }
3660         err = i40e_dev_rx_init(pf);
3661         if (err) {
3662                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3663                 return err;
3664         }
3665
3666         return err;
3667 }
3668
3669 static int
3670 i40e_vmdq_setup(struct rte_eth_dev *dev)
3671 {
3672         struct rte_eth_conf *conf = &dev->data->dev_conf;
3673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3674         int i, err, conf_vsis, j, loop;
3675         struct i40e_vsi *vsi;
3676         struct i40e_vmdq_info *vmdq_info;
3677         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3678         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3679
3680         /*
3681          * Disable interrupt to avoid message from VF. Furthermore, it will
3682          * avoid race condition in VSI creation/destroy.
3683          */
3684         i40e_pf_disable_irq0(hw);
3685
3686         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3687                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3688                 return -ENOTSUP;
3689         }
3690
3691         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3692         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3693                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3694                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3695                         pf->max_nb_vmdq_vsi);
3696                 return -ENOTSUP;
3697         }
3698
3699         if (pf->vmdq != NULL) {
3700                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3701                 return 0;
3702         }
3703
3704         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3705                                 sizeof(*vmdq_info) * conf_vsis, 0);
3706
3707         if (pf->vmdq == NULL) {
3708                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3709                 return -ENOMEM;
3710         }
3711
3712         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3713
3714         /* Create VMDQ VSI */
3715         for (i = 0; i < conf_vsis; i++) {
3716                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3717                                 vmdq_conf->enable_loop_back);
3718                 if (vsi == NULL) {
3719                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3720                         err = -1;
3721                         goto err_vsi_setup;
3722                 }
3723                 vmdq_info = &pf->vmdq[i];
3724                 vmdq_info->pf = pf;
3725                 vmdq_info->vsi = vsi;
3726         }
3727         pf->nb_cfg_vmdq_vsi = conf_vsis;
3728
3729         /* Configure Vlan */
3730         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3731         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3732                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3733                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3734                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3735                                         vmdq_conf->pool_map[i].vlan_id, j);
3736
3737                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3738                                                 vmdq_conf->pool_map[i].vlan_id);
3739                                 if (err) {
3740                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3741                                         err = -1;
3742                                         goto err_vsi_setup;
3743                                 }
3744                         }
3745                 }
3746         }
3747
3748         i40e_pf_enable_irq0(hw);
3749
3750         return 0;
3751
3752 err_vsi_setup:
3753         for (i = 0; i < conf_vsis; i++)
3754                 if (pf->vmdq[i].vsi == NULL)
3755                         break;
3756                 else
3757                         i40e_vsi_release(pf->vmdq[i].vsi);
3758
3759         rte_free(pf->vmdq);
3760         pf->vmdq = NULL;
3761         i40e_pf_enable_irq0(hw);
3762         return err;
3763 }
3764
3765 static void
3766 i40e_stat_update_32(struct i40e_hw *hw,
3767                    uint32_t reg,
3768                    bool offset_loaded,
3769                    uint64_t *offset,
3770                    uint64_t *stat)
3771 {
3772         uint64_t new_data;
3773
3774         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3775         if (!offset_loaded)
3776                 *offset = new_data;
3777
3778         if (new_data >= *offset)
3779                 *stat = (uint64_t)(new_data - *offset);
3780         else
3781                 *stat = (uint64_t)((new_data +
3782                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3783 }
3784
3785 static void
3786 i40e_stat_update_48(struct i40e_hw *hw,
3787                    uint32_t hireg,
3788                    uint32_t loreg,
3789                    bool offset_loaded,
3790                    uint64_t *offset,
3791                    uint64_t *stat)
3792 {
3793         uint64_t new_data;
3794
3795         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3796         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3797                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3798
3799         if (!offset_loaded)
3800                 *offset = new_data;
3801
3802         if (new_data >= *offset)
3803                 *stat = new_data - *offset;
3804         else
3805                 *stat = (uint64_t)((new_data +
3806                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3807
3808         *stat &= I40E_48_BIT_MASK;
3809 }
3810
3811 /* Disable IRQ0 */
3812 void
3813 i40e_pf_disable_irq0(struct i40e_hw *hw)
3814 {
3815         /* Disable all interrupt types */
3816         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3817         I40E_WRITE_FLUSH(hw);
3818 }
3819
3820 /* Enable IRQ0 */
3821 void
3822 i40e_pf_enable_irq0(struct i40e_hw *hw)
3823 {
3824         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3825                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3826                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3827                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3828         I40E_WRITE_FLUSH(hw);
3829 }
3830
3831 static void
3832 i40e_pf_config_irq0(struct i40e_hw *hw)
3833 {
3834         /* read pending request and disable first */
3835         i40e_pf_disable_irq0(hw);
3836         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3837         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3838                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3839
3840         /* Link no queues with irq0 */
3841         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3842                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3843 }
3844
3845 static void
3846 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3847 {
3848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3850         int i;
3851         uint16_t abs_vf_id;
3852         uint32_t index, offset, val;
3853
3854         if (!pf->vfs)
3855                 return;
3856         /**
3857          * Try to find which VF trigger a reset, use absolute VF id to access
3858          * since the reg is global register.
3859          */
3860         for (i = 0; i < pf->vf_num; i++) {
3861                 abs_vf_id = hw->func_caps.vf_base_id + i;
3862                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3863                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3864                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3865                 /* VFR event occured */
3866                 if (val & (0x1 << offset)) {
3867                         int ret;
3868
3869                         /* Clear the event first */
3870                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3871                                                         (0x1 << offset));
3872                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3873                         /**
3874                          * Only notify a VF reset event occured,
3875                          * don't trigger another SW reset
3876                          */
3877                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3878                         if (ret != I40E_SUCCESS)
3879                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3880                 }
3881         }
3882 }
3883
3884 static void
3885 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3886 {
3887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3888         struct i40e_arq_event_info info;
3889         uint16_t pending, opcode;
3890         int ret;
3891
3892         info.buf_len = I40E_AQ_BUF_SZ;
3893         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3894         if (!info.msg_buf) {
3895                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3896                 return;
3897         }
3898
3899         pending = 1;
3900         while (pending) {
3901                 ret = i40e_clean_arq_element(hw, &info, &pending);
3902
3903                 if (ret != I40E_SUCCESS) {
3904                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3905                                     "aq_err: %u", hw->aq.asq_last_status);
3906                         break;
3907                 }
3908                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3909
3910                 switch (opcode) {
3911                 case i40e_aqc_opc_send_msg_to_pf:
3912                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
3913                         i40e_pf_host_handle_vf_msg(dev,
3914                                         rte_le_to_cpu_16(info.desc.retval),
3915                                         rte_le_to_cpu_32(info.desc.cookie_high),
3916                                         rte_le_to_cpu_32(info.desc.cookie_low),
3917                                         info.msg_buf,
3918                                         info.msg_len);
3919                         break;
3920                 default:
3921                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
3922                                     opcode);
3923                         break;
3924                 }
3925         }
3926         rte_free(info.msg_buf);
3927 }
3928
3929 /*
3930  * Interrupt handler is registered as the alarm callback for handling LSC
3931  * interrupt in a definite of time, in order to wait the NIC into a stable
3932  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
3933  * no need for link down interrupt.
3934  */
3935 static void
3936 i40e_dev_interrupt_delayed_handler(void *param)
3937 {
3938         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940         uint32_t icr0;
3941
3942         /* read interrupt causes again */
3943         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
3944
3945 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
3946         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
3947                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
3948         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
3949                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
3950         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
3951                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
3952         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
3953                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
3954         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
3955                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
3956                                                                 "state\n");
3957         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
3958                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
3959         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
3960                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
3961 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
3962
3963         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3964                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
3965                 i40e_dev_handle_vfr_event(dev);
3966         }
3967         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3968                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
3969                 i40e_dev_handle_aq_msg(dev);
3970         }
3971
3972         /* handle the link up interrupt in an alarm callback */
3973         i40e_dev_link_update(dev, 0);
3974         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3975
3976         i40e_pf_enable_irq0(hw);
3977         rte_intr_enable(&(dev->pci_dev->intr_handle));
3978 }
3979
3980 /**
3981  * Interrupt handler triggered by NIC  for handling
3982  * specific interrupt.
3983  *
3984  * @param handle
3985  *  Pointer to interrupt handle.
3986  * @param param
3987  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3988  *
3989  * @return
3990  *  void
3991  */
3992 static void
3993 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3994                            void *param)
3995 {
3996         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3997         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3998         uint32_t icr0;
3999
4000         /* Disable interrupt */
4001         i40e_pf_disable_irq0(hw);
4002
4003         /* read out interrupt causes */
4004         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4005
4006         /* No interrupt event indicated */
4007         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4008                 PMD_DRV_LOG(INFO, "No interrupt event");
4009                 goto done;
4010         }
4011 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4012         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4013                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4014         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4015                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4016         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4017                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4018         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4019                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4020         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4021                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4022         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4023                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4024         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4025                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4026 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4027
4028         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4029                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4030                 i40e_dev_handle_vfr_event(dev);
4031         }
4032         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4033                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4034                 i40e_dev_handle_aq_msg(dev);
4035         }
4036
4037         /* Link Status Change interrupt */
4038         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4039 #define I40E_US_PER_SECOND 1000000
4040                 struct rte_eth_link link;
4041
4042                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4043                 memset(&link, 0, sizeof(link));
4044                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4045                 i40e_dev_link_update(dev, 0);
4046
4047                 /*
4048                  * For link up interrupt, it needs to wait 1 second to let the
4049                  * hardware be a stable state. Otherwise several consecutive
4050                  * interrupts can be observed.
4051                  * For link down interrupt, no need to wait.
4052                  */
4053                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4054                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4055                         return;
4056                 else
4057                         _rte_eth_dev_callback_process(dev,
4058                                 RTE_ETH_EVENT_INTR_LSC);
4059         }
4060
4061 done:
4062         /* Enable interrupt */
4063         i40e_pf_enable_irq0(hw);
4064         rte_intr_enable(&(dev->pci_dev->intr_handle));
4065 }
4066
4067 static int
4068 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4069                          struct i40e_macvlan_filter *filter,
4070                          int total)
4071 {
4072         int ele_num, ele_buff_size;
4073         int num, actual_num, i;
4074         uint16_t flags;
4075         int ret = I40E_SUCCESS;
4076         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4077         struct i40e_aqc_add_macvlan_element_data *req_list;
4078
4079         if (filter == NULL  || total == 0)
4080                 return I40E_ERR_PARAM;
4081         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4082         ele_buff_size = hw->aq.asq_buf_size;
4083
4084         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4085         if (req_list == NULL) {
4086                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4087                 return I40E_ERR_NO_MEMORY;
4088         }
4089
4090         num = 0;
4091         do {
4092                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4093                 memset(req_list, 0, ele_buff_size);
4094
4095                 for (i = 0; i < actual_num; i++) {
4096                         (void)rte_memcpy(req_list[i].mac_addr,
4097                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4098                         req_list[i].vlan_tag =
4099                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4100
4101                         switch (filter[num + i].filter_type) {
4102                         case RTE_MAC_PERFECT_MATCH:
4103                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4104                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4105                                 break;
4106                         case RTE_MACVLAN_PERFECT_MATCH:
4107                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4108                                 break;
4109                         case RTE_MAC_HASH_MATCH:
4110                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4111                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4112                                 break;
4113                         case RTE_MACVLAN_HASH_MATCH:
4114                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4115                                 break;
4116                         default:
4117                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4118                                 ret = I40E_ERR_PARAM;
4119                                 goto DONE;
4120                         }
4121
4122                         req_list[i].queue_number = 0;
4123
4124                         req_list[i].flags = rte_cpu_to_le_16(flags);
4125                 }
4126
4127                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4128                                                 actual_num, NULL);
4129                 if (ret != I40E_SUCCESS) {
4130                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4131                         goto DONE;
4132                 }
4133                 num += actual_num;
4134         } while (num < total);
4135
4136 DONE:
4137         rte_free(req_list);
4138         return ret;
4139 }
4140
4141 static int
4142 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4143                             struct i40e_macvlan_filter *filter,
4144                             int total)
4145 {
4146         int ele_num, ele_buff_size;
4147         int num, actual_num, i;
4148         uint16_t flags;
4149         int ret = I40E_SUCCESS;
4150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4151         struct i40e_aqc_remove_macvlan_element_data *req_list;
4152
4153         if (filter == NULL  || total == 0)
4154                 return I40E_ERR_PARAM;
4155
4156         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4157         ele_buff_size = hw->aq.asq_buf_size;
4158
4159         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4160         if (req_list == NULL) {
4161                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4162                 return I40E_ERR_NO_MEMORY;
4163         }
4164
4165         num = 0;
4166         do {
4167                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4168                 memset(req_list, 0, ele_buff_size);
4169
4170                 for (i = 0; i < actual_num; i++) {
4171                         (void)rte_memcpy(req_list[i].mac_addr,
4172                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4173                         req_list[i].vlan_tag =
4174                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4175
4176                         switch (filter[num + i].filter_type) {
4177                         case RTE_MAC_PERFECT_MATCH:
4178                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4179                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4180                                 break;
4181                         case RTE_MACVLAN_PERFECT_MATCH:
4182                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4183                                 break;
4184                         case RTE_MAC_HASH_MATCH:
4185                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4186                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4187                                 break;
4188                         case RTE_MACVLAN_HASH_MATCH:
4189                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4190                                 break;
4191                         default:
4192                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4193                                 ret = I40E_ERR_PARAM;
4194                                 goto DONE;
4195                         }
4196                         req_list[i].flags = rte_cpu_to_le_16(flags);
4197                 }
4198
4199                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4200                                                 actual_num, NULL);
4201                 if (ret != I40E_SUCCESS) {
4202                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4203                         goto DONE;
4204                 }
4205                 num += actual_num;
4206         } while (num < total);
4207
4208 DONE:
4209         rte_free(req_list);
4210         return ret;
4211 }
4212
4213 /* Find out specific MAC filter */
4214 static struct i40e_mac_filter *
4215 i40e_find_mac_filter(struct i40e_vsi *vsi,
4216                          struct ether_addr *macaddr)
4217 {
4218         struct i40e_mac_filter *f;
4219
4220         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4221                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4222                         return f;
4223         }
4224
4225         return NULL;
4226 }
4227
4228 static bool
4229 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4230                          uint16_t vlan_id)
4231 {
4232         uint32_t vid_idx, vid_bit;
4233
4234         if (vlan_id > ETH_VLAN_ID_MAX)
4235                 return 0;
4236
4237         vid_idx = I40E_VFTA_IDX(vlan_id);
4238         vid_bit = I40E_VFTA_BIT(vlan_id);
4239
4240         if (vsi->vfta[vid_idx] & vid_bit)
4241                 return 1;
4242         else
4243                 return 0;
4244 }
4245
4246 static void
4247 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4248                          uint16_t vlan_id, bool on)
4249 {
4250         uint32_t vid_idx, vid_bit;
4251
4252         if (vlan_id > ETH_VLAN_ID_MAX)
4253                 return;
4254
4255         vid_idx = I40E_VFTA_IDX(vlan_id);
4256         vid_bit = I40E_VFTA_BIT(vlan_id);
4257
4258         if (on)
4259                 vsi->vfta[vid_idx] |= vid_bit;
4260         else
4261                 vsi->vfta[vid_idx] &= ~vid_bit;
4262 }
4263
4264 /**
4265  * Find all vlan options for specific mac addr,
4266  * return with actual vlan found.
4267  */
4268 static inline int
4269 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4270                            struct i40e_macvlan_filter *mv_f,
4271                            int num, struct ether_addr *addr)
4272 {
4273         int i;
4274         uint32_t j, k;
4275
4276         /**
4277          * Not to use i40e_find_vlan_filter to decrease the loop time,
4278          * although the code looks complex.
4279           */
4280         if (num < vsi->vlan_num)
4281                 return I40E_ERR_PARAM;
4282
4283         i = 0;
4284         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4285                 if (vsi->vfta[j]) {
4286                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4287                                 if (vsi->vfta[j] & (1 << k)) {
4288                                         if (i > num - 1) {
4289                                                 PMD_DRV_LOG(ERR, "vlan number "
4290                                                             "not match");
4291                                                 return I40E_ERR_PARAM;
4292                                         }
4293                                         (void)rte_memcpy(&mv_f[i].macaddr,
4294                                                         addr, ETH_ADDR_LEN);
4295                                         mv_f[i].vlan_id =
4296                                                 j * I40E_UINT32_BIT_SIZE + k;
4297                                         i++;
4298                                 }
4299                         }
4300                 }
4301         }
4302         return I40E_SUCCESS;
4303 }
4304
4305 static inline int
4306 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4307                            struct i40e_macvlan_filter *mv_f,
4308                            int num,
4309                            uint16_t vlan)
4310 {
4311         int i = 0;
4312         struct i40e_mac_filter *f;
4313
4314         if (num < vsi->mac_num)
4315                 return I40E_ERR_PARAM;
4316
4317         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4318                 if (i > num - 1) {
4319                         PMD_DRV_LOG(ERR, "buffer number not match");
4320                         return I40E_ERR_PARAM;
4321                 }
4322                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4323                                 ETH_ADDR_LEN);
4324                 mv_f[i].vlan_id = vlan;
4325                 mv_f[i].filter_type = f->mac_info.filter_type;
4326                 i++;
4327         }
4328
4329         return I40E_SUCCESS;
4330 }
4331
4332 static int
4333 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4334 {
4335         int i, num;
4336         struct i40e_mac_filter *f;
4337         struct i40e_macvlan_filter *mv_f;
4338         int ret = I40E_SUCCESS;
4339
4340         if (vsi == NULL || vsi->mac_num == 0)
4341                 return I40E_ERR_PARAM;
4342
4343         /* Case that no vlan is set */
4344         if (vsi->vlan_num == 0)
4345                 num = vsi->mac_num;
4346         else
4347                 num = vsi->mac_num * vsi->vlan_num;
4348
4349         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4350         if (mv_f == NULL) {
4351                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4352                 return I40E_ERR_NO_MEMORY;
4353         }
4354
4355         i = 0;
4356         if (vsi->vlan_num == 0) {
4357                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4358                         (void)rte_memcpy(&mv_f[i].macaddr,
4359                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4360                         mv_f[i].vlan_id = 0;
4361                         i++;
4362                 }
4363         } else {
4364                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4365                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4366                                         vsi->vlan_num, &f->mac_info.mac_addr);
4367                         if (ret != I40E_SUCCESS)
4368                                 goto DONE;
4369                         i += vsi->vlan_num;
4370                 }
4371         }
4372
4373         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4374 DONE:
4375         rte_free(mv_f);
4376
4377         return ret;
4378 }
4379
4380 int
4381 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4382 {
4383         struct i40e_macvlan_filter *mv_f;
4384         int mac_num;
4385         int ret = I40E_SUCCESS;
4386
4387         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4388                 return I40E_ERR_PARAM;
4389
4390         /* If it's already set, just return */
4391         if (i40e_find_vlan_filter(vsi,vlan))
4392                 return I40E_SUCCESS;
4393
4394         mac_num = vsi->mac_num;
4395
4396         if (mac_num == 0) {
4397                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4398                 return I40E_ERR_PARAM;
4399         }
4400
4401         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4402
4403         if (mv_f == NULL) {
4404                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4405                 return I40E_ERR_NO_MEMORY;
4406         }
4407
4408         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4409
4410         if (ret != I40E_SUCCESS)
4411                 goto DONE;
4412
4413         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4414
4415         if (ret != I40E_SUCCESS)
4416                 goto DONE;
4417
4418         i40e_set_vlan_filter(vsi, vlan, 1);
4419
4420         vsi->vlan_num++;
4421         ret = I40E_SUCCESS;
4422 DONE:
4423         rte_free(mv_f);
4424         return ret;
4425 }
4426
4427 int
4428 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4429 {
4430         struct i40e_macvlan_filter *mv_f;
4431         int mac_num;
4432         int ret = I40E_SUCCESS;
4433
4434         /**
4435          * Vlan 0 is the generic filter for untagged packets
4436          * and can't be removed.
4437          */
4438         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4439                 return I40E_ERR_PARAM;
4440
4441         /* If can't find it, just return */
4442         if (!i40e_find_vlan_filter(vsi, vlan))
4443                 return I40E_ERR_PARAM;
4444
4445         mac_num = vsi->mac_num;
4446
4447         if (mac_num == 0) {
4448                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4449                 return I40E_ERR_PARAM;
4450         }
4451
4452         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4453
4454         if (mv_f == NULL) {
4455                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4456                 return I40E_ERR_NO_MEMORY;
4457         }
4458
4459         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4460
4461         if (ret != I40E_SUCCESS)
4462                 goto DONE;
4463
4464         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4465
4466         if (ret != I40E_SUCCESS)
4467                 goto DONE;
4468
4469         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4470         if (vsi->vlan_num == 1) {
4471                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4472                 if (ret != I40E_SUCCESS)
4473                         goto DONE;
4474
4475                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4476                 if (ret != I40E_SUCCESS)
4477                         goto DONE;
4478         }
4479
4480         i40e_set_vlan_filter(vsi, vlan, 0);
4481
4482         vsi->vlan_num--;
4483         ret = I40E_SUCCESS;
4484 DONE:
4485         rte_free(mv_f);
4486         return ret;
4487 }
4488
4489 int
4490 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4491 {
4492         struct i40e_mac_filter *f;
4493         struct i40e_macvlan_filter *mv_f;
4494         int i, vlan_num = 0;
4495         int ret = I40E_SUCCESS;
4496
4497         /* If it's add and we've config it, return */
4498         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4499         if (f != NULL)
4500                 return I40E_SUCCESS;
4501         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4502                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4503
4504                 /**
4505                  * If vlan_num is 0, that's the first time to add mac,
4506                  * set mask for vlan_id 0.
4507                  */
4508                 if (vsi->vlan_num == 0) {
4509                         i40e_set_vlan_filter(vsi, 0, 1);
4510                         vsi->vlan_num = 1;
4511                 }
4512                 vlan_num = vsi->vlan_num;
4513         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4514                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4515                 vlan_num = 1;
4516
4517         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4518         if (mv_f == NULL) {
4519                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4520                 return I40E_ERR_NO_MEMORY;
4521         }
4522
4523         for (i = 0; i < vlan_num; i++) {
4524                 mv_f[i].filter_type = mac_filter->filter_type;
4525                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4526                                 ETH_ADDR_LEN);
4527         }
4528
4529         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4530                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4531                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4532                                         &mac_filter->mac_addr);
4533                 if (ret != I40E_SUCCESS)
4534                         goto DONE;
4535         }
4536
4537         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4538         if (ret != I40E_SUCCESS)
4539                 goto DONE;
4540
4541         /* Add the mac addr into mac list */
4542         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4543         if (f == NULL) {
4544                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4545                 ret = I40E_ERR_NO_MEMORY;
4546                 goto DONE;
4547         }
4548         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4549                         ETH_ADDR_LEN);
4550         f->mac_info.filter_type = mac_filter->filter_type;
4551         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4552         vsi->mac_num++;
4553
4554         ret = I40E_SUCCESS;
4555 DONE:
4556         rte_free(mv_f);
4557
4558         return ret;
4559 }
4560
4561 int
4562 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4563 {
4564         struct i40e_mac_filter *f;
4565         struct i40e_macvlan_filter *mv_f;
4566         int i, vlan_num;
4567         enum rte_mac_filter_type filter_type;
4568         int ret = I40E_SUCCESS;
4569
4570         /* Can't find it, return an error */
4571         f = i40e_find_mac_filter(vsi, addr);
4572         if (f == NULL)
4573                 return I40E_ERR_PARAM;
4574
4575         vlan_num = vsi->vlan_num;
4576         filter_type = f->mac_info.filter_type;
4577         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4578                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4579                 if (vlan_num == 0) {
4580                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4581                         return I40E_ERR_PARAM;
4582                 }
4583         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4584                         filter_type == RTE_MAC_HASH_MATCH)
4585                 vlan_num = 1;
4586
4587         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4588         if (mv_f == NULL) {
4589                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4590                 return I40E_ERR_NO_MEMORY;
4591         }
4592
4593         for (i = 0; i < vlan_num; i++) {
4594                 mv_f[i].filter_type = filter_type;
4595                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4596                                 ETH_ADDR_LEN);
4597         }
4598         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4599                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4600                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4601                 if (ret != I40E_SUCCESS)
4602                         goto DONE;
4603         }
4604
4605         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4606         if (ret != I40E_SUCCESS)
4607                 goto DONE;
4608
4609         /* Remove the mac addr into mac list */
4610         TAILQ_REMOVE(&vsi->mac_list, f, next);
4611         rte_free(f);
4612         vsi->mac_num--;
4613
4614         ret = I40E_SUCCESS;
4615 DONE:
4616         rte_free(mv_f);
4617         return ret;
4618 }
4619
4620 /* Configure hash enable flags for RSS */
4621 uint64_t
4622 i40e_config_hena(uint64_t flags)
4623 {
4624         uint64_t hena = 0;
4625
4626         if (!flags)
4627                 return hena;
4628
4629         if (flags & ETH_RSS_FRAG_IPV4)
4630                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4631         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4632                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4633         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4634                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4635         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4636                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4637         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4638                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4639         if (flags & ETH_RSS_FRAG_IPV6)
4640                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4641         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4642                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4643         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4644                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4645         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4646                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4647         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4648                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4649         if (flags & ETH_RSS_L2_PAYLOAD)
4650                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4651
4652         return hena;
4653 }
4654
4655 /* Parse the hash enable flags */
4656 uint64_t
4657 i40e_parse_hena(uint64_t flags)
4658 {
4659         uint64_t rss_hf = 0;
4660
4661         if (!flags)
4662                 return rss_hf;
4663         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4664                 rss_hf |= ETH_RSS_FRAG_IPV4;
4665         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4666                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4667         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4668                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4669         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4670                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4671         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4672                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4673         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4674                 rss_hf |= ETH_RSS_FRAG_IPV6;
4675         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4676                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4677         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4678                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4679         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4680                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4681         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4682                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4683         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4684                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4685
4686         return rss_hf;
4687 }
4688
4689 /* Disable RSS */
4690 static void
4691 i40e_pf_disable_rss(struct i40e_pf *pf)
4692 {
4693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4694         uint64_t hena;
4695
4696         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4697         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4698         hena &= ~I40E_RSS_HENA_ALL;
4699         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4700         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4701         I40E_WRITE_FLUSH(hw);
4702 }
4703
4704 static int
4705 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4706 {
4707         uint32_t *hash_key;
4708         uint8_t hash_key_len;
4709         uint64_t rss_hf;
4710         uint16_t i;
4711         uint64_t hena;
4712
4713         hash_key = (uint32_t *)(rss_conf->rss_key);
4714         hash_key_len = rss_conf->rss_key_len;
4715         if (hash_key != NULL && hash_key_len >=
4716                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4717                 /* Fill in RSS hash key */
4718                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4719                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4720         }
4721
4722         rss_hf = rss_conf->rss_hf;
4723         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4724         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4725         hena &= ~I40E_RSS_HENA_ALL;
4726         hena |= i40e_config_hena(rss_hf);
4727         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4728         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4729         I40E_WRITE_FLUSH(hw);
4730
4731         return 0;
4732 }
4733
4734 static int
4735 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4736                          struct rte_eth_rss_conf *rss_conf)
4737 {
4738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4739         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4740         uint64_t hena;
4741
4742         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4743         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4744         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4745                 if (rss_hf != 0) /* Enable RSS */
4746                         return -EINVAL;
4747                 return 0; /* Nothing to do */
4748         }
4749         /* RSS enabled */
4750         if (rss_hf == 0) /* Disable RSS */
4751                 return -EINVAL;
4752
4753         return i40e_hw_rss_hash_set(hw, rss_conf);
4754 }
4755
4756 static int
4757 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4758                            struct rte_eth_rss_conf *rss_conf)
4759 {
4760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4761         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4762         uint64_t hena;
4763         uint16_t i;
4764
4765         if (hash_key != NULL) {
4766                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4767                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4768                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4769         }
4770         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4771         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4772         rss_conf->rss_hf = i40e_parse_hena(hena);
4773
4774         return 0;
4775 }
4776
4777 static int
4778 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4779 {
4780         switch (filter_type) {
4781         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4782                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4783                 break;
4784         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4785                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4786                 break;
4787         case RTE_TUNNEL_FILTER_IMAC_TENID:
4788                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4789                 break;
4790         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4791                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4792                 break;
4793         case ETH_TUNNEL_FILTER_IMAC:
4794                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4795                 break;
4796         default:
4797                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4798                 return -EINVAL;
4799         }
4800
4801         return 0;
4802 }
4803
4804 static int
4805 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4806                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4807                         uint8_t add)
4808 {
4809         uint16_t ip_type;
4810         uint8_t tun_type = 0;
4811         int val, ret = 0;
4812         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813         struct i40e_vsi *vsi = pf->main_vsi;
4814         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4815         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4816
4817         cld_filter = rte_zmalloc("tunnel_filter",
4818                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4819                 0);
4820
4821         if (NULL == cld_filter) {
4822                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4823                 return -EINVAL;
4824         }
4825         pfilter = cld_filter;
4826
4827         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4828                         sizeof(struct ether_addr));
4829         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4830                         sizeof(struct ether_addr));
4831
4832         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4833         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4834                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4835                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4836                                 &tunnel_filter->ip_addr,
4837                                 sizeof(pfilter->ipaddr.v4.data));
4838         } else {
4839                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4840                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4841                                 &tunnel_filter->ip_addr,
4842                                 sizeof(pfilter->ipaddr.v6.data));
4843         }
4844
4845         /* check tunneled type */
4846         switch (tunnel_filter->tunnel_type) {
4847         case RTE_TUNNEL_TYPE_VXLAN:
4848                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4849                 break;
4850         case RTE_TUNNEL_TYPE_NVGRE:
4851                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4852                 break;
4853         default:
4854                 /* Other tunnel types is not supported. */
4855                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4856                 rte_free(cld_filter);
4857                 return -EINVAL;
4858         }
4859
4860         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4861                                                 &pfilter->flags);
4862         if (val < 0) {
4863                 rte_free(cld_filter);
4864                 return -EINVAL;
4865         }
4866
4867         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4868                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4869         pfilter->tenant_id = tunnel_filter->tenant_id;
4870         pfilter->queue_number = tunnel_filter->queue_id;
4871
4872         if (add)
4873                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4874         else
4875                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4876                                                 cld_filter, 1);
4877
4878         rte_free(cld_filter);
4879         return ret;
4880 }
4881
4882 static int
4883 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4884 {
4885         uint8_t i;
4886
4887         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4888                 if (pf->vxlan_ports[i] == port)
4889                         return i;
4890         }
4891
4892         return -1;
4893 }
4894
4895 static int
4896 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4897 {
4898         int  idx, ret;
4899         uint8_t filter_idx;
4900         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4901
4902         idx = i40e_get_vxlan_port_idx(pf, port);
4903
4904         /* Check if port already exists */
4905         if (idx >= 0) {
4906                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4907                 return -EINVAL;
4908         }
4909
4910         /* Now check if there is space to add the new port */
4911         idx = i40e_get_vxlan_port_idx(pf, 0);
4912         if (idx < 0) {
4913                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
4914                         "not adding port %d", port);
4915                 return -ENOSPC;
4916         }
4917
4918         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
4919                                         &filter_idx, NULL);
4920         if (ret < 0) {
4921                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
4922                 return -1;
4923         }
4924
4925         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
4926                          port,  filter_idx);
4927
4928         /* New port: add it and mark its index in the bitmap */
4929         pf->vxlan_ports[idx] = port;
4930         pf->vxlan_bitmap |= (1 << idx);
4931
4932         if (!(pf->flags & I40E_FLAG_VXLAN))
4933                 pf->flags |= I40E_FLAG_VXLAN;
4934
4935         return 0;
4936 }
4937
4938 static int
4939 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
4940 {
4941         int idx;
4942         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4943
4944         if (!(pf->flags & I40E_FLAG_VXLAN)) {
4945                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
4946                 return -EINVAL;
4947         }
4948
4949         idx = i40e_get_vxlan_port_idx(pf, port);
4950
4951         if (idx < 0) {
4952                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
4953                 return -EINVAL;
4954         }
4955
4956         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
4957                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
4958                 return -1;
4959         }
4960
4961         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
4962                         port, idx);
4963
4964         pf->vxlan_ports[idx] = 0;
4965         pf->vxlan_bitmap &= ~(1 << idx);
4966
4967         if (!pf->vxlan_bitmap)
4968                 pf->flags &= ~I40E_FLAG_VXLAN;
4969
4970         return 0;
4971 }
4972
4973 /* Add UDP tunneling port */
4974 static int
4975 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
4976                         struct rte_eth_udp_tunnel *udp_tunnel)
4977 {
4978         int ret = 0;
4979         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4980
4981         if (udp_tunnel == NULL)
4982                 return -EINVAL;
4983
4984         switch (udp_tunnel->prot_type) {
4985         case RTE_TUNNEL_TYPE_VXLAN:
4986                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
4987                 break;
4988
4989         case RTE_TUNNEL_TYPE_GENEVE:
4990         case RTE_TUNNEL_TYPE_TEREDO:
4991                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
4992                 ret = -1;
4993                 break;
4994
4995         default:
4996                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4997                 ret = -1;
4998                 break;
4999         }
5000
5001         return ret;
5002 }
5003
5004 /* Remove UDP tunneling port */
5005 static int
5006 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5007                         struct rte_eth_udp_tunnel *udp_tunnel)
5008 {
5009         int ret = 0;
5010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5011
5012         if (udp_tunnel == NULL)
5013                 return -EINVAL;
5014
5015         switch (udp_tunnel->prot_type) {
5016         case RTE_TUNNEL_TYPE_VXLAN:
5017                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5018                 break;
5019         case RTE_TUNNEL_TYPE_GENEVE:
5020         case RTE_TUNNEL_TYPE_TEREDO:
5021                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5022                 ret = -1;
5023                 break;
5024         default:
5025                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5026                 ret = -1;
5027                 break;
5028         }
5029
5030         return ret;
5031 }
5032
5033 /* Calculate the maximum number of contiguous PF queues that are configured */
5034 static int
5035 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5036 {
5037         struct rte_eth_dev_data *data = pf->dev_data;
5038         int i, num;
5039         struct i40e_rx_queue *rxq;
5040
5041         num = 0;
5042         for (i = 0; i < pf->lan_nb_qps; i++) {
5043                 rxq = data->rx_queues[i];
5044                 if (rxq && rxq->q_set)
5045                         num++;
5046                 else
5047                         break;
5048         }
5049
5050         return num;
5051 }
5052
5053 /* Configure RSS */
5054 static int
5055 i40e_pf_config_rss(struct i40e_pf *pf)
5056 {
5057         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5058         struct rte_eth_rss_conf rss_conf;
5059         uint32_t i, lut = 0;
5060         uint16_t j, num;
5061
5062         /*
5063          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5064          * It's necessary to calulate the actual PF queues that are configured.
5065          */
5066         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5067                 num = i40e_pf_calc_configured_queues_num(pf);
5068                 num = i40e_align_floor(num);
5069         } else
5070                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5071
5072         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5073                         num);
5074
5075         if (num == 0) {
5076                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5077                 return -ENOTSUP;
5078         }
5079
5080         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5081                 if (j == num)
5082                         j = 0;
5083                 lut = (lut << 8) | (j & ((0x1 <<
5084                         hw->func_caps.rss_table_entry_width) - 1));
5085                 if ((i & 3) == 3)
5086                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5087         }
5088
5089         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5090         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5091                 i40e_pf_disable_rss(pf);
5092                 return 0;
5093         }
5094         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5095                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5096                 /* Random default keys */
5097                 static uint32_t rss_key_default[] = {0x6b793944,
5098                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5099                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5100                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5101
5102                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5103                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5104                                                         sizeof(uint32_t);
5105         }
5106
5107         return i40e_hw_rss_hash_set(hw, &rss_conf);
5108 }
5109
5110 static int
5111 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5112                         struct rte_eth_tunnel_filter_conf *filter)
5113 {
5114         if (pf == NULL || filter == NULL) {
5115                 PMD_DRV_LOG(ERR, "Invalid parameter");
5116                 return -EINVAL;
5117         }
5118
5119         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5120                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5121                 return -EINVAL;
5122         }
5123
5124         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5125                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5126                 return -EINVAL;
5127         }
5128
5129         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5130                 (is_zero_ether_addr(filter->outer_mac))) {
5131                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5132                 return -EINVAL;
5133         }
5134
5135         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5136                 (is_zero_ether_addr(filter->inner_mac))) {
5137                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5138                 return -EINVAL;
5139         }
5140
5141         return 0;
5142 }
5143
5144 static int
5145 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5146                         void *arg)
5147 {
5148         struct rte_eth_tunnel_filter_conf *filter;
5149         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5150         int ret = I40E_SUCCESS;
5151
5152         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5153
5154         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5155                 return I40E_ERR_PARAM;
5156
5157         switch (filter_op) {
5158         case RTE_ETH_FILTER_NOP:
5159                 if (!(pf->flags & I40E_FLAG_VXLAN))
5160                         ret = I40E_NOT_SUPPORTED;
5161         case RTE_ETH_FILTER_ADD:
5162                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5163                 break;
5164         case RTE_ETH_FILTER_DELETE:
5165                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5166                 break;
5167         default:
5168                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5169                 ret = I40E_ERR_PARAM;
5170                 break;
5171         }
5172
5173         return ret;
5174 }
5175
5176 static int
5177 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5178 {
5179         int ret = 0;
5180         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5181
5182         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5183                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5184                 return -ENOTSUP;
5185         }
5186
5187         /* RSS setup */
5188         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5189                 ret = i40e_pf_config_rss(pf);
5190         else
5191                 i40e_pf_disable_rss(pf);
5192
5193         return ret;
5194 }
5195
5196 /* Get the symmetric hash enable configurations per port */
5197 static void
5198 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5199 {
5200         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5201
5202         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5203 }
5204
5205 /* Set the symmetric hash enable configurations per port */
5206 static void
5207 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5208 {
5209         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5210
5211         if (enable > 0) {
5212                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5213                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5214                                                         "been enabled");
5215                         return;
5216                 }
5217                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5218         } else {
5219                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5220                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5221                                                         "been disabled");
5222                         return;
5223                 }
5224                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5225         }
5226         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5227         I40E_WRITE_FLUSH(hw);
5228 }
5229
5230 /*
5231  * Get global configurations of hash function type and symmetric hash enable
5232  * per flow type (pctype). Note that global configuration means it affects all
5233  * the ports on the same NIC.
5234  */
5235 static int
5236 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5237                                    struct rte_eth_hash_global_conf *g_cfg)
5238 {
5239         uint32_t reg, mask = I40E_FLOW_TYPES;
5240         uint16_t i;
5241         enum i40e_filter_pctype pctype;
5242
5243         memset(g_cfg, 0, sizeof(*g_cfg));
5244         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5245         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5246                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5247         else
5248                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5249         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5250                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5251
5252         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5253                 if (!(mask & (1UL << i)))
5254                         continue;
5255                 mask &= ~(1UL << i);
5256                 /* Bit set indicats the coresponding flow type is supported */
5257                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5258                 pctype = i40e_flowtype_to_pctype(i);
5259                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5260                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5261                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5262         }
5263
5264         return 0;
5265 }
5266
5267 static int
5268 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5269 {
5270         uint32_t i;
5271         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5272
5273         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5274                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5275                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5276                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5277                                                 g_cfg->hash_func);
5278                 return -EINVAL;
5279         }
5280
5281         /*
5282          * As i40e supports less than 32 flow types, only first 32 bits need to
5283          * be checked.
5284          */
5285         mask0 = g_cfg->valid_bit_mask[0];
5286         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5287                 if (i == 0) {
5288                         /* Check if any unsupported flow type configured */
5289                         if ((mask0 | i40e_mask) ^ i40e_mask)
5290                                 goto mask_err;
5291                 } else {
5292                         if (g_cfg->valid_bit_mask[i])
5293                                 goto mask_err;
5294                 }
5295         }
5296
5297         return 0;
5298
5299 mask_err:
5300         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5301
5302         return -EINVAL;
5303 }
5304
5305 /*
5306  * Set global configurations of hash function type and symmetric hash enable
5307  * per flow type (pctype). Note any modifying global configuration will affect
5308  * all the ports on the same NIC.
5309  */
5310 static int
5311 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5312                                    struct rte_eth_hash_global_conf *g_cfg)
5313 {
5314         int ret;
5315         uint16_t i;
5316         uint32_t reg;
5317         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5318         enum i40e_filter_pctype pctype;
5319
5320         /* Check the input parameters */
5321         ret = i40e_hash_global_config_check(g_cfg);
5322         if (ret < 0)
5323                 return ret;
5324
5325         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5326                 if (!(mask0 & (1UL << i)))
5327                         continue;
5328                 mask0 &= ~(1UL << i);
5329                 pctype = i40e_flowtype_to_pctype(i);
5330                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5331                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5332                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5333         }
5334
5335         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5336         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5337                 /* Toeplitz */
5338                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5339                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5340                                                                 "Toeplitz");
5341                         goto out;
5342                 }
5343                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5344         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5345                 /* Simple XOR */
5346                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5347                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5348                                                         "Simple XOR");
5349                         goto out;
5350                 }
5351                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5352         } else
5353                 /* Use the default, and keep it as it is */
5354                 goto out;
5355
5356         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5357
5358 out:
5359         I40E_WRITE_FLUSH(hw);
5360
5361         return 0;
5362 }
5363
5364 static int
5365 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5366 {
5367         int ret = 0;
5368
5369         if (!hw || !info) {
5370                 PMD_DRV_LOG(ERR, "Invalid pointer");
5371                 return -EFAULT;
5372         }
5373
5374         switch (info->info_type) {
5375         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5376                 i40e_get_symmetric_hash_enable_per_port(hw,
5377                                         &(info->info.enable));
5378                 break;
5379         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5380                 ret = i40e_get_hash_filter_global_config(hw,
5381                                 &(info->info.global_conf));
5382                 break;
5383         default:
5384                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5385                                                         info->info_type);
5386                 ret = -EINVAL;
5387                 break;
5388         }
5389
5390         return ret;
5391 }
5392
5393 static int
5394 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5395 {
5396         int ret = 0;
5397
5398         if (!hw || !info) {
5399                 PMD_DRV_LOG(ERR, "Invalid pointer");
5400                 return -EFAULT;
5401         }
5402
5403         switch (info->info_type) {
5404         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5405                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5406                 break;
5407         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5408                 ret = i40e_set_hash_filter_global_config(hw,
5409                                 &(info->info.global_conf));
5410                 break;
5411         default:
5412                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5413                                                         info->info_type);
5414                 ret = -EINVAL;
5415                 break;
5416         }
5417
5418         return ret;
5419 }
5420
5421 /* Operations for hash function */
5422 static int
5423 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5424                       enum rte_filter_op filter_op,
5425                       void *arg)
5426 {
5427         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5428         int ret = 0;
5429
5430         switch (filter_op) {
5431         case RTE_ETH_FILTER_NOP:
5432                 break;
5433         case RTE_ETH_FILTER_GET:
5434                 ret = i40e_hash_filter_get(hw,
5435                         (struct rte_eth_hash_filter_info *)arg);
5436                 break;
5437         case RTE_ETH_FILTER_SET:
5438                 ret = i40e_hash_filter_set(hw,
5439                         (struct rte_eth_hash_filter_info *)arg);
5440                 break;
5441         default:
5442                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5443                                                                 filter_op);
5444                 ret = -ENOTSUP;
5445                 break;
5446         }
5447
5448         return ret;
5449 }
5450
5451 /*
5452  * Configure ethertype filter, which can director packet by filtering
5453  * with mac address and ether_type or only ether_type
5454  */
5455 static int
5456 i40e_ethertype_filter_set(struct i40e_pf *pf,
5457                         struct rte_eth_ethertype_filter *filter,
5458                         bool add)
5459 {
5460         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5461         struct i40e_control_filter_stats stats;
5462         uint16_t flags = 0;
5463         int ret;
5464
5465         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5466                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5467                 return -EINVAL;
5468         }
5469         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5470                 filter->ether_type == ETHER_TYPE_IPv6) {
5471                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5472                         " control packet filter.", filter->ether_type);
5473                 return -EINVAL;
5474         }
5475         if (filter->ether_type == ETHER_TYPE_VLAN)
5476                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5477                         " not supported.");
5478
5479         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5480                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5481         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5482                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5483         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5484
5485         memset(&stats, 0, sizeof(stats));
5486         ret = i40e_aq_add_rem_control_packet_filter(hw,
5487                         filter->mac_addr.addr_bytes,
5488                         filter->ether_type, flags,
5489                         pf->main_vsi->seid,
5490                         filter->queue, add, &stats, NULL);
5491
5492         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5493                          " mac_etype_used = %u, etype_used = %u,"
5494                          " mac_etype_free = %u, etype_free = %u\n",
5495                          ret, stats.mac_etype_used, stats.etype_used,
5496                          stats.mac_etype_free, stats.etype_free);
5497         if (ret < 0)
5498                 return -ENOSYS;
5499         return 0;
5500 }
5501
5502 /*
5503  * Handle operations for ethertype filter.
5504  */
5505 static int
5506 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5507                                 enum rte_filter_op filter_op,
5508                                 void *arg)
5509 {
5510         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5511         int ret = 0;
5512
5513         if (filter_op == RTE_ETH_FILTER_NOP)
5514                 return ret;
5515
5516         if (arg == NULL) {
5517                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5518                             filter_op);
5519                 return -EINVAL;
5520         }
5521
5522         switch (filter_op) {
5523         case RTE_ETH_FILTER_ADD:
5524                 ret = i40e_ethertype_filter_set(pf,
5525                         (struct rte_eth_ethertype_filter *)arg,
5526                         TRUE);
5527                 break;
5528         case RTE_ETH_FILTER_DELETE:
5529                 ret = i40e_ethertype_filter_set(pf,
5530                         (struct rte_eth_ethertype_filter *)arg,
5531                         FALSE);
5532                 break;
5533         default:
5534                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5535                 ret = -ENOSYS;
5536                 break;
5537         }
5538         return ret;
5539 }
5540
5541 static int
5542 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5543                      enum rte_filter_type filter_type,
5544                      enum rte_filter_op filter_op,
5545                      void *arg)
5546 {
5547         int ret = 0;
5548
5549         if (dev == NULL)
5550                 return -EINVAL;
5551
5552         switch (filter_type) {
5553         case RTE_ETH_FILTER_HASH:
5554                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5555                 break;
5556         case RTE_ETH_FILTER_MACVLAN:
5557                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5558                 break;
5559         case RTE_ETH_FILTER_ETHERTYPE:
5560                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5561                 break;
5562         case RTE_ETH_FILTER_TUNNEL:
5563                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5564                 break;
5565         case RTE_ETH_FILTER_FDIR:
5566                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5567                 break;
5568         default:
5569                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5570                                                         filter_type);
5571                 ret = -EINVAL;
5572                 break;
5573         }
5574
5575         return ret;
5576 }
5577
5578 /*
5579  * As some registers wouldn't be reset unless a global hardware reset,
5580  * hardware initialization is needed to put those registers into an
5581  * expected initial state.
5582  */
5583 static void
5584 i40e_hw_init(struct i40e_hw *hw)
5585 {
5586         /* clear the PF Queue Filter control register */
5587         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5588
5589         /* Disable symmetric hash per port */
5590         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5591 }
5592
5593 enum i40e_filter_pctype
5594 i40e_flowtype_to_pctype(uint16_t flow_type)
5595 {
5596         static const enum i40e_filter_pctype pctype_table[] = {
5597                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5598                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5599                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5600                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5601                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5602                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5603                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5604                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5605                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5606                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5607                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5608                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5609                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5610                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5611                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5612                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5613                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5614                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5615                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5616         };
5617
5618         return pctype_table[flow_type];
5619 }
5620
5621 uint16_t
5622 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5623 {
5624         static const uint16_t flowtype_table[] = {
5625                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5627                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5628                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5629                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5630                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5631                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5632                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5633                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5634                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5635                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5636                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5637                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5638                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5639                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5640                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5641                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5642                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5643                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5644         };
5645
5646         return flowtype_table[pctype];
5647 }
5648
5649 /*
5650  * On X710, performance number is far from the expectation on recent firmware
5651  * versions; on XL710, performance number is also far from the expectation on
5652  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5653  * mode is enabled and port MAC address is equal to the packet destination MAC
5654  * address. The fix for this issue may not be integrated in the following
5655  * firmware version. So the workaround in software driver is needed. It needs
5656  * to modify the initial values of 3 internal only registers for both X710 and
5657  * XL710. Note that the values for X710 or XL710 could be different, and the
5658  * workaround can be removed when it is fixed in firmware in the future.
5659  */
5660
5661 /* For both X710 and XL710 */
5662 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5663 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5664
5665 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5666 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5667
5668 /* For X710 */
5669 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5670 /* For XL710 */
5671 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5672 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5673
5674 static void
5675 i40e_configure_registers(struct i40e_hw *hw)
5676 {
5677         static struct {
5678                 uint32_t addr;
5679                 uint64_t val;
5680         } reg_table[] = {
5681                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5682                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5683                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5684         };
5685         uint64_t reg;
5686         uint32_t i;
5687         int ret;
5688
5689         for (i = 0; i < RTE_DIM(reg_table); i++) {
5690                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5691                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5692                                 reg_table[i].val =
5693                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5694                         else /* For X710 */
5695                                 reg_table[i].val =
5696                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5697                 }
5698
5699                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5700                                                         &reg, NULL);
5701                 if (ret < 0) {
5702                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5703                                                         reg_table[i].addr);
5704                         break;
5705                 }
5706                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5707                                                 reg_table[i].addr, reg);
5708                 if (reg == reg_table[i].val)
5709                         continue;
5710
5711                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5712                                                 reg_table[i].val, NULL);
5713                 if (ret < 0) {
5714                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5715                                 "address of 0x%"PRIx32, reg_table[i].val,
5716                                                         reg_table[i].addr);
5717                         break;
5718                 }
5719                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5720                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5721         }
5722 }
5723
5724 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
5725 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
5726 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
5727 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5728 static int
5729 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5730 {
5731         uint32_t reg;
5732         int ret;
5733
5734         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5735                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5736                 return -EINVAL;
5737         }
5738
5739         /* Configure for double VLAN RX stripping */
5740         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5741         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5742                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5743                 ret = i40e_aq_debug_write_register(hw,
5744                                                    I40E_VSI_TSR(vsi->vsi_id),
5745                                                    reg, NULL);
5746                 if (ret < 0) {
5747                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5748                                     vsi->vsi_id);
5749                         return I40E_ERR_CONFIG;
5750                 }
5751         }
5752
5753         /* Configure for double VLAN TX insertion */
5754         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5755         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5756                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5757                 ret = i40e_aq_debug_write_register(hw,
5758                                                    I40E_VSI_L2TAGSTXVALID(
5759                                                    vsi->vsi_id), reg, NULL);
5760                 if (ret < 0) {
5761                         PMD_DRV_LOG(ERR, "Failed to update "
5762                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5763                         return I40E_ERR_CONFIG;
5764                 }
5765         }
5766
5767         return 0;
5768 }
5769
5770 /**
5771  * i40e_aq_add_mirror_rule
5772  * @hw: pointer to the hardware structure
5773  * @seid: VEB seid to add mirror rule to
5774  * @dst_id: destination vsi seid
5775  * @entries: Buffer which contains the entities to be mirrored
5776  * @count: number of entities contained in the buffer
5777  * @rule_id:the rule_id of the rule to be added
5778  *
5779  * Add a mirror rule for a given veb.
5780  *
5781  **/
5782 static enum i40e_status_code
5783 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5784                         uint16_t seid, uint16_t dst_id,
5785                         uint16_t rule_type, uint16_t *entries,
5786                         uint16_t count, uint16_t *rule_id)
5787 {
5788         struct i40e_aq_desc desc;
5789         struct i40e_aqc_add_delete_mirror_rule *cmd =
5790                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
5791         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5792                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5793                 &desc.params.raw;
5794         uint16_t buff_len;
5795         enum i40e_status_code status;
5796
5797         i40e_fill_default_direct_cmd_desc(&desc,
5798                                           i40e_aqc_opc_add_mirror_rule);
5799
5800         buff_len = sizeof(uint16_t) * count;
5801         desc.datalen = rte_cpu_to_le_16(buff_len);
5802         if (buff_len > 0)
5803                 desc.flags |= rte_cpu_to_le_16(
5804                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5805         cmd->rule_type = rte_cpu_to_le_16(rule_type <<
5806                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5807         cmd->num_entries = rte_cpu_to_le_16(count);
5808         cmd->seid = rte_cpu_to_le_16(seid);
5809         cmd->destination = rte_cpu_to_le_16(dst_id);
5810
5811         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5812         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5813                          "rule_id = %u"
5814                          " mirror_rules_used = %u, mirror_rules_free = %u,",
5815                          hw->aq.asq_last_status, resp->rule_id,
5816                          resp->mirror_rules_used, resp->mirror_rules_free);
5817         *rule_id = rte_le_to_cpu_16(resp->rule_id);
5818
5819         return status;
5820 }
5821
5822 /**
5823  * i40e_aq_del_mirror_rule
5824  * @hw: pointer to the hardware structure
5825  * @seid: VEB seid to add mirror rule to
5826  * @entries: Buffer which contains the entities to be mirrored
5827  * @count: number of entities contained in the buffer
5828  * @rule_id:the rule_id of the rule to be delete
5829  *
5830  * Delete a mirror rule for a given veb.
5831  *
5832  **/
5833 static enum i40e_status_code
5834 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5835                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5836                 uint16_t count, uint16_t rule_id)
5837 {
5838         struct i40e_aq_desc desc;
5839         struct i40e_aqc_add_delete_mirror_rule *cmd =
5840                 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
5841         uint16_t buff_len = 0;
5842         enum i40e_status_code status;
5843         void *buff = NULL;
5844
5845         i40e_fill_default_direct_cmd_desc(&desc,
5846                                           i40e_aqc_opc_delete_mirror_rule);
5847
5848         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5849                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5850                                                           I40E_AQ_FLAG_RD));
5851                 cmd->num_entries = count;
5852                 buff_len = sizeof(uint16_t) * count;
5853                 desc.datalen = rte_cpu_to_le_16(buff_len);
5854                 buff = (void *)entries;
5855         } else
5856                 /* rule id is filled in destination field for deleting mirror rule */
5857                 cmd->destination = rte_cpu_to_le_16(rule_id);
5858
5859         cmd->rule_type = rte_cpu_to_le_16(rule_type <<
5860                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5861         cmd->seid = rte_cpu_to_le_16(seid);
5862
5863         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5864
5865         return status;
5866 }
5867
5868 /**
5869  * i40e_mirror_rule_set
5870  * @dev: pointer to the hardware structure
5871  * @mirror_conf: mirror rule info
5872  * @sw_id: mirror rule's sw_id
5873  * @on: enable/disable
5874  *
5875  * set a mirror rule.
5876  *
5877  **/
5878 static int
5879 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5880                         struct rte_eth_mirror_conf *mirror_conf,
5881                         uint8_t sw_id, uint8_t on)
5882 {
5883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         struct i40e_mirror_rule *it, *mirr_rule = NULL;
5886         struct i40e_mirror_rule *parent = NULL;
5887         uint16_t seid, dst_seid, rule_id;
5888         uint16_t i, j = 0;
5889         int ret;
5890
5891         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5892
5893         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5894                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5895                         " without veb or vfs.");
5896                 return -ENOSYS;
5897         }
5898         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5899                 PMD_DRV_LOG(ERR, "mirror table is full.");
5900                 return -ENOSPC;
5901         }
5902         if (mirror_conf->dst_pool > pf->vf_num) {
5903                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5904                                  mirror_conf->dst_pool);
5905                 return -EINVAL;
5906         }
5907
5908         seid = pf->main_vsi->veb->seid;
5909
5910         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
5911                 if (sw_id <= it->index) {
5912                         mirr_rule = it;
5913                         break;
5914                 }
5915                 parent = it;
5916         }
5917         if (mirr_rule && sw_id == mirr_rule->index) {
5918                 if (on) {
5919                         PMD_DRV_LOG(ERR, "mirror rule exists.");
5920                         return -EEXIST;
5921                 } else {
5922                         ret = i40e_aq_del_mirror_rule(hw, seid,
5923                                         mirr_rule->rule_type,
5924                                         mirr_rule->entries,
5925                                         mirr_rule->num_entries, mirr_rule->id);
5926                         if (ret < 0) {
5927                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
5928                                                    " ret = %d, aq_err = %d.",
5929                                                    ret, hw->aq.asq_last_status);
5930                                 return -ENOSYS;
5931                         }
5932                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
5933                         rte_free(mirr_rule);
5934                         pf->nb_mirror_rule--;
5935                         return 0;
5936                 }
5937         } else if (!on) {
5938                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
5939                 return -ENOENT;
5940         }
5941
5942         mirr_rule = rte_zmalloc("i40e_mirror_rule",
5943                                 sizeof(struct i40e_mirror_rule) , 0);
5944         if (!mirr_rule) {
5945                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5946                 return I40E_ERR_NO_MEMORY;
5947         }
5948         switch (mirror_conf->rule_type) {
5949         case ETH_MIRROR_VLAN:
5950                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
5951                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5952                                 mirr_rule->entries[j] =
5953                                         mirror_conf->vlan.vlan_id[i];
5954                                 j++;
5955                         }
5956                 }
5957                 if (j == 0) {
5958                         PMD_DRV_LOG(ERR, "vlan is not specified.");
5959                         rte_free(mirr_rule);
5960                         return -EINVAL;
5961                 }
5962                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
5963                 break;
5964         case ETH_MIRROR_VIRTUAL_POOL_UP:
5965         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
5966                 /* check if the specified pool bit is out of range */
5967                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
5968                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
5969                         rte_free(mirr_rule);
5970                         return -EINVAL;
5971                 }
5972                 for (i = 0, j = 0; i < pf->vf_num; i++) {
5973                         if (mirror_conf->pool_mask & (1ULL << i)) {
5974                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
5975                                 j++;
5976                         }
5977                 }
5978                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
5979                         /* add pf vsi to entries */
5980                         mirr_rule->entries[j] = pf->main_vsi_seid;
5981                         j++;
5982                 }
5983                 if (j == 0) {
5984                         PMD_DRV_LOG(ERR, "pool is not specified.");
5985                         rte_free(mirr_rule);
5986                         return -EINVAL;
5987                 }
5988                 /* egress and ingress in aq commands means from switch but not port */
5989                 mirr_rule->rule_type =
5990                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
5991                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
5992                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
5993                 break;
5994         case ETH_MIRROR_UPLINK_PORT:
5995                 /* egress and ingress in aq commands means from switch but not port*/
5996                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
5997                 break;
5998         case ETH_MIRROR_DOWNLINK_PORT:
5999                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6000                 break;
6001         default:
6002                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6003                         mirror_conf->rule_type);
6004                 rte_free(mirr_rule);
6005                 return -EINVAL;
6006         }
6007
6008         /* If the dst_pool is equal to vf_num, consider it as PF */
6009         if (mirror_conf->dst_pool == pf->vf_num)
6010                 dst_seid = pf->main_vsi_seid;
6011         else
6012                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6013
6014         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6015                                       mirr_rule->rule_type, mirr_rule->entries,
6016                                       j, &rule_id);
6017         if (ret < 0) {
6018                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6019                                    " ret = %d, aq_err = %d.",
6020                                    ret, hw->aq.asq_last_status);
6021                 rte_free(mirr_rule);
6022                 return -ENOSYS;
6023         }
6024
6025         mirr_rule->index = sw_id;
6026         mirr_rule->num_entries = j;
6027         mirr_rule->id = rule_id;
6028         mirr_rule->dst_vsi_seid = dst_seid;
6029
6030         if (parent)
6031                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6032         else
6033                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6034
6035         pf->nb_mirror_rule++;
6036         return 0;
6037 }
6038
6039 /**
6040  * i40e_mirror_rule_reset
6041  * @dev: pointer to the device
6042  * @sw_id: mirror rule's sw_id
6043  *
6044  * reset a mirror rule.
6045  *
6046  **/
6047 static int
6048 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6049 {
6050         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6052         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6053         uint16_t seid;
6054         int ret;
6055
6056         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6057
6058         seid = pf->main_vsi->veb->seid;
6059
6060         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6061                 if (sw_id == it->index) {
6062                         mirr_rule = it;
6063                         break;
6064                 }
6065         }
6066         if (mirr_rule) {
6067                 ret = i40e_aq_del_mirror_rule(hw, seid,
6068                                 mirr_rule->rule_type,
6069                                 mirr_rule->entries,
6070                                 mirr_rule->num_entries, mirr_rule->id);
6071                 if (ret < 0) {
6072                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6073                                            " status = %d, aq_err = %d.",
6074                                            ret, hw->aq.asq_last_status);
6075                         return -ENOSYS;
6076                 }
6077                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6078                 rte_free(mirr_rule);
6079                 pf->nb_mirror_rule--;
6080         } else {
6081                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6082                 return -ENOENT;
6083         }
6084         return 0;
6085 }