drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { .vendor_id = 0, /* sentinel */ },
 447 };
 448
 449 static const struct eth_dev_ops i40e_eth_dev_ops = {
 450         .dev_configure                = i40e_dev_configure,
 451         .dev_start                    = i40e_dev_start,
 452         .dev_stop                     = i40e_dev_stop,
 453         .dev_close                    = i40e_dev_close,
 454         .dev_reset                    = i40e_dev_reset,
 455         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 456         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 457         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 458         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 459         .dev_set_link_up              = i40e_dev_set_link_up,
 460         .dev_set_link_down            = i40e_dev_set_link_down,
 461         .link_update                  = i40e_dev_link_update,
 462         .stats_get                    = i40e_dev_stats_get,
 463         .xstats_get                   = i40e_dev_xstats_get,
 464         .xstats_get_names             = i40e_dev_xstats_get_names,
 465         .stats_reset                  = i40e_dev_stats_reset,
 466         .xstats_reset                 = i40e_dev_stats_reset,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 506         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .get_module_info              = i40e_get_module_info,
 521         .get_module_eeprom            = i40e_get_module_eeprom,
 522         .mac_addr_set                 = i40e_set_default_mac_addr,
 523         .mtu_set                      = i40e_dev_mtu_set,
 524         .tm_ops_get                   = i40e_tm_ops_get,
 525 };
 526
 527 /* store statistics names and its offset in stats structure */
 528 struct rte_i40e_xstats_name_off {
 529         char name[RTE_ETH_XSTATS_NAME_SIZE];
 530         unsigned offset;
 531 };
 532
 533 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 534         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 535         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 536         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 537         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 538         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 539                 rx_unknown_protocol)},
 540         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 541         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 542         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 543         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 544 };
 545
 546 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 547                 sizeof(rte_i40e_stats_strings[0]))
 548
 549 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 550         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 551                 tx_dropped_link_down)},
 552         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 553         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 554                 illegal_bytes)},
 555         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 556         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_local_faults)},
 558         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 559                 mac_remote_faults)},
 560         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 561                 rx_length_errors)},
 562         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 563         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 564         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 565         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 566         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 567         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_127)},
 569         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_255)},
 571         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_511)},
 573         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1023)},
 575         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_1522)},
 577         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_big)},
 579         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_undersize)},
 581         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_oversize)},
 583         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 584                 mac_short_packet_dropped)},
 585         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_fragments)},
 587         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 588         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 589         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_127)},
 591         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_255)},
 593         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_511)},
 595         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1023)},
 597         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_1522)},
 599         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_big)},
 601         {"rx_flow_director_atr_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 603         {"rx_flow_director_sb_match_packets",
 604                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 605         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_status)},
 607         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_status)},
 609         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 tx_lpi_count)},
 611         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 612                 rx_lpi_count)},
 613 };
 614
 615 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 616                 sizeof(rte_i40e_hw_port_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_rx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_rx)},
 623 };
 624
 625 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 626                 sizeof(rte_i40e_rxq_prio_strings[0]))
 627
 628 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 629         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_tx)},
 631         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xoff_tx)},
 633         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xon_2_xoff)},
 635 };
 636
 637 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 638                 sizeof(rte_i40e_txq_prio_strings[0]))
 639
 640 static int
 641 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 642         struct rte_pci_device *pci_dev)
 643 {
 644         char name[RTE_ETH_NAME_MAX_LEN];
 645         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 646         int i, retval;
 647
 648         if (pci_dev->device.devargs) {
 649                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 650                                 &eth_da);
 651                 if (retval)
 652                         return retval;
 653         }
 654
 655         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 656                 sizeof(struct i40e_adapter),
 657                 eth_dev_pci_specific_init, pci_dev,
 658                 eth_i40e_dev_init, NULL);
 659
 660         if (retval || eth_da.nb_representor_ports < 1)
 661                 return retval;
 662
 663         /* probe VF representor ports */
 664         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 665                 pci_dev->device.name);
 666
 667         if (pf_ethdev == NULL)
 668                 return -ENODEV;
 669
 670         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 671                 struct i40e_vf_representor representor = {
 672                         .vf_id = eth_da.representor_ports[i],
 673                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 674                                 pf_ethdev->data->dev_private)->switch_domain_id,
 675                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 676                                 pf_ethdev->data->dev_private)
 677                 };
 678
 679                 /* representor port net_bdf_port */
 680                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 681                         pci_dev->device.name, eth_da.representor_ports[i]);
 682
 683                 retval = rte_eth_dev_create(&pci_dev->device, name,
 684                         sizeof(struct i40e_vf_representor), NULL, NULL,
 685                         i40e_vf_representor_init, &representor);
 686
 687                 if (retval)
 688                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 689                                 "representor %s.", name);
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 696 {
 697         struct rte_eth_dev *ethdev;
 698
 699         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 700         if (!ethdev)
 701                 return -ENODEV;
 702
 703
 704         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 705                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 706         else
 707                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 708 }
 709
 710 static struct rte_pci_driver rte_i40e_pmd = {
 711         .id_table = pci_id_i40e_map,
 712         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 713         .probe = eth_i40e_pci_probe,
 714         .remove = eth_i40e_pci_remove,
 715 };
 716
 717 static inline void
 718 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 719                          uint32_t reg_val)
 720 {
 721         uint32_t ori_reg_val;
 722         struct rte_eth_dev *dev;
 723
 724         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 725         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 726         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 727         if (ori_reg_val != reg_val)
 728                 PMD_DRV_LOG(WARNING,
 729                             "i40e device %s changed global register [0x%08x]."
 730                             " original: 0x%08x, new: 0x%08x",
 731                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 732 }
 733
 734 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 735 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 736 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 737
 738 #ifndef I40E_GLQF_ORT
 739 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 740 #endif
 741 #ifndef I40E_GLQF_PIT
 742 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 743 #endif
 744 #ifndef I40E_GLQF_L3_MAP
 745 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 746 #endif
 747
 748 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 749 {
 750         /*
 751          * Initialize registers for parsing packet type of QinQ
 752          * This should be removed from code once proper
 753          * configuration API is added to avoid configuration conflicts
 754          * between ports of the same device.
 755          */
 756         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 757         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 758 }
 759
 760 static inline void i40e_config_automask(struct i40e_pf *pf)
 761 {
 762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 763         uint32_t val;
 764
 765         /* INTENA flag is not auto-cleared for interrupt */
 766         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 767         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 768                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 769
 770         /* If support multi-driver, PF will use INT0. */
 771         if (!pf->support_multi_driver)
 772                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 773
 774         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 775 }
 776
 777 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 778
 779 /*
 780  * Add a ethertype filter to drop all flow control frames transmitted
 781  * from VSIs.
 782 */
 783 static void
 784 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 785 {
 786         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 787         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 788                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 789                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 790         int ret;
 791
 792         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 793                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 794                                 pf->main_vsi_seid, 0,
 795                                 TRUE, NULL, NULL);
 796         if (ret)
 797                 PMD_INIT_LOG(ERR,
 798                         "Failed to add filter to drop flow control frames from VSIs.");
 799 }
 800
 801 static int
 802 floating_veb_list_handler(__rte_unused const char *key,
 803                           const char *floating_veb_value,
 804                           void *opaque)
 805 {
 806         int idx = 0;
 807         unsigned int count = 0;
 808         char *end = NULL;
 809         int min, max;
 810         bool *vf_floating_veb = opaque;
 811
 812         while (isblank(*floating_veb_value))
 813                 floating_veb_value++;
 814
 815         /* Reset floating VEB configuration for VFs */
 816         for (idx = 0; idx < I40E_MAX_VF; idx++)
 817                 vf_floating_veb[idx] = false;
 818
 819         min = I40E_MAX_VF;
 820         do {
 821                 while (isblank(*floating_veb_value))
 822                         floating_veb_value++;
 823                 if (*floating_veb_value == '\0')
 824                         return -1;
 825                 errno = 0;
 826                 idx = strtoul(floating_veb_value, &end, 10);
 827                 if (errno || end == NULL)
 828                         return -1;
 829                 while (isblank(*end))
 830                         end++;
 831                 if (*end == '-') {
 832                         min = idx;
 833                 } else if ((*end == ';') || (*end == '\0')) {
 834                         max = idx;
 835                         if (min == I40E_MAX_VF)
 836                                 min = idx;
 837                         if (max >= I40E_MAX_VF)
 838                                 max = I40E_MAX_VF - 1;
 839                         for (idx = min; idx <= max; idx++) {
 840                                 vf_floating_veb[idx] = true;
 841                                 count++;
 842                         }
 843                         min = I40E_MAX_VF;
 844                 } else {
 845                         return -1;
 846                 }
 847                 floating_veb_value = end + 1;
 848         } while (*end != '\0');
 849
 850         if (count == 0)
 851                 return -1;
 852
 853         return 0;
 854 }
 855
 856 static void
 857 config_vf_floating_veb(struct rte_devargs *devargs,
 858                        uint16_t floating_veb,
 859                        bool *vf_floating_veb)
 860 {
 861         struct rte_kvargs *kvlist;
 862         int i;
 863         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 864
 865         if (!floating_veb)
 866                 return;
 867         /* All the VFs attach to the floating VEB by default
 868          * when the floating VEB is enabled.
 869          */
 870         for (i = 0; i < I40E_MAX_VF; i++)
 871                 vf_floating_veb[i] = true;
 872
 873         if (devargs == NULL)
 874                 return;
 875
 876         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 877         if (kvlist == NULL)
 878                 return;
 879
 880         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 881                 rte_kvargs_free(kvlist);
 882                 return;
 883         }
 884         /* When the floating_veb_list parameter exists, all the VFs
 885          * will attach to the legacy VEB firstly, then configure VFs
 886          * to the floating VEB according to the floating_veb_list.
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_list,
 889                                floating_veb_list_handler,
 890                                vf_floating_veb) < 0) {
 891                 rte_kvargs_free(kvlist);
 892                 return;
 893         }
 894         rte_kvargs_free(kvlist);
 895 }
 896
 897 static int
 898 i40e_check_floating_handler(__rte_unused const char *key,
 899                             const char *value,
 900                             __rte_unused void *opaque)
 901 {
 902         if (strcmp(value, "1"))
 903                 return -1;
 904
 905         return 0;
 906 }
 907
 908 static int
 909 is_floating_veb_supported(struct rte_devargs *devargs)
 910 {
 911         struct rte_kvargs *kvlist;
 912         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 913
 914         if (devargs == NULL)
 915                 return 0;
 916
 917         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 918         if (kvlist == NULL)
 919                 return 0;
 920
 921         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 922                 rte_kvargs_free(kvlist);
 923                 return 0;
 924         }
 925         /* Floating VEB is enabled when there's key-value:
 926          * enable_floating_veb=1
 927          */
 928         if (rte_kvargs_process(kvlist, floating_veb_key,
 929                                i40e_check_floating_handler, NULL) < 0) {
 930                 rte_kvargs_free(kvlist);
 931                 return 0;
 932         }
 933         rte_kvargs_free(kvlist);
 934
 935         return 1;
 936 }
 937
 938 static void
 939 config_floating_veb(struct rte_eth_dev *dev)
 940 {
 941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 944
 945         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 946
 947         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 948                 pf->floating_veb =
 949                         is_floating_veb_supported(pci_dev->device.devargs);
 950                 config_vf_floating_veb(pci_dev->device.devargs,
 951                                        pf->floating_veb,
 952                                        pf->floating_veb_list);
 953         } else {
 954                 pf->floating_veb = false;
 955         }
 956 }
 957
 958 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 959 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 960
 961 static int
 962 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 963 {
 964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 965         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 966         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 967         int ret;
 968
 969         struct rte_hash_parameters ethertype_hash_params = {
 970                 .name = ethertype_hash_name,
 971                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 972                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 973                 .hash_func = rte_hash_crc,
 974                 .hash_func_init_val = 0,
 975                 .socket_id = rte_socket_id(),
 976         };
 977
 978         /* Initialize ethertype filter rule list and hash */
 979         TAILQ_INIT(&ethertype_rule->ethertype_list);
 980         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 981                  "ethertype_%s", dev->device->name);
 982         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 983         if (!ethertype_rule->hash_table) {
 984                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 985                 return -EINVAL;
 986         }
 987         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 988                                        sizeof(struct i40e_ethertype_filter *) *
 989                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 990                                        0);
 991         if (!ethertype_rule->hash_map) {
 992                 PMD_INIT_LOG(ERR,
 993                              "Failed to allocate memory for ethertype hash map!");
 994                 ret = -ENOMEM;
 995                 goto err_ethertype_hash_map_alloc;
 996         }
 997
 998         return 0;
 999
1000 err_ethertype_hash_map_alloc:
1001         rte_hash_free(ethertype_rule->hash_table);
1002
1003         return ret;
1004 }
1005
1006 static int
1007 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1008 {
1009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1011         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1012         int ret;
1013
1014         struct rte_hash_parameters tunnel_hash_params = {
1015                 .name = tunnel_hash_name,
1016                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1017                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1018                 .hash_func = rte_hash_crc,
1019                 .hash_func_init_val = 0,
1020                 .socket_id = rte_socket_id(),
1021         };
1022
1023         /* Initialize tunnel filter rule list and hash */
1024         TAILQ_INIT(&tunnel_rule->tunnel_list);
1025         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1026                  "tunnel_%s", dev->device->name);
1027         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1028         if (!tunnel_rule->hash_table) {
1029                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1030                 return -EINVAL;
1031         }
1032         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1033                                     sizeof(struct i40e_tunnel_filter *) *
1034                                     I40E_MAX_TUNNEL_FILTER_NUM,
1035                                     0);
1036         if (!tunnel_rule->hash_map) {
1037                 PMD_INIT_LOG(ERR,
1038                              "Failed to allocate memory for tunnel hash map!");
1039                 ret = -ENOMEM;
1040                 goto err_tunnel_hash_map_alloc;
1041         }
1042
1043         return 0;
1044
1045 err_tunnel_hash_map_alloc:
1046         rte_hash_free(tunnel_rule->hash_table);
1047
1048         return ret;
1049 }
1050
1051 static int
1052 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1053 {
1054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055         struct i40e_fdir_info *fdir_info = &pf->fdir;
1056         char fdir_hash_name[RTE_HASH_NAMESIZE];
1057         int ret;
1058
1059         struct rte_hash_parameters fdir_hash_params = {
1060                 .name = fdir_hash_name,
1061                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1062                 .key_len = sizeof(struct i40e_fdir_input),
1063                 .hash_func = rte_hash_crc,
1064                 .hash_func_init_val = 0,
1065                 .socket_id = rte_socket_id(),
1066         };
1067
1068         /* Initialize flow director filter rule list and hash */
1069         TAILQ_INIT(&fdir_info->fdir_list);
1070         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1071                  "fdir_%s", dev->device->name);
1072         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1073         if (!fdir_info->hash_table) {
1074                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1075                 return -EINVAL;
1076         }
1077         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078                                           sizeof(struct i40e_fdir_filter *) *
1079                                           I40E_MAX_FDIR_FILTER_NUM,
1080                                           0);
1081         if (!fdir_info->hash_map) {
1082                 PMD_INIT_LOG(ERR,
1083                              "Failed to allocate memory for fdir hash map!");
1084                 ret = -ENOMEM;
1085                 goto err_fdir_hash_map_alloc;
1086         }
1087         return 0;
1088
1089 err_fdir_hash_map_alloc:
1090         rte_hash_free(fdir_info->hash_table);
1091
1092         return ret;
1093 }
1094
1095 static void
1096 i40e_init_customized_info(struct i40e_pf *pf)
1097 {
1098         int i;
1099
1100         /* Initialize customized pctype */
1101         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1102                 pf->customized_pctype[i].index = i;
1103                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1104                 pf->customized_pctype[i].valid = false;
1105         }
1106
1107         pf->gtp_support = false;
1108 }
1109
1110 void
1111 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1112 {
1113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1115         struct i40e_queue_regions *info = &pf->queue_region;
1116         uint16_t i;
1117
1118         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1119                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1120
1121         memset(info, 0, sizeof(struct i40e_queue_regions));
1122 }
1123
1124 static int
1125 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1126                                const char *value,
1127                                void *opaque)
1128 {
1129         struct i40e_pf *pf;
1130         unsigned long support_multi_driver;
1131         char *end;
1132
1133         pf = (struct i40e_pf *)opaque;
1134
1135         errno = 0;
1136         support_multi_driver = strtoul(value, &end, 10);
1137         if (errno != 0 || end == value || *end != 0) {
1138                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1139                 return -(EINVAL);
1140         }
1141
1142         if (support_multi_driver == 1 || support_multi_driver == 0)
1143                 pf->support_multi_driver = (bool)support_multi_driver;
1144         else
1145                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1146                             "enable global configuration by default."
1147                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1148         return 0;
1149 }
1150
1151 static int
1152 i40e_support_multi_driver(struct rte_eth_dev *dev)
1153 {
1154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1155         struct rte_kvargs *kvlist;
1156         int kvargs_count;
1157
1158         /* Enable global configuration by default */
1159         pf->support_multi_driver = false;
1160
1161         if (!dev->device->devargs)
1162                 return 0;
1163
1164         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1165         if (!kvlist)
1166                 return -EINVAL;
1167
1168         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1169         if (!kvargs_count) {
1170                 rte_kvargs_free(kvlist);
1171                 return 0;
1172         }
1173
1174         if (kvargs_count > 1)
1175                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1176                             "the first invalid or last valid one is used !",
1177                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1178
1179         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1180                                i40e_parse_multi_drv_handler, pf) < 0) {
1181                 rte_kvargs_free(kvlist);
1182                 return -EINVAL;
1183         }
1184
1185         rte_kvargs_free(kvlist);
1186         return 0;
1187 }
1188
1189 static int
1190 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1191                                     uint32_t reg_addr, uint64_t reg_val,
1192                                     struct i40e_asq_cmd_details *cmd_details)
1193 {
1194         uint64_t ori_reg_val;
1195         struct rte_eth_dev *dev;
1196         int ret;
1197
1198         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1199         if (ret != I40E_SUCCESS) {
1200                 PMD_DRV_LOG(ERR,
1201                             "Fail to debug read from 0x%08x",
1202                             reg_addr);
1203                 return -EIO;
1204         }
1205         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1206
1207         if (ori_reg_val != reg_val)
1208                 PMD_DRV_LOG(WARNING,
1209                             "i40e device %s changed global register [0x%08x]."
1210                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1211                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1212
1213         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1214 }
1215
1216 static int
1217 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1218                                 const char *value,
1219                                 void *opaque)
1220 {
1221         struct i40e_adapter *ad = opaque;
1222         int use_latest_vec;
1223
1224         use_latest_vec = atoi(value);
1225
1226         if (use_latest_vec != 0 && use_latest_vec != 1)
1227                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1228
1229         ad->use_latest_vec = (uint8_t)use_latest_vec;
1230
1231         return 0;
1232 }
1233
1234 static int
1235 i40e_use_latest_vec(struct rte_eth_dev *dev)
1236 {
1237         struct i40e_adapter *ad =
1238                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1239         struct rte_kvargs *kvlist;
1240         int kvargs_count;
1241
1242         ad->use_latest_vec = false;
1243
1244         if (!dev->device->devargs)
1245                 return 0;
1246
1247         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1248         if (!kvlist)
1249                 return -EINVAL;
1250
1251         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1252         if (!kvargs_count) {
1253                 rte_kvargs_free(kvlist);
1254                 return 0;
1255         }
1256
1257         if (kvargs_count > 1)
1258                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1259                             "the first invalid or last valid one is used !",
1260                             ETH_I40E_USE_LATEST_VEC);
1261
1262         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1263                                 i40e_parse_latest_vec_handler, ad) < 0) {
1264                 rte_kvargs_free(kvlist);
1265                 return -EINVAL;
1266         }
1267
1268         rte_kvargs_free(kvlist);
1269         return 0;
1270 }
1271
1272 static int
1273 read_vf_msg_config(__rte_unused const char *key,
1274                                const char *value,
1275                                void *opaque)
1276 {
1277         struct i40e_vf_msg_cfg *cfg = opaque;
1278
1279         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1280                         &cfg->ignore_second) != 3) {
1281                 memset(cfg, 0, sizeof(*cfg));
1282                 PMD_DRV_LOG(ERR, "format error! example: "
1283                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1284                 return -EINVAL;
1285         }
1286
1287         /*
1288          * If the message validation function been enabled, the 'period'
1289          * and 'ignore_second' must greater than 0.
1290          */
1291         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1292                 memset(cfg, 0, sizeof(*cfg));
1293                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1294                                 " number must be greater than 0!",
1295                                 ETH_I40E_VF_MSG_CFG);
1296                 return -EINVAL;
1297         }
1298
1299         return 0;
1300 }
1301
1302 static int
1303 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1304                 struct i40e_vf_msg_cfg *msg_cfg)
1305 {
1306         struct rte_kvargs *kvlist;
1307         int kvargs_count;
1308         int ret = 0;
1309
1310         memset(msg_cfg, 0, sizeof(*msg_cfg));
1311
1312         if (!dev->device->devargs)
1313                 return ret;
1314
1315         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1316         if (!kvlist)
1317                 return -EINVAL;
1318
1319         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1320         if (!kvargs_count)
1321                 goto free_end;
1322
1323         if (kvargs_count > 1) {
1324                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1325                                 ETH_I40E_VF_MSG_CFG);
1326                 ret = -EINVAL;
1327                 goto free_end;
1328         }
1329
1330         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1331                         read_vf_msg_config, msg_cfg) < 0)
1332                 ret = -EINVAL;
1333
1334 free_end:
1335         rte_kvargs_free(kvlist);
1336         return ret;
1337 }
1338
1339 #define I40E_ALARM_INTERVAL 50000 /* us */
1340
1341 static int
1342 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1343 {
1344         struct rte_pci_device *pci_dev;
1345         struct rte_intr_handle *intr_handle;
1346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1347         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         struct i40e_vsi *vsi;
1349         int ret;
1350         uint32_t len, val;
1351         uint8_t aq_fail = 0;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         dev->dev_ops = &i40e_eth_dev_ops;
1356         dev->rx_pkt_burst = i40e_recv_pkts;
1357         dev->tx_pkt_burst = i40e_xmit_pkts;
1358         dev->tx_pkt_prepare = i40e_prep_pkts;
1359
1360         /* for secondary processes, we don't initialise any further as primary
1361          * has already done this work. Only check we don't need a different
1362          * RX function */
1363         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1364                 i40e_set_rx_function(dev);
1365                 i40e_set_tx_function(dev);
1366                 return 0;
1367         }
1368         i40e_set_default_ptype_table(dev);
1369         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1370         intr_handle = &pci_dev->intr_handle;
1371
1372         rte_eth_copy_pci_info(dev, pci_dev);
1373
1374         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1375         pf->adapter->eth_dev = dev;
1376         pf->dev_data = dev->data;
1377
1378         hw->back = I40E_PF_TO_ADAPTER(pf);
1379         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1380         if (!hw->hw_addr) {
1381                 PMD_INIT_LOG(ERR,
1382                         "Hardware is not available, as address is NULL");
1383                 return -ENODEV;
1384         }
1385
1386         hw->vendor_id = pci_dev->id.vendor_id;
1387         hw->device_id = pci_dev->id.device_id;
1388         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1389         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1390         hw->bus.device = pci_dev->addr.devid;
1391         hw->bus.func = pci_dev->addr.function;
1392         hw->adapter_stopped = 0;
1393         hw->adapter_closed = 0;
1394
1395         /*
1396          * Switch Tag value should not be identical to either the First Tag
1397          * or Second Tag values. So set something other than common Ethertype
1398          * for internal switching.
1399          */
1400         hw->switch_tag = 0xffff;
1401
1402         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1403         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1404                 PMD_INIT_LOG(ERR, "\nERROR: "
1405                         "Firmware recovery mode detected. Limiting functionality.\n"
1406                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1407                         "User Guide for details on firmware recovery mode.");
1408                 return -EIO;
1409         }
1410
1411         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1412         /* Check if need to support multi-driver */
1413         i40e_support_multi_driver(dev);
1414         /* Check if users want the latest supported vec path */
1415         i40e_use_latest_vec(dev);
1416
1417         /* Make sure all is clean before doing PF reset */
1418         i40e_clear_hw(hw);
1419
1420         /* Reset here to make sure all is clean for each PF */
1421         ret = i40e_pf_reset(hw);
1422         if (ret) {
1423                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1424                 return ret;
1425         }
1426
1427         /* Initialize the shared code (base driver) */
1428         ret = i40e_init_shared_code(hw);
1429         if (ret) {
1430                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1431                 return ret;
1432         }
1433
1434         /* Initialize the parameters for adminq */
1435         i40e_init_adminq_parameter(hw);
1436         ret = i40e_init_adminq(hw);
1437         if (ret != I40E_SUCCESS) {
1438                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1439                 return -EIO;
1440         }
1441         /* Firmware of SFP x722 does not support adminq option */
1442         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1443                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1444
1445         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1446                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1447                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1448                      ((hw->nvm.version >> 12) & 0xf),
1449                      ((hw->nvm.version >> 4) & 0xff),
1450                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1451
1452         /* Initialize the hardware */
1453         i40e_hw_init(dev);
1454
1455         i40e_config_automask(pf);
1456
1457         i40e_set_default_pctype_table(dev);
1458
1459         /*
1460          * To work around the NVM issue, initialize registers
1461          * for packet type of QinQ by software.
1462          * It should be removed once issues are fixed in NVM.
1463          */
1464         if (!pf->support_multi_driver)
1465                 i40e_GLQF_reg_init(hw);
1466
1467         /* Initialize the input set for filters (hash and fd) to default value */
1468         i40e_filter_input_set_init(pf);
1469
1470         /* initialise the L3_MAP register */
1471         if (!pf->support_multi_driver) {
1472                 ret = i40e_aq_debug_write_global_register(hw,
1473                                                    I40E_GLQF_L3_MAP(40),
1474                                                    0x00000028,  NULL);
1475                 if (ret)
1476                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1477                                      ret);
1478                 PMD_INIT_LOG(DEBUG,
1479                              "Global register 0x%08x is changed with 0x28",
1480                              I40E_GLQF_L3_MAP(40));
1481         }
1482
1483         /* Need the special FW version to support floating VEB */
1484         config_floating_veb(dev);
1485         /* Clear PXE mode */
1486         i40e_clear_pxe_mode(hw);
1487         i40e_dev_sync_phy_type(hw);
1488
1489         /*
1490          * On X710, performance number is far from the expectation on recent
1491          * firmware versions. The fix for this issue may not be integrated in
1492          * the following firmware version. So the workaround in software driver
1493          * is needed. It needs to modify the initial values of 3 internal only
1494          * registers. Note that the workaround can be removed when it is fixed
1495          * in firmware in the future.
1496          */
1497         i40e_configure_registers(hw);
1498
1499         /* Get hw capabilities */
1500         ret = i40e_get_cap(hw);
1501         if (ret != I40E_SUCCESS) {
1502                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1503                 goto err_get_capabilities;
1504         }
1505
1506         /* Initialize parameters for PF */
1507         ret = i40e_pf_parameter_init(dev);
1508         if (ret != 0) {
1509                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1510                 goto err_parameter_init;
1511         }
1512
1513         /* Initialize the queue management */
1514         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1515         if (ret < 0) {
1516                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1517                 goto err_qp_pool_init;
1518         }
1519         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1520                                 hw->func_caps.num_msix_vectors - 1);
1521         if (ret < 0) {
1522                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1523                 goto err_msix_pool_init;
1524         }
1525
1526         /* Initialize lan hmc */
1527         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1528                                 hw->func_caps.num_rx_qp, 0, 0);
1529         if (ret != I40E_SUCCESS) {
1530                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1531                 goto err_init_lan_hmc;
1532         }
1533
1534         /* Configure lan hmc */
1535         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1536         if (ret != I40E_SUCCESS) {
1537                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1538                 goto err_configure_lan_hmc;
1539         }
1540
1541         /* Get and check the mac address */
1542         i40e_get_mac_addr(hw, hw->mac.addr);
1543         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1544                 PMD_INIT_LOG(ERR, "mac address is not valid");
1545                 ret = -EIO;
1546                 goto err_get_mac_addr;
1547         }
1548         /* Copy the permanent MAC address */
1549         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1550                         (struct rte_ether_addr *)hw->mac.perm_addr);
1551
1552         /* Disable flow control */
1553         hw->fc.requested_mode = I40E_FC_NONE;
1554         i40e_set_fc(hw, &aq_fail, TRUE);
1555
1556         /* Set the global registers with default ether type value */
1557         if (!pf->support_multi_driver) {
1558                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1559                                          RTE_ETHER_TYPE_VLAN);
1560                 if (ret != I40E_SUCCESS) {
1561                         PMD_INIT_LOG(ERR,
1562                                      "Failed to set the default outer "
1563                                      "VLAN ether type");
1564                         goto err_setup_pf_switch;
1565                 }
1566         }
1567
1568         /* PF setup, which includes VSI setup */
1569         ret = i40e_pf_setup(pf);
1570         if (ret) {
1571                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1572                 goto err_setup_pf_switch;
1573         }
1574
1575         vsi = pf->main_vsi;
1576
1577         /* Disable double vlan by default */
1578         i40e_vsi_config_double_vlan(vsi, FALSE);
1579
1580         /* Disable S-TAG identification when floating_veb is disabled */
1581         if (!pf->floating_veb) {
1582                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1583                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1584                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1585                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1586                 }
1587         }
1588
1589         if (!vsi->max_macaddrs)
1590                 len = RTE_ETHER_ADDR_LEN;
1591         else
1592                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1593
1594         /* Should be after VSI initialized */
1595         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1596         if (!dev->data->mac_addrs) {
1597                 PMD_INIT_LOG(ERR,
1598                         "Failed to allocated memory for storing mac address");
1599                 goto err_mac_alloc;
1600         }
1601         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1602                                         &dev->data->mac_addrs[0]);
1603
1604         /* Pass the information to the rte_eth_dev_close() that it should also
1605          * release the private port resources.
1606          */
1607         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1608
1609         /* Init dcb to sw mode by default */
1610         ret = i40e_dcb_init_configure(dev, TRUE);
1611         if (ret != I40E_SUCCESS) {
1612                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1613                 pf->flags &= ~I40E_FLAG_DCB;
1614         }
1615         /* Update HW struct after DCB configuration */
1616         i40e_get_cap(hw);
1617
1618         /* initialize pf host driver to setup SRIOV resource if applicable */
1619         i40e_pf_host_init(dev);
1620
1621         /* register callback func to eal lib */
1622         rte_intr_callback_register(intr_handle,
1623                                    i40e_dev_interrupt_handler, dev);
1624
1625         /* configure and enable device interrupt */
1626         i40e_pf_config_irq0(hw, TRUE);
1627         i40e_pf_enable_irq0(hw);
1628
1629         /* enable uio intr after callback register */
1630         rte_intr_enable(intr_handle);
1631
1632         /* By default disable flexible payload in global configuration */
1633         if (!pf->support_multi_driver)
1634                 i40e_flex_payload_reg_set_default(hw);
1635
1636         /*
1637          * Add an ethertype filter to drop all flow control frames transmitted
1638          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1639          * frames to wire.
1640          */
1641         i40e_add_tx_flow_control_drop_filter(pf);
1642
1643         /* Set the max frame size to 0x2600 by default,
1644          * in case other drivers changed the default value.
1645          */
1646         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1647
1648         /* initialize mirror rule list */
1649         TAILQ_INIT(&pf->mirror_list);
1650
1651         /* initialize Traffic Manager configuration */
1652         i40e_tm_conf_init(dev);
1653
1654         /* Initialize customized information */
1655         i40e_init_customized_info(pf);
1656
1657         ret = i40e_init_ethtype_filter_list(dev);
1658         if (ret < 0)
1659                 goto err_init_ethtype_filter_list;
1660         ret = i40e_init_tunnel_filter_list(dev);
1661         if (ret < 0)
1662                 goto err_init_tunnel_filter_list;
1663         ret = i40e_init_fdir_filter_list(dev);
1664         if (ret < 0)
1665                 goto err_init_fdir_filter_list;
1666
1667         /* initialize queue region configuration */
1668         i40e_init_queue_region_conf(dev);
1669
1670         /* initialize rss configuration from rte_flow */
1671         memset(&pf->rss_info, 0,
1672                 sizeof(struct i40e_rte_flow_rss_conf));
1673
1674         /* reset all stats of the device, including pf and main vsi */
1675         i40e_dev_stats_reset(dev);
1676
1677         return 0;
1678
1679 err_init_fdir_filter_list:
1680         rte_free(pf->tunnel.hash_table);
1681         rte_free(pf->tunnel.hash_map);
1682 err_init_tunnel_filter_list:
1683         rte_free(pf->ethertype.hash_table);
1684         rte_free(pf->ethertype.hash_map);
1685 err_init_ethtype_filter_list:
1686         rte_free(dev->data->mac_addrs);
1687         dev->data->mac_addrs = NULL;
1688 err_mac_alloc:
1689         i40e_vsi_release(pf->main_vsi);
1690 err_setup_pf_switch:
1691 err_get_mac_addr:
1692 err_configure_lan_hmc:
1693         (void)i40e_shutdown_lan_hmc(hw);
1694 err_init_lan_hmc:
1695         i40e_res_pool_destroy(&pf->msix_pool);
1696 err_msix_pool_init:
1697         i40e_res_pool_destroy(&pf->qp_pool);
1698 err_qp_pool_init:
1699 err_parameter_init:
1700 err_get_capabilities:
1701         (void)i40e_shutdown_adminq(hw);
1702
1703         return ret;
1704 }
1705
1706 static void
1707 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1708 {
1709         struct i40e_ethertype_filter *p_ethertype;
1710         struct i40e_ethertype_rule *ethertype_rule;
1711
1712         ethertype_rule = &pf->ethertype;
1713         /* Remove all ethertype filter rules and hash */
1714         if (ethertype_rule->hash_map)
1715                 rte_free(ethertype_rule->hash_map);
1716         if (ethertype_rule->hash_table)
1717                 rte_hash_free(ethertype_rule->hash_table);
1718
1719         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1720                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1721                              p_ethertype, rules);
1722                 rte_free(p_ethertype);
1723         }
1724 }
1725
1726 static void
1727 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1728 {
1729         struct i40e_tunnel_filter *p_tunnel;
1730         struct i40e_tunnel_rule *tunnel_rule;
1731
1732         tunnel_rule = &pf->tunnel;
1733         /* Remove all tunnel director rules and hash */
1734         if (tunnel_rule->hash_map)
1735                 rte_free(tunnel_rule->hash_map);
1736         if (tunnel_rule->hash_table)
1737                 rte_hash_free(tunnel_rule->hash_table);
1738
1739         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1740                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1741                 rte_free(p_tunnel);
1742         }
1743 }
1744
1745 static void
1746 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1747 {
1748         struct i40e_fdir_filter *p_fdir;
1749         struct i40e_fdir_info *fdir_info;
1750
1751         fdir_info = &pf->fdir;
1752         /* Remove all flow director rules and hash */
1753         if (fdir_info->hash_map)
1754                 rte_free(fdir_info->hash_map);
1755         if (fdir_info->hash_table)
1756                 rte_hash_free(fdir_info->hash_table);
1757
1758         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1759                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1760                 rte_free(p_fdir);
1761         }
1762 }
1763
1764 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1765 {
1766         /*
1767          * Disable by default flexible payload
1768          * for corresponding L2/L3/L4 layers.
1769          */
1770         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1771         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1772         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1773 }
1774
1775 static int
1776 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_hw *hw;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1783                 return 0;
1784
1785         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786
1787         if (hw->adapter_closed == 0)
1788                 i40e_dev_close(dev);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 i40e_dev_configure(struct rte_eth_dev *dev)
1795 {
1796         struct i40e_adapter *ad =
1797                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1798         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1801         int i, ret;
1802
1803         ret = i40e_dev_sync_phy_type(hw);
1804         if (ret)
1805                 return ret;
1806
1807         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1808          * bulk allocation or vector Rx preconditions we will reset it.
1809          */
1810         ad->rx_bulk_alloc_allowed = true;
1811         ad->rx_vec_allowed = true;
1812         ad->tx_simple_allowed = true;
1813         ad->tx_vec_allowed = true;
1814
1815         /* Only legacy filter API needs the following fdir config. So when the
1816          * legacy filter API is deprecated, the following codes should also be
1817          * removed.
1818          */
1819         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1820                 ret = i40e_fdir_setup(pf);
1821                 if (ret != I40E_SUCCESS) {
1822                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1823                         return -ENOTSUP;
1824                 }
1825                 ret = i40e_fdir_configure(dev);
1826                 if (ret < 0) {
1827                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1828                         goto err;
1829                 }
1830         } else
1831                 i40e_fdir_teardown(pf);
1832
1833         ret = i40e_dev_init_vlan(dev);
1834         if (ret < 0)
1835                 goto err;
1836
1837         /* VMDQ setup.
1838          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1839          *  RSS setting have different requirements.
1840          *  General PMD driver call sequence are NIC init, configure,
1841          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1842          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1843          *  applicable. So, VMDQ setting has to be done before
1844          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1845          *  For RSS setting, it will try to calculate actual configured RX queue
1846          *  number, which will be available after rx_queue_setup(). dev_start()
1847          *  function is good to place RSS setup.
1848          */
1849         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1850                 ret = i40e_vmdq_setup(dev);
1851                 if (ret)
1852                         goto err;
1853         }
1854
1855         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1856                 ret = i40e_dcb_setup(dev);
1857                 if (ret) {
1858                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1859                         goto err_dcb;
1860                 }
1861         }
1862
1863         TAILQ_INIT(&pf->flow_list);
1864
1865         return 0;
1866
1867 err_dcb:
1868         /* need to release vmdq resource if exists */
1869         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1870                 i40e_vsi_release(pf->vmdq[i].vsi);
1871                 pf->vmdq[i].vsi = NULL;
1872         }
1873         rte_free(pf->vmdq);
1874         pf->vmdq = NULL;
1875 err:
1876         /* Need to release fdir resource if exists.
1877          * Only legacy filter API needs the following fdir config. So when the
1878          * legacy filter API is deprecated, the following code should also be
1879          * removed.
1880          */
1881         i40e_fdir_teardown(pf);
1882         return ret;
1883 }
1884
1885 void
1886 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1887 {
1888         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1889         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1890         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1891         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1892         uint16_t msix_vect = vsi->msix_intr;
1893         uint16_t i;
1894
1895         for (i = 0; i < vsi->nb_qps; i++) {
1896                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1897                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1898                 rte_wmb();
1899         }
1900
1901         if (vsi->type != I40E_VSI_SRIOV) {
1902                 if (!rte_intr_allow_others(intr_handle)) {
1903                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1904                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1905                         I40E_WRITE_REG(hw,
1906                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1907                                        0);
1908                 } else {
1909                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1910                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1911                         I40E_WRITE_REG(hw,
1912                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1913                                                        msix_vect - 1), 0);
1914                 }
1915         } else {
1916                 uint32_t reg;
1917                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1918                         vsi->user_param + (msix_vect - 1);
1919
1920                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1921                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1922         }
1923         I40E_WRITE_FLUSH(hw);
1924 }
1925
1926 static void
1927 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1928                        int base_queue, int nb_queue,
1929                        uint16_t itr_idx)
1930 {
1931         int i;
1932         uint32_t val;
1933         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1934         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1935
1936         /* Bind all RX queues to allocated MSIX interrupt */
1937         for (i = 0; i < nb_queue; i++) {
1938                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1939                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1940                         ((base_queue + i + 1) <<
1941                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1942                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1943                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1944
1945                 if (i == nb_queue - 1)
1946                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1947                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1948         }
1949
1950         /* Write first RX queue to Link list register as the head element */
1951         if (vsi->type != I40E_VSI_SRIOV) {
1952                 uint16_t interval =
1953                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1954
1955                 if (msix_vect == I40E_MISC_VEC_ID) {
1956                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1957                                        (base_queue <<
1958                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1959                                        (0x0 <<
1960                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1963                                        interval);
1964                 } else {
1965                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1966                                        (base_queue <<
1967                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1968                                        (0x0 <<
1969                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1970                         I40E_WRITE_REG(hw,
1971                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1972                                                        msix_vect - 1),
1973                                        interval);
1974                 }
1975         } else {
1976                 uint32_t reg;
1977
1978                 if (msix_vect == I40E_MISC_VEC_ID) {
1979                         I40E_WRITE_REG(hw,
1980                                        I40E_VPINT_LNKLST0(vsi->user_param),
1981                                        (base_queue <<
1982                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1983                                        (0x0 <<
1984                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1985                 } else {
1986                         /* num_msix_vectors_vf needs to minus irq0 */
1987                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1988                                 vsi->user_param + (msix_vect - 1);
1989
1990                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1991                                        (base_queue <<
1992                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1993                                        (0x0 <<
1994                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1995                 }
1996         }
1997
1998         I40E_WRITE_FLUSH(hw);
1999 }
2000
2001 void
2002 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2003 {
2004         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2005         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2007         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2008         uint16_t msix_vect = vsi->msix_intr;
2009         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2010         uint16_t queue_idx = 0;
2011         int record = 0;
2012         int i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017         }
2018
2019         /* VF bind interrupt */
2020         if (vsi->type == I40E_VSI_SRIOV) {
2021                 __vsi_queues_bind_intr(vsi, msix_vect,
2022                                        vsi->base_queue, vsi->nb_qps,
2023                                        itr_idx);
2024                 return;
2025         }
2026
2027         /* PF & VMDq bind interrupt */
2028         if (rte_intr_dp_is_en(intr_handle)) {
2029                 if (vsi->type == I40E_VSI_MAIN) {
2030                         queue_idx = 0;
2031                         record = 1;
2032                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2033                         struct i40e_vsi *main_vsi =
2034                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2035                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2036                         record = 1;
2037                 }
2038         }
2039
2040         for (i = 0; i < vsi->nb_used_qps; i++) {
2041                 if (nb_msix <= 1) {
2042                         if (!rte_intr_allow_others(intr_handle))
2043                                 /* allow to share MISC_VEC_ID */
2044                                 msix_vect = I40E_MISC_VEC_ID;
2045
2046                         /* no enough msix_vect, map all to one */
2047                         __vsi_queues_bind_intr(vsi, msix_vect,
2048                                                vsi->base_queue + i,
2049                                                vsi->nb_used_qps - i,
2050                                                itr_idx);
2051                         for (; !!record && i < vsi->nb_used_qps; i++)
2052                                 intr_handle->intr_vec[queue_idx + i] =
2053                                         msix_vect;
2054                         break;
2055                 }
2056                 /* 1:1 queue/msix_vect mapping */
2057                 __vsi_queues_bind_intr(vsi, msix_vect,
2058                                        vsi->base_queue + i, 1,
2059                                        itr_idx);
2060                 if (!!record)
2061                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2062
2063                 msix_vect++;
2064                 nb_msix--;
2065         }
2066 }
2067
2068 static void
2069 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2070 {
2071         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2074         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2075         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2076         uint16_t msix_intr, i;
2077
2078         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2079                 for (i = 0; i < vsi->nb_msix; i++) {
2080                         msix_intr = vsi->msix_intr + i;
2081                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2082                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2083                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2084                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2085                 }
2086         else
2087                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2088                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2089                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2090                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2091
2092         I40E_WRITE_FLUSH(hw);
2093 }
2094
2095 static void
2096 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2097 {
2098         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2099         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2100         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2102         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2103         uint16_t msix_intr, i;
2104
2105         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2106                 for (i = 0; i < vsi->nb_msix; i++) {
2107                         msix_intr = vsi->msix_intr + i;
2108                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2109                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2110                 }
2111         else
2112                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2113                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2114
2115         I40E_WRITE_FLUSH(hw);
2116 }
2117
2118 static inline uint8_t
2119 i40e_parse_link_speeds(uint16_t link_speeds)
2120 {
2121         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2122
2123         if (link_speeds & ETH_LINK_SPEED_40G)
2124                 link_speed |= I40E_LINK_SPEED_40GB;
2125         if (link_speeds & ETH_LINK_SPEED_25G)
2126                 link_speed |= I40E_LINK_SPEED_25GB;
2127         if (link_speeds & ETH_LINK_SPEED_20G)
2128                 link_speed |= I40E_LINK_SPEED_20GB;
2129         if (link_speeds & ETH_LINK_SPEED_10G)
2130                 link_speed |= I40E_LINK_SPEED_10GB;
2131         if (link_speeds & ETH_LINK_SPEED_1G)
2132                 link_speed |= I40E_LINK_SPEED_1GB;
2133         if (link_speeds & ETH_LINK_SPEED_100M)
2134                 link_speed |= I40E_LINK_SPEED_100MB;
2135
2136         return link_speed;
2137 }
2138
2139 static int
2140 i40e_phy_conf_link(struct i40e_hw *hw,
2141                    uint8_t abilities,
2142                    uint8_t force_speed,
2143                    bool is_up)
2144 {
2145         enum i40e_status_code status;
2146         struct i40e_aq_get_phy_abilities_resp phy_ab;
2147         struct i40e_aq_set_phy_config phy_conf;
2148         enum i40e_aq_phy_type cnt;
2149         uint8_t avail_speed;
2150         uint32_t phy_type_mask = 0;
2151
2152         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2153                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2154                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2155                         I40E_AQ_PHY_FLAG_LOW_POWER;
2156         int ret = -ENOTSUP;
2157
2158         /* To get phy capabilities of available speeds. */
2159         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2160                                               NULL);
2161         if (status) {
2162                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2163                                 status);
2164                 return ret;
2165         }
2166         avail_speed = phy_ab.link_speed;
2167
2168         /* To get the current phy config. */
2169         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2170                                               NULL);
2171         if (status) {
2172                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2173                                 status);
2174                 return ret;
2175         }
2176
2177         /* If link needs to go up and it is in autoneg mode the speed is OK,
2178          * no need to set up again.
2179          */
2180         if (is_up && phy_ab.phy_type != 0 &&
2181                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2182                      phy_ab.link_speed != 0)
2183                 return I40E_SUCCESS;
2184
2185         memset(&phy_conf, 0, sizeof(phy_conf));
2186
2187         /* bits 0-2 use the values from get_phy_abilities_resp */
2188         abilities &= ~mask;
2189         abilities |= phy_ab.abilities & mask;
2190
2191         phy_conf.abilities = abilities;
2192
2193         /* If link needs to go up, but the force speed is not supported,
2194          * Warn users and config the default available speeds.
2195          */
2196         if (is_up && !(force_speed & avail_speed)) {
2197                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2198                 phy_conf.link_speed = avail_speed;
2199         } else {
2200                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2201         }
2202
2203         /* PHY type mask needs to include each type except PHY type extension */
2204         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2205                 phy_type_mask |= 1 << cnt;
2206
2207         /* use get_phy_abilities_resp value for the rest */
2208         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2209         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2210                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2211                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2212         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2213         phy_conf.eee_capability = phy_ab.eee_capability;
2214         phy_conf.eeer = phy_ab.eeer_val;
2215         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2216
2217         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2218                     phy_ab.abilities, phy_ab.link_speed);
2219         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2220                     phy_conf.abilities, phy_conf.link_speed);
2221
2222         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2223         if (status)
2224                 return ret;
2225
2226         return I40E_SUCCESS;
2227 }
2228
2229 static int
2230 i40e_apply_link_speed(struct rte_eth_dev *dev)
2231 {
2232         uint8_t speed;
2233         uint8_t abilities = 0;
2234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         struct rte_eth_conf *conf = &dev->data->dev_conf;
2236
2237         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2238                 conf->link_speeds = ETH_LINK_SPEED_40G |
2239                                     ETH_LINK_SPEED_25G |
2240                                     ETH_LINK_SPEED_20G |
2241                                     ETH_LINK_SPEED_10G |
2242                                     ETH_LINK_SPEED_1G |
2243                                     ETH_LINK_SPEED_100M;
2244         }
2245         speed = i40e_parse_link_speeds(conf->link_speeds);
2246         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2247                      I40E_AQ_PHY_AN_ENABLED |
2248                      I40E_AQ_PHY_LINK_ENABLED;
2249
2250         return i40e_phy_conf_link(hw, abilities, speed, true);
2251 }
2252
2253 static int
2254 i40e_dev_start(struct rte_eth_dev *dev)
2255 {
2256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         struct i40e_vsi *main_vsi = pf->main_vsi;
2259         int ret, i;
2260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2262         uint32_t intr_vector = 0;
2263         struct i40e_vsi *vsi;
2264
2265         hw->adapter_stopped = 0;
2266
2267         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2268                 PMD_INIT_LOG(ERR,
2269                 "Invalid link_speeds for port %u, autonegotiation disabled",
2270                               dev->data->port_id);
2271                 return -EINVAL;
2272         }
2273
2274         rte_intr_disable(intr_handle);
2275
2276         if ((rte_intr_cap_multiple(intr_handle) ||
2277              !RTE_ETH_DEV_SRIOV(dev).active) &&
2278             dev->data->dev_conf.intr_conf.rxq != 0) {
2279                 intr_vector = dev->data->nb_rx_queues;
2280                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2281                 if (ret)
2282                         return ret;
2283         }
2284
2285         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2286                 intr_handle->intr_vec =
2287                         rte_zmalloc("intr_vec",
2288                                     dev->data->nb_rx_queues * sizeof(int),
2289                                     0);
2290                 if (!intr_handle->intr_vec) {
2291                         PMD_INIT_LOG(ERR,
2292                                 "Failed to allocate %d rx_queues intr_vec",
2293                                 dev->data->nb_rx_queues);
2294                         return -ENOMEM;
2295                 }
2296         }
2297
2298         /* Initialize VSI */
2299         ret = i40e_dev_rxtx_init(pf);
2300         if (ret != I40E_SUCCESS) {
2301                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2302                 goto err_up;
2303         }
2304
2305         /* Map queues with MSIX interrupt */
2306         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2307                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2308         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2309         i40e_vsi_enable_queues_intr(main_vsi);
2310
2311         /* Map VMDQ VSI queues with MSIX interrupt */
2312         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2313                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2314                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2315                                           I40E_ITR_INDEX_DEFAULT);
2316                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2317         }
2318
2319         /* enable FDIR MSIX interrupt */
2320         if (pf->fdir.fdir_vsi) {
2321                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2322                                           I40E_ITR_INDEX_NONE);
2323                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2324         }
2325
2326         /* Enable all queues which have been configured */
2327         ret = i40e_dev_switch_queues(pf, TRUE);
2328         if (ret != I40E_SUCCESS) {
2329                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2330                 goto err_up;
2331         }
2332
2333         /* Enable receiving broadcast packets */
2334         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2335         if (ret != I40E_SUCCESS)
2336                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2337
2338         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2339                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2340                                                 true, NULL);
2341                 if (ret != I40E_SUCCESS)
2342                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2343         }
2344
2345         /* Enable the VLAN promiscuous mode. */
2346         if (pf->vfs) {
2347                 for (i = 0; i < pf->vf_num; i++) {
2348                         vsi = pf->vfs[i].vsi;
2349                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2350                                                      true, NULL);
2351                 }
2352         }
2353
2354         /* Enable mac loopback mode */
2355         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2356             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2357                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2358                 if (ret != I40E_SUCCESS) {
2359                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2360                         goto err_up;
2361                 }
2362         }
2363
2364         /* Apply link configure */
2365         ret = i40e_apply_link_speed(dev);
2366         if (I40E_SUCCESS != ret) {
2367                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2368                 goto err_up;
2369         }
2370
2371         if (!rte_intr_allow_others(intr_handle)) {
2372                 rte_intr_callback_unregister(intr_handle,
2373                                              i40e_dev_interrupt_handler,
2374                                              (void *)dev);
2375                 /* configure and enable device interrupt */
2376                 i40e_pf_config_irq0(hw, FALSE);
2377                 i40e_pf_enable_irq0(hw);
2378
2379                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2380                         PMD_INIT_LOG(INFO,
2381                                 "lsc won't enable because of no intr multiplex");
2382         } else {
2383                 ret = i40e_aq_set_phy_int_mask(hw,
2384                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2385                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2386                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2387                 if (ret != I40E_SUCCESS)
2388                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2389
2390                 /* Call get_link_info aq commond to enable/disable LSE */
2391                 i40e_dev_link_update(dev, 0);
2392         }
2393
2394         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2395                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2396                                   i40e_dev_alarm_handler, dev);
2397         } else {
2398                 /* enable uio intr after callback register */
2399                 rte_intr_enable(intr_handle);
2400         }
2401
2402         i40e_filter_restore(pf);
2403
2404         if (pf->tm_conf.root && !pf->tm_conf.committed)
2405                 PMD_DRV_LOG(WARNING,
2406                             "please call hierarchy_commit() "
2407                             "before starting the port");
2408
2409         return I40E_SUCCESS;
2410
2411 err_up:
2412         i40e_dev_switch_queues(pf, FALSE);
2413         i40e_dev_clear_queues(dev);
2414
2415         return ret;
2416 }
2417
2418 static void
2419 i40e_dev_stop(struct rte_eth_dev *dev)
2420 {
2421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct i40e_vsi *main_vsi = pf->main_vsi;
2424         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2425         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2426         int i;
2427
2428         if (hw->adapter_stopped == 1)
2429                 return;
2430
2431         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2432                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2433                 rte_intr_enable(intr_handle);
2434         }
2435
2436         /* Disable all queues */
2437         i40e_dev_switch_queues(pf, FALSE);
2438
2439         /* un-map queues with interrupt registers */
2440         i40e_vsi_disable_queues_intr(main_vsi);
2441         i40e_vsi_queues_unbind_intr(main_vsi);
2442
2443         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2444                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2445                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2446         }
2447
2448         if (pf->fdir.fdir_vsi) {
2449                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2450                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2451         }
2452         /* Clear all queues and release memory */
2453         i40e_dev_clear_queues(dev);
2454
2455         /* Set link down */
2456         i40e_dev_set_link_down(dev);
2457
2458         if (!rte_intr_allow_others(intr_handle))
2459                 /* resume to the default handler */
2460                 rte_intr_callback_register(intr_handle,
2461                                            i40e_dev_interrupt_handler,
2462                                            (void *)dev);
2463
2464         /* Clean datapath event and queue/vec mapping */
2465         rte_intr_efd_disable(intr_handle);
2466         if (intr_handle->intr_vec) {
2467                 rte_free(intr_handle->intr_vec);
2468                 intr_handle->intr_vec = NULL;
2469         }
2470
2471         /* reset hierarchy commit */
2472         pf->tm_conf.committed = false;
2473
2474         hw->adapter_stopped = 1;
2475
2476         pf->adapter->rss_reta_updated = 0;
2477 }
2478
2479 static void
2480 i40e_dev_close(struct rte_eth_dev *dev)
2481 {
2482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2485         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2486         struct i40e_mirror_rule *p_mirror;
2487         struct i40e_filter_control_settings settings;
2488         struct rte_flow *p_flow;
2489         uint32_t reg;
2490         int i;
2491         int ret;
2492         uint8_t aq_fail = 0;
2493         int retries = 0;
2494
2495         PMD_INIT_FUNC_TRACE();
2496
2497         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2498         if (ret)
2499                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2500
2501
2502         i40e_dev_stop(dev);
2503
2504         /* Remove all mirror rules */
2505         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2506                 ret = i40e_aq_del_mirror_rule(hw,
2507                                               pf->main_vsi->veb->seid,
2508                                               p_mirror->rule_type,
2509                                               p_mirror->entries,
2510                                               p_mirror->num_entries,
2511                                               p_mirror->id);
2512                 if (ret < 0)
2513                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2514                                     "status = %d, aq_err = %d.", ret,
2515                                     hw->aq.asq_last_status);
2516
2517                 /* remove mirror software resource anyway */
2518                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2519                 rte_free(p_mirror);
2520                 pf->nb_mirror_rule--;
2521         }
2522
2523         i40e_dev_free_queues(dev);
2524
2525         /* Disable interrupt */
2526         i40e_pf_disable_irq0(hw);
2527         rte_intr_disable(intr_handle);
2528
2529         /*
2530          * Only legacy filter API needs the following fdir config. So when the
2531          * legacy filter API is deprecated, the following code should also be
2532          * removed.
2533          */
2534         i40e_fdir_teardown(pf);
2535
2536         /* shutdown and destroy the HMC */
2537         i40e_shutdown_lan_hmc(hw);
2538
2539         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2540                 i40e_vsi_release(pf->vmdq[i].vsi);
2541                 pf->vmdq[i].vsi = NULL;
2542         }
2543         rte_free(pf->vmdq);
2544         pf->vmdq = NULL;
2545
2546         /* release all the existing VSIs and VEBs */
2547         i40e_vsi_release(pf->main_vsi);
2548
2549         /* shutdown the adminq */
2550         i40e_aq_queue_shutdown(hw, true);
2551         i40e_shutdown_adminq(hw);
2552
2553         i40e_res_pool_destroy(&pf->qp_pool);
2554         i40e_res_pool_destroy(&pf->msix_pool);
2555
2556         /* Disable flexible payload in global configuration */
2557         if (!pf->support_multi_driver)
2558                 i40e_flex_payload_reg_set_default(hw);
2559
2560         /* force a PF reset to clean anything leftover */
2561         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2562         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2563                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2564         I40E_WRITE_FLUSH(hw);
2565
2566         dev->dev_ops = NULL;
2567         dev->rx_pkt_burst = NULL;
2568         dev->tx_pkt_burst = NULL;
2569
2570         /* Clear PXE mode */
2571         i40e_clear_pxe_mode(hw);
2572
2573         /* Unconfigure filter control */
2574         memset(&settings, 0, sizeof(settings));
2575         ret = i40e_set_filter_control(hw, &settings);
2576         if (ret)
2577                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2578                                         ret);
2579
2580         /* Disable flow control */
2581         hw->fc.requested_mode = I40E_FC_NONE;
2582         i40e_set_fc(hw, &aq_fail, TRUE);
2583
2584         /* uninitialize pf host driver */
2585         i40e_pf_host_uninit(dev);
2586
2587         do {
2588                 ret = rte_intr_callback_unregister(intr_handle,
2589                                 i40e_dev_interrupt_handler, dev);
2590                 if (ret >= 0) {
2591                         break;
2592                 } else if (ret != -EAGAIN) {
2593                         PMD_INIT_LOG(ERR,
2594                                  "intr callback unregister failed: %d",
2595                                  ret);
2596                 }
2597                 i40e_msec_delay(500);
2598         } while (retries++ < 5);
2599
2600         i40e_rm_ethtype_filter_list(pf);
2601         i40e_rm_tunnel_filter_list(pf);
2602         i40e_rm_fdir_filter_list(pf);
2603
2604         /* Remove all flows */
2605         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2606                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2607                 rte_free(p_flow);
2608         }
2609
2610         /* Remove all Traffic Manager configuration */
2611         i40e_tm_conf_uninit(dev);
2612
2613         hw->adapter_closed = 1;
2614 }
2615
2616 /*
2617  * Reset PF device only to re-initialize resources in PMD layer
2618  */
2619 static int
2620 i40e_dev_reset(struct rte_eth_dev *dev)
2621 {
2622         int ret;
2623
2624         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2625          * its VF to make them align with it. The detailed notification
2626          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2627          * To avoid unexpected behavior in VF, currently reset of PF with
2628          * SR-IOV activation is not supported. It might be supported later.
2629          */
2630         if (dev->data->sriov.active)
2631                 return -ENOTSUP;
2632
2633         ret = eth_i40e_dev_uninit(dev);
2634         if (ret)
2635                 return ret;
2636
2637         ret = eth_i40e_dev_init(dev, NULL);
2638
2639         return ret;
2640 }
2641
2642 static int
2643 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2644 {
2645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct i40e_vsi *vsi = pf->main_vsi;
2648         int status;
2649
2650         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2651                                                      true, NULL, true);
2652         if (status != I40E_SUCCESS) {
2653                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2654                 return -EAGAIN;
2655         }
2656
2657         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2658                                                         TRUE, NULL);
2659         if (status != I40E_SUCCESS) {
2660                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2661                 /* Rollback unicast promiscuous mode */
2662                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2663                                                     false, NULL, true);
2664                 return -EAGAIN;
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int
2671 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2672 {
2673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         struct i40e_vsi *vsi = pf->main_vsi;
2676         int status;
2677
2678         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2679                                                      false, NULL, true);
2680         if (status != I40E_SUCCESS) {
2681                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2682                 return -EAGAIN;
2683         }
2684
2685         /* must remain in all_multicast mode */
2686         if (dev->data->all_multicast == 1)
2687                 return 0;
2688
2689         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2690                                                         false, NULL);
2691         if (status != I40E_SUCCESS) {
2692                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2693                 /* Rollback unicast promiscuous mode */
2694                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2695                                                     true, NULL, true);
2696                 return -EAGAIN;
2697         }
2698
2699         return 0;
2700 }
2701
2702 static int
2703 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2704 {
2705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         struct i40e_vsi *vsi = pf->main_vsi;
2708         int ret;
2709
2710         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2711         if (ret != I40E_SUCCESS) {
2712                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2713                 return -EAGAIN;
2714         }
2715
2716         return 0;
2717 }
2718
2719 static int
2720 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2721 {
2722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct i40e_vsi *vsi = pf->main_vsi;
2725         int ret;
2726
2727         if (dev->data->promiscuous == 1)
2728                 return 0; /* must remain in all_multicast mode */
2729
2730         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2731                                 vsi->seid, FALSE, NULL);
2732         if (ret != I40E_SUCCESS) {
2733                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2734                 return -EAGAIN;
2735         }
2736
2737         return 0;
2738 }
2739
2740 /*
2741  * Set device link up.
2742  */
2743 static int
2744 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2745 {
2746         /* re-apply link speed setting */
2747         return i40e_apply_link_speed(dev);
2748 }
2749
2750 /*
2751  * Set device link down.
2752  */
2753 static int
2754 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2755 {
2756         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2757         uint8_t abilities = 0;
2758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759
2760         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2761         return i40e_phy_conf_link(hw, abilities, speed, false);
2762 }
2763
2764 static __rte_always_inline void
2765 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2766 {
2767 /* Link status registers and values*/
2768 #define I40E_PRTMAC_LINKSTA             0x001E2420
2769 #define I40E_REG_LINK_UP                0x40000080
2770 #define I40E_PRTMAC_MACC                0x001E24E0
2771 #define I40E_REG_MACC_25GB              0x00020000
2772 #define I40E_REG_SPEED_MASK             0x38000000
2773 #define I40E_REG_SPEED_0                0x00000000
2774 #define I40E_REG_SPEED_1                0x08000000
2775 #define I40E_REG_SPEED_2                0x10000000
2776 #define I40E_REG_SPEED_3                0x18000000
2777 #define I40E_REG_SPEED_4                0x20000000
2778         uint32_t link_speed;
2779         uint32_t reg_val;
2780
2781         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2782         link_speed = reg_val & I40E_REG_SPEED_MASK;
2783         reg_val &= I40E_REG_LINK_UP;
2784         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2785
2786         if (unlikely(link->link_status == 0))
2787                 return;
2788
2789         /* Parse the link status */
2790         switch (link_speed) {
2791         case I40E_REG_SPEED_0:
2792                 link->link_speed = ETH_SPEED_NUM_100M;
2793                 break;
2794         case I40E_REG_SPEED_1:
2795                 link->link_speed = ETH_SPEED_NUM_1G;
2796                 break;
2797         case I40E_REG_SPEED_2:
2798                 if (hw->mac.type == I40E_MAC_X722)
2799                         link->link_speed = ETH_SPEED_NUM_2_5G;
2800                 else
2801                         link->link_speed = ETH_SPEED_NUM_10G;
2802                 break;
2803         case I40E_REG_SPEED_3:
2804                 if (hw->mac.type == I40E_MAC_X722) {
2805                         link->link_speed = ETH_SPEED_NUM_5G;
2806                 } else {
2807                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2808
2809                         if (reg_val & I40E_REG_MACC_25GB)
2810                                 link->link_speed = ETH_SPEED_NUM_25G;
2811                         else
2812                                 link->link_speed = ETH_SPEED_NUM_40G;
2813                 }
2814                 break;
2815         case I40E_REG_SPEED_4:
2816                 if (hw->mac.type == I40E_MAC_X722)
2817                         link->link_speed = ETH_SPEED_NUM_10G;
2818                 else
2819                         link->link_speed = ETH_SPEED_NUM_20G;
2820                 break;
2821         default:
2822                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2823                 break;
2824         }
2825 }
2826
2827 static __rte_always_inline void
2828 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2829         bool enable_lse, int wait_to_complete)
2830 {
2831 #define CHECK_INTERVAL             100  /* 100ms */
2832 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2833         uint32_t rep_cnt = MAX_REPEAT_TIME;
2834         struct i40e_link_status link_status;
2835         int status;
2836
2837         memset(&link_status, 0, sizeof(link_status));
2838
2839         do {
2840                 memset(&link_status, 0, sizeof(link_status));
2841
2842                 /* Get link status information from hardware */
2843                 status = i40e_aq_get_link_info(hw, enable_lse,
2844                                                 &link_status, NULL);
2845                 if (unlikely(status != I40E_SUCCESS)) {
2846                         link->link_speed = ETH_SPEED_NUM_NONE;
2847                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2848                         PMD_DRV_LOG(ERR, "Failed to get link info");
2849                         return;
2850                 }
2851
2852                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2853                 if (!wait_to_complete || link->link_status)
2854                         break;
2855
2856                 rte_delay_ms(CHECK_INTERVAL);
2857         } while (--rep_cnt);
2858
2859         /* Parse the link status */
2860         switch (link_status.link_speed) {
2861         case I40E_LINK_SPEED_100MB:
2862                 link->link_speed = ETH_SPEED_NUM_100M;
2863                 break;
2864         case I40E_LINK_SPEED_1GB:
2865                 link->link_speed = ETH_SPEED_NUM_1G;
2866                 break;
2867         case I40E_LINK_SPEED_10GB:
2868                 link->link_speed = ETH_SPEED_NUM_10G;
2869                 break;
2870         case I40E_LINK_SPEED_20GB:
2871                 link->link_speed = ETH_SPEED_NUM_20G;
2872                 break;
2873         case I40E_LINK_SPEED_25GB:
2874                 link->link_speed = ETH_SPEED_NUM_25G;
2875                 break;
2876         case I40E_LINK_SPEED_40GB:
2877                 link->link_speed = ETH_SPEED_NUM_40G;
2878                 break;
2879         default:
2880                 link->link_speed = ETH_SPEED_NUM_NONE;
2881                 break;
2882         }
2883 }
2884
2885 int
2886 i40e_dev_link_update(struct rte_eth_dev *dev,
2887                      int wait_to_complete)
2888 {
2889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct rte_eth_link link;
2891         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2892         int ret;
2893
2894         memset(&link, 0, sizeof(link));
2895
2896         /* i40e uses full duplex only */
2897         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2898         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2899                         ETH_LINK_SPEED_FIXED);
2900
2901         if (!wait_to_complete && !enable_lse)
2902                 update_link_reg(hw, &link);
2903         else
2904                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2905
2906         ret = rte_eth_linkstatus_set(dev, &link);
2907         i40e_notify_all_vfs_link_status(dev);
2908
2909         return ret;
2910 }
2911
2912 /* Get all the statistics of a VSI */
2913 void
2914 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2915 {
2916         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2917         struct i40e_eth_stats *nes = &vsi->eth_stats;
2918         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2919         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2920
2921         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2922                             vsi->offset_loaded, &oes->rx_bytes,
2923                             &nes->rx_bytes);
2924         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2925                             vsi->offset_loaded, &oes->rx_unicast,
2926                             &nes->rx_unicast);
2927         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2928                             vsi->offset_loaded, &oes->rx_multicast,
2929                             &nes->rx_multicast);
2930         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2931                             vsi->offset_loaded, &oes->rx_broadcast,
2932                             &nes->rx_broadcast);
2933         /* exclude CRC bytes */
2934         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2935                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2936
2937         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2938                             &oes->rx_discards, &nes->rx_discards);
2939         /* GLV_REPC not supported */
2940         /* GLV_RMPC not supported */
2941         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2942                             &oes->rx_unknown_protocol,
2943                             &nes->rx_unknown_protocol);
2944         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2945                             vsi->offset_loaded, &oes->tx_bytes,
2946                             &nes->tx_bytes);
2947         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2948                             vsi->offset_loaded, &oes->tx_unicast,
2949                             &nes->tx_unicast);
2950         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2951                             vsi->offset_loaded, &oes->tx_multicast,
2952                             &nes->tx_multicast);
2953         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2954                             vsi->offset_loaded,  &oes->tx_broadcast,
2955                             &nes->tx_broadcast);
2956         /* GLV_TDPC not supported */
2957         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2958                             &oes->tx_errors, &nes->tx_errors);
2959         vsi->offset_loaded = true;
2960
2961         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2962                     vsi->vsi_id);
2963         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2964         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2965         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2966         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2967         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2968         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2969                     nes->rx_unknown_protocol);
2970         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2971         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2972         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2973         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2974         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2975         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2976         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2977                     vsi->vsi_id);
2978 }
2979
2980 static void
2981 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2982 {
2983         unsigned int i;
2984         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2985         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2986
2987         /* Get rx/tx bytes of internal transfer packets */
2988         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2989                         I40E_GLV_GORCL(hw->port),
2990                         pf->offset_loaded,
2991                         &pf->internal_stats_offset.rx_bytes,
2992                         &pf->internal_stats.rx_bytes);
2993
2994         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2995                         I40E_GLV_GOTCL(hw->port),
2996                         pf->offset_loaded,
2997                         &pf->internal_stats_offset.tx_bytes,
2998                         &pf->internal_stats.tx_bytes);
2999         /* Get total internal rx packet count */
3000         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3001                             I40E_GLV_UPRCL(hw->port),
3002                             pf->offset_loaded,
3003                             &pf->internal_stats_offset.rx_unicast,
3004                             &pf->internal_stats.rx_unicast);
3005         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3006                             I40E_GLV_MPRCL(hw->port),
3007                             pf->offset_loaded,
3008                             &pf->internal_stats_offset.rx_multicast,
3009                             &pf->internal_stats.rx_multicast);
3010         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3011                             I40E_GLV_BPRCL(hw->port),
3012                             pf->offset_loaded,
3013                             &pf->internal_stats_offset.rx_broadcast,
3014                             &pf->internal_stats.rx_broadcast);
3015         /* Get total internal tx packet count */
3016         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3017                             I40E_GLV_UPTCL(hw->port),
3018                             pf->offset_loaded,
3019                             &pf->internal_stats_offset.tx_unicast,
3020                             &pf->internal_stats.tx_unicast);
3021         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3022                             I40E_GLV_MPTCL(hw->port),
3023                             pf->offset_loaded,
3024                             &pf->internal_stats_offset.tx_multicast,
3025                             &pf->internal_stats.tx_multicast);
3026         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3027                             I40E_GLV_BPTCL(hw->port),
3028                             pf->offset_loaded,
3029                             &pf->internal_stats_offset.tx_broadcast,
3030                             &pf->internal_stats.tx_broadcast);
3031
3032         /* exclude CRC size */
3033         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3034                 pf->internal_stats.rx_multicast +
3035                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3036
3037         /* Get statistics of struct i40e_eth_stats */
3038         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3039                             I40E_GLPRT_GORCL(hw->port),
3040                             pf->offset_loaded, &os->eth.rx_bytes,
3041                             &ns->eth.rx_bytes);
3042         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3043                             I40E_GLPRT_UPRCL(hw->port),
3044                             pf->offset_loaded, &os->eth.rx_unicast,
3045                             &ns->eth.rx_unicast);
3046         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3047                             I40E_GLPRT_MPRCL(hw->port),
3048                             pf->offset_loaded, &os->eth.rx_multicast,
3049                             &ns->eth.rx_multicast);
3050         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3051                             I40E_GLPRT_BPRCL(hw->port),
3052                             pf->offset_loaded, &os->eth.rx_broadcast,
3053                             &ns->eth.rx_broadcast);
3054         /* Workaround: CRC size should not be included in byte statistics,
3055          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3056          * packet.
3057          */
3058         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3059                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3060
3061         /* exclude internal rx bytes
3062          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3063          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3064          * value.
3065          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3066          */
3067         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3068                 ns->eth.rx_bytes = 0;
3069         else
3070                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3071
3072         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3073                 ns->eth.rx_unicast = 0;
3074         else
3075                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3076
3077         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3078                 ns->eth.rx_multicast = 0;
3079         else
3080                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3081
3082         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3083                 ns->eth.rx_broadcast = 0;
3084         else
3085                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3086
3087         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3088                             pf->offset_loaded, &os->eth.rx_discards,
3089                             &ns->eth.rx_discards);
3090         /* GLPRT_REPC not supported */
3091         /* GLPRT_RMPC not supported */
3092         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3093                             pf->offset_loaded,
3094                             &os->eth.rx_unknown_protocol,
3095                             &ns->eth.rx_unknown_protocol);
3096         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3097                             I40E_GLPRT_GOTCL(hw->port),
3098                             pf->offset_loaded, &os->eth.tx_bytes,
3099                             &ns->eth.tx_bytes);
3100         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3101                             I40E_GLPRT_UPTCL(hw->port),
3102                             pf->offset_loaded, &os->eth.tx_unicast,
3103                             &ns->eth.tx_unicast);
3104         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3105                             I40E_GLPRT_MPTCL(hw->port),
3106                             pf->offset_loaded, &os->eth.tx_multicast,
3107                             &ns->eth.tx_multicast);
3108         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3109                             I40E_GLPRT_BPTCL(hw->port),
3110                             pf->offset_loaded, &os->eth.tx_broadcast,
3111                             &ns->eth.tx_broadcast);
3112         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3113                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3114
3115         /* exclude internal tx bytes
3116          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3117          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3118          * value.
3119          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3120          */
3121         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3122                 ns->eth.tx_bytes = 0;
3123         else
3124                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3125
3126         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3127                 ns->eth.tx_unicast = 0;
3128         else
3129                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3130
3131         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3132                 ns->eth.tx_multicast = 0;
3133         else
3134                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3135
3136         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3137                 ns->eth.tx_broadcast = 0;
3138         else
3139                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3140
3141         /* GLPRT_TEPC not supported */
3142
3143         /* additional port specific stats */
3144         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3145                             pf->offset_loaded, &os->tx_dropped_link_down,
3146                             &ns->tx_dropped_link_down);
3147         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3148                             pf->offset_loaded, &os->crc_errors,
3149                             &ns->crc_errors);
3150         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3151                             pf->offset_loaded, &os->illegal_bytes,
3152                             &ns->illegal_bytes);
3153         /* GLPRT_ERRBC not supported */
3154         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3155                             pf->offset_loaded, &os->mac_local_faults,
3156                             &ns->mac_local_faults);
3157         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3158                             pf->offset_loaded, &os->mac_remote_faults,
3159                             &ns->mac_remote_faults);
3160         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3161                             pf->offset_loaded, &os->rx_length_errors,
3162                             &ns->rx_length_errors);
3163         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3164                             pf->offset_loaded, &os->link_xon_rx,
3165                             &ns->link_xon_rx);
3166         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3167                             pf->offset_loaded, &os->link_xoff_rx,
3168                             &ns->link_xoff_rx);
3169         for (i = 0; i < 8; i++) {
3170                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3171                                     pf->offset_loaded,
3172                                     &os->priority_xon_rx[i],
3173                                     &ns->priority_xon_rx[i]);
3174                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3175                                     pf->offset_loaded,
3176                                     &os->priority_xoff_rx[i],
3177                                     &ns->priority_xoff_rx[i]);
3178         }
3179         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3180                             pf->offset_loaded, &os->link_xon_tx,
3181                             &ns->link_xon_tx);
3182         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3183                             pf->offset_loaded, &os->link_xoff_tx,
3184                             &ns->link_xoff_tx);
3185         for (i = 0; i < 8; i++) {
3186                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3187                                     pf->offset_loaded,
3188                                     &os->priority_xon_tx[i],
3189                                     &ns->priority_xon_tx[i]);
3190                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3191                                     pf->offset_loaded,
3192                                     &os->priority_xoff_tx[i],
3193                                     &ns->priority_xoff_tx[i]);
3194                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3195                                     pf->offset_loaded,
3196                                     &os->priority_xon_2_xoff[i],
3197                                     &ns->priority_xon_2_xoff[i]);
3198         }
3199         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3200                             I40E_GLPRT_PRC64L(hw->port),
3201                             pf->offset_loaded, &os->rx_size_64,
3202                             &ns->rx_size_64);
3203         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3204                             I40E_GLPRT_PRC127L(hw->port),
3205                             pf->offset_loaded, &os->rx_size_127,
3206                             &ns->rx_size_127);
3207         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3208                             I40E_GLPRT_PRC255L(hw->port),
3209                             pf->offset_loaded, &os->rx_size_255,
3210                             &ns->rx_size_255);
3211         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3212                             I40E_GLPRT_PRC511L(hw->port),
3213                             pf->offset_loaded, &os->rx_size_511,
3214                             &ns->rx_size_511);
3215         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3216                             I40E_GLPRT_PRC1023L(hw->port),
3217                             pf->offset_loaded, &os->rx_size_1023,
3218                             &ns->rx_size_1023);
3219         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3220                             I40E_GLPRT_PRC1522L(hw->port),
3221                             pf->offset_loaded, &os->rx_size_1522,
3222                             &ns->rx_size_1522);
3223         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3224                             I40E_GLPRT_PRC9522L(hw->port),
3225                             pf->offset_loaded, &os->rx_size_big,
3226                             &ns->rx_size_big);
3227         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3228                             pf->offset_loaded, &os->rx_undersize,
3229                             &ns->rx_undersize);
3230         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3231                             pf->offset_loaded, &os->rx_fragments,
3232                             &ns->rx_fragments);
3233         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3234                             pf->offset_loaded, &os->rx_oversize,
3235                             &ns->rx_oversize);
3236         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3237                             pf->offset_loaded, &os->rx_jabber,
3238                             &ns->rx_jabber);
3239         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3240                             I40E_GLPRT_PTC64L(hw->port),
3241                             pf->offset_loaded, &os->tx_size_64,
3242                             &ns->tx_size_64);
3243         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3244                             I40E_GLPRT_PTC127L(hw->port),
3245                             pf->offset_loaded, &os->tx_size_127,
3246                             &ns->tx_size_127);
3247         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3248                             I40E_GLPRT_PTC255L(hw->port),
3249                             pf->offset_loaded, &os->tx_size_255,
3250                             &ns->tx_size_255);
3251         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3252                             I40E_GLPRT_PTC511L(hw->port),
3253                             pf->offset_loaded, &os->tx_size_511,
3254                             &ns->tx_size_511);
3255         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3256                             I40E_GLPRT_PTC1023L(hw->port),
3257                             pf->offset_loaded, &os->tx_size_1023,
3258                             &ns->tx_size_1023);
3259         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3260                             I40E_GLPRT_PTC1522L(hw->port),
3261                             pf->offset_loaded, &os->tx_size_1522,
3262                             &ns->tx_size_1522);
3263         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3264                             I40E_GLPRT_PTC9522L(hw->port),
3265                             pf->offset_loaded, &os->tx_size_big,
3266                             &ns->tx_size_big);
3267         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3268                            pf->offset_loaded,
3269                            &os->fd_sb_match, &ns->fd_sb_match);
3270         /* GLPRT_MSPDC not supported */
3271         /* GLPRT_XEC not supported */
3272
3273         pf->offset_loaded = true;
3274
3275         if (pf->main_vsi)
3276                 i40e_update_vsi_stats(pf->main_vsi);
3277 }
3278
3279 /* Get all statistics of a port */
3280 static int
3281 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3282 {
3283         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3286         struct i40e_vsi *vsi;
3287         unsigned i;
3288
3289         /* call read registers - updates values, now write them to struct */
3290         i40e_read_stats_registers(pf, hw);
3291
3292         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3293                         pf->main_vsi->eth_stats.rx_multicast +
3294                         pf->main_vsi->eth_stats.rx_broadcast -
3295                         pf->main_vsi->eth_stats.rx_discards;
3296         stats->opackets = ns->eth.tx_unicast +
3297                         ns->eth.tx_multicast +
3298                         ns->eth.tx_broadcast;
3299         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3300         stats->obytes   = ns->eth.tx_bytes;
3301         stats->oerrors  = ns->eth.tx_errors +
3302                         pf->main_vsi->eth_stats.tx_errors;
3303
3304         /* Rx Errors */
3305         stats->imissed  = ns->eth.rx_discards +
3306                         pf->main_vsi->eth_stats.rx_discards;
3307         stats->ierrors  = ns->crc_errors +
3308                         ns->rx_length_errors + ns->rx_undersize +
3309                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3310
3311         if (pf->vfs) {
3312                 for (i = 0; i < pf->vf_num; i++) {
3313                         vsi = pf->vfs[i].vsi;
3314                         i40e_update_vsi_stats(vsi);
3315
3316                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3317                                         vsi->eth_stats.rx_multicast +
3318                                         vsi->eth_stats.rx_broadcast -
3319                                         vsi->eth_stats.rx_discards);
3320                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3321                         stats->oerrors  += vsi->eth_stats.tx_errors;
3322                         stats->imissed  += vsi->eth_stats.rx_discards;
3323                 }
3324         }
3325
3326         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3327         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3328         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3329         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3330         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3331         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3332         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3333                     ns->eth.rx_unknown_protocol);
3334         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3335         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3336         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3337         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3338         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3339         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3340
3341         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3342                     ns->tx_dropped_link_down);
3343         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3344         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3345                     ns->illegal_bytes);
3346         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3347         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3348                     ns->mac_local_faults);
3349         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3350                     ns->mac_remote_faults);
3351         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3352                     ns->rx_length_errors);
3353         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3354         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3355         for (i = 0; i < 8; i++) {
3356                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3357                                 i, ns->priority_xon_rx[i]);
3358                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3359                                 i, ns->priority_xoff_rx[i]);
3360         }
3361         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3362         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3363         for (i = 0; i < 8; i++) {
3364                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3365                                 i, ns->priority_xon_tx[i]);
3366                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3367                                 i, ns->priority_xoff_tx[i]);
3368                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3369                                 i, ns->priority_xon_2_xoff[i]);
3370         }
3371         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3372         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3373         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3374         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3375         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3376         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3377         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3378         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3379         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3380         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3381         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3382         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3383         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3384         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3385         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3386         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3387         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3388         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3389         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3390                         ns->mac_short_packet_dropped);
3391         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3392                     ns->checksum_error);
3393         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3394         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3395         return 0;
3396 }
3397
3398 /* Reset the statistics */
3399 static int
3400 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3401 {
3402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404
3405         /* Mark PF and VSI stats to update the offset, aka "reset" */
3406         pf->offset_loaded = false;
3407         if (pf->main_vsi)
3408                 pf->main_vsi->offset_loaded = false;
3409
3410         /* read the stats, reading current register values into offset */
3411         i40e_read_stats_registers(pf, hw);
3412
3413         return 0;
3414 }
3415
3416 static uint32_t
3417 i40e_xstats_calc_num(void)
3418 {
3419         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3420                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3421                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3422 }
3423
3424 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3425                                      struct rte_eth_xstat_name *xstats_names,
3426                                      __rte_unused unsigned limit)
3427 {
3428         unsigned count = 0;
3429         unsigned i, prio;
3430
3431         if (xstats_names == NULL)
3432                 return i40e_xstats_calc_num();
3433
3434         /* Note: limit checked in rte_eth_xstats_names() */
3435
3436         /* Get stats from i40e_eth_stats struct */
3437         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3438                 strlcpy(xstats_names[count].name,
3439                         rte_i40e_stats_strings[i].name,
3440                         sizeof(xstats_names[count].name));
3441                 count++;
3442         }
3443
3444         /* Get individiual stats from i40e_hw_port struct */
3445         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3446                 strlcpy(xstats_names[count].name,
3447                         rte_i40e_hw_port_strings[i].name,
3448                         sizeof(xstats_names[count].name));
3449                 count++;
3450         }
3451
3452         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3453                 for (prio = 0; prio < 8; prio++) {
3454                         snprintf(xstats_names[count].name,
3455                                  sizeof(xstats_names[count].name),
3456                                  "rx_priority%u_%s", prio,
3457                                  rte_i40e_rxq_prio_strings[i].name);
3458                         count++;
3459                 }
3460         }
3461
3462         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3463                 for (prio = 0; prio < 8; prio++) {
3464                         snprintf(xstats_names[count].name,
3465                                  sizeof(xstats_names[count].name),
3466                                  "tx_priority%u_%s", prio,
3467                                  rte_i40e_txq_prio_strings[i].name);
3468                         count++;
3469                 }
3470         }
3471         return count;
3472 }
3473
3474 static int
3475 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3476                     unsigned n)
3477 {
3478         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3479         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         unsigned i, count, prio;
3481         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3482
3483         count = i40e_xstats_calc_num();
3484         if (n < count)
3485                 return count;
3486
3487         i40e_read_stats_registers(pf, hw);
3488
3489         if (xstats == NULL)
3490                 return 0;
3491
3492         count = 0;
3493
3494         /* Get stats from i40e_eth_stats struct */
3495         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3496                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3497                         rte_i40e_stats_strings[i].offset);
3498                 xstats[count].id = count;
3499                 count++;
3500         }
3501
3502         /* Get individiual stats from i40e_hw_port struct */
3503         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3504                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3505                         rte_i40e_hw_port_strings[i].offset);
3506                 xstats[count].id = count;
3507                 count++;
3508         }
3509
3510         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3511                 for (prio = 0; prio < 8; prio++) {
3512                         xstats[count].value =
3513                                 *(uint64_t *)(((char *)hw_stats) +
3514                                 rte_i40e_rxq_prio_strings[i].offset +
3515                                 (sizeof(uint64_t) * prio));
3516                         xstats[count].id = count;
3517                         count++;
3518                 }
3519         }
3520
3521         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3522                 for (prio = 0; prio < 8; prio++) {
3523                         xstats[count].value =
3524                                 *(uint64_t *)(((char *)hw_stats) +
3525                                 rte_i40e_txq_prio_strings[i].offset +
3526                                 (sizeof(uint64_t) * prio));
3527                         xstats[count].id = count;
3528                         count++;
3529                 }
3530         }
3531
3532         return count;
3533 }
3534
3535 static int
3536 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3537 {
3538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         u32 full_ver;
3540         u8 ver, patch;
3541         u16 build;
3542         int ret;
3543
3544         full_ver = hw->nvm.oem_ver;
3545         ver = (u8)(full_ver >> 24);
3546         build = (u16)((full_ver >> 8) & 0xffff);
3547         patch = (u8)(full_ver & 0xff);
3548
3549         ret = snprintf(fw_version, fw_size,
3550                  "%d.%d%d 0x%08x %d.%d.%d",
3551                  ((hw->nvm.version >> 12) & 0xf),
3552                  ((hw->nvm.version >> 4) & 0xff),
3553                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3554                  ver, build, patch);
3555
3556         ret += 1; /* add the size of '\0' */
3557         if (fw_size < (u32)ret)
3558                 return ret;
3559         else
3560                 return 0;
3561 }
3562
3563 /*
3564  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3565  * the Rx data path does not hang if the FW LLDP is stopped.
3566  * return true if lldp need to stop
3567  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3568  */
3569 static bool
3570 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3571 {
3572         double nvm_ver;
3573         char ver_str[64] = {0};
3574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575
3576         i40e_fw_version_get(dev, ver_str, 64);
3577         nvm_ver = atof(ver_str);
3578         if ((hw->mac.type == I40E_MAC_X722 ||
3579              hw->mac.type == I40E_MAC_X722_VF) &&
3580              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3581                 return true;
3582         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3583                 return true;
3584
3585         return false;
3586 }
3587
3588 static int
3589 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3590 {
3591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         struct i40e_vsi *vsi = pf->main_vsi;
3594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3595
3596         dev_info->max_rx_queues = vsi->nb_qps;
3597         dev_info->max_tx_queues = vsi->nb_qps;
3598         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3599         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3600         dev_info->max_mac_addrs = vsi->max_macaddrs;
3601         dev_info->max_vfs = pci_dev->max_vfs;
3602         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3603         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3604         dev_info->rx_queue_offload_capa = 0;
3605         dev_info->rx_offload_capa =
3606                 DEV_RX_OFFLOAD_VLAN_STRIP |
3607                 DEV_RX_OFFLOAD_QINQ_STRIP |
3608                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3609                 DEV_RX_OFFLOAD_UDP_CKSUM |
3610                 DEV_RX_OFFLOAD_TCP_CKSUM |
3611                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3612                 DEV_RX_OFFLOAD_KEEP_CRC |
3613                 DEV_RX_OFFLOAD_SCATTER |
3614                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3615                 DEV_RX_OFFLOAD_VLAN_FILTER |
3616                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3617
3618         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3619         dev_info->tx_offload_capa =
3620                 DEV_TX_OFFLOAD_VLAN_INSERT |
3621                 DEV_TX_OFFLOAD_QINQ_INSERT |
3622                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3623                 DEV_TX_OFFLOAD_UDP_CKSUM |
3624                 DEV_TX_OFFLOAD_TCP_CKSUM |
3625                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3626                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3627                 DEV_TX_OFFLOAD_TCP_TSO |
3628                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3629                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3630                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3631                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3632                 DEV_TX_OFFLOAD_MULTI_SEGS |
3633                 dev_info->tx_queue_offload_capa;
3634         dev_info->dev_capa =
3635                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3636                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3637
3638         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3639                                                 sizeof(uint32_t);
3640         dev_info->reta_size = pf->hash_lut_size;
3641         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3642
3643         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3644                 .rx_thresh = {
3645                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3646                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3647                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3648                 },
3649                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3650                 .rx_drop_en = 0,
3651                 .offloads = 0,
3652         };
3653
3654         dev_info->default_txconf = (struct rte_eth_txconf) {
3655                 .tx_thresh = {
3656                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3657                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3658                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3659                 },
3660                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3661                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3662                 .offloads = 0,
3663         };
3664
3665         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3666                 .nb_max = I40E_MAX_RING_DESC,
3667                 .nb_min = I40E_MIN_RING_DESC,
3668                 .nb_align = I40E_ALIGN_RING_DESC,
3669         };
3670
3671         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3672                 .nb_max = I40E_MAX_RING_DESC,
3673                 .nb_min = I40E_MIN_RING_DESC,
3674                 .nb_align = I40E_ALIGN_RING_DESC,
3675                 .nb_seg_max = I40E_TX_MAX_SEG,
3676                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3677         };
3678
3679         if (pf->flags & I40E_FLAG_VMDQ) {
3680                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3681                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3682                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3683                                                 pf->max_nb_vmdq_vsi;
3684                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3685                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3686                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3687         }
3688
3689         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3690                 /* For XL710 */
3691                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3692                 dev_info->default_rxportconf.nb_queues = 2;
3693                 dev_info->default_txportconf.nb_queues = 2;
3694                 if (dev->data->nb_rx_queues == 1)
3695                         dev_info->default_rxportconf.ring_size = 2048;
3696                 else
3697                         dev_info->default_rxportconf.ring_size = 1024;
3698                 if (dev->data->nb_tx_queues == 1)
3699                         dev_info->default_txportconf.ring_size = 1024;
3700                 else
3701                         dev_info->default_txportconf.ring_size = 512;
3702
3703         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3704                 /* For XXV710 */
3705                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3706                 dev_info->default_rxportconf.nb_queues = 1;
3707                 dev_info->default_txportconf.nb_queues = 1;
3708                 dev_info->default_rxportconf.ring_size = 256;
3709                 dev_info->default_txportconf.ring_size = 256;
3710         } else {
3711                 /* For X710 */
3712                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3713                 dev_info->default_rxportconf.nb_queues = 1;
3714                 dev_info->default_txportconf.nb_queues = 1;
3715                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3716                         dev_info->default_rxportconf.ring_size = 512;
3717                         dev_info->default_txportconf.ring_size = 256;
3718                 } else {
3719                         dev_info->default_rxportconf.ring_size = 256;
3720                         dev_info->default_txportconf.ring_size = 256;
3721                 }
3722         }
3723         dev_info->default_rxportconf.burst_size = 32;
3724         dev_info->default_txportconf.burst_size = 32;
3725
3726         return 0;
3727 }
3728
3729 static int
3730 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3731 {
3732         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3733         struct i40e_vsi *vsi = pf->main_vsi;
3734         PMD_INIT_FUNC_TRACE();
3735
3736         if (on)
3737                 return i40e_vsi_add_vlan(vsi, vlan_id);
3738         else
3739                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3740 }
3741
3742 static int
3743 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3744                                 enum rte_vlan_type vlan_type,
3745                                 uint16_t tpid, int qinq)
3746 {
3747         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         uint64_t reg_r = 0;
3749         uint64_t reg_w = 0;
3750         uint16_t reg_id = 3;
3751         int ret;
3752
3753         if (qinq) {
3754                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3755                         reg_id = 2;
3756         }
3757
3758         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3759                                           &reg_r, NULL);
3760         if (ret != I40E_SUCCESS) {
3761                 PMD_DRV_LOG(ERR,
3762                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3763                            reg_id);
3764                 return -EIO;
3765         }
3766         PMD_DRV_LOG(DEBUG,
3767                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3768                     reg_id, reg_r);
3769
3770         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3771         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3772         if (reg_r == reg_w) {
3773                 PMD_DRV_LOG(DEBUG, "No need to write");
3774                 return 0;
3775         }
3776
3777         ret = i40e_aq_debug_write_global_register(hw,
3778                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3779                                            reg_w, NULL);
3780         if (ret != I40E_SUCCESS) {
3781                 PMD_DRV_LOG(ERR,
3782                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3783                             reg_id);
3784                 return -EIO;
3785         }
3786         PMD_DRV_LOG(DEBUG,
3787                     "Global register 0x%08x is changed with value 0x%08x",
3788                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3789
3790         return 0;
3791 }
3792
3793 static int
3794 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3795                    enum rte_vlan_type vlan_type,
3796                    uint16_t tpid)
3797 {
3798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3800         int qinq = dev->data->dev_conf.rxmode.offloads &
3801                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3802         int ret = 0;
3803
3804         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3805              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3806             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3807                 PMD_DRV_LOG(ERR,
3808                             "Unsupported vlan type.");
3809                 return -EINVAL;
3810         }
3811
3812         if (pf->support_multi_driver) {
3813                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3814                 return -ENOTSUP;
3815         }
3816
3817         /* 802.1ad frames ability is added in NVM API 1.7*/
3818         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3819                 if (qinq) {
3820                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3821                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3822                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3823                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3824                 } else {
3825                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3826                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3827                 }
3828                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3829                 if (ret != I40E_SUCCESS) {
3830                         PMD_DRV_LOG(ERR,
3831                                     "Set switch config failed aq_err: %d",
3832                                     hw->aq.asq_last_status);
3833                         ret = -EIO;
3834                 }
3835         } else
3836                 /* If NVM API < 1.7, keep the register setting */
3837                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3838                                                       tpid, qinq);
3839
3840         return ret;
3841 }
3842
3843 static int
3844 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3845 {
3846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3847         struct i40e_vsi *vsi = pf->main_vsi;
3848         struct rte_eth_rxmode *rxmode;
3849
3850         rxmode = &dev->data->dev_conf.rxmode;
3851         if (mask & ETH_VLAN_FILTER_MASK) {
3852                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3853                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3854                 else
3855                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3856         }
3857
3858         if (mask & ETH_VLAN_STRIP_MASK) {
3859                 /* Enable or disable VLAN stripping */
3860                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3861                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3862                 else
3863                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3864         }
3865
3866         if (mask & ETH_VLAN_EXTEND_MASK) {
3867                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3868                         i40e_vsi_config_double_vlan(vsi, TRUE);
3869                         /* Set global registers with default ethertype. */
3870                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3871                                            RTE_ETHER_TYPE_VLAN);
3872                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3873                                            RTE_ETHER_TYPE_VLAN);
3874                 }
3875                 else
3876                         i40e_vsi_config_double_vlan(vsi, FALSE);
3877         }
3878
3879         return 0;
3880 }
3881
3882 static void
3883 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3884                           __rte_unused uint16_t queue,
3885                           __rte_unused int on)
3886 {
3887         PMD_INIT_FUNC_TRACE();
3888 }
3889
3890 static int
3891 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3892 {
3893         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3894         struct i40e_vsi *vsi = pf->main_vsi;
3895         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3896         struct i40e_vsi_vlan_pvid_info info;
3897
3898         memset(&info, 0, sizeof(info));
3899         info.on = on;
3900         if (info.on)
3901                 info.config.pvid = pvid;
3902         else {
3903                 info.config.reject.tagged =
3904                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3905                 info.config.reject.untagged =
3906                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3907         }
3908
3909         return i40e_vsi_vlan_pvid_set(vsi, &info);
3910 }
3911
3912 static int
3913 i40e_dev_led_on(struct rte_eth_dev *dev)
3914 {
3915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3916         uint32_t mode = i40e_led_get(hw);
3917
3918         if (mode == 0)
3919                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3920
3921         return 0;
3922 }
3923
3924 static int
3925 i40e_dev_led_off(struct rte_eth_dev *dev)
3926 {
3927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3928         uint32_t mode = i40e_led_get(hw);
3929
3930         if (mode != 0)
3931                 i40e_led_set(hw, 0, false);
3932
3933         return 0;
3934 }
3935
3936 static int
3937 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3938 {
3939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3941
3942         fc_conf->pause_time = pf->fc_conf.pause_time;
3943
3944         /* read out from register, in case they are modified by other port */
3945         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3946                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3947         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3948                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3949
3950         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3951         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3952
3953          /* Return current mode according to actual setting*/
3954         switch (hw->fc.current_mode) {
3955         case I40E_FC_FULL:
3956                 fc_conf->mode = RTE_FC_FULL;
3957                 break;
3958         case I40E_FC_TX_PAUSE:
3959                 fc_conf->mode = RTE_FC_TX_PAUSE;
3960                 break;
3961         case I40E_FC_RX_PAUSE:
3962                 fc_conf->mode = RTE_FC_RX_PAUSE;
3963                 break;
3964         case I40E_FC_NONE:
3965         default:
3966                 fc_conf->mode = RTE_FC_NONE;
3967         };
3968
3969         return 0;
3970 }
3971
3972 static int
3973 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3974 {
3975         uint32_t mflcn_reg, fctrl_reg, reg;
3976         uint32_t max_high_water;
3977         uint8_t i, aq_failure;
3978         int err;
3979         struct i40e_hw *hw;
3980         struct i40e_pf *pf;
3981         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3982                 [RTE_FC_NONE] = I40E_FC_NONE,
3983                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3984                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3985                 [RTE_FC_FULL] = I40E_FC_FULL
3986         };
3987
3988         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3989
3990         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3991         if ((fc_conf->high_water > max_high_water) ||
3992                         (fc_conf->high_water < fc_conf->low_water)) {
3993                 PMD_INIT_LOG(ERR,
3994                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3995                         max_high_water);
3996                 return -EINVAL;
3997         }
3998
3999         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4001         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4002
4003         pf->fc_conf.pause_time = fc_conf->pause_time;
4004         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4005         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4006
4007         PMD_INIT_FUNC_TRACE();
4008
4009         /* All the link flow control related enable/disable register
4010          * configuration is handle by the F/W
4011          */
4012         err = i40e_set_fc(hw, &aq_failure, true);
4013         if (err < 0)
4014                 return -ENOSYS;
4015
4016         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4017                 /* Configure flow control refresh threshold,
4018                  * the value for stat_tx_pause_refresh_timer[8]
4019                  * is used for global pause operation.
4020                  */
4021
4022                 I40E_WRITE_REG(hw,
4023                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4024                                pf->fc_conf.pause_time);
4025
4026                 /* configure the timer value included in transmitted pause
4027                  * frame,
4028                  * the value for stat_tx_pause_quanta[8] is used for global
4029                  * pause operation
4030                  */
4031                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4032                                pf->fc_conf.pause_time);
4033
4034                 fctrl_reg = I40E_READ_REG(hw,
4035                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4036
4037                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4038                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4039                 else
4040                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4041
4042                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4043                                fctrl_reg);
4044         } else {
4045                 /* Configure pause time (2 TCs per register) */
4046                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4047                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4048                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4049
4050                 /* Configure flow control refresh threshold value */
4051                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4052                                pf->fc_conf.pause_time / 2);
4053
4054                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4055
4056                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4057                  *depending on configuration
4058                  */
4059                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4060                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4061                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4062                 } else {
4063                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4064                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4065                 }
4066
4067                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4068         }
4069
4070         if (!pf->support_multi_driver) {
4071                 /* config water marker both based on the packets and bytes */
4072                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4073                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4074                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4075                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4076                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4077                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4078                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4079                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4080                                   << I40E_KILOSHIFT);
4081                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4082                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4083                                    << I40E_KILOSHIFT);
4084         } else {
4085                 PMD_DRV_LOG(ERR,
4086                             "Water marker configuration is not supported.");
4087         }
4088
4089         I40E_WRITE_FLUSH(hw);
4090
4091         return 0;
4092 }
4093
4094 static int
4095 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4096                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4097 {
4098         PMD_INIT_FUNC_TRACE();
4099
4100         return -ENOSYS;
4101 }
4102
4103 /* Add a MAC address, and update filters */
4104 static int
4105 i40e_macaddr_add(struct rte_eth_dev *dev,
4106                  struct rte_ether_addr *mac_addr,
4107                  __rte_unused uint32_t index,
4108                  uint32_t pool)
4109 {
4110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4111         struct i40e_mac_filter_info mac_filter;
4112         struct i40e_vsi *vsi;
4113         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4114         int ret;
4115
4116         /* If VMDQ not enabled or configured, return */
4117         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4118                           !pf->nb_cfg_vmdq_vsi)) {
4119                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4120                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4121                         pool);
4122                 return -ENOTSUP;
4123         }
4124
4125         if (pool > pf->nb_cfg_vmdq_vsi) {
4126                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4127                                 pool, pf->nb_cfg_vmdq_vsi);
4128                 return -EINVAL;
4129         }
4130
4131         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4132         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4133                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4134         else
4135                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4136
4137         if (pool == 0)
4138                 vsi = pf->main_vsi;
4139         else
4140                 vsi = pf->vmdq[pool - 1].vsi;
4141
4142         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4143         if (ret != I40E_SUCCESS) {
4144                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4145                 return -ENODEV;
4146         }
4147         return 0;
4148 }
4149
4150 /* Remove a MAC address, and update filters */
4151 static void
4152 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4153 {
4154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4155         struct i40e_vsi *vsi;
4156         struct rte_eth_dev_data *data = dev->data;
4157         struct rte_ether_addr *macaddr;
4158         int ret;
4159         uint32_t i;
4160         uint64_t pool_sel;
4161
4162         macaddr = &(data->mac_addrs[index]);
4163
4164         pool_sel = dev->data->mac_pool_sel[index];
4165
4166         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4167                 if (pool_sel & (1ULL << i)) {
4168                         if (i == 0)
4169                                 vsi = pf->main_vsi;
4170                         else {
4171                                 /* No VMDQ pool enabled or configured */
4172                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4173                                         (i > pf->nb_cfg_vmdq_vsi)) {
4174                                         PMD_DRV_LOG(ERR,
4175                                                 "No VMDQ pool enabled/configured");
4176                                         return;
4177                                 }
4178                                 vsi = pf->vmdq[i - 1].vsi;
4179                         }
4180                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4181
4182                         if (ret) {
4183                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4184                                 return;
4185                         }
4186                 }
4187         }
4188 }
4189
4190 /* Set perfect match or hash match of MAC and VLAN for a VF */
4191 static int
4192 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4193                  struct rte_eth_mac_filter *filter,
4194                  bool add)
4195 {
4196         struct i40e_hw *hw;
4197         struct i40e_mac_filter_info mac_filter;
4198         struct rte_ether_addr old_mac;
4199         struct rte_ether_addr *new_mac;
4200         struct i40e_pf_vf *vf = NULL;
4201         uint16_t vf_id;
4202         int ret;
4203
4204         if (pf == NULL) {
4205                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4206                 return -EINVAL;
4207         }
4208         hw = I40E_PF_TO_HW(pf);
4209
4210         if (filter == NULL) {
4211                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4212                 return -EINVAL;
4213         }
4214
4215         new_mac = &filter->mac_addr;
4216
4217         if (rte_is_zero_ether_addr(new_mac)) {
4218                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4219                 return -EINVAL;
4220         }
4221
4222         vf_id = filter->dst_id;
4223
4224         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4225                 PMD_DRV_LOG(ERR, "Invalid argument.");
4226                 return -EINVAL;
4227         }
4228         vf = &pf->vfs[vf_id];
4229
4230         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4231                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4232                 return -EINVAL;
4233         }
4234
4235         if (add) {
4236                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4237                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4238                                 RTE_ETHER_ADDR_LEN);
4239                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4240                                  RTE_ETHER_ADDR_LEN);
4241
4242                 mac_filter.filter_type = filter->filter_type;
4243                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4244                 if (ret != I40E_SUCCESS) {
4245                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4246                         return -1;
4247                 }
4248                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4249         } else {
4250                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4251                                 RTE_ETHER_ADDR_LEN);
4252                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4253                 if (ret != I40E_SUCCESS) {
4254                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4255                         return -1;
4256                 }
4257
4258                 /* Clear device address as it has been removed */
4259                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4260                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4261         }
4262
4263         return 0;
4264 }
4265
4266 /* MAC filter handle */
4267 static int
4268 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4269                 void *arg)
4270 {
4271         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4272         struct rte_eth_mac_filter *filter;
4273         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4274         int ret = I40E_NOT_SUPPORTED;
4275
4276         filter = (struct rte_eth_mac_filter *)(arg);
4277
4278         switch (filter_op) {
4279         case RTE_ETH_FILTER_NOP:
4280                 ret = I40E_SUCCESS;
4281                 break;
4282         case RTE_ETH_FILTER_ADD:
4283                 i40e_pf_disable_irq0(hw);
4284                 if (filter->is_vf)
4285                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4286                 i40e_pf_enable_irq0(hw);
4287                 break;
4288         case RTE_ETH_FILTER_DELETE:
4289                 i40e_pf_disable_irq0(hw);
4290                 if (filter->is_vf)
4291                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4292                 i40e_pf_enable_irq0(hw);
4293                 break;
4294         default:
4295                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4296                 ret = I40E_ERR_PARAM;
4297                 break;
4298         }
4299
4300         return ret;
4301 }
4302
4303 static int
4304 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4305 {
4306         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4307         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4308         uint32_t reg;
4309         int ret;
4310
4311         if (!lut)
4312                 return -EINVAL;
4313
4314         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4315                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4316                                           vsi->type != I40E_VSI_SRIOV,
4317                                           lut, lut_size);
4318                 if (ret) {
4319                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4320                         return ret;
4321                 }
4322         } else {
4323                 uint32_t *lut_dw = (uint32_t *)lut;
4324                 uint16_t i, lut_size_dw = lut_size / 4;
4325
4326                 if (vsi->type == I40E_VSI_SRIOV) {
4327                         for (i = 0; i <= lut_size_dw; i++) {
4328                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4329                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4330                         }
4331                 } else {
4332                         for (i = 0; i < lut_size_dw; i++)
4333                                 lut_dw[i] = I40E_READ_REG(hw,
4334                                                           I40E_PFQF_HLUT(i));
4335                 }
4336         }
4337
4338         return 0;
4339 }
4340
4341 int
4342 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4343 {
4344         struct i40e_pf *pf;
4345         struct i40e_hw *hw;
4346         int ret;
4347
4348         if (!vsi || !lut)
4349                 return -EINVAL;
4350
4351         pf = I40E_VSI_TO_PF(vsi);
4352         hw = I40E_VSI_TO_HW(vsi);
4353
4354         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4355                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4356                                           vsi->type != I40E_VSI_SRIOV,
4357                                           lut, lut_size);
4358                 if (ret) {
4359                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4360                         return ret;
4361                 }
4362         } else {
4363                 uint32_t *lut_dw = (uint32_t *)lut;
4364                 uint16_t i, lut_size_dw = lut_size / 4;
4365
4366                 if (vsi->type == I40E_VSI_SRIOV) {
4367                         for (i = 0; i < lut_size_dw; i++)
4368                                 I40E_WRITE_REG(
4369                                         hw,
4370                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4371                                         lut_dw[i]);
4372                 } else {
4373                         for (i = 0; i < lut_size_dw; i++)
4374                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4375                                                lut_dw[i]);
4376                 }
4377                 I40E_WRITE_FLUSH(hw);
4378         }
4379
4380         return 0;
4381 }
4382
4383 static int
4384 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4385                          struct rte_eth_rss_reta_entry64 *reta_conf,
4386                          uint16_t reta_size)
4387 {
4388         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4389         uint16_t i, lut_size = pf->hash_lut_size;
4390         uint16_t idx, shift;
4391         uint8_t *lut;
4392         int ret;
4393
4394         if (reta_size != lut_size ||
4395                 reta_size > ETH_RSS_RETA_SIZE_512) {
4396                 PMD_DRV_LOG(ERR,
4397                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4398                         reta_size, lut_size);
4399                 return -EINVAL;
4400         }
4401
4402         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4403         if (!lut) {
4404                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4405                 return -ENOMEM;
4406         }
4407         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4408         if (ret)
4409                 goto out;
4410         for (i = 0; i < reta_size; i++) {
4411                 idx = i / RTE_RETA_GROUP_SIZE;
4412                 shift = i % RTE_RETA_GROUP_SIZE;
4413                 if (reta_conf[idx].mask & (1ULL << shift))
4414                         lut[i] = reta_conf[idx].reta[shift];
4415         }
4416         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4417
4418         pf->adapter->rss_reta_updated = 1;
4419
4420 out:
4421         rte_free(lut);
4422
4423         return ret;
4424 }
4425
4426 static int
4427 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4428                         struct rte_eth_rss_reta_entry64 *reta_conf,
4429                         uint16_t reta_size)
4430 {
4431         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4432         uint16_t i, lut_size = pf->hash_lut_size;
4433         uint16_t idx, shift;
4434         uint8_t *lut;
4435         int ret;
4436
4437         if (reta_size != lut_size ||
4438                 reta_size > ETH_RSS_RETA_SIZE_512) {
4439                 PMD_DRV_LOG(ERR,
4440                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4441                         reta_size, lut_size);
4442                 return -EINVAL;
4443         }
4444
4445         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4446         if (!lut) {
4447                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4448                 return -ENOMEM;
4449         }
4450
4451         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4452         if (ret)
4453                 goto out;
4454         for (i = 0; i < reta_size; i++) {
4455                 idx = i / RTE_RETA_GROUP_SIZE;
4456                 shift = i % RTE_RETA_GROUP_SIZE;
4457                 if (reta_conf[idx].mask & (1ULL << shift))
4458                         reta_conf[idx].reta[shift] = lut[i];
4459         }
4460
4461 out:
4462         rte_free(lut);
4463
4464         return ret;
4465 }
4466
4467 /**
4468  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4469  * @hw:   pointer to the HW structure
4470  * @mem:  pointer to mem struct to fill out
4471  * @size: size of memory requested
4472  * @alignment: what to align the allocation to
4473  **/
4474 enum i40e_status_code
4475 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4476                         struct i40e_dma_mem *mem,
4477                         u64 size,
4478                         u32 alignment)
4479 {
4480         const struct rte_memzone *mz = NULL;
4481         char z_name[RTE_MEMZONE_NAMESIZE];
4482
4483         if (!mem)
4484                 return I40E_ERR_PARAM;
4485
4486         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4487         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4488                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4489         if (!mz)
4490                 return I40E_ERR_NO_MEMORY;
4491
4492         mem->size = size;
4493         mem->va = mz->addr;
4494         mem->pa = mz->iova;
4495         mem->zone = (const void *)mz;
4496         PMD_DRV_LOG(DEBUG,
4497                 "memzone %s allocated with physical address: %"PRIu64,
4498                 mz->name, mem->pa);
4499
4500         return I40E_SUCCESS;
4501 }
4502
4503 /**
4504  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4505  * @hw:   pointer to the HW structure
4506  * @mem:  ptr to mem struct to free
4507  **/
4508 enum i40e_status_code
4509 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4510                     struct i40e_dma_mem *mem)
4511 {
4512         if (!mem)
4513                 return I40E_ERR_PARAM;
4514
4515         PMD_DRV_LOG(DEBUG,
4516                 "memzone %s to be freed with physical address: %"PRIu64,
4517                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4518         rte_memzone_free((const struct rte_memzone *)mem->zone);
4519         mem->zone = NULL;
4520         mem->va = NULL;
4521         mem->pa = (u64)0;
4522
4523         return I40E_SUCCESS;
4524 }
4525
4526 /**
4527  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4528  * @hw:   pointer to the HW structure
4529  * @mem:  pointer to mem struct to fill out
4530  * @size: size of memory requested
4531  **/
4532 enum i40e_status_code
4533 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4534                          struct i40e_virt_mem *mem,
4535                          u32 size)
4536 {
4537         if (!mem)
4538                 return I40E_ERR_PARAM;
4539
4540         mem->size = size;
4541         mem->va = rte_zmalloc("i40e", size, 0);
4542
4543         if (mem->va)
4544                 return I40E_SUCCESS;
4545         else
4546                 return I40E_ERR_NO_MEMORY;
4547 }
4548
4549 /**
4550  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4551  * @hw:   pointer to the HW structure
4552  * @mem:  pointer to mem struct to free
4553  **/
4554 enum i40e_status_code
4555 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4556                      struct i40e_virt_mem *mem)
4557 {
4558         if (!mem)
4559                 return I40E_ERR_PARAM;
4560
4561         rte_free(mem->va);
4562         mem->va = NULL;
4563
4564         return I40E_SUCCESS;
4565 }
4566
4567 void
4568 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4569 {
4570         rte_spinlock_init(&sp->spinlock);
4571 }
4572
4573 void
4574 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4575 {
4576         rte_spinlock_lock(&sp->spinlock);
4577 }
4578
4579 void
4580 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4581 {
4582         rte_spinlock_unlock(&sp->spinlock);
4583 }
4584
4585 void
4586 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4587 {
4588         return;
4589 }
4590
4591 /**
4592  * Get the hardware capabilities, which will be parsed
4593  * and saved into struct i40e_hw.
4594  */
4595 static int
4596 i40e_get_cap(struct i40e_hw *hw)
4597 {
4598         struct i40e_aqc_list_capabilities_element_resp *buf;
4599         uint16_t len, size = 0;
4600         int ret;
4601
4602         /* Calculate a huge enough buff for saving response data temporarily */
4603         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4604                                                 I40E_MAX_CAP_ELE_NUM;
4605         buf = rte_zmalloc("i40e", len, 0);
4606         if (!buf) {
4607                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4608                 return I40E_ERR_NO_MEMORY;
4609         }
4610
4611         /* Get, parse the capabilities and save it to hw */
4612         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4613                         i40e_aqc_opc_list_func_capabilities, NULL);
4614         if (ret != I40E_SUCCESS)
4615                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4616
4617         /* Free the temporary buffer after being used */
4618         rte_free(buf);
4619
4620         return ret;
4621 }
4622
4623 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4624
4625 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4626                 const char *value,
4627                 void *opaque)
4628 {
4629         struct i40e_pf *pf;
4630         unsigned long num;
4631         char *end;
4632
4633         pf = (struct i40e_pf *)opaque;
4634         RTE_SET_USED(key);
4635
4636         errno = 0;
4637         num = strtoul(value, &end, 0);
4638         if (errno != 0 || end == value || *end != 0) {
4639                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4640                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4641                 return -(EINVAL);
4642         }
4643
4644         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4645                 pf->vf_nb_qp_max = (uint16_t)num;
4646         else
4647                 /* here return 0 to make next valid same argument work */
4648                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4649                             "power of 2 and equal or less than 16 !, Now it is "
4650                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4651
4652         return 0;
4653 }
4654
4655 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4656 {
4657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4658         struct rte_kvargs *kvlist;
4659         int kvargs_count;
4660
4661         /* set default queue number per VF as 4 */
4662         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4663
4664         if (dev->device->devargs == NULL)
4665                 return 0;
4666
4667         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4668         if (kvlist == NULL)
4669                 return -(EINVAL);
4670
4671         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4672         if (!kvargs_count) {
4673                 rte_kvargs_free(kvlist);
4674                 return 0;
4675         }
4676
4677         if (kvargs_count > 1)
4678                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4679                             "the first invalid or last valid one is used !",
4680                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4681
4682         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4683                            i40e_pf_parse_vf_queue_number_handler, pf);
4684
4685         rte_kvargs_free(kvlist);
4686
4687         return 0;
4688 }
4689
4690 static int
4691 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4692 {
4693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4695         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4696         uint16_t qp_count = 0, vsi_count = 0;
4697
4698         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4699                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4700                 return -EINVAL;
4701         }
4702
4703         i40e_pf_config_vf_rxq_number(dev);
4704
4705         /* Add the parameter init for LFC */
4706         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4707         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4708         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4709
4710         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4711         pf->max_num_vsi = hw->func_caps.num_vsis;
4712         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4713         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4714
4715         /* FDir queue/VSI allocation */
4716         pf->fdir_qp_offset = 0;
4717         if (hw->func_caps.fd) {
4718                 pf->flags |= I40E_FLAG_FDIR;
4719                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4720         } else {
4721                 pf->fdir_nb_qps = 0;
4722         }
4723         qp_count += pf->fdir_nb_qps;
4724         vsi_count += 1;
4725
4726         /* LAN queue/VSI allocation */
4727         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4728         if (!hw->func_caps.rss) {
4729                 pf->lan_nb_qps = 1;
4730         } else {
4731                 pf->flags |= I40E_FLAG_RSS;
4732                 if (hw->mac.type == I40E_MAC_X722)
4733                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4734                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4735         }
4736         qp_count += pf->lan_nb_qps;
4737         vsi_count += 1;
4738
4739         /* VF queue/VSI allocation */
4740         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4741         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4742                 pf->flags |= I40E_FLAG_SRIOV;
4743                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4744                 pf->vf_num = pci_dev->max_vfs;
4745                 PMD_DRV_LOG(DEBUG,
4746                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4747                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4748         } else {
4749                 pf->vf_nb_qps = 0;
4750                 pf->vf_num = 0;
4751         }
4752         qp_count += pf->vf_nb_qps * pf->vf_num;
4753         vsi_count += pf->vf_num;
4754
4755         /* VMDq queue/VSI allocation */
4756         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4757         pf->vmdq_nb_qps = 0;
4758         pf->max_nb_vmdq_vsi = 0;
4759         if (hw->func_caps.vmdq) {
4760                 if (qp_count < hw->func_caps.num_tx_qp &&
4761                         vsi_count < hw->func_caps.num_vsis) {
4762                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4763                                 qp_count) / pf->vmdq_nb_qp_max;
4764
4765                         /* Limit the maximum number of VMDq vsi to the maximum
4766                          * ethdev can support
4767                          */
4768                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4769                                 hw->func_caps.num_vsis - vsi_count);
4770                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4771                                 ETH_64_POOLS);
4772                         if (pf->max_nb_vmdq_vsi) {
4773                                 pf->flags |= I40E_FLAG_VMDQ;
4774                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4775                                 PMD_DRV_LOG(DEBUG,
4776                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4777                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4778                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4779                         } else {
4780                                 PMD_DRV_LOG(INFO,
4781                                         "No enough queues left for VMDq");
4782                         }
4783                 } else {
4784                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4785                 }
4786         }
4787         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4788         vsi_count += pf->max_nb_vmdq_vsi;
4789
4790         if (hw->func_caps.dcb)
4791                 pf->flags |= I40E_FLAG_DCB;
4792
4793         if (qp_count > hw->func_caps.num_tx_qp) {
4794                 PMD_DRV_LOG(ERR,
4795                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4796                         qp_count, hw->func_caps.num_tx_qp);
4797                 return -EINVAL;
4798         }
4799         if (vsi_count > hw->func_caps.num_vsis) {
4800                 PMD_DRV_LOG(ERR,
4801                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4802                         vsi_count, hw->func_caps.num_vsis);
4803                 return -EINVAL;
4804         }
4805
4806         return 0;
4807 }
4808
4809 static int
4810 i40e_pf_get_switch_config(struct i40e_pf *pf)
4811 {
4812         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813         struct i40e_aqc_get_switch_config_resp *switch_config;
4814         struct i40e_aqc_switch_config_element_resp *element;
4815         uint16_t start_seid = 0, num_reported;
4816         int ret;
4817
4818         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4819                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4820         if (!switch_config) {
4821                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4822                 return -ENOMEM;
4823         }
4824
4825         /* Get the switch configurations */
4826         ret = i40e_aq_get_switch_config(hw, switch_config,
4827                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4828         if (ret != I40E_SUCCESS) {
4829                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4830                 goto fail;
4831         }
4832         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4833         if (num_reported != 1) { /* The number should be 1 */
4834                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4835                 goto fail;
4836         }
4837
4838         /* Parse the switch configuration elements */
4839         element = &(switch_config->element[0]);
4840         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4841                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4842                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4843         } else
4844                 PMD_DRV_LOG(INFO, "Unknown element type");
4845
4846 fail:
4847         rte_free(switch_config);
4848
4849         return ret;
4850 }
4851
4852 static int
4853 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4854                         uint32_t num)
4855 {
4856         struct pool_entry *entry;
4857
4858         if (pool == NULL || num == 0)
4859                 return -EINVAL;
4860
4861         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4862         if (entry == NULL) {
4863                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4864                 return -ENOMEM;
4865         }
4866
4867         /* queue heap initialize */
4868         pool->num_free = num;
4869         pool->num_alloc = 0;
4870         pool->base = base;
4871         LIST_INIT(&pool->alloc_list);
4872         LIST_INIT(&pool->free_list);
4873
4874         /* Initialize element  */
4875         entry->base = 0;
4876         entry->len = num;
4877
4878         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4879         return 0;
4880 }
4881
4882 static void
4883 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4884 {
4885         struct pool_entry *entry, *next_entry;
4886
4887         if (pool == NULL)
4888                 return;
4889
4890         for (entry = LIST_FIRST(&pool->alloc_list);
4891                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4892                         entry = next_entry) {
4893                 LIST_REMOVE(entry, next);
4894                 rte_free(entry);
4895         }
4896
4897         for (entry = LIST_FIRST(&pool->free_list);
4898                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4899                         entry = next_entry) {
4900                 LIST_REMOVE(entry, next);
4901                 rte_free(entry);
4902         }
4903
4904         pool->num_free = 0;
4905         pool->num_alloc = 0;
4906         pool->base = 0;
4907         LIST_INIT(&pool->alloc_list);
4908         LIST_INIT(&pool->free_list);
4909 }
4910
4911 static int
4912 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4913                        uint32_t base)
4914 {
4915         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4916         uint32_t pool_offset;
4917         int insert;
4918
4919         if (pool == NULL) {
4920                 PMD_DRV_LOG(ERR, "Invalid parameter");
4921                 return -EINVAL;
4922         }
4923
4924         pool_offset = base - pool->base;
4925         /* Lookup in alloc list */
4926         LIST_FOREACH(entry, &pool->alloc_list, next) {
4927                 if (entry->base == pool_offset) {
4928                         valid_entry = entry;
4929                         LIST_REMOVE(entry, next);
4930                         break;
4931                 }
4932         }
4933
4934         /* Not find, return */
4935         if (valid_entry == NULL) {
4936                 PMD_DRV_LOG(ERR, "Failed to find entry");
4937                 return -EINVAL;
4938         }
4939
4940         /**
4941          * Found it, move it to free list  and try to merge.
4942          * In order to make merge easier, always sort it by qbase.
4943          * Find adjacent prev and last entries.
4944          */
4945         prev = next = NULL;
4946         LIST_FOREACH(entry, &pool->free_list, next) {
4947                 if (entry->base > valid_entry->base) {
4948                         next = entry;
4949                         break;
4950                 }
4951                 prev = entry;
4952         }
4953
4954         insert = 0;
4955         /* Try to merge with next one*/
4956         if (next != NULL) {
4957                 /* Merge with next one */
4958                 if (valid_entry->base + valid_entry->len == next->base) {
4959                         next->base = valid_entry->base;
4960                         next->len += valid_entry->len;
4961                         rte_free(valid_entry);
4962                         valid_entry = next;
4963                         insert = 1;
4964                 }
4965         }
4966
4967         if (prev != NULL) {
4968                 /* Merge with previous one */
4969                 if (prev->base + prev->len == valid_entry->base) {
4970                         prev->len += valid_entry->len;
4971                         /* If it merge with next one, remove next node */
4972                         if (insert == 1) {
4973                                 LIST_REMOVE(valid_entry, next);
4974                                 rte_free(valid_entry);
4975                         } else {
4976                                 rte_free(valid_entry);
4977                                 insert = 1;
4978                         }
4979                 }
4980         }
4981
4982         /* Not find any entry to merge, insert */
4983         if (insert == 0) {
4984                 if (prev != NULL)
4985                         LIST_INSERT_AFTER(prev, valid_entry, next);
4986                 else if (next != NULL)
4987                         LIST_INSERT_BEFORE(next, valid_entry, next);
4988                 else /* It's empty list, insert to head */
4989                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4990         }
4991
4992         pool->num_free += valid_entry->len;
4993         pool->num_alloc -= valid_entry->len;
4994
4995         return 0;
4996 }
4997
4998 static int
4999 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5000                        uint16_t num)
5001 {
5002         struct pool_entry *entry, *valid_entry;
5003
5004         if (pool == NULL || num == 0) {
5005                 PMD_DRV_LOG(ERR, "Invalid parameter");
5006                 return -EINVAL;
5007         }
5008
5009         if (pool->num_free < num) {
5010                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5011                             num, pool->num_free);
5012                 return -ENOMEM;
5013         }
5014
5015         valid_entry = NULL;
5016         /* Lookup  in free list and find most fit one */
5017         LIST_FOREACH(entry, &pool->free_list, next) {
5018                 if (entry->len >= num) {
5019                         /* Find best one */
5020                         if (entry->len == num) {
5021                                 valid_entry = entry;
5022                                 break;
5023                         }
5024                         if (valid_entry == NULL || valid_entry->len > entry->len)
5025                                 valid_entry = entry;
5026                 }
5027         }
5028
5029         /* Not find one to satisfy the request, return */
5030         if (valid_entry == NULL) {
5031                 PMD_DRV_LOG(ERR, "No valid entry found");
5032                 return -ENOMEM;
5033         }
5034         /**
5035          * The entry have equal queue number as requested,
5036          * remove it from alloc_list.
5037          */
5038         if (valid_entry->len == num) {
5039                 LIST_REMOVE(valid_entry, next);
5040         } else {
5041                 /**
5042                  * The entry have more numbers than requested,
5043                  * create a new entry for alloc_list and minus its
5044                  * queue base and number in free_list.
5045                  */
5046                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5047                 if (entry == NULL) {
5048                         PMD_DRV_LOG(ERR,
5049                                 "Failed to allocate memory for resource pool");
5050                         return -ENOMEM;
5051                 }
5052                 entry->base = valid_entry->base;
5053                 entry->len = num;
5054                 valid_entry->base += num;
5055                 valid_entry->len -= num;
5056                 valid_entry = entry;
5057         }
5058
5059         /* Insert it into alloc list, not sorted */
5060         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5061
5062         pool->num_free -= valid_entry->len;
5063         pool->num_alloc += valid_entry->len;
5064
5065         return valid_entry->base + pool->base;
5066 }
5067
5068 /**
5069  * bitmap_is_subset - Check whether src2 is subset of src1
5070  **/
5071 static inline int
5072 bitmap_is_subset(uint8_t src1, uint8_t src2)
5073 {
5074         return !((src1 ^ src2) & src2);
5075 }
5076
5077 static enum i40e_status_code
5078 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5079 {
5080         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5081
5082         /* If DCB is not supported, only default TC is supported */
5083         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5084                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5085                 return I40E_NOT_SUPPORTED;
5086         }
5087
5088         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5089                 PMD_DRV_LOG(ERR,
5090                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5091                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5092                 return I40E_NOT_SUPPORTED;
5093         }
5094         return I40E_SUCCESS;
5095 }
5096
5097 int
5098 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5099                                 struct i40e_vsi_vlan_pvid_info *info)
5100 {
5101         struct i40e_hw *hw;
5102         struct i40e_vsi_context ctxt;
5103         uint8_t vlan_flags = 0;
5104         int ret;
5105
5106         if (vsi == NULL || info == NULL) {
5107                 PMD_DRV_LOG(ERR, "invalid parameters");
5108                 return I40E_ERR_PARAM;
5109         }
5110
5111         if (info->on) {
5112                 vsi->info.pvid = info->config.pvid;
5113                 /**
5114                  * If insert pvid is enabled, only tagged pkts are
5115                  * allowed to be sent out.
5116                  */
5117                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5118                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5119         } else {
5120                 vsi->info.pvid = 0;
5121                 if (info->config.reject.tagged == 0)
5122                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5123
5124                 if (info->config.reject.untagged == 0)
5125                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5126         }
5127         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5128                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5129         vsi->info.port_vlan_flags |= vlan_flags;
5130         vsi->info.valid_sections =
5131                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5132         memset(&ctxt, 0, sizeof(ctxt));
5133         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5134         ctxt.seid = vsi->seid;
5135
5136         hw = I40E_VSI_TO_HW(vsi);
5137         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5138         if (ret != I40E_SUCCESS)
5139                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5140
5141         return ret;
5142 }
5143
5144 static int
5145 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5146 {
5147         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5148         int i, ret;
5149         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5150
5151         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5152         if (ret != I40E_SUCCESS)
5153                 return ret;
5154
5155         if (!vsi->seid) {
5156                 PMD_DRV_LOG(ERR, "seid not valid");
5157                 return -EINVAL;
5158         }
5159
5160         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5161         tc_bw_data.tc_valid_bits = enabled_tcmap;
5162         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5163                 tc_bw_data.tc_bw_credits[i] =
5164                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5165
5166         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5167         if (ret != I40E_SUCCESS) {
5168                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5169                 return ret;
5170         }
5171
5172         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5173                                         sizeof(vsi->info.qs_handle));
5174         return I40E_SUCCESS;
5175 }
5176
5177 static enum i40e_status_code
5178 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5179                                  struct i40e_aqc_vsi_properties_data *info,
5180                                  uint8_t enabled_tcmap)
5181 {
5182         enum i40e_status_code ret;
5183         int i, total_tc = 0;
5184         uint16_t qpnum_per_tc, bsf, qp_idx;
5185
5186         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5187         if (ret != I40E_SUCCESS)
5188                 return ret;
5189
5190         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5191                 if (enabled_tcmap & (1 << i))
5192                         total_tc++;
5193         if (total_tc == 0)
5194                 total_tc = 1;
5195         vsi->enabled_tc = enabled_tcmap;
5196
5197         /* Number of queues per enabled TC */
5198         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5199         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5200         bsf = rte_bsf32(qpnum_per_tc);
5201
5202         /* Adjust the queue number to actual queues that can be applied */
5203         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5204                 vsi->nb_qps = qpnum_per_tc * total_tc;
5205
5206         /**
5207          * Configure TC and queue mapping parameters, for enabled TC,
5208          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5209          * default queue will serve it.
5210          */
5211         qp_idx = 0;
5212         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5213                 if (vsi->enabled_tc & (1 << i)) {
5214                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5215                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5216                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5217                         qp_idx += qpnum_per_tc;
5218                 } else
5219                         info->tc_mapping[i] = 0;
5220         }
5221
5222         /* Associate queue number with VSI */
5223         if (vsi->type == I40E_VSI_SRIOV) {
5224                 info->mapping_flags |=
5225                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5226                 for (i = 0; i < vsi->nb_qps; i++)
5227                         info->queue_mapping[i] =
5228                                 rte_cpu_to_le_16(vsi->base_queue + i);
5229         } else {
5230                 info->mapping_flags |=
5231                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5232                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5233         }
5234         info->valid_sections |=
5235                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5236
5237         return I40E_SUCCESS;
5238 }
5239
5240 static int
5241 i40e_veb_release(struct i40e_veb *veb)
5242 {
5243         struct i40e_vsi *vsi;
5244         struct i40e_hw *hw;
5245
5246         if (veb == NULL)
5247                 return -EINVAL;
5248
5249         if (!TAILQ_EMPTY(&veb->head)) {
5250                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5251                 return -EACCES;
5252         }
5253         /* associate_vsi field is NULL for floating VEB */
5254         if (veb->associate_vsi != NULL) {
5255                 vsi = veb->associate_vsi;
5256                 hw = I40E_VSI_TO_HW(vsi);
5257
5258                 vsi->uplink_seid = veb->uplink_seid;
5259                 vsi->veb = NULL;
5260         } else {
5261                 veb->associate_pf->main_vsi->floating_veb = NULL;
5262                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5263         }
5264
5265         i40e_aq_delete_element(hw, veb->seid, NULL);
5266         rte_free(veb);
5267         return I40E_SUCCESS;
5268 }
5269
5270 /* Setup a veb */
5271 static struct i40e_veb *
5272 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5273 {
5274         struct i40e_veb *veb;
5275         int ret;
5276         struct i40e_hw *hw;
5277
5278         if (pf == NULL) {
5279                 PMD_DRV_LOG(ERR,
5280                             "veb setup failed, associated PF shouldn't null");
5281                 return NULL;
5282         }
5283         hw = I40E_PF_TO_HW(pf);
5284
5285         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5286         if (!veb) {
5287                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5288                 goto fail;
5289         }
5290
5291         veb->associate_vsi = vsi;
5292         veb->associate_pf = pf;
5293         TAILQ_INIT(&veb->head);
5294         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5295
5296         /* create floating veb if vsi is NULL */
5297         if (vsi != NULL) {
5298                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5299                                       I40E_DEFAULT_TCMAP, false,
5300                                       &veb->seid, false, NULL);
5301         } else {
5302                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5303                                       true, &veb->seid, false, NULL);
5304         }
5305
5306         if (ret != I40E_SUCCESS) {
5307                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5308                             hw->aq.asq_last_status);
5309                 goto fail;
5310         }
5311         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5312
5313         /* get statistics index */
5314         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5315                                 &veb->stats_idx, NULL, NULL, NULL);
5316         if (ret != I40E_SUCCESS) {
5317                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5318                             hw->aq.asq_last_status);
5319                 goto fail;
5320         }
5321         /* Get VEB bandwidth, to be implemented */
5322         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5323         if (vsi)
5324                 vsi->uplink_seid = veb->seid;
5325
5326         return veb;
5327 fail:
5328         rte_free(veb);
5329         return NULL;
5330 }
5331
5332 int
5333 i40e_vsi_release(struct i40e_vsi *vsi)
5334 {
5335         struct i40e_pf *pf;
5336         struct i40e_hw *hw;
5337         struct i40e_vsi_list *vsi_list;
5338         void *temp;
5339         int ret;
5340         struct i40e_mac_filter *f;
5341         uint16_t user_param;
5342
5343         if (!vsi)
5344                 return I40E_SUCCESS;
5345
5346         if (!vsi->adapter)
5347                 return -EFAULT;
5348
5349         user_param = vsi->user_param;
5350
5351         pf = I40E_VSI_TO_PF(vsi);
5352         hw = I40E_VSI_TO_HW(vsi);
5353
5354         /* VSI has child to attach, release child first */
5355         if (vsi->veb) {
5356                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5357                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5358                                 return -1;
5359                 }
5360                 i40e_veb_release(vsi->veb);
5361         }
5362
5363         if (vsi->floating_veb) {
5364                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5365                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5366                                 return -1;
5367                 }
5368         }
5369
5370         /* Remove all macvlan filters of the VSI */
5371         i40e_vsi_remove_all_macvlan_filter(vsi);
5372         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5373                 rte_free(f);
5374
5375         if (vsi->type != I40E_VSI_MAIN &&
5376             ((vsi->type != I40E_VSI_SRIOV) ||
5377             !pf->floating_veb_list[user_param])) {
5378                 /* Remove vsi from parent's sibling list */
5379                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5380                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5381                         return I40E_ERR_PARAM;
5382                 }
5383                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5384                                 &vsi->sib_vsi_list, list);
5385
5386                 /* Remove all switch element of the VSI */
5387                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5388                 if (ret != I40E_SUCCESS)
5389                         PMD_DRV_LOG(ERR, "Failed to delete element");
5390         }
5391
5392         if ((vsi->type == I40E_VSI_SRIOV) &&
5393             pf->floating_veb_list[user_param]) {
5394                 /* Remove vsi from parent's sibling list */
5395                 if (vsi->parent_vsi == NULL ||
5396                     vsi->parent_vsi->floating_veb == NULL) {
5397                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5398                         return I40E_ERR_PARAM;
5399                 }
5400                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5401                              &vsi->sib_vsi_list, list);
5402
5403                 /* Remove all switch element of the VSI */
5404                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5405                 if (ret != I40E_SUCCESS)
5406                         PMD_DRV_LOG(ERR, "Failed to delete element");
5407         }
5408
5409         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5410
5411         if (vsi->type != I40E_VSI_SRIOV)
5412                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5413         rte_free(vsi);
5414
5415         return I40E_SUCCESS;
5416 }
5417
5418 static int
5419 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5420 {
5421         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5422         struct i40e_aqc_remove_macvlan_element_data def_filter;
5423         struct i40e_mac_filter_info filter;
5424         int ret;
5425
5426         if (vsi->type != I40E_VSI_MAIN)
5427                 return I40E_ERR_CONFIG;
5428         memset(&def_filter, 0, sizeof(def_filter));
5429         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5430                                         ETH_ADDR_LEN);
5431         def_filter.vlan_tag = 0;
5432         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5433                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5434         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5435         if (ret != I40E_SUCCESS) {
5436                 struct i40e_mac_filter *f;
5437                 struct rte_ether_addr *mac;
5438
5439                 PMD_DRV_LOG(DEBUG,
5440                             "Cannot remove the default macvlan filter");
5441                 /* It needs to add the permanent mac into mac list */
5442                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5443                 if (f == NULL) {
5444                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5445                         return I40E_ERR_NO_MEMORY;
5446                 }
5447                 mac = &f->mac_info.mac_addr;
5448                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5449                                 ETH_ADDR_LEN);
5450                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5451                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5452                 vsi->mac_num++;
5453
5454                 return ret;
5455         }
5456         rte_memcpy(&filter.mac_addr,
5457                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5458         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5459         return i40e_vsi_add_mac(vsi, &filter);
5460 }
5461
5462 /*
5463  * i40e_vsi_get_bw_config - Query VSI BW Information
5464  * @vsi: the VSI to be queried
5465  *
5466  * Returns 0 on success, negative value on failure
5467  */
5468 static enum i40e_status_code
5469 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5470 {
5471         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5472         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5473         struct i40e_hw *hw = &vsi->adapter->hw;
5474         i40e_status ret;
5475         int i;
5476         uint32_t bw_max;
5477
5478         memset(&bw_config, 0, sizeof(bw_config));
5479         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5480         if (ret != I40E_SUCCESS) {
5481                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5482                             hw->aq.asq_last_status);
5483                 return ret;
5484         }
5485
5486         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5487         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5488                                         &ets_sla_config, NULL);
5489         if (ret != I40E_SUCCESS) {
5490                 PMD_DRV_LOG(ERR,
5491                         "VSI failed to get TC bandwdith configuration %u",
5492                         hw->aq.asq_last_status);
5493                 return ret;
5494         }
5495
5496         /* store and print out BW info */
5497         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5498         vsi->bw_info.bw_max = bw_config.max_bw;
5499         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5500         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5501         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5502                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5503                      I40E_16_BIT_WIDTH);
5504         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5505                 vsi->bw_info.bw_ets_share_credits[i] =
5506                                 ets_sla_config.share_credits[i];
5507                 vsi->bw_info.bw_ets_credits[i] =
5508                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5509                 /* 4 bits per TC, 4th bit is reserved */
5510                 vsi->bw_info.bw_ets_max[i] =
5511                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5512                                   RTE_LEN2MASK(3, uint8_t));
5513                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5514                             vsi->bw_info.bw_ets_share_credits[i]);
5515                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5516                             vsi->bw_info.bw_ets_credits[i]);
5517                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5518                             vsi->bw_info.bw_ets_max[i]);
5519         }
5520
5521         return I40E_SUCCESS;
5522 }
5523
5524 /* i40e_enable_pf_lb
5525  * @pf: pointer to the pf structure
5526  *
5527  * allow loopback on pf
5528  */
5529 static inline void
5530 i40e_enable_pf_lb(struct i40e_pf *pf)
5531 {
5532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5533         struct i40e_vsi_context ctxt;
5534         int ret;
5535
5536         /* Use the FW API if FW >= v5.0 */
5537         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5538                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5539                 return;
5540         }
5541
5542         memset(&ctxt, 0, sizeof(ctxt));
5543         ctxt.seid = pf->main_vsi_seid;
5544         ctxt.pf_num = hw->pf_id;
5545         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5546         if (ret) {
5547                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5548                             ret, hw->aq.asq_last_status);
5549                 return;
5550         }
5551         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5552         ctxt.info.valid_sections =
5553                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5554         ctxt.info.switch_id |=
5555                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5556
5557         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5558         if (ret)
5559                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5560                             hw->aq.asq_last_status);
5561 }
5562
5563 /* Setup a VSI */
5564 struct i40e_vsi *
5565 i40e_vsi_setup(struct i40e_pf *pf,
5566                enum i40e_vsi_type type,
5567                struct i40e_vsi *uplink_vsi,
5568                uint16_t user_param)
5569 {
5570         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5571         struct i40e_vsi *vsi;
5572         struct i40e_mac_filter_info filter;
5573         int ret;
5574         struct i40e_vsi_context ctxt;
5575         struct rte_ether_addr broadcast =
5576                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5577
5578         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5579             uplink_vsi == NULL) {
5580                 PMD_DRV_LOG(ERR,
5581                         "VSI setup failed, VSI link shouldn't be NULL");
5582                 return NULL;
5583         }
5584
5585         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5586                 PMD_DRV_LOG(ERR,
5587                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5588                 return NULL;
5589         }
5590
5591         /* two situations
5592          * 1.type is not MAIN and uplink vsi is not NULL
5593          * If uplink vsi didn't setup VEB, create one first under veb field
5594          * 2.type is SRIOV and the uplink is NULL
5595          * If floating VEB is NULL, create one veb under floating veb field
5596          */
5597
5598         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5599             uplink_vsi->veb == NULL) {
5600                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5601
5602                 if (uplink_vsi->veb == NULL) {
5603                         PMD_DRV_LOG(ERR, "VEB setup failed");
5604                         return NULL;
5605                 }
5606                 /* set ALLOWLOOPBACk on pf, when veb is created */
5607                 i40e_enable_pf_lb(pf);
5608         }
5609
5610         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5611             pf->main_vsi->floating_veb == NULL) {
5612                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5613
5614                 if (pf->main_vsi->floating_veb == NULL) {
5615                         PMD_DRV_LOG(ERR, "VEB setup failed");
5616                         return NULL;
5617                 }
5618         }
5619
5620         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5621         if (!vsi) {
5622                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5623                 return NULL;
5624         }
5625         TAILQ_INIT(&vsi->mac_list);
5626         vsi->type = type;
5627         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5628         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5629         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5630         vsi->user_param = user_param;
5631         vsi->vlan_anti_spoof_on = 0;
5632         vsi->vlan_filter_on = 0;
5633         /* Allocate queues */
5634         switch (vsi->type) {
5635         case I40E_VSI_MAIN  :
5636                 vsi->nb_qps = pf->lan_nb_qps;
5637                 break;
5638         case I40E_VSI_SRIOV :
5639                 vsi->nb_qps = pf->vf_nb_qps;
5640                 break;
5641         case I40E_VSI_VMDQ2:
5642                 vsi->nb_qps = pf->vmdq_nb_qps;
5643                 break;
5644         case I40E_VSI_FDIR:
5645                 vsi->nb_qps = pf->fdir_nb_qps;
5646                 break;
5647         default:
5648                 goto fail_mem;
5649         }
5650         /*
5651          * The filter status descriptor is reported in rx queue 0,
5652          * while the tx queue for fdir filter programming has no
5653          * such constraints, can be non-zero queues.
5654          * To simplify it, choose FDIR vsi use queue 0 pair.
5655          * To make sure it will use queue 0 pair, queue allocation
5656          * need be done before this function is called
5657          */
5658         if (type != I40E_VSI_FDIR) {
5659                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5660                         if (ret < 0) {
5661                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5662                                                 vsi->seid, ret);
5663                                 goto fail_mem;
5664                         }
5665                         vsi->base_queue = ret;
5666         } else
5667                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5668
5669         /* VF has MSIX interrupt in VF range, don't allocate here */
5670         if (type == I40E_VSI_MAIN) {
5671                 if (pf->support_multi_driver) {
5672                         /* If support multi-driver, need to use INT0 instead of
5673                          * allocating from msix pool. The Msix pool is init from
5674                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5675                          * to 1 without calling i40e_res_pool_alloc.
5676                          */
5677                         vsi->msix_intr = 0;
5678                         vsi->nb_msix = 1;
5679                 } else {
5680                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5681                                                   RTE_MIN(vsi->nb_qps,
5682                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5683                         if (ret < 0) {
5684                                 PMD_DRV_LOG(ERR,
5685                                             "VSI MAIN %d get heap failed %d",
5686                                             vsi->seid, ret);
5687                                 goto fail_queue_alloc;
5688                         }
5689                         vsi->msix_intr = ret;
5690                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5691                                                RTE_MAX_RXTX_INTR_VEC_ID);
5692                 }
5693         } else if (type != I40E_VSI_SRIOV) {
5694                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5695                 if (ret < 0) {
5696                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5697                         goto fail_queue_alloc;
5698                 }
5699                 vsi->msix_intr = ret;
5700                 vsi->nb_msix = 1;
5701         } else {
5702                 vsi->msix_intr = 0;
5703                 vsi->nb_msix = 0;
5704         }
5705
5706         /* Add VSI */
5707         if (type == I40E_VSI_MAIN) {
5708                 /* For main VSI, no need to add since it's default one */
5709                 vsi->uplink_seid = pf->mac_seid;
5710                 vsi->seid = pf->main_vsi_seid;
5711                 /* Bind queues with specific MSIX interrupt */
5712                 /**
5713                  * Needs 2 interrupt at least, one for misc cause which will
5714                  * enabled from OS side, Another for queues binding the
5715                  * interrupt from device side only.
5716                  */
5717
5718                 /* Get default VSI parameters from hardware */
5719                 memset(&ctxt, 0, sizeof(ctxt));
5720                 ctxt.seid = vsi->seid;
5721                 ctxt.pf_num = hw->pf_id;
5722                 ctxt.uplink_seid = vsi->uplink_seid;
5723                 ctxt.vf_num = 0;
5724                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5725                 if (ret != I40E_SUCCESS) {
5726                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5727                         goto fail_msix_alloc;
5728                 }
5729                 rte_memcpy(&vsi->info, &ctxt.info,
5730                         sizeof(struct i40e_aqc_vsi_properties_data));
5731                 vsi->vsi_id = ctxt.vsi_number;
5732                 vsi->info.valid_sections = 0;
5733
5734                 /* Configure tc, enabled TC0 only */
5735                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5736                         I40E_SUCCESS) {
5737                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5738                         goto fail_msix_alloc;
5739                 }
5740
5741                 /* TC, queue mapping */
5742                 memset(&ctxt, 0, sizeof(ctxt));
5743                 vsi->info.valid_sections |=
5744                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5745                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5746                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5747                 rte_memcpy(&ctxt.info, &vsi->info,
5748                         sizeof(struct i40e_aqc_vsi_properties_data));
5749                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5750                                                 I40E_DEFAULT_TCMAP);
5751                 if (ret != I40E_SUCCESS) {
5752                         PMD_DRV_LOG(ERR,
5753                                 "Failed to configure TC queue mapping");
5754                         goto fail_msix_alloc;
5755                 }
5756                 ctxt.seid = vsi->seid;
5757                 ctxt.pf_num = hw->pf_id;
5758                 ctxt.uplink_seid = vsi->uplink_seid;
5759                 ctxt.vf_num = 0;
5760
5761                 /* Update VSI parameters */
5762                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5763                 if (ret != I40E_SUCCESS) {
5764                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5765                         goto fail_msix_alloc;
5766                 }
5767
5768                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5769                                                 sizeof(vsi->info.tc_mapping));
5770                 rte_memcpy(&vsi->info.queue_mapping,
5771                                 &ctxt.info.queue_mapping,
5772                         sizeof(vsi->info.queue_mapping));
5773                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5774                 vsi->info.valid_sections = 0;
5775
5776                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5777                                 ETH_ADDR_LEN);
5778
5779                 /**
5780                  * Updating default filter settings are necessary to prevent
5781                  * reception of tagged packets.
5782                  * Some old firmware configurations load a default macvlan
5783                  * filter which accepts both tagged and untagged packets.
5784                  * The updating is to use a normal filter instead if needed.
5785                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5786                  * The firmware with correct configurations load the default
5787                  * macvlan filter which is expected and cannot be removed.
5788                  */
5789                 i40e_update_default_filter_setting(vsi);
5790                 i40e_config_qinq(hw, vsi);
5791         } else if (type == I40E_VSI_SRIOV) {
5792                 memset(&ctxt, 0, sizeof(ctxt));
5793                 /**
5794                  * For other VSI, the uplink_seid equals to uplink VSI's
5795                  * uplink_seid since they share same VEB
5796                  */
5797                 if (uplink_vsi == NULL)
5798                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5799                 else
5800                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5801                 ctxt.pf_num = hw->pf_id;
5802                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5803                 ctxt.uplink_seid = vsi->uplink_seid;
5804                 ctxt.connection_type = 0x1;
5805                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5806
5807                 /* Use the VEB configuration if FW >= v5.0 */
5808                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5809                         /* Configure switch ID */
5810                         ctxt.info.valid_sections |=
5811                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5812                         ctxt.info.switch_id =
5813                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5814                 }
5815
5816                 /* Configure port/vlan */
5817                 ctxt.info.valid_sections |=
5818                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5819                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5820                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5821                                                 hw->func_caps.enabled_tcmap);
5822                 if (ret != I40E_SUCCESS) {
5823                         PMD_DRV_LOG(ERR,
5824                                 "Failed to configure TC queue mapping");
5825                         goto fail_msix_alloc;
5826                 }
5827
5828                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5829                 ctxt.info.valid_sections |=
5830                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5831                 /**
5832                  * Since VSI is not created yet, only configure parameter,
5833                  * will add vsi below.
5834                  */
5835
5836                 i40e_config_qinq(hw, vsi);
5837         } else if (type == I40E_VSI_VMDQ2) {
5838                 memset(&ctxt, 0, sizeof(ctxt));
5839                 /*
5840                  * For other VSI, the uplink_seid equals to uplink VSI's
5841                  * uplink_seid since they share same VEB
5842                  */
5843                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5844                 ctxt.pf_num = hw->pf_id;
5845                 ctxt.vf_num = 0;
5846                 ctxt.uplink_seid = vsi->uplink_seid;
5847                 ctxt.connection_type = 0x1;
5848                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5849
5850                 ctxt.info.valid_sections |=
5851                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5852                 /* user_param carries flag to enable loop back */
5853                 if (user_param) {
5854                         ctxt.info.switch_id =
5855                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5856                         ctxt.info.switch_id |=
5857                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5858                 }
5859
5860                 /* Configure port/vlan */
5861                 ctxt.info.valid_sections |=
5862                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5863                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5864                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5865                                                 I40E_DEFAULT_TCMAP);
5866                 if (ret != I40E_SUCCESS) {
5867                         PMD_DRV_LOG(ERR,
5868                                 "Failed to configure TC queue mapping");
5869                         goto fail_msix_alloc;
5870                 }
5871                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5872                 ctxt.info.valid_sections |=
5873                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5874         } else if (type == I40E_VSI_FDIR) {
5875                 memset(&ctxt, 0, sizeof(ctxt));
5876                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5877                 ctxt.pf_num = hw->pf_id;
5878                 ctxt.vf_num = 0;
5879                 ctxt.uplink_seid = vsi->uplink_seid;
5880                 ctxt.connection_type = 0x1;     /* regular data port */
5881                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5882                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5883                                                 I40E_DEFAULT_TCMAP);
5884                 if (ret != I40E_SUCCESS) {
5885                         PMD_DRV_LOG(ERR,
5886                                 "Failed to configure TC queue mapping.");
5887                         goto fail_msix_alloc;
5888                 }
5889                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5890                 ctxt.info.valid_sections |=
5891                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5892         } else {
5893                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5894                 goto fail_msix_alloc;
5895         }
5896
5897         if (vsi->type != I40E_VSI_MAIN) {
5898                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5899                 if (ret != I40E_SUCCESS) {
5900                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5901                                     hw->aq.asq_last_status);
5902                         goto fail_msix_alloc;
5903                 }
5904                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5905                 vsi->info.valid_sections = 0;
5906                 vsi->seid = ctxt.seid;
5907                 vsi->vsi_id = ctxt.vsi_number;
5908                 vsi->sib_vsi_list.vsi = vsi;
5909                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5910                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5911                                           &vsi->sib_vsi_list, list);
5912                 } else {
5913                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5914                                           &vsi->sib_vsi_list, list);
5915                 }
5916         }
5917
5918         /* MAC/VLAN configuration */
5919         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5920         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5921
5922         ret = i40e_vsi_add_mac(vsi, &filter);
5923         if (ret != I40E_SUCCESS) {
5924                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5925                 goto fail_msix_alloc;
5926         }
5927
5928         /* Get VSI BW information */
5929         i40e_vsi_get_bw_config(vsi);
5930         return vsi;
5931 fail_msix_alloc:
5932         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5933 fail_queue_alloc:
5934         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5935 fail_mem:
5936         rte_free(vsi);
5937         return NULL;
5938 }
5939
5940 /* Configure vlan filter on or off */
5941 int
5942 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5943 {
5944         int i, num;
5945         struct i40e_mac_filter *f;
5946         void *temp;
5947         struct i40e_mac_filter_info *mac_filter;
5948         enum rte_mac_filter_type desired_filter;
5949         int ret = I40E_SUCCESS;
5950
5951         if (on) {
5952                 /* Filter to match MAC and VLAN */
5953                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5954         } else {
5955                 /* Filter to match only MAC */
5956                 desired_filter = RTE_MAC_PERFECT_MATCH;
5957         }
5958
5959         num = vsi->mac_num;
5960
5961         mac_filter = rte_zmalloc("mac_filter_info_data",
5962                                  num * sizeof(*mac_filter), 0);
5963         if (mac_filter == NULL) {
5964                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5965                 return I40E_ERR_NO_MEMORY;
5966         }
5967
5968         i = 0;
5969
5970         /* Remove all existing mac */
5971         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5972                 mac_filter[i] = f->mac_info;
5973                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5974                 if (ret) {
5975                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5976                                     on ? "enable" : "disable");
5977                         goto DONE;
5978                 }
5979                 i++;
5980         }
5981
5982         /* Override with new filter */
5983         for (i = 0; i < num; i++) {
5984                 mac_filter[i].filter_type = desired_filter;
5985                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5986                 if (ret) {
5987                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5988                                     on ? "enable" : "disable");
5989                         goto DONE;
5990                 }
5991         }
5992
5993 DONE:
5994         rte_free(mac_filter);
5995         return ret;
5996 }
5997
5998 /* Configure vlan stripping on or off */
5999 int
6000 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6001 {
6002         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6003         struct i40e_vsi_context ctxt;
6004         uint8_t vlan_flags;
6005         int ret = I40E_SUCCESS;
6006
6007         /* Check if it has been already on or off */
6008         if (vsi->info.valid_sections &
6009                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6010                 if (on) {
6011                         if ((vsi->info.port_vlan_flags &
6012                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6013                                 return 0; /* already on */
6014                 } else {
6015                         if ((vsi->info.port_vlan_flags &
6016                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6017                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6018                                 return 0; /* already off */
6019                 }
6020         }
6021
6022         if (on)
6023                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6024         else
6025                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6026         vsi->info.valid_sections =
6027                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6028         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6029         vsi->info.port_vlan_flags |= vlan_flags;
6030         ctxt.seid = vsi->seid;
6031         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6032         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6033         if (ret)
6034                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6035                             on ? "enable" : "disable");
6036
6037         return ret;
6038 }
6039
6040 static int
6041 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6042 {
6043         struct rte_eth_dev_data *data = dev->data;
6044         int ret;
6045         int mask = 0;
6046
6047         /* Apply vlan offload setting */
6048         mask = ETH_VLAN_STRIP_MASK |
6049                ETH_VLAN_FILTER_MASK |
6050                ETH_VLAN_EXTEND_MASK;
6051         ret = i40e_vlan_offload_set(dev, mask);
6052         if (ret) {
6053                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6054                 return ret;
6055         }
6056
6057         /* Apply pvid setting */
6058         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6059                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6060         if (ret)
6061                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6062
6063         return ret;
6064 }
6065
6066 static int
6067 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6068 {
6069         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6070
6071         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6072 }
6073
6074 static int
6075 i40e_update_flow_control(struct i40e_hw *hw)
6076 {
6077 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6078         struct i40e_link_status link_status;
6079         uint32_t rxfc = 0, txfc = 0, reg;
6080         uint8_t an_info;
6081         int ret;
6082
6083         memset(&link_status, 0, sizeof(link_status));
6084         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6085         if (ret != I40E_SUCCESS) {
6086                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6087                 goto write_reg; /* Disable flow control */
6088         }
6089
6090         an_info = hw->phy.link_info.an_info;
6091         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6092                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6093                 ret = I40E_ERR_NOT_READY;
6094                 goto write_reg; /* Disable flow control */
6095         }
6096         /**
6097          * If link auto negotiation is enabled, flow control needs to
6098          * be configured according to it
6099          */
6100         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6101         case I40E_LINK_PAUSE_RXTX:
6102                 rxfc = 1;
6103                 txfc = 1;
6104                 hw->fc.current_mode = I40E_FC_FULL;
6105                 break;
6106         case I40E_AQ_LINK_PAUSE_RX:
6107                 rxfc = 1;
6108                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6109                 break;
6110         case I40E_AQ_LINK_PAUSE_TX:
6111                 txfc = 1;
6112                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6113                 break;
6114         default:
6115                 hw->fc.current_mode = I40E_FC_NONE;
6116                 break;
6117         }
6118
6119 write_reg:
6120         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6121                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6122         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6123         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6124         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6125         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6126
6127         return ret;
6128 }
6129
6130 /* PF setup */
6131 static int
6132 i40e_pf_setup(struct i40e_pf *pf)
6133 {
6134         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6135         struct i40e_filter_control_settings settings;
6136         struct i40e_vsi *vsi;
6137         int ret;
6138
6139         /* Clear all stats counters */
6140         pf->offset_loaded = FALSE;
6141         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6142         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6143         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6144         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6145
6146         ret = i40e_pf_get_switch_config(pf);
6147         if (ret != I40E_SUCCESS) {
6148                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6149                 return ret;
6150         }
6151
6152         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6153         if (ret)
6154                 PMD_INIT_LOG(WARNING,
6155                         "failed to allocate switch domain for device %d", ret);
6156
6157         if (pf->flags & I40E_FLAG_FDIR) {
6158                 /* make queue allocated first, let FDIR use queue pair 0*/
6159                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6160                 if (ret != I40E_FDIR_QUEUE_ID) {
6161                         PMD_DRV_LOG(ERR,
6162                                 "queue allocation fails for FDIR: ret =%d",
6163                                 ret);
6164                         pf->flags &= ~I40E_FLAG_FDIR;
6165                 }
6166         }
6167         /*  main VSI setup */
6168         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6169         if (!vsi) {
6170                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6171                 return I40E_ERR_NOT_READY;
6172         }
6173         pf->main_vsi = vsi;
6174
6175         /* Configure filter control */
6176         memset(&settings, 0, sizeof(settings));
6177         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6178                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6179         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6180                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6181         else {
6182                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6183                         hw->func_caps.rss_table_size);
6184                 return I40E_ERR_PARAM;
6185         }
6186         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6187                 hw->func_caps.rss_table_size);
6188         pf->hash_lut_size = hw->func_caps.rss_table_size;
6189
6190         /* Enable ethtype and macvlan filters */
6191         settings.enable_ethtype = TRUE;
6192         settings.enable_macvlan = TRUE;
6193         ret = i40e_set_filter_control(hw, &settings);
6194         if (ret)
6195                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6196                                                                 ret);
6197
6198         /* Update flow control according to the auto negotiation */
6199         i40e_update_flow_control(hw);
6200
6201         return I40E_SUCCESS;
6202 }
6203
6204 int
6205 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6206 {
6207         uint32_t reg;
6208         uint16_t j;
6209
6210         /**
6211          * Set or clear TX Queue Disable flags,
6212          * which is required by hardware.
6213          */
6214         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6215         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6216
6217         /* Wait until the request is finished */
6218         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6219                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6220                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6221                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6222                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6223                                                         & 0x1))) {
6224                         break;
6225                 }
6226         }
6227         if (on) {
6228                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6229                         return I40E_SUCCESS; /* already on, skip next steps */
6230
6231                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6232                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6233         } else {
6234                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6235                         return I40E_SUCCESS; /* already off, skip next steps */
6236                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6237         }
6238         /* Write the register */
6239         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6240         /* Check the result */
6241         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6242                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6243                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6244                 if (on) {
6245                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6246                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6247                                 break;
6248                 } else {
6249                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6250                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6251                                 break;
6252                 }
6253         }
6254         /* Check if it is timeout */
6255         if (j >= I40E_CHK_Q_ENA_COUNT) {
6256                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6257                             (on ? "enable" : "disable"), q_idx);
6258                 return I40E_ERR_TIMEOUT;
6259         }
6260
6261         return I40E_SUCCESS;
6262 }
6263
6264 /* Swith on or off the tx queues */
6265 static int
6266 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6267 {
6268         struct rte_eth_dev_data *dev_data = pf->dev_data;
6269         struct i40e_tx_queue *txq;
6270         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6271         uint16_t i;
6272         int ret;
6273
6274         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6275                 txq = dev_data->tx_queues[i];
6276                 /* Don't operate the queue if not configured or
6277                  * if starting only per queue */
6278                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6279                         continue;
6280                 if (on)
6281                         ret = i40e_dev_tx_queue_start(dev, i);
6282                 else
6283                         ret = i40e_dev_tx_queue_stop(dev, i);
6284                 if ( ret != I40E_SUCCESS)
6285                         return ret;
6286         }
6287
6288         return I40E_SUCCESS;
6289 }
6290
6291 int
6292 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6293 {
6294         uint32_t reg;
6295         uint16_t j;
6296
6297         /* Wait until the request is finished */
6298         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6299                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6300                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6301                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6302                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6303                         break;
6304         }
6305
6306         if (on) {
6307                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6308                         return I40E_SUCCESS; /* Already on, skip next steps */
6309                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6310         } else {
6311                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6312                         return I40E_SUCCESS; /* Already off, skip next steps */
6313                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6314         }
6315
6316         /* Write the register */
6317         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6318         /* Check the result */
6319         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6320                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6321                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6322                 if (on) {
6323                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6324                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6325                                 break;
6326                 } else {
6327                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6328                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6329                                 break;
6330                 }
6331         }
6332
6333         /* Check if it is timeout */
6334         if (j >= I40E_CHK_Q_ENA_COUNT) {
6335                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6336                             (on ? "enable" : "disable"), q_idx);
6337                 return I40E_ERR_TIMEOUT;
6338         }
6339
6340         return I40E_SUCCESS;
6341 }
6342 /* Switch on or off the rx queues */
6343 static int
6344 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6345 {
6346         struct rte_eth_dev_data *dev_data = pf->dev_data;
6347         struct i40e_rx_queue *rxq;
6348         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6349         uint16_t i;
6350         int ret;
6351
6352         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6353                 rxq = dev_data->rx_queues[i];
6354                 /* Don't operate the queue if not configured or
6355                  * if starting only per queue */
6356                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6357                         continue;
6358                 if (on)
6359                         ret = i40e_dev_rx_queue_start(dev, i);
6360                 else
6361                         ret = i40e_dev_rx_queue_stop(dev, i);
6362                 if (ret != I40E_SUCCESS)
6363                         return ret;
6364         }
6365
6366         return I40E_SUCCESS;
6367 }
6368
6369 /* Switch on or off all the rx/tx queues */
6370 int
6371 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6372 {
6373         int ret;
6374
6375         if (on) {
6376                 /* enable rx queues before enabling tx queues */
6377                 ret = i40e_dev_switch_rx_queues(pf, on);
6378                 if (ret) {
6379                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6380                         return ret;
6381                 }
6382                 ret = i40e_dev_switch_tx_queues(pf, on);
6383         } else {
6384                 /* Stop tx queues before stopping rx queues */
6385                 ret = i40e_dev_switch_tx_queues(pf, on);
6386                 if (ret) {
6387                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6388                         return ret;
6389                 }
6390                 ret = i40e_dev_switch_rx_queues(pf, on);
6391         }
6392
6393         return ret;
6394 }
6395
6396 /* Initialize VSI for TX */
6397 static int
6398 i40e_dev_tx_init(struct i40e_pf *pf)
6399 {
6400         struct rte_eth_dev_data *data = pf->dev_data;
6401         uint16_t i;
6402         uint32_t ret = I40E_SUCCESS;
6403         struct i40e_tx_queue *txq;
6404
6405         for (i = 0; i < data->nb_tx_queues; i++) {
6406                 txq = data->tx_queues[i];
6407                 if (!txq || !txq->q_set)
6408                         continue;
6409                 ret = i40e_tx_queue_init(txq);
6410                 if (ret != I40E_SUCCESS)
6411                         break;
6412         }
6413         if (ret == I40E_SUCCESS)
6414                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6415                                      ->eth_dev);
6416
6417         return ret;
6418 }
6419
6420 /* Initialize VSI for RX */
6421 static int
6422 i40e_dev_rx_init(struct i40e_pf *pf)
6423 {
6424         struct rte_eth_dev_data *data = pf->dev_data;
6425         int ret = I40E_SUCCESS;
6426         uint16_t i;
6427         struct i40e_rx_queue *rxq;
6428
6429         i40e_pf_config_mq_rx(pf);
6430         for (i = 0; i < data->nb_rx_queues; i++) {
6431                 rxq = data->rx_queues[i];
6432                 if (!rxq || !rxq->q_set)
6433                         continue;
6434
6435                 ret = i40e_rx_queue_init(rxq);
6436                 if (ret != I40E_SUCCESS) {
6437                         PMD_DRV_LOG(ERR,
6438                                 "Failed to do RX queue initialization");
6439                         break;
6440                 }
6441         }
6442         if (ret == I40E_SUCCESS)
6443                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6444                                      ->eth_dev);
6445
6446         return ret;
6447 }
6448
6449 static int
6450 i40e_dev_rxtx_init(struct i40e_pf *pf)
6451 {
6452         int err;
6453
6454         err = i40e_dev_tx_init(pf);
6455         if (err) {
6456                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6457                 return err;
6458         }
6459         err = i40e_dev_rx_init(pf);
6460         if (err) {
6461                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6462                 return err;
6463         }
6464
6465         return err;
6466 }
6467
6468 static int
6469 i40e_vmdq_setup(struct rte_eth_dev *dev)
6470 {
6471         struct rte_eth_conf *conf = &dev->data->dev_conf;
6472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6473         int i, err, conf_vsis, j, loop;
6474         struct i40e_vsi *vsi;
6475         struct i40e_vmdq_info *vmdq_info;
6476         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6478
6479         /*
6480          * Disable interrupt to avoid message from VF. Furthermore, it will
6481          * avoid race condition in VSI creation/destroy.
6482          */
6483         i40e_pf_disable_irq0(hw);
6484
6485         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6486                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6487                 return -ENOTSUP;
6488         }
6489
6490         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6491         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6492                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6493                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6494                         pf->max_nb_vmdq_vsi);
6495                 return -ENOTSUP;
6496         }
6497
6498         if (pf->vmdq != NULL) {
6499                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6500                 return 0;
6501         }
6502
6503         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6504                                 sizeof(*vmdq_info) * conf_vsis, 0);
6505
6506         if (pf->vmdq == NULL) {
6507                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6508                 return -ENOMEM;
6509         }
6510
6511         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6512
6513         /* Create VMDQ VSI */
6514         for (i = 0; i < conf_vsis; i++) {
6515                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6516                                 vmdq_conf->enable_loop_back);
6517                 if (vsi == NULL) {
6518                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6519                         err = -1;
6520                         goto err_vsi_setup;
6521                 }
6522                 vmdq_info = &pf->vmdq[i];
6523                 vmdq_info->pf = pf;
6524                 vmdq_info->vsi = vsi;
6525         }
6526         pf->nb_cfg_vmdq_vsi = conf_vsis;
6527
6528         /* Configure Vlan */
6529         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6530         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6531                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6532                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6533                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6534                                         vmdq_conf->pool_map[i].vlan_id, j);
6535
6536                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6537                                                 vmdq_conf->pool_map[i].vlan_id);
6538                                 if (err) {
6539                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6540                                         err = -1;
6541                                         goto err_vsi_setup;
6542                                 }
6543                         }
6544                 }
6545         }
6546
6547         i40e_pf_enable_irq0(hw);
6548
6549         return 0;
6550
6551 err_vsi_setup:
6552         for (i = 0; i < conf_vsis; i++)
6553                 if (pf->vmdq[i].vsi == NULL)
6554                         break;
6555                 else
6556                         i40e_vsi_release(pf->vmdq[i].vsi);
6557
6558         rte_free(pf->vmdq);
6559         pf->vmdq = NULL;
6560         i40e_pf_enable_irq0(hw);
6561         return err;
6562 }
6563
6564 static void
6565 i40e_stat_update_32(struct i40e_hw *hw,
6566                    uint32_t reg,
6567                    bool offset_loaded,
6568                    uint64_t *offset,
6569                    uint64_t *stat)
6570 {
6571         uint64_t new_data;
6572
6573         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6574         if (!offset_loaded)
6575                 *offset = new_data;
6576
6577         if (new_data >= *offset)
6578                 *stat = (uint64_t)(new_data - *offset);
6579         else
6580                 *stat = (uint64_t)((new_data +
6581                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6582 }
6583
6584 static void
6585 i40e_stat_update_48(struct i40e_hw *hw,
6586                    uint32_t hireg,
6587                    uint32_t loreg,
6588                    bool offset_loaded,
6589                    uint64_t *offset,
6590                    uint64_t *stat)
6591 {
6592         uint64_t new_data;
6593
6594         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6595         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6596                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6597
6598         if (!offset_loaded)
6599                 *offset = new_data;
6600
6601         if (new_data >= *offset)
6602                 *stat = new_data - *offset;
6603         else
6604                 *stat = (uint64_t)((new_data +
6605                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6606
6607         *stat &= I40E_48_BIT_MASK;
6608 }
6609
6610 /* Disable IRQ0 */
6611 void
6612 i40e_pf_disable_irq0(struct i40e_hw *hw)
6613 {
6614         /* Disable all interrupt types */
6615         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6616                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6617         I40E_WRITE_FLUSH(hw);
6618 }
6619
6620 /* Enable IRQ0 */
6621 void
6622 i40e_pf_enable_irq0(struct i40e_hw *hw)
6623 {
6624         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6625                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6626                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6627                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6628         I40E_WRITE_FLUSH(hw);
6629 }
6630
6631 static void
6632 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6633 {
6634         /* read pending request and disable first */
6635         i40e_pf_disable_irq0(hw);
6636         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6637         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6638                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6639
6640         if (no_queue)
6641                 /* Link no queues with irq0 */
6642                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6643                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6644 }
6645
6646 static void
6647 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6648 {
6649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6650         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6651         int i;
6652         uint16_t abs_vf_id;
6653         uint32_t index, offset, val;
6654
6655         if (!pf->vfs)
6656                 return;
6657         /**
6658          * Try to find which VF trigger a reset, use absolute VF id to access
6659          * since the reg is global register.
6660          */
6661         for (i = 0; i < pf->vf_num; i++) {
6662                 abs_vf_id = hw->func_caps.vf_base_id + i;
6663                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6664                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6665                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6666                 /* VFR event occurred */
6667                 if (val & (0x1 << offset)) {
6668                         int ret;
6669
6670                         /* Clear the event first */
6671                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6672                                                         (0x1 << offset));
6673                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6674                         /**
6675                          * Only notify a VF reset event occurred,
6676                          * don't trigger another SW reset
6677                          */
6678                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6679                         if (ret != I40E_SUCCESS)
6680                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6681                 }
6682         }
6683 }
6684
6685 static void
6686 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6687 {
6688         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6689         int i;
6690
6691         for (i = 0; i < pf->vf_num; i++)
6692                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6693 }
6694
6695 static void
6696 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6697 {
6698         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6699         struct i40e_arq_event_info info;
6700         uint16_t pending, opcode;
6701         int ret;
6702
6703         info.buf_len = I40E_AQ_BUF_SZ;
6704         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6705         if (!info.msg_buf) {
6706                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6707                 return;
6708         }
6709
6710         pending = 1;
6711         while (pending) {
6712                 ret = i40e_clean_arq_element(hw, &info, &pending);
6713
6714                 if (ret != I40E_SUCCESS) {
6715                         PMD_DRV_LOG(INFO,
6716                                 "Failed to read msg from AdminQ, aq_err: %u",
6717                                 hw->aq.asq_last_status);
6718                         break;
6719                 }
6720                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6721
6722                 switch (opcode) {
6723                 case i40e_aqc_opc_send_msg_to_pf:
6724                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6725                         i40e_pf_host_handle_vf_msg(dev,
6726                                         rte_le_to_cpu_16(info.desc.retval),
6727                                         rte_le_to_cpu_32(info.desc.cookie_high),
6728                                         rte_le_to_cpu_32(info.desc.cookie_low),
6729                                         info.msg_buf,
6730                                         info.msg_len);
6731                         break;
6732                 case i40e_aqc_opc_get_link_status:
6733                         ret = i40e_dev_link_update(dev, 0);
6734                         if (!ret)
6735                                 _rte_eth_dev_callback_process(dev,
6736                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6737                         break;
6738                 default:
6739                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6740                                     opcode);
6741                         break;
6742                 }
6743         }
6744         rte_free(info.msg_buf);
6745 }
6746
6747 /**
6748  * Interrupt handler triggered by NIC  for handling
6749  * specific interrupt.
6750  *
6751  * @param handle
6752  *  Pointer to interrupt handle.
6753  * @param param
6754  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6755  *
6756  * @return
6757  *  void
6758  */
6759 static void
6760 i40e_dev_interrupt_handler(void *param)
6761 {
6762         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6764         uint32_t icr0;
6765
6766         /* Disable interrupt */
6767         i40e_pf_disable_irq0(hw);
6768
6769         /* read out interrupt causes */
6770         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6771
6772         /* No interrupt event indicated */
6773         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6774                 PMD_DRV_LOG(INFO, "No interrupt event");
6775                 goto done;
6776         }
6777         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6778                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6779         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6780                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6781         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6782                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6783         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6784                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6785         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6786                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6787         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6788                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6789         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6790                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6791
6792         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6793                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6794                 i40e_dev_handle_vfr_event(dev);
6795         }
6796         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6797                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6798                 i40e_dev_handle_aq_msg(dev);
6799         }
6800
6801 done:
6802         /* Enable interrupt */
6803         i40e_pf_enable_irq0(hw);
6804 }
6805
6806 static void
6807 i40e_dev_alarm_handler(void *param)
6808 {
6809         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6810         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811         uint32_t icr0;
6812
6813         /* Disable interrupt */
6814         i40e_pf_disable_irq0(hw);
6815
6816         /* read out interrupt causes */
6817         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6818
6819         /* No interrupt event indicated */
6820         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6821                 goto done;
6822         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6823                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6824         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6825                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6826         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6827                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6828         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6829                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6830         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6831                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6832         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6833                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6834         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6835                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6836
6837         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6838                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6839                 i40e_dev_handle_vfr_event(dev);
6840         }
6841         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6842                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6843                 i40e_dev_handle_aq_msg(dev);
6844         }
6845
6846 done:
6847         /* Enable interrupt */
6848         i40e_pf_enable_irq0(hw);
6849         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6850                           i40e_dev_alarm_handler, dev);
6851 }
6852
6853 int
6854 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6855                          struct i40e_macvlan_filter *filter,
6856                          int total)
6857 {
6858         int ele_num, ele_buff_size;
6859         int num, actual_num, i;
6860         uint16_t flags;
6861         int ret = I40E_SUCCESS;
6862         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6863         struct i40e_aqc_add_macvlan_element_data *req_list;
6864
6865         if (filter == NULL  || total == 0)
6866                 return I40E_ERR_PARAM;
6867         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6868         ele_buff_size = hw->aq.asq_buf_size;
6869
6870         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6871         if (req_list == NULL) {
6872                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6873                 return I40E_ERR_NO_MEMORY;
6874         }
6875
6876         num = 0;
6877         do {
6878                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6879                 memset(req_list, 0, ele_buff_size);
6880
6881                 for (i = 0; i < actual_num; i++) {
6882                         rte_memcpy(req_list[i].mac_addr,
6883                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6884                         req_list[i].vlan_tag =
6885                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6886
6887                         switch (filter[num + i].filter_type) {
6888                         case RTE_MAC_PERFECT_MATCH:
6889                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6890                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6891                                 break;
6892                         case RTE_MACVLAN_PERFECT_MATCH:
6893                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6894                                 break;
6895                         case RTE_MAC_HASH_MATCH:
6896                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6897                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6898                                 break;
6899                         case RTE_MACVLAN_HASH_MATCH:
6900                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6901                                 break;
6902                         default:
6903                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6904                                 ret = I40E_ERR_PARAM;
6905                                 goto DONE;
6906                         }
6907
6908                         req_list[i].queue_number = 0;
6909
6910                         req_list[i].flags = rte_cpu_to_le_16(flags);
6911                 }
6912
6913                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6914                                                 actual_num, NULL);
6915                 if (ret != I40E_SUCCESS) {
6916                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6917                         goto DONE;
6918                 }
6919                 num += actual_num;
6920         } while (num < total);
6921
6922 DONE:
6923         rte_free(req_list);
6924         return ret;
6925 }
6926
6927 int
6928 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6929                             struct i40e_macvlan_filter *filter,
6930                             int total)
6931 {
6932         int ele_num, ele_buff_size;
6933         int num, actual_num, i;
6934         uint16_t flags;
6935         int ret = I40E_SUCCESS;
6936         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6937         struct i40e_aqc_remove_macvlan_element_data *req_list;
6938
6939         if (filter == NULL  || total == 0)
6940                 return I40E_ERR_PARAM;
6941
6942         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6943         ele_buff_size = hw->aq.asq_buf_size;
6944
6945         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6946         if (req_list == NULL) {
6947                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6948                 return I40E_ERR_NO_MEMORY;
6949         }
6950
6951         num = 0;
6952         do {
6953                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6954                 memset(req_list, 0, ele_buff_size);
6955
6956                 for (i = 0; i < actual_num; i++) {
6957                         rte_memcpy(req_list[i].mac_addr,
6958                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6959                         req_list[i].vlan_tag =
6960                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6961
6962                         switch (filter[num + i].filter_type) {
6963                         case RTE_MAC_PERFECT_MATCH:
6964                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6965                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6966                                 break;
6967                         case RTE_MACVLAN_PERFECT_MATCH:
6968                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6969                                 break;
6970                         case RTE_MAC_HASH_MATCH:
6971                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6972                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6973                                 break;
6974                         case RTE_MACVLAN_HASH_MATCH:
6975                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6976                                 break;
6977                         default:
6978                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6979                                 ret = I40E_ERR_PARAM;
6980                                 goto DONE;
6981                         }
6982                         req_list[i].flags = rte_cpu_to_le_16(flags);
6983                 }
6984
6985                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6986                                                 actual_num, NULL);
6987                 if (ret != I40E_SUCCESS) {
6988                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6989                         goto DONE;
6990                 }
6991                 num += actual_num;
6992         } while (num < total);
6993
6994 DONE:
6995         rte_free(req_list);
6996         return ret;
6997 }
6998
6999 /* Find out specific MAC filter */
7000 static struct i40e_mac_filter *
7001 i40e_find_mac_filter(struct i40e_vsi *vsi,
7002                          struct rte_ether_addr *macaddr)
7003 {
7004         struct i40e_mac_filter *f;
7005
7006         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7007                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7008                         return f;
7009         }
7010
7011         return NULL;
7012 }
7013
7014 static bool
7015 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7016                          uint16_t vlan_id)
7017 {
7018         uint32_t vid_idx, vid_bit;
7019
7020         if (vlan_id > ETH_VLAN_ID_MAX)
7021                 return 0;
7022
7023         vid_idx = I40E_VFTA_IDX(vlan_id);
7024         vid_bit = I40E_VFTA_BIT(vlan_id);
7025
7026         if (vsi->vfta[vid_idx] & vid_bit)
7027                 return 1;
7028         else
7029                 return 0;
7030 }
7031
7032 static void
7033 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7034                        uint16_t vlan_id, bool on)
7035 {
7036         uint32_t vid_idx, vid_bit;
7037
7038         vid_idx = I40E_VFTA_IDX(vlan_id);
7039         vid_bit = I40E_VFTA_BIT(vlan_id);
7040
7041         if (on)
7042                 vsi->vfta[vid_idx] |= vid_bit;
7043         else
7044                 vsi->vfta[vid_idx] &= ~vid_bit;
7045 }
7046
7047 void
7048 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7049                      uint16_t vlan_id, bool on)
7050 {
7051         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7052         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7053         int ret;
7054
7055         if (vlan_id > ETH_VLAN_ID_MAX)
7056                 return;
7057
7058         i40e_store_vlan_filter(vsi, vlan_id, on);
7059
7060         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7061                 return;
7062
7063         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7064
7065         if (on) {
7066                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7067                                        &vlan_data, 1, NULL);
7068                 if (ret != I40E_SUCCESS)
7069                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7070         } else {
7071                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7072                                           &vlan_data, 1, NULL);
7073                 if (ret != I40E_SUCCESS)
7074                         PMD_DRV_LOG(ERR,
7075                                     "Failed to remove vlan filter");
7076         }
7077 }
7078
7079 /**
7080  * Find all vlan options for specific mac addr,
7081  * return with actual vlan found.
7082  */
7083 int
7084 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7085                            struct i40e_macvlan_filter *mv_f,
7086                            int num, struct rte_ether_addr *addr)
7087 {
7088         int i;
7089         uint32_t j, k;
7090
7091         /**
7092          * Not to use i40e_find_vlan_filter to decrease the loop time,
7093          * although the code looks complex.
7094           */
7095         if (num < vsi->vlan_num)
7096                 return I40E_ERR_PARAM;
7097
7098         i = 0;
7099         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7100                 if (vsi->vfta[j]) {
7101                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7102                                 if (vsi->vfta[j] & (1 << k)) {
7103                                         if (i > num - 1) {
7104                                                 PMD_DRV_LOG(ERR,
7105                                                         "vlan number doesn't match");
7106                                                 return I40E_ERR_PARAM;
7107                                         }
7108                                         rte_memcpy(&mv_f[i].macaddr,
7109                                                         addr, ETH_ADDR_LEN);
7110                                         mv_f[i].vlan_id =
7111                                                 j * I40E_UINT32_BIT_SIZE + k;
7112                                         i++;
7113                                 }
7114                         }
7115                 }
7116         }
7117         return I40E_SUCCESS;
7118 }
7119
7120 static inline int
7121 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7122                            struct i40e_macvlan_filter *mv_f,
7123                            int num,
7124                            uint16_t vlan)
7125 {
7126         int i = 0;
7127         struct i40e_mac_filter *f;
7128
7129         if (num < vsi->mac_num)
7130                 return I40E_ERR_PARAM;
7131
7132         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7133                 if (i > num - 1) {
7134                         PMD_DRV_LOG(ERR, "buffer number not match");
7135                         return I40E_ERR_PARAM;
7136                 }
7137                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7138                                 ETH_ADDR_LEN);
7139                 mv_f[i].vlan_id = vlan;
7140                 mv_f[i].filter_type = f->mac_info.filter_type;
7141                 i++;
7142         }
7143
7144         return I40E_SUCCESS;
7145 }
7146
7147 static int
7148 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7149 {
7150         int i, j, num;
7151         struct i40e_mac_filter *f;
7152         struct i40e_macvlan_filter *mv_f;
7153         int ret = I40E_SUCCESS;
7154
7155         if (vsi == NULL || vsi->mac_num == 0)
7156                 return I40E_ERR_PARAM;
7157
7158         /* Case that no vlan is set */
7159         if (vsi->vlan_num == 0)
7160                 num = vsi->mac_num;
7161         else
7162                 num = vsi->mac_num * vsi->vlan_num;
7163
7164         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7165         if (mv_f == NULL) {
7166                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7167                 return I40E_ERR_NO_MEMORY;
7168         }
7169
7170         i = 0;
7171         if (vsi->vlan_num == 0) {
7172                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7173                         rte_memcpy(&mv_f[i].macaddr,
7174                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7175                         mv_f[i].filter_type = f->mac_info.filter_type;
7176                         mv_f[i].vlan_id = 0;
7177                         i++;
7178                 }
7179         } else {
7180                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7181                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7182                                         vsi->vlan_num, &f->mac_info.mac_addr);
7183                         if (ret != I40E_SUCCESS)
7184                                 goto DONE;
7185                         for (j = i; j < i + vsi->vlan_num; j++)
7186                                 mv_f[j].filter_type = f->mac_info.filter_type;
7187                         i += vsi->vlan_num;
7188                 }
7189         }
7190
7191         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7192 DONE:
7193         rte_free(mv_f);
7194
7195         return ret;
7196 }
7197
7198 int
7199 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7200 {
7201         struct i40e_macvlan_filter *mv_f;
7202         int mac_num;
7203         int ret = I40E_SUCCESS;
7204
7205         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7206                 return I40E_ERR_PARAM;
7207
7208         /* If it's already set, just return */
7209         if (i40e_find_vlan_filter(vsi,vlan))
7210                 return I40E_SUCCESS;
7211
7212         mac_num = vsi->mac_num;
7213
7214         if (mac_num == 0) {
7215                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7216                 return I40E_ERR_PARAM;
7217         }
7218
7219         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7220
7221         if (mv_f == NULL) {
7222                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7223                 return I40E_ERR_NO_MEMORY;
7224         }
7225
7226         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7227
7228         if (ret != I40E_SUCCESS)
7229                 goto DONE;
7230
7231         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7232
7233         if (ret != I40E_SUCCESS)
7234                 goto DONE;
7235
7236         i40e_set_vlan_filter(vsi, vlan, 1);
7237
7238         vsi->vlan_num++;
7239         ret = I40E_SUCCESS;
7240 DONE:
7241         rte_free(mv_f);
7242         return ret;
7243 }
7244
7245 int
7246 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7247 {
7248         struct i40e_macvlan_filter *mv_f;
7249         int mac_num;
7250         int ret = I40E_SUCCESS;
7251
7252         /**
7253          * Vlan 0 is the generic filter for untagged packets
7254          * and can't be removed.
7255          */
7256         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7257                 return I40E_ERR_PARAM;
7258
7259         /* If can't find it, just return */
7260         if (!i40e_find_vlan_filter(vsi, vlan))
7261                 return I40E_ERR_PARAM;
7262
7263         mac_num = vsi->mac_num;
7264
7265         if (mac_num == 0) {
7266                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7267                 return I40E_ERR_PARAM;
7268         }
7269
7270         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7271
7272         if (mv_f == NULL) {
7273                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7274                 return I40E_ERR_NO_MEMORY;
7275         }
7276
7277         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7278
7279         if (ret != I40E_SUCCESS)
7280                 goto DONE;
7281
7282         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7283
7284         if (ret != I40E_SUCCESS)
7285                 goto DONE;
7286
7287         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7288         if (vsi->vlan_num == 1) {
7289                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7290                 if (ret != I40E_SUCCESS)
7291                         goto DONE;
7292
7293                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7294                 if (ret != I40E_SUCCESS)
7295                         goto DONE;
7296         }
7297
7298         i40e_set_vlan_filter(vsi, vlan, 0);
7299
7300         vsi->vlan_num--;
7301         ret = I40E_SUCCESS;
7302 DONE:
7303         rte_free(mv_f);
7304         return ret;
7305 }
7306
7307 int
7308 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7309 {
7310         struct i40e_mac_filter *f;
7311         struct i40e_macvlan_filter *mv_f;
7312         int i, vlan_num = 0;
7313         int ret = I40E_SUCCESS;
7314
7315         /* If it's add and we've config it, return */
7316         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7317         if (f != NULL)
7318                 return I40E_SUCCESS;
7319         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7320                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7321
7322                 /**
7323                  * If vlan_num is 0, that's the first time to add mac,
7324                  * set mask for vlan_id 0.
7325                  */
7326                 if (vsi->vlan_num == 0) {
7327                         i40e_set_vlan_filter(vsi, 0, 1);
7328                         vsi->vlan_num = 1;
7329                 }
7330                 vlan_num = vsi->vlan_num;
7331         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7332                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7333                 vlan_num = 1;
7334
7335         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7336         if (mv_f == NULL) {
7337                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7338                 return I40E_ERR_NO_MEMORY;
7339         }
7340
7341         for (i = 0; i < vlan_num; i++) {
7342                 mv_f[i].filter_type = mac_filter->filter_type;
7343                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7344                                 ETH_ADDR_LEN);
7345         }
7346
7347         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7348                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7349                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7350                                         &mac_filter->mac_addr);
7351                 if (ret != I40E_SUCCESS)
7352                         goto DONE;
7353         }
7354
7355         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7356         if (ret != I40E_SUCCESS)
7357                 goto DONE;
7358
7359         /* Add the mac addr into mac list */
7360         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7361         if (f == NULL) {
7362                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7363                 ret = I40E_ERR_NO_MEMORY;
7364                 goto DONE;
7365         }
7366         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7367                         ETH_ADDR_LEN);
7368         f->mac_info.filter_type = mac_filter->filter_type;
7369         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7370         vsi->mac_num++;
7371
7372         ret = I40E_SUCCESS;
7373 DONE:
7374         rte_free(mv_f);
7375
7376         return ret;
7377 }
7378
7379 int
7380 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7381 {
7382         struct i40e_mac_filter *f;
7383         struct i40e_macvlan_filter *mv_f;
7384         int i, vlan_num;
7385         enum rte_mac_filter_type filter_type;
7386         int ret = I40E_SUCCESS;
7387
7388         /* Can't find it, return an error */
7389         f = i40e_find_mac_filter(vsi, addr);
7390         if (f == NULL)
7391                 return I40E_ERR_PARAM;
7392
7393         vlan_num = vsi->vlan_num;
7394         filter_type = f->mac_info.filter_type;
7395         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7396                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7397                 if (vlan_num == 0) {
7398                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7399                         return I40E_ERR_PARAM;
7400                 }
7401         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7402                         filter_type == RTE_MAC_HASH_MATCH)
7403                 vlan_num = 1;
7404
7405         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7406         if (mv_f == NULL) {
7407                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7408                 return I40E_ERR_NO_MEMORY;
7409         }
7410
7411         for (i = 0; i < vlan_num; i++) {
7412                 mv_f[i].filter_type = filter_type;
7413                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7414                                 ETH_ADDR_LEN);
7415         }
7416         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7417                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7418                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7419                 if (ret != I40E_SUCCESS)
7420                         goto DONE;
7421         }
7422
7423         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7424         if (ret != I40E_SUCCESS)
7425                 goto DONE;
7426
7427         /* Remove the mac addr into mac list */
7428         TAILQ_REMOVE(&vsi->mac_list, f, next);
7429         rte_free(f);
7430         vsi->mac_num--;
7431
7432         ret = I40E_SUCCESS;
7433 DONE:
7434         rte_free(mv_f);
7435         return ret;
7436 }
7437
7438 /* Configure hash enable flags for RSS */
7439 uint64_t
7440 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7441 {
7442         uint64_t hena = 0;
7443         int i;
7444
7445         if (!flags)
7446                 return hena;
7447
7448         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7449                 if (flags & (1ULL << i))
7450                         hena |= adapter->pctypes_tbl[i];
7451         }
7452
7453         return hena;
7454 }
7455
7456 /* Parse the hash enable flags */
7457 uint64_t
7458 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7459 {
7460         uint64_t rss_hf = 0;
7461
7462         if (!flags)
7463                 return rss_hf;
7464         int i;
7465
7466         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7467                 if (flags & adapter->pctypes_tbl[i])
7468                         rss_hf |= (1ULL << i);
7469         }
7470         return rss_hf;
7471 }
7472
7473 /* Disable RSS */
7474 static void
7475 i40e_pf_disable_rss(struct i40e_pf *pf)
7476 {
7477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7478
7479         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7480         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7481         I40E_WRITE_FLUSH(hw);
7482 }
7483
7484 int
7485 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7486 {
7487         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7488         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7489         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7490                            I40E_VFQF_HKEY_MAX_INDEX :
7491                            I40E_PFQF_HKEY_MAX_INDEX;
7492         int ret = 0;
7493
7494         if (!key || key_len == 0) {
7495                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7496                 return 0;
7497         } else if (key_len != (key_idx + 1) *
7498                 sizeof(uint32_t)) {
7499                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7500                 return -EINVAL;
7501         }
7502
7503         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7504                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7505                         (struct i40e_aqc_get_set_rss_key_data *)key;
7506
7507                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7508                 if (ret)
7509                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7510         } else {
7511                 uint32_t *hash_key = (uint32_t *)key;
7512                 uint16_t i;
7513
7514                 if (vsi->type == I40E_VSI_SRIOV) {
7515                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7516                                 I40E_WRITE_REG(
7517                                         hw,
7518                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7519                                         hash_key[i]);
7520
7521                 } else {
7522                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7523                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7524                                                hash_key[i]);
7525                 }
7526                 I40E_WRITE_FLUSH(hw);
7527         }
7528
7529         return ret;
7530 }
7531
7532 static int
7533 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7534 {
7535         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7536         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7537         uint32_t reg;
7538         int ret;
7539
7540         if (!key || !key_len)
7541                 return 0;
7542
7543         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7544                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7545                         (struct i40e_aqc_get_set_rss_key_data *)key);
7546                 if (ret) {
7547                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7548                         return ret;
7549                 }
7550         } else {
7551                 uint32_t *key_dw = (uint32_t *)key;
7552                 uint16_t i;
7553
7554                 if (vsi->type == I40E_VSI_SRIOV) {
7555                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7556                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7557                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7558                         }
7559                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7560                                    sizeof(uint32_t);
7561                 } else {
7562                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7563                                 reg = I40E_PFQF_HKEY(i);
7564                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7565                         }
7566                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7567                                    sizeof(uint32_t);
7568                 }
7569         }
7570         return 0;
7571 }
7572
7573 static int
7574 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7575 {
7576         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7577         uint64_t hena;
7578         int ret;
7579
7580         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7581                                rss_conf->rss_key_len);
7582         if (ret)
7583                 return ret;
7584
7585         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7586         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7587         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7588         I40E_WRITE_FLUSH(hw);
7589
7590         return 0;
7591 }
7592
7593 static int
7594 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7595                          struct rte_eth_rss_conf *rss_conf)
7596 {
7597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7599         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7600         uint64_t hena;
7601
7602         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7603         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7604
7605         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7606                 if (rss_hf != 0) /* Enable RSS */
7607                         return -EINVAL;
7608                 return 0; /* Nothing to do */
7609         }
7610         /* RSS enabled */
7611         if (rss_hf == 0) /* Disable RSS */
7612                 return -EINVAL;
7613
7614         return i40e_hw_rss_hash_set(pf, rss_conf);
7615 }
7616
7617 static int
7618 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7619                            struct rte_eth_rss_conf *rss_conf)
7620 {
7621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7623         uint64_t hena;
7624         int ret;
7625
7626         if (!rss_conf)
7627                 return -EINVAL;
7628
7629         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7630                          &rss_conf->rss_key_len);
7631         if (ret)
7632                 return ret;
7633
7634         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7635         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7636         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7637
7638         return 0;
7639 }
7640
7641 static int
7642 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7643 {
7644         switch (filter_type) {
7645         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7646                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7647                 break;
7648         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7649                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7650                 break;
7651         case RTE_TUNNEL_FILTER_IMAC_TENID:
7652                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7653                 break;
7654         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7655                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7656                 break;
7657         case ETH_TUNNEL_FILTER_IMAC:
7658                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7659                 break;
7660         case ETH_TUNNEL_FILTER_OIP:
7661                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7662                 break;
7663         case ETH_TUNNEL_FILTER_IIP:
7664                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7665                 break;
7666         default:
7667                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7668                 return -EINVAL;
7669         }
7670
7671         return 0;
7672 }
7673
7674 /* Convert tunnel filter structure */
7675 static int
7676 i40e_tunnel_filter_convert(
7677         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7678         struct i40e_tunnel_filter *tunnel_filter)
7679 {
7680         rte_ether_addr_copy((struct rte_ether_addr *)
7681                         &cld_filter->element.outer_mac,
7682                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7683         rte_ether_addr_copy((struct rte_ether_addr *)
7684                         &cld_filter->element.inner_mac,
7685                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7686         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7687         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7688              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7689             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7690                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7691         else
7692                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7693         tunnel_filter->input.flags = cld_filter->element.flags;
7694         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7695         tunnel_filter->queue = cld_filter->element.queue_number;
7696         rte_memcpy(tunnel_filter->input.general_fields,
7697                    cld_filter->general_fields,
7698                    sizeof(cld_filter->general_fields));
7699
7700         return 0;
7701 }
7702
7703 /* Check if there exists the tunnel filter */
7704 struct i40e_tunnel_filter *
7705 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7706                              const struct i40e_tunnel_filter_input *input)
7707 {
7708         int ret;
7709
7710         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7711         if (ret < 0)
7712                 return NULL;
7713
7714         return tunnel_rule->hash_map[ret];
7715 }
7716
7717 /* Add a tunnel filter into the SW list */
7718 static int
7719 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7720                              struct i40e_tunnel_filter *tunnel_filter)
7721 {
7722         struct i40e_tunnel_rule *rule = &pf->tunnel;
7723         int ret;
7724
7725         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7726         if (ret < 0) {
7727                 PMD_DRV_LOG(ERR,
7728                             "Failed to insert tunnel filter to hash table %d!",
7729                             ret);
7730                 return ret;
7731         }
7732         rule->hash_map[ret] = tunnel_filter;
7733
7734         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7735
7736         return 0;
7737 }
7738
7739 /* Delete a tunnel filter from the SW list */
7740 int
7741 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7742                           struct i40e_tunnel_filter_input *input)
7743 {
7744         struct i40e_tunnel_rule *rule = &pf->tunnel;
7745         struct i40e_tunnel_filter *tunnel_filter;
7746         int ret;
7747
7748         ret = rte_hash_del_key(rule->hash_table, input);
7749         if (ret < 0) {
7750                 PMD_DRV_LOG(ERR,
7751                             "Failed to delete tunnel filter to hash table %d!",
7752                             ret);
7753                 return ret;
7754         }
7755         tunnel_filter = rule->hash_map[ret];
7756         rule->hash_map[ret] = NULL;
7757
7758         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7759         rte_free(tunnel_filter);
7760
7761         return 0;
7762 }
7763
7764 int
7765 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7766                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7767                         uint8_t add)
7768 {
7769         uint16_t ip_type;
7770         uint32_t ipv4_addr, ipv4_addr_le;
7771         uint8_t i, tun_type = 0;
7772         /* internal varialbe to convert ipv6 byte order */
7773         uint32_t convert_ipv6[4];
7774         int val, ret = 0;
7775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7776         struct i40e_vsi *vsi = pf->main_vsi;
7777         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7778         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7779         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7780         struct i40e_tunnel_filter *tunnel, *node;
7781         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7782
7783         cld_filter = rte_zmalloc("tunnel_filter",
7784                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7785         0);
7786
7787         if (NULL == cld_filter) {
7788                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7789                 return -ENOMEM;
7790         }
7791         pfilter = cld_filter;
7792
7793         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7794                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7795         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7796                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7797
7798         pfilter->element.inner_vlan =
7799                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7800         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7801                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7802                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7803                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7804                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7805                                 &ipv4_addr_le,
7806                                 sizeof(pfilter->element.ipaddr.v4.data));
7807         } else {
7808                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7809                 for (i = 0; i < 4; i++) {
7810                         convert_ipv6[i] =
7811                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7812                 }
7813                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7814                            &convert_ipv6,
7815                            sizeof(pfilter->element.ipaddr.v6.data));
7816         }
7817
7818         /* check tunneled type */
7819         switch (tunnel_filter->tunnel_type) {
7820         case RTE_TUNNEL_TYPE_VXLAN:
7821                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7822                 break;
7823         case RTE_TUNNEL_TYPE_NVGRE:
7824                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7825                 break;
7826         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7827                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7828                 break;
7829         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7830                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7831                 break;
7832         default:
7833                 /* Other tunnel types is not supported. */
7834                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7835                 rte_free(cld_filter);
7836                 return -EINVAL;
7837         }
7838
7839         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7840                                        &pfilter->element.flags);
7841         if (val < 0) {
7842                 rte_free(cld_filter);
7843                 return -EINVAL;
7844         }
7845
7846         pfilter->element.flags |= rte_cpu_to_le_16(
7847                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7848                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7849         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7850         pfilter->element.queue_number =
7851                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7852
7853         /* Check if there is the filter in SW list */
7854         memset(&check_filter, 0, sizeof(check_filter));
7855         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7856         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7857         if (add && node) {
7858                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7859                 rte_free(cld_filter);
7860                 return -EINVAL;
7861         }
7862
7863         if (!add && !node) {
7864                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7865                 rte_free(cld_filter);
7866                 return -EINVAL;
7867         }
7868
7869         if (add) {
7870                 ret = i40e_aq_add_cloud_filters(hw,
7871                                         vsi->seid, &cld_filter->element, 1);
7872                 if (ret < 0) {
7873                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7874                         rte_free(cld_filter);
7875                         return -ENOTSUP;
7876                 }
7877                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7878                 if (tunnel == NULL) {
7879                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7880                         rte_free(cld_filter);
7881                         return -ENOMEM;
7882                 }
7883
7884                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7885                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7886                 if (ret < 0)
7887                         rte_free(tunnel);
7888         } else {
7889                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7890                                                    &cld_filter->element, 1);
7891                 if (ret < 0) {
7892                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7893                         rte_free(cld_filter);
7894                         return -ENOTSUP;
7895                 }
7896                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7897         }
7898
7899         rte_free(cld_filter);
7900         return ret;
7901 }
7902
7903 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7904 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7905 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7906 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7907 #define I40E_TR_GRE_KEY_MASK                    0x400
7908 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7909 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7910
7911 static enum
7912 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7913 {
7914         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7915         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7916         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7917         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7918         enum i40e_status_code status = I40E_SUCCESS;
7919
7920         if (pf->support_multi_driver) {
7921                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7922                 return I40E_NOT_SUPPORTED;
7923         }
7924
7925         memset(&filter_replace, 0,
7926                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7927         memset(&filter_replace_buf, 0,
7928                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7929
7930         /* create L1 filter */
7931         filter_replace.old_filter_type =
7932                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7933         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7934         filter_replace.tr_bit = 0;
7935
7936         /* Prepare the buffer, 3 entries */
7937         filter_replace_buf.data[0] =
7938                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7939         filter_replace_buf.data[0] |=
7940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7941         filter_replace_buf.data[2] = 0xFF;
7942         filter_replace_buf.data[3] = 0xFF;
7943         filter_replace_buf.data[4] =
7944                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7945         filter_replace_buf.data[4] |=
7946                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7947         filter_replace_buf.data[7] = 0xF0;
7948         filter_replace_buf.data[8]
7949                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7950         filter_replace_buf.data[8] |=
7951                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7952         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7953                 I40E_TR_GENEVE_KEY_MASK |
7954                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7955         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7956                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7957                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7958
7959         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7960                                                &filter_replace_buf);
7961         if (!status && (filter_replace.old_filter_type !=
7962                         filter_replace.new_filter_type))
7963                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7964                             " original: 0x%x, new: 0x%x",
7965                             dev->device->name,
7966                             filter_replace.old_filter_type,
7967                             filter_replace.new_filter_type);
7968
7969         return status;
7970 }
7971
7972 static enum
7973 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7974 {
7975         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7976         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7978         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7979         enum i40e_status_code status = I40E_SUCCESS;
7980
7981         if (pf->support_multi_driver) {
7982                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7983                 return I40E_NOT_SUPPORTED;
7984         }
7985
7986         /* For MPLSoUDP */
7987         memset(&filter_replace, 0,
7988                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7989         memset(&filter_replace_buf, 0,
7990                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7991         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7992                 I40E_AQC_MIRROR_CLOUD_FILTER;
7993         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7994         filter_replace.new_filter_type =
7995                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7996         /* Prepare the buffer, 2 entries */
7997         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7998         filter_replace_buf.data[0] |=
7999                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8000         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8001         filter_replace_buf.data[4] |=
8002                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8003         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8004                                                &filter_replace_buf);
8005         if (status < 0)
8006                 return status;
8007         if (filter_replace.old_filter_type !=
8008             filter_replace.new_filter_type)
8009                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8010                             " original: 0x%x, new: 0x%x",
8011                             dev->device->name,
8012                             filter_replace.old_filter_type,
8013                             filter_replace.new_filter_type);
8014
8015         /* For MPLSoGRE */
8016         memset(&filter_replace, 0,
8017                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8018         memset(&filter_replace_buf, 0,
8019                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8020
8021         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8022                 I40E_AQC_MIRROR_CLOUD_FILTER;
8023         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8024         filter_replace.new_filter_type =
8025                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8026         /* Prepare the buffer, 2 entries */
8027         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8028         filter_replace_buf.data[0] |=
8029                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8030         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8031         filter_replace_buf.data[4] |=
8032                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8033
8034         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8035                                                &filter_replace_buf);
8036         if (!status && (filter_replace.old_filter_type !=
8037                         filter_replace.new_filter_type))
8038                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8039                             " original: 0x%x, new: 0x%x",
8040                             dev->device->name,
8041                             filter_replace.old_filter_type,
8042                             filter_replace.new_filter_type);
8043
8044         return status;
8045 }
8046
8047 static enum i40e_status_code
8048 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8049 {
8050         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8051         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8052         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8053         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8054         enum i40e_status_code status = I40E_SUCCESS;
8055
8056         if (pf->support_multi_driver) {
8057                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8058                 return I40E_NOT_SUPPORTED;
8059         }
8060
8061         /* For GTP-C */
8062         memset(&filter_replace, 0,
8063                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8064         memset(&filter_replace_buf, 0,
8065                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8066         /* create L1 filter */
8067         filter_replace.old_filter_type =
8068                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8069         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8070         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8071                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8072         /* Prepare the buffer, 2 entries */
8073         filter_replace_buf.data[0] =
8074                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8075         filter_replace_buf.data[0] |=
8076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8077         filter_replace_buf.data[2] = 0xFF;
8078         filter_replace_buf.data[3] = 0xFF;
8079         filter_replace_buf.data[4] =
8080                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8081         filter_replace_buf.data[4] |=
8082                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8083         filter_replace_buf.data[6] = 0xFF;
8084         filter_replace_buf.data[7] = 0xFF;
8085         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8086                                                &filter_replace_buf);
8087         if (status < 0)
8088                 return status;
8089         if (filter_replace.old_filter_type !=
8090             filter_replace.new_filter_type)
8091                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8092                             " original: 0x%x, new: 0x%x",
8093                             dev->device->name,
8094                             filter_replace.old_filter_type,
8095                             filter_replace.new_filter_type);
8096
8097         /* for GTP-U */
8098         memset(&filter_replace, 0,
8099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8100         memset(&filter_replace_buf, 0,
8101                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8102         /* create L1 filter */
8103         filter_replace.old_filter_type =
8104                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8105         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8106         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108         /* Prepare the buffer, 2 entries */
8109         filter_replace_buf.data[0] =
8110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8111         filter_replace_buf.data[0] |=
8112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8113         filter_replace_buf.data[2] = 0xFF;
8114         filter_replace_buf.data[3] = 0xFF;
8115         filter_replace_buf.data[4] =
8116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8117         filter_replace_buf.data[4] |=
8118                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8119         filter_replace_buf.data[6] = 0xFF;
8120         filter_replace_buf.data[7] = 0xFF;
8121
8122         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8123                                                &filter_replace_buf);
8124         if (!status && (filter_replace.old_filter_type !=
8125                         filter_replace.new_filter_type))
8126                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8127                             " original: 0x%x, new: 0x%x",
8128                             dev->device->name,
8129                             filter_replace.old_filter_type,
8130                             filter_replace.new_filter_type);
8131
8132         return status;
8133 }
8134
8135 static enum
8136 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8137 {
8138         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8139         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8141         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8142         enum i40e_status_code status = I40E_SUCCESS;
8143
8144         if (pf->support_multi_driver) {
8145                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8146                 return I40E_NOT_SUPPORTED;
8147         }
8148
8149         /* for GTP-C */
8150         memset(&filter_replace, 0,
8151                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8152         memset(&filter_replace_buf, 0,
8153                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8154         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8155         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8156         filter_replace.new_filter_type =
8157                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8158         /* Prepare the buffer, 2 entries */
8159         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8160         filter_replace_buf.data[0] |=
8161                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8162         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8163         filter_replace_buf.data[4] |=
8164                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8165         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8166                                                &filter_replace_buf);
8167         if (status < 0)
8168                 return status;
8169         if (filter_replace.old_filter_type !=
8170             filter_replace.new_filter_type)
8171                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8172                             " original: 0x%x, new: 0x%x",
8173                             dev->device->name,
8174                             filter_replace.old_filter_type,
8175                             filter_replace.new_filter_type);
8176
8177         /* for GTP-U */
8178         memset(&filter_replace, 0,
8179                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8180         memset(&filter_replace_buf, 0,
8181                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8182         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8183         filter_replace.old_filter_type =
8184                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8185         filter_replace.new_filter_type =
8186                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8187         /* Prepare the buffer, 2 entries */
8188         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8189         filter_replace_buf.data[0] |=
8190                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8191         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8192         filter_replace_buf.data[4] |=
8193                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8194
8195         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8196                                                &filter_replace_buf);
8197         if (!status && (filter_replace.old_filter_type !=
8198                         filter_replace.new_filter_type))
8199                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8200                             " original: 0x%x, new: 0x%x",
8201                             dev->device->name,
8202                             filter_replace.old_filter_type,
8203                             filter_replace.new_filter_type);
8204
8205         return status;
8206 }
8207
8208 int
8209 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8210                       struct i40e_tunnel_filter_conf *tunnel_filter,
8211                       uint8_t add)
8212 {
8213         uint16_t ip_type;
8214         uint32_t ipv4_addr, ipv4_addr_le;
8215         uint8_t i, tun_type = 0;
8216         /* internal variable to convert ipv6 byte order */
8217         uint32_t convert_ipv6[4];
8218         int val, ret = 0;
8219         struct i40e_pf_vf *vf = NULL;
8220         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8221         struct i40e_vsi *vsi;
8222         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8223         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8224         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8225         struct i40e_tunnel_filter *tunnel, *node;
8226         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8227         uint32_t teid_le;
8228         bool big_buffer = 0;
8229
8230         cld_filter = rte_zmalloc("tunnel_filter",
8231                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8232                          0);
8233
8234         if (cld_filter == NULL) {
8235                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8236                 return -ENOMEM;
8237         }
8238         pfilter = cld_filter;
8239
8240         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8241                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8242         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8243                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8244
8245         pfilter->element.inner_vlan =
8246                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8247         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8248                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8249                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8250                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8251                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8252                                 &ipv4_addr_le,
8253                                 sizeof(pfilter->element.ipaddr.v4.data));
8254         } else {
8255                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8256                 for (i = 0; i < 4; i++) {
8257                         convert_ipv6[i] =
8258                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8259                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8260                 }
8261                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8262                            &convert_ipv6,
8263                            sizeof(pfilter->element.ipaddr.v6.data));
8264         }
8265
8266         /* check tunneled type */
8267         switch (tunnel_filter->tunnel_type) {
8268         case I40E_TUNNEL_TYPE_VXLAN:
8269                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8270                 break;
8271         case I40E_TUNNEL_TYPE_NVGRE:
8272                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8273                 break;
8274         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8275                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8276                 break;
8277         case I40E_TUNNEL_TYPE_MPLSoUDP:
8278                 if (!pf->mpls_replace_flag) {
8279                         i40e_replace_mpls_l1_filter(pf);
8280                         i40e_replace_mpls_cloud_filter(pf);
8281                         pf->mpls_replace_flag = 1;
8282                 }
8283                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8284                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8285                         teid_le >> 4;
8286                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8287                         (teid_le & 0xF) << 12;
8288                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8289                         0x40;
8290                 big_buffer = 1;
8291                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8292                 break;
8293         case I40E_TUNNEL_TYPE_MPLSoGRE:
8294                 if (!pf->mpls_replace_flag) {
8295                         i40e_replace_mpls_l1_filter(pf);
8296                         i40e_replace_mpls_cloud_filter(pf);
8297                         pf->mpls_replace_flag = 1;
8298                 }
8299                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8300                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8301                         teid_le >> 4;
8302                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8303                         (teid_le & 0xF) << 12;
8304                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8305                         0x0;
8306                 big_buffer = 1;
8307                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8308                 break;
8309         case I40E_TUNNEL_TYPE_GTPC:
8310                 if (!pf->gtp_replace_flag) {
8311                         i40e_replace_gtp_l1_filter(pf);
8312                         i40e_replace_gtp_cloud_filter(pf);
8313                         pf->gtp_replace_flag = 1;
8314                 }
8315                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8316                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8317                         (teid_le >> 16) & 0xFFFF;
8318                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8319                         teid_le & 0xFFFF;
8320                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8321                         0x0;
8322                 big_buffer = 1;
8323                 break;
8324         case I40E_TUNNEL_TYPE_GTPU:
8325                 if (!pf->gtp_replace_flag) {
8326                         i40e_replace_gtp_l1_filter(pf);
8327                         i40e_replace_gtp_cloud_filter(pf);
8328                         pf->gtp_replace_flag = 1;
8329                 }
8330                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8331                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8332                         (teid_le >> 16) & 0xFFFF;
8333                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8334                         teid_le & 0xFFFF;
8335                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8336                         0x0;
8337                 big_buffer = 1;
8338                 break;
8339         case I40E_TUNNEL_TYPE_QINQ:
8340                 if (!pf->qinq_replace_flag) {
8341                         ret = i40e_cloud_filter_qinq_create(pf);
8342                         if (ret < 0)
8343                                 PMD_DRV_LOG(DEBUG,
8344                                             "QinQ tunnel filter already created.");
8345                         pf->qinq_replace_flag = 1;
8346                 }
8347                 /*      Add in the General fields the values of
8348                  *      the Outer and Inner VLAN
8349                  *      Big Buffer should be set, see changes in
8350                  *      i40e_aq_add_cloud_filters
8351                  */
8352                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8353                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8354                 big_buffer = 1;
8355                 break;
8356         default:
8357                 /* Other tunnel types is not supported. */
8358                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8359                 rte_free(cld_filter);
8360                 return -EINVAL;
8361         }
8362
8363         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8364                 pfilter->element.flags =
8365                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8366         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8367                 pfilter->element.flags =
8368                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8369         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8370                 pfilter->element.flags =
8371                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8372         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8373                 pfilter->element.flags =
8374                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8375         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8376                 pfilter->element.flags |=
8377                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8378         else {
8379                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8380                                                 &pfilter->element.flags);
8381                 if (val < 0) {
8382                         rte_free(cld_filter);
8383                         return -EINVAL;
8384                 }
8385         }
8386
8387         pfilter->element.flags |= rte_cpu_to_le_16(
8388                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8389                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8390         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8391         pfilter->element.queue_number =
8392                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8393
8394         if (!tunnel_filter->is_to_vf)
8395                 vsi = pf->main_vsi;
8396         else {
8397                 if (tunnel_filter->vf_id >= pf->vf_num) {
8398                         PMD_DRV_LOG(ERR, "Invalid argument.");
8399                         rte_free(cld_filter);
8400                         return -EINVAL;
8401                 }
8402                 vf = &pf->vfs[tunnel_filter->vf_id];
8403                 vsi = vf->vsi;
8404         }
8405
8406         /* Check if there is the filter in SW list */
8407         memset(&check_filter, 0, sizeof(check_filter));
8408         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8409         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8410         check_filter.vf_id = tunnel_filter->vf_id;
8411         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8412         if (add && node) {
8413                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8414                 rte_free(cld_filter);
8415                 return -EINVAL;
8416         }
8417
8418         if (!add && !node) {
8419                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8420                 rte_free(cld_filter);
8421                 return -EINVAL;
8422         }
8423
8424         if (add) {
8425                 if (big_buffer)
8426                         ret = i40e_aq_add_cloud_filters_bb(hw,
8427                                                    vsi->seid, cld_filter, 1);
8428                 else
8429                         ret = i40e_aq_add_cloud_filters(hw,
8430                                         vsi->seid, &cld_filter->element, 1);
8431                 if (ret < 0) {
8432                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8433                         rte_free(cld_filter);
8434                         return -ENOTSUP;
8435                 }
8436                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8437                 if (tunnel == NULL) {
8438                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8439                         rte_free(cld_filter);
8440                         return -ENOMEM;
8441                 }
8442
8443                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8444                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8445                 if (ret < 0)
8446                         rte_free(tunnel);
8447         } else {
8448                 if (big_buffer)
8449                         ret = i40e_aq_rem_cloud_filters_bb(
8450                                 hw, vsi->seid, cld_filter, 1);
8451                 else
8452                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8453                                                 &cld_filter->element, 1);
8454                 if (ret < 0) {
8455                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8456                         rte_free(cld_filter);
8457                         return -ENOTSUP;
8458                 }
8459                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8460         }
8461
8462         rte_free(cld_filter);
8463         return ret;
8464 }
8465
8466 static int
8467 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8468 {
8469         uint8_t i;
8470
8471         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8472                 if (pf->vxlan_ports[i] == port)
8473                         return i;
8474         }
8475
8476         return -1;
8477 }
8478
8479 static int
8480 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8481 {
8482         int  idx, ret;
8483         uint8_t filter_idx = 0;
8484         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8485
8486         idx = i40e_get_vxlan_port_idx(pf, port);
8487
8488         /* Check if port already exists */
8489         if (idx >= 0) {
8490                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8491                 return -EINVAL;
8492         }
8493
8494         /* Now check if there is space to add the new port */
8495         idx = i40e_get_vxlan_port_idx(pf, 0);
8496         if (idx < 0) {
8497                 PMD_DRV_LOG(ERR,
8498                         "Maximum number of UDP ports reached, not adding port %d",
8499                         port);
8500                 return -ENOSPC;
8501         }
8502
8503         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8504                                         &filter_idx, NULL);
8505         if (ret < 0) {
8506                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8507                 return -1;
8508         }
8509
8510         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8511                          port,  filter_idx);
8512
8513         /* New port: add it and mark its index in the bitmap */
8514         pf->vxlan_ports[idx] = port;
8515         pf->vxlan_bitmap |= (1 << idx);
8516
8517         if (!(pf->flags & I40E_FLAG_VXLAN))
8518                 pf->flags |= I40E_FLAG_VXLAN;
8519
8520         return 0;
8521 }
8522
8523 static int
8524 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8525 {
8526         int idx;
8527         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8528
8529         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8530                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8531                 return -EINVAL;
8532         }
8533
8534         idx = i40e_get_vxlan_port_idx(pf, port);
8535
8536         if (idx < 0) {
8537                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8538                 return -EINVAL;
8539         }
8540
8541         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8542                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8543                 return -1;
8544         }
8545
8546         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8547                         port, idx);
8548
8549         pf->vxlan_ports[idx] = 0;
8550         pf->vxlan_bitmap &= ~(1 << idx);
8551
8552         if (!pf->vxlan_bitmap)
8553                 pf->flags &= ~I40E_FLAG_VXLAN;
8554
8555         return 0;
8556 }
8557
8558 /* Add UDP tunneling port */
8559 static int
8560 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8561                              struct rte_eth_udp_tunnel *udp_tunnel)
8562 {
8563         int ret = 0;
8564         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8565
8566         if (udp_tunnel == NULL)
8567                 return -EINVAL;
8568
8569         switch (udp_tunnel->prot_type) {
8570         case RTE_TUNNEL_TYPE_VXLAN:
8571                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8572                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8573                 break;
8574         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8575                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8576                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8577                 break;
8578         case RTE_TUNNEL_TYPE_GENEVE:
8579         case RTE_TUNNEL_TYPE_TEREDO:
8580                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8581                 ret = -1;
8582                 break;
8583
8584         default:
8585                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8586                 ret = -1;
8587                 break;
8588         }
8589
8590         return ret;
8591 }
8592
8593 /* Remove UDP tunneling port */
8594 static int
8595 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8596                              struct rte_eth_udp_tunnel *udp_tunnel)
8597 {
8598         int ret = 0;
8599         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8600
8601         if (udp_tunnel == NULL)
8602                 return -EINVAL;
8603
8604         switch (udp_tunnel->prot_type) {
8605         case RTE_TUNNEL_TYPE_VXLAN:
8606         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8607                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8608                 break;
8609         case RTE_TUNNEL_TYPE_GENEVE:
8610         case RTE_TUNNEL_TYPE_TEREDO:
8611                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8612                 ret = -1;
8613                 break;
8614         default:
8615                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8616                 ret = -1;
8617                 break;
8618         }
8619
8620         return ret;
8621 }
8622
8623 /* Calculate the maximum number of contiguous PF queues that are configured */
8624 static int
8625 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8626 {
8627         struct rte_eth_dev_data *data = pf->dev_data;
8628         int i, num;
8629         struct i40e_rx_queue *rxq;
8630
8631         num = 0;
8632         for (i = 0; i < pf->lan_nb_qps; i++) {
8633                 rxq = data->rx_queues[i];
8634                 if (rxq && rxq->q_set)
8635                         num++;
8636                 else
8637                         break;
8638         }
8639
8640         return num;
8641 }
8642
8643 /* Configure RSS */
8644 static int
8645 i40e_pf_config_rss(struct i40e_pf *pf)
8646 {
8647         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8648         struct rte_eth_rss_conf rss_conf;
8649         uint32_t i, lut = 0;
8650         uint16_t j, num;
8651
8652         /*
8653          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8654          * It's necessary to calculate the actual PF queues that are configured.
8655          */
8656         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8657                 num = i40e_pf_calc_configured_queues_num(pf);
8658         else
8659                 num = pf->dev_data->nb_rx_queues;
8660
8661         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8662         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8663                         num);
8664
8665         if (num == 0) {
8666                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8667                 return -ENOTSUP;
8668         }
8669
8670         if (pf->adapter->rss_reta_updated == 0) {
8671                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8672                         if (j == num)
8673                                 j = 0;
8674                         lut = (lut << 8) | (j & ((0x1 <<
8675                                 hw->func_caps.rss_table_entry_width) - 1));
8676                         if ((i & 3) == 3)
8677                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8678                                                rte_bswap32(lut));
8679                 }
8680         }
8681
8682         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8683         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8684                 i40e_pf_disable_rss(pf);
8685                 return 0;
8686         }
8687         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8688                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8689                 /* Random default keys */
8690                 static uint32_t rss_key_default[] = {0x6b793944,
8691                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8692                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8693                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8694
8695                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8696                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8697                                                         sizeof(uint32_t);
8698         }
8699
8700         return i40e_hw_rss_hash_set(pf, &rss_conf);
8701 }
8702
8703 static int
8704 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8705                                struct rte_eth_tunnel_filter_conf *filter)
8706 {
8707         if (pf == NULL || filter == NULL) {
8708                 PMD_DRV_LOG(ERR, "Invalid parameter");
8709                 return -EINVAL;
8710         }
8711
8712         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8713                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8714                 return -EINVAL;
8715         }
8716
8717         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8718                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8719                 return -EINVAL;
8720         }
8721
8722         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8723                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8724                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8725                 return -EINVAL;
8726         }
8727
8728         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8729                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8730                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8731                 return -EINVAL;
8732         }
8733
8734         return 0;
8735 }
8736
8737 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8738 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8739 static int
8740 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8741 {
8742         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8743         uint32_t val, reg;
8744         int ret = -EINVAL;
8745
8746         if (pf->support_multi_driver) {
8747                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8748                 return -ENOTSUP;
8749         }
8750
8751         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8752         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8753
8754         if (len == 3) {
8755                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8756         } else if (len == 4) {
8757                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8758         } else {
8759                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8760                 return ret;
8761         }
8762
8763         if (reg != val) {
8764                 ret = i40e_aq_debug_write_global_register(hw,
8765                                                    I40E_GL_PRS_FVBM(2),
8766                                                    reg, NULL);
8767                 if (ret != 0)
8768                         return ret;
8769                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8770                             "with value 0x%08x",
8771                             I40E_GL_PRS_FVBM(2), reg);
8772         } else {
8773                 ret = 0;
8774         }
8775         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8776                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8777
8778         return ret;
8779 }
8780
8781 static int
8782 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8783 {
8784         int ret = -EINVAL;
8785
8786         if (!hw || !cfg)
8787                 return -EINVAL;
8788
8789         switch (cfg->cfg_type) {
8790         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8791                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8792                 break;
8793         default:
8794                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8795                 break;
8796         }
8797
8798         return ret;
8799 }
8800
8801 static int
8802 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8803                                enum rte_filter_op filter_op,
8804                                void *arg)
8805 {
8806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8807         int ret = I40E_ERR_PARAM;
8808
8809         switch (filter_op) {
8810         case RTE_ETH_FILTER_SET:
8811                 ret = i40e_dev_global_config_set(hw,
8812                         (struct rte_eth_global_cfg *)arg);
8813                 break;
8814         default:
8815                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8816                 break;
8817         }
8818
8819         return ret;
8820 }
8821
8822 static int
8823 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8824                           enum rte_filter_op filter_op,
8825                           void *arg)
8826 {
8827         struct rte_eth_tunnel_filter_conf *filter;
8828         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8829         int ret = I40E_SUCCESS;
8830
8831         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8832
8833         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8834                 return I40E_ERR_PARAM;
8835
8836         switch (filter_op) {
8837         case RTE_ETH_FILTER_NOP:
8838                 if (!(pf->flags & I40E_FLAG_VXLAN))
8839                         ret = I40E_NOT_SUPPORTED;
8840                 break;
8841         case RTE_ETH_FILTER_ADD:
8842                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8843                 break;
8844         case RTE_ETH_FILTER_DELETE:
8845                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8846                 break;
8847         default:
8848                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8849                 ret = I40E_ERR_PARAM;
8850                 break;
8851         }
8852
8853         return ret;
8854 }
8855
8856 static int
8857 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8858 {
8859         int ret = 0;
8860         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8861
8862         /* RSS setup */
8863         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8864                 ret = i40e_pf_config_rss(pf);
8865         else
8866                 i40e_pf_disable_rss(pf);
8867
8868         return ret;
8869 }
8870
8871 /* Get the symmetric hash enable configurations per port */
8872 static void
8873 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8874 {
8875         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8876
8877         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8878 }
8879
8880 /* Set the symmetric hash enable configurations per port */
8881 static void
8882 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8883 {
8884         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8885
8886         if (enable > 0) {
8887                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8888                         PMD_DRV_LOG(INFO,
8889                                 "Symmetric hash has already been enabled");
8890                         return;
8891                 }
8892                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8893         } else {
8894                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8895                         PMD_DRV_LOG(INFO,
8896                                 "Symmetric hash has already been disabled");
8897                         return;
8898                 }
8899                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8900         }
8901         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8902         I40E_WRITE_FLUSH(hw);
8903 }
8904
8905 /*
8906  * Get global configurations of hash function type and symmetric hash enable
8907  * per flow type (pctype). Note that global configuration means it affects all
8908  * the ports on the same NIC.
8909  */
8910 static int
8911 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8912                                    struct rte_eth_hash_global_conf *g_cfg)
8913 {
8914         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8915         uint32_t reg;
8916         uint16_t i, j;
8917
8918         memset(g_cfg, 0, sizeof(*g_cfg));
8919         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8920         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8921                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8922         else
8923                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8924         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8925                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8926
8927         /*
8928          * As i40e supports less than 64 flow types, only first 64 bits need to
8929          * be checked.
8930          */
8931         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8932                 g_cfg->valid_bit_mask[i] = 0ULL;
8933                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8934         }
8935
8936         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8937
8938         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8939                 if (!adapter->pctypes_tbl[i])
8940                         continue;
8941                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8942                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8943                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8944                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8945                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8946                                         g_cfg->sym_hash_enable_mask[0] |=
8947                                                                 (1ULL << i);
8948                                 }
8949                         }
8950                 }
8951         }
8952
8953         return 0;
8954 }
8955
8956 static int
8957 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8958                               const struct rte_eth_hash_global_conf *g_cfg)
8959 {
8960         uint32_t i;
8961         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8962
8963         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8964                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8965                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8966                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8967                                                 g_cfg->hash_func);
8968                 return -EINVAL;
8969         }
8970
8971         /*
8972          * As i40e supports less than 64 flow types, only first 64 bits need to
8973          * be checked.
8974          */
8975         mask0 = g_cfg->valid_bit_mask[0];
8976         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8977                 if (i == 0) {
8978                         /* Check if any unsupported flow type configured */
8979                         if ((mask0 | i40e_mask) ^ i40e_mask)
8980                                 goto mask_err;
8981                 } else {
8982                         if (g_cfg->valid_bit_mask[i])
8983                                 goto mask_err;
8984                 }
8985         }
8986
8987         return 0;
8988
8989 mask_err:
8990         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8991
8992         return -EINVAL;
8993 }
8994
8995 /*
8996  * Set global configurations of hash function type and symmetric hash enable
8997  * per flow type (pctype). Note any modifying global configuration will affect
8998  * all the ports on the same NIC.
8999  */
9000 static int
9001 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9002                                    struct rte_eth_hash_global_conf *g_cfg)
9003 {
9004         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9005         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9006         int ret;
9007         uint16_t i, j;
9008         uint32_t reg;
9009         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9010
9011         if (pf->support_multi_driver) {
9012                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9013                 return -ENOTSUP;
9014         }
9015
9016         /* Check the input parameters */
9017         ret = i40e_hash_global_config_check(adapter, g_cfg);
9018         if (ret < 0)
9019                 return ret;
9020
9021         /*
9022          * As i40e supports less than 64 flow types, only first 64 bits need to
9023          * be configured.
9024          */
9025         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9026                 if (mask0 & (1UL << i)) {
9027                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9028                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9029
9030                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9031                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9032                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9033                                         i40e_write_global_rx_ctl(hw,
9034                                                           I40E_GLQF_HSYM(j),
9035                                                           reg);
9036                         }
9037                 }
9038         }
9039
9040         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9041         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9042                 /* Toeplitz */
9043                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9044                         PMD_DRV_LOG(DEBUG,
9045                                 "Hash function already set to Toeplitz");
9046                         goto out;
9047                 }
9048                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9049         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9050                 /* Simple XOR */
9051                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9052                         PMD_DRV_LOG(DEBUG,
9053                                 "Hash function already set to Simple XOR");
9054                         goto out;
9055                 }
9056                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9057         } else
9058                 /* Use the default, and keep it as it is */
9059                 goto out;
9060
9061         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9062
9063 out:
9064         I40E_WRITE_FLUSH(hw);
9065
9066         return 0;
9067 }
9068
9069 /**
9070  * Valid input sets for hash and flow director filters per PCTYPE
9071  */
9072 static uint64_t
9073 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9074                 enum rte_filter_type filter)
9075 {
9076         uint64_t valid;
9077
9078         static const uint64_t valid_hash_inset_table[] = {
9079                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9080                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9081                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9082                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9083                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9084                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9085                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9086                         I40E_INSET_FLEX_PAYLOAD,
9087                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9088                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9089                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9091                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9092                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9093                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9094                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9095                         I40E_INSET_FLEX_PAYLOAD,
9096                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9100                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9101                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9102                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9103                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9104                         I40E_INSET_FLEX_PAYLOAD,
9105                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9109                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9110                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9111                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9112                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9113                         I40E_INSET_FLEX_PAYLOAD,
9114                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9118                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9119                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9120                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9122                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9123                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9127                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9128                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9129                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9130                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9131                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9132                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9138                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9139                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9140                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9141                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9145                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9146                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9147                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148                         I40E_INSET_FLEX_PAYLOAD,
9149                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9150                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9151                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9153                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9154                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9155                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9156                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9157                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9158                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9159                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9161                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9162                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9163                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9164                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9165                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9166                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9167                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9168                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9169                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9170                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9171                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9172                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9173                         I40E_INSET_FLEX_PAYLOAD,
9174                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9175                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9176                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9178                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9179                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9180                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9181                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9182                         I40E_INSET_FLEX_PAYLOAD,
9183                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9184                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9185                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9187                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9188                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9189                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9190                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9191                         I40E_INSET_FLEX_PAYLOAD,
9192                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9193                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9194                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9196                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9197                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9198                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9199                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9200                         I40E_INSET_FLEX_PAYLOAD,
9201                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9202                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9203                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9204                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9205                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9206                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9207                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9208                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9209                         I40E_INSET_FLEX_PAYLOAD,
9210                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9211                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9212                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9214                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9215                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9216                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9217                         I40E_INSET_FLEX_PAYLOAD,
9218                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9219                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9220                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9221                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9222                         I40E_INSET_FLEX_PAYLOAD,
9223         };
9224
9225         /**
9226          * Flow director supports only fields defined in
9227          * union rte_eth_fdir_flow.
9228          */
9229         static const uint64_t valid_fdir_inset_table[] = {
9230                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9231                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9232                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9233                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9234                 I40E_INSET_IPV4_TTL,
9235                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9236                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9237                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9238                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9239                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9240                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9241                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9242                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9243                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9244                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9245                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9246                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9247                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9248                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9249                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9250                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9251                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9254                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9259                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9264                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9265                 I40E_INSET_SCTP_VT,
9266                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9267                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9268                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9269                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9270                 I40E_INSET_IPV4_TTL,
9271                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9274                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9275                 I40E_INSET_IPV6_HOP_LIMIT,
9276                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9283                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9284                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9288                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9291                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9293                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9304                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9305                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9306                 I40E_INSET_SCTP_VT,
9307                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9308                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9309                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9310                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9311                 I40E_INSET_IPV6_HOP_LIMIT,
9312                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9314                 I40E_INSET_LAST_ETHER_TYPE,
9315         };
9316
9317         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9318                 return 0;
9319         if (filter == RTE_ETH_FILTER_HASH)
9320                 valid = valid_hash_inset_table[pctype];
9321         else
9322                 valid = valid_fdir_inset_table[pctype];
9323
9324         return valid;
9325 }
9326
9327 /**
9328  * Validate if the input set is allowed for a specific PCTYPE
9329  */
9330 int
9331 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9332                 enum rte_filter_type filter, uint64_t inset)
9333 {
9334         uint64_t valid;
9335
9336         valid = i40e_get_valid_input_set(pctype, filter);
9337         if (inset & (~valid))
9338                 return -EINVAL;
9339
9340         return 0;
9341 }
9342
9343 /* default input set fields combination per pctype */
9344 uint64_t
9345 i40e_get_default_input_set(uint16_t pctype)
9346 {
9347         static const uint64_t default_inset_table[] = {
9348                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9349                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9350                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9351                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9352                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9353                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9354                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9355                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9356                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9357                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9358                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9359                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9360                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9361                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9362                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9363                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9364                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9365                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9366                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9367                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9368                         I40E_INSET_SCTP_VT,
9369                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9370                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9371                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9372                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9373                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9374                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9375                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9376                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9377                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9378                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9379                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9380                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9381                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9382                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9383                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9385                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9386                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9387                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9388                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9389                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9390                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9391                         I40E_INSET_SCTP_VT,
9392                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9393                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9394                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9395                         I40E_INSET_LAST_ETHER_TYPE,
9396         };
9397
9398         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9399                 return 0;
9400
9401         return default_inset_table[pctype];
9402 }
9403
9404 /**
9405  * Parse the input set from index to logical bit masks
9406  */
9407 static int
9408 i40e_parse_input_set(uint64_t *inset,
9409                      enum i40e_filter_pctype pctype,
9410                      enum rte_eth_input_set_field *field,
9411                      uint16_t size)
9412 {
9413         uint16_t i, j;
9414         int ret = -EINVAL;
9415
9416         static const struct {
9417                 enum rte_eth_input_set_field field;
9418                 uint64_t inset;
9419         } inset_convert_table[] = {
9420                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9421                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9422                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9423                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9424                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9425                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9426                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9427                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9428                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9429                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9430                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9431                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9432                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9433                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9434                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9435                         I40E_INSET_IPV6_NEXT_HDR},
9436                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9437                         I40E_INSET_IPV6_HOP_LIMIT},
9438                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9439                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9440                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9441                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9442                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9443                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9444                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9445                         I40E_INSET_SCTP_VT},
9446                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9447                         I40E_INSET_TUNNEL_DMAC},
9448                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9449                         I40E_INSET_VLAN_TUNNEL},
9450                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9451                         I40E_INSET_TUNNEL_ID},
9452                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9453                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9454                         I40E_INSET_FLEX_PAYLOAD_W1},
9455                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9456                         I40E_INSET_FLEX_PAYLOAD_W2},
9457                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9458                         I40E_INSET_FLEX_PAYLOAD_W3},
9459                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9460                         I40E_INSET_FLEX_PAYLOAD_W4},
9461                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9462                         I40E_INSET_FLEX_PAYLOAD_W5},
9463                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9464                         I40E_INSET_FLEX_PAYLOAD_W6},
9465                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9466                         I40E_INSET_FLEX_PAYLOAD_W7},
9467                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9468                         I40E_INSET_FLEX_PAYLOAD_W8},
9469         };
9470
9471         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9472                 return ret;
9473
9474         /* Only one item allowed for default or all */
9475         if (size == 1) {
9476                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9477                         *inset = i40e_get_default_input_set(pctype);
9478                         return 0;
9479                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9480                         *inset = I40E_INSET_NONE;
9481                         return 0;
9482                 }
9483         }
9484
9485         for (i = 0, *inset = 0; i < size; i++) {
9486                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9487                         if (field[i] == inset_convert_table[j].field) {
9488                                 *inset |= inset_convert_table[j].inset;
9489                                 break;
9490                         }
9491                 }
9492
9493                 /* It contains unsupported input set, return immediately */
9494                 if (j == RTE_DIM(inset_convert_table))
9495                         return ret;
9496         }
9497
9498         return 0;
9499 }
9500
9501 /**
9502  * Translate the input set from bit masks to register aware bit masks
9503  * and vice versa
9504  */
9505 uint64_t
9506 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9507 {
9508         uint64_t val = 0;
9509         uint16_t i;
9510
9511         struct inset_map {
9512                 uint64_t inset;
9513                 uint64_t inset_reg;
9514         };
9515
9516         static const struct inset_map inset_map_common[] = {
9517                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9518                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9519                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9520                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9521                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9522                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9523                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9524                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9525                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9526                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9527                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9528                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9529                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9530                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9531                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9532                 {I40E_INSET_TUNNEL_DMAC,
9533                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9534                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9535                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9536                 {I40E_INSET_TUNNEL_SRC_PORT,
9537                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9538                 {I40E_INSET_TUNNEL_DST_PORT,
9539                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9540                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9541                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9542                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9543                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9544                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9545                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9546                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9547                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9548                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9549         };
9550
9551     /* some different registers map in x722*/
9552         static const struct inset_map inset_map_diff_x722[] = {
9553                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9554                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9555                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9556                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9557         };
9558
9559         static const struct inset_map inset_map_diff_not_x722[] = {
9560                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9561                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9562                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9563                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9564         };
9565
9566         if (input == 0)
9567                 return val;
9568
9569         /* Translate input set to register aware inset */
9570         if (type == I40E_MAC_X722) {
9571                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9572                         if (input & inset_map_diff_x722[i].inset)
9573                                 val |= inset_map_diff_x722[i].inset_reg;
9574                 }
9575         } else {
9576                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9577                         if (input & inset_map_diff_not_x722[i].inset)
9578                                 val |= inset_map_diff_not_x722[i].inset_reg;
9579                 }
9580         }
9581
9582         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9583                 if (input & inset_map_common[i].inset)
9584                         val |= inset_map_common[i].inset_reg;
9585         }
9586
9587         return val;
9588 }
9589
9590 int
9591 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9592 {
9593         uint8_t i, idx = 0;
9594         uint64_t inset_need_mask = inset;
9595
9596         static const struct {
9597                 uint64_t inset;
9598                 uint32_t mask;
9599         } inset_mask_map[] = {
9600                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9601                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9602                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9603                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9604                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9605                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9606                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9607                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9608         };
9609
9610         if (!inset || !mask || !nb_elem)
9611                 return 0;
9612
9613         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9614                 /* Clear the inset bit, if no MASK is required,
9615                  * for example proto + ttl
9616                  */
9617                 if ((inset & inset_mask_map[i].inset) ==
9618                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9619                         inset_need_mask &= ~inset_mask_map[i].inset;
9620                 if (!inset_need_mask)
9621                         return 0;
9622         }
9623         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9624                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9625                     inset_mask_map[i].inset) {
9626                         if (idx >= nb_elem) {
9627                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9628                                 return -EINVAL;
9629                         }
9630                         mask[idx] = inset_mask_map[i].mask;
9631                         idx++;
9632                 }
9633         }
9634
9635         return idx;
9636 }
9637
9638 void
9639 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9640 {
9641         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9642
9643         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9644         if (reg != val)
9645                 i40e_write_rx_ctl(hw, addr, val);
9646         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9647                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9648 }
9649
9650 void
9651 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9652 {
9653         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9654         struct rte_eth_dev *dev;
9655
9656         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9657         if (reg != val) {
9658                 i40e_write_rx_ctl(hw, addr, val);
9659                 PMD_DRV_LOG(WARNING,
9660                             "i40e device %s changed global register [0x%08x]."
9661                             " original: 0x%08x, new: 0x%08x",
9662                             dev->device->name, addr, reg,
9663                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9664         }
9665 }
9666
9667 static void
9668 i40e_filter_input_set_init(struct i40e_pf *pf)
9669 {
9670         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9671         enum i40e_filter_pctype pctype;
9672         uint64_t input_set, inset_reg;
9673         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9674         int num, i;
9675         uint16_t flow_type;
9676
9677         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9678              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9679                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9680
9681                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9682                         continue;
9683
9684                 input_set = i40e_get_default_input_set(pctype);
9685
9686                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9687                                                    I40E_INSET_MASK_NUM_REG);
9688                 if (num < 0)
9689                         return;
9690                 if (pf->support_multi_driver && num > 0) {
9691                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9692                         return;
9693                 }
9694                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9695                                         input_set);
9696
9697                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9698                                       (uint32_t)(inset_reg & UINT32_MAX));
9699                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9700                                      (uint32_t)((inset_reg >>
9701                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9702                 if (!pf->support_multi_driver) {
9703                         i40e_check_write_global_reg(hw,
9704                                             I40E_GLQF_HASH_INSET(0, pctype),
9705                                             (uint32_t)(inset_reg & UINT32_MAX));
9706                         i40e_check_write_global_reg(hw,
9707                                              I40E_GLQF_HASH_INSET(1, pctype),
9708                                              (uint32_t)((inset_reg >>
9709                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9710
9711                         for (i = 0; i < num; i++) {
9712                                 i40e_check_write_global_reg(hw,
9713                                                     I40E_GLQF_FD_MSK(i, pctype),
9714                                                     mask_reg[i]);
9715                                 i40e_check_write_global_reg(hw,
9716                                                   I40E_GLQF_HASH_MSK(i, pctype),
9717                                                   mask_reg[i]);
9718                         }
9719                         /*clear unused mask registers of the pctype */
9720                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9721                                 i40e_check_write_global_reg(hw,
9722                                                     I40E_GLQF_FD_MSK(i, pctype),
9723                                                     0);
9724                                 i40e_check_write_global_reg(hw,
9725                                                   I40E_GLQF_HASH_MSK(i, pctype),
9726                                                   0);
9727                         }
9728                 } else {
9729                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9730                 }
9731                 I40E_WRITE_FLUSH(hw);
9732
9733                 /* store the default input set */
9734                 if (!pf->support_multi_driver)
9735                         pf->hash_input_set[pctype] = input_set;
9736                 pf->fdir.input_set[pctype] = input_set;
9737         }
9738 }
9739
9740 int
9741 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9742                          struct rte_eth_input_set_conf *conf)
9743 {
9744         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9745         enum i40e_filter_pctype pctype;
9746         uint64_t input_set, inset_reg = 0;
9747         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9748         int ret, i, num;
9749
9750         if (!conf) {
9751                 PMD_DRV_LOG(ERR, "Invalid pointer");
9752                 return -EFAULT;
9753         }
9754         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9755             conf->op != RTE_ETH_INPUT_SET_ADD) {
9756                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9757                 return -EINVAL;
9758         }
9759
9760         if (pf->support_multi_driver) {
9761                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9762                 return -ENOTSUP;
9763         }
9764
9765         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9766         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9767                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9768                 return -EINVAL;
9769         }
9770
9771         if (hw->mac.type == I40E_MAC_X722) {
9772                 /* get translated pctype value in fd pctype register */
9773                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9774                         I40E_GLQF_FD_PCTYPES((int)pctype));
9775         }
9776
9777         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9778                                    conf->inset_size);
9779         if (ret) {
9780                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9781                 return -EINVAL;
9782         }
9783
9784         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9785                 /* get inset value in register */
9786                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9787                 inset_reg <<= I40E_32_BIT_WIDTH;
9788                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9789                 input_set |= pf->hash_input_set[pctype];
9790         }
9791         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9792                                            I40E_INSET_MASK_NUM_REG);
9793         if (num < 0)
9794                 return -EINVAL;
9795
9796         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9797
9798         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9799                                     (uint32_t)(inset_reg & UINT32_MAX));
9800         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9801                                     (uint32_t)((inset_reg >>
9802                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9803
9804         for (i = 0; i < num; i++)
9805                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9806                                             mask_reg[i]);
9807         /*clear unused mask registers of the pctype */
9808         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9809                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9810                                             0);
9811         I40E_WRITE_FLUSH(hw);
9812
9813         pf->hash_input_set[pctype] = input_set;
9814         return 0;
9815 }
9816
9817 int
9818 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9819                          struct rte_eth_input_set_conf *conf)
9820 {
9821         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9822         enum i40e_filter_pctype pctype;
9823         uint64_t input_set, inset_reg = 0;
9824         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9825         int ret, i, num;
9826
9827         if (!hw || !conf) {
9828                 PMD_DRV_LOG(ERR, "Invalid pointer");
9829                 return -EFAULT;
9830         }
9831         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9832             conf->op != RTE_ETH_INPUT_SET_ADD) {
9833                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9834                 return -EINVAL;
9835         }
9836
9837         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9838
9839         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9840                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9841                 return -EINVAL;
9842         }
9843
9844         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9845                                    conf->inset_size);
9846         if (ret) {
9847                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9848                 return -EINVAL;
9849         }
9850
9851         /* get inset value in register */
9852         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9853         inset_reg <<= I40E_32_BIT_WIDTH;
9854         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9855
9856         /* Can not change the inset reg for flex payload for fdir,
9857          * it is done by writing I40E_PRTQF_FD_FLXINSET
9858          * in i40e_set_flex_mask_on_pctype.
9859          */
9860         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9861                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9862         else
9863                 input_set |= pf->fdir.input_set[pctype];
9864         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9865                                            I40E_INSET_MASK_NUM_REG);
9866         if (num < 0)
9867                 return -EINVAL;
9868         if (pf->support_multi_driver && num > 0) {
9869                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9870                 return -ENOTSUP;
9871         }
9872
9873         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9874
9875         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9876                               (uint32_t)(inset_reg & UINT32_MAX));
9877         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9878                              (uint32_t)((inset_reg >>
9879                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9880
9881         if (!pf->support_multi_driver) {
9882                 for (i = 0; i < num; i++)
9883                         i40e_check_write_global_reg(hw,
9884                                                     I40E_GLQF_FD_MSK(i, pctype),
9885                                                     mask_reg[i]);
9886                 /*clear unused mask registers of the pctype */
9887                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9888                         i40e_check_write_global_reg(hw,
9889                                                     I40E_GLQF_FD_MSK(i, pctype),
9890                                                     0);
9891         } else {
9892                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9893         }
9894         I40E_WRITE_FLUSH(hw);
9895
9896         pf->fdir.input_set[pctype] = input_set;
9897         return 0;
9898 }
9899
9900 static int
9901 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9902 {
9903         int ret = 0;
9904
9905         if (!hw || !info) {
9906                 PMD_DRV_LOG(ERR, "Invalid pointer");
9907                 return -EFAULT;
9908         }
9909
9910         switch (info->info_type) {
9911         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9912                 i40e_get_symmetric_hash_enable_per_port(hw,
9913                                         &(info->info.enable));
9914                 break;
9915         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9916                 ret = i40e_get_hash_filter_global_config(hw,
9917                                 &(info->info.global_conf));
9918                 break;
9919         default:
9920                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9921                                                         info->info_type);
9922                 ret = -EINVAL;
9923                 break;
9924         }
9925
9926         return ret;
9927 }
9928
9929 static int
9930 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9931 {
9932         int ret = 0;
9933
9934         if (!hw || !info) {
9935                 PMD_DRV_LOG(ERR, "Invalid pointer");
9936                 return -EFAULT;
9937         }
9938
9939         switch (info->info_type) {
9940         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9941                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9942                 break;
9943         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9944                 ret = i40e_set_hash_filter_global_config(hw,
9945                                 &(info->info.global_conf));
9946                 break;
9947         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9948                 ret = i40e_hash_filter_inset_select(hw,
9949                                                &(info->info.input_set_conf));
9950                 break;
9951
9952         default:
9953                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9954                                                         info->info_type);
9955                 ret = -EINVAL;
9956                 break;
9957         }
9958
9959         return ret;
9960 }
9961
9962 /* Operations for hash function */
9963 static int
9964 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9965                       enum rte_filter_op filter_op,
9966                       void *arg)
9967 {
9968         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9969         int ret = 0;
9970
9971         switch (filter_op) {
9972         case RTE_ETH_FILTER_NOP:
9973                 break;
9974         case RTE_ETH_FILTER_GET:
9975                 ret = i40e_hash_filter_get(hw,
9976                         (struct rte_eth_hash_filter_info *)arg);
9977                 break;
9978         case RTE_ETH_FILTER_SET:
9979                 ret = i40e_hash_filter_set(hw,
9980                         (struct rte_eth_hash_filter_info *)arg);
9981                 break;
9982         default:
9983                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9984                                                                 filter_op);
9985                 ret = -ENOTSUP;
9986                 break;
9987         }
9988
9989         return ret;
9990 }
9991
9992 /* Convert ethertype filter structure */
9993 static int
9994 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9995                               struct i40e_ethertype_filter *filter)
9996 {
9997         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9998                 RTE_ETHER_ADDR_LEN);
9999         filter->input.ether_type = input->ether_type;
10000         filter->flags = input->flags;
10001         filter->queue = input->queue;
10002
10003         return 0;
10004 }
10005
10006 /* Check if there exists the ehtertype filter */
10007 struct i40e_ethertype_filter *
10008 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10009                                 const struct i40e_ethertype_filter_input *input)
10010 {
10011         int ret;
10012
10013         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10014         if (ret < 0)
10015                 return NULL;
10016
10017         return ethertype_rule->hash_map[ret];
10018 }
10019
10020 /* Add ethertype filter in SW list */
10021 static int
10022 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10023                                 struct i40e_ethertype_filter *filter)
10024 {
10025         struct i40e_ethertype_rule *rule = &pf->ethertype;
10026         int ret;
10027
10028         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10029         if (ret < 0) {
10030                 PMD_DRV_LOG(ERR,
10031                             "Failed to insert ethertype filter"
10032                             " to hash table %d!",
10033                             ret);
10034                 return ret;
10035         }
10036         rule->hash_map[ret] = filter;
10037
10038         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10039
10040         return 0;
10041 }
10042
10043 /* Delete ethertype filter in SW list */
10044 int
10045 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10046                              struct i40e_ethertype_filter_input *input)
10047 {
10048         struct i40e_ethertype_rule *rule = &pf->ethertype;
10049         struct i40e_ethertype_filter *filter;
10050         int ret;
10051
10052         ret = rte_hash_del_key(rule->hash_table, input);
10053         if (ret < 0) {
10054                 PMD_DRV_LOG(ERR,
10055                             "Failed to delete ethertype filter"
10056                             " to hash table %d!",
10057                             ret);
10058                 return ret;
10059         }
10060         filter = rule->hash_map[ret];
10061         rule->hash_map[ret] = NULL;
10062
10063         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10064         rte_free(filter);
10065
10066         return 0;
10067 }
10068
10069 /*
10070  * Configure ethertype filter, which can director packet by filtering
10071  * with mac address and ether_type or only ether_type
10072  */
10073 int
10074 i40e_ethertype_filter_set(struct i40e_pf *pf,
10075                         struct rte_eth_ethertype_filter *filter,
10076                         bool add)
10077 {
10078         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10079         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10080         struct i40e_ethertype_filter *ethertype_filter, *node;
10081         struct i40e_ethertype_filter check_filter;
10082         struct i40e_control_filter_stats stats;
10083         uint16_t flags = 0;
10084         int ret;
10085
10086         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10087                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10088                 return -EINVAL;
10089         }
10090         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10091                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10092                 PMD_DRV_LOG(ERR,
10093                         "unsupported ether_type(0x%04x) in control packet filter.",
10094                         filter->ether_type);
10095                 return -EINVAL;
10096         }
10097         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10098                 PMD_DRV_LOG(WARNING,
10099                         "filter vlan ether_type in first tag is not supported.");
10100
10101         /* Check if there is the filter in SW list */
10102         memset(&check_filter, 0, sizeof(check_filter));
10103         i40e_ethertype_filter_convert(filter, &check_filter);
10104         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10105                                                &check_filter.input);
10106         if (add && node) {
10107                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10108                 return -EINVAL;
10109         }
10110
10111         if (!add && !node) {
10112                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10113                 return -EINVAL;
10114         }
10115
10116         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10117                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10118         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10119                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10120         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10121
10122         memset(&stats, 0, sizeof(stats));
10123         ret = i40e_aq_add_rem_control_packet_filter(hw,
10124                         filter->mac_addr.addr_bytes,
10125                         filter->ether_type, flags,
10126                         pf->main_vsi->seid,
10127                         filter->queue, add, &stats, NULL);
10128
10129         PMD_DRV_LOG(INFO,
10130                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10131                 ret, stats.mac_etype_used, stats.etype_used,
10132                 stats.mac_etype_free, stats.etype_free);
10133         if (ret < 0)
10134                 return -ENOSYS;
10135
10136         /* Add or delete a filter in SW list */
10137         if (add) {
10138                 ethertype_filter = rte_zmalloc("ethertype_filter",
10139                                        sizeof(*ethertype_filter), 0);
10140                 if (ethertype_filter == NULL) {
10141                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10142                         return -ENOMEM;
10143                 }
10144
10145                 rte_memcpy(ethertype_filter, &check_filter,
10146                            sizeof(check_filter));
10147                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10148                 if (ret < 0)
10149                         rte_free(ethertype_filter);
10150         } else {
10151                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10152         }
10153
10154         return ret;
10155 }
10156
10157 /*
10158  * Handle operations for ethertype filter.
10159  */
10160 static int
10161 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10162                                 enum rte_filter_op filter_op,
10163                                 void *arg)
10164 {
10165         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10166         int ret = 0;
10167
10168         if (filter_op == RTE_ETH_FILTER_NOP)
10169                 return ret;
10170
10171         if (arg == NULL) {
10172                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10173                             filter_op);
10174                 return -EINVAL;
10175         }
10176
10177         switch (filter_op) {
10178         case RTE_ETH_FILTER_ADD:
10179                 ret = i40e_ethertype_filter_set(pf,
10180                         (struct rte_eth_ethertype_filter *)arg,
10181                         TRUE);
10182                 break;
10183         case RTE_ETH_FILTER_DELETE:
10184                 ret = i40e_ethertype_filter_set(pf,
10185                         (struct rte_eth_ethertype_filter *)arg,
10186                         FALSE);
10187                 break;
10188         default:
10189                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10190                 ret = -ENOSYS;
10191                 break;
10192         }
10193         return ret;
10194 }
10195
10196 static int
10197 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10198                      enum rte_filter_type filter_type,
10199                      enum rte_filter_op filter_op,
10200                      void *arg)
10201 {
10202         int ret = 0;
10203
10204         if (dev == NULL)
10205                 return -EINVAL;
10206
10207         switch (filter_type) {
10208         case RTE_ETH_FILTER_NONE:
10209                 /* For global configuration */
10210                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10211                 break;
10212         case RTE_ETH_FILTER_HASH:
10213                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10214                 break;
10215         case RTE_ETH_FILTER_MACVLAN:
10216                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10217                 break;
10218         case RTE_ETH_FILTER_ETHERTYPE:
10219                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10220                 break;
10221         case RTE_ETH_FILTER_TUNNEL:
10222                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10223                 break;
10224         case RTE_ETH_FILTER_FDIR:
10225                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10226                 break;
10227         case RTE_ETH_FILTER_GENERIC:
10228                 if (filter_op != RTE_ETH_FILTER_GET)
10229                         return -EINVAL;
10230                 *(const void **)arg = &i40e_flow_ops;
10231                 break;
10232         default:
10233                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10234                                                         filter_type);
10235                 ret = -EINVAL;
10236                 break;
10237         }
10238
10239         return ret;
10240 }
10241
10242 /*
10243  * Check and enable Extended Tag.
10244  * Enabling Extended Tag is important for 40G performance.
10245  */
10246 static void
10247 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10248 {
10249         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10250         uint32_t buf = 0;
10251         int ret;
10252
10253         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10254                                       PCI_DEV_CAP_REG);
10255         if (ret < 0) {
10256                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10257                             PCI_DEV_CAP_REG);
10258                 return;
10259         }
10260         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10261                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10262                 return;
10263         }
10264
10265         buf = 0;
10266         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10267                                       PCI_DEV_CTRL_REG);
10268         if (ret < 0) {
10269                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10270                             PCI_DEV_CTRL_REG);
10271                 return;
10272         }
10273         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10274                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10275                 return;
10276         }
10277         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10278         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10279                                        PCI_DEV_CTRL_REG);
10280         if (ret < 0) {
10281                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10282                             PCI_DEV_CTRL_REG);
10283                 return;
10284         }
10285 }
10286
10287 /*
10288  * As some registers wouldn't be reset unless a global hardware reset,
10289  * hardware initialization is needed to put those registers into an
10290  * expected initial state.
10291  */
10292 static void
10293 i40e_hw_init(struct rte_eth_dev *dev)
10294 {
10295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10296
10297         i40e_enable_extended_tag(dev);
10298
10299         /* clear the PF Queue Filter control register */
10300         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10301
10302         /* Disable symmetric hash per port */
10303         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10304 }
10305
10306 /*
10307  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10308  * however this function will return only one highest pctype index,
10309  * which is not quite correct. This is known problem of i40e driver
10310  * and needs to be fixed later.
10311  */
10312 enum i40e_filter_pctype
10313 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10314 {
10315         int i;
10316         uint64_t pctype_mask;
10317
10318         if (flow_type < I40E_FLOW_TYPE_MAX) {
10319                 pctype_mask = adapter->pctypes_tbl[flow_type];
10320                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10321                         if (pctype_mask & (1ULL << i))
10322                                 return (enum i40e_filter_pctype)i;
10323                 }
10324         }
10325         return I40E_FILTER_PCTYPE_INVALID;
10326 }
10327
10328 uint16_t
10329 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10330                         enum i40e_filter_pctype pctype)
10331 {
10332         uint16_t flowtype;
10333         uint64_t pctype_mask = 1ULL << pctype;
10334
10335         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10336              flowtype++) {
10337                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10338                         return flowtype;
10339         }
10340
10341         return RTE_ETH_FLOW_UNKNOWN;
10342 }
10343
10344 /*
10345  * On X710, performance number is far from the expectation on recent firmware
10346  * versions; on XL710, performance number is also far from the expectation on
10347  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10348  * mode is enabled and port MAC address is equal to the packet destination MAC
10349  * address. The fix for this issue may not be integrated in the following
10350  * firmware version. So the workaround in software driver is needed. It needs
10351  * to modify the initial values of 3 internal only registers for both X710 and
10352  * XL710. Note that the values for X710 or XL710 could be different, and the
10353  * workaround can be removed when it is fixed in firmware in the future.
10354  */
10355
10356 /* For both X710 and XL710 */
10357 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10358 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10359 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10360
10361 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10362 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10363
10364 /* For X722 */
10365 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10366 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10367
10368 /* For X710 */
10369 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10370 /* For XL710 */
10371 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10372 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10373
10374 /*
10375  * GL_SWR_PM_UP_THR:
10376  * The value is not impacted from the link speed, its value is set according
10377  * to the total number of ports for a better pipe-monitor configuration.
10378  */
10379 static bool
10380 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10381 {
10382 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10383                 .device_id = (dev),   \
10384                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10385
10386 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10387                 .device_id = (dev),   \
10388                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10389
10390         static const struct {
10391                 uint16_t device_id;
10392                 uint32_t val;
10393         } swr_pm_table[] = {
10394                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10395                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10396                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10397                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10398
10399                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10400                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10401                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10402                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10403                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10404                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10405                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10406         };
10407         uint32_t i;
10408
10409         if (value == NULL) {
10410                 PMD_DRV_LOG(ERR, "value is NULL");
10411                 return false;
10412         }
10413
10414         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10415                 if (hw->device_id == swr_pm_table[i].device_id) {
10416                         *value = swr_pm_table[i].val;
10417
10418                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10419                                     "value - 0x%08x",
10420                                     hw->device_id, *value);
10421                         return true;
10422                 }
10423         }
10424
10425         return false;
10426 }
10427
10428 static int
10429 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10430 {
10431         enum i40e_status_code status;
10432         struct i40e_aq_get_phy_abilities_resp phy_ab;
10433         int ret = -ENOTSUP;
10434         int retries = 0;
10435
10436         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10437                                               NULL);
10438
10439         while (status) {
10440                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10441                         status);
10442                 retries++;
10443                 rte_delay_us(100000);
10444                 if  (retries < 5)
10445                         status = i40e_aq_get_phy_capabilities(hw, false,
10446                                         true, &phy_ab, NULL);
10447                 else
10448                         return ret;
10449         }
10450         return 0;
10451 }
10452
10453 static void
10454 i40e_configure_registers(struct i40e_hw *hw)
10455 {
10456         static struct {
10457                 uint32_t addr;
10458                 uint64_t val;
10459         } reg_table[] = {
10460                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10461                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10462                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10463         };
10464         uint64_t reg;
10465         uint32_t i;
10466         int ret;
10467
10468         for (i = 0; i < RTE_DIM(reg_table); i++) {
10469                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10470                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10471                                 reg_table[i].val =
10472                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10473                         else /* For X710/XL710/XXV710 */
10474                                 if (hw->aq.fw_maj_ver < 6)
10475                                         reg_table[i].val =
10476                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10477                                 else
10478                                         reg_table[i].val =
10479                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10480                 }
10481
10482                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10483                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10484                                 reg_table[i].val =
10485                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10486                         else /* For X710/XL710/XXV710 */
10487                                 reg_table[i].val =
10488                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10489                 }
10490
10491                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10492                         uint32_t cfg_val;
10493
10494                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10495                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10496                                             "GL_SWR_PM_UP_THR value fixup",
10497                                             hw->device_id);
10498                                 continue;
10499                         }
10500
10501                         reg_table[i].val = cfg_val;
10502                 }
10503
10504                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10505                                                         &reg, NULL);
10506                 if (ret < 0) {
10507                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10508                                                         reg_table[i].addr);
10509                         break;
10510                 }
10511                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10512                                                 reg_table[i].addr, reg);
10513                 if (reg == reg_table[i].val)
10514                         continue;
10515
10516                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10517                                                 reg_table[i].val, NULL);
10518                 if (ret < 0) {
10519                         PMD_DRV_LOG(ERR,
10520                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10521                                 reg_table[i].val, reg_table[i].addr);
10522                         break;
10523                 }
10524                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10525                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10526         }
10527 }
10528
10529 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10530 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10531 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10532 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10533 static int
10534 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10535 {
10536         uint32_t reg;
10537         int ret;
10538
10539         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10540                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10541                 return -EINVAL;
10542         }
10543
10544         /* Configure for double VLAN RX stripping */
10545         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10546         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10547                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10548                 ret = i40e_aq_debug_write_register(hw,
10549                                                    I40E_VSI_TSR(vsi->vsi_id),
10550                                                    reg, NULL);
10551                 if (ret < 0) {
10552                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10553                                     vsi->vsi_id);
10554                         return I40E_ERR_CONFIG;
10555                 }
10556         }
10557
10558         /* Configure for double VLAN TX insertion */
10559         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10560         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10561                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10562                 ret = i40e_aq_debug_write_register(hw,
10563                                                    I40E_VSI_L2TAGSTXVALID(
10564                                                    vsi->vsi_id), reg, NULL);
10565                 if (ret < 0) {
10566                         PMD_DRV_LOG(ERR,
10567                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10568                                 vsi->vsi_id);
10569                         return I40E_ERR_CONFIG;
10570                 }
10571         }
10572
10573         return 0;
10574 }
10575
10576 /**
10577  * i40e_aq_add_mirror_rule
10578  * @hw: pointer to the hardware structure
10579  * @seid: VEB seid to add mirror rule to
10580  * @dst_id: destination vsi seid
10581  * @entries: Buffer which contains the entities to be mirrored
10582  * @count: number of entities contained in the buffer
10583  * @rule_id:the rule_id of the rule to be added
10584  *
10585  * Add a mirror rule for a given veb.
10586  *
10587  **/
10588 static enum i40e_status_code
10589 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10590                         uint16_t seid, uint16_t dst_id,
10591                         uint16_t rule_type, uint16_t *entries,
10592                         uint16_t count, uint16_t *rule_id)
10593 {
10594         struct i40e_aq_desc desc;
10595         struct i40e_aqc_add_delete_mirror_rule cmd;
10596         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10597                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10598                 &desc.params.raw;
10599         uint16_t buff_len;
10600         enum i40e_status_code status;
10601
10602         i40e_fill_default_direct_cmd_desc(&desc,
10603                                           i40e_aqc_opc_add_mirror_rule);
10604         memset(&cmd, 0, sizeof(cmd));
10605
10606         buff_len = sizeof(uint16_t) * count;
10607         desc.datalen = rte_cpu_to_le_16(buff_len);
10608         if (buff_len > 0)
10609                 desc.flags |= rte_cpu_to_le_16(
10610                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10611         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10612                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10613         cmd.num_entries = rte_cpu_to_le_16(count);
10614         cmd.seid = rte_cpu_to_le_16(seid);
10615         cmd.destination = rte_cpu_to_le_16(dst_id);
10616
10617         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10618         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10619         PMD_DRV_LOG(INFO,
10620                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10621                 hw->aq.asq_last_status, resp->rule_id,
10622                 resp->mirror_rules_used, resp->mirror_rules_free);
10623         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10624
10625         return status;
10626 }
10627
10628 /**
10629  * i40e_aq_del_mirror_rule
10630  * @hw: pointer to the hardware structure
10631  * @seid: VEB seid to add mirror rule to
10632  * @entries: Buffer which contains the entities to be mirrored
10633  * @count: number of entities contained in the buffer
10634  * @rule_id:the rule_id of the rule to be delete
10635  *
10636  * Delete a mirror rule for a given veb.
10637  *
10638  **/
10639 static enum i40e_status_code
10640 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10641                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10642                 uint16_t count, uint16_t rule_id)
10643 {
10644         struct i40e_aq_desc desc;
10645         struct i40e_aqc_add_delete_mirror_rule cmd;
10646         uint16_t buff_len = 0;
10647         enum i40e_status_code status;
10648         void *buff = NULL;
10649
10650         i40e_fill_default_direct_cmd_desc(&desc,
10651                                           i40e_aqc_opc_delete_mirror_rule);
10652         memset(&cmd, 0, sizeof(cmd));
10653         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10654                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10655                                                           I40E_AQ_FLAG_RD));
10656                 cmd.num_entries = count;
10657                 buff_len = sizeof(uint16_t) * count;
10658                 desc.datalen = rte_cpu_to_le_16(buff_len);
10659                 buff = (void *)entries;
10660         } else
10661                 /* rule id is filled in destination field for deleting mirror rule */
10662                 cmd.destination = rte_cpu_to_le_16(rule_id);
10663
10664         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10665                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10666         cmd.seid = rte_cpu_to_le_16(seid);
10667
10668         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10669         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10670
10671         return status;
10672 }
10673
10674 /**
10675  * i40e_mirror_rule_set
10676  * @dev: pointer to the hardware structure
10677  * @mirror_conf: mirror rule info
10678  * @sw_id: mirror rule's sw_id
10679  * @on: enable/disable
10680  *
10681  * set a mirror rule.
10682  *
10683  **/
10684 static int
10685 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10686                         struct rte_eth_mirror_conf *mirror_conf,
10687                         uint8_t sw_id, uint8_t on)
10688 {
10689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10690         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10691         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10692         struct i40e_mirror_rule *parent = NULL;
10693         uint16_t seid, dst_seid, rule_id;
10694         uint16_t i, j = 0;
10695         int ret;
10696
10697         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10698
10699         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10700                 PMD_DRV_LOG(ERR,
10701                         "mirror rule can not be configured without veb or vfs.");
10702                 return -ENOSYS;
10703         }
10704         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10705                 PMD_DRV_LOG(ERR, "mirror table is full.");
10706                 return -ENOSPC;
10707         }
10708         if (mirror_conf->dst_pool > pf->vf_num) {
10709                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10710                                  mirror_conf->dst_pool);
10711                 return -EINVAL;
10712         }
10713
10714         seid = pf->main_vsi->veb->seid;
10715
10716         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10717                 if (sw_id <= it->index) {
10718                         mirr_rule = it;
10719                         break;
10720                 }
10721                 parent = it;
10722         }
10723         if (mirr_rule && sw_id == mirr_rule->index) {
10724                 if (on) {
10725                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10726                         return -EEXIST;
10727                 } else {
10728                         ret = i40e_aq_del_mirror_rule(hw, seid,
10729                                         mirr_rule->rule_type,
10730                                         mirr_rule->entries,
10731                                         mirr_rule->num_entries, mirr_rule->id);
10732                         if (ret < 0) {
10733                                 PMD_DRV_LOG(ERR,
10734                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10735                                         ret, hw->aq.asq_last_status);
10736                                 return -ENOSYS;
10737                         }
10738                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10739                         rte_free(mirr_rule);
10740                         pf->nb_mirror_rule--;
10741                         return 0;
10742                 }
10743         } else if (!on) {
10744                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10745                 return -ENOENT;
10746         }
10747
10748         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10749                                 sizeof(struct i40e_mirror_rule) , 0);
10750         if (!mirr_rule) {
10751                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10752                 return I40E_ERR_NO_MEMORY;
10753         }
10754         switch (mirror_conf->rule_type) {
10755         case ETH_MIRROR_VLAN:
10756                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10757                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10758                                 mirr_rule->entries[j] =
10759                                         mirror_conf->vlan.vlan_id[i];
10760                                 j++;
10761                         }
10762                 }
10763                 if (j == 0) {
10764                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10765                         rte_free(mirr_rule);
10766                         return -EINVAL;
10767                 }
10768                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10769                 break;
10770         case ETH_MIRROR_VIRTUAL_POOL_UP:
10771         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10772                 /* check if the specified pool bit is out of range */
10773                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10774                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10775                         rte_free(mirr_rule);
10776                         return -EINVAL;
10777                 }
10778                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10779                         if (mirror_conf->pool_mask & (1ULL << i)) {
10780                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10781                                 j++;
10782                         }
10783                 }
10784                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10785                         /* add pf vsi to entries */
10786                         mirr_rule->entries[j] = pf->main_vsi_seid;
10787                         j++;
10788                 }
10789                 if (j == 0) {
10790                         PMD_DRV_LOG(ERR, "pool is not specified.");
10791                         rte_free(mirr_rule);
10792                         return -EINVAL;
10793                 }
10794                 /* egress and ingress in aq commands means from switch but not port */
10795                 mirr_rule->rule_type =
10796                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10797                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10798                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10799                 break;
10800         case ETH_MIRROR_UPLINK_PORT:
10801                 /* egress and ingress in aq commands means from switch but not port*/
10802                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10803                 break;
10804         case ETH_MIRROR_DOWNLINK_PORT:
10805                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10806                 break;
10807         default:
10808                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10809                         mirror_conf->rule_type);
10810                 rte_free(mirr_rule);
10811                 return -EINVAL;
10812         }
10813
10814         /* If the dst_pool is equal to vf_num, consider it as PF */
10815         if (mirror_conf->dst_pool == pf->vf_num)
10816                 dst_seid = pf->main_vsi_seid;
10817         else
10818                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10819
10820         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10821                                       mirr_rule->rule_type, mirr_rule->entries,
10822                                       j, &rule_id);
10823         if (ret < 0) {
10824                 PMD_DRV_LOG(ERR,
10825                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10826                         ret, hw->aq.asq_last_status);
10827                 rte_free(mirr_rule);
10828                 return -ENOSYS;
10829         }
10830
10831         mirr_rule->index = sw_id;
10832         mirr_rule->num_entries = j;
10833         mirr_rule->id = rule_id;
10834         mirr_rule->dst_vsi_seid = dst_seid;
10835
10836         if (parent)
10837                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10838         else
10839                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10840
10841         pf->nb_mirror_rule++;
10842         return 0;
10843 }
10844
10845 /**
10846  * i40e_mirror_rule_reset
10847  * @dev: pointer to the device
10848  * @sw_id: mirror rule's sw_id
10849  *
10850  * reset a mirror rule.
10851  *
10852  **/
10853 static int
10854 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10855 {
10856         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10858         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10859         uint16_t seid;
10860         int ret;
10861
10862         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10863
10864         seid = pf->main_vsi->veb->seid;
10865
10866         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10867                 if (sw_id == it->index) {
10868                         mirr_rule = it;
10869                         break;
10870                 }
10871         }
10872         if (mirr_rule) {
10873                 ret = i40e_aq_del_mirror_rule(hw, seid,
10874                                 mirr_rule->rule_type,
10875                                 mirr_rule->entries,
10876                                 mirr_rule->num_entries, mirr_rule->id);
10877                 if (ret < 0) {
10878                         PMD_DRV_LOG(ERR,
10879                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10880                                 ret, hw->aq.asq_last_status);
10881                         return -ENOSYS;
10882                 }
10883                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10884                 rte_free(mirr_rule);
10885                 pf->nb_mirror_rule--;
10886         } else {
10887                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10888                 return -ENOENT;
10889         }
10890         return 0;
10891 }
10892
10893 static uint64_t
10894 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10895 {
10896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10897         uint64_t systim_cycles;
10898
10899         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10900         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10901                         << 32;
10902
10903         return systim_cycles;
10904 }
10905
10906 static uint64_t
10907 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10908 {
10909         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10910         uint64_t rx_tstamp;
10911
10912         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10913         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10914                         << 32;
10915
10916         return rx_tstamp;
10917 }
10918
10919 static uint64_t
10920 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10921 {
10922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10923         uint64_t tx_tstamp;
10924
10925         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10926         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10927                         << 32;
10928
10929         return tx_tstamp;
10930 }
10931
10932 static void
10933 i40e_start_timecounters(struct rte_eth_dev *dev)
10934 {
10935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10936         struct i40e_adapter *adapter = dev->data->dev_private;
10937         struct rte_eth_link link;
10938         uint32_t tsync_inc_l;
10939         uint32_t tsync_inc_h;
10940
10941         /* Get current link speed. */
10942         i40e_dev_link_update(dev, 1);
10943         rte_eth_linkstatus_get(dev, &link);
10944
10945         switch (link.link_speed) {
10946         case ETH_SPEED_NUM_40G:
10947         case ETH_SPEED_NUM_25G:
10948                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10949                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10950                 break;
10951         case ETH_SPEED_NUM_10G:
10952                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10953                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10954                 break;
10955         case ETH_SPEED_NUM_1G:
10956                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10957                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10958                 break;
10959         default:
10960                 tsync_inc_l = 0x0;
10961                 tsync_inc_h = 0x0;
10962         }
10963
10964         /* Set the timesync increment value. */
10965         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10966         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10967
10968         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10969         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10970         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10971
10972         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10973         adapter->systime_tc.cc_shift = 0;
10974         adapter->systime_tc.nsec_mask = 0;
10975
10976         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10977         adapter->rx_tstamp_tc.cc_shift = 0;
10978         adapter->rx_tstamp_tc.nsec_mask = 0;
10979
10980         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10981         adapter->tx_tstamp_tc.cc_shift = 0;
10982         adapter->tx_tstamp_tc.nsec_mask = 0;
10983 }
10984
10985 static int
10986 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10987 {
10988         struct i40e_adapter *adapter = dev->data->dev_private;
10989
10990         adapter->systime_tc.nsec += delta;
10991         adapter->rx_tstamp_tc.nsec += delta;
10992         adapter->tx_tstamp_tc.nsec += delta;
10993
10994         return 0;
10995 }
10996
10997 static int
10998 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10999 {
11000         uint64_t ns;
11001         struct i40e_adapter *adapter = dev->data->dev_private;
11002
11003         ns = rte_timespec_to_ns(ts);
11004
11005         /* Set the timecounters to a new value. */
11006         adapter->systime_tc.nsec = ns;
11007         adapter->rx_tstamp_tc.nsec = ns;
11008         adapter->tx_tstamp_tc.nsec = ns;
11009
11010         return 0;
11011 }
11012
11013 static int
11014 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11015 {
11016         uint64_t ns, systime_cycles;
11017         struct i40e_adapter *adapter = dev->data->dev_private;
11018
11019         systime_cycles = i40e_read_systime_cyclecounter(dev);
11020         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11021         *ts = rte_ns_to_timespec(ns);
11022
11023         return 0;
11024 }
11025
11026 static int
11027 i40e_timesync_enable(struct rte_eth_dev *dev)
11028 {
11029         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11030         uint32_t tsync_ctl_l;
11031         uint32_t tsync_ctl_h;
11032
11033         /* Stop the timesync system time. */
11034         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11035         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11036         /* Reset the timesync system time value. */
11037         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11038         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11039
11040         i40e_start_timecounters(dev);
11041
11042         /* Clear timesync registers. */
11043         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11044         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11045         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11046         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11047         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11048         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11049
11050         /* Enable timestamping of PTP packets. */
11051         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11052         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11053
11054         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11055         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11056         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11057
11058         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11059         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11060
11061         return 0;
11062 }
11063
11064 static int
11065 i40e_timesync_disable(struct rte_eth_dev *dev)
11066 {
11067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11068         uint32_t tsync_ctl_l;
11069         uint32_t tsync_ctl_h;
11070
11071         /* Disable timestamping of transmitted PTP packets. */
11072         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11073         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11074
11075         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11076         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11077
11078         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11079         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11080
11081         /* Reset the timesync increment value. */
11082         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11083         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11084
11085         return 0;
11086 }
11087
11088 static int
11089 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11090                                 struct timespec *timestamp, uint32_t flags)
11091 {
11092         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11093         struct i40e_adapter *adapter = dev->data->dev_private;
11094         uint32_t sync_status;
11095         uint32_t index = flags & 0x03;
11096         uint64_t rx_tstamp_cycles;
11097         uint64_t ns;
11098
11099         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11100         if ((sync_status & (1 << index)) == 0)
11101                 return -EINVAL;
11102
11103         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11104         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11105         *timestamp = rte_ns_to_timespec(ns);
11106
11107         return 0;
11108 }
11109
11110 static int
11111 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11112                                 struct timespec *timestamp)
11113 {
11114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11115         struct i40e_adapter *adapter = dev->data->dev_private;
11116         uint32_t sync_status;
11117         uint64_t tx_tstamp_cycles;
11118         uint64_t ns;
11119
11120         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11121         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11122                 return -EINVAL;
11123
11124         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11125         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11126         *timestamp = rte_ns_to_timespec(ns);
11127
11128         return 0;
11129 }
11130
11131 /*
11132  * i40e_parse_dcb_configure - parse dcb configure from user
11133  * @dev: the device being configured
11134  * @dcb_cfg: pointer of the result of parse
11135  * @*tc_map: bit map of enabled traffic classes
11136  *
11137  * Returns 0 on success, negative value on failure
11138  */
11139 static int
11140 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11141                          struct i40e_dcbx_config *dcb_cfg,
11142                          uint8_t *tc_map)
11143 {
11144         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11145         uint8_t i, tc_bw, bw_lf;
11146
11147         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11148
11149         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11150         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11151                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11152                 return -EINVAL;
11153         }
11154
11155         /* assume each tc has the same bw */
11156         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11157         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11158                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11159         /* to ensure the sum of tcbw is equal to 100 */
11160         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11161         for (i = 0; i < bw_lf; i++)
11162                 dcb_cfg->etscfg.tcbwtable[i]++;
11163
11164         /* assume each tc has the same Transmission Selection Algorithm */
11165         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11166                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11167
11168         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11169                 dcb_cfg->etscfg.prioritytable[i] =
11170                                 dcb_rx_conf->dcb_tc[i];
11171
11172         /* FW needs one App to configure HW */
11173         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11174         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11175         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11176         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11177
11178         if (dcb_rx_conf->nb_tcs == 0)
11179                 *tc_map = 1; /* tc0 only */
11180         else
11181                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11182
11183         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11184                 dcb_cfg->pfc.willing = 0;
11185                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11186                 dcb_cfg->pfc.pfcenable = *tc_map;
11187         }
11188         return 0;
11189 }
11190
11191
11192 static enum i40e_status_code
11193 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11194                               struct i40e_aqc_vsi_properties_data *info,
11195                               uint8_t enabled_tcmap)
11196 {
11197         enum i40e_status_code ret;
11198         int i, total_tc = 0;
11199         uint16_t qpnum_per_tc, bsf, qp_idx;
11200         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11201         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11202         uint16_t used_queues;
11203
11204         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11205         if (ret != I40E_SUCCESS)
11206                 return ret;
11207
11208         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11209                 if (enabled_tcmap & (1 << i))
11210                         total_tc++;
11211         }
11212         if (total_tc == 0)
11213                 total_tc = 1;
11214         vsi->enabled_tc = enabled_tcmap;
11215
11216         /* different VSI has different queues assigned */
11217         if (vsi->type == I40E_VSI_MAIN)
11218                 used_queues = dev_data->nb_rx_queues -
11219                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11220         else if (vsi->type == I40E_VSI_VMDQ2)
11221                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11222         else {
11223                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11224                 return I40E_ERR_NO_AVAILABLE_VSI;
11225         }
11226
11227         qpnum_per_tc = used_queues / total_tc;
11228         /* Number of queues per enabled TC */
11229         if (qpnum_per_tc == 0) {
11230                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11231                 return I40E_ERR_INVALID_QP_ID;
11232         }
11233         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11234                                 I40E_MAX_Q_PER_TC);
11235         bsf = rte_bsf32(qpnum_per_tc);
11236
11237         /**
11238          * Configure TC and queue mapping parameters, for enabled TC,
11239          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11240          * default queue will serve it.
11241          */
11242         qp_idx = 0;
11243         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11244                 if (vsi->enabled_tc & (1 << i)) {
11245                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11246                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11247                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11248                         qp_idx += qpnum_per_tc;
11249                 } else
11250                         info->tc_mapping[i] = 0;
11251         }
11252
11253         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11254         if (vsi->type == I40E_VSI_SRIOV) {
11255                 info->mapping_flags |=
11256                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11257                 for (i = 0; i < vsi->nb_qps; i++)
11258                         info->queue_mapping[i] =
11259                                 rte_cpu_to_le_16(vsi->base_queue + i);
11260         } else {
11261                 info->mapping_flags |=
11262                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11263                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11264         }
11265         info->valid_sections |=
11266                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11267
11268         return I40E_SUCCESS;
11269 }
11270
11271 /*
11272  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11273  * @veb: VEB to be configured
11274  * @tc_map: enabled TC bitmap
11275  *
11276  * Returns 0 on success, negative value on failure
11277  */
11278 static enum i40e_status_code
11279 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11280 {
11281         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11282         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11283         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11284         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11285         enum i40e_status_code ret = I40E_SUCCESS;
11286         int i;
11287         uint32_t bw_max;
11288
11289         /* Check if enabled_tc is same as existing or new TCs */
11290         if (veb->enabled_tc == tc_map)
11291                 return ret;
11292
11293         /* configure tc bandwidth */
11294         memset(&veb_bw, 0, sizeof(veb_bw));
11295         veb_bw.tc_valid_bits = tc_map;
11296         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11297         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11298                 if (tc_map & BIT_ULL(i))
11299                         veb_bw.tc_bw_share_credits[i] = 1;
11300         }
11301         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11302                                                    &veb_bw, NULL);
11303         if (ret) {
11304                 PMD_INIT_LOG(ERR,
11305                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11306                         hw->aq.asq_last_status);
11307                 return ret;
11308         }
11309
11310         memset(&ets_query, 0, sizeof(ets_query));
11311         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11312                                                    &ets_query, NULL);
11313         if (ret != I40E_SUCCESS) {
11314                 PMD_DRV_LOG(ERR,
11315                         "Failed to get switch_comp ETS configuration %u",
11316                         hw->aq.asq_last_status);
11317                 return ret;
11318         }
11319         memset(&bw_query, 0, sizeof(bw_query));
11320         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11321                                                   &bw_query, NULL);
11322         if (ret != I40E_SUCCESS) {
11323                 PMD_DRV_LOG(ERR,
11324                         "Failed to get switch_comp bandwidth configuration %u",
11325                         hw->aq.asq_last_status);
11326                 return ret;
11327         }
11328
11329         /* store and print out BW info */
11330         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11331         veb->bw_info.bw_max = ets_query.tc_bw_max;
11332         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11333         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11334         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11335                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11336                      I40E_16_BIT_WIDTH);
11337         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11338                 veb->bw_info.bw_ets_share_credits[i] =
11339                                 bw_query.tc_bw_share_credits[i];
11340                 veb->bw_info.bw_ets_credits[i] =
11341                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11342                 /* 4 bits per TC, 4th bit is reserved */
11343                 veb->bw_info.bw_ets_max[i] =
11344                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11345                                   RTE_LEN2MASK(3, uint8_t));
11346                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11347                             veb->bw_info.bw_ets_share_credits[i]);
11348                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11349                             veb->bw_info.bw_ets_credits[i]);
11350                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11351                             veb->bw_info.bw_ets_max[i]);
11352         }
11353
11354         veb->enabled_tc = tc_map;
11355
11356         return ret;
11357 }
11358
11359
11360 /*
11361  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11362  * @vsi: VSI to be configured
11363  * @tc_map: enabled TC bitmap
11364  *
11365  * Returns 0 on success, negative value on failure
11366  */
11367 static enum i40e_status_code
11368 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11369 {
11370         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11371         struct i40e_vsi_context ctxt;
11372         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11373         enum i40e_status_code ret = I40E_SUCCESS;
11374         int i;
11375
11376         /* Check if enabled_tc is same as existing or new TCs */
11377         if (vsi->enabled_tc == tc_map)
11378                 return ret;
11379
11380         /* configure tc bandwidth */
11381         memset(&bw_data, 0, sizeof(bw_data));
11382         bw_data.tc_valid_bits = tc_map;
11383         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11384         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11385                 if (tc_map & BIT_ULL(i))
11386                         bw_data.tc_bw_credits[i] = 1;
11387         }
11388         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11389         if (ret) {
11390                 PMD_INIT_LOG(ERR,
11391                         "AQ command Config VSI BW allocation per TC failed = %d",
11392                         hw->aq.asq_last_status);
11393                 goto out;
11394         }
11395         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11396                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11397
11398         /* Update Queue Pairs Mapping for currently enabled UPs */
11399         ctxt.seid = vsi->seid;
11400         ctxt.pf_num = hw->pf_id;
11401         ctxt.vf_num = 0;
11402         ctxt.uplink_seid = vsi->uplink_seid;
11403         ctxt.info = vsi->info;
11404         i40e_get_cap(hw);
11405         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11406         if (ret)
11407                 goto out;
11408
11409         /* Update the VSI after updating the VSI queue-mapping information */
11410         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11411         if (ret) {
11412                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11413                         hw->aq.asq_last_status);
11414                 goto out;
11415         }
11416         /* update the local VSI info with updated queue map */
11417         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11418                                         sizeof(vsi->info.tc_mapping));
11419         rte_memcpy(&vsi->info.queue_mapping,
11420                         &ctxt.info.queue_mapping,
11421                 sizeof(vsi->info.queue_mapping));
11422         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11423         vsi->info.valid_sections = 0;
11424
11425         /* query and update current VSI BW information */
11426         ret = i40e_vsi_get_bw_config(vsi);
11427         if (ret) {
11428                 PMD_INIT_LOG(ERR,
11429                          "Failed updating vsi bw info, err %s aq_err %s",
11430                          i40e_stat_str(hw, ret),
11431                          i40e_aq_str(hw, hw->aq.asq_last_status));
11432                 goto out;
11433         }
11434
11435         vsi->enabled_tc = tc_map;
11436
11437 out:
11438         return ret;
11439 }
11440
11441 /*
11442  * i40e_dcb_hw_configure - program the dcb setting to hw
11443  * @pf: pf the configuration is taken on
11444  * @new_cfg: new configuration
11445  * @tc_map: enabled TC bitmap
11446  *
11447  * Returns 0 on success, negative value on failure
11448  */
11449 static enum i40e_status_code
11450 i40e_dcb_hw_configure(struct i40e_pf *pf,
11451                       struct i40e_dcbx_config *new_cfg,
11452                       uint8_t tc_map)
11453 {
11454         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11455         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11456         struct i40e_vsi *main_vsi = pf->main_vsi;
11457         struct i40e_vsi_list *vsi_list;
11458         enum i40e_status_code ret;
11459         int i;
11460         uint32_t val;
11461
11462         /* Use the FW API if FW > v4.4*/
11463         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11464               (hw->aq.fw_maj_ver >= 5))) {
11465                 PMD_INIT_LOG(ERR,
11466                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11467                 return I40E_ERR_FIRMWARE_API_VERSION;
11468         }
11469
11470         /* Check if need reconfiguration */
11471         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11472                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11473                 return I40E_SUCCESS;
11474         }
11475
11476         /* Copy the new config to the current config */
11477         *old_cfg = *new_cfg;
11478         old_cfg->etsrec = old_cfg->etscfg;
11479         ret = i40e_set_dcb_config(hw);
11480         if (ret) {
11481                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11482                          i40e_stat_str(hw, ret),
11483                          i40e_aq_str(hw, hw->aq.asq_last_status));
11484                 return ret;
11485         }
11486         /* set receive Arbiter to RR mode and ETS scheme by default */
11487         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11488                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11489                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11490                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11491                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11492                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11493                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11494                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11495                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11496                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11497                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11498                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11499                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11500         }
11501         /* get local mib to check whether it is configured correctly */
11502         /* IEEE mode */
11503         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11504         /* Get Local DCB Config */
11505         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11506                                      &hw->local_dcbx_config);
11507
11508         /* if Veb is created, need to update TC of it at first */
11509         if (main_vsi->veb) {
11510                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11511                 if (ret)
11512                         PMD_INIT_LOG(WARNING,
11513                                  "Failed configuring TC for VEB seid=%d",
11514                                  main_vsi->veb->seid);
11515         }
11516         /* Update each VSI */
11517         i40e_vsi_config_tc(main_vsi, tc_map);
11518         if (main_vsi->veb) {
11519                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11520                         /* Beside main VSI and VMDQ VSIs, only enable default
11521                          * TC for other VSIs
11522                          */
11523                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11524                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11525                                                          tc_map);
11526                         else
11527                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11528                                                          I40E_DEFAULT_TCMAP);
11529                         if (ret)
11530                                 PMD_INIT_LOG(WARNING,
11531                                         "Failed configuring TC for VSI seid=%d",
11532                                         vsi_list->vsi->seid);
11533                         /* continue */
11534                 }
11535         }
11536         return I40E_SUCCESS;
11537 }
11538
11539 /*
11540  * i40e_dcb_init_configure - initial dcb config
11541  * @dev: device being configured
11542  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11543  *
11544  * Returns 0 on success, negative value on failure
11545  */
11546 int
11547 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11548 {
11549         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11550         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11551         int i, ret = 0;
11552
11553         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11554                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11555                 return -ENOTSUP;
11556         }
11557
11558         /* DCB initialization:
11559          * Update DCB configuration from the Firmware and configure
11560          * LLDP MIB change event.
11561          */
11562         if (sw_dcb == TRUE) {
11563                 if (i40e_need_stop_lldp(dev)) {
11564                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11565                         if (ret != I40E_SUCCESS)
11566                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11567                 }
11568
11569                 ret = i40e_init_dcb(hw);
11570                 /* If lldp agent is stopped, the return value from
11571                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11572                  * adminq status. Otherwise, it should return success.
11573                  */
11574                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11575                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11576                         memset(&hw->local_dcbx_config, 0,
11577                                 sizeof(struct i40e_dcbx_config));
11578                         /* set dcb default configuration */
11579                         hw->local_dcbx_config.etscfg.willing = 0;
11580                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11581                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11582                         hw->local_dcbx_config.etscfg.tsatable[0] =
11583                                                 I40E_IEEE_TSA_ETS;
11584                         /* all UPs mapping to TC0 */
11585                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11586                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11587                         hw->local_dcbx_config.etsrec =
11588                                 hw->local_dcbx_config.etscfg;
11589                         hw->local_dcbx_config.pfc.willing = 0;
11590                         hw->local_dcbx_config.pfc.pfccap =
11591                                                 I40E_MAX_TRAFFIC_CLASS;
11592                         /* FW needs one App to configure HW */
11593                         hw->local_dcbx_config.numapps = 1;
11594                         hw->local_dcbx_config.app[0].selector =
11595                                                 I40E_APP_SEL_ETHTYPE;
11596                         hw->local_dcbx_config.app[0].priority = 3;
11597                         hw->local_dcbx_config.app[0].protocolid =
11598                                                 I40E_APP_PROTOID_FCOE;
11599                         ret = i40e_set_dcb_config(hw);
11600                         if (ret) {
11601                                 PMD_INIT_LOG(ERR,
11602                                         "default dcb config fails. err = %d, aq_err = %d.",
11603                                         ret, hw->aq.asq_last_status);
11604                                 return -ENOSYS;
11605                         }
11606                 } else {
11607                         PMD_INIT_LOG(ERR,
11608                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11609                                 ret, hw->aq.asq_last_status);
11610                         return -ENOTSUP;
11611                 }
11612         } else {
11613                 ret = i40e_aq_start_lldp(hw, NULL);
11614                 if (ret != I40E_SUCCESS)
11615                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11616
11617                 ret = i40e_init_dcb(hw);
11618                 if (!ret) {
11619                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11620                                 PMD_INIT_LOG(ERR,
11621                                         "HW doesn't support DCBX offload.");
11622                                 return -ENOTSUP;
11623                         }
11624                 } else {
11625                         PMD_INIT_LOG(ERR,
11626                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11627                                 ret, hw->aq.asq_last_status);
11628                         return -ENOTSUP;
11629                 }
11630         }
11631         return 0;
11632 }
11633
11634 /*
11635  * i40e_dcb_setup - setup dcb related config
11636  * @dev: device being configured
11637  *
11638  * Returns 0 on success, negative value on failure
11639  */
11640 static int
11641 i40e_dcb_setup(struct rte_eth_dev *dev)
11642 {
11643         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11644         struct i40e_dcbx_config dcb_cfg;
11645         uint8_t tc_map = 0;
11646         int ret = 0;
11647
11648         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11649                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11650                 return -ENOTSUP;
11651         }
11652
11653         if (pf->vf_num != 0)
11654                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11655
11656         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11657         if (ret) {
11658                 PMD_INIT_LOG(ERR, "invalid dcb config");
11659                 return -EINVAL;
11660         }
11661         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11662         if (ret) {
11663                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11664                 return -ENOSYS;
11665         }
11666
11667         return 0;
11668 }
11669
11670 static int
11671 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11672                       struct rte_eth_dcb_info *dcb_info)
11673 {
11674         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11675         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11676         struct i40e_vsi *vsi = pf->main_vsi;
11677         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11678         uint16_t bsf, tc_mapping;
11679         int i, j = 0;
11680
11681         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11682                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11683         else
11684                 dcb_info->nb_tcs = 1;
11685         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11686                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11687         for (i = 0; i < dcb_info->nb_tcs; i++)
11688                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11689
11690         /* get queue mapping if vmdq is disabled */
11691         if (!pf->nb_cfg_vmdq_vsi) {
11692                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11693                         if (!(vsi->enabled_tc & (1 << i)))
11694                                 continue;
11695                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11696                         dcb_info->tc_queue.tc_rxq[j][i].base =
11697                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11698                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11699                         dcb_info->tc_queue.tc_txq[j][i].base =
11700                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11701                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11702                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11703                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11704                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11705                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11706                 }
11707                 return 0;
11708         }
11709
11710         /* get queue mapping if vmdq is enabled */
11711         do {
11712                 vsi = pf->vmdq[j].vsi;
11713                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11714                         if (!(vsi->enabled_tc & (1 << i)))
11715                                 continue;
11716                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11717                         dcb_info->tc_queue.tc_rxq[j][i].base =
11718                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11719                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11720                         dcb_info->tc_queue.tc_txq[j][i].base =
11721                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11722                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11723                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11724                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11725                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11726                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11727                 }
11728                 j++;
11729         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11730         return 0;
11731 }
11732
11733 static int
11734 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11735 {
11736         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11737         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11738         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11739         uint16_t msix_intr;
11740
11741         msix_intr = intr_handle->intr_vec[queue_id];
11742         if (msix_intr == I40E_MISC_VEC_ID)
11743                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11744                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11745                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11746                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11747         else
11748                 I40E_WRITE_REG(hw,
11749                                I40E_PFINT_DYN_CTLN(msix_intr -
11750                                                    I40E_RX_VEC_START),
11751                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11752                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11753                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11754
11755         I40E_WRITE_FLUSH(hw);
11756         rte_intr_ack(&pci_dev->intr_handle);
11757
11758         return 0;
11759 }
11760
11761 static int
11762 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11763 {
11764         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11765         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11767         uint16_t msix_intr;
11768
11769         msix_intr = intr_handle->intr_vec[queue_id];
11770         if (msix_intr == I40E_MISC_VEC_ID)
11771                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11772                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11773         else
11774                 I40E_WRITE_REG(hw,
11775                                I40E_PFINT_DYN_CTLN(msix_intr -
11776                                                    I40E_RX_VEC_START),
11777                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11778         I40E_WRITE_FLUSH(hw);
11779
11780         return 0;
11781 }
11782
11783 /**
11784  * This function is used to check if the register is valid.
11785  * Below is the valid registers list for X722 only:
11786  * 0x2b800--0x2bb00
11787  * 0x38700--0x38a00
11788  * 0x3d800--0x3db00
11789  * 0x208e00--0x209000
11790  * 0x20be00--0x20c000
11791  * 0x263c00--0x264000
11792  * 0x265c00--0x266000
11793  */
11794 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11795 {
11796         if ((type != I40E_MAC_X722) &&
11797             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11798              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11799              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11800              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11801              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11802              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11803              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11804                 return 0;
11805         else
11806                 return 1;
11807 }
11808
11809 static int i40e_get_regs(struct rte_eth_dev *dev,
11810                          struct rte_dev_reg_info *regs)
11811 {
11812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11813         uint32_t *ptr_data = regs->data;
11814         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11815         const struct i40e_reg_info *reg_info;
11816
11817         if (ptr_data == NULL) {
11818                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11819                 regs->width = sizeof(uint32_t);
11820                 return 0;
11821         }
11822
11823         /* The first few registers have to be read using AQ operations */
11824         reg_idx = 0;
11825         while (i40e_regs_adminq[reg_idx].name) {
11826                 reg_info = &i40e_regs_adminq[reg_idx++];
11827                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11828                         for (arr_idx2 = 0;
11829                                         arr_idx2 <= reg_info->count2;
11830                                         arr_idx2++) {
11831                                 reg_offset = arr_idx * reg_info->stride1 +
11832                                         arr_idx2 * reg_info->stride2;
11833                                 reg_offset += reg_info->base_addr;
11834                                 ptr_data[reg_offset >> 2] =
11835                                         i40e_read_rx_ctl(hw, reg_offset);
11836                         }
11837         }
11838
11839         /* The remaining registers can be read using primitives */
11840         reg_idx = 0;
11841         while (i40e_regs_others[reg_idx].name) {
11842                 reg_info = &i40e_regs_others[reg_idx++];
11843                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11844                         for (arr_idx2 = 0;
11845                                         arr_idx2 <= reg_info->count2;
11846                                         arr_idx2++) {
11847                                 reg_offset = arr_idx * reg_info->stride1 +
11848                                         arr_idx2 * reg_info->stride2;
11849                                 reg_offset += reg_info->base_addr;
11850                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11851                                         ptr_data[reg_offset >> 2] = 0;
11852                                 else
11853                                         ptr_data[reg_offset >> 2] =
11854                                                 I40E_READ_REG(hw, reg_offset);
11855                         }
11856         }
11857
11858         return 0;
11859 }
11860
11861 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11862 {
11863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11864
11865         /* Convert word count to byte count */
11866         return hw->nvm.sr_size << 1;
11867 }
11868
11869 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11870                            struct rte_dev_eeprom_info *eeprom)
11871 {
11872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11873         uint16_t *data = eeprom->data;
11874         uint16_t offset, length, cnt_words;
11875         int ret_code;
11876
11877         offset = eeprom->offset >> 1;
11878         length = eeprom->length >> 1;
11879         cnt_words = length;
11880
11881         if (offset > hw->nvm.sr_size ||
11882                 offset + length > hw->nvm.sr_size) {
11883                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11884                 return -EINVAL;
11885         }
11886
11887         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11888
11889         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11890         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11891                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11892                 return -EIO;
11893         }
11894
11895         return 0;
11896 }
11897
11898 static int i40e_get_module_info(struct rte_eth_dev *dev,
11899                                 struct rte_eth_dev_module_info *modinfo)
11900 {
11901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11902         uint32_t sff8472_comp = 0;
11903         uint32_t sff8472_swap = 0;
11904         uint32_t sff8636_rev = 0;
11905         i40e_status status;
11906         uint32_t type = 0;
11907
11908         /* Check if firmware supports reading module EEPROM. */
11909         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11910                 PMD_DRV_LOG(ERR,
11911                             "Module EEPROM memory read not supported. "
11912                             "Please update the NVM image.\n");
11913                 return -EINVAL;
11914         }
11915
11916         status = i40e_update_link_info(hw);
11917         if (status)
11918                 return -EIO;
11919
11920         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11921                 PMD_DRV_LOG(ERR,
11922                             "Cannot read module EEPROM memory. "
11923                             "No module connected.\n");
11924                 return -EINVAL;
11925         }
11926
11927         type = hw->phy.link_info.module_type[0];
11928
11929         switch (type) {
11930         case I40E_MODULE_TYPE_SFP:
11931                 status = i40e_aq_get_phy_register(hw,
11932                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11933                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11934                                 I40E_MODULE_SFF_8472_COMP,
11935                                 &sff8472_comp, NULL);
11936                 if (status)
11937                         return -EIO;
11938
11939                 status = i40e_aq_get_phy_register(hw,
11940                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11941                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11942                                 I40E_MODULE_SFF_8472_SWAP,
11943                                 &sff8472_swap, NULL);
11944                 if (status)
11945                         return -EIO;
11946
11947                 /* Check if the module requires address swap to access
11948                  * the other EEPROM memory page.
11949                  */
11950                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11951                         PMD_DRV_LOG(WARNING,
11952                                     "Module address swap to access "
11953                                     "page 0xA2 is not supported.\n");
11954                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11955                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11956                 } else if (sff8472_comp == 0x00) {
11957                         /* Module is not SFF-8472 compliant */
11958                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11959                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11960                 } else {
11961                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11962                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11963                 }
11964                 break;
11965         case I40E_MODULE_TYPE_QSFP_PLUS:
11966                 /* Read from memory page 0. */
11967                 status = i40e_aq_get_phy_register(hw,
11968                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11969                                 0, 1,
11970                                 I40E_MODULE_REVISION_ADDR,
11971                                 &sff8636_rev, NULL);
11972                 if (status)
11973                         return -EIO;
11974                 /* Determine revision compliance byte */
11975                 if (sff8636_rev > 0x02) {
11976                         /* Module is SFF-8636 compliant */
11977                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11978                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11979                 } else {
11980                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11981                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11982                 }
11983                 break;
11984         case I40E_MODULE_TYPE_QSFP28:
11985                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11986                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11987                 break;
11988         default:
11989                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11990                 return -EINVAL;
11991         }
11992         return 0;
11993 }
11994
11995 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11996                                   struct rte_dev_eeprom_info *info)
11997 {
11998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11999         bool is_sfp = false;
12000         i40e_status status;
12001         uint8_t *data;
12002         uint32_t value = 0;
12003         uint32_t i;
12004
12005         if (!info || !info->length || !info->data)
12006                 return -EINVAL;
12007
12008         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12009                 is_sfp = true;
12010
12011         data = info->data;
12012         for (i = 0; i < info->length; i++) {
12013                 u32 offset = i + info->offset;
12014                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12015
12016                 /* Check if we need to access the other memory page */
12017                 if (is_sfp) {
12018                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12019                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12020                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12021                         }
12022                 } else {
12023                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12024                                 /* Compute memory page number and offset. */
12025                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12026                                 addr++;
12027                         }
12028                 }
12029                 status = i40e_aq_get_phy_register(hw,
12030                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12031                                 addr, offset, 1, &value, NULL);
12032                 if (status)
12033                         return -EIO;
12034                 data[i] = (uint8_t)value;
12035         }
12036         return 0;
12037 }
12038
12039 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12040                                      struct rte_ether_addr *mac_addr)
12041 {
12042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12044         struct i40e_vsi *vsi = pf->main_vsi;
12045         struct i40e_mac_filter_info mac_filter;
12046         struct i40e_mac_filter *f;
12047         int ret;
12048
12049         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12050                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12051                 return -EINVAL;
12052         }
12053
12054         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12055                 if (rte_is_same_ether_addr(&pf->dev_addr,
12056                                                 &f->mac_info.mac_addr))
12057                         break;
12058         }
12059
12060         if (f == NULL) {
12061                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12062                 return -EIO;
12063         }
12064
12065         mac_filter = f->mac_info;
12066         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12067         if (ret != I40E_SUCCESS) {
12068                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12069                 return -EIO;
12070         }
12071         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12072         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12073         if (ret != I40E_SUCCESS) {
12074                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12075                 return -EIO;
12076         }
12077         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12078
12079         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12080                                         mac_addr->addr_bytes, NULL);
12081         if (ret != I40E_SUCCESS) {
12082                 PMD_DRV_LOG(ERR, "Failed to change mac");
12083                 return -EIO;
12084         }
12085
12086         return 0;
12087 }
12088
12089 static int
12090 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12091 {
12092         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12093         struct rte_eth_dev_data *dev_data = pf->dev_data;
12094         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12095         int ret = 0;
12096
12097         /* check if mtu is within the allowed range */
12098         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12099                 return -EINVAL;
12100
12101         /* mtu setting is forbidden if port is start */
12102         if (dev_data->dev_started) {
12103                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12104                             dev_data->port_id);
12105                 return -EBUSY;
12106         }
12107
12108         if (frame_size > RTE_ETHER_MAX_LEN)
12109                 dev_data->dev_conf.rxmode.offloads |=
12110                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12111         else
12112                 dev_data->dev_conf.rxmode.offloads &=
12113                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12114
12115         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12116
12117         return ret;
12118 }
12119
12120 /* Restore ethertype filter */
12121 static void
12122 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12123 {
12124         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12125         struct i40e_ethertype_filter_list
12126                 *ethertype_list = &pf->ethertype.ethertype_list;
12127         struct i40e_ethertype_filter *f;
12128         struct i40e_control_filter_stats stats;
12129         uint16_t flags;
12130
12131         TAILQ_FOREACH(f, ethertype_list, rules) {
12132                 flags = 0;
12133                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12134                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12135                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12136                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12137                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12138
12139                 memset(&stats, 0, sizeof(stats));
12140                 i40e_aq_add_rem_control_packet_filter(hw,
12141                                             f->input.mac_addr.addr_bytes,
12142                                             f->input.ether_type,
12143                                             flags, pf->main_vsi->seid,
12144                                             f->queue, 1, &stats, NULL);
12145         }
12146         PMD_DRV_LOG(INFO, "Ethertype filter:"
12147                     " mac_etype_used = %u, etype_used = %u,"
12148                     " mac_etype_free = %u, etype_free = %u",
12149                     stats.mac_etype_used, stats.etype_used,
12150                     stats.mac_etype_free, stats.etype_free);
12151 }
12152
12153 /* Restore tunnel filter */
12154 static void
12155 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12156 {
12157         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12158         struct i40e_vsi *vsi;
12159         struct i40e_pf_vf *vf;
12160         struct i40e_tunnel_filter_list
12161                 *tunnel_list = &pf->tunnel.tunnel_list;
12162         struct i40e_tunnel_filter *f;
12163         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12164         bool big_buffer = 0;
12165
12166         TAILQ_FOREACH(f, tunnel_list, rules) {
12167                 if (!f->is_to_vf)
12168                         vsi = pf->main_vsi;
12169                 else {
12170                         vf = &pf->vfs[f->vf_id];
12171                         vsi = vf->vsi;
12172                 }
12173                 memset(&cld_filter, 0, sizeof(cld_filter));
12174                 rte_ether_addr_copy((struct rte_ether_addr *)
12175                                 &f->input.outer_mac,
12176                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12177                 rte_ether_addr_copy((struct rte_ether_addr *)
12178                                 &f->input.inner_mac,
12179                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12180                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12181                 cld_filter.element.flags = f->input.flags;
12182                 cld_filter.element.tenant_id = f->input.tenant_id;
12183                 cld_filter.element.queue_number = f->queue;
12184                 rte_memcpy(cld_filter.general_fields,
12185                            f->input.general_fields,
12186                            sizeof(f->input.general_fields));
12187
12188                 if (((f->input.flags &
12189                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12190                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12191                     ((f->input.flags &
12192                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12193                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12194                     ((f->input.flags &
12195                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12196                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12197                         big_buffer = 1;
12198
12199                 if (big_buffer)
12200                         i40e_aq_add_cloud_filters_bb(hw,
12201                                         vsi->seid, &cld_filter, 1);
12202                 else
12203                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12204                                                   &cld_filter.element, 1);
12205         }
12206 }
12207
12208 /* Restore rss filter */
12209 static inline void
12210 i40e_rss_filter_restore(struct i40e_pf *pf)
12211 {
12212         struct i40e_rte_flow_rss_conf *conf =
12213                                         &pf->rss_info;
12214         if (conf->conf.queue_num)
12215                 i40e_config_rss_filter(pf, conf, TRUE);
12216 }
12217
12218 static void
12219 i40e_filter_restore(struct i40e_pf *pf)
12220 {
12221         i40e_ethertype_filter_restore(pf);
12222         i40e_tunnel_filter_restore(pf);
12223         i40e_fdir_filter_restore(pf);
12224         i40e_rss_filter_restore(pf);
12225 }
12226
12227 bool
12228 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12229 {
12230         if (strcmp(dev->device->driver->name, drv->driver.name))
12231                 return false;
12232
12233         return true;
12234 }
12235
12236 bool
12237 is_i40e_supported(struct rte_eth_dev *dev)
12238 {
12239         return is_device_supported(dev, &rte_i40e_pmd);
12240 }
12241
12242 struct i40e_customized_pctype*
12243 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12244 {
12245         int i;
12246
12247         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12248                 if (pf->customized_pctype[i].index == index)
12249                         return &pf->customized_pctype[i];
12250         }
12251         return NULL;
12252 }
12253
12254 static int
12255 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12256                               uint32_t pkg_size, uint32_t proto_num,
12257                               struct rte_pmd_i40e_proto_info *proto,
12258                               enum rte_pmd_i40e_package_op op)
12259 {
12260         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12261         uint32_t pctype_num;
12262         struct rte_pmd_i40e_ptype_info *pctype;
12263         uint32_t buff_size;
12264         struct i40e_customized_pctype *new_pctype = NULL;
12265         uint8_t proto_id;
12266         uint8_t pctype_value;
12267         char name[64];
12268         uint32_t i, j, n;
12269         int ret;
12270
12271         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12272             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12273                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12274                 return -1;
12275         }
12276
12277         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12278                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12279                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12280         if (ret) {
12281                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12282                 return -1;
12283         }
12284         if (!pctype_num) {
12285                 PMD_DRV_LOG(INFO, "No new pctype added");
12286                 return -1;
12287         }
12288
12289         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12290         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12291         if (!pctype) {
12292                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12293                 return -1;
12294         }
12295         /* get information about new pctype list */
12296         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12297                                         (uint8_t *)pctype, buff_size,
12298                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12299         if (ret) {
12300                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12301                 rte_free(pctype);
12302                 return -1;
12303         }
12304
12305         /* Update customized pctype. */
12306         for (i = 0; i < pctype_num; i++) {
12307                 pctype_value = pctype[i].ptype_id;
12308                 memset(name, 0, sizeof(name));
12309                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12310                         proto_id = pctype[i].protocols[j];
12311                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12312                                 continue;
12313                         for (n = 0; n < proto_num; n++) {
12314                                 if (proto[n].proto_id != proto_id)
12315                                         continue;
12316                                 strlcat(name, proto[n].name, sizeof(name));
12317                                 strlcat(name, "_", sizeof(name));
12318                                 break;
12319                         }
12320                 }
12321                 name[strlen(name) - 1] = '\0';
12322                 if (!strcmp(name, "GTPC"))
12323                         new_pctype =
12324                                 i40e_find_customized_pctype(pf,
12325                                                       I40E_CUSTOMIZED_GTPC);
12326                 else if (!strcmp(name, "GTPU_IPV4"))
12327                         new_pctype =
12328                                 i40e_find_customized_pctype(pf,
12329                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12330                 else if (!strcmp(name, "GTPU_IPV6"))
12331                         new_pctype =
12332                                 i40e_find_customized_pctype(pf,
12333                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12334                 else if (!strcmp(name, "GTPU"))
12335                         new_pctype =
12336                                 i40e_find_customized_pctype(pf,
12337                                                       I40E_CUSTOMIZED_GTPU);
12338                 if (new_pctype) {
12339                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12340                                 new_pctype->pctype = pctype_value;
12341                                 new_pctype->valid = true;
12342                         } else {
12343                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12344                                 new_pctype->valid = false;
12345                         }
12346                 }
12347         }
12348
12349         rte_free(pctype);
12350         return 0;
12351 }
12352
12353 static int
12354 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12355                              uint32_t pkg_size, uint32_t proto_num,
12356                              struct rte_pmd_i40e_proto_info *proto,
12357                              enum rte_pmd_i40e_package_op op)
12358 {
12359         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12360         uint16_t port_id = dev->data->port_id;
12361         uint32_t ptype_num;
12362         struct rte_pmd_i40e_ptype_info *ptype;
12363         uint32_t buff_size;
12364         uint8_t proto_id;
12365         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12366         uint32_t i, j, n;
12367         bool in_tunnel;
12368         int ret;
12369
12370         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12371             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12372                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12373                 return -1;
12374         }
12375
12376         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12377                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12378                 return 0;
12379         }
12380
12381         /* get information about new ptype num */
12382         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12383                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12384                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12385         if (ret) {
12386                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12387                 return ret;
12388         }
12389         if (!ptype_num) {
12390                 PMD_DRV_LOG(INFO, "No new ptype added");
12391                 return -1;
12392         }
12393
12394         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12395         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12396         if (!ptype) {
12397                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12398                 return -1;
12399         }
12400
12401         /* get information about new ptype list */
12402         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12403                                         (uint8_t *)ptype, buff_size,
12404                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12405         if (ret) {
12406                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12407                 rte_free(ptype);
12408                 return ret;
12409         }
12410
12411         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12412         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12413         if (!ptype_mapping) {
12414                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12415                 rte_free(ptype);
12416                 return -1;
12417         }
12418
12419         /* Update ptype mapping table. */
12420         for (i = 0; i < ptype_num; i++) {
12421                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12422                 ptype_mapping[i].sw_ptype = 0;
12423                 in_tunnel = false;
12424                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12425                         proto_id = ptype[i].protocols[j];
12426                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12427                                 continue;
12428                         for (n = 0; n < proto_num; n++) {
12429                                 if (proto[n].proto_id != proto_id)
12430                                         continue;
12431                                 memset(name, 0, sizeof(name));
12432                                 strcpy(name, proto[n].name);
12433                                 if (!strncasecmp(name, "PPPOE", 5))
12434                                         ptype_mapping[i].sw_ptype |=
12435                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12436                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12437                                          !in_tunnel) {
12438                                         ptype_mapping[i].sw_ptype |=
12439                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12440                                         ptype_mapping[i].sw_ptype |=
12441                                                 RTE_PTYPE_L4_FRAG;
12442                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12443                                            in_tunnel) {
12444                                         ptype_mapping[i].sw_ptype |=
12445                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12446                                         ptype_mapping[i].sw_ptype |=
12447                                                 RTE_PTYPE_INNER_L4_FRAG;
12448                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12449                                         ptype_mapping[i].sw_ptype |=
12450                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12451                                         in_tunnel = true;
12452                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12453                                            !in_tunnel)
12454                                         ptype_mapping[i].sw_ptype |=
12455                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12456                                 else if (!strncasecmp(name, "IPV4", 4) &&
12457                                          in_tunnel)
12458                                         ptype_mapping[i].sw_ptype |=
12459                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12460                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12461                                          !in_tunnel) {
12462                                         ptype_mapping[i].sw_ptype |=
12463                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12464                                         ptype_mapping[i].sw_ptype |=
12465                                                 RTE_PTYPE_L4_FRAG;
12466                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12467                                            in_tunnel) {
12468                                         ptype_mapping[i].sw_ptype |=
12469                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12470                                         ptype_mapping[i].sw_ptype |=
12471                                                 RTE_PTYPE_INNER_L4_FRAG;
12472                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12473                                         ptype_mapping[i].sw_ptype |=
12474                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12475                                         in_tunnel = true;
12476                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12477                                            !in_tunnel)
12478                                         ptype_mapping[i].sw_ptype |=
12479                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12480                                 else if (!strncasecmp(name, "IPV6", 4) &&
12481                                          in_tunnel)
12482                                         ptype_mapping[i].sw_ptype |=
12483                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12484                                 else if (!strncasecmp(name, "UDP", 3) &&
12485                                          !in_tunnel)
12486                                         ptype_mapping[i].sw_ptype |=
12487                                                 RTE_PTYPE_L4_UDP;
12488                                 else if (!strncasecmp(name, "UDP", 3) &&
12489                                          in_tunnel)
12490                                         ptype_mapping[i].sw_ptype |=
12491                                                 RTE_PTYPE_INNER_L4_UDP;
12492                                 else if (!strncasecmp(name, "TCP", 3) &&
12493                                          !in_tunnel)
12494                                         ptype_mapping[i].sw_ptype |=
12495                                                 RTE_PTYPE_L4_TCP;
12496                                 else if (!strncasecmp(name, "TCP", 3) &&
12497                                          in_tunnel)
12498                                         ptype_mapping[i].sw_ptype |=
12499                                                 RTE_PTYPE_INNER_L4_TCP;
12500                                 else if (!strncasecmp(name, "SCTP", 4) &&
12501                                          !in_tunnel)
12502                                         ptype_mapping[i].sw_ptype |=
12503                                                 RTE_PTYPE_L4_SCTP;
12504                                 else if (!strncasecmp(name, "SCTP", 4) &&
12505                                          in_tunnel)
12506                                         ptype_mapping[i].sw_ptype |=
12507                                                 RTE_PTYPE_INNER_L4_SCTP;
12508                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12509                                           !strncasecmp(name, "ICMPV6", 6)) &&
12510                                          !in_tunnel)
12511                                         ptype_mapping[i].sw_ptype |=
12512                                                 RTE_PTYPE_L4_ICMP;
12513                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12514                                           !strncasecmp(name, "ICMPV6", 6)) &&
12515                                          in_tunnel)
12516                                         ptype_mapping[i].sw_ptype |=
12517                                                 RTE_PTYPE_INNER_L4_ICMP;
12518                                 else if (!strncasecmp(name, "GTPC", 4)) {
12519                                         ptype_mapping[i].sw_ptype |=
12520                                                 RTE_PTYPE_TUNNEL_GTPC;
12521                                         in_tunnel = true;
12522                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12523                                         ptype_mapping[i].sw_ptype |=
12524                                                 RTE_PTYPE_TUNNEL_GTPU;
12525                                         in_tunnel = true;
12526                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12527                                         ptype_mapping[i].sw_ptype |=
12528                                                 RTE_PTYPE_TUNNEL_GRENAT;
12529                                         in_tunnel = true;
12530                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12531                                            !strncasecmp(name, "L2TPV2", 6)) {
12532                                         ptype_mapping[i].sw_ptype |=
12533                                                 RTE_PTYPE_TUNNEL_L2TP;
12534                                         in_tunnel = true;
12535                                 }
12536
12537                                 break;
12538                         }
12539                 }
12540         }
12541
12542         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12543                                                 ptype_num, 0);
12544         if (ret)
12545                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12546
12547         rte_free(ptype_mapping);
12548         rte_free(ptype);
12549         return ret;
12550 }
12551
12552 void
12553 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12554                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12555 {
12556         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12557         uint32_t proto_num;
12558         struct rte_pmd_i40e_proto_info *proto;
12559         uint32_t buff_size;
12560         uint32_t i;
12561         int ret;
12562
12563         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12564             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12565                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12566                 return;
12567         }
12568
12569         /* get information about protocol number */
12570         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12571                                        (uint8_t *)&proto_num, sizeof(proto_num),
12572                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12573         if (ret) {
12574                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12575                 return;
12576         }
12577         if (!proto_num) {
12578                 PMD_DRV_LOG(INFO, "No new protocol added");
12579                 return;
12580         }
12581
12582         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12583         proto = rte_zmalloc("new_proto", buff_size, 0);
12584         if (!proto) {
12585                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12586                 return;
12587         }
12588
12589         /* get information about protocol list */
12590         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12591                                         (uint8_t *)proto, buff_size,
12592                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12593         if (ret) {
12594                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12595                 rte_free(proto);
12596                 return;
12597         }
12598
12599         /* Check if GTP is supported. */
12600         for (i = 0; i < proto_num; i++) {
12601                 if (!strncmp(proto[i].name, "GTP", 3)) {
12602                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12603                                 pf->gtp_support = true;
12604                         else
12605                                 pf->gtp_support = false;
12606                         break;
12607                 }
12608         }
12609
12610         /* Update customized pctype info */
12611         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12612                                             proto_num, proto, op);
12613         if (ret)
12614                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12615
12616         /* Update customized ptype info */
12617         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12618                                            proto_num, proto, op);
12619         if (ret)
12620                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12621
12622         rte_free(proto);
12623 }
12624
12625 /* Create a QinQ cloud filter
12626  *
12627  * The Fortville NIC has limited resources for tunnel filters,
12628  * so we can only reuse existing filters.
12629  *
12630  * In step 1 we define which Field Vector fields can be used for
12631  * filter types.
12632  * As we do not have the inner tag defined as a field,
12633  * we have to define it first, by reusing one of L1 entries.
12634  *
12635  * In step 2 we are replacing one of existing filter types with
12636  * a new one for QinQ.
12637  * As we reusing L1 and replacing L2, some of the default filter
12638  * types will disappear,which depends on L1 and L2 entries we reuse.
12639  *
12640  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12641  *
12642  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12643  *              later when we define the cloud filter.
12644  *      a.      Valid_flags.replace_cloud = 0
12645  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12646  *      c.      New_filter = 0x10
12647  *      d.      TR bit = 0xff (optional, not used here)
12648  *      e.      Buffer – 2 entries:
12649  *              i.      Byte 0 = 8 (outer vlan FV index).
12650  *                      Byte 1 = 0 (rsv)
12651  *                      Byte 2-3 = 0x0fff
12652  *              ii.     Byte 0 = 37 (inner vlan FV index).
12653  *                      Byte 1 =0 (rsv)
12654  *                      Byte 2-3 = 0x0fff
12655  *
12656  * Step 2:
12657  * 2.   Create cloud filter using two L1 filters entries: stag and
12658  *              new filter(outer vlan+ inner vlan)
12659  *      a.      Valid_flags.replace_cloud = 1
12660  *      b.      Old_filter = 1 (instead of outer IP)
12661  *      c.      New_filter = 0x10
12662  *      d.      Buffer – 2 entries:
12663  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12664  *                      Byte 1-3 = 0 (rsv)
12665  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12666  *                      Byte 9-11 = 0 (rsv)
12667  */
12668 static int
12669 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12670 {
12671         int ret = -ENOTSUP;
12672         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12673         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12674         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12675         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12676
12677         if (pf->support_multi_driver) {
12678                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12679                 return ret;
12680         }
12681
12682         /* Init */
12683         memset(&filter_replace, 0,
12684                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12685         memset(&filter_replace_buf, 0,
12686                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12687
12688         /* create L1 filter */
12689         filter_replace.old_filter_type =
12690                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12691         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12692         filter_replace.tr_bit = 0;
12693
12694         /* Prepare the buffer, 2 entries */
12695         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12696         filter_replace_buf.data[0] |=
12697                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12698         /* Field Vector 12b mask */
12699         filter_replace_buf.data[2] = 0xff;
12700         filter_replace_buf.data[3] = 0x0f;
12701         filter_replace_buf.data[4] =
12702                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12703         filter_replace_buf.data[4] |=
12704                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12705         /* Field Vector 12b mask */
12706         filter_replace_buf.data[6] = 0xff;
12707         filter_replace_buf.data[7] = 0x0f;
12708         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12709                         &filter_replace_buf);
12710         if (ret != I40E_SUCCESS)
12711                 return ret;
12712
12713         if (filter_replace.old_filter_type !=
12714             filter_replace.new_filter_type)
12715                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12716                             " original: 0x%x, new: 0x%x",
12717                             dev->device->name,
12718                             filter_replace.old_filter_type,
12719                             filter_replace.new_filter_type);
12720
12721         /* Apply the second L2 cloud filter */
12722         memset(&filter_replace, 0,
12723                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12724         memset(&filter_replace_buf, 0,
12725                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12726
12727         /* create L2 filter, input for L2 filter will be L1 filter  */
12728         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12729         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12730         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12731
12732         /* Prepare the buffer, 2 entries */
12733         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12734         filter_replace_buf.data[0] |=
12735                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12736         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12737         filter_replace_buf.data[4] |=
12738                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12739         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12740                         &filter_replace_buf);
12741         if (!ret && (filter_replace.old_filter_type !=
12742                      filter_replace.new_filter_type))
12743                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12744                             " original: 0x%x, new: 0x%x",
12745                             dev->device->name,
12746                             filter_replace.old_filter_type,
12747                             filter_replace.new_filter_type);
12748
12749         return ret;
12750 }
12751
12752 int
12753 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12754                    const struct rte_flow_action_rss *in)
12755 {
12756         if (in->key_len > RTE_DIM(out->key) ||
12757             in->queue_num > RTE_DIM(out->queue))
12758                 return -EINVAL;
12759         if (!in->key && in->key_len)
12760                 return -EINVAL;
12761         out->conf = (struct rte_flow_action_rss){
12762                 .func = in->func,
12763                 .level = in->level,
12764                 .types = in->types,
12765                 .key_len = in->key_len,
12766                 .queue_num = in->queue_num,
12767                 .queue = memcpy(out->queue, in->queue,
12768                                 sizeof(*in->queue) * in->queue_num),
12769         };
12770         if (in->key)
12771                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12772         return 0;
12773 }
12774
12775 int
12776 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12777                      const struct rte_flow_action_rss *with)
12778 {
12779         return (comp->func == with->func &&
12780                 comp->level == with->level &&
12781                 comp->types == with->types &&
12782                 comp->key_len == with->key_len &&
12783                 comp->queue_num == with->queue_num &&
12784                 !memcmp(comp->key, with->key, with->key_len) &&
12785                 !memcmp(comp->queue, with->queue,
12786                         sizeof(*with->queue) * with->queue_num));
12787 }
12788
12789 int
12790 i40e_config_rss_filter(struct i40e_pf *pf,
12791                 struct i40e_rte_flow_rss_conf *conf, bool add)
12792 {
12793         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12794         uint32_t i, lut = 0;
12795         uint16_t j, num;
12796         struct rte_eth_rss_conf rss_conf = {
12797                 .rss_key = conf->conf.key_len ?
12798                         (void *)(uintptr_t)conf->conf.key : NULL,
12799                 .rss_key_len = conf->conf.key_len,
12800                 .rss_hf = conf->conf.types,
12801         };
12802         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12803
12804         if (!add) {
12805                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12806                         i40e_pf_disable_rss(pf);
12807                         memset(rss_info, 0,
12808                                 sizeof(struct i40e_rte_flow_rss_conf));
12809                         return 0;
12810                 }
12811                 return -EINVAL;
12812         }
12813
12814         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12815          * It's necessary to calculate the actual PF queues that are configured.
12816          */
12817         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12818                 num = i40e_pf_calc_configured_queues_num(pf);
12819         else
12820                 num = pf->dev_data->nb_rx_queues;
12821
12822         num = RTE_MIN(num, conf->conf.queue_num);
12823         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12824                         num);
12825
12826         if (num == 0) {
12827                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12828                 return -ENOTSUP;
12829         }
12830
12831         /* Fill in redirection table */
12832         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12833                 if (j == num)
12834                         j = 0;
12835                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12836                         hw->func_caps.rss_table_entry_width) - 1));
12837                 if ((i & 3) == 3)
12838                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12839         }
12840
12841         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12842                 i40e_pf_disable_rss(pf);
12843                 return 0;
12844         }
12845         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12846                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12847                 /* Random default keys */
12848                 static uint32_t rss_key_default[] = {0x6b793944,
12849                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12850                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12851                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12852
12853                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12854                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12855                                                         sizeof(uint32_t);
12856                 PMD_DRV_LOG(INFO,
12857                         "No valid RSS key config for i40e, using default\n");
12858         }
12859
12860         i40e_hw_rss_hash_set(pf, &rss_conf);
12861
12862         if (i40e_rss_conf_init(rss_info, &conf->conf))
12863                 return -EINVAL;
12864
12865         return 0;
12866 }
12867
12868 RTE_INIT(i40e_init_log)
12869 {
12870         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12871         if (i40e_logtype_init >= 0)
12872                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12873         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12874         if (i40e_logtype_driver >= 0)
12875                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12876
12877 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12878         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12879         if (i40e_logtype_rx >= 0)
12880                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12881 #endif
12882
12883 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12884         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12885         if (i40e_logtype_tx >= 0)
12886                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12887 #endif
12888
12889 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12890         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12891         if (i40e_logtype_tx_free >= 0)
12892                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12893 #endif
12894 }
12895
12896 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12897                               ETH_I40E_FLOATING_VEB_ARG "=1"
12898                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12899                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12900                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12901                               ETH_I40E_USE_LATEST_VEC "=0|1");