drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 449         { .vendor_id = 0, /* sentinel */ },
 450 };
 451
 452 static const struct eth_dev_ops i40e_eth_dev_ops = {
 453         .dev_configure                = i40e_dev_configure,
 454         .dev_start                    = i40e_dev_start,
 455         .dev_stop                     = i40e_dev_stop,
 456         .dev_close                    = i40e_dev_close,
 457         .dev_reset                    = i40e_dev_reset,
 458         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 459         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 460         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 461         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 462         .dev_set_link_up              = i40e_dev_set_link_up,
 463         .dev_set_link_down            = i40e_dev_set_link_down,
 464         .link_update                  = i40e_dev_link_update,
 465         .stats_get                    = i40e_dev_stats_get,
 466         .xstats_get                   = i40e_dev_xstats_get,
 467         .xstats_get_names             = i40e_dev_xstats_get_names,
 468         .stats_reset                  = i40e_dev_stats_reset,
 469         .xstats_reset                 = i40e_dev_stats_reset,
 470         .fw_version_get               = i40e_fw_version_get,
 471         .dev_infos_get                = i40e_dev_info_get,
 472         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 473         .vlan_filter_set              = i40e_vlan_filter_set,
 474         .vlan_tpid_set                = i40e_vlan_tpid_set,
 475         .vlan_offload_set             = i40e_vlan_offload_set,
 476         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 477         .vlan_pvid_set                = i40e_vlan_pvid_set,
 478         .rx_queue_start               = i40e_dev_rx_queue_start,
 479         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 480         .tx_queue_start               = i40e_dev_tx_queue_start,
 481         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 482         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 483         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 484         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 485         .rx_queue_release             = i40e_dev_rx_queue_release,
 486         .rx_queue_count               = i40e_dev_rx_queue_count,
 487         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 488         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 489         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .filter_ctrl                  = i40e_dev_filter_ctrl,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 509         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 510         .mirror_rule_set              = i40e_mirror_rule_set,
 511         .mirror_rule_reset            = i40e_mirror_rule_reset,
 512         .timesync_enable              = i40e_timesync_enable,
 513         .timesync_disable             = i40e_timesync_disable,
 514         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 515         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 516         .get_dcb_info                 = i40e_dev_get_dcb_info,
 517         .timesync_adjust_time         = i40e_timesync_adjust_time,
 518         .timesync_read_time           = i40e_timesync_read_time,
 519         .timesync_write_time          = i40e_timesync_write_time,
 520         .get_reg                      = i40e_get_regs,
 521         .get_eeprom_length            = i40e_get_eeprom_length,
 522         .get_eeprom                   = i40e_get_eeprom,
 523         .get_module_info              = i40e_get_module_info,
 524         .get_module_eeprom            = i40e_get_module_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528         .tx_done_cleanup              = i40e_tx_done_cleanup,
 529 };
 530
 531 /* store statistics names and its offset in stats structure */
 532 struct rte_i40e_xstats_name_off {
 533         char name[RTE_ETH_XSTATS_NAME_SIZE];
 534         unsigned offset;
 535 };
 536
 537 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 538         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 539         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 540         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 541         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 542         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 543                 rx_unknown_protocol)},
 544         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 545         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 546         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 547         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 548 };
 549
 550 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 551                 sizeof(rte_i40e_stats_strings[0]))
 552
 553 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 554         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 555                 tx_dropped_link_down)},
 556         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 557         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 558                 illegal_bytes)},
 559         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 560         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 561                 mac_local_faults)},
 562         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 563                 mac_remote_faults)},
 564         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 565                 rx_length_errors)},
 566         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 567         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 568         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 569         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 570         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 571         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_127)},
 573         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_255)},
 575         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_511)},
 577         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_1023)},
 579         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 580                 rx_size_1522)},
 581         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 582                 rx_size_big)},
 583         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 584                 rx_undersize)},
 585         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_oversize)},
 587         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 588                 mac_short_packet_dropped)},
 589         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 590                 rx_fragments)},
 591         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 592         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 593         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_127)},
 595         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_255)},
 597         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_511)},
 599         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_1023)},
 601         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 602                 tx_size_1522)},
 603         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 604                 tx_size_big)},
 605         {"rx_flow_director_atr_match_packets",
 606                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 607         {"rx_flow_director_sb_match_packets",
 608                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 609         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 610                 tx_lpi_status)},
 611         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 612                 rx_lpi_status)},
 613         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 614                 tx_lpi_count)},
 615         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 616                 rx_lpi_count)},
 617 };
 618
 619 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 620                 sizeof(rte_i40e_hw_port_strings[0]))
 621
 622 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 623         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xon_rx)},
 625         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xoff_rx)},
 627 };
 628
 629 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 630                 sizeof(rte_i40e_rxq_prio_strings[0]))
 631
 632 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 633         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xon_tx)},
 635         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 636                 priority_xoff_tx)},
 637         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 638                 priority_xon_2_xoff)},
 639 };
 640
 641 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 642                 sizeof(rte_i40e_txq_prio_strings[0]))
 643
 644 static int
 645 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 646         struct rte_pci_device *pci_dev)
 647 {
 648         char name[RTE_ETH_NAME_MAX_LEN];
 649         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 650         int i, retval;
 651
 652         if (pci_dev->device.devargs) {
 653                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 654                                 &eth_da);
 655                 if (retval)
 656                         return retval;
 657         }
 658
 659         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 660                 sizeof(struct i40e_adapter),
 661                 eth_dev_pci_specific_init, pci_dev,
 662                 eth_i40e_dev_init, NULL);
 663
 664         if (retval || eth_da.nb_representor_ports < 1)
 665                 return retval;
 666
 667         /* probe VF representor ports */
 668         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 669                 pci_dev->device.name);
 670
 671         if (pf_ethdev == NULL)
 672                 return -ENODEV;
 673
 674         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 675                 struct i40e_vf_representor representor = {
 676                         .vf_id = eth_da.representor_ports[i],
 677                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 678                                 pf_ethdev->data->dev_private)->switch_domain_id,
 679                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 680                                 pf_ethdev->data->dev_private)
 681                 };
 682
 683                 /* representor port net_bdf_port */
 684                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 685                         pci_dev->device.name, eth_da.representor_ports[i]);
 686
 687                 retval = rte_eth_dev_create(&pci_dev->device, name,
 688                         sizeof(struct i40e_vf_representor), NULL, NULL,
 689                         i40e_vf_representor_init, &representor);
 690
 691                 if (retval)
 692                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 693                                 "representor %s.", name);
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 700 {
 701         struct rte_eth_dev *ethdev;
 702
 703         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 704         if (!ethdev)
 705                 return 0;
 706
 707         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 708                 return rte_eth_dev_pci_generic_remove(pci_dev,
 709                                         i40e_vf_representor_uninit);
 710         else
 711                 return rte_eth_dev_pci_generic_remove(pci_dev,
 712                                                 eth_i40e_dev_uninit);
 713 }
 714
 715 static struct rte_pci_driver rte_i40e_pmd = {
 716         .id_table = pci_id_i40e_map,
 717         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 718         .probe = eth_i40e_pci_probe,
 719         .remove = eth_i40e_pci_remove,
 720 };
 721
 722 static inline void
 723 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 724                          uint32_t reg_val)
 725 {
 726         uint32_t ori_reg_val;
 727         struct rte_eth_dev *dev;
 728
 729         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 730         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 731         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 732         if (ori_reg_val != reg_val)
 733                 PMD_DRV_LOG(WARNING,
 734                             "i40e device %s changed global register [0x%08x]."
 735                             " original: 0x%08x, new: 0x%08x",
 736                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 737 }
 738
 739 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 740 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 741 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 742
 743 #ifndef I40E_GLQF_ORT
 744 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 745 #endif
 746 #ifndef I40E_GLQF_PIT
 747 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 748 #endif
 749 #ifndef I40E_GLQF_L3_MAP
 750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 751 #endif
 752
 753 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 754 {
 755         /*
 756          * Initialize registers for parsing packet type of QinQ
 757          * This should be removed from code once proper
 758          * configuration API is added to avoid configuration conflicts
 759          * between ports of the same device.
 760          */
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 762         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 763 }
 764
 765 static inline void i40e_config_automask(struct i40e_pf *pf)
 766 {
 767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 768         uint32_t val;
 769
 770         /* INTENA flag is not auto-cleared for interrupt */
 771         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 772         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 773                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 774
 775         /* If support multi-driver, PF will use INT0. */
 776         if (!pf->support_multi_driver)
 777                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 778
 779         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 780 }
 781
 782 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 783
 784 /*
 785  * Add a ethertype filter to drop all flow control frames transmitted
 786  * from VSIs.
 787 */
 788 static void
 789 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 790 {
 791         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 792         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 793                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 794                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 795         int ret;
 796
 797         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 798                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 799                                 pf->main_vsi_seid, 0,
 800                                 TRUE, NULL, NULL);
 801         if (ret)
 802                 PMD_INIT_LOG(ERR,
 803                         "Failed to add filter to drop flow control frames from VSIs.");
 804 }
 805
 806 static int
 807 floating_veb_list_handler(__rte_unused const char *key,
 808                           const char *floating_veb_value,
 809                           void *opaque)
 810 {
 811         int idx = 0;
 812         unsigned int count = 0;
 813         char *end = NULL;
 814         int min, max;
 815         bool *vf_floating_veb = opaque;
 816
 817         while (isblank(*floating_veb_value))
 818                 floating_veb_value++;
 819
 820         /* Reset floating VEB configuration for VFs */
 821         for (idx = 0; idx < I40E_MAX_VF; idx++)
 822                 vf_floating_veb[idx] = false;
 823
 824         min = I40E_MAX_VF;
 825         do {
 826                 while (isblank(*floating_veb_value))
 827                         floating_veb_value++;
 828                 if (*floating_veb_value == '\0')
 829                         return -1;
 830                 errno = 0;
 831                 idx = strtoul(floating_veb_value, &end, 10);
 832                 if (errno || end == NULL)
 833                         return -1;
 834                 while (isblank(*end))
 835                         end++;
 836                 if (*end == '-') {
 837                         min = idx;
 838                 } else if ((*end == ';') || (*end == '\0')) {
 839                         max = idx;
 840                         if (min == I40E_MAX_VF)
 841                                 min = idx;
 842                         if (max >= I40E_MAX_VF)
 843                                 max = I40E_MAX_VF - 1;
 844                         for (idx = min; idx <= max; idx++) {
 845                                 vf_floating_veb[idx] = true;
 846                                 count++;
 847                         }
 848                         min = I40E_MAX_VF;
 849                 } else {
 850                         return -1;
 851                 }
 852                 floating_veb_value = end + 1;
 853         } while (*end != '\0');
 854
 855         if (count == 0)
 856                 return -1;
 857
 858         return 0;
 859 }
 860
 861 static void
 862 config_vf_floating_veb(struct rte_devargs *devargs,
 863                        uint16_t floating_veb,
 864                        bool *vf_floating_veb)
 865 {
 866         struct rte_kvargs *kvlist;
 867         int i;
 868         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 869
 870         if (!floating_veb)
 871                 return;
 872         /* All the VFs attach to the floating VEB by default
 873          * when the floating VEB is enabled.
 874          */
 875         for (i = 0; i < I40E_MAX_VF; i++)
 876                 vf_floating_veb[i] = true;
 877
 878         if (devargs == NULL)
 879                 return;
 880
 881         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 882         if (kvlist == NULL)
 883                 return;
 884
 885         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 886                 rte_kvargs_free(kvlist);
 887                 return;
 888         }
 889         /* When the floating_veb_list parameter exists, all the VFs
 890          * will attach to the legacy VEB firstly, then configure VFs
 891          * to the floating VEB according to the floating_veb_list.
 892          */
 893         if (rte_kvargs_process(kvlist, floating_veb_list,
 894                                floating_veb_list_handler,
 895                                vf_floating_veb) < 0) {
 896                 rte_kvargs_free(kvlist);
 897                 return;
 898         }
 899         rte_kvargs_free(kvlist);
 900 }
 901
 902 static int
 903 i40e_check_floating_handler(__rte_unused const char *key,
 904                             const char *value,
 905                             __rte_unused void *opaque)
 906 {
 907         if (strcmp(value, "1"))
 908                 return -1;
 909
 910         return 0;
 911 }
 912
 913 static int
 914 is_floating_veb_supported(struct rte_devargs *devargs)
 915 {
 916         struct rte_kvargs *kvlist;
 917         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 918
 919         if (devargs == NULL)
 920                 return 0;
 921
 922         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 923         if (kvlist == NULL)
 924                 return 0;
 925
 926         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 927                 rte_kvargs_free(kvlist);
 928                 return 0;
 929         }
 930         /* Floating VEB is enabled when there's key-value:
 931          * enable_floating_veb=1
 932          */
 933         if (rte_kvargs_process(kvlist, floating_veb_key,
 934                                i40e_check_floating_handler, NULL) < 0) {
 935                 rte_kvargs_free(kvlist);
 936                 return 0;
 937         }
 938         rte_kvargs_free(kvlist);
 939
 940         return 1;
 941 }
 942
 943 static void
 944 config_floating_veb(struct rte_eth_dev *dev)
 945 {
 946         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 949
 950         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 951
 952         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 953                 pf->floating_veb =
 954                         is_floating_veb_supported(pci_dev->device.devargs);
 955                 config_vf_floating_veb(pci_dev->device.devargs,
 956                                        pf->floating_veb,
 957                                        pf->floating_veb_list);
 958         } else {
 959                 pf->floating_veb = false;
 960         }
 961 }
 962
 963 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 964 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 965
 966 static int
 967 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 968 {
 969         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 970         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 971         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 972         int ret;
 973
 974         struct rte_hash_parameters ethertype_hash_params = {
 975                 .name = ethertype_hash_name,
 976                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 977                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 978                 .hash_func = rte_hash_crc,
 979                 .hash_func_init_val = 0,
 980                 .socket_id = rte_socket_id(),
 981         };
 982
 983         /* Initialize ethertype filter rule list and hash */
 984         TAILQ_INIT(&ethertype_rule->ethertype_list);
 985         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 986                  "ethertype_%s", dev->device->name);
 987         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 988         if (!ethertype_rule->hash_table) {
 989                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 990                 return -EINVAL;
 991         }
 992         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 993                                        sizeof(struct i40e_ethertype_filter *) *
 994                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 995                                        0);
 996         if (!ethertype_rule->hash_map) {
 997                 PMD_INIT_LOG(ERR,
 998                              "Failed to allocate memory for ethertype hash map!");
 999                 ret = -ENOMEM;
1000                 goto err_ethertype_hash_map_alloc;
1001         }
1002
1003         return 0;
1004
1005 err_ethertype_hash_map_alloc:
1006         rte_hash_free(ethertype_rule->hash_table);
1007
1008         return ret;
1009 }
1010
1011 static int
1012 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1016         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1017         int ret;
1018
1019         struct rte_hash_parameters tunnel_hash_params = {
1020                 .name = tunnel_hash_name,
1021                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1022                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1023                 .hash_func = rte_hash_crc,
1024                 .hash_func_init_val = 0,
1025                 .socket_id = rte_socket_id(),
1026         };
1027
1028         /* Initialize tunnel filter rule list and hash */
1029         TAILQ_INIT(&tunnel_rule->tunnel_list);
1030         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1031                  "tunnel_%s", dev->device->name);
1032         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1033         if (!tunnel_rule->hash_table) {
1034                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1035                 return -EINVAL;
1036         }
1037         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1038                                     sizeof(struct i40e_tunnel_filter *) *
1039                                     I40E_MAX_TUNNEL_FILTER_NUM,
1040                                     0);
1041         if (!tunnel_rule->hash_map) {
1042                 PMD_INIT_LOG(ERR,
1043                              "Failed to allocate memory for tunnel hash map!");
1044                 ret = -ENOMEM;
1045                 goto err_tunnel_hash_map_alloc;
1046         }
1047
1048         return 0;
1049
1050 err_tunnel_hash_map_alloc:
1051         rte_hash_free(tunnel_rule->hash_table);
1052
1053         return ret;
1054 }
1055
1056 static int
1057 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1058 {
1059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1060         struct i40e_fdir_info *fdir_info = &pf->fdir;
1061         char fdir_hash_name[RTE_HASH_NAMESIZE];
1062         int ret;
1063
1064         struct rte_hash_parameters fdir_hash_params = {
1065                 .name = fdir_hash_name,
1066                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1067                 .key_len = sizeof(struct i40e_fdir_input),
1068                 .hash_func = rte_hash_crc,
1069                 .hash_func_init_val = 0,
1070                 .socket_id = rte_socket_id(),
1071         };
1072
1073         /* Initialize flow director filter rule list and hash */
1074         TAILQ_INIT(&fdir_info->fdir_list);
1075         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1076                  "fdir_%s", dev->device->name);
1077         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1078         if (!fdir_info->hash_table) {
1079                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1080                 return -EINVAL;
1081         }
1082         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1083                                           sizeof(struct i40e_fdir_filter *) *
1084                                           I40E_MAX_FDIR_FILTER_NUM,
1085                                           0);
1086         if (!fdir_info->hash_map) {
1087                 PMD_INIT_LOG(ERR,
1088                              "Failed to allocate memory for fdir hash map!");
1089                 ret = -ENOMEM;
1090                 goto err_fdir_hash_map_alloc;
1091         }
1092         return 0;
1093
1094 err_fdir_hash_map_alloc:
1095         rte_hash_free(fdir_info->hash_table);
1096
1097         return ret;
1098 }
1099
1100 static void
1101 i40e_init_customized_info(struct i40e_pf *pf)
1102 {
1103         int i;
1104
1105         /* Initialize customized pctype */
1106         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1107                 pf->customized_pctype[i].index = i;
1108                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1109                 pf->customized_pctype[i].valid = false;
1110         }
1111
1112         pf->gtp_support = false;
1113         pf->esp_support = false;
1114 }
1115
1116 void
1117 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1118 {
1119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1120         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1121         struct i40e_queue_regions *info = &pf->queue_region;
1122         uint16_t i;
1123
1124         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1125                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1126
1127         memset(info, 0, sizeof(struct i40e_queue_regions));
1128 }
1129
1130 static int
1131 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1132                                const char *value,
1133                                void *opaque)
1134 {
1135         struct i40e_pf *pf;
1136         unsigned long support_multi_driver;
1137         char *end;
1138
1139         pf = (struct i40e_pf *)opaque;
1140
1141         errno = 0;
1142         support_multi_driver = strtoul(value, &end, 10);
1143         if (errno != 0 || end == value || *end != 0) {
1144                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1145                 return -(EINVAL);
1146         }
1147
1148         if (support_multi_driver == 1 || support_multi_driver == 0)
1149                 pf->support_multi_driver = (bool)support_multi_driver;
1150         else
1151                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1152                             "enable global configuration by default."
1153                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1154         return 0;
1155 }
1156
1157 static int
1158 i40e_support_multi_driver(struct rte_eth_dev *dev)
1159 {
1160         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1161         struct rte_kvargs *kvlist;
1162         int kvargs_count;
1163
1164         /* Enable global configuration by default */
1165         pf->support_multi_driver = false;
1166
1167         if (!dev->device->devargs)
1168                 return 0;
1169
1170         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1171         if (!kvlist)
1172                 return -EINVAL;
1173
1174         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1175         if (!kvargs_count) {
1176                 rte_kvargs_free(kvlist);
1177                 return 0;
1178         }
1179
1180         if (kvargs_count > 1)
1181                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1182                             "the first invalid or last valid one is used !",
1183                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1184
1185         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1186                                i40e_parse_multi_drv_handler, pf) < 0) {
1187                 rte_kvargs_free(kvlist);
1188                 return -EINVAL;
1189         }
1190
1191         rte_kvargs_free(kvlist);
1192         return 0;
1193 }
1194
1195 static int
1196 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1197                                     uint32_t reg_addr, uint64_t reg_val,
1198                                     struct i40e_asq_cmd_details *cmd_details)
1199 {
1200         uint64_t ori_reg_val;
1201         struct rte_eth_dev *dev;
1202         int ret;
1203
1204         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1205         if (ret != I40E_SUCCESS) {
1206                 PMD_DRV_LOG(ERR,
1207                             "Fail to debug read from 0x%08x",
1208                             reg_addr);
1209                 return -EIO;
1210         }
1211         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1212
1213         if (ori_reg_val != reg_val)
1214                 PMD_DRV_LOG(WARNING,
1215                             "i40e device %s changed global register [0x%08x]."
1216                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1217                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1218
1219         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1220 }
1221
1222 static int
1223 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1224                                 const char *value,
1225                                 void *opaque)
1226 {
1227         struct i40e_adapter *ad = opaque;
1228         int use_latest_vec;
1229
1230         use_latest_vec = atoi(value);
1231
1232         if (use_latest_vec != 0 && use_latest_vec != 1)
1233                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1234
1235         ad->use_latest_vec = (uint8_t)use_latest_vec;
1236
1237         return 0;
1238 }
1239
1240 static int
1241 i40e_use_latest_vec(struct rte_eth_dev *dev)
1242 {
1243         struct i40e_adapter *ad =
1244                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1245         struct rte_kvargs *kvlist;
1246         int kvargs_count;
1247
1248         ad->use_latest_vec = false;
1249
1250         if (!dev->device->devargs)
1251                 return 0;
1252
1253         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1254         if (!kvlist)
1255                 return -EINVAL;
1256
1257         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1258         if (!kvargs_count) {
1259                 rte_kvargs_free(kvlist);
1260                 return 0;
1261         }
1262
1263         if (kvargs_count > 1)
1264                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1265                             "the first invalid or last valid one is used !",
1266                             ETH_I40E_USE_LATEST_VEC);
1267
1268         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1269                                 i40e_parse_latest_vec_handler, ad) < 0) {
1270                 rte_kvargs_free(kvlist);
1271                 return -EINVAL;
1272         }
1273
1274         rte_kvargs_free(kvlist);
1275         return 0;
1276 }
1277
1278 static int
1279 read_vf_msg_config(__rte_unused const char *key,
1280                                const char *value,
1281                                void *opaque)
1282 {
1283         struct i40e_vf_msg_cfg *cfg = opaque;
1284
1285         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1286                         &cfg->ignore_second) != 3) {
1287                 memset(cfg, 0, sizeof(*cfg));
1288                 PMD_DRV_LOG(ERR, "format error! example: "
1289                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1290                 return -EINVAL;
1291         }
1292
1293         /*
1294          * If the message validation function been enabled, the 'period'
1295          * and 'ignore_second' must greater than 0.
1296          */
1297         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1298                 memset(cfg, 0, sizeof(*cfg));
1299                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1300                                 " number must be greater than 0!",
1301                                 ETH_I40E_VF_MSG_CFG);
1302                 return -EINVAL;
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int
1309 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1310                 struct i40e_vf_msg_cfg *msg_cfg)
1311 {
1312         struct rte_kvargs *kvlist;
1313         int kvargs_count;
1314         int ret = 0;
1315
1316         memset(msg_cfg, 0, sizeof(*msg_cfg));
1317
1318         if (!dev->device->devargs)
1319                 return ret;
1320
1321         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1322         if (!kvlist)
1323                 return -EINVAL;
1324
1325         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1326         if (!kvargs_count)
1327                 goto free_end;
1328
1329         if (kvargs_count > 1) {
1330                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1331                                 ETH_I40E_VF_MSG_CFG);
1332                 ret = -EINVAL;
1333                 goto free_end;
1334         }
1335
1336         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1337                         read_vf_msg_config, msg_cfg) < 0)
1338                 ret = -EINVAL;
1339
1340 free_end:
1341         rte_kvargs_free(kvlist);
1342         return ret;
1343 }
1344
1345 #define I40E_ALARM_INTERVAL 50000 /* us */
1346
1347 static int
1348 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1349 {
1350         struct rte_pci_device *pci_dev;
1351         struct rte_intr_handle *intr_handle;
1352         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1354         struct i40e_vsi *vsi;
1355         int ret;
1356         uint32_t len, val;
1357         uint8_t aq_fail = 0;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         dev->dev_ops = &i40e_eth_dev_ops;
1362         dev->rx_pkt_burst = i40e_recv_pkts;
1363         dev->tx_pkt_burst = i40e_xmit_pkts;
1364         dev->tx_pkt_prepare = i40e_prep_pkts;
1365
1366         /* for secondary processes, we don't initialise any further as primary
1367          * has already done this work. Only check we don't need a different
1368          * RX function */
1369         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1370                 i40e_set_rx_function(dev);
1371                 i40e_set_tx_function(dev);
1372                 return 0;
1373         }
1374         i40e_set_default_ptype_table(dev);
1375         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1376         intr_handle = &pci_dev->intr_handle;
1377
1378         rte_eth_copy_pci_info(dev, pci_dev);
1379
1380         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1381         pf->adapter->eth_dev = dev;
1382         pf->dev_data = dev->data;
1383
1384         hw->back = I40E_PF_TO_ADAPTER(pf);
1385         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1386         if (!hw->hw_addr) {
1387                 PMD_INIT_LOG(ERR,
1388                         "Hardware is not available, as address is NULL");
1389                 return -ENODEV;
1390         }
1391
1392         hw->vendor_id = pci_dev->id.vendor_id;
1393         hw->device_id = pci_dev->id.device_id;
1394         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1395         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1396         hw->bus.device = pci_dev->addr.devid;
1397         hw->bus.func = pci_dev->addr.function;
1398         hw->adapter_stopped = 0;
1399         hw->adapter_closed = 0;
1400
1401         /* Init switch device pointer */
1402         hw->switch_dev = NULL;
1403
1404         /*
1405          * Switch Tag value should not be identical to either the First Tag
1406          * or Second Tag values. So set something other than common Ethertype
1407          * for internal switching.
1408          */
1409         hw->switch_tag = 0xffff;
1410
1411         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1412         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1413                 PMD_INIT_LOG(ERR, "\nERROR: "
1414                         "Firmware recovery mode detected. Limiting functionality.\n"
1415                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1416                         "User Guide for details on firmware recovery mode.");
1417                 return -EIO;
1418         }
1419
1420         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1421         /* Check if need to support multi-driver */
1422         i40e_support_multi_driver(dev);
1423         /* Check if users want the latest supported vec path */
1424         i40e_use_latest_vec(dev);
1425
1426         /* Make sure all is clean before doing PF reset */
1427         i40e_clear_hw(hw);
1428
1429         /* Reset here to make sure all is clean for each PF */
1430         ret = i40e_pf_reset(hw);
1431         if (ret) {
1432                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1433                 return ret;
1434         }
1435
1436         /* Initialize the shared code (base driver) */
1437         ret = i40e_init_shared_code(hw);
1438         if (ret) {
1439                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1440                 return ret;
1441         }
1442
1443         /* Initialize the parameters for adminq */
1444         i40e_init_adminq_parameter(hw);
1445         ret = i40e_init_adminq(hw);
1446         if (ret != I40E_SUCCESS) {
1447                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1448                 return -EIO;
1449         }
1450         /* Firmware of SFP x722 does not support adminq option */
1451         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1452                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1453
1454         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1455                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1456                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1457                      ((hw->nvm.version >> 12) & 0xf),
1458                      ((hw->nvm.version >> 4) & 0xff),
1459                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1460
1461         /* Initialize the hardware */
1462         i40e_hw_init(dev);
1463
1464         i40e_config_automask(pf);
1465
1466         i40e_set_default_pctype_table(dev);
1467
1468         /*
1469          * To work around the NVM issue, initialize registers
1470          * for packet type of QinQ by software.
1471          * It should be removed once issues are fixed in NVM.
1472          */
1473         if (!pf->support_multi_driver)
1474                 i40e_GLQF_reg_init(hw);
1475
1476         /* Initialize the input set for filters (hash and fd) to default value */
1477         i40e_filter_input_set_init(pf);
1478
1479         /* initialise the L3_MAP register */
1480         if (!pf->support_multi_driver) {
1481                 ret = i40e_aq_debug_write_global_register(hw,
1482                                                    I40E_GLQF_L3_MAP(40),
1483                                                    0x00000028,  NULL);
1484                 if (ret)
1485                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1486                                      ret);
1487                 PMD_INIT_LOG(DEBUG,
1488                              "Global register 0x%08x is changed with 0x28",
1489                              I40E_GLQF_L3_MAP(40));
1490         }
1491
1492         /* Need the special FW version to support floating VEB */
1493         config_floating_veb(dev);
1494         /* Clear PXE mode */
1495         i40e_clear_pxe_mode(hw);
1496         i40e_dev_sync_phy_type(hw);
1497
1498         /*
1499          * On X710, performance number is far from the expectation on recent
1500          * firmware versions. The fix for this issue may not be integrated in
1501          * the following firmware version. So the workaround in software driver
1502          * is needed. It needs to modify the initial values of 3 internal only
1503          * registers. Note that the workaround can be removed when it is fixed
1504          * in firmware in the future.
1505          */
1506         i40e_configure_registers(hw);
1507
1508         /* Get hw capabilities */
1509         ret = i40e_get_cap(hw);
1510         if (ret != I40E_SUCCESS) {
1511                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1512                 goto err_get_capabilities;
1513         }
1514
1515         /* Initialize parameters for PF */
1516         ret = i40e_pf_parameter_init(dev);
1517         if (ret != 0) {
1518                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1519                 goto err_parameter_init;
1520         }
1521
1522         /* Initialize the queue management */
1523         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1524         if (ret < 0) {
1525                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1526                 goto err_qp_pool_init;
1527         }
1528         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1529                                 hw->func_caps.num_msix_vectors - 1);
1530         if (ret < 0) {
1531                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1532                 goto err_msix_pool_init;
1533         }
1534
1535         /* Initialize lan hmc */
1536         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1537                                 hw->func_caps.num_rx_qp, 0, 0);
1538         if (ret != I40E_SUCCESS) {
1539                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1540                 goto err_init_lan_hmc;
1541         }
1542
1543         /* Configure lan hmc */
1544         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1545         if (ret != I40E_SUCCESS) {
1546                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1547                 goto err_configure_lan_hmc;
1548         }
1549
1550         /* Get and check the mac address */
1551         i40e_get_mac_addr(hw, hw->mac.addr);
1552         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1553                 PMD_INIT_LOG(ERR, "mac address is not valid");
1554                 ret = -EIO;
1555                 goto err_get_mac_addr;
1556         }
1557         /* Copy the permanent MAC address */
1558         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1559                         (struct rte_ether_addr *)hw->mac.perm_addr);
1560
1561         /* Disable flow control */
1562         hw->fc.requested_mode = I40E_FC_NONE;
1563         i40e_set_fc(hw, &aq_fail, TRUE);
1564
1565         /* Set the global registers with default ether type value */
1566         if (!pf->support_multi_driver) {
1567                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1568                                          RTE_ETHER_TYPE_VLAN);
1569                 if (ret != I40E_SUCCESS) {
1570                         PMD_INIT_LOG(ERR,
1571                                      "Failed to set the default outer "
1572                                      "VLAN ether type");
1573                         goto err_setup_pf_switch;
1574                 }
1575         }
1576
1577         /* PF setup, which includes VSI setup */
1578         ret = i40e_pf_setup(pf);
1579         if (ret) {
1580                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1581                 goto err_setup_pf_switch;
1582         }
1583
1584         vsi = pf->main_vsi;
1585
1586         /* Disable double vlan by default */
1587         i40e_vsi_config_double_vlan(vsi, FALSE);
1588
1589         /* Disable S-TAG identification when floating_veb is disabled */
1590         if (!pf->floating_veb) {
1591                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1592                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1593                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1594                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1595                 }
1596         }
1597
1598         if (!vsi->max_macaddrs)
1599                 len = RTE_ETHER_ADDR_LEN;
1600         else
1601                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1602
1603         /* Should be after VSI initialized */
1604         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1605         if (!dev->data->mac_addrs) {
1606                 PMD_INIT_LOG(ERR,
1607                         "Failed to allocated memory for storing mac address");
1608                 goto err_mac_alloc;
1609         }
1610         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1611                                         &dev->data->mac_addrs[0]);
1612
1613         /* Pass the information to the rte_eth_dev_close() that it should also
1614          * release the private port resources.
1615          */
1616         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1617
1618         /* Init dcb to sw mode by default */
1619         ret = i40e_dcb_init_configure(dev, TRUE);
1620         if (ret != I40E_SUCCESS) {
1621                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1622                 pf->flags &= ~I40E_FLAG_DCB;
1623         }
1624         /* Update HW struct after DCB configuration */
1625         i40e_get_cap(hw);
1626
1627         /* initialize pf host driver to setup SRIOV resource if applicable */
1628         i40e_pf_host_init(dev);
1629
1630         /* register callback func to eal lib */
1631         rte_intr_callback_register(intr_handle,
1632                                    i40e_dev_interrupt_handler, dev);
1633
1634         /* configure and enable device interrupt */
1635         i40e_pf_config_irq0(hw, TRUE);
1636         i40e_pf_enable_irq0(hw);
1637
1638         /* enable uio intr after callback register */
1639         rte_intr_enable(intr_handle);
1640
1641         /* By default disable flexible payload in global configuration */
1642         if (!pf->support_multi_driver)
1643                 i40e_flex_payload_reg_set_default(hw);
1644
1645         /*
1646          * Add an ethertype filter to drop all flow control frames transmitted
1647          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1648          * frames to wire.
1649          */
1650         i40e_add_tx_flow_control_drop_filter(pf);
1651
1652         /* Set the max frame size to 0x2600 by default,
1653          * in case other drivers changed the default value.
1654          */
1655         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1656
1657         /* initialize mirror rule list */
1658         TAILQ_INIT(&pf->mirror_list);
1659
1660         /* initialize RSS rule list */
1661         TAILQ_INIT(&pf->rss_config_list);
1662
1663         /* initialize Traffic Manager configuration */
1664         i40e_tm_conf_init(dev);
1665
1666         /* Initialize customized information */
1667         i40e_init_customized_info(pf);
1668
1669         ret = i40e_init_ethtype_filter_list(dev);
1670         if (ret < 0)
1671                 goto err_init_ethtype_filter_list;
1672         ret = i40e_init_tunnel_filter_list(dev);
1673         if (ret < 0)
1674                 goto err_init_tunnel_filter_list;
1675         ret = i40e_init_fdir_filter_list(dev);
1676         if (ret < 0)
1677                 goto err_init_fdir_filter_list;
1678
1679         /* initialize queue region configuration */
1680         i40e_init_queue_region_conf(dev);
1681
1682         /* initialize RSS configuration from rte_flow */
1683         memset(&pf->rss_info, 0,
1684                 sizeof(struct i40e_rte_flow_rss_conf));
1685
1686         /* reset all stats of the device, including pf and main vsi */
1687         i40e_dev_stats_reset(dev);
1688
1689         return 0;
1690
1691 err_init_fdir_filter_list:
1692         rte_free(pf->tunnel.hash_table);
1693         rte_free(pf->tunnel.hash_map);
1694 err_init_tunnel_filter_list:
1695         rte_free(pf->ethertype.hash_table);
1696         rte_free(pf->ethertype.hash_map);
1697 err_init_ethtype_filter_list:
1698         rte_free(dev->data->mac_addrs);
1699         dev->data->mac_addrs = NULL;
1700 err_mac_alloc:
1701         i40e_vsi_release(pf->main_vsi);
1702 err_setup_pf_switch:
1703 err_get_mac_addr:
1704 err_configure_lan_hmc:
1705         (void)i40e_shutdown_lan_hmc(hw);
1706 err_init_lan_hmc:
1707         i40e_res_pool_destroy(&pf->msix_pool);
1708 err_msix_pool_init:
1709         i40e_res_pool_destroy(&pf->qp_pool);
1710 err_qp_pool_init:
1711 err_parameter_init:
1712 err_get_capabilities:
1713         (void)i40e_shutdown_adminq(hw);
1714
1715         return ret;
1716 }
1717
1718 static void
1719 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1720 {
1721         struct i40e_ethertype_filter *p_ethertype;
1722         struct i40e_ethertype_rule *ethertype_rule;
1723
1724         ethertype_rule = &pf->ethertype;
1725         /* Remove all ethertype filter rules and hash */
1726         if (ethertype_rule->hash_map)
1727                 rte_free(ethertype_rule->hash_map);
1728         if (ethertype_rule->hash_table)
1729                 rte_hash_free(ethertype_rule->hash_table);
1730
1731         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1732                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1733                              p_ethertype, rules);
1734                 rte_free(p_ethertype);
1735         }
1736 }
1737
1738 static void
1739 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1740 {
1741         struct i40e_tunnel_filter *p_tunnel;
1742         struct i40e_tunnel_rule *tunnel_rule;
1743
1744         tunnel_rule = &pf->tunnel;
1745         /* Remove all tunnel director rules and hash */
1746         if (tunnel_rule->hash_map)
1747                 rte_free(tunnel_rule->hash_map);
1748         if (tunnel_rule->hash_table)
1749                 rte_hash_free(tunnel_rule->hash_table);
1750
1751         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1752                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1753                 rte_free(p_tunnel);
1754         }
1755 }
1756
1757 static void
1758 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1759 {
1760         struct i40e_fdir_filter *p_fdir;
1761         struct i40e_fdir_info *fdir_info;
1762
1763         fdir_info = &pf->fdir;
1764         /* Remove all flow director rules and hash */
1765         if (fdir_info->hash_map)
1766                 rte_free(fdir_info->hash_map);
1767         if (fdir_info->hash_table)
1768                 rte_hash_free(fdir_info->hash_table);
1769
1770         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1771                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1772                 rte_free(p_fdir);
1773         }
1774 }
1775
1776 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1777 {
1778         /*
1779          * Disable by default flexible payload
1780          * for corresponding L2/L3/L4 layers.
1781          */
1782         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1783         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1784         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1785 }
1786
1787 static int
1788 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1789 {
1790         struct i40e_hw *hw;
1791
1792         PMD_INIT_FUNC_TRACE();
1793
1794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1795                 return 0;
1796
1797         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798
1799         if (hw->adapter_closed == 0)
1800                 i40e_dev_close(dev);
1801
1802         return 0;
1803 }
1804
1805 static int
1806 i40e_dev_configure(struct rte_eth_dev *dev)
1807 {
1808         struct i40e_adapter *ad =
1809                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1813         int i, ret;
1814
1815         ret = i40e_dev_sync_phy_type(hw);
1816         if (ret)
1817                 return ret;
1818
1819         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1820          * bulk allocation or vector Rx preconditions we will reset it.
1821          */
1822         ad->rx_bulk_alloc_allowed = true;
1823         ad->rx_vec_allowed = true;
1824         ad->tx_simple_allowed = true;
1825         ad->tx_vec_allowed = true;
1826
1827         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1828                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1829
1830         /* Only legacy filter API needs the following fdir config. So when the
1831          * legacy filter API is deprecated, the following codes should also be
1832          * removed.
1833          */
1834         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1835                 ret = i40e_fdir_setup(pf);
1836                 if (ret != I40E_SUCCESS) {
1837                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1838                         return -ENOTSUP;
1839                 }
1840                 ret = i40e_fdir_configure(dev);
1841                 if (ret < 0) {
1842                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1843                         goto err;
1844                 }
1845         } else
1846                 i40e_fdir_teardown(pf);
1847
1848         ret = i40e_dev_init_vlan(dev);
1849         if (ret < 0)
1850                 goto err;
1851
1852         /* VMDQ setup.
1853          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1854          *  RSS setting have different requirements.
1855          *  General PMD driver call sequence are NIC init, configure,
1856          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1857          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1858          *  applicable. So, VMDQ setting has to be done before
1859          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1860          *  For RSS setting, it will try to calculate actual configured RX queue
1861          *  number, which will be available after rx_queue_setup(). dev_start()
1862          *  function is good to place RSS setup.
1863          */
1864         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1865                 ret = i40e_vmdq_setup(dev);
1866                 if (ret)
1867                         goto err;
1868         }
1869
1870         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1871                 ret = i40e_dcb_setup(dev);
1872                 if (ret) {
1873                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1874                         goto err_dcb;
1875                 }
1876         }
1877
1878         TAILQ_INIT(&pf->flow_list);
1879
1880         return 0;
1881
1882 err_dcb:
1883         /* need to release vmdq resource if exists */
1884         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1885                 i40e_vsi_release(pf->vmdq[i].vsi);
1886                 pf->vmdq[i].vsi = NULL;
1887         }
1888         rte_free(pf->vmdq);
1889         pf->vmdq = NULL;
1890 err:
1891         /* Need to release fdir resource if exists.
1892          * Only legacy filter API needs the following fdir config. So when the
1893          * legacy filter API is deprecated, the following code should also be
1894          * removed.
1895          */
1896         i40e_fdir_teardown(pf);
1897         return ret;
1898 }
1899
1900 void
1901 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1902 {
1903         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1905         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1906         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1907         uint16_t msix_vect = vsi->msix_intr;
1908         uint16_t i;
1909
1910         for (i = 0; i < vsi->nb_qps; i++) {
1911                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1912                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1913                 rte_wmb();
1914         }
1915
1916         if (vsi->type != I40E_VSI_SRIOV) {
1917                 if (!rte_intr_allow_others(intr_handle)) {
1918                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1919                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1920                         I40E_WRITE_REG(hw,
1921                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1922                                        0);
1923                 } else {
1924                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1925                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1926                         I40E_WRITE_REG(hw,
1927                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1928                                                        msix_vect - 1), 0);
1929                 }
1930         } else {
1931                 uint32_t reg;
1932                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1933                         vsi->user_param + (msix_vect - 1);
1934
1935                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1936                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1937         }
1938         I40E_WRITE_FLUSH(hw);
1939 }
1940
1941 static void
1942 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1943                        int base_queue, int nb_queue,
1944                        uint16_t itr_idx)
1945 {
1946         int i;
1947         uint32_t val;
1948         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1949         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1950
1951         /* Bind all RX queues to allocated MSIX interrupt */
1952         for (i = 0; i < nb_queue; i++) {
1953                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1954                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1955                         ((base_queue + i + 1) <<
1956                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1957                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1958                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1959
1960                 if (i == nb_queue - 1)
1961                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1962                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1963         }
1964
1965         /* Write first RX queue to Link list register as the head element */
1966         if (vsi->type != I40E_VSI_SRIOV) {
1967                 uint16_t interval =
1968                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1969
1970                 if (msix_vect == I40E_MISC_VEC_ID) {
1971                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1972                                        (base_queue <<
1973                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1974                                        (0x0 <<
1975                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1976                         I40E_WRITE_REG(hw,
1977                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1978                                        interval);
1979                 } else {
1980                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1981                                        (base_queue <<
1982                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1983                                        (0x0 <<
1984                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1985                         I40E_WRITE_REG(hw,
1986                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1987                                                        msix_vect - 1),
1988                                        interval);
1989                 }
1990         } else {
1991                 uint32_t reg;
1992
1993                 if (msix_vect == I40E_MISC_VEC_ID) {
1994                         I40E_WRITE_REG(hw,
1995                                        I40E_VPINT_LNKLST0(vsi->user_param),
1996                                        (base_queue <<
1997                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1998                                        (0x0 <<
1999                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2000                 } else {
2001                         /* num_msix_vectors_vf needs to minus irq0 */
2002                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2003                                 vsi->user_param + (msix_vect - 1);
2004
2005                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2006                                        (base_queue <<
2007                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2008                                        (0x0 <<
2009                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2010                 }
2011         }
2012
2013         I40E_WRITE_FLUSH(hw);
2014 }
2015
2016 void
2017 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2018 {
2019         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2020         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2021         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2022         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2023         uint16_t msix_vect = vsi->msix_intr;
2024         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2025         uint16_t queue_idx = 0;
2026         int record = 0;
2027         int i;
2028
2029         for (i = 0; i < vsi->nb_qps; i++) {
2030                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2031                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2032         }
2033
2034         /* VF bind interrupt */
2035         if (vsi->type == I40E_VSI_SRIOV) {
2036                 __vsi_queues_bind_intr(vsi, msix_vect,
2037                                        vsi->base_queue, vsi->nb_qps,
2038                                        itr_idx);
2039                 return;
2040         }
2041
2042         /* PF & VMDq bind interrupt */
2043         if (rte_intr_dp_is_en(intr_handle)) {
2044                 if (vsi->type == I40E_VSI_MAIN) {
2045                         queue_idx = 0;
2046                         record = 1;
2047                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2048                         struct i40e_vsi *main_vsi =
2049                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2050                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2051                         record = 1;
2052                 }
2053         }
2054
2055         for (i = 0; i < vsi->nb_used_qps; i++) {
2056                 if (nb_msix <= 1) {
2057                         if (!rte_intr_allow_others(intr_handle))
2058                                 /* allow to share MISC_VEC_ID */
2059                                 msix_vect = I40E_MISC_VEC_ID;
2060
2061                         /* no enough msix_vect, map all to one */
2062                         __vsi_queues_bind_intr(vsi, msix_vect,
2063                                                vsi->base_queue + i,
2064                                                vsi->nb_used_qps - i,
2065                                                itr_idx);
2066                         for (; !!record && i < vsi->nb_used_qps; i++)
2067                                 intr_handle->intr_vec[queue_idx + i] =
2068                                         msix_vect;
2069                         break;
2070                 }
2071                 /* 1:1 queue/msix_vect mapping */
2072                 __vsi_queues_bind_intr(vsi, msix_vect,
2073                                        vsi->base_queue + i, 1,
2074                                        itr_idx);
2075                 if (!!record)
2076                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2077
2078                 msix_vect++;
2079                 nb_msix--;
2080         }
2081 }
2082
2083 static void
2084 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2085 {
2086         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2087         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2088         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2089         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2090         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2091         uint16_t msix_intr, i;
2092
2093         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2094                 for (i = 0; i < vsi->nb_msix; i++) {
2095                         msix_intr = vsi->msix_intr + i;
2096                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2097                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2098                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2099                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2100                 }
2101         else
2102                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2103                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2104                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2105                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2106
2107         I40E_WRITE_FLUSH(hw);
2108 }
2109
2110 static void
2111 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2112 {
2113         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2114         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2115         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2116         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2117         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2118         uint16_t msix_intr, i;
2119
2120         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2121                 for (i = 0; i < vsi->nb_msix; i++) {
2122                         msix_intr = vsi->msix_intr + i;
2123                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2124                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2125                 }
2126         else
2127                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2128                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2129
2130         I40E_WRITE_FLUSH(hw);
2131 }
2132
2133 static inline uint8_t
2134 i40e_parse_link_speeds(uint16_t link_speeds)
2135 {
2136         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2137
2138         if (link_speeds & ETH_LINK_SPEED_40G)
2139                 link_speed |= I40E_LINK_SPEED_40GB;
2140         if (link_speeds & ETH_LINK_SPEED_25G)
2141                 link_speed |= I40E_LINK_SPEED_25GB;
2142         if (link_speeds & ETH_LINK_SPEED_20G)
2143                 link_speed |= I40E_LINK_SPEED_20GB;
2144         if (link_speeds & ETH_LINK_SPEED_10G)
2145                 link_speed |= I40E_LINK_SPEED_10GB;
2146         if (link_speeds & ETH_LINK_SPEED_1G)
2147                 link_speed |= I40E_LINK_SPEED_1GB;
2148         if (link_speeds & ETH_LINK_SPEED_100M)
2149                 link_speed |= I40E_LINK_SPEED_100MB;
2150
2151         return link_speed;
2152 }
2153
2154 static int
2155 i40e_phy_conf_link(struct i40e_hw *hw,
2156                    uint8_t abilities,
2157                    uint8_t force_speed,
2158                    bool is_up)
2159 {
2160         enum i40e_status_code status;
2161         struct i40e_aq_get_phy_abilities_resp phy_ab;
2162         struct i40e_aq_set_phy_config phy_conf;
2163         enum i40e_aq_phy_type cnt;
2164         uint8_t avail_speed;
2165         uint32_t phy_type_mask = 0;
2166
2167         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2168                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2169                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2170                         I40E_AQ_PHY_FLAG_LOW_POWER;
2171         int ret = -ENOTSUP;
2172
2173         /* To get phy capabilities of available speeds. */
2174         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2175                                               NULL);
2176         if (status) {
2177                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2178                                 status);
2179                 return ret;
2180         }
2181         avail_speed = phy_ab.link_speed;
2182
2183         /* To get the current phy config. */
2184         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2185                                               NULL);
2186         if (status) {
2187                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2188                                 status);
2189                 return ret;
2190         }
2191
2192         /* If link needs to go up and it is in autoneg mode the speed is OK,
2193          * no need to set up again.
2194          */
2195         if (is_up && phy_ab.phy_type != 0 &&
2196                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2197                      phy_ab.link_speed != 0)
2198                 return I40E_SUCCESS;
2199
2200         memset(&phy_conf, 0, sizeof(phy_conf));
2201
2202         /* bits 0-2 use the values from get_phy_abilities_resp */
2203         abilities &= ~mask;
2204         abilities |= phy_ab.abilities & mask;
2205
2206         phy_conf.abilities = abilities;
2207
2208         /* If link needs to go up, but the force speed is not supported,
2209          * Warn users and config the default available speeds.
2210          */
2211         if (is_up && !(force_speed & avail_speed)) {
2212                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2213                 phy_conf.link_speed = avail_speed;
2214         } else {
2215                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2216         }
2217
2218         /* PHY type mask needs to include each type except PHY type extension */
2219         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2220                 phy_type_mask |= 1 << cnt;
2221
2222         /* use get_phy_abilities_resp value for the rest */
2223         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2224         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2225                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2226                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2227         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2228         phy_conf.eee_capability = phy_ab.eee_capability;
2229         phy_conf.eeer = phy_ab.eeer_val;
2230         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2231
2232         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2233                     phy_ab.abilities, phy_ab.link_speed);
2234         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2235                     phy_conf.abilities, phy_conf.link_speed);
2236
2237         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2238         if (status)
2239                 return ret;
2240
2241         return I40E_SUCCESS;
2242 }
2243
2244 static int
2245 i40e_apply_link_speed(struct rte_eth_dev *dev)
2246 {
2247         uint8_t speed;
2248         uint8_t abilities = 0;
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct rte_eth_conf *conf = &dev->data->dev_conf;
2251
2252         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2253                      I40E_AQ_PHY_LINK_ENABLED;
2254
2255         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2256                 conf->link_speeds = ETH_LINK_SPEED_40G |
2257                                     ETH_LINK_SPEED_25G |
2258                                     ETH_LINK_SPEED_20G |
2259                                     ETH_LINK_SPEED_10G |
2260                                     ETH_LINK_SPEED_1G |
2261                                     ETH_LINK_SPEED_100M;
2262
2263                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2264         } else {
2265                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2266         }
2267         speed = i40e_parse_link_speeds(conf->link_speeds);
2268
2269         return i40e_phy_conf_link(hw, abilities, speed, true);
2270 }
2271
2272 static int
2273 i40e_dev_start(struct rte_eth_dev *dev)
2274 {
2275         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277         struct i40e_vsi *main_vsi = pf->main_vsi;
2278         int ret, i;
2279         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2280         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2281         uint32_t intr_vector = 0;
2282         struct i40e_vsi *vsi;
2283
2284         hw->adapter_stopped = 0;
2285
2286         rte_intr_disable(intr_handle);
2287
2288         if ((rte_intr_cap_multiple(intr_handle) ||
2289              !RTE_ETH_DEV_SRIOV(dev).active) &&
2290             dev->data->dev_conf.intr_conf.rxq != 0) {
2291                 intr_vector = dev->data->nb_rx_queues;
2292                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2293                 if (ret)
2294                         return ret;
2295         }
2296
2297         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2298                 intr_handle->intr_vec =
2299                         rte_zmalloc("intr_vec",
2300                                     dev->data->nb_rx_queues * sizeof(int),
2301                                     0);
2302                 if (!intr_handle->intr_vec) {
2303                         PMD_INIT_LOG(ERR,
2304                                 "Failed to allocate %d rx_queues intr_vec",
2305                                 dev->data->nb_rx_queues);
2306                         return -ENOMEM;
2307                 }
2308         }
2309
2310         /* Initialize VSI */
2311         ret = i40e_dev_rxtx_init(pf);
2312         if (ret != I40E_SUCCESS) {
2313                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2314                 goto err_up;
2315         }
2316
2317         /* Map queues with MSIX interrupt */
2318         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2319                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2320         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2321         i40e_vsi_enable_queues_intr(main_vsi);
2322
2323         /* Map VMDQ VSI queues with MSIX interrupt */
2324         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2325                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2326                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2327                                           I40E_ITR_INDEX_DEFAULT);
2328                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2329         }
2330
2331         /* enable FDIR MSIX interrupt */
2332         if (pf->fdir.fdir_vsi) {
2333                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2334                                           I40E_ITR_INDEX_NONE);
2335                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2336         }
2337
2338         /* Enable all queues which have been configured */
2339         ret = i40e_dev_switch_queues(pf, TRUE);
2340         if (ret != I40E_SUCCESS) {
2341                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2342                 goto err_up;
2343         }
2344
2345         /* Enable receiving broadcast packets */
2346         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2347         if (ret != I40E_SUCCESS)
2348                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2349
2350         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2351                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2352                                                 true, NULL);
2353                 if (ret != I40E_SUCCESS)
2354                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2355         }
2356
2357         /* Enable the VLAN promiscuous mode. */
2358         if (pf->vfs) {
2359                 for (i = 0; i < pf->vf_num; i++) {
2360                         vsi = pf->vfs[i].vsi;
2361                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2362                                                      true, NULL);
2363                 }
2364         }
2365
2366         /* Enable mac loopback mode */
2367         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2368             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2369                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2370                 if (ret != I40E_SUCCESS) {
2371                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2372                         goto err_up;
2373                 }
2374         }
2375
2376         /* Apply link configure */
2377         ret = i40e_apply_link_speed(dev);
2378         if (I40E_SUCCESS != ret) {
2379                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2380                 goto err_up;
2381         }
2382
2383         if (!rte_intr_allow_others(intr_handle)) {
2384                 rte_intr_callback_unregister(intr_handle,
2385                                              i40e_dev_interrupt_handler,
2386                                              (void *)dev);
2387                 /* configure and enable device interrupt */
2388                 i40e_pf_config_irq0(hw, FALSE);
2389                 i40e_pf_enable_irq0(hw);
2390
2391                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2392                         PMD_INIT_LOG(INFO,
2393                                 "lsc won't enable because of no intr multiplex");
2394         } else {
2395                 ret = i40e_aq_set_phy_int_mask(hw,
2396                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2397                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2398                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2399                 if (ret != I40E_SUCCESS)
2400                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2401
2402                 /* Call get_link_info aq commond to enable/disable LSE */
2403                 i40e_dev_link_update(dev, 0);
2404         }
2405
2406         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2407                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2408                                   i40e_dev_alarm_handler, dev);
2409         } else {
2410                 /* enable uio intr after callback register */
2411                 rte_intr_enable(intr_handle);
2412         }
2413
2414         i40e_filter_restore(pf);
2415
2416         if (pf->tm_conf.root && !pf->tm_conf.committed)
2417                 PMD_DRV_LOG(WARNING,
2418                             "please call hierarchy_commit() "
2419                             "before starting the port");
2420
2421         return I40E_SUCCESS;
2422
2423 err_up:
2424         i40e_dev_switch_queues(pf, FALSE);
2425         i40e_dev_clear_queues(dev);
2426
2427         return ret;
2428 }
2429
2430 static void
2431 i40e_dev_stop(struct rte_eth_dev *dev)
2432 {
2433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct i40e_vsi *main_vsi = pf->main_vsi;
2436         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2437         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2438         int i;
2439
2440         if (hw->adapter_stopped == 1)
2441                 return;
2442
2443         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2444                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2445                 rte_intr_enable(intr_handle);
2446         }
2447
2448         /* Disable all queues */
2449         i40e_dev_switch_queues(pf, FALSE);
2450
2451         /* un-map queues with interrupt registers */
2452         i40e_vsi_disable_queues_intr(main_vsi);
2453         i40e_vsi_queues_unbind_intr(main_vsi);
2454
2455         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2456                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2457                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2458         }
2459
2460         if (pf->fdir.fdir_vsi) {
2461                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2462                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2463         }
2464         /* Clear all queues and release memory */
2465         i40e_dev_clear_queues(dev);
2466
2467         /* Set link down */
2468         i40e_dev_set_link_down(dev);
2469
2470         if (!rte_intr_allow_others(intr_handle))
2471                 /* resume to the default handler */
2472                 rte_intr_callback_register(intr_handle,
2473                                            i40e_dev_interrupt_handler,
2474                                            (void *)dev);
2475
2476         /* Clean datapath event and queue/vec mapping */
2477         rte_intr_efd_disable(intr_handle);
2478         if (intr_handle->intr_vec) {
2479                 rte_free(intr_handle->intr_vec);
2480                 intr_handle->intr_vec = NULL;
2481         }
2482
2483         /* reset hierarchy commit */
2484         pf->tm_conf.committed = false;
2485
2486         hw->adapter_stopped = 1;
2487
2488         pf->adapter->rss_reta_updated = 0;
2489 }
2490
2491 static void
2492 i40e_dev_close(struct rte_eth_dev *dev)
2493 {
2494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2495         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2498         struct i40e_mirror_rule *p_mirror;
2499         struct i40e_filter_control_settings settings;
2500         struct rte_flow *p_flow;
2501         uint32_t reg;
2502         int i;
2503         int ret;
2504         uint8_t aq_fail = 0;
2505         int retries = 0;
2506
2507         PMD_INIT_FUNC_TRACE();
2508
2509         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2510         if (ret)
2511                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2512
2513
2514         i40e_dev_stop(dev);
2515
2516         /* Remove all mirror rules */
2517         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2518                 ret = i40e_aq_del_mirror_rule(hw,
2519                                               pf->main_vsi->veb->seid,
2520                                               p_mirror->rule_type,
2521                                               p_mirror->entries,
2522                                               p_mirror->num_entries,
2523                                               p_mirror->id);
2524                 if (ret < 0)
2525                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2526                                     "status = %d, aq_err = %d.", ret,
2527                                     hw->aq.asq_last_status);
2528
2529                 /* remove mirror software resource anyway */
2530                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2531                 rte_free(p_mirror);
2532                 pf->nb_mirror_rule--;
2533         }
2534
2535         i40e_dev_free_queues(dev);
2536
2537         /* Disable interrupt */
2538         i40e_pf_disable_irq0(hw);
2539         rte_intr_disable(intr_handle);
2540
2541         /*
2542          * Only legacy filter API needs the following fdir config. So when the
2543          * legacy filter API is deprecated, the following code should also be
2544          * removed.
2545          */
2546         i40e_fdir_teardown(pf);
2547
2548         /* shutdown and destroy the HMC */
2549         i40e_shutdown_lan_hmc(hw);
2550
2551         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2552                 i40e_vsi_release(pf->vmdq[i].vsi);
2553                 pf->vmdq[i].vsi = NULL;
2554         }
2555         rte_free(pf->vmdq);
2556         pf->vmdq = NULL;
2557
2558         /* release all the existing VSIs and VEBs */
2559         i40e_vsi_release(pf->main_vsi);
2560
2561         /* shutdown the adminq */
2562         i40e_aq_queue_shutdown(hw, true);
2563         i40e_shutdown_adminq(hw);
2564
2565         i40e_res_pool_destroy(&pf->qp_pool);
2566         i40e_res_pool_destroy(&pf->msix_pool);
2567
2568         /* Disable flexible payload in global configuration */
2569         if (!pf->support_multi_driver)
2570                 i40e_flex_payload_reg_set_default(hw);
2571
2572         /* force a PF reset to clean anything leftover */
2573         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2574         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2575                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2576         I40E_WRITE_FLUSH(hw);
2577
2578         dev->dev_ops = NULL;
2579         dev->rx_pkt_burst = NULL;
2580         dev->tx_pkt_burst = NULL;
2581
2582         /* Clear PXE mode */
2583         i40e_clear_pxe_mode(hw);
2584
2585         /* Unconfigure filter control */
2586         memset(&settings, 0, sizeof(settings));
2587         ret = i40e_set_filter_control(hw, &settings);
2588         if (ret)
2589                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2590                                         ret);
2591
2592         /* Disable flow control */
2593         hw->fc.requested_mode = I40E_FC_NONE;
2594         i40e_set_fc(hw, &aq_fail, TRUE);
2595
2596         /* uninitialize pf host driver */
2597         i40e_pf_host_uninit(dev);
2598
2599         do {
2600                 ret = rte_intr_callback_unregister(intr_handle,
2601                                 i40e_dev_interrupt_handler, dev);
2602                 if (ret >= 0 || ret == -ENOENT) {
2603                         break;
2604                 } else if (ret != -EAGAIN) {
2605                         PMD_INIT_LOG(ERR,
2606                                  "intr callback unregister failed: %d",
2607                                  ret);
2608                 }
2609                 i40e_msec_delay(500);
2610         } while (retries++ < 5);
2611
2612         i40e_rm_ethtype_filter_list(pf);
2613         i40e_rm_tunnel_filter_list(pf);
2614         i40e_rm_fdir_filter_list(pf);
2615
2616         /* Remove all flows */
2617         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2618                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2619                 rte_free(p_flow);
2620         }
2621
2622         /* Remove all Traffic Manager configuration */
2623         i40e_tm_conf_uninit(dev);
2624
2625         hw->adapter_closed = 1;
2626 }
2627
2628 /*
2629  * Reset PF device only to re-initialize resources in PMD layer
2630  */
2631 static int
2632 i40e_dev_reset(struct rte_eth_dev *dev)
2633 {
2634         int ret;
2635
2636         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2637          * its VF to make them align with it. The detailed notification
2638          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2639          * To avoid unexpected behavior in VF, currently reset of PF with
2640          * SR-IOV activation is not supported. It might be supported later.
2641          */
2642         if (dev->data->sriov.active)
2643                 return -ENOTSUP;
2644
2645         ret = eth_i40e_dev_uninit(dev);
2646         if (ret)
2647                 return ret;
2648
2649         ret = eth_i40e_dev_init(dev, NULL);
2650
2651         return ret;
2652 }
2653
2654 static int
2655 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2656 {
2657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2659         struct i40e_vsi *vsi = pf->main_vsi;
2660         int status;
2661
2662         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2663                                                      true, NULL, true);
2664         if (status != I40E_SUCCESS) {
2665                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2666                 return -EAGAIN;
2667         }
2668
2669         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2670                                                         TRUE, NULL);
2671         if (status != I40E_SUCCESS) {
2672                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2673                 /* Rollback unicast promiscuous mode */
2674                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2675                                                     false, NULL, true);
2676                 return -EAGAIN;
2677         }
2678
2679         return 0;
2680 }
2681
2682 static int
2683 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2684 {
2685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2686         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2687         struct i40e_vsi *vsi = pf->main_vsi;
2688         int status;
2689
2690         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2691                                                      false, NULL, true);
2692         if (status != I40E_SUCCESS) {
2693                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2694                 return -EAGAIN;
2695         }
2696
2697         /* must remain in all_multicast mode */
2698         if (dev->data->all_multicast == 1)
2699                 return 0;
2700
2701         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2702                                                         false, NULL);
2703         if (status != I40E_SUCCESS) {
2704                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2705                 /* Rollback unicast promiscuous mode */
2706                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2707                                                     true, NULL, true);
2708                 return -EAGAIN;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int
2715 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2716 {
2717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2719         struct i40e_vsi *vsi = pf->main_vsi;
2720         int ret;
2721
2722         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2723         if (ret != I40E_SUCCESS) {
2724                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2725                 return -EAGAIN;
2726         }
2727
2728         return 0;
2729 }
2730
2731 static int
2732 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2733 {
2734         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2736         struct i40e_vsi *vsi = pf->main_vsi;
2737         int ret;
2738
2739         if (dev->data->promiscuous == 1)
2740                 return 0; /* must remain in all_multicast mode */
2741
2742         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2743                                 vsi->seid, FALSE, NULL);
2744         if (ret != I40E_SUCCESS) {
2745                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2746                 return -EAGAIN;
2747         }
2748
2749         return 0;
2750 }
2751
2752 /*
2753  * Set device link up.
2754  */
2755 static int
2756 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2757 {
2758         /* re-apply link speed setting */
2759         return i40e_apply_link_speed(dev);
2760 }
2761
2762 /*
2763  * Set device link down.
2764  */
2765 static int
2766 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2767 {
2768         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2769         uint8_t abilities = 0;
2770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2771
2772         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2773         return i40e_phy_conf_link(hw, abilities, speed, false);
2774 }
2775
2776 static __rte_always_inline void
2777 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2778 {
2779 /* Link status registers and values*/
2780 #define I40E_PRTMAC_LINKSTA             0x001E2420
2781 #define I40E_REG_LINK_UP                0x40000080
2782 #define I40E_PRTMAC_MACC                0x001E24E0
2783 #define I40E_REG_MACC_25GB              0x00020000
2784 #define I40E_REG_SPEED_MASK             0x38000000
2785 #define I40E_REG_SPEED_0                0x00000000
2786 #define I40E_REG_SPEED_1                0x08000000
2787 #define I40E_REG_SPEED_2                0x10000000
2788 #define I40E_REG_SPEED_3                0x18000000
2789 #define I40E_REG_SPEED_4                0x20000000
2790         uint32_t link_speed;
2791         uint32_t reg_val;
2792
2793         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2794         link_speed = reg_val & I40E_REG_SPEED_MASK;
2795         reg_val &= I40E_REG_LINK_UP;
2796         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2797
2798         if (unlikely(link->link_status == 0))
2799                 return;
2800
2801         /* Parse the link status */
2802         switch (link_speed) {
2803         case I40E_REG_SPEED_0:
2804                 link->link_speed = ETH_SPEED_NUM_100M;
2805                 break;
2806         case I40E_REG_SPEED_1:
2807                 link->link_speed = ETH_SPEED_NUM_1G;
2808                 break;
2809         case I40E_REG_SPEED_2:
2810                 if (hw->mac.type == I40E_MAC_X722)
2811                         link->link_speed = ETH_SPEED_NUM_2_5G;
2812                 else
2813                         link->link_speed = ETH_SPEED_NUM_10G;
2814                 break;
2815         case I40E_REG_SPEED_3:
2816                 if (hw->mac.type == I40E_MAC_X722) {
2817                         link->link_speed = ETH_SPEED_NUM_5G;
2818                 } else {
2819                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2820
2821                         if (reg_val & I40E_REG_MACC_25GB)
2822                                 link->link_speed = ETH_SPEED_NUM_25G;
2823                         else
2824                                 link->link_speed = ETH_SPEED_NUM_40G;
2825                 }
2826                 break;
2827         case I40E_REG_SPEED_4:
2828                 if (hw->mac.type == I40E_MAC_X722)
2829                         link->link_speed = ETH_SPEED_NUM_10G;
2830                 else
2831                         link->link_speed = ETH_SPEED_NUM_20G;
2832                 break;
2833         default:
2834                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2835                 break;
2836         }
2837 }
2838
2839 static __rte_always_inline void
2840 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2841         bool enable_lse, int wait_to_complete)
2842 {
2843 #define CHECK_INTERVAL             100  /* 100ms */
2844 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2845         uint32_t rep_cnt = MAX_REPEAT_TIME;
2846         struct i40e_link_status link_status;
2847         int status;
2848
2849         memset(&link_status, 0, sizeof(link_status));
2850
2851         do {
2852                 memset(&link_status, 0, sizeof(link_status));
2853
2854                 /* Get link status information from hardware */
2855                 status = i40e_aq_get_link_info(hw, enable_lse,
2856                                                 &link_status, NULL);
2857                 if (unlikely(status != I40E_SUCCESS)) {
2858                         link->link_speed = ETH_SPEED_NUM_NONE;
2859                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2860                         PMD_DRV_LOG(ERR, "Failed to get link info");
2861                         return;
2862                 }
2863
2864                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2865                 if (!wait_to_complete || link->link_status)
2866                         break;
2867
2868                 rte_delay_ms(CHECK_INTERVAL);
2869         } while (--rep_cnt);
2870
2871         /* Parse the link status */
2872         switch (link_status.link_speed) {
2873         case I40E_LINK_SPEED_100MB:
2874                 link->link_speed = ETH_SPEED_NUM_100M;
2875                 break;
2876         case I40E_LINK_SPEED_1GB:
2877                 link->link_speed = ETH_SPEED_NUM_1G;
2878                 break;
2879         case I40E_LINK_SPEED_10GB:
2880                 link->link_speed = ETH_SPEED_NUM_10G;
2881                 break;
2882         case I40E_LINK_SPEED_20GB:
2883                 link->link_speed = ETH_SPEED_NUM_20G;
2884                 break;
2885         case I40E_LINK_SPEED_25GB:
2886                 link->link_speed = ETH_SPEED_NUM_25G;
2887                 break;
2888         case I40E_LINK_SPEED_40GB:
2889                 link->link_speed = ETH_SPEED_NUM_40G;
2890                 break;
2891         default:
2892                 link->link_speed = ETH_SPEED_NUM_NONE;
2893                 break;
2894         }
2895 }
2896
2897 int
2898 i40e_dev_link_update(struct rte_eth_dev *dev,
2899                      int wait_to_complete)
2900 {
2901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902         struct rte_eth_link link;
2903         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2904         int ret;
2905
2906         memset(&link, 0, sizeof(link));
2907
2908         /* i40e uses full duplex only */
2909         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2910         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2911                         ETH_LINK_SPEED_FIXED);
2912
2913         if (!wait_to_complete && !enable_lse)
2914                 update_link_reg(hw, &link);
2915         else
2916                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2917
2918         if (hw->switch_dev)
2919                 rte_eth_linkstatus_get(hw->switch_dev, &link);
2920
2921         ret = rte_eth_linkstatus_set(dev, &link);
2922         i40e_notify_all_vfs_link_status(dev);
2923
2924         return ret;
2925 }
2926
2927 /* Get all the statistics of a VSI */
2928 void
2929 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2930 {
2931         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2932         struct i40e_eth_stats *nes = &vsi->eth_stats;
2933         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2934         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2935
2936         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2937                             vsi->offset_loaded, &oes->rx_bytes,
2938                             &nes->rx_bytes);
2939         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2940                             vsi->offset_loaded, &oes->rx_unicast,
2941                             &nes->rx_unicast);
2942         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2943                             vsi->offset_loaded, &oes->rx_multicast,
2944                             &nes->rx_multicast);
2945         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2946                             vsi->offset_loaded, &oes->rx_broadcast,
2947                             &nes->rx_broadcast);
2948         /* exclude CRC bytes */
2949         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2950                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2951
2952         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2953                             &oes->rx_discards, &nes->rx_discards);
2954         /* GLV_REPC not supported */
2955         /* GLV_RMPC not supported */
2956         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2957                             &oes->rx_unknown_protocol,
2958                             &nes->rx_unknown_protocol);
2959         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2960                             vsi->offset_loaded, &oes->tx_bytes,
2961                             &nes->tx_bytes);
2962         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2963                             vsi->offset_loaded, &oes->tx_unicast,
2964                             &nes->tx_unicast);
2965         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2966                             vsi->offset_loaded, &oes->tx_multicast,
2967                             &nes->tx_multicast);
2968         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2969                             vsi->offset_loaded,  &oes->tx_broadcast,
2970                             &nes->tx_broadcast);
2971         /* GLV_TDPC not supported */
2972         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2973                             &oes->tx_errors, &nes->tx_errors);
2974         vsi->offset_loaded = true;
2975
2976         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2977                     vsi->vsi_id);
2978         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2979         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2980         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2981         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2982         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2983         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2984                     nes->rx_unknown_protocol);
2985         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2986         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2987         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2988         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2989         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2990         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2991         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2992                     vsi->vsi_id);
2993 }
2994
2995 static void
2996 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2997 {
2998         unsigned int i;
2999         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3000         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3001
3002         /* Get rx/tx bytes of internal transfer packets */
3003         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3004                         I40E_GLV_GORCL(hw->port),
3005                         pf->offset_loaded,
3006                         &pf->internal_stats_offset.rx_bytes,
3007                         &pf->internal_stats.rx_bytes);
3008
3009         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3010                         I40E_GLV_GOTCL(hw->port),
3011                         pf->offset_loaded,
3012                         &pf->internal_stats_offset.tx_bytes,
3013                         &pf->internal_stats.tx_bytes);
3014         /* Get total internal rx packet count */
3015         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3016                             I40E_GLV_UPRCL(hw->port),
3017                             pf->offset_loaded,
3018                             &pf->internal_stats_offset.rx_unicast,
3019                             &pf->internal_stats.rx_unicast);
3020         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3021                             I40E_GLV_MPRCL(hw->port),
3022                             pf->offset_loaded,
3023                             &pf->internal_stats_offset.rx_multicast,
3024                             &pf->internal_stats.rx_multicast);
3025         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3026                             I40E_GLV_BPRCL(hw->port),
3027                             pf->offset_loaded,
3028                             &pf->internal_stats_offset.rx_broadcast,
3029                             &pf->internal_stats.rx_broadcast);
3030         /* Get total internal tx packet count */
3031         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3032                             I40E_GLV_UPTCL(hw->port),
3033                             pf->offset_loaded,
3034                             &pf->internal_stats_offset.tx_unicast,
3035                             &pf->internal_stats.tx_unicast);
3036         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3037                             I40E_GLV_MPTCL(hw->port),
3038                             pf->offset_loaded,
3039                             &pf->internal_stats_offset.tx_multicast,
3040                             &pf->internal_stats.tx_multicast);
3041         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3042                             I40E_GLV_BPTCL(hw->port),
3043                             pf->offset_loaded,
3044                             &pf->internal_stats_offset.tx_broadcast,
3045                             &pf->internal_stats.tx_broadcast);
3046
3047         /* exclude CRC size */
3048         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3049                 pf->internal_stats.rx_multicast +
3050                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3051
3052         /* Get statistics of struct i40e_eth_stats */
3053         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3054                             I40E_GLPRT_GORCL(hw->port),
3055                             pf->offset_loaded, &os->eth.rx_bytes,
3056                             &ns->eth.rx_bytes);
3057         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3058                             I40E_GLPRT_UPRCL(hw->port),
3059                             pf->offset_loaded, &os->eth.rx_unicast,
3060                             &ns->eth.rx_unicast);
3061         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3062                             I40E_GLPRT_MPRCL(hw->port),
3063                             pf->offset_loaded, &os->eth.rx_multicast,
3064                             &ns->eth.rx_multicast);
3065         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3066                             I40E_GLPRT_BPRCL(hw->port),
3067                             pf->offset_loaded, &os->eth.rx_broadcast,
3068                             &ns->eth.rx_broadcast);
3069         /* Workaround: CRC size should not be included in byte statistics,
3070          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3071          * packet.
3072          */
3073         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3074                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3075
3076         /* exclude internal rx bytes
3077          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3078          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3079          * value.
3080          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3081          */
3082         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3083                 ns->eth.rx_bytes = 0;
3084         else
3085                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3086
3087         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3088                 ns->eth.rx_unicast = 0;
3089         else
3090                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3091
3092         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3093                 ns->eth.rx_multicast = 0;
3094         else
3095                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3096
3097         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3098                 ns->eth.rx_broadcast = 0;
3099         else
3100                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3101
3102         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3103                             pf->offset_loaded, &os->eth.rx_discards,
3104                             &ns->eth.rx_discards);
3105         /* GLPRT_REPC not supported */
3106         /* GLPRT_RMPC not supported */
3107         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3108                             pf->offset_loaded,
3109                             &os->eth.rx_unknown_protocol,
3110                             &ns->eth.rx_unknown_protocol);
3111         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3112                             I40E_GLPRT_GOTCL(hw->port),
3113                             pf->offset_loaded, &os->eth.tx_bytes,
3114                             &ns->eth.tx_bytes);
3115         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3116                             I40E_GLPRT_UPTCL(hw->port),
3117                             pf->offset_loaded, &os->eth.tx_unicast,
3118                             &ns->eth.tx_unicast);
3119         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3120                             I40E_GLPRT_MPTCL(hw->port),
3121                             pf->offset_loaded, &os->eth.tx_multicast,
3122                             &ns->eth.tx_multicast);
3123         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3124                             I40E_GLPRT_BPTCL(hw->port),
3125                             pf->offset_loaded, &os->eth.tx_broadcast,
3126                             &ns->eth.tx_broadcast);
3127         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3128                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3129
3130         /* exclude internal tx bytes
3131          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3132          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3133          * value.
3134          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3135          */
3136         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3137                 ns->eth.tx_bytes = 0;
3138         else
3139                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3140
3141         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3142                 ns->eth.tx_unicast = 0;
3143         else
3144                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3145
3146         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3147                 ns->eth.tx_multicast = 0;
3148         else
3149                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3150
3151         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3152                 ns->eth.tx_broadcast = 0;
3153         else
3154                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3155
3156         /* GLPRT_TEPC not supported */
3157
3158         /* additional port specific stats */
3159         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3160                             pf->offset_loaded, &os->tx_dropped_link_down,
3161                             &ns->tx_dropped_link_down);
3162         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3163                             pf->offset_loaded, &os->crc_errors,
3164                             &ns->crc_errors);
3165         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3166                             pf->offset_loaded, &os->illegal_bytes,
3167                             &ns->illegal_bytes);
3168         /* GLPRT_ERRBC not supported */
3169         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3170                             pf->offset_loaded, &os->mac_local_faults,
3171                             &ns->mac_local_faults);
3172         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3173                             pf->offset_loaded, &os->mac_remote_faults,
3174                             &ns->mac_remote_faults);
3175         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3176                             pf->offset_loaded, &os->rx_length_errors,
3177                             &ns->rx_length_errors);
3178         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3179                             pf->offset_loaded, &os->link_xon_rx,
3180                             &ns->link_xon_rx);
3181         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3182                             pf->offset_loaded, &os->link_xoff_rx,
3183                             &ns->link_xoff_rx);
3184         for (i = 0; i < 8; i++) {
3185                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3186                                     pf->offset_loaded,
3187                                     &os->priority_xon_rx[i],
3188                                     &ns->priority_xon_rx[i]);
3189                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3190                                     pf->offset_loaded,
3191                                     &os->priority_xoff_rx[i],
3192                                     &ns->priority_xoff_rx[i]);
3193         }
3194         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3195                             pf->offset_loaded, &os->link_xon_tx,
3196                             &ns->link_xon_tx);
3197         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3198                             pf->offset_loaded, &os->link_xoff_tx,
3199                             &ns->link_xoff_tx);
3200         for (i = 0; i < 8; i++) {
3201                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3202                                     pf->offset_loaded,
3203                                     &os->priority_xon_tx[i],
3204                                     &ns->priority_xon_tx[i]);
3205                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3206                                     pf->offset_loaded,
3207                                     &os->priority_xoff_tx[i],
3208                                     &ns->priority_xoff_tx[i]);
3209                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3210                                     pf->offset_loaded,
3211                                     &os->priority_xon_2_xoff[i],
3212                                     &ns->priority_xon_2_xoff[i]);
3213         }
3214         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3215                             I40E_GLPRT_PRC64L(hw->port),
3216                             pf->offset_loaded, &os->rx_size_64,
3217                             &ns->rx_size_64);
3218         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3219                             I40E_GLPRT_PRC127L(hw->port),
3220                             pf->offset_loaded, &os->rx_size_127,
3221                             &ns->rx_size_127);
3222         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3223                             I40E_GLPRT_PRC255L(hw->port),
3224                             pf->offset_loaded, &os->rx_size_255,
3225                             &ns->rx_size_255);
3226         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3227                             I40E_GLPRT_PRC511L(hw->port),
3228                             pf->offset_loaded, &os->rx_size_511,
3229                             &ns->rx_size_511);
3230         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3231                             I40E_GLPRT_PRC1023L(hw->port),
3232                             pf->offset_loaded, &os->rx_size_1023,
3233                             &ns->rx_size_1023);
3234         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3235                             I40E_GLPRT_PRC1522L(hw->port),
3236                             pf->offset_loaded, &os->rx_size_1522,
3237                             &ns->rx_size_1522);
3238         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3239                             I40E_GLPRT_PRC9522L(hw->port),
3240                             pf->offset_loaded, &os->rx_size_big,
3241                             &ns->rx_size_big);
3242         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3243                             pf->offset_loaded, &os->rx_undersize,
3244                             &ns->rx_undersize);
3245         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3246                             pf->offset_loaded, &os->rx_fragments,
3247                             &ns->rx_fragments);
3248         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3249                             pf->offset_loaded, &os->rx_oversize,
3250                             &ns->rx_oversize);
3251         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3252                             pf->offset_loaded, &os->rx_jabber,
3253                             &ns->rx_jabber);
3254         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3255                             I40E_GLPRT_PTC64L(hw->port),
3256                             pf->offset_loaded, &os->tx_size_64,
3257                             &ns->tx_size_64);
3258         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3259                             I40E_GLPRT_PTC127L(hw->port),
3260                             pf->offset_loaded, &os->tx_size_127,
3261                             &ns->tx_size_127);
3262         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3263                             I40E_GLPRT_PTC255L(hw->port),
3264                             pf->offset_loaded, &os->tx_size_255,
3265                             &ns->tx_size_255);
3266         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3267                             I40E_GLPRT_PTC511L(hw->port),
3268                             pf->offset_loaded, &os->tx_size_511,
3269                             &ns->tx_size_511);
3270         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3271                             I40E_GLPRT_PTC1023L(hw->port),
3272                             pf->offset_loaded, &os->tx_size_1023,
3273                             &ns->tx_size_1023);
3274         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3275                             I40E_GLPRT_PTC1522L(hw->port),
3276                             pf->offset_loaded, &os->tx_size_1522,
3277                             &ns->tx_size_1522);
3278         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3279                             I40E_GLPRT_PTC9522L(hw->port),
3280                             pf->offset_loaded, &os->tx_size_big,
3281                             &ns->tx_size_big);
3282         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3283                            pf->offset_loaded,
3284                            &os->fd_sb_match, &ns->fd_sb_match);
3285         /* GLPRT_MSPDC not supported */
3286         /* GLPRT_XEC not supported */
3287
3288         pf->offset_loaded = true;
3289
3290         if (pf->main_vsi)
3291                 i40e_update_vsi_stats(pf->main_vsi);
3292 }
3293
3294 /* Get all statistics of a port */
3295 static int
3296 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3297 {
3298         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3299         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3301         struct i40e_vsi *vsi;
3302         unsigned i;
3303
3304         /* call read registers - updates values, now write them to struct */
3305         i40e_read_stats_registers(pf, hw);
3306
3307         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3308                         pf->main_vsi->eth_stats.rx_multicast +
3309                         pf->main_vsi->eth_stats.rx_broadcast -
3310                         pf->main_vsi->eth_stats.rx_discards;
3311         stats->opackets = ns->eth.tx_unicast +
3312                         ns->eth.tx_multicast +
3313                         ns->eth.tx_broadcast;
3314         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3315         stats->obytes   = ns->eth.tx_bytes;
3316         stats->oerrors  = ns->eth.tx_errors +
3317                         pf->main_vsi->eth_stats.tx_errors;
3318
3319         /* Rx Errors */
3320         stats->imissed  = ns->eth.rx_discards +
3321                         pf->main_vsi->eth_stats.rx_discards;
3322         stats->ierrors  = ns->crc_errors +
3323                         ns->rx_length_errors + ns->rx_undersize +
3324                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3325
3326         if (pf->vfs) {
3327                 for (i = 0; i < pf->vf_num; i++) {
3328                         vsi = pf->vfs[i].vsi;
3329                         i40e_update_vsi_stats(vsi);
3330
3331                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3332                                         vsi->eth_stats.rx_multicast +
3333                                         vsi->eth_stats.rx_broadcast -
3334                                         vsi->eth_stats.rx_discards);
3335                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3336                         stats->oerrors  += vsi->eth_stats.tx_errors;
3337                         stats->imissed  += vsi->eth_stats.rx_discards;
3338                 }
3339         }
3340
3341         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3342         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3343         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3344         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3345         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3346         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3347         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3348                     ns->eth.rx_unknown_protocol);
3349         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3350         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3351         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3352         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3353         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3354         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3355
3356         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3357                     ns->tx_dropped_link_down);
3358         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3359         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3360                     ns->illegal_bytes);
3361         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3362         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3363                     ns->mac_local_faults);
3364         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3365                     ns->mac_remote_faults);
3366         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3367                     ns->rx_length_errors);
3368         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3369         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3370         for (i = 0; i < 8; i++) {
3371                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3372                                 i, ns->priority_xon_rx[i]);
3373                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3374                                 i, ns->priority_xoff_rx[i]);
3375         }
3376         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3377         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3378         for (i = 0; i < 8; i++) {
3379                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3380                                 i, ns->priority_xon_tx[i]);
3381                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3382                                 i, ns->priority_xoff_tx[i]);
3383                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3384                                 i, ns->priority_xon_2_xoff[i]);
3385         }
3386         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3387         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3388         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3389         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3390         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3391         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3392         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3393         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3394         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3395         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3396         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3397         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3398         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3399         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3400         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3401         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3402         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3403         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3404         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3405                         ns->mac_short_packet_dropped);
3406         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3407                     ns->checksum_error);
3408         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3409         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3410         return 0;
3411 }
3412
3413 /* Reset the statistics */
3414 static int
3415 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3416 {
3417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3419
3420         /* Mark PF and VSI stats to update the offset, aka "reset" */
3421         pf->offset_loaded = false;
3422         if (pf->main_vsi)
3423                 pf->main_vsi->offset_loaded = false;
3424
3425         /* read the stats, reading current register values into offset */
3426         i40e_read_stats_registers(pf, hw);
3427
3428         return 0;
3429 }
3430
3431 static uint32_t
3432 i40e_xstats_calc_num(void)
3433 {
3434         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3435                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3436                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3437 }
3438
3439 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3440                                      struct rte_eth_xstat_name *xstats_names,
3441                                      __rte_unused unsigned limit)
3442 {
3443         unsigned count = 0;
3444         unsigned i, prio;
3445
3446         if (xstats_names == NULL)
3447                 return i40e_xstats_calc_num();
3448
3449         /* Note: limit checked in rte_eth_xstats_names() */
3450
3451         /* Get stats from i40e_eth_stats struct */
3452         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3453                 strlcpy(xstats_names[count].name,
3454                         rte_i40e_stats_strings[i].name,
3455                         sizeof(xstats_names[count].name));
3456                 count++;
3457         }
3458
3459         /* Get individiual stats from i40e_hw_port struct */
3460         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3461                 strlcpy(xstats_names[count].name,
3462                         rte_i40e_hw_port_strings[i].name,
3463                         sizeof(xstats_names[count].name));
3464                 count++;
3465         }
3466
3467         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3468                 for (prio = 0; prio < 8; prio++) {
3469                         snprintf(xstats_names[count].name,
3470                                  sizeof(xstats_names[count].name),
3471                                  "rx_priority%u_%s", prio,
3472                                  rte_i40e_rxq_prio_strings[i].name);
3473                         count++;
3474                 }
3475         }
3476
3477         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3478                 for (prio = 0; prio < 8; prio++) {
3479                         snprintf(xstats_names[count].name,
3480                                  sizeof(xstats_names[count].name),
3481                                  "tx_priority%u_%s", prio,
3482                                  rte_i40e_txq_prio_strings[i].name);
3483                         count++;
3484                 }
3485         }
3486         return count;
3487 }
3488
3489 static int
3490 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3491                     unsigned n)
3492 {
3493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3495         unsigned i, count, prio;
3496         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3497
3498         count = i40e_xstats_calc_num();
3499         if (n < count)
3500                 return count;
3501
3502         i40e_read_stats_registers(pf, hw);
3503
3504         if (xstats == NULL)
3505                 return 0;
3506
3507         count = 0;
3508
3509         /* Get stats from i40e_eth_stats struct */
3510         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3511                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3512                         rte_i40e_stats_strings[i].offset);
3513                 xstats[count].id = count;
3514                 count++;
3515         }
3516
3517         /* Get individiual stats from i40e_hw_port struct */
3518         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3519                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3520                         rte_i40e_hw_port_strings[i].offset);
3521                 xstats[count].id = count;
3522                 count++;
3523         }
3524
3525         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3526                 for (prio = 0; prio < 8; prio++) {
3527                         xstats[count].value =
3528                                 *(uint64_t *)(((char *)hw_stats) +
3529                                 rte_i40e_rxq_prio_strings[i].offset +
3530                                 (sizeof(uint64_t) * prio));
3531                         xstats[count].id = count;
3532                         count++;
3533                 }
3534         }
3535
3536         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3537                 for (prio = 0; prio < 8; prio++) {
3538                         xstats[count].value =
3539                                 *(uint64_t *)(((char *)hw_stats) +
3540                                 rte_i40e_txq_prio_strings[i].offset +
3541                                 (sizeof(uint64_t) * prio));
3542                         xstats[count].id = count;
3543                         count++;
3544                 }
3545         }
3546
3547         return count;
3548 }
3549
3550 static int
3551 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3552 {
3553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554         u32 full_ver;
3555         u8 ver, patch;
3556         u16 build;
3557         int ret;
3558
3559         full_ver = hw->nvm.oem_ver;
3560         ver = (u8)(full_ver >> 24);
3561         build = (u16)((full_ver >> 8) & 0xffff);
3562         patch = (u8)(full_ver & 0xff);
3563
3564         ret = snprintf(fw_version, fw_size,
3565                  "%d.%d%d 0x%08x %d.%d.%d",
3566                  ((hw->nvm.version >> 12) & 0xf),
3567                  ((hw->nvm.version >> 4) & 0xff),
3568                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3569                  ver, build, patch);
3570
3571         ret += 1; /* add the size of '\0' */
3572         if (fw_size < (u32)ret)
3573                 return ret;
3574         else
3575                 return 0;
3576 }
3577
3578 /*
3579  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3580  * the Rx data path does not hang if the FW LLDP is stopped.
3581  * return true if lldp need to stop
3582  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3583  */
3584 static bool
3585 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3586 {
3587         double nvm_ver;
3588         char ver_str[64] = {0};
3589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3590
3591         i40e_fw_version_get(dev, ver_str, 64);
3592         nvm_ver = atof(ver_str);
3593         if ((hw->mac.type == I40E_MAC_X722 ||
3594              hw->mac.type == I40E_MAC_X722_VF) &&
3595              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3596                 return true;
3597         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3598                 return true;
3599
3600         return false;
3601 }
3602
3603 static int
3604 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3605 {
3606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3608         struct i40e_vsi *vsi = pf->main_vsi;
3609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3610
3611         dev_info->max_rx_queues = vsi->nb_qps;
3612         dev_info->max_tx_queues = vsi->nb_qps;
3613         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3614         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3615         dev_info->max_mac_addrs = vsi->max_macaddrs;
3616         dev_info->max_vfs = pci_dev->max_vfs;
3617         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3618         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3619         dev_info->rx_queue_offload_capa = 0;
3620         dev_info->rx_offload_capa =
3621                 DEV_RX_OFFLOAD_VLAN_STRIP |
3622                 DEV_RX_OFFLOAD_QINQ_STRIP |
3623                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3624                 DEV_RX_OFFLOAD_UDP_CKSUM |
3625                 DEV_RX_OFFLOAD_TCP_CKSUM |
3626                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3627                 DEV_RX_OFFLOAD_KEEP_CRC |
3628                 DEV_RX_OFFLOAD_SCATTER |
3629                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3630                 DEV_RX_OFFLOAD_VLAN_FILTER |
3631                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3632                 DEV_RX_OFFLOAD_RSS_HASH;
3633
3634         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3635         dev_info->tx_offload_capa =
3636                 DEV_TX_OFFLOAD_VLAN_INSERT |
3637                 DEV_TX_OFFLOAD_QINQ_INSERT |
3638                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3639                 DEV_TX_OFFLOAD_UDP_CKSUM |
3640                 DEV_TX_OFFLOAD_TCP_CKSUM |
3641                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3642                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3643                 DEV_TX_OFFLOAD_TCP_TSO |
3644                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3645                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3646                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3647                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3648                 DEV_TX_OFFLOAD_MULTI_SEGS |
3649                 dev_info->tx_queue_offload_capa;
3650         dev_info->dev_capa =
3651                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3652                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3653
3654         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3655                                                 sizeof(uint32_t);
3656         dev_info->reta_size = pf->hash_lut_size;
3657         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3658
3659         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3660                 .rx_thresh = {
3661                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3662                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3663                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3664                 },
3665                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3666                 .rx_drop_en = 0,
3667                 .offloads = 0,
3668         };
3669
3670         dev_info->default_txconf = (struct rte_eth_txconf) {
3671                 .tx_thresh = {
3672                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3673                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3674                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3675                 },
3676                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3677                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3678                 .offloads = 0,
3679         };
3680
3681         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3682                 .nb_max = I40E_MAX_RING_DESC,
3683                 .nb_min = I40E_MIN_RING_DESC,
3684                 .nb_align = I40E_ALIGN_RING_DESC,
3685         };
3686
3687         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3688                 .nb_max = I40E_MAX_RING_DESC,
3689                 .nb_min = I40E_MIN_RING_DESC,
3690                 .nb_align = I40E_ALIGN_RING_DESC,
3691                 .nb_seg_max = I40E_TX_MAX_SEG,
3692                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3693         };
3694
3695         if (pf->flags & I40E_FLAG_VMDQ) {
3696                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3697                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3698                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3699                                                 pf->max_nb_vmdq_vsi;
3700                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3701                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3702                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3703         }
3704
3705         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3706                 /* For XL710 */
3707                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3708                 dev_info->default_rxportconf.nb_queues = 2;
3709                 dev_info->default_txportconf.nb_queues = 2;
3710                 if (dev->data->nb_rx_queues == 1)
3711                         dev_info->default_rxportconf.ring_size = 2048;
3712                 else
3713                         dev_info->default_rxportconf.ring_size = 1024;
3714                 if (dev->data->nb_tx_queues == 1)
3715                         dev_info->default_txportconf.ring_size = 1024;
3716                 else
3717                         dev_info->default_txportconf.ring_size = 512;
3718
3719         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3720                 /* For XXV710 */
3721                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3722                 dev_info->default_rxportconf.nb_queues = 1;
3723                 dev_info->default_txportconf.nb_queues = 1;
3724                 dev_info->default_rxportconf.ring_size = 256;
3725                 dev_info->default_txportconf.ring_size = 256;
3726         } else {
3727                 /* For X710 */
3728                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3729                 dev_info->default_rxportconf.nb_queues = 1;
3730                 dev_info->default_txportconf.nb_queues = 1;
3731                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3732                         dev_info->default_rxportconf.ring_size = 512;
3733                         dev_info->default_txportconf.ring_size = 256;
3734                 } else {
3735                         dev_info->default_rxportconf.ring_size = 256;
3736                         dev_info->default_txportconf.ring_size = 256;
3737                 }
3738         }
3739         dev_info->default_rxportconf.burst_size = 32;
3740         dev_info->default_txportconf.burst_size = 32;
3741
3742         return 0;
3743 }
3744
3745 static int
3746 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3747 {
3748         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3749         struct i40e_vsi *vsi = pf->main_vsi;
3750         PMD_INIT_FUNC_TRACE();
3751
3752         if (on)
3753                 return i40e_vsi_add_vlan(vsi, vlan_id);
3754         else
3755                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3756 }
3757
3758 static int
3759 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3760                                 enum rte_vlan_type vlan_type,
3761                                 uint16_t tpid, int qinq)
3762 {
3763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764         uint64_t reg_r = 0;
3765         uint64_t reg_w = 0;
3766         uint16_t reg_id = 3;
3767         int ret;
3768
3769         if (qinq) {
3770                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3771                         reg_id = 2;
3772         }
3773
3774         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3775                                           &reg_r, NULL);
3776         if (ret != I40E_SUCCESS) {
3777                 PMD_DRV_LOG(ERR,
3778                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3779                            reg_id);
3780                 return -EIO;
3781         }
3782         PMD_DRV_LOG(DEBUG,
3783                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3784                     reg_id, reg_r);
3785
3786         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3787         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3788         if (reg_r == reg_w) {
3789                 PMD_DRV_LOG(DEBUG, "No need to write");
3790                 return 0;
3791         }
3792
3793         ret = i40e_aq_debug_write_global_register(hw,
3794                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3795                                            reg_w, NULL);
3796         if (ret != I40E_SUCCESS) {
3797                 PMD_DRV_LOG(ERR,
3798                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3799                             reg_id);
3800                 return -EIO;
3801         }
3802         PMD_DRV_LOG(DEBUG,
3803                     "Global register 0x%08x is changed with value 0x%08x",
3804                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3805
3806         return 0;
3807 }
3808
3809 static int
3810 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3811                    enum rte_vlan_type vlan_type,
3812                    uint16_t tpid)
3813 {
3814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3816         int qinq = dev->data->dev_conf.rxmode.offloads &
3817                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3818         int ret = 0;
3819
3820         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3821              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3822             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3823                 PMD_DRV_LOG(ERR,
3824                             "Unsupported vlan type.");
3825                 return -EINVAL;
3826         }
3827
3828         if (pf->support_multi_driver) {
3829                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3830                 return -ENOTSUP;
3831         }
3832
3833         /* 802.1ad frames ability is added in NVM API 1.7*/
3834         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3835                 if (qinq) {
3836                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3837                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3838                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3839                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3840                 } else {
3841                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3842                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3843                 }
3844                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3845                 if (ret != I40E_SUCCESS) {
3846                         PMD_DRV_LOG(ERR,
3847                                     "Set switch config failed aq_err: %d",
3848                                     hw->aq.asq_last_status);
3849                         ret = -EIO;
3850                 }
3851         } else
3852                 /* If NVM API < 1.7, keep the register setting */
3853                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3854                                                       tpid, qinq);
3855
3856         return ret;
3857 }
3858
3859 static int
3860 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3861 {
3862         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3863         struct i40e_vsi *vsi = pf->main_vsi;
3864         struct rte_eth_rxmode *rxmode;
3865
3866         if (mask & ETH_QINQ_STRIP_MASK) {
3867                 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3868                 return -ENOTSUP;
3869         }
3870
3871         rxmode = &dev->data->dev_conf.rxmode;
3872         if (mask & ETH_VLAN_FILTER_MASK) {
3873                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3874                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3875                 else
3876                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3877         }
3878
3879         if (mask & ETH_VLAN_STRIP_MASK) {
3880                 /* Enable or disable VLAN stripping */
3881                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3882                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3883                 else
3884                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3885         }
3886
3887         if (mask & ETH_VLAN_EXTEND_MASK) {
3888                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3889                         i40e_vsi_config_double_vlan(vsi, TRUE);
3890                         /* Set global registers with default ethertype. */
3891                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3892                                            RTE_ETHER_TYPE_VLAN);
3893                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3894                                            RTE_ETHER_TYPE_VLAN);
3895                 }
3896                 else
3897                         i40e_vsi_config_double_vlan(vsi, FALSE);
3898         }
3899
3900         return 0;
3901 }
3902
3903 static void
3904 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3905                           __rte_unused uint16_t queue,
3906                           __rte_unused int on)
3907 {
3908         PMD_INIT_FUNC_TRACE();
3909 }
3910
3911 static int
3912 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3913 {
3914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3915         struct i40e_vsi *vsi = pf->main_vsi;
3916         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3917         struct i40e_vsi_vlan_pvid_info info;
3918
3919         memset(&info, 0, sizeof(info));
3920         info.on = on;
3921         if (info.on)
3922                 info.config.pvid = pvid;
3923         else {
3924                 info.config.reject.tagged =
3925                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3926                 info.config.reject.untagged =
3927                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3928         }
3929
3930         return i40e_vsi_vlan_pvid_set(vsi, &info);
3931 }
3932
3933 static int
3934 i40e_dev_led_on(struct rte_eth_dev *dev)
3935 {
3936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         uint32_t mode = i40e_led_get(hw);
3938
3939         if (mode == 0)
3940                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3941
3942         return 0;
3943 }
3944
3945 static int
3946 i40e_dev_led_off(struct rte_eth_dev *dev)
3947 {
3948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3949         uint32_t mode = i40e_led_get(hw);
3950
3951         if (mode != 0)
3952                 i40e_led_set(hw, 0, false);
3953
3954         return 0;
3955 }
3956
3957 static int
3958 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3959 {
3960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3962
3963         fc_conf->pause_time = pf->fc_conf.pause_time;
3964
3965         /* read out from register, in case they are modified by other port */
3966         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3967                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3968         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3969                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3970
3971         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3972         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3973
3974          /* Return current mode according to actual setting*/
3975         switch (hw->fc.current_mode) {
3976         case I40E_FC_FULL:
3977                 fc_conf->mode = RTE_FC_FULL;
3978                 break;
3979         case I40E_FC_TX_PAUSE:
3980                 fc_conf->mode = RTE_FC_TX_PAUSE;
3981                 break;
3982         case I40E_FC_RX_PAUSE:
3983                 fc_conf->mode = RTE_FC_RX_PAUSE;
3984                 break;
3985         case I40E_FC_NONE:
3986         default:
3987                 fc_conf->mode = RTE_FC_NONE;
3988         };
3989
3990         return 0;
3991 }
3992
3993 static int
3994 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3995 {
3996         uint32_t mflcn_reg, fctrl_reg, reg;
3997         uint32_t max_high_water;
3998         uint8_t i, aq_failure;
3999         int err;
4000         struct i40e_hw *hw;
4001         struct i40e_pf *pf;
4002         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4003                 [RTE_FC_NONE] = I40E_FC_NONE,
4004                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4005                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4006                 [RTE_FC_FULL] = I40E_FC_FULL
4007         };
4008
4009         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4010
4011         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4012         if ((fc_conf->high_water > max_high_water) ||
4013                         (fc_conf->high_water < fc_conf->low_water)) {
4014                 PMD_INIT_LOG(ERR,
4015                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4016                         max_high_water);
4017                 return -EINVAL;
4018         }
4019
4020         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4021         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4022         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4023
4024         pf->fc_conf.pause_time = fc_conf->pause_time;
4025         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4026         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4027
4028         PMD_INIT_FUNC_TRACE();
4029
4030         /* All the link flow control related enable/disable register
4031          * configuration is handle by the F/W
4032          */
4033         err = i40e_set_fc(hw, &aq_failure, true);
4034         if (err < 0)
4035                 return -ENOSYS;
4036
4037         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4038                 /* Configure flow control refresh threshold,
4039                  * the value for stat_tx_pause_refresh_timer[8]
4040                  * is used for global pause operation.
4041                  */
4042
4043                 I40E_WRITE_REG(hw,
4044                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4045                                pf->fc_conf.pause_time);
4046
4047                 /* configure the timer value included in transmitted pause
4048                  * frame,
4049                  * the value for stat_tx_pause_quanta[8] is used for global
4050                  * pause operation
4051                  */
4052                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4053                                pf->fc_conf.pause_time);
4054
4055                 fctrl_reg = I40E_READ_REG(hw,
4056                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4057
4058                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4059                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4060                 else
4061                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4062
4063                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4064                                fctrl_reg);
4065         } else {
4066                 /* Configure pause time (2 TCs per register) */
4067                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4068                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4069                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4070
4071                 /* Configure flow control refresh threshold value */
4072                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4073                                pf->fc_conf.pause_time / 2);
4074
4075                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4076
4077                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4078                  *depending on configuration
4079                  */
4080                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4081                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4082                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4083                 } else {
4084                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4085                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4086                 }
4087
4088                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4089         }
4090
4091         if (!pf->support_multi_driver) {
4092                 /* config water marker both based on the packets and bytes */
4093                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4094                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4095                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4096                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4097                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4098                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4099                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4100                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4101                                   << I40E_KILOSHIFT);
4102                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4103                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4104                                    << I40E_KILOSHIFT);
4105         } else {
4106                 PMD_DRV_LOG(ERR,
4107                             "Water marker configuration is not supported.");
4108         }
4109
4110         I40E_WRITE_FLUSH(hw);
4111
4112         return 0;
4113 }
4114
4115 static int
4116 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4117                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4118 {
4119         PMD_INIT_FUNC_TRACE();
4120
4121         return -ENOSYS;
4122 }
4123
4124 /* Add a MAC address, and update filters */
4125 static int
4126 i40e_macaddr_add(struct rte_eth_dev *dev,
4127                  struct rte_ether_addr *mac_addr,
4128                  __rte_unused uint32_t index,
4129                  uint32_t pool)
4130 {
4131         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4132         struct i40e_mac_filter_info mac_filter;
4133         struct i40e_vsi *vsi;
4134         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4135         int ret;
4136
4137         /* If VMDQ not enabled or configured, return */
4138         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4139                           !pf->nb_cfg_vmdq_vsi)) {
4140                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4141                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4142                         pool);
4143                 return -ENOTSUP;
4144         }
4145
4146         if (pool > pf->nb_cfg_vmdq_vsi) {
4147                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4148                                 pool, pf->nb_cfg_vmdq_vsi);
4149                 return -EINVAL;
4150         }
4151
4152         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4153         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4154                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4155         else
4156                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4157
4158         if (pool == 0)
4159                 vsi = pf->main_vsi;
4160         else
4161                 vsi = pf->vmdq[pool - 1].vsi;
4162
4163         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4164         if (ret != I40E_SUCCESS) {
4165                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4166                 return -ENODEV;
4167         }
4168         return 0;
4169 }
4170
4171 /* Remove a MAC address, and update filters */
4172 static void
4173 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4174 {
4175         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4176         struct i40e_vsi *vsi;
4177         struct rte_eth_dev_data *data = dev->data;
4178         struct rte_ether_addr *macaddr;
4179         int ret;
4180         uint32_t i;
4181         uint64_t pool_sel;
4182
4183         macaddr = &(data->mac_addrs[index]);
4184
4185         pool_sel = dev->data->mac_pool_sel[index];
4186
4187         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4188                 if (pool_sel & (1ULL << i)) {
4189                         if (i == 0)
4190                                 vsi = pf->main_vsi;
4191                         else {
4192                                 /* No VMDQ pool enabled or configured */
4193                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4194                                         (i > pf->nb_cfg_vmdq_vsi)) {
4195                                         PMD_DRV_LOG(ERR,
4196                                                 "No VMDQ pool enabled/configured");
4197                                         return;
4198                                 }
4199                                 vsi = pf->vmdq[i - 1].vsi;
4200                         }
4201                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4202
4203                         if (ret) {
4204                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4205                                 return;
4206                         }
4207                 }
4208         }
4209 }
4210
4211 /* Set perfect match or hash match of MAC and VLAN for a VF */
4212 static int
4213 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4214                  struct rte_eth_mac_filter *filter,
4215                  bool add)
4216 {
4217         struct i40e_hw *hw;
4218         struct i40e_mac_filter_info mac_filter;
4219         struct rte_ether_addr old_mac;
4220         struct rte_ether_addr *new_mac;
4221         struct i40e_pf_vf *vf = NULL;
4222         uint16_t vf_id;
4223         int ret;
4224
4225         if (pf == NULL) {
4226                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4227                 return -EINVAL;
4228         }
4229         hw = I40E_PF_TO_HW(pf);
4230
4231         if (filter == NULL) {
4232                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4233                 return -EINVAL;
4234         }
4235
4236         new_mac = &filter->mac_addr;
4237
4238         if (rte_is_zero_ether_addr(new_mac)) {
4239                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4240                 return -EINVAL;
4241         }
4242
4243         vf_id = filter->dst_id;
4244
4245         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4246                 PMD_DRV_LOG(ERR, "Invalid argument.");
4247                 return -EINVAL;
4248         }
4249         vf = &pf->vfs[vf_id];
4250
4251         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4252                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4253                 return -EINVAL;
4254         }
4255
4256         if (add) {
4257                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4258                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4259                                 RTE_ETHER_ADDR_LEN);
4260                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4261                                  RTE_ETHER_ADDR_LEN);
4262
4263                 mac_filter.filter_type = filter->filter_type;
4264                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4265                 if (ret != I40E_SUCCESS) {
4266                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4267                         return -1;
4268                 }
4269                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4270         } else {
4271                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4272                                 RTE_ETHER_ADDR_LEN);
4273                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4274                 if (ret != I40E_SUCCESS) {
4275                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4276                         return -1;
4277                 }
4278
4279                 /* Clear device address as it has been removed */
4280                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4281                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4282         }
4283
4284         return 0;
4285 }
4286
4287 /* MAC filter handle */
4288 static int
4289 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4290                 void *arg)
4291 {
4292         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4293         struct rte_eth_mac_filter *filter;
4294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4295         int ret = I40E_NOT_SUPPORTED;
4296
4297         filter = (struct rte_eth_mac_filter *)(arg);
4298
4299         switch (filter_op) {
4300         case RTE_ETH_FILTER_NOP:
4301                 ret = I40E_SUCCESS;
4302                 break;
4303         case RTE_ETH_FILTER_ADD:
4304                 i40e_pf_disable_irq0(hw);
4305                 if (filter->is_vf)
4306                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4307                 i40e_pf_enable_irq0(hw);
4308                 break;
4309         case RTE_ETH_FILTER_DELETE:
4310                 i40e_pf_disable_irq0(hw);
4311                 if (filter->is_vf)
4312                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4313                 i40e_pf_enable_irq0(hw);
4314                 break;
4315         default:
4316                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4317                 ret = I40E_ERR_PARAM;
4318                 break;
4319         }
4320
4321         return ret;
4322 }
4323
4324 static int
4325 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4326 {
4327         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4329         uint32_t reg;
4330         int ret;
4331
4332         if (!lut)
4333                 return -EINVAL;
4334
4335         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4336                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4337                                           vsi->type != I40E_VSI_SRIOV,
4338                                           lut, lut_size);
4339                 if (ret) {
4340                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4341                         return ret;
4342                 }
4343         } else {
4344                 uint32_t *lut_dw = (uint32_t *)lut;
4345                 uint16_t i, lut_size_dw = lut_size / 4;
4346
4347                 if (vsi->type == I40E_VSI_SRIOV) {
4348                         for (i = 0; i <= lut_size_dw; i++) {
4349                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4350                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4351                         }
4352                 } else {
4353                         for (i = 0; i < lut_size_dw; i++)
4354                                 lut_dw[i] = I40E_READ_REG(hw,
4355                                                           I40E_PFQF_HLUT(i));
4356                 }
4357         }
4358
4359         return 0;
4360 }
4361
4362 int
4363 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4364 {
4365         struct i40e_pf *pf;
4366         struct i40e_hw *hw;
4367         int ret;
4368
4369         if (!vsi || !lut)
4370                 return -EINVAL;
4371
4372         pf = I40E_VSI_TO_PF(vsi);
4373         hw = I40E_VSI_TO_HW(vsi);
4374
4375         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4376                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4377                                           vsi->type != I40E_VSI_SRIOV,
4378                                           lut, lut_size);
4379                 if (ret) {
4380                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4381                         return ret;
4382                 }
4383         } else {
4384                 uint32_t *lut_dw = (uint32_t *)lut;
4385                 uint16_t i, lut_size_dw = lut_size / 4;
4386
4387                 if (vsi->type == I40E_VSI_SRIOV) {
4388                         for (i = 0; i < lut_size_dw; i++)
4389                                 I40E_WRITE_REG(
4390                                         hw,
4391                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4392                                         lut_dw[i]);
4393                 } else {
4394                         for (i = 0; i < lut_size_dw; i++)
4395                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4396                                                lut_dw[i]);
4397                 }
4398                 I40E_WRITE_FLUSH(hw);
4399         }
4400
4401         return 0;
4402 }
4403
4404 static int
4405 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4406                          struct rte_eth_rss_reta_entry64 *reta_conf,
4407                          uint16_t reta_size)
4408 {
4409         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4410         uint16_t i, lut_size = pf->hash_lut_size;
4411         uint16_t idx, shift;
4412         uint8_t *lut;
4413         int ret;
4414
4415         if (reta_size != lut_size ||
4416                 reta_size > ETH_RSS_RETA_SIZE_512) {
4417                 PMD_DRV_LOG(ERR,
4418                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4419                         reta_size, lut_size);
4420                 return -EINVAL;
4421         }
4422
4423         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4424         if (!lut) {
4425                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4426                 return -ENOMEM;
4427         }
4428         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4429         if (ret)
4430                 goto out;
4431         for (i = 0; i < reta_size; i++) {
4432                 idx = i / RTE_RETA_GROUP_SIZE;
4433                 shift = i % RTE_RETA_GROUP_SIZE;
4434                 if (reta_conf[idx].mask & (1ULL << shift))
4435                         lut[i] = reta_conf[idx].reta[shift];
4436         }
4437         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4438
4439         pf->adapter->rss_reta_updated = 1;
4440
4441 out:
4442         rte_free(lut);
4443
4444         return ret;
4445 }
4446
4447 static int
4448 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4449                         struct rte_eth_rss_reta_entry64 *reta_conf,
4450                         uint16_t reta_size)
4451 {
4452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4453         uint16_t i, lut_size = pf->hash_lut_size;
4454         uint16_t idx, shift;
4455         uint8_t *lut;
4456         int ret;
4457
4458         if (reta_size != lut_size ||
4459                 reta_size > ETH_RSS_RETA_SIZE_512) {
4460                 PMD_DRV_LOG(ERR,
4461                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4462                         reta_size, lut_size);
4463                 return -EINVAL;
4464         }
4465
4466         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4467         if (!lut) {
4468                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4469                 return -ENOMEM;
4470         }
4471
4472         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4473         if (ret)
4474                 goto out;
4475         for (i = 0; i < reta_size; i++) {
4476                 idx = i / RTE_RETA_GROUP_SIZE;
4477                 shift = i % RTE_RETA_GROUP_SIZE;
4478                 if (reta_conf[idx].mask & (1ULL << shift))
4479                         reta_conf[idx].reta[shift] = lut[i];
4480         }
4481
4482 out:
4483         rte_free(lut);
4484
4485         return ret;
4486 }
4487
4488 /**
4489  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4490  * @hw:   pointer to the HW structure
4491  * @mem:  pointer to mem struct to fill out
4492  * @size: size of memory requested
4493  * @alignment: what to align the allocation to
4494  **/
4495 enum i40e_status_code
4496 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4497                         struct i40e_dma_mem *mem,
4498                         u64 size,
4499                         u32 alignment)
4500 {
4501         const struct rte_memzone *mz = NULL;
4502         char z_name[RTE_MEMZONE_NAMESIZE];
4503
4504         if (!mem)
4505                 return I40E_ERR_PARAM;
4506
4507         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4508         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4509                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4510         if (!mz)
4511                 return I40E_ERR_NO_MEMORY;
4512
4513         mem->size = size;
4514         mem->va = mz->addr;
4515         mem->pa = mz->iova;
4516         mem->zone = (const void *)mz;
4517         PMD_DRV_LOG(DEBUG,
4518                 "memzone %s allocated with physical address: %"PRIu64,
4519                 mz->name, mem->pa);
4520
4521         return I40E_SUCCESS;
4522 }
4523
4524 /**
4525  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4526  * @hw:   pointer to the HW structure
4527  * @mem:  ptr to mem struct to free
4528  **/
4529 enum i40e_status_code
4530 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4531                     struct i40e_dma_mem *mem)
4532 {
4533         if (!mem)
4534                 return I40E_ERR_PARAM;
4535
4536         PMD_DRV_LOG(DEBUG,
4537                 "memzone %s to be freed with physical address: %"PRIu64,
4538                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4539         rte_memzone_free((const struct rte_memzone *)mem->zone);
4540         mem->zone = NULL;
4541         mem->va = NULL;
4542         mem->pa = (u64)0;
4543
4544         return I40E_SUCCESS;
4545 }
4546
4547 /**
4548  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4549  * @hw:   pointer to the HW structure
4550  * @mem:  pointer to mem struct to fill out
4551  * @size: size of memory requested
4552  **/
4553 enum i40e_status_code
4554 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4555                          struct i40e_virt_mem *mem,
4556                          u32 size)
4557 {
4558         if (!mem)
4559                 return I40E_ERR_PARAM;
4560
4561         mem->size = size;
4562         mem->va = rte_zmalloc("i40e", size, 0);
4563
4564         if (mem->va)
4565                 return I40E_SUCCESS;
4566         else
4567                 return I40E_ERR_NO_MEMORY;
4568 }
4569
4570 /**
4571  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4572  * @hw:   pointer to the HW structure
4573  * @mem:  pointer to mem struct to free
4574  **/
4575 enum i40e_status_code
4576 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4577                      struct i40e_virt_mem *mem)
4578 {
4579         if (!mem)
4580                 return I40E_ERR_PARAM;
4581
4582         rte_free(mem->va);
4583         mem->va = NULL;
4584
4585         return I40E_SUCCESS;
4586 }
4587
4588 void
4589 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4590 {
4591         rte_spinlock_init(&sp->spinlock);
4592 }
4593
4594 void
4595 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4596 {
4597         rte_spinlock_lock(&sp->spinlock);
4598 }
4599
4600 void
4601 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4602 {
4603         rte_spinlock_unlock(&sp->spinlock);
4604 }
4605
4606 void
4607 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4608 {
4609         return;
4610 }
4611
4612 /**
4613  * Get the hardware capabilities, which will be parsed
4614  * and saved into struct i40e_hw.
4615  */
4616 static int
4617 i40e_get_cap(struct i40e_hw *hw)
4618 {
4619         struct i40e_aqc_list_capabilities_element_resp *buf;
4620         uint16_t len, size = 0;
4621         int ret;
4622
4623         /* Calculate a huge enough buff for saving response data temporarily */
4624         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4625                                                 I40E_MAX_CAP_ELE_NUM;
4626         buf = rte_zmalloc("i40e", len, 0);
4627         if (!buf) {
4628                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4629                 return I40E_ERR_NO_MEMORY;
4630         }
4631
4632         /* Get, parse the capabilities and save it to hw */
4633         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4634                         i40e_aqc_opc_list_func_capabilities, NULL);
4635         if (ret != I40E_SUCCESS)
4636                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4637
4638         /* Free the temporary buffer after being used */
4639         rte_free(buf);
4640
4641         return ret;
4642 }
4643
4644 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4645
4646 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4647                 const char *value,
4648                 void *opaque)
4649 {
4650         struct i40e_pf *pf;
4651         unsigned long num;
4652         char *end;
4653
4654         pf = (struct i40e_pf *)opaque;
4655         RTE_SET_USED(key);
4656
4657         errno = 0;
4658         num = strtoul(value, &end, 0);
4659         if (errno != 0 || end == value || *end != 0) {
4660                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4661                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4662                 return -(EINVAL);
4663         }
4664
4665         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4666                 pf->vf_nb_qp_max = (uint16_t)num;
4667         else
4668                 /* here return 0 to make next valid same argument work */
4669                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4670                             "power of 2 and equal or less than 16 !, Now it is "
4671                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4672
4673         return 0;
4674 }
4675
4676 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4677 {
4678         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4679         struct rte_kvargs *kvlist;
4680         int kvargs_count;
4681
4682         /* set default queue number per VF as 4 */
4683         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4684
4685         if (dev->device->devargs == NULL)
4686                 return 0;
4687
4688         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4689         if (kvlist == NULL)
4690                 return -(EINVAL);
4691
4692         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4693         if (!kvargs_count) {
4694                 rte_kvargs_free(kvlist);
4695                 return 0;
4696         }
4697
4698         if (kvargs_count > 1)
4699                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4700                             "the first invalid or last valid one is used !",
4701                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4702
4703         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4704                            i40e_pf_parse_vf_queue_number_handler, pf);
4705
4706         rte_kvargs_free(kvlist);
4707
4708         return 0;
4709 }
4710
4711 static int
4712 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4713 {
4714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4715         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4716         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4717         uint16_t qp_count = 0, vsi_count = 0;
4718
4719         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4720                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4721                 return -EINVAL;
4722         }
4723
4724         i40e_pf_config_vf_rxq_number(dev);
4725
4726         /* Add the parameter init for LFC */
4727         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4728         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4729         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4730
4731         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4732         pf->max_num_vsi = hw->func_caps.num_vsis;
4733         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4734         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4735
4736         /* FDir queue/VSI allocation */
4737         pf->fdir_qp_offset = 0;
4738         if (hw->func_caps.fd) {
4739                 pf->flags |= I40E_FLAG_FDIR;
4740                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4741         } else {
4742                 pf->fdir_nb_qps = 0;
4743         }
4744         qp_count += pf->fdir_nb_qps;
4745         vsi_count += 1;
4746
4747         /* LAN queue/VSI allocation */
4748         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4749         if (!hw->func_caps.rss) {
4750                 pf->lan_nb_qps = 1;
4751         } else {
4752                 pf->flags |= I40E_FLAG_RSS;
4753                 if (hw->mac.type == I40E_MAC_X722)
4754                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4755                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4756         }
4757         qp_count += pf->lan_nb_qps;
4758         vsi_count += 1;
4759
4760         /* VF queue/VSI allocation */
4761         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4762         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4763                 pf->flags |= I40E_FLAG_SRIOV;
4764                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4765                 pf->vf_num = pci_dev->max_vfs;
4766                 PMD_DRV_LOG(DEBUG,
4767                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4768                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4769         } else {
4770                 pf->vf_nb_qps = 0;
4771                 pf->vf_num = 0;
4772         }
4773         qp_count += pf->vf_nb_qps * pf->vf_num;
4774         vsi_count += pf->vf_num;
4775
4776         /* VMDq queue/VSI allocation */
4777         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4778         pf->vmdq_nb_qps = 0;
4779         pf->max_nb_vmdq_vsi = 0;
4780         if (hw->func_caps.vmdq) {
4781                 if (qp_count < hw->func_caps.num_tx_qp &&
4782                         vsi_count < hw->func_caps.num_vsis) {
4783                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4784                                 qp_count) / pf->vmdq_nb_qp_max;
4785
4786                         /* Limit the maximum number of VMDq vsi to the maximum
4787                          * ethdev can support
4788                          */
4789                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4790                                 hw->func_caps.num_vsis - vsi_count);
4791                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4792                                 ETH_64_POOLS);
4793                         if (pf->max_nb_vmdq_vsi) {
4794                                 pf->flags |= I40E_FLAG_VMDQ;
4795                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4796                                 PMD_DRV_LOG(DEBUG,
4797                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4798                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4799                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4800                         } else {
4801                                 PMD_DRV_LOG(INFO,
4802                                         "No enough queues left for VMDq");
4803                         }
4804                 } else {
4805                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4806                 }
4807         }
4808         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4809         vsi_count += pf->max_nb_vmdq_vsi;
4810
4811         if (hw->func_caps.dcb)
4812                 pf->flags |= I40E_FLAG_DCB;
4813
4814         if (qp_count > hw->func_caps.num_tx_qp) {
4815                 PMD_DRV_LOG(ERR,
4816                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4817                         qp_count, hw->func_caps.num_tx_qp);
4818                 return -EINVAL;
4819         }
4820         if (vsi_count > hw->func_caps.num_vsis) {
4821                 PMD_DRV_LOG(ERR,
4822                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4823                         vsi_count, hw->func_caps.num_vsis);
4824                 return -EINVAL;
4825         }
4826
4827         return 0;
4828 }
4829
4830 static int
4831 i40e_pf_get_switch_config(struct i40e_pf *pf)
4832 {
4833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834         struct i40e_aqc_get_switch_config_resp *switch_config;
4835         struct i40e_aqc_switch_config_element_resp *element;
4836         uint16_t start_seid = 0, num_reported;
4837         int ret;
4838
4839         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4840                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4841         if (!switch_config) {
4842                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4843                 return -ENOMEM;
4844         }
4845
4846         /* Get the switch configurations */
4847         ret = i40e_aq_get_switch_config(hw, switch_config,
4848                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4849         if (ret != I40E_SUCCESS) {
4850                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4851                 goto fail;
4852         }
4853         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4854         if (num_reported != 1) { /* The number should be 1 */
4855                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4856                 goto fail;
4857         }
4858
4859         /* Parse the switch configuration elements */
4860         element = &(switch_config->element[0]);
4861         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4862                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4863                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4864         } else
4865                 PMD_DRV_LOG(INFO, "Unknown element type");
4866
4867 fail:
4868         rte_free(switch_config);
4869
4870         return ret;
4871 }
4872
4873 static int
4874 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4875                         uint32_t num)
4876 {
4877         struct pool_entry *entry;
4878
4879         if (pool == NULL || num == 0)
4880                 return -EINVAL;
4881
4882         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4883         if (entry == NULL) {
4884                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4885                 return -ENOMEM;
4886         }
4887
4888         /* queue heap initialize */
4889         pool->num_free = num;
4890         pool->num_alloc = 0;
4891         pool->base = base;
4892         LIST_INIT(&pool->alloc_list);
4893         LIST_INIT(&pool->free_list);
4894
4895         /* Initialize element  */
4896         entry->base = 0;
4897         entry->len = num;
4898
4899         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4900         return 0;
4901 }
4902
4903 static void
4904 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4905 {
4906         struct pool_entry *entry, *next_entry;
4907
4908         if (pool == NULL)
4909                 return;
4910
4911         for (entry = LIST_FIRST(&pool->alloc_list);
4912                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4913                         entry = next_entry) {
4914                 LIST_REMOVE(entry, next);
4915                 rte_free(entry);
4916         }
4917
4918         for (entry = LIST_FIRST(&pool->free_list);
4919                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4920                         entry = next_entry) {
4921                 LIST_REMOVE(entry, next);
4922                 rte_free(entry);
4923         }
4924
4925         pool->num_free = 0;
4926         pool->num_alloc = 0;
4927         pool->base = 0;
4928         LIST_INIT(&pool->alloc_list);
4929         LIST_INIT(&pool->free_list);
4930 }
4931
4932 static int
4933 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4934                        uint32_t base)
4935 {
4936         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4937         uint32_t pool_offset;
4938         uint16_t len;
4939         int insert;
4940
4941         if (pool == NULL) {
4942                 PMD_DRV_LOG(ERR, "Invalid parameter");
4943                 return -EINVAL;
4944         }
4945
4946         pool_offset = base - pool->base;
4947         /* Lookup in alloc list */
4948         LIST_FOREACH(entry, &pool->alloc_list, next) {
4949                 if (entry->base == pool_offset) {
4950                         valid_entry = entry;
4951                         LIST_REMOVE(entry, next);
4952                         break;
4953                 }
4954         }
4955
4956         /* Not find, return */
4957         if (valid_entry == NULL) {
4958                 PMD_DRV_LOG(ERR, "Failed to find entry");
4959                 return -EINVAL;
4960         }
4961
4962         /**
4963          * Found it, move it to free list  and try to merge.
4964          * In order to make merge easier, always sort it by qbase.
4965          * Find adjacent prev and last entries.
4966          */
4967         prev = next = NULL;
4968         LIST_FOREACH(entry, &pool->free_list, next) {
4969                 if (entry->base > valid_entry->base) {
4970                         next = entry;
4971                         break;
4972                 }
4973                 prev = entry;
4974         }
4975
4976         insert = 0;
4977         len = valid_entry->len;
4978         /* Try to merge with next one*/
4979         if (next != NULL) {
4980                 /* Merge with next one */
4981                 if (valid_entry->base + len == next->base) {
4982                         next->base = valid_entry->base;
4983                         next->len += len;
4984                         rte_free(valid_entry);
4985                         valid_entry = next;
4986                         insert = 1;
4987                 }
4988         }
4989
4990         if (prev != NULL) {
4991                 /* Merge with previous one */
4992                 if (prev->base + prev->len == valid_entry->base) {
4993                         prev->len += len;
4994                         /* If it merge with next one, remove next node */
4995                         if (insert == 1) {
4996                                 LIST_REMOVE(valid_entry, next);
4997                                 rte_free(valid_entry);
4998                                 valid_entry = NULL;
4999                         } else {
5000                                 rte_free(valid_entry);
5001                                 valid_entry = NULL;
5002                                 insert = 1;
5003                         }
5004                 }
5005         }
5006
5007         /* Not find any entry to merge, insert */
5008         if (insert == 0) {
5009                 if (prev != NULL)
5010                         LIST_INSERT_AFTER(prev, valid_entry, next);
5011                 else if (next != NULL)
5012                         LIST_INSERT_BEFORE(next, valid_entry, next);
5013                 else /* It's empty list, insert to head */
5014                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5015         }
5016
5017         pool->num_free += len;
5018         pool->num_alloc -= len;
5019
5020         return 0;
5021 }
5022
5023 static int
5024 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5025                        uint16_t num)
5026 {
5027         struct pool_entry *entry, *valid_entry;
5028
5029         if (pool == NULL || num == 0) {
5030                 PMD_DRV_LOG(ERR, "Invalid parameter");
5031                 return -EINVAL;
5032         }
5033
5034         if (pool->num_free < num) {
5035                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5036                             num, pool->num_free);
5037                 return -ENOMEM;
5038         }
5039
5040         valid_entry = NULL;
5041         /* Lookup  in free list and find most fit one */
5042         LIST_FOREACH(entry, &pool->free_list, next) {
5043                 if (entry->len >= num) {
5044                         /* Find best one */
5045                         if (entry->len == num) {
5046                                 valid_entry = entry;
5047                                 break;
5048                         }
5049                         if (valid_entry == NULL || valid_entry->len > entry->len)
5050                                 valid_entry = entry;
5051                 }
5052         }
5053
5054         /* Not find one to satisfy the request, return */
5055         if (valid_entry == NULL) {
5056                 PMD_DRV_LOG(ERR, "No valid entry found");
5057                 return -ENOMEM;
5058         }
5059         /**
5060          * The entry have equal queue number as requested,
5061          * remove it from alloc_list.
5062          */
5063         if (valid_entry->len == num) {
5064                 LIST_REMOVE(valid_entry, next);
5065         } else {
5066                 /**
5067                  * The entry have more numbers than requested,
5068                  * create a new entry for alloc_list and minus its
5069                  * queue base and number in free_list.
5070                  */
5071                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5072                 if (entry == NULL) {
5073                         PMD_DRV_LOG(ERR,
5074                                 "Failed to allocate memory for resource pool");
5075                         return -ENOMEM;
5076                 }
5077                 entry->base = valid_entry->base;
5078                 entry->len = num;
5079                 valid_entry->base += num;
5080                 valid_entry->len -= num;
5081                 valid_entry = entry;
5082         }
5083
5084         /* Insert it into alloc list, not sorted */
5085         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5086
5087         pool->num_free -= valid_entry->len;
5088         pool->num_alloc += valid_entry->len;
5089
5090         return valid_entry->base + pool->base;
5091 }
5092
5093 /**
5094  * bitmap_is_subset - Check whether src2 is subset of src1
5095  **/
5096 static inline int
5097 bitmap_is_subset(uint8_t src1, uint8_t src2)
5098 {
5099         return !((src1 ^ src2) & src2);
5100 }
5101
5102 static enum i40e_status_code
5103 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5104 {
5105         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5106
5107         /* If DCB is not supported, only default TC is supported */
5108         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5109                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5110                 return I40E_NOT_SUPPORTED;
5111         }
5112
5113         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5114                 PMD_DRV_LOG(ERR,
5115                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5116                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5117                 return I40E_NOT_SUPPORTED;
5118         }
5119         return I40E_SUCCESS;
5120 }
5121
5122 int
5123 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5124                                 struct i40e_vsi_vlan_pvid_info *info)
5125 {
5126         struct i40e_hw *hw;
5127         struct i40e_vsi_context ctxt;
5128         uint8_t vlan_flags = 0;
5129         int ret;
5130
5131         if (vsi == NULL || info == NULL) {
5132                 PMD_DRV_LOG(ERR, "invalid parameters");
5133                 return I40E_ERR_PARAM;
5134         }
5135
5136         if (info->on) {
5137                 vsi->info.pvid = info->config.pvid;
5138                 /**
5139                  * If insert pvid is enabled, only tagged pkts are
5140                  * allowed to be sent out.
5141                  */
5142                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5143                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5144         } else {
5145                 vsi->info.pvid = 0;
5146                 if (info->config.reject.tagged == 0)
5147                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5148
5149                 if (info->config.reject.untagged == 0)
5150                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5151         }
5152         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5153                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5154         vsi->info.port_vlan_flags |= vlan_flags;
5155         vsi->info.valid_sections =
5156                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5157         memset(&ctxt, 0, sizeof(ctxt));
5158         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5159         ctxt.seid = vsi->seid;
5160
5161         hw = I40E_VSI_TO_HW(vsi);
5162         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5163         if (ret != I40E_SUCCESS)
5164                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5165
5166         return ret;
5167 }
5168
5169 static int
5170 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5171 {
5172         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5173         int i, ret;
5174         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5175
5176         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5177         if (ret != I40E_SUCCESS)
5178                 return ret;
5179
5180         if (!vsi->seid) {
5181                 PMD_DRV_LOG(ERR, "seid not valid");
5182                 return -EINVAL;
5183         }
5184
5185         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5186         tc_bw_data.tc_valid_bits = enabled_tcmap;
5187         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5188                 tc_bw_data.tc_bw_credits[i] =
5189                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5190
5191         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5192         if (ret != I40E_SUCCESS) {
5193                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5194                 return ret;
5195         }
5196
5197         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5198                                         sizeof(vsi->info.qs_handle));
5199         return I40E_SUCCESS;
5200 }
5201
5202 static enum i40e_status_code
5203 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5204                                  struct i40e_aqc_vsi_properties_data *info,
5205                                  uint8_t enabled_tcmap)
5206 {
5207         enum i40e_status_code ret;
5208         int i, total_tc = 0;
5209         uint16_t qpnum_per_tc, bsf, qp_idx;
5210
5211         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5212         if (ret != I40E_SUCCESS)
5213                 return ret;
5214
5215         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5216                 if (enabled_tcmap & (1 << i))
5217                         total_tc++;
5218         if (total_tc == 0)
5219                 total_tc = 1;
5220         vsi->enabled_tc = enabled_tcmap;
5221
5222         /* Number of queues per enabled TC */
5223         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5224         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5225         bsf = rte_bsf32(qpnum_per_tc);
5226
5227         /* Adjust the queue number to actual queues that can be applied */
5228         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5229                 vsi->nb_qps = qpnum_per_tc * total_tc;
5230
5231         /**
5232          * Configure TC and queue mapping parameters, for enabled TC,
5233          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5234          * default queue will serve it.
5235          */
5236         qp_idx = 0;
5237         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5238                 if (vsi->enabled_tc & (1 << i)) {
5239                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5240                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5241                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5242                         qp_idx += qpnum_per_tc;
5243                 } else
5244                         info->tc_mapping[i] = 0;
5245         }
5246
5247         /* Associate queue number with VSI */
5248         if (vsi->type == I40E_VSI_SRIOV) {
5249                 info->mapping_flags |=
5250                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5251                 for (i = 0; i < vsi->nb_qps; i++)
5252                         info->queue_mapping[i] =
5253                                 rte_cpu_to_le_16(vsi->base_queue + i);
5254         } else {
5255                 info->mapping_flags |=
5256                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5257                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5258         }
5259         info->valid_sections |=
5260                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5261
5262         return I40E_SUCCESS;
5263 }
5264
5265 static int
5266 i40e_veb_release(struct i40e_veb *veb)
5267 {
5268         struct i40e_vsi *vsi;
5269         struct i40e_hw *hw;
5270
5271         if (veb == NULL)
5272                 return -EINVAL;
5273
5274         if (!TAILQ_EMPTY(&veb->head)) {
5275                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5276                 return -EACCES;
5277         }
5278         /* associate_vsi field is NULL for floating VEB */
5279         if (veb->associate_vsi != NULL) {
5280                 vsi = veb->associate_vsi;
5281                 hw = I40E_VSI_TO_HW(vsi);
5282
5283                 vsi->uplink_seid = veb->uplink_seid;
5284                 vsi->veb = NULL;
5285         } else {
5286                 veb->associate_pf->main_vsi->floating_veb = NULL;
5287                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5288         }
5289
5290         i40e_aq_delete_element(hw, veb->seid, NULL);
5291         rte_free(veb);
5292         return I40E_SUCCESS;
5293 }
5294
5295 /* Setup a veb */
5296 static struct i40e_veb *
5297 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5298 {
5299         struct i40e_veb *veb;
5300         int ret;
5301         struct i40e_hw *hw;
5302
5303         if (pf == NULL) {
5304                 PMD_DRV_LOG(ERR,
5305                             "veb setup failed, associated PF shouldn't null");
5306                 return NULL;
5307         }
5308         hw = I40E_PF_TO_HW(pf);
5309
5310         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5311         if (!veb) {
5312                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5313                 goto fail;
5314         }
5315
5316         veb->associate_vsi = vsi;
5317         veb->associate_pf = pf;
5318         TAILQ_INIT(&veb->head);
5319         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5320
5321         /* create floating veb if vsi is NULL */
5322         if (vsi != NULL) {
5323                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5324                                       I40E_DEFAULT_TCMAP, false,
5325                                       &veb->seid, false, NULL);
5326         } else {
5327                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5328                                       true, &veb->seid, false, NULL);
5329         }
5330
5331         if (ret != I40E_SUCCESS) {
5332                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5333                             hw->aq.asq_last_status);
5334                 goto fail;
5335         }
5336         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5337
5338         /* get statistics index */
5339         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5340                                 &veb->stats_idx, NULL, NULL, NULL);
5341         if (ret != I40E_SUCCESS) {
5342                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5343                             hw->aq.asq_last_status);
5344                 goto fail;
5345         }
5346         /* Get VEB bandwidth, to be implemented */
5347         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5348         if (vsi)
5349                 vsi->uplink_seid = veb->seid;
5350
5351         return veb;
5352 fail:
5353         rte_free(veb);
5354         return NULL;
5355 }
5356
5357 int
5358 i40e_vsi_release(struct i40e_vsi *vsi)
5359 {
5360         struct i40e_pf *pf;
5361         struct i40e_hw *hw;
5362         struct i40e_vsi_list *vsi_list;
5363         void *temp;
5364         int ret;
5365         struct i40e_mac_filter *f;
5366         uint16_t user_param;
5367
5368         if (!vsi)
5369                 return I40E_SUCCESS;
5370
5371         if (!vsi->adapter)
5372                 return -EFAULT;
5373
5374         user_param = vsi->user_param;
5375
5376         pf = I40E_VSI_TO_PF(vsi);
5377         hw = I40E_VSI_TO_HW(vsi);
5378
5379         /* VSI has child to attach, release child first */
5380         if (vsi->veb) {
5381                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5382                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5383                                 return -1;
5384                 }
5385                 i40e_veb_release(vsi->veb);
5386         }
5387
5388         if (vsi->floating_veb) {
5389                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5390                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5391                                 return -1;
5392                 }
5393         }
5394
5395         /* Remove all macvlan filters of the VSI */
5396         i40e_vsi_remove_all_macvlan_filter(vsi);
5397         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5398                 rte_free(f);
5399
5400         if (vsi->type != I40E_VSI_MAIN &&
5401             ((vsi->type != I40E_VSI_SRIOV) ||
5402             !pf->floating_veb_list[user_param])) {
5403                 /* Remove vsi from parent's sibling list */
5404                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5405                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5406                         return I40E_ERR_PARAM;
5407                 }
5408                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5409                                 &vsi->sib_vsi_list, list);
5410
5411                 /* Remove all switch element of the VSI */
5412                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5413                 if (ret != I40E_SUCCESS)
5414                         PMD_DRV_LOG(ERR, "Failed to delete element");
5415         }
5416
5417         if ((vsi->type == I40E_VSI_SRIOV) &&
5418             pf->floating_veb_list[user_param]) {
5419                 /* Remove vsi from parent's sibling list */
5420                 if (vsi->parent_vsi == NULL ||
5421                     vsi->parent_vsi->floating_veb == NULL) {
5422                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5423                         return I40E_ERR_PARAM;
5424                 }
5425                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5426                              &vsi->sib_vsi_list, list);
5427
5428                 /* Remove all switch element of the VSI */
5429                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5430                 if (ret != I40E_SUCCESS)
5431                         PMD_DRV_LOG(ERR, "Failed to delete element");
5432         }
5433
5434         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5435
5436         if (vsi->type != I40E_VSI_SRIOV)
5437                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5438         rte_free(vsi);
5439
5440         return I40E_SUCCESS;
5441 }
5442
5443 static int
5444 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5445 {
5446         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5447         struct i40e_aqc_remove_macvlan_element_data def_filter;
5448         struct i40e_mac_filter_info filter;
5449         int ret;
5450
5451         if (vsi->type != I40E_VSI_MAIN)
5452                 return I40E_ERR_CONFIG;
5453         memset(&def_filter, 0, sizeof(def_filter));
5454         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5455                                         ETH_ADDR_LEN);
5456         def_filter.vlan_tag = 0;
5457         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5458                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5459         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5460         if (ret != I40E_SUCCESS) {
5461                 struct i40e_mac_filter *f;
5462                 struct rte_ether_addr *mac;
5463
5464                 PMD_DRV_LOG(DEBUG,
5465                             "Cannot remove the default macvlan filter");
5466                 /* It needs to add the permanent mac into mac list */
5467                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5468                 if (f == NULL) {
5469                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5470                         return I40E_ERR_NO_MEMORY;
5471                 }
5472                 mac = &f->mac_info.mac_addr;
5473                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5474                                 ETH_ADDR_LEN);
5475                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5476                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5477                 vsi->mac_num++;
5478
5479                 return ret;
5480         }
5481         rte_memcpy(&filter.mac_addr,
5482                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5483         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5484         return i40e_vsi_add_mac(vsi, &filter);
5485 }
5486
5487 /*
5488  * i40e_vsi_get_bw_config - Query VSI BW Information
5489  * @vsi: the VSI to be queried
5490  *
5491  * Returns 0 on success, negative value on failure
5492  */
5493 static enum i40e_status_code
5494 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5495 {
5496         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5497         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5498         struct i40e_hw *hw = &vsi->adapter->hw;
5499         i40e_status ret;
5500         int i;
5501         uint32_t bw_max;
5502
5503         memset(&bw_config, 0, sizeof(bw_config));
5504         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5505         if (ret != I40E_SUCCESS) {
5506                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5507                             hw->aq.asq_last_status);
5508                 return ret;
5509         }
5510
5511         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5512         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5513                                         &ets_sla_config, NULL);
5514         if (ret != I40E_SUCCESS) {
5515                 PMD_DRV_LOG(ERR,
5516                         "VSI failed to get TC bandwdith configuration %u",
5517                         hw->aq.asq_last_status);
5518                 return ret;
5519         }
5520
5521         /* store and print out BW info */
5522         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5523         vsi->bw_info.bw_max = bw_config.max_bw;
5524         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5525         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5526         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5527                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5528                      I40E_16_BIT_WIDTH);
5529         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5530                 vsi->bw_info.bw_ets_share_credits[i] =
5531                                 ets_sla_config.share_credits[i];
5532                 vsi->bw_info.bw_ets_credits[i] =
5533                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5534                 /* 4 bits per TC, 4th bit is reserved */
5535                 vsi->bw_info.bw_ets_max[i] =
5536                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5537                                   RTE_LEN2MASK(3, uint8_t));
5538                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5539                             vsi->bw_info.bw_ets_share_credits[i]);
5540                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5541                             vsi->bw_info.bw_ets_credits[i]);
5542                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5543                             vsi->bw_info.bw_ets_max[i]);
5544         }
5545
5546         return I40E_SUCCESS;
5547 }
5548
5549 /* i40e_enable_pf_lb
5550  * @pf: pointer to the pf structure
5551  *
5552  * allow loopback on pf
5553  */
5554 static inline void
5555 i40e_enable_pf_lb(struct i40e_pf *pf)
5556 {
5557         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5558         struct i40e_vsi_context ctxt;
5559         int ret;
5560
5561         /* Use the FW API if FW >= v5.0 */
5562         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5563                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5564                 return;
5565         }
5566
5567         memset(&ctxt, 0, sizeof(ctxt));
5568         ctxt.seid = pf->main_vsi_seid;
5569         ctxt.pf_num = hw->pf_id;
5570         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5571         if (ret) {
5572                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5573                             ret, hw->aq.asq_last_status);
5574                 return;
5575         }
5576         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5577         ctxt.info.valid_sections =
5578                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5579         ctxt.info.switch_id |=
5580                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5581
5582         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5583         if (ret)
5584                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5585                             hw->aq.asq_last_status);
5586 }
5587
5588 /* Setup a VSI */
5589 struct i40e_vsi *
5590 i40e_vsi_setup(struct i40e_pf *pf,
5591                enum i40e_vsi_type type,
5592                struct i40e_vsi *uplink_vsi,
5593                uint16_t user_param)
5594 {
5595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5596         struct i40e_vsi *vsi;
5597         struct i40e_mac_filter_info filter;
5598         int ret;
5599         struct i40e_vsi_context ctxt;
5600         struct rte_ether_addr broadcast =
5601                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5602
5603         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5604             uplink_vsi == NULL) {
5605                 PMD_DRV_LOG(ERR,
5606                         "VSI setup failed, VSI link shouldn't be NULL");
5607                 return NULL;
5608         }
5609
5610         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5611                 PMD_DRV_LOG(ERR,
5612                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5613                 return NULL;
5614         }
5615
5616         /* two situations
5617          * 1.type is not MAIN and uplink vsi is not NULL
5618          * If uplink vsi didn't setup VEB, create one first under veb field
5619          * 2.type is SRIOV and the uplink is NULL
5620          * If floating VEB is NULL, create one veb under floating veb field
5621          */
5622
5623         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5624             uplink_vsi->veb == NULL) {
5625                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5626
5627                 if (uplink_vsi->veb == NULL) {
5628                         PMD_DRV_LOG(ERR, "VEB setup failed");
5629                         return NULL;
5630                 }
5631                 /* set ALLOWLOOPBACk on pf, when veb is created */
5632                 i40e_enable_pf_lb(pf);
5633         }
5634
5635         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5636             pf->main_vsi->floating_veb == NULL) {
5637                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5638
5639                 if (pf->main_vsi->floating_veb == NULL) {
5640                         PMD_DRV_LOG(ERR, "VEB setup failed");
5641                         return NULL;
5642                 }
5643         }
5644
5645         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5646         if (!vsi) {
5647                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5648                 return NULL;
5649         }
5650         TAILQ_INIT(&vsi->mac_list);
5651         vsi->type = type;
5652         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5653         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5654         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5655         vsi->user_param = user_param;
5656         vsi->vlan_anti_spoof_on = 0;
5657         vsi->vlan_filter_on = 0;
5658         /* Allocate queues */
5659         switch (vsi->type) {
5660         case I40E_VSI_MAIN  :
5661                 vsi->nb_qps = pf->lan_nb_qps;
5662                 break;
5663         case I40E_VSI_SRIOV :
5664                 vsi->nb_qps = pf->vf_nb_qps;
5665                 break;
5666         case I40E_VSI_VMDQ2:
5667                 vsi->nb_qps = pf->vmdq_nb_qps;
5668                 break;
5669         case I40E_VSI_FDIR:
5670                 vsi->nb_qps = pf->fdir_nb_qps;
5671                 break;
5672         default:
5673                 goto fail_mem;
5674         }
5675         /*
5676          * The filter status descriptor is reported in rx queue 0,
5677          * while the tx queue for fdir filter programming has no
5678          * such constraints, can be non-zero queues.
5679          * To simplify it, choose FDIR vsi use queue 0 pair.
5680          * To make sure it will use queue 0 pair, queue allocation
5681          * need be done before this function is called
5682          */
5683         if (type != I40E_VSI_FDIR) {
5684                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5685                         if (ret < 0) {
5686                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5687                                                 vsi->seid, ret);
5688                                 goto fail_mem;
5689                         }
5690                         vsi->base_queue = ret;
5691         } else
5692                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5693
5694         /* VF has MSIX interrupt in VF range, don't allocate here */
5695         if (type == I40E_VSI_MAIN) {
5696                 if (pf->support_multi_driver) {
5697                         /* If support multi-driver, need to use INT0 instead of
5698                          * allocating from msix pool. The Msix pool is init from
5699                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5700                          * to 1 without calling i40e_res_pool_alloc.
5701                          */
5702                         vsi->msix_intr = 0;
5703                         vsi->nb_msix = 1;
5704                 } else {
5705                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5706                                                   RTE_MIN(vsi->nb_qps,
5707                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5708                         if (ret < 0) {
5709                                 PMD_DRV_LOG(ERR,
5710                                             "VSI MAIN %d get heap failed %d",
5711                                             vsi->seid, ret);
5712                                 goto fail_queue_alloc;
5713                         }
5714                         vsi->msix_intr = ret;
5715                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5716                                                RTE_MAX_RXTX_INTR_VEC_ID);
5717                 }
5718         } else if (type != I40E_VSI_SRIOV) {
5719                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5720                 if (ret < 0) {
5721                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5722                         goto fail_queue_alloc;
5723                 }
5724                 vsi->msix_intr = ret;
5725                 vsi->nb_msix = 1;
5726         } else {
5727                 vsi->msix_intr = 0;
5728                 vsi->nb_msix = 0;
5729         }
5730
5731         /* Add VSI */
5732         if (type == I40E_VSI_MAIN) {
5733                 /* For main VSI, no need to add since it's default one */
5734                 vsi->uplink_seid = pf->mac_seid;
5735                 vsi->seid = pf->main_vsi_seid;
5736                 /* Bind queues with specific MSIX interrupt */
5737                 /**
5738                  * Needs 2 interrupt at least, one for misc cause which will
5739                  * enabled from OS side, Another for queues binding the
5740                  * interrupt from device side only.
5741                  */
5742
5743                 /* Get default VSI parameters from hardware */
5744                 memset(&ctxt, 0, sizeof(ctxt));
5745                 ctxt.seid = vsi->seid;
5746                 ctxt.pf_num = hw->pf_id;
5747                 ctxt.uplink_seid = vsi->uplink_seid;
5748                 ctxt.vf_num = 0;
5749                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5750                 if (ret != I40E_SUCCESS) {
5751                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5752                         goto fail_msix_alloc;
5753                 }
5754                 rte_memcpy(&vsi->info, &ctxt.info,
5755                         sizeof(struct i40e_aqc_vsi_properties_data));
5756                 vsi->vsi_id = ctxt.vsi_number;
5757                 vsi->info.valid_sections = 0;
5758
5759                 /* Configure tc, enabled TC0 only */
5760                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5761                         I40E_SUCCESS) {
5762                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5763                         goto fail_msix_alloc;
5764                 }
5765
5766                 /* TC, queue mapping */
5767                 memset(&ctxt, 0, sizeof(ctxt));
5768                 vsi->info.valid_sections |=
5769                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5770                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5771                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5772                 rte_memcpy(&ctxt.info, &vsi->info,
5773                         sizeof(struct i40e_aqc_vsi_properties_data));
5774                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5775                                                 I40E_DEFAULT_TCMAP);
5776                 if (ret != I40E_SUCCESS) {
5777                         PMD_DRV_LOG(ERR,
5778                                 "Failed to configure TC queue mapping");
5779                         goto fail_msix_alloc;
5780                 }
5781                 ctxt.seid = vsi->seid;
5782                 ctxt.pf_num = hw->pf_id;
5783                 ctxt.uplink_seid = vsi->uplink_seid;
5784                 ctxt.vf_num = 0;
5785
5786                 /* Update VSI parameters */
5787                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5788                 if (ret != I40E_SUCCESS) {
5789                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5790                         goto fail_msix_alloc;
5791                 }
5792
5793                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5794                                                 sizeof(vsi->info.tc_mapping));
5795                 rte_memcpy(&vsi->info.queue_mapping,
5796                                 &ctxt.info.queue_mapping,
5797                         sizeof(vsi->info.queue_mapping));
5798                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5799                 vsi->info.valid_sections = 0;
5800
5801                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5802                                 ETH_ADDR_LEN);
5803
5804                 /**
5805                  * Updating default filter settings are necessary to prevent
5806                  * reception of tagged packets.
5807                  * Some old firmware configurations load a default macvlan
5808                  * filter which accepts both tagged and untagged packets.
5809                  * The updating is to use a normal filter instead if needed.
5810                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5811                  * The firmware with correct configurations load the default
5812                  * macvlan filter which is expected and cannot be removed.
5813                  */
5814                 i40e_update_default_filter_setting(vsi);
5815                 i40e_config_qinq(hw, vsi);
5816         } else if (type == I40E_VSI_SRIOV) {
5817                 memset(&ctxt, 0, sizeof(ctxt));
5818                 /**
5819                  * For other VSI, the uplink_seid equals to uplink VSI's
5820                  * uplink_seid since they share same VEB
5821                  */
5822                 if (uplink_vsi == NULL)
5823                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5824                 else
5825                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5826                 ctxt.pf_num = hw->pf_id;
5827                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5828                 ctxt.uplink_seid = vsi->uplink_seid;
5829                 ctxt.connection_type = 0x1;
5830                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5831
5832                 /* Use the VEB configuration if FW >= v5.0 */
5833                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5834                         /* Configure switch ID */
5835                         ctxt.info.valid_sections |=
5836                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5837                         ctxt.info.switch_id =
5838                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5839                 }
5840
5841                 /* Configure port/vlan */
5842                 ctxt.info.valid_sections |=
5843                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5844                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5845                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5846                                                 hw->func_caps.enabled_tcmap);
5847                 if (ret != I40E_SUCCESS) {
5848                         PMD_DRV_LOG(ERR,
5849                                 "Failed to configure TC queue mapping");
5850                         goto fail_msix_alloc;
5851                 }
5852
5853                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5854                 ctxt.info.valid_sections |=
5855                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5856                 /**
5857                  * Since VSI is not created yet, only configure parameter,
5858                  * will add vsi below.
5859                  */
5860
5861                 i40e_config_qinq(hw, vsi);
5862         } else if (type == I40E_VSI_VMDQ2) {
5863                 memset(&ctxt, 0, sizeof(ctxt));
5864                 /*
5865                  * For other VSI, the uplink_seid equals to uplink VSI's
5866                  * uplink_seid since they share same VEB
5867                  */
5868                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5869                 ctxt.pf_num = hw->pf_id;
5870                 ctxt.vf_num = 0;
5871                 ctxt.uplink_seid = vsi->uplink_seid;
5872                 ctxt.connection_type = 0x1;
5873                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5874
5875                 ctxt.info.valid_sections |=
5876                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5877                 /* user_param carries flag to enable loop back */
5878                 if (user_param) {
5879                         ctxt.info.switch_id =
5880                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5881                         ctxt.info.switch_id |=
5882                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5883                 }
5884
5885                 /* Configure port/vlan */
5886                 ctxt.info.valid_sections |=
5887                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5888                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5889                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5890                                                 I40E_DEFAULT_TCMAP);
5891                 if (ret != I40E_SUCCESS) {
5892                         PMD_DRV_LOG(ERR,
5893                                 "Failed to configure TC queue mapping");
5894                         goto fail_msix_alloc;
5895                 }
5896                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5897                 ctxt.info.valid_sections |=
5898                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5899         } else if (type == I40E_VSI_FDIR) {
5900                 memset(&ctxt, 0, sizeof(ctxt));
5901                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5902                 ctxt.pf_num = hw->pf_id;
5903                 ctxt.vf_num = 0;
5904                 ctxt.uplink_seid = vsi->uplink_seid;
5905                 ctxt.connection_type = 0x1;     /* regular data port */
5906                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5907                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5908                                                 I40E_DEFAULT_TCMAP);
5909                 if (ret != I40E_SUCCESS) {
5910                         PMD_DRV_LOG(ERR,
5911                                 "Failed to configure TC queue mapping.");
5912                         goto fail_msix_alloc;
5913                 }
5914                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5915                 ctxt.info.valid_sections |=
5916                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5917         } else {
5918                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5919                 goto fail_msix_alloc;
5920         }
5921
5922         if (vsi->type != I40E_VSI_MAIN) {
5923                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5924                 if (ret != I40E_SUCCESS) {
5925                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5926                                     hw->aq.asq_last_status);
5927                         goto fail_msix_alloc;
5928                 }
5929                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5930                 vsi->info.valid_sections = 0;
5931                 vsi->seid = ctxt.seid;
5932                 vsi->vsi_id = ctxt.vsi_number;
5933                 vsi->sib_vsi_list.vsi = vsi;
5934                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5935                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5936                                           &vsi->sib_vsi_list, list);
5937                 } else {
5938                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5939                                           &vsi->sib_vsi_list, list);
5940                 }
5941         }
5942
5943         /* MAC/VLAN configuration */
5944         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5945         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5946
5947         ret = i40e_vsi_add_mac(vsi, &filter);
5948         if (ret != I40E_SUCCESS) {
5949                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5950                 goto fail_msix_alloc;
5951         }
5952
5953         /* Get VSI BW information */
5954         i40e_vsi_get_bw_config(vsi);
5955         return vsi;
5956 fail_msix_alloc:
5957         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5958 fail_queue_alloc:
5959         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5960 fail_mem:
5961         rte_free(vsi);
5962         return NULL;
5963 }
5964
5965 /* Configure vlan filter on or off */
5966 int
5967 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5968 {
5969         int i, num;
5970         struct i40e_mac_filter *f;
5971         void *temp;
5972         struct i40e_mac_filter_info *mac_filter;
5973         enum rte_mac_filter_type desired_filter;
5974         int ret = I40E_SUCCESS;
5975
5976         if (on) {
5977                 /* Filter to match MAC and VLAN */
5978                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5979         } else {
5980                 /* Filter to match only MAC */
5981                 desired_filter = RTE_MAC_PERFECT_MATCH;
5982         }
5983
5984         num = vsi->mac_num;
5985
5986         mac_filter = rte_zmalloc("mac_filter_info_data",
5987                                  num * sizeof(*mac_filter), 0);
5988         if (mac_filter == NULL) {
5989                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5990                 return I40E_ERR_NO_MEMORY;
5991         }
5992
5993         i = 0;
5994
5995         /* Remove all existing mac */
5996         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5997                 mac_filter[i] = f->mac_info;
5998                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5999                 if (ret) {
6000                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6001                                     on ? "enable" : "disable");
6002                         goto DONE;
6003                 }
6004                 i++;
6005         }
6006
6007         /* Override with new filter */
6008         for (i = 0; i < num; i++) {
6009                 mac_filter[i].filter_type = desired_filter;
6010                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6011                 if (ret) {
6012                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6013                                     on ? "enable" : "disable");
6014                         goto DONE;
6015                 }
6016         }
6017
6018 DONE:
6019         rte_free(mac_filter);
6020         return ret;
6021 }
6022
6023 /* Configure vlan stripping on or off */
6024 int
6025 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6026 {
6027         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6028         struct i40e_vsi_context ctxt;
6029         uint8_t vlan_flags;
6030         int ret = I40E_SUCCESS;
6031
6032         /* Check if it has been already on or off */
6033         if (vsi->info.valid_sections &
6034                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6035                 if (on) {
6036                         if ((vsi->info.port_vlan_flags &
6037                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6038                                 return 0; /* already on */
6039                 } else {
6040                         if ((vsi->info.port_vlan_flags &
6041                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6042                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6043                                 return 0; /* already off */
6044                 }
6045         }
6046
6047         if (on)
6048                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6049         else
6050                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6051         vsi->info.valid_sections =
6052                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6053         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6054         vsi->info.port_vlan_flags |= vlan_flags;
6055         ctxt.seid = vsi->seid;
6056         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6057         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6058         if (ret)
6059                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6060                             on ? "enable" : "disable");
6061
6062         return ret;
6063 }
6064
6065 static int
6066 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6067 {
6068         struct rte_eth_dev_data *data = dev->data;
6069         int ret;
6070         int mask = 0;
6071
6072         /* Apply vlan offload setting */
6073         mask = ETH_VLAN_STRIP_MASK |
6074                ETH_VLAN_FILTER_MASK |
6075                ETH_VLAN_EXTEND_MASK;
6076         ret = i40e_vlan_offload_set(dev, mask);
6077         if (ret) {
6078                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6079                 return ret;
6080         }
6081
6082         /* Apply pvid setting */
6083         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6084                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6085         if (ret)
6086                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6087
6088         return ret;
6089 }
6090
6091 static int
6092 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6093 {
6094         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6095
6096         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6097 }
6098
6099 static int
6100 i40e_update_flow_control(struct i40e_hw *hw)
6101 {
6102 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6103         struct i40e_link_status link_status;
6104         uint32_t rxfc = 0, txfc = 0, reg;
6105         uint8_t an_info;
6106         int ret;
6107
6108         memset(&link_status, 0, sizeof(link_status));
6109         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6110         if (ret != I40E_SUCCESS) {
6111                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6112                 goto write_reg; /* Disable flow control */
6113         }
6114
6115         an_info = hw->phy.link_info.an_info;
6116         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6117                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6118                 ret = I40E_ERR_NOT_READY;
6119                 goto write_reg; /* Disable flow control */
6120         }
6121         /**
6122          * If link auto negotiation is enabled, flow control needs to
6123          * be configured according to it
6124          */
6125         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6126         case I40E_LINK_PAUSE_RXTX:
6127                 rxfc = 1;
6128                 txfc = 1;
6129                 hw->fc.current_mode = I40E_FC_FULL;
6130                 break;
6131         case I40E_AQ_LINK_PAUSE_RX:
6132                 rxfc = 1;
6133                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6134                 break;
6135         case I40E_AQ_LINK_PAUSE_TX:
6136                 txfc = 1;
6137                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6138                 break;
6139         default:
6140                 hw->fc.current_mode = I40E_FC_NONE;
6141                 break;
6142         }
6143
6144 write_reg:
6145         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6146                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6147         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6148         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6149         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6150         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6151
6152         return ret;
6153 }
6154
6155 /* PF setup */
6156 static int
6157 i40e_pf_setup(struct i40e_pf *pf)
6158 {
6159         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6160         struct i40e_filter_control_settings settings;
6161         struct i40e_vsi *vsi;
6162         int ret;
6163
6164         /* Clear all stats counters */
6165         pf->offset_loaded = FALSE;
6166         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6167         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6168         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6169         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6170
6171         ret = i40e_pf_get_switch_config(pf);
6172         if (ret != I40E_SUCCESS) {
6173                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6174                 return ret;
6175         }
6176
6177         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6178         if (ret)
6179                 PMD_INIT_LOG(WARNING,
6180                         "failed to allocate switch domain for device %d", ret);
6181
6182         if (pf->flags & I40E_FLAG_FDIR) {
6183                 /* make queue allocated first, let FDIR use queue pair 0*/
6184                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6185                 if (ret != I40E_FDIR_QUEUE_ID) {
6186                         PMD_DRV_LOG(ERR,
6187                                 "queue allocation fails for FDIR: ret =%d",
6188                                 ret);
6189                         pf->flags &= ~I40E_FLAG_FDIR;
6190                 }
6191         }
6192         /*  main VSI setup */
6193         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6194         if (!vsi) {
6195                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6196                 return I40E_ERR_NOT_READY;
6197         }
6198         pf->main_vsi = vsi;
6199
6200         /* Configure filter control */
6201         memset(&settings, 0, sizeof(settings));
6202         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6203                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6204         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6205                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6206         else {
6207                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6208                         hw->func_caps.rss_table_size);
6209                 return I40E_ERR_PARAM;
6210         }
6211         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6212                 hw->func_caps.rss_table_size);
6213         pf->hash_lut_size = hw->func_caps.rss_table_size;
6214
6215         /* Enable ethtype and macvlan filters */
6216         settings.enable_ethtype = TRUE;
6217         settings.enable_macvlan = TRUE;
6218         ret = i40e_set_filter_control(hw, &settings);
6219         if (ret)
6220                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6221                                                                 ret);
6222
6223         /* Update flow control according to the auto negotiation */
6224         i40e_update_flow_control(hw);
6225
6226         return I40E_SUCCESS;
6227 }
6228
6229 int
6230 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6231 {
6232         uint32_t reg;
6233         uint16_t j;
6234
6235         /**
6236          * Set or clear TX Queue Disable flags,
6237          * which is required by hardware.
6238          */
6239         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6240         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6241
6242         /* Wait until the request is finished */
6243         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6244                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6245                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6246                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6247                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6248                                                         & 0x1))) {
6249                         break;
6250                 }
6251         }
6252         if (on) {
6253                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6254                         return I40E_SUCCESS; /* already on, skip next steps */
6255
6256                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6257                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6258         } else {
6259                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6260                         return I40E_SUCCESS; /* already off, skip next steps */
6261                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6262         }
6263         /* Write the register */
6264         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6265         /* Check the result */
6266         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6267                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6268                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6269                 if (on) {
6270                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6271                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6272                                 break;
6273                 } else {
6274                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6275                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6276                                 break;
6277                 }
6278         }
6279         /* Check if it is timeout */
6280         if (j >= I40E_CHK_Q_ENA_COUNT) {
6281                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6282                             (on ? "enable" : "disable"), q_idx);
6283                 return I40E_ERR_TIMEOUT;
6284         }
6285
6286         return I40E_SUCCESS;
6287 }
6288
6289 /* Swith on or off the tx queues */
6290 static int
6291 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6292 {
6293         struct rte_eth_dev_data *dev_data = pf->dev_data;
6294         struct i40e_tx_queue *txq;
6295         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6296         uint16_t i;
6297         int ret;
6298
6299         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6300                 txq = dev_data->tx_queues[i];
6301                 /* Don't operate the queue if not configured or
6302                  * if starting only per queue */
6303                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6304                         continue;
6305                 if (on)
6306                         ret = i40e_dev_tx_queue_start(dev, i);
6307                 else
6308                         ret = i40e_dev_tx_queue_stop(dev, i);
6309                 if ( ret != I40E_SUCCESS)
6310                         return ret;
6311         }
6312
6313         return I40E_SUCCESS;
6314 }
6315
6316 int
6317 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6318 {
6319         uint32_t reg;
6320         uint16_t j;
6321
6322         /* Wait until the request is finished */
6323         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6324                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6325                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6326                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6327                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6328                         break;
6329         }
6330
6331         if (on) {
6332                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6333                         return I40E_SUCCESS; /* Already on, skip next steps */
6334                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6335         } else {
6336                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6337                         return I40E_SUCCESS; /* Already off, skip next steps */
6338                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6339         }
6340
6341         /* Write the register */
6342         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6343         /* Check the result */
6344         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6345                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6346                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6347                 if (on) {
6348                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6349                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6350                                 break;
6351                 } else {
6352                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6353                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6354                                 break;
6355                 }
6356         }
6357
6358         /* Check if it is timeout */
6359         if (j >= I40E_CHK_Q_ENA_COUNT) {
6360                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6361                             (on ? "enable" : "disable"), q_idx);
6362                 return I40E_ERR_TIMEOUT;
6363         }
6364
6365         return I40E_SUCCESS;
6366 }
6367 /* Switch on or off the rx queues */
6368 static int
6369 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6370 {
6371         struct rte_eth_dev_data *dev_data = pf->dev_data;
6372         struct i40e_rx_queue *rxq;
6373         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6374         uint16_t i;
6375         int ret;
6376
6377         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6378                 rxq = dev_data->rx_queues[i];
6379                 /* Don't operate the queue if not configured or
6380                  * if starting only per queue */
6381                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6382                         continue;
6383                 if (on)
6384                         ret = i40e_dev_rx_queue_start(dev, i);
6385                 else
6386                         ret = i40e_dev_rx_queue_stop(dev, i);
6387                 if (ret != I40E_SUCCESS)
6388                         return ret;
6389         }
6390
6391         return I40E_SUCCESS;
6392 }
6393
6394 /* Switch on or off all the rx/tx queues */
6395 int
6396 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6397 {
6398         int ret;
6399
6400         if (on) {
6401                 /* enable rx queues before enabling tx queues */
6402                 ret = i40e_dev_switch_rx_queues(pf, on);
6403                 if (ret) {
6404                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6405                         return ret;
6406                 }
6407                 ret = i40e_dev_switch_tx_queues(pf, on);
6408         } else {
6409                 /* Stop tx queues before stopping rx queues */
6410                 ret = i40e_dev_switch_tx_queues(pf, on);
6411                 if (ret) {
6412                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6413                         return ret;
6414                 }
6415                 ret = i40e_dev_switch_rx_queues(pf, on);
6416         }
6417
6418         return ret;
6419 }
6420
6421 /* Initialize VSI for TX */
6422 static int
6423 i40e_dev_tx_init(struct i40e_pf *pf)
6424 {
6425         struct rte_eth_dev_data *data = pf->dev_data;
6426         uint16_t i;
6427         uint32_t ret = I40E_SUCCESS;
6428         struct i40e_tx_queue *txq;
6429
6430         for (i = 0; i < data->nb_tx_queues; i++) {
6431                 txq = data->tx_queues[i];
6432                 if (!txq || !txq->q_set)
6433                         continue;
6434                 ret = i40e_tx_queue_init(txq);
6435                 if (ret != I40E_SUCCESS)
6436                         break;
6437         }
6438         if (ret == I40E_SUCCESS)
6439                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6440                                      ->eth_dev);
6441
6442         return ret;
6443 }
6444
6445 /* Initialize VSI for RX */
6446 static int
6447 i40e_dev_rx_init(struct i40e_pf *pf)
6448 {
6449         struct rte_eth_dev_data *data = pf->dev_data;
6450         int ret = I40E_SUCCESS;
6451         uint16_t i;
6452         struct i40e_rx_queue *rxq;
6453
6454         i40e_pf_config_mq_rx(pf);
6455         for (i = 0; i < data->nb_rx_queues; i++) {
6456                 rxq = data->rx_queues[i];
6457                 if (!rxq || !rxq->q_set)
6458                         continue;
6459
6460                 ret = i40e_rx_queue_init(rxq);
6461                 if (ret != I40E_SUCCESS) {
6462                         PMD_DRV_LOG(ERR,
6463                                 "Failed to do RX queue initialization");
6464                         break;
6465                 }
6466         }
6467         if (ret == I40E_SUCCESS)
6468                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6469                                      ->eth_dev);
6470
6471         return ret;
6472 }
6473
6474 static int
6475 i40e_dev_rxtx_init(struct i40e_pf *pf)
6476 {
6477         int err;
6478
6479         err = i40e_dev_tx_init(pf);
6480         if (err) {
6481                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6482                 return err;
6483         }
6484         err = i40e_dev_rx_init(pf);
6485         if (err) {
6486                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6487                 return err;
6488         }
6489
6490         return err;
6491 }
6492
6493 static int
6494 i40e_vmdq_setup(struct rte_eth_dev *dev)
6495 {
6496         struct rte_eth_conf *conf = &dev->data->dev_conf;
6497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6498         int i, err, conf_vsis, j, loop;
6499         struct i40e_vsi *vsi;
6500         struct i40e_vmdq_info *vmdq_info;
6501         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6502         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6503
6504         /*
6505          * Disable interrupt to avoid message from VF. Furthermore, it will
6506          * avoid race condition in VSI creation/destroy.
6507          */
6508         i40e_pf_disable_irq0(hw);
6509
6510         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6511                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6512                 return -ENOTSUP;
6513         }
6514
6515         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6516         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6517                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6518                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6519                         pf->max_nb_vmdq_vsi);
6520                 return -ENOTSUP;
6521         }
6522
6523         if (pf->vmdq != NULL) {
6524                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6525                 return 0;
6526         }
6527
6528         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6529                                 sizeof(*vmdq_info) * conf_vsis, 0);
6530
6531         if (pf->vmdq == NULL) {
6532                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6533                 return -ENOMEM;
6534         }
6535
6536         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6537
6538         /* Create VMDQ VSI */
6539         for (i = 0; i < conf_vsis; i++) {
6540                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6541                                 vmdq_conf->enable_loop_back);
6542                 if (vsi == NULL) {
6543                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6544                         err = -1;
6545                         goto err_vsi_setup;
6546                 }
6547                 vmdq_info = &pf->vmdq[i];
6548                 vmdq_info->pf = pf;
6549                 vmdq_info->vsi = vsi;
6550         }
6551         pf->nb_cfg_vmdq_vsi = conf_vsis;
6552
6553         /* Configure Vlan */
6554         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6555         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6556                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6557                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6558                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6559                                         vmdq_conf->pool_map[i].vlan_id, j);
6560
6561                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6562                                                 vmdq_conf->pool_map[i].vlan_id);
6563                                 if (err) {
6564                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6565                                         err = -1;
6566                                         goto err_vsi_setup;
6567                                 }
6568                         }
6569                 }
6570         }
6571
6572         i40e_pf_enable_irq0(hw);
6573
6574         return 0;
6575
6576 err_vsi_setup:
6577         for (i = 0; i < conf_vsis; i++)
6578                 if (pf->vmdq[i].vsi == NULL)
6579                         break;
6580                 else
6581                         i40e_vsi_release(pf->vmdq[i].vsi);
6582
6583         rte_free(pf->vmdq);
6584         pf->vmdq = NULL;
6585         i40e_pf_enable_irq0(hw);
6586         return err;
6587 }
6588
6589 static void
6590 i40e_stat_update_32(struct i40e_hw *hw,
6591                    uint32_t reg,
6592                    bool offset_loaded,
6593                    uint64_t *offset,
6594                    uint64_t *stat)
6595 {
6596         uint64_t new_data;
6597
6598         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6599         if (!offset_loaded)
6600                 *offset = new_data;
6601
6602         if (new_data >= *offset)
6603                 *stat = (uint64_t)(new_data - *offset);
6604         else
6605                 *stat = (uint64_t)((new_data +
6606                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6607 }
6608
6609 static void
6610 i40e_stat_update_48(struct i40e_hw *hw,
6611                    uint32_t hireg,
6612                    uint32_t loreg,
6613                    bool offset_loaded,
6614                    uint64_t *offset,
6615                    uint64_t *stat)
6616 {
6617         uint64_t new_data;
6618
6619         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6620         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6621                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6622
6623         if (!offset_loaded)
6624                 *offset = new_data;
6625
6626         if (new_data >= *offset)
6627                 *stat = new_data - *offset;
6628         else
6629                 *stat = (uint64_t)((new_data +
6630                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6631
6632         *stat &= I40E_48_BIT_MASK;
6633 }
6634
6635 /* Disable IRQ0 */
6636 void
6637 i40e_pf_disable_irq0(struct i40e_hw *hw)
6638 {
6639         /* Disable all interrupt types */
6640         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6641                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6642         I40E_WRITE_FLUSH(hw);
6643 }
6644
6645 /* Enable IRQ0 */
6646 void
6647 i40e_pf_enable_irq0(struct i40e_hw *hw)
6648 {
6649         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6650                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6651                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6652                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6653         I40E_WRITE_FLUSH(hw);
6654 }
6655
6656 static void
6657 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6658 {
6659         /* read pending request and disable first */
6660         i40e_pf_disable_irq0(hw);
6661         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6662         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6663                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6664
6665         if (no_queue)
6666                 /* Link no queues with irq0 */
6667                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6668                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6669 }
6670
6671 static void
6672 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6673 {
6674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6676         int i;
6677         uint16_t abs_vf_id;
6678         uint32_t index, offset, val;
6679
6680         if (!pf->vfs)
6681                 return;
6682         /**
6683          * Try to find which VF trigger a reset, use absolute VF id to access
6684          * since the reg is global register.
6685          */
6686         for (i = 0; i < pf->vf_num; i++) {
6687                 abs_vf_id = hw->func_caps.vf_base_id + i;
6688                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6689                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6690                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6691                 /* VFR event occurred */
6692                 if (val & (0x1 << offset)) {
6693                         int ret;
6694
6695                         /* Clear the event first */
6696                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6697                                                         (0x1 << offset));
6698                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6699                         /**
6700                          * Only notify a VF reset event occurred,
6701                          * don't trigger another SW reset
6702                          */
6703                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6704                         if (ret != I40E_SUCCESS)
6705                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6706                 }
6707         }
6708 }
6709
6710 static void
6711 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6712 {
6713         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6714         int i;
6715
6716         for (i = 0; i < pf->vf_num; i++)
6717                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6718 }
6719
6720 static void
6721 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6722 {
6723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6724         struct i40e_arq_event_info info;
6725         uint16_t pending, opcode;
6726         int ret;
6727
6728         info.buf_len = I40E_AQ_BUF_SZ;
6729         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6730         if (!info.msg_buf) {
6731                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6732                 return;
6733         }
6734
6735         pending = 1;
6736         while (pending) {
6737                 ret = i40e_clean_arq_element(hw, &info, &pending);
6738
6739                 if (ret != I40E_SUCCESS) {
6740                         PMD_DRV_LOG(INFO,
6741                                 "Failed to read msg from AdminQ, aq_err: %u",
6742                                 hw->aq.asq_last_status);
6743                         break;
6744                 }
6745                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6746
6747                 switch (opcode) {
6748                 case i40e_aqc_opc_send_msg_to_pf:
6749                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6750                         i40e_pf_host_handle_vf_msg(dev,
6751                                         rte_le_to_cpu_16(info.desc.retval),
6752                                         rte_le_to_cpu_32(info.desc.cookie_high),
6753                                         rte_le_to_cpu_32(info.desc.cookie_low),
6754                                         info.msg_buf,
6755                                         info.msg_len);
6756                         break;
6757                 case i40e_aqc_opc_get_link_status:
6758                         ret = i40e_dev_link_update(dev, 0);
6759                         if (!ret)
6760                                 _rte_eth_dev_callback_process(dev,
6761                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6762                         break;
6763                 default:
6764                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6765                                     opcode);
6766                         break;
6767                 }
6768         }
6769         rte_free(info.msg_buf);
6770 }
6771
6772 static void
6773 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6774 {
6775 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6776 #define I40E_MDD_CLEAR16 0xFFFF
6777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6779         bool mdd_detected = false;
6780         struct i40e_pf_vf *vf;
6781         uint32_t reg;
6782         int i;
6783
6784         /* find what triggered the MDD event */
6785         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6786         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6787                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6788                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6789                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6790                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6791                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6792                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6793                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6794                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6795                                         hw->func_caps.base_queue;
6796                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6797                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6798                                 event, queue, pf_num, vf_num, dev->data->name);
6799                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6800                 mdd_detected = true;
6801         }
6802         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6803         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6804                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6805                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6806                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6807                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6808                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6809                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6810                                         hw->func_caps.base_queue;
6811
6812                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6813                                 "queue %d of function 0x%02x device %s\n",
6814                                         event, queue, func, dev->data->name);
6815                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6816                 mdd_detected = true;
6817         }
6818
6819         if (mdd_detected) {
6820                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6821                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6822                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6823                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6824                 }
6825                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6826                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6827                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6828                                         I40E_MDD_CLEAR16);
6829                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6830                 }
6831         }
6832
6833         /* see if one of the VFs needs its hand slapped */
6834         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6835                 vf = &pf->vfs[i];
6836                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6837                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6838                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6839                                         I40E_MDD_CLEAR16);
6840                         vf->num_mdd_events++;
6841                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6842                                         PRIu64 "times\n",
6843                                         i, vf->num_mdd_events);
6844                 }
6845
6846                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6847                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6848                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6849                                         I40E_MDD_CLEAR16);
6850                         vf->num_mdd_events++;
6851                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6852                                         PRIu64 "times\n",
6853                                         i, vf->num_mdd_events);
6854                 }
6855         }
6856 }
6857
6858 /**
6859  * Interrupt handler triggered by NIC  for handling
6860  * specific interrupt.
6861  *
6862  * @param handle
6863  *  Pointer to interrupt handle.
6864  * @param param
6865  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6866  *
6867  * @return
6868  *  void
6869  */
6870 static void
6871 i40e_dev_interrupt_handler(void *param)
6872 {
6873         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6875         uint32_t icr0;
6876
6877         /* Disable interrupt */
6878         i40e_pf_disable_irq0(hw);
6879
6880         /* read out interrupt causes */
6881         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6882
6883         /* No interrupt event indicated */
6884         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6885                 PMD_DRV_LOG(INFO, "No interrupt event");
6886                 goto done;
6887         }
6888         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6889                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6890         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6891                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6892                 i40e_handle_mdd_event(dev);
6893         }
6894         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6895                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6896         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6897                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6898         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6899                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6900         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6901                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6902         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6903                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6904
6905         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6906                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6907                 i40e_dev_handle_vfr_event(dev);
6908         }
6909         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6910                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6911                 i40e_dev_handle_aq_msg(dev);
6912         }
6913
6914 done:
6915         /* Enable interrupt */
6916         i40e_pf_enable_irq0(hw);
6917 }
6918
6919 static void
6920 i40e_dev_alarm_handler(void *param)
6921 {
6922         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6924         uint32_t icr0;
6925
6926         /* Disable interrupt */
6927         i40e_pf_disable_irq0(hw);
6928
6929         /* read out interrupt causes */
6930         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6931
6932         /* No interrupt event indicated */
6933         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6934                 goto done;
6935         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6936                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6937         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6938                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6939                 i40e_handle_mdd_event(dev);
6940         }
6941         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6942                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6943         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6944                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6945         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6946                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6947         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6948                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6949         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6950                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6951
6952         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6953                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6954                 i40e_dev_handle_vfr_event(dev);
6955         }
6956         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6957                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6958                 i40e_dev_handle_aq_msg(dev);
6959         }
6960
6961 done:
6962         /* Enable interrupt */
6963         i40e_pf_enable_irq0(hw);
6964         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6965                           i40e_dev_alarm_handler, dev);
6966 }
6967
6968 int
6969 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6970                          struct i40e_macvlan_filter *filter,
6971                          int total)
6972 {
6973         int ele_num, ele_buff_size;
6974         int num, actual_num, i;
6975         uint16_t flags;
6976         int ret = I40E_SUCCESS;
6977         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6978         struct i40e_aqc_add_macvlan_element_data *req_list;
6979
6980         if (filter == NULL  || total == 0)
6981                 return I40E_ERR_PARAM;
6982         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6983         ele_buff_size = hw->aq.asq_buf_size;
6984
6985         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6986         if (req_list == NULL) {
6987                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6988                 return I40E_ERR_NO_MEMORY;
6989         }
6990
6991         num = 0;
6992         do {
6993                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6994                 memset(req_list, 0, ele_buff_size);
6995
6996                 for (i = 0; i < actual_num; i++) {
6997                         rte_memcpy(req_list[i].mac_addr,
6998                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6999                         req_list[i].vlan_tag =
7000                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7001
7002                         switch (filter[num + i].filter_type) {
7003                         case RTE_MAC_PERFECT_MATCH:
7004                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7005                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7006                                 break;
7007                         case RTE_MACVLAN_PERFECT_MATCH:
7008                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7009                                 break;
7010                         case RTE_MAC_HASH_MATCH:
7011                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7012                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7013                                 break;
7014                         case RTE_MACVLAN_HASH_MATCH:
7015                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7016                                 break;
7017                         default:
7018                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7019                                 ret = I40E_ERR_PARAM;
7020                                 goto DONE;
7021                         }
7022
7023                         req_list[i].queue_number = 0;
7024
7025                         req_list[i].flags = rte_cpu_to_le_16(flags);
7026                 }
7027
7028                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7029                                                 actual_num, NULL);
7030                 if (ret != I40E_SUCCESS) {
7031                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7032                         goto DONE;
7033                 }
7034                 num += actual_num;
7035         } while (num < total);
7036
7037 DONE:
7038         rte_free(req_list);
7039         return ret;
7040 }
7041
7042 int
7043 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7044                             struct i40e_macvlan_filter *filter,
7045                             int total)
7046 {
7047         int ele_num, ele_buff_size;
7048         int num, actual_num, i;
7049         uint16_t flags;
7050         int ret = I40E_SUCCESS;
7051         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7052         struct i40e_aqc_remove_macvlan_element_data *req_list;
7053
7054         if (filter == NULL  || total == 0)
7055                 return I40E_ERR_PARAM;
7056
7057         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7058         ele_buff_size = hw->aq.asq_buf_size;
7059
7060         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7061         if (req_list == NULL) {
7062                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7063                 return I40E_ERR_NO_MEMORY;
7064         }
7065
7066         num = 0;
7067         do {
7068                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7069                 memset(req_list, 0, ele_buff_size);
7070
7071                 for (i = 0; i < actual_num; i++) {
7072                         rte_memcpy(req_list[i].mac_addr,
7073                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7074                         req_list[i].vlan_tag =
7075                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7076
7077                         switch (filter[num + i].filter_type) {
7078                         case RTE_MAC_PERFECT_MATCH:
7079                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7080                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7081                                 break;
7082                         case RTE_MACVLAN_PERFECT_MATCH:
7083                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7084                                 break;
7085                         case RTE_MAC_HASH_MATCH:
7086                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7087                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7088                                 break;
7089                         case RTE_MACVLAN_HASH_MATCH:
7090                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7091                                 break;
7092                         default:
7093                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7094                                 ret = I40E_ERR_PARAM;
7095                                 goto DONE;
7096                         }
7097                         req_list[i].flags = rte_cpu_to_le_16(flags);
7098                 }
7099
7100                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7101                                                 actual_num, NULL);
7102                 if (ret != I40E_SUCCESS) {
7103                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7104                         goto DONE;
7105                 }
7106                 num += actual_num;
7107         } while (num < total);
7108
7109 DONE:
7110         rte_free(req_list);
7111         return ret;
7112 }
7113
7114 /* Find out specific MAC filter */
7115 static struct i40e_mac_filter *
7116 i40e_find_mac_filter(struct i40e_vsi *vsi,
7117                          struct rte_ether_addr *macaddr)
7118 {
7119         struct i40e_mac_filter *f;
7120
7121         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7122                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7123                         return f;
7124         }
7125
7126         return NULL;
7127 }
7128
7129 static bool
7130 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7131                          uint16_t vlan_id)
7132 {
7133         uint32_t vid_idx, vid_bit;
7134
7135         if (vlan_id > ETH_VLAN_ID_MAX)
7136                 return 0;
7137
7138         vid_idx = I40E_VFTA_IDX(vlan_id);
7139         vid_bit = I40E_VFTA_BIT(vlan_id);
7140
7141         if (vsi->vfta[vid_idx] & vid_bit)
7142                 return 1;
7143         else
7144                 return 0;
7145 }
7146
7147 static void
7148 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7149                        uint16_t vlan_id, bool on)
7150 {
7151         uint32_t vid_idx, vid_bit;
7152
7153         vid_idx = I40E_VFTA_IDX(vlan_id);
7154         vid_bit = I40E_VFTA_BIT(vlan_id);
7155
7156         if (on)
7157                 vsi->vfta[vid_idx] |= vid_bit;
7158         else
7159                 vsi->vfta[vid_idx] &= ~vid_bit;
7160 }
7161
7162 void
7163 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7164                      uint16_t vlan_id, bool on)
7165 {
7166         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7167         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7168         int ret;
7169
7170         if (vlan_id > ETH_VLAN_ID_MAX)
7171                 return;
7172
7173         i40e_store_vlan_filter(vsi, vlan_id, on);
7174
7175         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7176                 return;
7177
7178         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7179
7180         if (on) {
7181                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7182                                        &vlan_data, 1, NULL);
7183                 if (ret != I40E_SUCCESS)
7184                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7185         } else {
7186                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7187                                           &vlan_data, 1, NULL);
7188                 if (ret != I40E_SUCCESS)
7189                         PMD_DRV_LOG(ERR,
7190                                     "Failed to remove vlan filter");
7191         }
7192 }
7193
7194 /**
7195  * Find all vlan options for specific mac addr,
7196  * return with actual vlan found.
7197  */
7198 int
7199 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7200                            struct i40e_macvlan_filter *mv_f,
7201                            int num, struct rte_ether_addr *addr)
7202 {
7203         int i;
7204         uint32_t j, k;
7205
7206         /**
7207          * Not to use i40e_find_vlan_filter to decrease the loop time,
7208          * although the code looks complex.
7209           */
7210         if (num < vsi->vlan_num)
7211                 return I40E_ERR_PARAM;
7212
7213         i = 0;
7214         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7215                 if (vsi->vfta[j]) {
7216                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7217                                 if (vsi->vfta[j] & (1 << k)) {
7218                                         if (i > num - 1) {
7219                                                 PMD_DRV_LOG(ERR,
7220                                                         "vlan number doesn't match");
7221                                                 return I40E_ERR_PARAM;
7222                                         }
7223                                         rte_memcpy(&mv_f[i].macaddr,
7224                                                         addr, ETH_ADDR_LEN);
7225                                         mv_f[i].vlan_id =
7226                                                 j * I40E_UINT32_BIT_SIZE + k;
7227                                         i++;
7228                                 }
7229                         }
7230                 }
7231         }
7232         return I40E_SUCCESS;
7233 }
7234
7235 static inline int
7236 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7237                            struct i40e_macvlan_filter *mv_f,
7238                            int num,
7239                            uint16_t vlan)
7240 {
7241         int i = 0;
7242         struct i40e_mac_filter *f;
7243
7244         if (num < vsi->mac_num)
7245                 return I40E_ERR_PARAM;
7246
7247         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7248                 if (i > num - 1) {
7249                         PMD_DRV_LOG(ERR, "buffer number not match");
7250                         return I40E_ERR_PARAM;
7251                 }
7252                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7253                                 ETH_ADDR_LEN);
7254                 mv_f[i].vlan_id = vlan;
7255                 mv_f[i].filter_type = f->mac_info.filter_type;
7256                 i++;
7257         }
7258
7259         return I40E_SUCCESS;
7260 }
7261
7262 static int
7263 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7264 {
7265         int i, j, num;
7266         struct i40e_mac_filter *f;
7267         struct i40e_macvlan_filter *mv_f;
7268         int ret = I40E_SUCCESS;
7269
7270         if (vsi == NULL || vsi->mac_num == 0)
7271                 return I40E_ERR_PARAM;
7272
7273         /* Case that no vlan is set */
7274         if (vsi->vlan_num == 0)
7275                 num = vsi->mac_num;
7276         else
7277                 num = vsi->mac_num * vsi->vlan_num;
7278
7279         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7280         if (mv_f == NULL) {
7281                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7282                 return I40E_ERR_NO_MEMORY;
7283         }
7284
7285         i = 0;
7286         if (vsi->vlan_num == 0) {
7287                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7288                         rte_memcpy(&mv_f[i].macaddr,
7289                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7290                         mv_f[i].filter_type = f->mac_info.filter_type;
7291                         mv_f[i].vlan_id = 0;
7292                         i++;
7293                 }
7294         } else {
7295                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7296                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7297                                         vsi->vlan_num, &f->mac_info.mac_addr);
7298                         if (ret != I40E_SUCCESS)
7299                                 goto DONE;
7300                         for (j = i; j < i + vsi->vlan_num; j++)
7301                                 mv_f[j].filter_type = f->mac_info.filter_type;
7302                         i += vsi->vlan_num;
7303                 }
7304         }
7305
7306         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7307 DONE:
7308         rte_free(mv_f);
7309
7310         return ret;
7311 }
7312
7313 int
7314 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7315 {
7316         struct i40e_macvlan_filter *mv_f;
7317         int mac_num;
7318         int ret = I40E_SUCCESS;
7319
7320         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7321                 return I40E_ERR_PARAM;
7322
7323         /* If it's already set, just return */
7324         if (i40e_find_vlan_filter(vsi,vlan))
7325                 return I40E_SUCCESS;
7326
7327         mac_num = vsi->mac_num;
7328
7329         if (mac_num == 0) {
7330                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7331                 return I40E_ERR_PARAM;
7332         }
7333
7334         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7335
7336         if (mv_f == NULL) {
7337                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7338                 return I40E_ERR_NO_MEMORY;
7339         }
7340
7341         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7342
7343         if (ret != I40E_SUCCESS)
7344                 goto DONE;
7345
7346         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7347
7348         if (ret != I40E_SUCCESS)
7349                 goto DONE;
7350
7351         i40e_set_vlan_filter(vsi, vlan, 1);
7352
7353         vsi->vlan_num++;
7354         ret = I40E_SUCCESS;
7355 DONE:
7356         rte_free(mv_f);
7357         return ret;
7358 }
7359
7360 int
7361 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7362 {
7363         struct i40e_macvlan_filter *mv_f;
7364         int mac_num;
7365         int ret = I40E_SUCCESS;
7366
7367         /**
7368          * Vlan 0 is the generic filter for untagged packets
7369          * and can't be removed.
7370          */
7371         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7372                 return I40E_ERR_PARAM;
7373
7374         /* If can't find it, just return */
7375         if (!i40e_find_vlan_filter(vsi, vlan))
7376                 return I40E_ERR_PARAM;
7377
7378         mac_num = vsi->mac_num;
7379
7380         if (mac_num == 0) {
7381                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7382                 return I40E_ERR_PARAM;
7383         }
7384
7385         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7386
7387         if (mv_f == NULL) {
7388                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7389                 return I40E_ERR_NO_MEMORY;
7390         }
7391
7392         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7393
7394         if (ret != I40E_SUCCESS)
7395                 goto DONE;
7396
7397         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7398
7399         if (ret != I40E_SUCCESS)
7400                 goto DONE;
7401
7402         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7403         if (vsi->vlan_num == 1) {
7404                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7405                 if (ret != I40E_SUCCESS)
7406                         goto DONE;
7407
7408                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7409                 if (ret != I40E_SUCCESS)
7410                         goto DONE;
7411         }
7412
7413         i40e_set_vlan_filter(vsi, vlan, 0);
7414
7415         vsi->vlan_num--;
7416         ret = I40E_SUCCESS;
7417 DONE:
7418         rte_free(mv_f);
7419         return ret;
7420 }
7421
7422 int
7423 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7424 {
7425         struct i40e_mac_filter *f;
7426         struct i40e_macvlan_filter *mv_f;
7427         int i, vlan_num = 0;
7428         int ret = I40E_SUCCESS;
7429
7430         /* If it's add and we've config it, return */
7431         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7432         if (f != NULL)
7433                 return I40E_SUCCESS;
7434         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7435                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7436
7437                 /**
7438                  * If vlan_num is 0, that's the first time to add mac,
7439                  * set mask for vlan_id 0.
7440                  */
7441                 if (vsi->vlan_num == 0) {
7442                         i40e_set_vlan_filter(vsi, 0, 1);
7443                         vsi->vlan_num = 1;
7444                 }
7445                 vlan_num = vsi->vlan_num;
7446         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7447                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7448                 vlan_num = 1;
7449
7450         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7451         if (mv_f == NULL) {
7452                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7453                 return I40E_ERR_NO_MEMORY;
7454         }
7455
7456         for (i = 0; i < vlan_num; i++) {
7457                 mv_f[i].filter_type = mac_filter->filter_type;
7458                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7459                                 ETH_ADDR_LEN);
7460         }
7461
7462         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7463                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7464                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7465                                         &mac_filter->mac_addr);
7466                 if (ret != I40E_SUCCESS)
7467                         goto DONE;
7468         }
7469
7470         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7471         if (ret != I40E_SUCCESS)
7472                 goto DONE;
7473
7474         /* Add the mac addr into mac list */
7475         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7476         if (f == NULL) {
7477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7478                 ret = I40E_ERR_NO_MEMORY;
7479                 goto DONE;
7480         }
7481         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7482                         ETH_ADDR_LEN);
7483         f->mac_info.filter_type = mac_filter->filter_type;
7484         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7485         vsi->mac_num++;
7486
7487         ret = I40E_SUCCESS;
7488 DONE:
7489         rte_free(mv_f);
7490
7491         return ret;
7492 }
7493
7494 int
7495 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7496 {
7497         struct i40e_mac_filter *f;
7498         struct i40e_macvlan_filter *mv_f;
7499         int i, vlan_num;
7500         enum rte_mac_filter_type filter_type;
7501         int ret = I40E_SUCCESS;
7502
7503         /* Can't find it, return an error */
7504         f = i40e_find_mac_filter(vsi, addr);
7505         if (f == NULL)
7506                 return I40E_ERR_PARAM;
7507
7508         vlan_num = vsi->vlan_num;
7509         filter_type = f->mac_info.filter_type;
7510         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7511                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7512                 if (vlan_num == 0) {
7513                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7514                         return I40E_ERR_PARAM;
7515                 }
7516         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7517                         filter_type == RTE_MAC_HASH_MATCH)
7518                 vlan_num = 1;
7519
7520         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7521         if (mv_f == NULL) {
7522                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7523                 return I40E_ERR_NO_MEMORY;
7524         }
7525
7526         for (i = 0; i < vlan_num; i++) {
7527                 mv_f[i].filter_type = filter_type;
7528                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7529                                 ETH_ADDR_LEN);
7530         }
7531         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7532                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7533                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7534                 if (ret != I40E_SUCCESS)
7535                         goto DONE;
7536         }
7537
7538         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7539         if (ret != I40E_SUCCESS)
7540                 goto DONE;
7541
7542         /* Remove the mac addr into mac list */
7543         TAILQ_REMOVE(&vsi->mac_list, f, next);
7544         rte_free(f);
7545         vsi->mac_num--;
7546
7547         ret = I40E_SUCCESS;
7548 DONE:
7549         rte_free(mv_f);
7550         return ret;
7551 }
7552
7553 /* Configure hash enable flags for RSS */
7554 uint64_t
7555 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7556 {
7557         uint64_t hena = 0;
7558         int i;
7559
7560         if (!flags)
7561                 return hena;
7562
7563         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7564                 if (flags & (1ULL << i))
7565                         hena |= adapter->pctypes_tbl[i];
7566         }
7567
7568         return hena;
7569 }
7570
7571 /* Parse the hash enable flags */
7572 uint64_t
7573 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7574 {
7575         uint64_t rss_hf = 0;
7576
7577         if (!flags)
7578                 return rss_hf;
7579         int i;
7580
7581         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7582                 if (flags & adapter->pctypes_tbl[i])
7583                         rss_hf |= (1ULL << i);
7584         }
7585         return rss_hf;
7586 }
7587
7588 /* Disable RSS */
7589 static void
7590 i40e_pf_disable_rss(struct i40e_pf *pf)
7591 {
7592         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7593
7594         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7595         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7596         I40E_WRITE_FLUSH(hw);
7597 }
7598
7599 int
7600 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7601 {
7602         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7604         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7605                            I40E_VFQF_HKEY_MAX_INDEX :
7606                            I40E_PFQF_HKEY_MAX_INDEX;
7607         int ret = 0;
7608
7609         if (!key || key_len == 0) {
7610                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7611                 return 0;
7612         } else if (key_len != (key_idx + 1) *
7613                 sizeof(uint32_t)) {
7614                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7615                 return -EINVAL;
7616         }
7617
7618         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7619                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7620                         (struct i40e_aqc_get_set_rss_key_data *)key;
7621
7622                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7623                 if (ret)
7624                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7625         } else {
7626                 uint32_t *hash_key = (uint32_t *)key;
7627                 uint16_t i;
7628
7629                 if (vsi->type == I40E_VSI_SRIOV) {
7630                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7631                                 I40E_WRITE_REG(
7632                                         hw,
7633                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7634                                         hash_key[i]);
7635
7636                 } else {
7637                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7638                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7639                                                hash_key[i]);
7640                 }
7641                 I40E_WRITE_FLUSH(hw);
7642         }
7643
7644         return ret;
7645 }
7646
7647 static int
7648 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7649 {
7650         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7651         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7652         uint32_t reg;
7653         int ret;
7654
7655         if (!key || !key_len)
7656                 return 0;
7657
7658         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7659                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7660                         (struct i40e_aqc_get_set_rss_key_data *)key);
7661                 if (ret) {
7662                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7663                         return ret;
7664                 }
7665         } else {
7666                 uint32_t *key_dw = (uint32_t *)key;
7667                 uint16_t i;
7668
7669                 if (vsi->type == I40E_VSI_SRIOV) {
7670                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7671                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7672                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7673                         }
7674                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7675                                    sizeof(uint32_t);
7676                 } else {
7677                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7678                                 reg = I40E_PFQF_HKEY(i);
7679                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7680                         }
7681                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7682                                    sizeof(uint32_t);
7683                 }
7684         }
7685         return 0;
7686 }
7687
7688 static int
7689 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7690 {
7691         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7692         uint64_t hena;
7693         int ret;
7694
7695         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7696                                rss_conf->rss_key_len);
7697         if (ret)
7698                 return ret;
7699
7700         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7701         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7702         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7703         I40E_WRITE_FLUSH(hw);
7704
7705         return 0;
7706 }
7707
7708 static int
7709 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7710                          struct rte_eth_rss_conf *rss_conf)
7711 {
7712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7714         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7715         uint64_t hena;
7716
7717         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7718         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7719
7720         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7721                 if (rss_hf != 0) /* Enable RSS */
7722                         return -EINVAL;
7723                 return 0; /* Nothing to do */
7724         }
7725         /* RSS enabled */
7726         if (rss_hf == 0) /* Disable RSS */
7727                 return -EINVAL;
7728
7729         return i40e_hw_rss_hash_set(pf, rss_conf);
7730 }
7731
7732 static int
7733 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7734                            struct rte_eth_rss_conf *rss_conf)
7735 {
7736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7738         uint64_t hena;
7739         int ret;
7740
7741         if (!rss_conf)
7742                 return -EINVAL;
7743
7744         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7745                          &rss_conf->rss_key_len);
7746         if (ret)
7747                 return ret;
7748
7749         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7750         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7751         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7752
7753         return 0;
7754 }
7755
7756 static int
7757 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7758 {
7759         switch (filter_type) {
7760         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7761                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7762                 break;
7763         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7764                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7765                 break;
7766         case RTE_TUNNEL_FILTER_IMAC_TENID:
7767                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7768                 break;
7769         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7770                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7771                 break;
7772         case ETH_TUNNEL_FILTER_IMAC:
7773                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7774                 break;
7775         case ETH_TUNNEL_FILTER_OIP:
7776                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7777                 break;
7778         case ETH_TUNNEL_FILTER_IIP:
7779                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7780                 break;
7781         default:
7782                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7783                 return -EINVAL;
7784         }
7785
7786         return 0;
7787 }
7788
7789 /* Convert tunnel filter structure */
7790 static int
7791 i40e_tunnel_filter_convert(
7792         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7793         struct i40e_tunnel_filter *tunnel_filter)
7794 {
7795         rte_ether_addr_copy((struct rte_ether_addr *)
7796                         &cld_filter->element.outer_mac,
7797                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7798         rte_ether_addr_copy((struct rte_ether_addr *)
7799                         &cld_filter->element.inner_mac,
7800                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7801         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7802         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7803              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7804             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7805                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7806         else
7807                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7808         tunnel_filter->input.flags = cld_filter->element.flags;
7809         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7810         tunnel_filter->queue = cld_filter->element.queue_number;
7811         rte_memcpy(tunnel_filter->input.general_fields,
7812                    cld_filter->general_fields,
7813                    sizeof(cld_filter->general_fields));
7814
7815         return 0;
7816 }
7817
7818 /* Check if there exists the tunnel filter */
7819 struct i40e_tunnel_filter *
7820 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7821                              const struct i40e_tunnel_filter_input *input)
7822 {
7823         int ret;
7824
7825         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7826         if (ret < 0)
7827                 return NULL;
7828
7829         return tunnel_rule->hash_map[ret];
7830 }
7831
7832 /* Add a tunnel filter into the SW list */
7833 static int
7834 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7835                              struct i40e_tunnel_filter *tunnel_filter)
7836 {
7837         struct i40e_tunnel_rule *rule = &pf->tunnel;
7838         int ret;
7839
7840         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7841         if (ret < 0) {
7842                 PMD_DRV_LOG(ERR,
7843                             "Failed to insert tunnel filter to hash table %d!",
7844                             ret);
7845                 return ret;
7846         }
7847         rule->hash_map[ret] = tunnel_filter;
7848
7849         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7850
7851         return 0;
7852 }
7853
7854 /* Delete a tunnel filter from the SW list */
7855 int
7856 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7857                           struct i40e_tunnel_filter_input *input)
7858 {
7859         struct i40e_tunnel_rule *rule = &pf->tunnel;
7860         struct i40e_tunnel_filter *tunnel_filter;
7861         int ret;
7862
7863         ret = rte_hash_del_key(rule->hash_table, input);
7864         if (ret < 0) {
7865                 PMD_DRV_LOG(ERR,
7866                             "Failed to delete tunnel filter to hash table %d!",
7867                             ret);
7868                 return ret;
7869         }
7870         tunnel_filter = rule->hash_map[ret];
7871         rule->hash_map[ret] = NULL;
7872
7873         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7874         rte_free(tunnel_filter);
7875
7876         return 0;
7877 }
7878
7879 int
7880 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7881                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7882                         uint8_t add)
7883 {
7884         uint16_t ip_type;
7885         uint32_t ipv4_addr, ipv4_addr_le;
7886         uint8_t i, tun_type = 0;
7887         /* internal varialbe to convert ipv6 byte order */
7888         uint32_t convert_ipv6[4];
7889         int val, ret = 0;
7890         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7891         struct i40e_vsi *vsi = pf->main_vsi;
7892         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7893         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7894         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7895         struct i40e_tunnel_filter *tunnel, *node;
7896         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7897
7898         cld_filter = rte_zmalloc("tunnel_filter",
7899                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7900         0);
7901
7902         if (NULL == cld_filter) {
7903                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7904                 return -ENOMEM;
7905         }
7906         pfilter = cld_filter;
7907
7908         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7909                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7910         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7911                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7912
7913         pfilter->element.inner_vlan =
7914                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7915         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7916                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7917                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7918                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7919                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7920                                 &ipv4_addr_le,
7921                                 sizeof(pfilter->element.ipaddr.v4.data));
7922         } else {
7923                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7924                 for (i = 0; i < 4; i++) {
7925                         convert_ipv6[i] =
7926                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7927                 }
7928                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7929                            &convert_ipv6,
7930                            sizeof(pfilter->element.ipaddr.v6.data));
7931         }
7932
7933         /* check tunneled type */
7934         switch (tunnel_filter->tunnel_type) {
7935         case RTE_TUNNEL_TYPE_VXLAN:
7936                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7937                 break;
7938         case RTE_TUNNEL_TYPE_NVGRE:
7939                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7940                 break;
7941         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7942                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7943                 break;
7944         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7945                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7946                 break;
7947         default:
7948                 /* Other tunnel types is not supported. */
7949                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7950                 rte_free(cld_filter);
7951                 return -EINVAL;
7952         }
7953
7954         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7955                                        &pfilter->element.flags);
7956         if (val < 0) {
7957                 rte_free(cld_filter);
7958                 return -EINVAL;
7959         }
7960
7961         pfilter->element.flags |= rte_cpu_to_le_16(
7962                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7963                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7964         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7965         pfilter->element.queue_number =
7966                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7967
7968         /* Check if there is the filter in SW list */
7969         memset(&check_filter, 0, sizeof(check_filter));
7970         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7971         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7972         if (add && node) {
7973                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7974                 rte_free(cld_filter);
7975                 return -EINVAL;
7976         }
7977
7978         if (!add && !node) {
7979                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7980                 rte_free(cld_filter);
7981                 return -EINVAL;
7982         }
7983
7984         if (add) {
7985                 ret = i40e_aq_add_cloud_filters(hw,
7986                                         vsi->seid, &cld_filter->element, 1);
7987                 if (ret < 0) {
7988                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7989                         rte_free(cld_filter);
7990                         return -ENOTSUP;
7991                 }
7992                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7993                 if (tunnel == NULL) {
7994                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7995                         rte_free(cld_filter);
7996                         return -ENOMEM;
7997                 }
7998
7999                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8000                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8001                 if (ret < 0)
8002                         rte_free(tunnel);
8003         } else {
8004                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8005                                                    &cld_filter->element, 1);
8006                 if (ret < 0) {
8007                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8008                         rte_free(cld_filter);
8009                         return -ENOTSUP;
8010                 }
8011                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8012         }
8013
8014         rte_free(cld_filter);
8015         return ret;
8016 }
8017
8018 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8019 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8020 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8021 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8022 #define I40E_TR_GRE_KEY_MASK                    0x400
8023 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8024 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8025
8026 static enum
8027 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8028 {
8029         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8030         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8031         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8032         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8033         enum i40e_status_code status = I40E_SUCCESS;
8034
8035         if (pf->support_multi_driver) {
8036                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8037                 return I40E_NOT_SUPPORTED;
8038         }
8039
8040         memset(&filter_replace, 0,
8041                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8042         memset(&filter_replace_buf, 0,
8043                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8044
8045         /* create L1 filter */
8046         filter_replace.old_filter_type =
8047                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8048         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8049         filter_replace.tr_bit = 0;
8050
8051         /* Prepare the buffer, 3 entries */
8052         filter_replace_buf.data[0] =
8053                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8054         filter_replace_buf.data[0] |=
8055                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8056         filter_replace_buf.data[2] = 0xFF;
8057         filter_replace_buf.data[3] = 0xFF;
8058         filter_replace_buf.data[4] =
8059                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8060         filter_replace_buf.data[4] |=
8061                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8062         filter_replace_buf.data[7] = 0xF0;
8063         filter_replace_buf.data[8]
8064                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8065         filter_replace_buf.data[8] |=
8066                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8067         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8068                 I40E_TR_GENEVE_KEY_MASK |
8069                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8070         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8071                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8072                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8073
8074         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8075                                                &filter_replace_buf);
8076         if (!status && (filter_replace.old_filter_type !=
8077                         filter_replace.new_filter_type))
8078                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8079                             " original: 0x%x, new: 0x%x",
8080                             dev->device->name,
8081                             filter_replace.old_filter_type,
8082                             filter_replace.new_filter_type);
8083
8084         return status;
8085 }
8086
8087 static enum
8088 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8089 {
8090         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8091         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8092         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8093         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8094         enum i40e_status_code status = I40E_SUCCESS;
8095
8096         if (pf->support_multi_driver) {
8097                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8098                 return I40E_NOT_SUPPORTED;
8099         }
8100
8101         /* For MPLSoUDP */
8102         memset(&filter_replace, 0,
8103                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8104         memset(&filter_replace_buf, 0,
8105                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8106         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8107                 I40E_AQC_MIRROR_CLOUD_FILTER;
8108         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8109         filter_replace.new_filter_type =
8110                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8111         /* Prepare the buffer, 2 entries */
8112         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8113         filter_replace_buf.data[0] |=
8114                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8115         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8116         filter_replace_buf.data[4] |=
8117                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8118         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8119                                                &filter_replace_buf);
8120         if (status < 0)
8121                 return status;
8122         if (filter_replace.old_filter_type !=
8123             filter_replace.new_filter_type)
8124                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8125                             " original: 0x%x, new: 0x%x",
8126                             dev->device->name,
8127                             filter_replace.old_filter_type,
8128                             filter_replace.new_filter_type);
8129
8130         /* For MPLSoGRE */
8131         memset(&filter_replace, 0,
8132                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8133         memset(&filter_replace_buf, 0,
8134                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8135
8136         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8137                 I40E_AQC_MIRROR_CLOUD_FILTER;
8138         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8139         filter_replace.new_filter_type =
8140                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8141         /* Prepare the buffer, 2 entries */
8142         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8143         filter_replace_buf.data[0] |=
8144                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8145         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8146         filter_replace_buf.data[4] |=
8147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8148
8149         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8150                                                &filter_replace_buf);
8151         if (!status && (filter_replace.old_filter_type !=
8152                         filter_replace.new_filter_type))
8153                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8154                             " original: 0x%x, new: 0x%x",
8155                             dev->device->name,
8156                             filter_replace.old_filter_type,
8157                             filter_replace.new_filter_type);
8158
8159         return status;
8160 }
8161
8162 static enum i40e_status_code
8163 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8164 {
8165         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8166         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8167         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8168         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8169         enum i40e_status_code status = I40E_SUCCESS;
8170
8171         if (pf->support_multi_driver) {
8172                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8173                 return I40E_NOT_SUPPORTED;
8174         }
8175
8176         /* For GTP-C */
8177         memset(&filter_replace, 0,
8178                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8179         memset(&filter_replace_buf, 0,
8180                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8181         /* create L1 filter */
8182         filter_replace.old_filter_type =
8183                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8184         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8185         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8186                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8187         /* Prepare the buffer, 2 entries */
8188         filter_replace_buf.data[0] =
8189                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8190         filter_replace_buf.data[0] |=
8191                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8192         filter_replace_buf.data[2] = 0xFF;
8193         filter_replace_buf.data[3] = 0xFF;
8194         filter_replace_buf.data[4] =
8195                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8196         filter_replace_buf.data[4] |=
8197                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8198         filter_replace_buf.data[6] = 0xFF;
8199         filter_replace_buf.data[7] = 0xFF;
8200         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8201                                                &filter_replace_buf);
8202         if (status < 0)
8203                 return status;
8204         if (filter_replace.old_filter_type !=
8205             filter_replace.new_filter_type)
8206                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8207                             " original: 0x%x, new: 0x%x",
8208                             dev->device->name,
8209                             filter_replace.old_filter_type,
8210                             filter_replace.new_filter_type);
8211
8212         /* for GTP-U */
8213         memset(&filter_replace, 0,
8214                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8215         memset(&filter_replace_buf, 0,
8216                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8217         /* create L1 filter */
8218         filter_replace.old_filter_type =
8219                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8220         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8221         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8222                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8223         /* Prepare the buffer, 2 entries */
8224         filter_replace_buf.data[0] =
8225                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8226         filter_replace_buf.data[0] |=
8227                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8228         filter_replace_buf.data[2] = 0xFF;
8229         filter_replace_buf.data[3] = 0xFF;
8230         filter_replace_buf.data[4] =
8231                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8232         filter_replace_buf.data[4] |=
8233                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8234         filter_replace_buf.data[6] = 0xFF;
8235         filter_replace_buf.data[7] = 0xFF;
8236
8237         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8238                                                &filter_replace_buf);
8239         if (!status && (filter_replace.old_filter_type !=
8240                         filter_replace.new_filter_type))
8241                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8242                             " original: 0x%x, new: 0x%x",
8243                             dev->device->name,
8244                             filter_replace.old_filter_type,
8245                             filter_replace.new_filter_type);
8246
8247         return status;
8248 }
8249
8250 static enum
8251 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8252 {
8253         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8254         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8255         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8256         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8257         enum i40e_status_code status = I40E_SUCCESS;
8258
8259         if (pf->support_multi_driver) {
8260                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8261                 return I40E_NOT_SUPPORTED;
8262         }
8263
8264         /* for GTP-C */
8265         memset(&filter_replace, 0,
8266                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8267         memset(&filter_replace_buf, 0,
8268                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8269         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8270         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8271         filter_replace.new_filter_type =
8272                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8273         /* Prepare the buffer, 2 entries */
8274         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8275         filter_replace_buf.data[0] |=
8276                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8277         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8278         filter_replace_buf.data[4] |=
8279                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8280         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8281                                                &filter_replace_buf);
8282         if (status < 0)
8283                 return status;
8284         if (filter_replace.old_filter_type !=
8285             filter_replace.new_filter_type)
8286                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8287                             " original: 0x%x, new: 0x%x",
8288                             dev->device->name,
8289                             filter_replace.old_filter_type,
8290                             filter_replace.new_filter_type);
8291
8292         /* for GTP-U */
8293         memset(&filter_replace, 0,
8294                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8295         memset(&filter_replace_buf, 0,
8296                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8297         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8298         filter_replace.old_filter_type =
8299                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8300         filter_replace.new_filter_type =
8301                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8302         /* Prepare the buffer, 2 entries */
8303         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8304         filter_replace_buf.data[0] |=
8305                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8306         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8307         filter_replace_buf.data[4] |=
8308                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8309
8310         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8311                                                &filter_replace_buf);
8312         if (!status && (filter_replace.old_filter_type !=
8313                         filter_replace.new_filter_type))
8314                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8315                             " original: 0x%x, new: 0x%x",
8316                             dev->device->name,
8317                             filter_replace.old_filter_type,
8318                             filter_replace.new_filter_type);
8319
8320         return status;
8321 }
8322
8323 int
8324 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8325                       struct i40e_tunnel_filter_conf *tunnel_filter,
8326                       uint8_t add)
8327 {
8328         uint16_t ip_type;
8329         uint32_t ipv4_addr, ipv4_addr_le;
8330         uint8_t i, tun_type = 0;
8331         /* internal variable to convert ipv6 byte order */
8332         uint32_t convert_ipv6[4];
8333         int val, ret = 0;
8334         struct i40e_pf_vf *vf = NULL;
8335         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8336         struct i40e_vsi *vsi;
8337         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8338         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8339         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8340         struct i40e_tunnel_filter *tunnel, *node;
8341         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8342         uint32_t teid_le;
8343         bool big_buffer = 0;
8344
8345         cld_filter = rte_zmalloc("tunnel_filter",
8346                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8347                          0);
8348
8349         if (cld_filter == NULL) {
8350                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8351                 return -ENOMEM;
8352         }
8353         pfilter = cld_filter;
8354
8355         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8356                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8357         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8358                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8359
8360         pfilter->element.inner_vlan =
8361                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8362         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8363                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8364                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8365                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8366                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8367                                 &ipv4_addr_le,
8368                                 sizeof(pfilter->element.ipaddr.v4.data));
8369         } else {
8370                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8371                 for (i = 0; i < 4; i++) {
8372                         convert_ipv6[i] =
8373                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8374                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8375                 }
8376                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8377                            &convert_ipv6,
8378                            sizeof(pfilter->element.ipaddr.v6.data));
8379         }
8380
8381         /* check tunneled type */
8382         switch (tunnel_filter->tunnel_type) {
8383         case I40E_TUNNEL_TYPE_VXLAN:
8384                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8385                 break;
8386         case I40E_TUNNEL_TYPE_NVGRE:
8387                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8388                 break;
8389         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8390                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8391                 break;
8392         case I40E_TUNNEL_TYPE_MPLSoUDP:
8393                 if (!pf->mpls_replace_flag) {
8394                         i40e_replace_mpls_l1_filter(pf);
8395                         i40e_replace_mpls_cloud_filter(pf);
8396                         pf->mpls_replace_flag = 1;
8397                 }
8398                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8399                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8400                         teid_le >> 4;
8401                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8402                         (teid_le & 0xF) << 12;
8403                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8404                         0x40;
8405                 big_buffer = 1;
8406                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8407                 break;
8408         case I40E_TUNNEL_TYPE_MPLSoGRE:
8409                 if (!pf->mpls_replace_flag) {
8410                         i40e_replace_mpls_l1_filter(pf);
8411                         i40e_replace_mpls_cloud_filter(pf);
8412                         pf->mpls_replace_flag = 1;
8413                 }
8414                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8415                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8416                         teid_le >> 4;
8417                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8418                         (teid_le & 0xF) << 12;
8419                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8420                         0x0;
8421                 big_buffer = 1;
8422                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8423                 break;
8424         case I40E_TUNNEL_TYPE_GTPC:
8425                 if (!pf->gtp_replace_flag) {
8426                         i40e_replace_gtp_l1_filter(pf);
8427                         i40e_replace_gtp_cloud_filter(pf);
8428                         pf->gtp_replace_flag = 1;
8429                 }
8430                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8431                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8432                         (teid_le >> 16) & 0xFFFF;
8433                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8434                         teid_le & 0xFFFF;
8435                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8436                         0x0;
8437                 big_buffer = 1;
8438                 break;
8439         case I40E_TUNNEL_TYPE_GTPU:
8440                 if (!pf->gtp_replace_flag) {
8441                         i40e_replace_gtp_l1_filter(pf);
8442                         i40e_replace_gtp_cloud_filter(pf);
8443                         pf->gtp_replace_flag = 1;
8444                 }
8445                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8446                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8447                         (teid_le >> 16) & 0xFFFF;
8448                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8449                         teid_le & 0xFFFF;
8450                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8451                         0x0;
8452                 big_buffer = 1;
8453                 break;
8454         case I40E_TUNNEL_TYPE_QINQ:
8455                 if (!pf->qinq_replace_flag) {
8456                         ret = i40e_cloud_filter_qinq_create(pf);
8457                         if (ret < 0)
8458                                 PMD_DRV_LOG(DEBUG,
8459                                             "QinQ tunnel filter already created.");
8460                         pf->qinq_replace_flag = 1;
8461                 }
8462                 /*      Add in the General fields the values of
8463                  *      the Outer and Inner VLAN
8464                  *      Big Buffer should be set, see changes in
8465                  *      i40e_aq_add_cloud_filters
8466                  */
8467                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8468                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8469                 big_buffer = 1;
8470                 break;
8471         default:
8472                 /* Other tunnel types is not supported. */
8473                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8474                 rte_free(cld_filter);
8475                 return -EINVAL;
8476         }
8477
8478         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8479                 pfilter->element.flags =
8480                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8481         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8482                 pfilter->element.flags =
8483                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8484         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8485                 pfilter->element.flags =
8486                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8487         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8488                 pfilter->element.flags =
8489                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8490         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8491                 pfilter->element.flags |=
8492                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8493         else {
8494                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8495                                                 &pfilter->element.flags);
8496                 if (val < 0) {
8497                         rte_free(cld_filter);
8498                         return -EINVAL;
8499                 }
8500         }
8501
8502         pfilter->element.flags |= rte_cpu_to_le_16(
8503                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8504                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8505         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8506         pfilter->element.queue_number =
8507                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8508
8509         if (!tunnel_filter->is_to_vf)
8510                 vsi = pf->main_vsi;
8511         else {
8512                 if (tunnel_filter->vf_id >= pf->vf_num) {
8513                         PMD_DRV_LOG(ERR, "Invalid argument.");
8514                         rte_free(cld_filter);
8515                         return -EINVAL;
8516                 }
8517                 vf = &pf->vfs[tunnel_filter->vf_id];
8518                 vsi = vf->vsi;
8519         }
8520
8521         /* Check if there is the filter in SW list */
8522         memset(&check_filter, 0, sizeof(check_filter));
8523         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8524         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8525         check_filter.vf_id = tunnel_filter->vf_id;
8526         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8527         if (add && node) {
8528                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8529                 rte_free(cld_filter);
8530                 return -EINVAL;
8531         }
8532
8533         if (!add && !node) {
8534                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8535                 rte_free(cld_filter);
8536                 return -EINVAL;
8537         }
8538
8539         if (add) {
8540                 if (big_buffer)
8541                         ret = i40e_aq_add_cloud_filters_bb(hw,
8542                                                    vsi->seid, cld_filter, 1);
8543                 else
8544                         ret = i40e_aq_add_cloud_filters(hw,
8545                                         vsi->seid, &cld_filter->element, 1);
8546                 if (ret < 0) {
8547                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8548                         rte_free(cld_filter);
8549                         return -ENOTSUP;
8550                 }
8551                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8552                 if (tunnel == NULL) {
8553                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8554                         rte_free(cld_filter);
8555                         return -ENOMEM;
8556                 }
8557
8558                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8559                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8560                 if (ret < 0)
8561                         rte_free(tunnel);
8562         } else {
8563                 if (big_buffer)
8564                         ret = i40e_aq_rem_cloud_filters_bb(
8565                                 hw, vsi->seid, cld_filter, 1);
8566                 else
8567                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8568                                                 &cld_filter->element, 1);
8569                 if (ret < 0) {
8570                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8571                         rte_free(cld_filter);
8572                         return -ENOTSUP;
8573                 }
8574                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8575         }
8576
8577         rte_free(cld_filter);
8578         return ret;
8579 }
8580
8581 static int
8582 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8583 {
8584         uint8_t i;
8585
8586         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8587                 if (pf->vxlan_ports[i] == port)
8588                         return i;
8589         }
8590
8591         return -1;
8592 }
8593
8594 static int
8595 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8596 {
8597         int  idx, ret;
8598         uint8_t filter_idx = 0;
8599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8600
8601         idx = i40e_get_vxlan_port_idx(pf, port);
8602
8603         /* Check if port already exists */
8604         if (idx >= 0) {
8605                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8606                 return -EINVAL;
8607         }
8608
8609         /* Now check if there is space to add the new port */
8610         idx = i40e_get_vxlan_port_idx(pf, 0);
8611         if (idx < 0) {
8612                 PMD_DRV_LOG(ERR,
8613                         "Maximum number of UDP ports reached, not adding port %d",
8614                         port);
8615                 return -ENOSPC;
8616         }
8617
8618         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8619                                         &filter_idx, NULL);
8620         if (ret < 0) {
8621                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8622                 return -1;
8623         }
8624
8625         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8626                          port,  filter_idx);
8627
8628         /* New port: add it and mark its index in the bitmap */
8629         pf->vxlan_ports[idx] = port;
8630         pf->vxlan_bitmap |= (1 << idx);
8631
8632         if (!(pf->flags & I40E_FLAG_VXLAN))
8633                 pf->flags |= I40E_FLAG_VXLAN;
8634
8635         return 0;
8636 }
8637
8638 static int
8639 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8640 {
8641         int idx;
8642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8643
8644         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8645                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8646                 return -EINVAL;
8647         }
8648
8649         idx = i40e_get_vxlan_port_idx(pf, port);
8650
8651         if (idx < 0) {
8652                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8653                 return -EINVAL;
8654         }
8655
8656         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8657                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8658                 return -1;
8659         }
8660
8661         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8662                         port, idx);
8663
8664         pf->vxlan_ports[idx] = 0;
8665         pf->vxlan_bitmap &= ~(1 << idx);
8666
8667         if (!pf->vxlan_bitmap)
8668                 pf->flags &= ~I40E_FLAG_VXLAN;
8669
8670         return 0;
8671 }
8672
8673 /* Add UDP tunneling port */
8674 static int
8675 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8676                              struct rte_eth_udp_tunnel *udp_tunnel)
8677 {
8678         int ret = 0;
8679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8680
8681         if (udp_tunnel == NULL)
8682                 return -EINVAL;
8683
8684         switch (udp_tunnel->prot_type) {
8685         case RTE_TUNNEL_TYPE_VXLAN:
8686                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8687                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8688                 break;
8689         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8690                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8691                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8692                 break;
8693         case RTE_TUNNEL_TYPE_GENEVE:
8694         case RTE_TUNNEL_TYPE_TEREDO:
8695                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8696                 ret = -1;
8697                 break;
8698
8699         default:
8700                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8701                 ret = -1;
8702                 break;
8703         }
8704
8705         return ret;
8706 }
8707
8708 /* Remove UDP tunneling port */
8709 static int
8710 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8711                              struct rte_eth_udp_tunnel *udp_tunnel)
8712 {
8713         int ret = 0;
8714         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8715
8716         if (udp_tunnel == NULL)
8717                 return -EINVAL;
8718
8719         switch (udp_tunnel->prot_type) {
8720         case RTE_TUNNEL_TYPE_VXLAN:
8721         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8722                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8723                 break;
8724         case RTE_TUNNEL_TYPE_GENEVE:
8725         case RTE_TUNNEL_TYPE_TEREDO:
8726                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8727                 ret = -1;
8728                 break;
8729         default:
8730                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8731                 ret = -1;
8732                 break;
8733         }
8734
8735         return ret;
8736 }
8737
8738 /* Calculate the maximum number of contiguous PF queues that are configured */
8739 static int
8740 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8741 {
8742         struct rte_eth_dev_data *data = pf->dev_data;
8743         int i, num;
8744         struct i40e_rx_queue *rxq;
8745
8746         num = 0;
8747         for (i = 0; i < pf->lan_nb_qps; i++) {
8748                 rxq = data->rx_queues[i];
8749                 if (rxq && rxq->q_set)
8750                         num++;
8751                 else
8752                         break;
8753         }
8754
8755         return num;
8756 }
8757
8758 /* Configure RSS */
8759 static int
8760 i40e_pf_config_rss(struct i40e_pf *pf)
8761 {
8762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8763         struct rte_eth_rss_conf rss_conf;
8764         uint32_t i, lut = 0;
8765         uint16_t j, num;
8766
8767         /*
8768          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8769          * It's necessary to calculate the actual PF queues that are configured.
8770          */
8771         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8772                 num = i40e_pf_calc_configured_queues_num(pf);
8773         else
8774                 num = pf->dev_data->nb_rx_queues;
8775
8776         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8777         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8778                         num);
8779
8780         if (num == 0) {
8781                 PMD_INIT_LOG(ERR,
8782                         "No PF queues are configured to enable RSS for port %u",
8783                         pf->dev_data->port_id);
8784                 return -ENOTSUP;
8785         }
8786
8787         if (pf->adapter->rss_reta_updated == 0) {
8788                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8789                         if (j == num)
8790                                 j = 0;
8791                         lut = (lut << 8) | (j & ((0x1 <<
8792                                 hw->func_caps.rss_table_entry_width) - 1));
8793                         if ((i & 3) == 3)
8794                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8795                                                rte_bswap32(lut));
8796                 }
8797         }
8798
8799         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8800         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8801                 i40e_pf_disable_rss(pf);
8802                 return 0;
8803         }
8804         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8805                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8806                 /* Random default keys */
8807                 static uint32_t rss_key_default[] = {0x6b793944,
8808                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8809                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8810                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8811
8812                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8813                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8814                                                         sizeof(uint32_t);
8815         }
8816
8817         return i40e_hw_rss_hash_set(pf, &rss_conf);
8818 }
8819
8820 static int
8821 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8822                                struct rte_eth_tunnel_filter_conf *filter)
8823 {
8824         if (pf == NULL || filter == NULL) {
8825                 PMD_DRV_LOG(ERR, "Invalid parameter");
8826                 return -EINVAL;
8827         }
8828
8829         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8830                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8831                 return -EINVAL;
8832         }
8833
8834         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8835                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8836                 return -EINVAL;
8837         }
8838
8839         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8840                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8841                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8842                 return -EINVAL;
8843         }
8844
8845         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8846                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8847                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8848                 return -EINVAL;
8849         }
8850
8851         return 0;
8852 }
8853
8854 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8855 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8856 static int
8857 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8858 {
8859         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8860         uint32_t val, reg;
8861         int ret = -EINVAL;
8862
8863         if (pf->support_multi_driver) {
8864                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8865                 return -ENOTSUP;
8866         }
8867
8868         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8869         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8870
8871         if (len == 3) {
8872                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8873         } else if (len == 4) {
8874                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8875         } else {
8876                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8877                 return ret;
8878         }
8879
8880         if (reg != val) {
8881                 ret = i40e_aq_debug_write_global_register(hw,
8882                                                    I40E_GL_PRS_FVBM(2),
8883                                                    reg, NULL);
8884                 if (ret != 0)
8885                         return ret;
8886                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8887                             "with value 0x%08x",
8888                             I40E_GL_PRS_FVBM(2), reg);
8889         } else {
8890                 ret = 0;
8891         }
8892         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8893                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8894
8895         return ret;
8896 }
8897
8898 static int
8899 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8900 {
8901         int ret = -EINVAL;
8902
8903         if (!hw || !cfg)
8904                 return -EINVAL;
8905
8906         switch (cfg->cfg_type) {
8907         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8908                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8909                 break;
8910         default:
8911                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8912                 break;
8913         }
8914
8915         return ret;
8916 }
8917
8918 static int
8919 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8920                                enum rte_filter_op filter_op,
8921                                void *arg)
8922 {
8923         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8924         int ret = I40E_ERR_PARAM;
8925
8926         switch (filter_op) {
8927         case RTE_ETH_FILTER_SET:
8928                 ret = i40e_dev_global_config_set(hw,
8929                         (struct rte_eth_global_cfg *)arg);
8930                 break;
8931         default:
8932                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8933                 break;
8934         }
8935
8936         return ret;
8937 }
8938
8939 static int
8940 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8941                           enum rte_filter_op filter_op,
8942                           void *arg)
8943 {
8944         struct rte_eth_tunnel_filter_conf *filter;
8945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8946         int ret = I40E_SUCCESS;
8947
8948         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8949
8950         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8951                 return I40E_ERR_PARAM;
8952
8953         switch (filter_op) {
8954         case RTE_ETH_FILTER_NOP:
8955                 if (!(pf->flags & I40E_FLAG_VXLAN))
8956                         ret = I40E_NOT_SUPPORTED;
8957                 break;
8958         case RTE_ETH_FILTER_ADD:
8959                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8960                 break;
8961         case RTE_ETH_FILTER_DELETE:
8962                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8963                 break;
8964         default:
8965                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8966                 ret = I40E_ERR_PARAM;
8967                 break;
8968         }
8969
8970         return ret;
8971 }
8972
8973 static int
8974 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8975 {
8976         int ret = 0;
8977         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8978
8979         /* RSS setup */
8980         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8981                 ret = i40e_pf_config_rss(pf);
8982         else
8983                 i40e_pf_disable_rss(pf);
8984
8985         return ret;
8986 }
8987
8988 /* Get the symmetric hash enable configurations per port */
8989 static void
8990 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8991 {
8992         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8993
8994         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8995 }
8996
8997 /* Set the symmetric hash enable configurations per port */
8998 static void
8999 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9000 {
9001         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9002
9003         if (enable > 0) {
9004                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9005                         PMD_DRV_LOG(INFO,
9006                                 "Symmetric hash has already been enabled");
9007                         return;
9008                 }
9009                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9010         } else {
9011                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9012                         PMD_DRV_LOG(INFO,
9013                                 "Symmetric hash has already been disabled");
9014                         return;
9015                 }
9016                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9017         }
9018         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9019         I40E_WRITE_FLUSH(hw);
9020 }
9021
9022 /*
9023  * Get global configurations of hash function type and symmetric hash enable
9024  * per flow type (pctype). Note that global configuration means it affects all
9025  * the ports on the same NIC.
9026  */
9027 static int
9028 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9029                                    struct rte_eth_hash_global_conf *g_cfg)
9030 {
9031         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9032         uint32_t reg;
9033         uint16_t i, j;
9034
9035         memset(g_cfg, 0, sizeof(*g_cfg));
9036         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9037         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9038                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9039         else
9040                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9041         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9042                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9043
9044         /*
9045          * As i40e supports less than 64 flow types, only first 64 bits need to
9046          * be checked.
9047          */
9048         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9049                 g_cfg->valid_bit_mask[i] = 0ULL;
9050                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9051         }
9052
9053         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9054
9055         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9056                 if (!adapter->pctypes_tbl[i])
9057                         continue;
9058                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9059                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9060                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9061                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9062                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9063                                         g_cfg->sym_hash_enable_mask[0] |=
9064                                                                 (1ULL << i);
9065                                 }
9066                         }
9067                 }
9068         }
9069
9070         return 0;
9071 }
9072
9073 static int
9074 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9075                               const struct rte_eth_hash_global_conf *g_cfg)
9076 {
9077         uint32_t i;
9078         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9079
9080         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9081                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9082                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9083                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9084                                                 g_cfg->hash_func);
9085                 return -EINVAL;
9086         }
9087
9088         /*
9089          * As i40e supports less than 64 flow types, only first 64 bits need to
9090          * be checked.
9091          */
9092         mask0 = g_cfg->valid_bit_mask[0];
9093         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9094                 if (i == 0) {
9095                         /* Check if any unsupported flow type configured */
9096                         if ((mask0 | i40e_mask) ^ i40e_mask)
9097                                 goto mask_err;
9098                 } else {
9099                         if (g_cfg->valid_bit_mask[i])
9100                                 goto mask_err;
9101                 }
9102         }
9103
9104         return 0;
9105
9106 mask_err:
9107         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9108
9109         return -EINVAL;
9110 }
9111
9112 /*
9113  * Set global configurations of hash function type and symmetric hash enable
9114  * per flow type (pctype). Note any modifying global configuration will affect
9115  * all the ports on the same NIC.
9116  */
9117 static int
9118 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9119                                    struct rte_eth_hash_global_conf *g_cfg)
9120 {
9121         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9122         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9123         int ret;
9124         uint16_t i, j;
9125         uint32_t reg;
9126         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9127
9128         if (pf->support_multi_driver) {
9129                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9130                 return -ENOTSUP;
9131         }
9132
9133         /* Check the input parameters */
9134         ret = i40e_hash_global_config_check(adapter, g_cfg);
9135         if (ret < 0)
9136                 return ret;
9137
9138         /*
9139          * As i40e supports less than 64 flow types, only first 64 bits need to
9140          * be configured.
9141          */
9142         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9143                 if (mask0 & (1UL << i)) {
9144                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9145                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9146
9147                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9148                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9149                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9150                                         i40e_write_global_rx_ctl(hw,
9151                                                           I40E_GLQF_HSYM(j),
9152                                                           reg);
9153                         }
9154                 }
9155         }
9156
9157         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9158         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9159                 /* Toeplitz */
9160                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9161                         PMD_DRV_LOG(DEBUG,
9162                                 "Hash function already set to Toeplitz");
9163                         goto out;
9164                 }
9165                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9166         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9167                 /* Simple XOR */
9168                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9169                         PMD_DRV_LOG(DEBUG,
9170                                 "Hash function already set to Simple XOR");
9171                         goto out;
9172                 }
9173                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9174         } else
9175                 /* Use the default, and keep it as it is */
9176                 goto out;
9177
9178         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9179
9180 out:
9181         I40E_WRITE_FLUSH(hw);
9182
9183         return 0;
9184 }
9185
9186 /**
9187  * Valid input sets for hash and flow director filters per PCTYPE
9188  */
9189 static uint64_t
9190 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9191                 enum rte_filter_type filter)
9192 {
9193         uint64_t valid;
9194
9195         static const uint64_t valid_hash_inset_table[] = {
9196                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9197                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9198                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9199                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9200                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9201                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9202                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9203                         I40E_INSET_FLEX_PAYLOAD,
9204                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9205                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9206                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9208                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9209                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9210                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9211                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9212                         I40E_INSET_FLEX_PAYLOAD,
9213                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9214                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9215                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9216                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9217                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9218                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9219                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9220                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9221                         I40E_INSET_FLEX_PAYLOAD,
9222                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9223                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9224                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9225                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9226                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9227                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9228                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9229                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9230                         I40E_INSET_FLEX_PAYLOAD,
9231                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9232                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9233                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9234                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9235                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9236                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9237                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9238                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9239                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9240                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9241                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9242                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9243                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9244                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9245                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9246                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9247                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9248                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9249                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9250                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9251                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9253                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9254                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9255                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9256                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9257                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9259                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9260                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9261                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9262                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9263                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9264                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9265                         I40E_INSET_FLEX_PAYLOAD,
9266                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9267                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9268                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9269                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9270                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9271                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9272                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9273                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9274                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9275                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9276                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9277                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9278                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9279                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9280                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9281                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9282                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9283                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9284                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9285                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9286                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9287                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9288                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9289                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9290                         I40E_INSET_FLEX_PAYLOAD,
9291                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9292                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9293                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9294                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9295                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9296                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9297                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9298                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9299                         I40E_INSET_FLEX_PAYLOAD,
9300                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9301                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9302                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9304                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9305                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9306                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9307                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9308                         I40E_INSET_FLEX_PAYLOAD,
9309                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9310                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9311                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9312                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9313                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9314                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9315                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9316                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9317                         I40E_INSET_FLEX_PAYLOAD,
9318                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9319                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9320                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9321                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9322                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9323                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9324                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9325                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9326                         I40E_INSET_FLEX_PAYLOAD,
9327                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9328                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9329                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9330                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9331                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9332                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9333                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9334                         I40E_INSET_FLEX_PAYLOAD,
9335                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9336                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9337                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9338                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9339                         I40E_INSET_FLEX_PAYLOAD,
9340         };
9341
9342         /**
9343          * Flow director supports only fields defined in
9344          * union rte_eth_fdir_flow.
9345          */
9346         static const uint64_t valid_fdir_inset_table[] = {
9347                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9348                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9349                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9350                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9351                 I40E_INSET_IPV4_TTL,
9352                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9353                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9354                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9355                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9356                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9357                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9358                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9359                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9360                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9361                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9362                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9363                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9364                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9365                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9366                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9367                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9368                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9369                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9370                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9371                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9372                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9373                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9374                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9375                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9376                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9377                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9378                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9379                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9380                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9381                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9382                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9383                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9384                 I40E_INSET_SCTP_VT,
9385                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9386                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9387                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9388                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9389                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9390                 I40E_INSET_IPV4_TTL,
9391                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9392                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9393                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9394                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9395                 I40E_INSET_IPV6_HOP_LIMIT,
9396                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9397                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9398                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9399                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9400                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9401                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9402                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9403                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9404                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9405                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9406                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9407                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9408                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9409                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9410                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9411                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9412                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9413                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9414                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9415                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9416                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9417                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9418                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9419                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9420                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9421                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9422                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9423                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9424                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9425                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9426                 I40E_INSET_SCTP_VT,
9427                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9428                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9429                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9430                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9431                 I40E_INSET_IPV6_HOP_LIMIT,
9432                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9433                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9434                 I40E_INSET_LAST_ETHER_TYPE,
9435         };
9436
9437         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9438                 return 0;
9439         if (filter == RTE_ETH_FILTER_HASH)
9440                 valid = valid_hash_inset_table[pctype];
9441         else
9442                 valid = valid_fdir_inset_table[pctype];
9443
9444         return valid;
9445 }
9446
9447 /**
9448  * Validate if the input set is allowed for a specific PCTYPE
9449  */
9450 int
9451 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9452                 enum rte_filter_type filter, uint64_t inset)
9453 {
9454         uint64_t valid;
9455
9456         valid = i40e_get_valid_input_set(pctype, filter);
9457         if (inset & (~valid))
9458                 return -EINVAL;
9459
9460         return 0;
9461 }
9462
9463 /* default input set fields combination per pctype */
9464 uint64_t
9465 i40e_get_default_input_set(uint16_t pctype)
9466 {
9467         static const uint64_t default_inset_table[] = {
9468                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9469                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9470                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9471                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9472                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9473                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9474                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9475                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9476                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9477                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9478                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9479                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9480                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9481                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9482                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9483                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9484                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9485                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9486                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9487                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9488                         I40E_INSET_SCTP_VT,
9489                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9490                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9491                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9492                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9493                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9494                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9495                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9496                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9497                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9498                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9499                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9500                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9501                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9502                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9503                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9504                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9505                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9506                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9507                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9508                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9509                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9510                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9511                         I40E_INSET_SCTP_VT,
9512                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9513                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9514                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9515                         I40E_INSET_LAST_ETHER_TYPE,
9516         };
9517
9518         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9519                 return 0;
9520
9521         return default_inset_table[pctype];
9522 }
9523
9524 /**
9525  * Parse the input set from index to logical bit masks
9526  */
9527 static int
9528 i40e_parse_input_set(uint64_t *inset,
9529                      enum i40e_filter_pctype pctype,
9530                      enum rte_eth_input_set_field *field,
9531                      uint16_t size)
9532 {
9533         uint16_t i, j;
9534         int ret = -EINVAL;
9535
9536         static const struct {
9537                 enum rte_eth_input_set_field field;
9538                 uint64_t inset;
9539         } inset_convert_table[] = {
9540                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9541                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9542                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9543                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9544                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9545                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9546                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9547                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9548                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9549                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9550                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9551                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9552                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9553                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9554                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9555                         I40E_INSET_IPV6_NEXT_HDR},
9556                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9557                         I40E_INSET_IPV6_HOP_LIMIT},
9558                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9559                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9560                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9561                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9562                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9563                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9564                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9565                         I40E_INSET_SCTP_VT},
9566                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9567                         I40E_INSET_TUNNEL_DMAC},
9568                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9569                         I40E_INSET_VLAN_TUNNEL},
9570                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9571                         I40E_INSET_TUNNEL_ID},
9572                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9573                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9574                         I40E_INSET_FLEX_PAYLOAD_W1},
9575                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9576                         I40E_INSET_FLEX_PAYLOAD_W2},
9577                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9578                         I40E_INSET_FLEX_PAYLOAD_W3},
9579                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9580                         I40E_INSET_FLEX_PAYLOAD_W4},
9581                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9582                         I40E_INSET_FLEX_PAYLOAD_W5},
9583                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9584                         I40E_INSET_FLEX_PAYLOAD_W6},
9585                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9586                         I40E_INSET_FLEX_PAYLOAD_W7},
9587                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9588                         I40E_INSET_FLEX_PAYLOAD_W8},
9589         };
9590
9591         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9592                 return ret;
9593
9594         /* Only one item allowed for default or all */
9595         if (size == 1) {
9596                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9597                         *inset = i40e_get_default_input_set(pctype);
9598                         return 0;
9599                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9600                         *inset = I40E_INSET_NONE;
9601                         return 0;
9602                 }
9603         }
9604
9605         for (i = 0, *inset = 0; i < size; i++) {
9606                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9607                         if (field[i] == inset_convert_table[j].field) {
9608                                 *inset |= inset_convert_table[j].inset;
9609                                 break;
9610                         }
9611                 }
9612
9613                 /* It contains unsupported input set, return immediately */
9614                 if (j == RTE_DIM(inset_convert_table))
9615                         return ret;
9616         }
9617
9618         return 0;
9619 }
9620
9621 /**
9622  * Translate the input set from bit masks to register aware bit masks
9623  * and vice versa
9624  */
9625 uint64_t
9626 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9627 {
9628         uint64_t val = 0;
9629         uint16_t i;
9630
9631         struct inset_map {
9632                 uint64_t inset;
9633                 uint64_t inset_reg;
9634         };
9635
9636         static const struct inset_map inset_map_common[] = {
9637                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9638                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9639                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9640                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9641                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9642                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9643                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9644                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9645                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9646                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9647                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9648                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9649                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9650                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9651                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9652                 {I40E_INSET_TUNNEL_DMAC,
9653                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9654                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9655                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9656                 {I40E_INSET_TUNNEL_SRC_PORT,
9657                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9658                 {I40E_INSET_TUNNEL_DST_PORT,
9659                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9660                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9661                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9662                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9663                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9664                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9665                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9666                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9667                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9668                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9669         };
9670
9671     /* some different registers map in x722*/
9672         static const struct inset_map inset_map_diff_x722[] = {
9673                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9674                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9675                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9676                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9677         };
9678
9679         static const struct inset_map inset_map_diff_not_x722[] = {
9680                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9681                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9682                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9683                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9684         };
9685
9686         if (input == 0)
9687                 return val;
9688
9689         /* Translate input set to register aware inset */
9690         if (type == I40E_MAC_X722) {
9691                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9692                         if (input & inset_map_diff_x722[i].inset)
9693                                 val |= inset_map_diff_x722[i].inset_reg;
9694                 }
9695         } else {
9696                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9697                         if (input & inset_map_diff_not_x722[i].inset)
9698                                 val |= inset_map_diff_not_x722[i].inset_reg;
9699                 }
9700         }
9701
9702         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9703                 if (input & inset_map_common[i].inset)
9704                         val |= inset_map_common[i].inset_reg;
9705         }
9706
9707         return val;
9708 }
9709
9710 int
9711 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9712 {
9713         uint8_t i, idx = 0;
9714         uint64_t inset_need_mask = inset;
9715
9716         static const struct {
9717                 uint64_t inset;
9718                 uint32_t mask;
9719         } inset_mask_map[] = {
9720                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9721                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9722                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9723                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9724                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9725                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9726                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9727                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9728         };
9729
9730         if (!inset || !mask || !nb_elem)
9731                 return 0;
9732
9733         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9734                 /* Clear the inset bit, if no MASK is required,
9735                  * for example proto + ttl
9736                  */
9737                 if ((inset & inset_mask_map[i].inset) ==
9738                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9739                         inset_need_mask &= ~inset_mask_map[i].inset;
9740                 if (!inset_need_mask)
9741                         return 0;
9742         }
9743         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9744                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9745                     inset_mask_map[i].inset) {
9746                         if (idx >= nb_elem) {
9747                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9748                                 return -EINVAL;
9749                         }
9750                         mask[idx] = inset_mask_map[i].mask;
9751                         idx++;
9752                 }
9753         }
9754
9755         return idx;
9756 }
9757
9758 void
9759 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9760 {
9761         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9762
9763         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9764         if (reg != val)
9765                 i40e_write_rx_ctl(hw, addr, val);
9766         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9767                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9768 }
9769
9770 void
9771 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9772 {
9773         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9774         struct rte_eth_dev *dev;
9775
9776         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9777         if (reg != val) {
9778                 i40e_write_rx_ctl(hw, addr, val);
9779                 PMD_DRV_LOG(WARNING,
9780                             "i40e device %s changed global register [0x%08x]."
9781                             " original: 0x%08x, new: 0x%08x",
9782                             dev->device->name, addr, reg,
9783                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9784         }
9785 }
9786
9787 static void
9788 i40e_filter_input_set_init(struct i40e_pf *pf)
9789 {
9790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9791         enum i40e_filter_pctype pctype;
9792         uint64_t input_set, inset_reg;
9793         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9794         int num, i;
9795         uint16_t flow_type;
9796
9797         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9798              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9799                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9800
9801                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9802                         continue;
9803
9804                 input_set = i40e_get_default_input_set(pctype);
9805
9806                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9807                                                    I40E_INSET_MASK_NUM_REG);
9808                 if (num < 0)
9809                         return;
9810                 if (pf->support_multi_driver && num > 0) {
9811                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9812                         return;
9813                 }
9814                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9815                                         input_set);
9816
9817                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9818                                       (uint32_t)(inset_reg & UINT32_MAX));
9819                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9820                                      (uint32_t)((inset_reg >>
9821                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9822                 if (!pf->support_multi_driver) {
9823                         i40e_check_write_global_reg(hw,
9824                                             I40E_GLQF_HASH_INSET(0, pctype),
9825                                             (uint32_t)(inset_reg & UINT32_MAX));
9826                         i40e_check_write_global_reg(hw,
9827                                              I40E_GLQF_HASH_INSET(1, pctype),
9828                                              (uint32_t)((inset_reg >>
9829                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9830
9831                         for (i = 0; i < num; i++) {
9832                                 i40e_check_write_global_reg(hw,
9833                                                     I40E_GLQF_FD_MSK(i, pctype),
9834                                                     mask_reg[i]);
9835                                 i40e_check_write_global_reg(hw,
9836                                                   I40E_GLQF_HASH_MSK(i, pctype),
9837                                                   mask_reg[i]);
9838                         }
9839                         /*clear unused mask registers of the pctype */
9840                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9841                                 i40e_check_write_global_reg(hw,
9842                                                     I40E_GLQF_FD_MSK(i, pctype),
9843                                                     0);
9844                                 i40e_check_write_global_reg(hw,
9845                                                   I40E_GLQF_HASH_MSK(i, pctype),
9846                                                   0);
9847                         }
9848                 } else {
9849                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9850                 }
9851                 I40E_WRITE_FLUSH(hw);
9852
9853                 /* store the default input set */
9854                 if (!pf->support_multi_driver)
9855                         pf->hash_input_set[pctype] = input_set;
9856                 pf->fdir.input_set[pctype] = input_set;
9857         }
9858 }
9859
9860 int
9861 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9862                          struct rte_eth_input_set_conf *conf)
9863 {
9864         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9865         enum i40e_filter_pctype pctype;
9866         uint64_t input_set, inset_reg = 0;
9867         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9868         int ret, i, num;
9869
9870         if (!conf) {
9871                 PMD_DRV_LOG(ERR, "Invalid pointer");
9872                 return -EFAULT;
9873         }
9874         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9875             conf->op != RTE_ETH_INPUT_SET_ADD) {
9876                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9877                 return -EINVAL;
9878         }
9879
9880         if (pf->support_multi_driver) {
9881                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9882                 return -ENOTSUP;
9883         }
9884
9885         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9886         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9887                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9888                 return -EINVAL;
9889         }
9890
9891         if (hw->mac.type == I40E_MAC_X722) {
9892                 /* get translated pctype value in fd pctype register */
9893                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9894                         I40E_GLQF_FD_PCTYPES((int)pctype));
9895         }
9896
9897         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9898                                    conf->inset_size);
9899         if (ret) {
9900                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9901                 return -EINVAL;
9902         }
9903
9904         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9905                 /* get inset value in register */
9906                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9907                 inset_reg <<= I40E_32_BIT_WIDTH;
9908                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9909                 input_set |= pf->hash_input_set[pctype];
9910         }
9911         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9912                                            I40E_INSET_MASK_NUM_REG);
9913         if (num < 0)
9914                 return -EINVAL;
9915
9916         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9917
9918         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9919                                     (uint32_t)(inset_reg & UINT32_MAX));
9920         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9921                                     (uint32_t)((inset_reg >>
9922                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9923
9924         for (i = 0; i < num; i++)
9925                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9926                                             mask_reg[i]);
9927         /*clear unused mask registers of the pctype */
9928         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9929                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9930                                             0);
9931         I40E_WRITE_FLUSH(hw);
9932
9933         pf->hash_input_set[pctype] = input_set;
9934         return 0;
9935 }
9936
9937 int
9938 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9939                          struct rte_eth_input_set_conf *conf)
9940 {
9941         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9942         enum i40e_filter_pctype pctype;
9943         uint64_t input_set, inset_reg = 0;
9944         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9945         int ret, i, num;
9946
9947         if (!hw || !conf) {
9948                 PMD_DRV_LOG(ERR, "Invalid pointer");
9949                 return -EFAULT;
9950         }
9951         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9952             conf->op != RTE_ETH_INPUT_SET_ADD) {
9953                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9954                 return -EINVAL;
9955         }
9956
9957         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9958
9959         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9960                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9961                 return -EINVAL;
9962         }
9963
9964         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9965                                    conf->inset_size);
9966         if (ret) {
9967                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9968                 return -EINVAL;
9969         }
9970
9971         /* get inset value in register */
9972         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9973         inset_reg <<= I40E_32_BIT_WIDTH;
9974         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9975
9976         /* Can not change the inset reg for flex payload for fdir,
9977          * it is done by writing I40E_PRTQF_FD_FLXINSET
9978          * in i40e_set_flex_mask_on_pctype.
9979          */
9980         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9981                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9982         else
9983                 input_set |= pf->fdir.input_set[pctype];
9984         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9985                                            I40E_INSET_MASK_NUM_REG);
9986         if (num < 0)
9987                 return -EINVAL;
9988         if (pf->support_multi_driver && num > 0) {
9989                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9990                 return -ENOTSUP;
9991         }
9992
9993         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9994
9995         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9996                               (uint32_t)(inset_reg & UINT32_MAX));
9997         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9998                              (uint32_t)((inset_reg >>
9999                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10000
10001         if (!pf->support_multi_driver) {
10002                 for (i = 0; i < num; i++)
10003                         i40e_check_write_global_reg(hw,
10004                                                     I40E_GLQF_FD_MSK(i, pctype),
10005                                                     mask_reg[i]);
10006                 /*clear unused mask registers of the pctype */
10007                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10008                         i40e_check_write_global_reg(hw,
10009                                                     I40E_GLQF_FD_MSK(i, pctype),
10010                                                     0);
10011         } else {
10012                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10013         }
10014         I40E_WRITE_FLUSH(hw);
10015
10016         pf->fdir.input_set[pctype] = input_set;
10017         return 0;
10018 }
10019
10020 static int
10021 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10022 {
10023         int ret = 0;
10024
10025         if (!hw || !info) {
10026                 PMD_DRV_LOG(ERR, "Invalid pointer");
10027                 return -EFAULT;
10028         }
10029
10030         switch (info->info_type) {
10031         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10032                 i40e_get_symmetric_hash_enable_per_port(hw,
10033                                         &(info->info.enable));
10034                 break;
10035         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10036                 ret = i40e_get_hash_filter_global_config(hw,
10037                                 &(info->info.global_conf));
10038                 break;
10039         default:
10040                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10041                                                         info->info_type);
10042                 ret = -EINVAL;
10043                 break;
10044         }
10045
10046         return ret;
10047 }
10048
10049 static int
10050 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10051 {
10052         int ret = 0;
10053
10054         if (!hw || !info) {
10055                 PMD_DRV_LOG(ERR, "Invalid pointer");
10056                 return -EFAULT;
10057         }
10058
10059         switch (info->info_type) {
10060         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10061                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10062                 break;
10063         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10064                 ret = i40e_set_hash_filter_global_config(hw,
10065                                 &(info->info.global_conf));
10066                 break;
10067         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10068                 ret = i40e_hash_filter_inset_select(hw,
10069                                                &(info->info.input_set_conf));
10070                 break;
10071
10072         default:
10073                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10074                                                         info->info_type);
10075                 ret = -EINVAL;
10076                 break;
10077         }
10078
10079         return ret;
10080 }
10081
10082 /* Operations for hash function */
10083 static int
10084 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10085                       enum rte_filter_op filter_op,
10086                       void *arg)
10087 {
10088         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10089         int ret = 0;
10090
10091         switch (filter_op) {
10092         case RTE_ETH_FILTER_NOP:
10093                 break;
10094         case RTE_ETH_FILTER_GET:
10095                 ret = i40e_hash_filter_get(hw,
10096                         (struct rte_eth_hash_filter_info *)arg);
10097                 break;
10098         case RTE_ETH_FILTER_SET:
10099                 ret = i40e_hash_filter_set(hw,
10100                         (struct rte_eth_hash_filter_info *)arg);
10101                 break;
10102         default:
10103                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10104                                                                 filter_op);
10105                 ret = -ENOTSUP;
10106                 break;
10107         }
10108
10109         return ret;
10110 }
10111
10112 /* Convert ethertype filter structure */
10113 static int
10114 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10115                               struct i40e_ethertype_filter *filter)
10116 {
10117         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10118                 RTE_ETHER_ADDR_LEN);
10119         filter->input.ether_type = input->ether_type;
10120         filter->flags = input->flags;
10121         filter->queue = input->queue;
10122
10123         return 0;
10124 }
10125
10126 /* Check if there exists the ehtertype filter */
10127 struct i40e_ethertype_filter *
10128 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10129                                 const struct i40e_ethertype_filter_input *input)
10130 {
10131         int ret;
10132
10133         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10134         if (ret < 0)
10135                 return NULL;
10136
10137         return ethertype_rule->hash_map[ret];
10138 }
10139
10140 /* Add ethertype filter in SW list */
10141 static int
10142 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10143                                 struct i40e_ethertype_filter *filter)
10144 {
10145         struct i40e_ethertype_rule *rule = &pf->ethertype;
10146         int ret;
10147
10148         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10149         if (ret < 0) {
10150                 PMD_DRV_LOG(ERR,
10151                             "Failed to insert ethertype filter"
10152                             " to hash table %d!",
10153                             ret);
10154                 return ret;
10155         }
10156         rule->hash_map[ret] = filter;
10157
10158         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10159
10160         return 0;
10161 }
10162
10163 /* Delete ethertype filter in SW list */
10164 int
10165 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10166                              struct i40e_ethertype_filter_input *input)
10167 {
10168         struct i40e_ethertype_rule *rule = &pf->ethertype;
10169         struct i40e_ethertype_filter *filter;
10170         int ret;
10171
10172         ret = rte_hash_del_key(rule->hash_table, input);
10173         if (ret < 0) {
10174                 PMD_DRV_LOG(ERR,
10175                             "Failed to delete ethertype filter"
10176                             " to hash table %d!",
10177                             ret);
10178                 return ret;
10179         }
10180         filter = rule->hash_map[ret];
10181         rule->hash_map[ret] = NULL;
10182
10183         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10184         rte_free(filter);
10185
10186         return 0;
10187 }
10188
10189 /*
10190  * Configure ethertype filter, which can director packet by filtering
10191  * with mac address and ether_type or only ether_type
10192  */
10193 int
10194 i40e_ethertype_filter_set(struct i40e_pf *pf,
10195                         struct rte_eth_ethertype_filter *filter,
10196                         bool add)
10197 {
10198         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10199         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10200         struct i40e_ethertype_filter *ethertype_filter, *node;
10201         struct i40e_ethertype_filter check_filter;
10202         struct i40e_control_filter_stats stats;
10203         uint16_t flags = 0;
10204         int ret;
10205
10206         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10207                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10208                 return -EINVAL;
10209         }
10210         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10211                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10212                 PMD_DRV_LOG(ERR,
10213                         "unsupported ether_type(0x%04x) in control packet filter.",
10214                         filter->ether_type);
10215                 return -EINVAL;
10216         }
10217         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10218                 PMD_DRV_LOG(WARNING,
10219                         "filter vlan ether_type in first tag is not supported.");
10220
10221         /* Check if there is the filter in SW list */
10222         memset(&check_filter, 0, sizeof(check_filter));
10223         i40e_ethertype_filter_convert(filter, &check_filter);
10224         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10225                                                &check_filter.input);
10226         if (add && node) {
10227                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10228                 return -EINVAL;
10229         }
10230
10231         if (!add && !node) {
10232                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10233                 return -EINVAL;
10234         }
10235
10236         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10237                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10238         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10239                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10240         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10241
10242         memset(&stats, 0, sizeof(stats));
10243         ret = i40e_aq_add_rem_control_packet_filter(hw,
10244                         filter->mac_addr.addr_bytes,
10245                         filter->ether_type, flags,
10246                         pf->main_vsi->seid,
10247                         filter->queue, add, &stats, NULL);
10248
10249         PMD_DRV_LOG(INFO,
10250                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10251                 ret, stats.mac_etype_used, stats.etype_used,
10252                 stats.mac_etype_free, stats.etype_free);
10253         if (ret < 0)
10254                 return -ENOSYS;
10255
10256         /* Add or delete a filter in SW list */
10257         if (add) {
10258                 ethertype_filter = rte_zmalloc("ethertype_filter",
10259                                        sizeof(*ethertype_filter), 0);
10260                 if (ethertype_filter == NULL) {
10261                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10262                         return -ENOMEM;
10263                 }
10264
10265                 rte_memcpy(ethertype_filter, &check_filter,
10266                            sizeof(check_filter));
10267                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10268                 if (ret < 0)
10269                         rte_free(ethertype_filter);
10270         } else {
10271                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10272         }
10273
10274         return ret;
10275 }
10276
10277 /*
10278  * Handle operations for ethertype filter.
10279  */
10280 static int
10281 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10282                                 enum rte_filter_op filter_op,
10283                                 void *arg)
10284 {
10285         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10286         int ret = 0;
10287
10288         if (filter_op == RTE_ETH_FILTER_NOP)
10289                 return ret;
10290
10291         if (arg == NULL) {
10292                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10293                             filter_op);
10294                 return -EINVAL;
10295         }
10296
10297         switch (filter_op) {
10298         case RTE_ETH_FILTER_ADD:
10299                 ret = i40e_ethertype_filter_set(pf,
10300                         (struct rte_eth_ethertype_filter *)arg,
10301                         TRUE);
10302                 break;
10303         case RTE_ETH_FILTER_DELETE:
10304                 ret = i40e_ethertype_filter_set(pf,
10305                         (struct rte_eth_ethertype_filter *)arg,
10306                         FALSE);
10307                 break;
10308         default:
10309                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10310                 ret = -ENOSYS;
10311                 break;
10312         }
10313         return ret;
10314 }
10315
10316 static int
10317 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10318                      enum rte_filter_type filter_type,
10319                      enum rte_filter_op filter_op,
10320                      void *arg)
10321 {
10322         int ret = 0;
10323
10324         if (dev == NULL)
10325                 return -EINVAL;
10326
10327         switch (filter_type) {
10328         case RTE_ETH_FILTER_NONE:
10329                 /* For global configuration */
10330                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10331                 break;
10332         case RTE_ETH_FILTER_HASH:
10333                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10334                 break;
10335         case RTE_ETH_FILTER_MACVLAN:
10336                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10337                 break;
10338         case RTE_ETH_FILTER_ETHERTYPE:
10339                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10340                 break;
10341         case RTE_ETH_FILTER_TUNNEL:
10342                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10343                 break;
10344         case RTE_ETH_FILTER_FDIR:
10345                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10346                 break;
10347         case RTE_ETH_FILTER_GENERIC:
10348                 if (filter_op != RTE_ETH_FILTER_GET)
10349                         return -EINVAL;
10350                 *(const void **)arg = &i40e_flow_ops;
10351                 break;
10352         default:
10353                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10354                                                         filter_type);
10355                 ret = -EINVAL;
10356                 break;
10357         }
10358
10359         return ret;
10360 }
10361
10362 /*
10363  * Check and enable Extended Tag.
10364  * Enabling Extended Tag is important for 40G performance.
10365  */
10366 static void
10367 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10368 {
10369         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10370         uint32_t buf = 0;
10371         int ret;
10372
10373         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10374                                       PCI_DEV_CAP_REG);
10375         if (ret < 0) {
10376                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10377                             PCI_DEV_CAP_REG);
10378                 return;
10379         }
10380         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10381                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10382                 return;
10383         }
10384
10385         buf = 0;
10386         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10387                                       PCI_DEV_CTRL_REG);
10388         if (ret < 0) {
10389                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10390                             PCI_DEV_CTRL_REG);
10391                 return;
10392         }
10393         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10394                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10395                 return;
10396         }
10397         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10398         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10399                                        PCI_DEV_CTRL_REG);
10400         if (ret < 0) {
10401                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10402                             PCI_DEV_CTRL_REG);
10403                 return;
10404         }
10405 }
10406
10407 /*
10408  * As some registers wouldn't be reset unless a global hardware reset,
10409  * hardware initialization is needed to put those registers into an
10410  * expected initial state.
10411  */
10412 static void
10413 i40e_hw_init(struct rte_eth_dev *dev)
10414 {
10415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10416
10417         i40e_enable_extended_tag(dev);
10418
10419         /* clear the PF Queue Filter control register */
10420         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10421
10422         /* Disable symmetric hash per port */
10423         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10424 }
10425
10426 /*
10427  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10428  * however this function will return only one highest pctype index,
10429  * which is not quite correct. This is known problem of i40e driver
10430  * and needs to be fixed later.
10431  */
10432 enum i40e_filter_pctype
10433 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10434 {
10435         int i;
10436         uint64_t pctype_mask;
10437
10438         if (flow_type < I40E_FLOW_TYPE_MAX) {
10439                 pctype_mask = adapter->pctypes_tbl[flow_type];
10440                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10441                         if (pctype_mask & (1ULL << i))
10442                                 return (enum i40e_filter_pctype)i;
10443                 }
10444         }
10445         return I40E_FILTER_PCTYPE_INVALID;
10446 }
10447
10448 uint16_t
10449 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10450                         enum i40e_filter_pctype pctype)
10451 {
10452         uint16_t flowtype;
10453         uint64_t pctype_mask = 1ULL << pctype;
10454
10455         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10456              flowtype++) {
10457                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10458                         return flowtype;
10459         }
10460
10461         return RTE_ETH_FLOW_UNKNOWN;
10462 }
10463
10464 /*
10465  * On X710, performance number is far from the expectation on recent firmware
10466  * versions; on XL710, performance number is also far from the expectation on
10467  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10468  * mode is enabled and port MAC address is equal to the packet destination MAC
10469  * address. The fix for this issue may not be integrated in the following
10470  * firmware version. So the workaround in software driver is needed. It needs
10471  * to modify the initial values of 3 internal only registers for both X710 and
10472  * XL710. Note that the values for X710 or XL710 could be different, and the
10473  * workaround can be removed when it is fixed in firmware in the future.
10474  */
10475
10476 /* For both X710 and XL710 */
10477 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10478 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10479 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10480
10481 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10482 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10483
10484 /* For X722 */
10485 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10486 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10487
10488 /* For X710 */
10489 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10490 /* For XL710 */
10491 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10492 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10493
10494 /*
10495  * GL_SWR_PM_UP_THR:
10496  * The value is not impacted from the link speed, its value is set according
10497  * to the total number of ports for a better pipe-monitor configuration.
10498  */
10499 static bool
10500 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10501 {
10502 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10503                 .device_id = (dev),   \
10504                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10505
10506 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10507                 .device_id = (dev),   \
10508                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10509
10510         static const struct {
10511                 uint16_t device_id;
10512                 uint32_t val;
10513         } swr_pm_table[] = {
10514                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10515                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10516                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10517                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10518                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10519
10520                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10521                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10522                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10523                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10524                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10525                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10526                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10527         };
10528         uint32_t i;
10529
10530         if (value == NULL) {
10531                 PMD_DRV_LOG(ERR, "value is NULL");
10532                 return false;
10533         }
10534
10535         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10536                 if (hw->device_id == swr_pm_table[i].device_id) {
10537                         *value = swr_pm_table[i].val;
10538
10539                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10540                                     "value - 0x%08x",
10541                                     hw->device_id, *value);
10542                         return true;
10543                 }
10544         }
10545
10546         return false;
10547 }
10548
10549 static int
10550 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10551 {
10552         enum i40e_status_code status;
10553         struct i40e_aq_get_phy_abilities_resp phy_ab;
10554         int ret = -ENOTSUP;
10555         int retries = 0;
10556
10557         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10558                                               NULL);
10559
10560         while (status) {
10561                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10562                         status);
10563                 retries++;
10564                 rte_delay_us(100000);
10565                 if  (retries < 5)
10566                         status = i40e_aq_get_phy_capabilities(hw, false,
10567                                         true, &phy_ab, NULL);
10568                 else
10569                         return ret;
10570         }
10571         return 0;
10572 }
10573
10574 static void
10575 i40e_configure_registers(struct i40e_hw *hw)
10576 {
10577         static struct {
10578                 uint32_t addr;
10579                 uint64_t val;
10580         } reg_table[] = {
10581                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10582                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10583                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10584         };
10585         uint64_t reg;
10586         uint32_t i;
10587         int ret;
10588
10589         for (i = 0; i < RTE_DIM(reg_table); i++) {
10590                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10591                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10592                                 reg_table[i].val =
10593                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10594                         else /* For X710/XL710/XXV710 */
10595                                 if (hw->aq.fw_maj_ver < 6)
10596                                         reg_table[i].val =
10597                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10598                                 else
10599                                         reg_table[i].val =
10600                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10601                 }
10602
10603                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10604                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10605                                 reg_table[i].val =
10606                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10607                         else /* For X710/XL710/XXV710 */
10608                                 reg_table[i].val =
10609                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10610                 }
10611
10612                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10613                         uint32_t cfg_val;
10614
10615                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10616                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10617                                             "GL_SWR_PM_UP_THR value fixup",
10618                                             hw->device_id);
10619                                 continue;
10620                         }
10621
10622                         reg_table[i].val = cfg_val;
10623                 }
10624
10625                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10626                                                         &reg, NULL);
10627                 if (ret < 0) {
10628                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10629                                                         reg_table[i].addr);
10630                         break;
10631                 }
10632                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10633                                                 reg_table[i].addr, reg);
10634                 if (reg == reg_table[i].val)
10635                         continue;
10636
10637                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10638                                                 reg_table[i].val, NULL);
10639                 if (ret < 0) {
10640                         PMD_DRV_LOG(ERR,
10641                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10642                                 reg_table[i].val, reg_table[i].addr);
10643                         break;
10644                 }
10645                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10646                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10647         }
10648 }
10649
10650 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10651 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10652 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10653 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10654 static int
10655 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10656 {
10657         uint32_t reg;
10658         int ret;
10659
10660         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10661                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10662                 return -EINVAL;
10663         }
10664
10665         /* Configure for double VLAN RX stripping */
10666         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10667         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10668                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10669                 ret = i40e_aq_debug_write_register(hw,
10670                                                    I40E_VSI_TSR(vsi->vsi_id),
10671                                                    reg, NULL);
10672                 if (ret < 0) {
10673                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10674                                     vsi->vsi_id);
10675                         return I40E_ERR_CONFIG;
10676                 }
10677         }
10678
10679         /* Configure for double VLAN TX insertion */
10680         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10681         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10682                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10683                 ret = i40e_aq_debug_write_register(hw,
10684                                                    I40E_VSI_L2TAGSTXVALID(
10685                                                    vsi->vsi_id), reg, NULL);
10686                 if (ret < 0) {
10687                         PMD_DRV_LOG(ERR,
10688                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10689                                 vsi->vsi_id);
10690                         return I40E_ERR_CONFIG;
10691                 }
10692         }
10693
10694         return 0;
10695 }
10696
10697 /**
10698  * i40e_aq_add_mirror_rule
10699  * @hw: pointer to the hardware structure
10700  * @seid: VEB seid to add mirror rule to
10701  * @dst_id: destination vsi seid
10702  * @entries: Buffer which contains the entities to be mirrored
10703  * @count: number of entities contained in the buffer
10704  * @rule_id:the rule_id of the rule to be added
10705  *
10706  * Add a mirror rule for a given veb.
10707  *
10708  **/
10709 static enum i40e_status_code
10710 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10711                         uint16_t seid, uint16_t dst_id,
10712                         uint16_t rule_type, uint16_t *entries,
10713                         uint16_t count, uint16_t *rule_id)
10714 {
10715         struct i40e_aq_desc desc;
10716         struct i40e_aqc_add_delete_mirror_rule cmd;
10717         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10718                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10719                 &desc.params.raw;
10720         uint16_t buff_len;
10721         enum i40e_status_code status;
10722
10723         i40e_fill_default_direct_cmd_desc(&desc,
10724                                           i40e_aqc_opc_add_mirror_rule);
10725         memset(&cmd, 0, sizeof(cmd));
10726
10727         buff_len = sizeof(uint16_t) * count;
10728         desc.datalen = rte_cpu_to_le_16(buff_len);
10729         if (buff_len > 0)
10730                 desc.flags |= rte_cpu_to_le_16(
10731                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10732         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10733                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10734         cmd.num_entries = rte_cpu_to_le_16(count);
10735         cmd.seid = rte_cpu_to_le_16(seid);
10736         cmd.destination = rte_cpu_to_le_16(dst_id);
10737
10738         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10739         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10740         PMD_DRV_LOG(INFO,
10741                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10742                 hw->aq.asq_last_status, resp->rule_id,
10743                 resp->mirror_rules_used, resp->mirror_rules_free);
10744         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10745
10746         return status;
10747 }
10748
10749 /**
10750  * i40e_aq_del_mirror_rule
10751  * @hw: pointer to the hardware structure
10752  * @seid: VEB seid to add mirror rule to
10753  * @entries: Buffer which contains the entities to be mirrored
10754  * @count: number of entities contained in the buffer
10755  * @rule_id:the rule_id of the rule to be delete
10756  *
10757  * Delete a mirror rule for a given veb.
10758  *
10759  **/
10760 static enum i40e_status_code
10761 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10762                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10763                 uint16_t count, uint16_t rule_id)
10764 {
10765         struct i40e_aq_desc desc;
10766         struct i40e_aqc_add_delete_mirror_rule cmd;
10767         uint16_t buff_len = 0;
10768         enum i40e_status_code status;
10769         void *buff = NULL;
10770
10771         i40e_fill_default_direct_cmd_desc(&desc,
10772                                           i40e_aqc_opc_delete_mirror_rule);
10773         memset(&cmd, 0, sizeof(cmd));
10774         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10775                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10776                                                           I40E_AQ_FLAG_RD));
10777                 cmd.num_entries = count;
10778                 buff_len = sizeof(uint16_t) * count;
10779                 desc.datalen = rte_cpu_to_le_16(buff_len);
10780                 buff = (void *)entries;
10781         } else
10782                 /* rule id is filled in destination field for deleting mirror rule */
10783                 cmd.destination = rte_cpu_to_le_16(rule_id);
10784
10785         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10786                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10787         cmd.seid = rte_cpu_to_le_16(seid);
10788
10789         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10790         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10791
10792         return status;
10793 }
10794
10795 /**
10796  * i40e_mirror_rule_set
10797  * @dev: pointer to the hardware structure
10798  * @mirror_conf: mirror rule info
10799  * @sw_id: mirror rule's sw_id
10800  * @on: enable/disable
10801  *
10802  * set a mirror rule.
10803  *
10804  **/
10805 static int
10806 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10807                         struct rte_eth_mirror_conf *mirror_conf,
10808                         uint8_t sw_id, uint8_t on)
10809 {
10810         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10812         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10813         struct i40e_mirror_rule *parent = NULL;
10814         uint16_t seid, dst_seid, rule_id;
10815         uint16_t i, j = 0;
10816         int ret;
10817
10818         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10819
10820         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10821                 PMD_DRV_LOG(ERR,
10822                         "mirror rule can not be configured without veb or vfs.");
10823                 return -ENOSYS;
10824         }
10825         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10826                 PMD_DRV_LOG(ERR, "mirror table is full.");
10827                 return -ENOSPC;
10828         }
10829         if (mirror_conf->dst_pool > pf->vf_num) {
10830                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10831                                  mirror_conf->dst_pool);
10832                 return -EINVAL;
10833         }
10834
10835         seid = pf->main_vsi->veb->seid;
10836
10837         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10838                 if (sw_id <= it->index) {
10839                         mirr_rule = it;
10840                         break;
10841                 }
10842                 parent = it;
10843         }
10844         if (mirr_rule && sw_id == mirr_rule->index) {
10845                 if (on) {
10846                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10847                         return -EEXIST;
10848                 } else {
10849                         ret = i40e_aq_del_mirror_rule(hw, seid,
10850                                         mirr_rule->rule_type,
10851                                         mirr_rule->entries,
10852                                         mirr_rule->num_entries, mirr_rule->id);
10853                         if (ret < 0) {
10854                                 PMD_DRV_LOG(ERR,
10855                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10856                                         ret, hw->aq.asq_last_status);
10857                                 return -ENOSYS;
10858                         }
10859                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10860                         rte_free(mirr_rule);
10861                         pf->nb_mirror_rule--;
10862                         return 0;
10863                 }
10864         } else if (!on) {
10865                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10866                 return -ENOENT;
10867         }
10868
10869         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10870                                 sizeof(struct i40e_mirror_rule) , 0);
10871         if (!mirr_rule) {
10872                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10873                 return I40E_ERR_NO_MEMORY;
10874         }
10875         switch (mirror_conf->rule_type) {
10876         case ETH_MIRROR_VLAN:
10877                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10878                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10879                                 mirr_rule->entries[j] =
10880                                         mirror_conf->vlan.vlan_id[i];
10881                                 j++;
10882                         }
10883                 }
10884                 if (j == 0) {
10885                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10886                         rte_free(mirr_rule);
10887                         return -EINVAL;
10888                 }
10889                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10890                 break;
10891         case ETH_MIRROR_VIRTUAL_POOL_UP:
10892         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10893                 /* check if the specified pool bit is out of range */
10894                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10895                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10896                         rte_free(mirr_rule);
10897                         return -EINVAL;
10898                 }
10899                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10900                         if (mirror_conf->pool_mask & (1ULL << i)) {
10901                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10902                                 j++;
10903                         }
10904                 }
10905                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10906                         /* add pf vsi to entries */
10907                         mirr_rule->entries[j] = pf->main_vsi_seid;
10908                         j++;
10909                 }
10910                 if (j == 0) {
10911                         PMD_DRV_LOG(ERR, "pool is not specified.");
10912                         rte_free(mirr_rule);
10913                         return -EINVAL;
10914                 }
10915                 /* egress and ingress in aq commands means from switch but not port */
10916                 mirr_rule->rule_type =
10917                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10918                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10919                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10920                 break;
10921         case ETH_MIRROR_UPLINK_PORT:
10922                 /* egress and ingress in aq commands means from switch but not port*/
10923                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10924                 break;
10925         case ETH_MIRROR_DOWNLINK_PORT:
10926                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10927                 break;
10928         default:
10929                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10930                         mirror_conf->rule_type);
10931                 rte_free(mirr_rule);
10932                 return -EINVAL;
10933         }
10934
10935         /* If the dst_pool is equal to vf_num, consider it as PF */
10936         if (mirror_conf->dst_pool == pf->vf_num)
10937                 dst_seid = pf->main_vsi_seid;
10938         else
10939                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10940
10941         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10942                                       mirr_rule->rule_type, mirr_rule->entries,
10943                                       j, &rule_id);
10944         if (ret < 0) {
10945                 PMD_DRV_LOG(ERR,
10946                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10947                         ret, hw->aq.asq_last_status);
10948                 rte_free(mirr_rule);
10949                 return -ENOSYS;
10950         }
10951
10952         mirr_rule->index = sw_id;
10953         mirr_rule->num_entries = j;
10954         mirr_rule->id = rule_id;
10955         mirr_rule->dst_vsi_seid = dst_seid;
10956
10957         if (parent)
10958                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10959         else
10960                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10961
10962         pf->nb_mirror_rule++;
10963         return 0;
10964 }
10965
10966 /**
10967  * i40e_mirror_rule_reset
10968  * @dev: pointer to the device
10969  * @sw_id: mirror rule's sw_id
10970  *
10971  * reset a mirror rule.
10972  *
10973  **/
10974 static int
10975 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10976 {
10977         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10978         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10979         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10980         uint16_t seid;
10981         int ret;
10982
10983         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10984
10985         seid = pf->main_vsi->veb->seid;
10986
10987         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10988                 if (sw_id == it->index) {
10989                         mirr_rule = it;
10990                         break;
10991                 }
10992         }
10993         if (mirr_rule) {
10994                 ret = i40e_aq_del_mirror_rule(hw, seid,
10995                                 mirr_rule->rule_type,
10996                                 mirr_rule->entries,
10997                                 mirr_rule->num_entries, mirr_rule->id);
10998                 if (ret < 0) {
10999                         PMD_DRV_LOG(ERR,
11000                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11001                                 ret, hw->aq.asq_last_status);
11002                         return -ENOSYS;
11003                 }
11004                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11005                 rte_free(mirr_rule);
11006                 pf->nb_mirror_rule--;
11007         } else {
11008                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11009                 return -ENOENT;
11010         }
11011         return 0;
11012 }
11013
11014 static uint64_t
11015 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11016 {
11017         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11018         uint64_t systim_cycles;
11019
11020         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11021         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11022                         << 32;
11023
11024         return systim_cycles;
11025 }
11026
11027 static uint64_t
11028 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11029 {
11030         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11031         uint64_t rx_tstamp;
11032
11033         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11034         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11035                         << 32;
11036
11037         return rx_tstamp;
11038 }
11039
11040 static uint64_t
11041 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11042 {
11043         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11044         uint64_t tx_tstamp;
11045
11046         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11047         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11048                         << 32;
11049
11050         return tx_tstamp;
11051 }
11052
11053 static void
11054 i40e_start_timecounters(struct rte_eth_dev *dev)
11055 {
11056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11057         struct i40e_adapter *adapter = dev->data->dev_private;
11058         struct rte_eth_link link;
11059         uint32_t tsync_inc_l;
11060         uint32_t tsync_inc_h;
11061
11062         /* Get current link speed. */
11063         i40e_dev_link_update(dev, 1);
11064         rte_eth_linkstatus_get(dev, &link);
11065
11066         switch (link.link_speed) {
11067         case ETH_SPEED_NUM_40G:
11068         case ETH_SPEED_NUM_25G:
11069                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11070                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11071                 break;
11072         case ETH_SPEED_NUM_10G:
11073                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11074                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11075                 break;
11076         case ETH_SPEED_NUM_1G:
11077                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11078                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11079                 break;
11080         default:
11081                 tsync_inc_l = 0x0;
11082                 tsync_inc_h = 0x0;
11083         }
11084
11085         /* Set the timesync increment value. */
11086         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11087         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11088
11089         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11090         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11091         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11092
11093         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11094         adapter->systime_tc.cc_shift = 0;
11095         adapter->systime_tc.nsec_mask = 0;
11096
11097         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11098         adapter->rx_tstamp_tc.cc_shift = 0;
11099         adapter->rx_tstamp_tc.nsec_mask = 0;
11100
11101         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11102         adapter->tx_tstamp_tc.cc_shift = 0;
11103         adapter->tx_tstamp_tc.nsec_mask = 0;
11104 }
11105
11106 static int
11107 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11108 {
11109         struct i40e_adapter *adapter = dev->data->dev_private;
11110
11111         adapter->systime_tc.nsec += delta;
11112         adapter->rx_tstamp_tc.nsec += delta;
11113         adapter->tx_tstamp_tc.nsec += delta;
11114
11115         return 0;
11116 }
11117
11118 static int
11119 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11120 {
11121         uint64_t ns;
11122         struct i40e_adapter *adapter = dev->data->dev_private;
11123
11124         ns = rte_timespec_to_ns(ts);
11125
11126         /* Set the timecounters to a new value. */
11127         adapter->systime_tc.nsec = ns;
11128         adapter->rx_tstamp_tc.nsec = ns;
11129         adapter->tx_tstamp_tc.nsec = ns;
11130
11131         return 0;
11132 }
11133
11134 static int
11135 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11136 {
11137         uint64_t ns, systime_cycles;
11138         struct i40e_adapter *adapter = dev->data->dev_private;
11139
11140         systime_cycles = i40e_read_systime_cyclecounter(dev);
11141         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11142         *ts = rte_ns_to_timespec(ns);
11143
11144         return 0;
11145 }
11146
11147 static int
11148 i40e_timesync_enable(struct rte_eth_dev *dev)
11149 {
11150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11151         uint32_t tsync_ctl_l;
11152         uint32_t tsync_ctl_h;
11153
11154         /* Stop the timesync system time. */
11155         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11156         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11157         /* Reset the timesync system time value. */
11158         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11159         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11160
11161         i40e_start_timecounters(dev);
11162
11163         /* Clear timesync registers. */
11164         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11165         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11166         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11167         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11168         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11169         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11170
11171         /* Enable timestamping of PTP packets. */
11172         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11173         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11174
11175         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11176         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11177         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11178
11179         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11180         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11181
11182         return 0;
11183 }
11184
11185 static int
11186 i40e_timesync_disable(struct rte_eth_dev *dev)
11187 {
11188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11189         uint32_t tsync_ctl_l;
11190         uint32_t tsync_ctl_h;
11191
11192         /* Disable timestamping of transmitted PTP packets. */
11193         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11194         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11195
11196         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11197         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11198
11199         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11200         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11201
11202         /* Reset the timesync increment value. */
11203         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11204         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11205
11206         return 0;
11207 }
11208
11209 static int
11210 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11211                                 struct timespec *timestamp, uint32_t flags)
11212 {
11213         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11214         struct i40e_adapter *adapter = dev->data->dev_private;
11215         uint32_t sync_status;
11216         uint32_t index = flags & 0x03;
11217         uint64_t rx_tstamp_cycles;
11218         uint64_t ns;
11219
11220         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11221         if ((sync_status & (1 << index)) == 0)
11222                 return -EINVAL;
11223
11224         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11225         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11226         *timestamp = rte_ns_to_timespec(ns);
11227
11228         return 0;
11229 }
11230
11231 static int
11232 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11233                                 struct timespec *timestamp)
11234 {
11235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11236         struct i40e_adapter *adapter = dev->data->dev_private;
11237         uint32_t sync_status;
11238         uint64_t tx_tstamp_cycles;
11239         uint64_t ns;
11240
11241         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11242         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11243                 return -EINVAL;
11244
11245         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11246         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11247         *timestamp = rte_ns_to_timespec(ns);
11248
11249         return 0;
11250 }
11251
11252 /*
11253  * i40e_parse_dcb_configure - parse dcb configure from user
11254  * @dev: the device being configured
11255  * @dcb_cfg: pointer of the result of parse
11256  * @*tc_map: bit map of enabled traffic classes
11257  *
11258  * Returns 0 on success, negative value on failure
11259  */
11260 static int
11261 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11262                          struct i40e_dcbx_config *dcb_cfg,
11263                          uint8_t *tc_map)
11264 {
11265         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11266         uint8_t i, tc_bw, bw_lf;
11267
11268         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11269
11270         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11271         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11272                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11273                 return -EINVAL;
11274         }
11275
11276         /* assume each tc has the same bw */
11277         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11278         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11279                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11280         /* to ensure the sum of tcbw is equal to 100 */
11281         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11282         for (i = 0; i < bw_lf; i++)
11283                 dcb_cfg->etscfg.tcbwtable[i]++;
11284
11285         /* assume each tc has the same Transmission Selection Algorithm */
11286         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11287                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11288
11289         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11290                 dcb_cfg->etscfg.prioritytable[i] =
11291                                 dcb_rx_conf->dcb_tc[i];
11292
11293         /* FW needs one App to configure HW */
11294         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11295         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11296         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11297         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11298
11299         if (dcb_rx_conf->nb_tcs == 0)
11300                 *tc_map = 1; /* tc0 only */
11301         else
11302                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11303
11304         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11305                 dcb_cfg->pfc.willing = 0;
11306                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11307                 dcb_cfg->pfc.pfcenable = *tc_map;
11308         }
11309         return 0;
11310 }
11311
11312
11313 static enum i40e_status_code
11314 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11315                               struct i40e_aqc_vsi_properties_data *info,
11316                               uint8_t enabled_tcmap)
11317 {
11318         enum i40e_status_code ret;
11319         int i, total_tc = 0;
11320         uint16_t qpnum_per_tc, bsf, qp_idx;
11321         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11322         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11323         uint16_t used_queues;
11324
11325         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11326         if (ret != I40E_SUCCESS)
11327                 return ret;
11328
11329         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11330                 if (enabled_tcmap & (1 << i))
11331                         total_tc++;
11332         }
11333         if (total_tc == 0)
11334                 total_tc = 1;
11335         vsi->enabled_tc = enabled_tcmap;
11336
11337         /* different VSI has different queues assigned */
11338         if (vsi->type == I40E_VSI_MAIN)
11339                 used_queues = dev_data->nb_rx_queues -
11340                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11341         else if (vsi->type == I40E_VSI_VMDQ2)
11342                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11343         else {
11344                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11345                 return I40E_ERR_NO_AVAILABLE_VSI;
11346         }
11347
11348         qpnum_per_tc = used_queues / total_tc;
11349         /* Number of queues per enabled TC */
11350         if (qpnum_per_tc == 0) {
11351                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11352                 return I40E_ERR_INVALID_QP_ID;
11353         }
11354         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11355                                 I40E_MAX_Q_PER_TC);
11356         bsf = rte_bsf32(qpnum_per_tc);
11357
11358         /**
11359          * Configure TC and queue mapping parameters, for enabled TC,
11360          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11361          * default queue will serve it.
11362          */
11363         qp_idx = 0;
11364         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11365                 if (vsi->enabled_tc & (1 << i)) {
11366                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11367                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11368                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11369                         qp_idx += qpnum_per_tc;
11370                 } else
11371                         info->tc_mapping[i] = 0;
11372         }
11373
11374         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11375         if (vsi->type == I40E_VSI_SRIOV) {
11376                 info->mapping_flags |=
11377                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11378                 for (i = 0; i < vsi->nb_qps; i++)
11379                         info->queue_mapping[i] =
11380                                 rte_cpu_to_le_16(vsi->base_queue + i);
11381         } else {
11382                 info->mapping_flags |=
11383                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11384                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11385         }
11386         info->valid_sections |=
11387                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11388
11389         return I40E_SUCCESS;
11390 }
11391
11392 /*
11393  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11394  * @veb: VEB to be configured
11395  * @tc_map: enabled TC bitmap
11396  *
11397  * Returns 0 on success, negative value on failure
11398  */
11399 static enum i40e_status_code
11400 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11401 {
11402         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11403         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11404         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11405         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11406         enum i40e_status_code ret = I40E_SUCCESS;
11407         int i;
11408         uint32_t bw_max;
11409
11410         /* Check if enabled_tc is same as existing or new TCs */
11411         if (veb->enabled_tc == tc_map)
11412                 return ret;
11413
11414         /* configure tc bandwidth */
11415         memset(&veb_bw, 0, sizeof(veb_bw));
11416         veb_bw.tc_valid_bits = tc_map;
11417         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11418         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11419                 if (tc_map & BIT_ULL(i))
11420                         veb_bw.tc_bw_share_credits[i] = 1;
11421         }
11422         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11423                                                    &veb_bw, NULL);
11424         if (ret) {
11425                 PMD_INIT_LOG(ERR,
11426                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11427                         hw->aq.asq_last_status);
11428                 return ret;
11429         }
11430
11431         memset(&ets_query, 0, sizeof(ets_query));
11432         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11433                                                    &ets_query, NULL);
11434         if (ret != I40E_SUCCESS) {
11435                 PMD_DRV_LOG(ERR,
11436                         "Failed to get switch_comp ETS configuration %u",
11437                         hw->aq.asq_last_status);
11438                 return ret;
11439         }
11440         memset(&bw_query, 0, sizeof(bw_query));
11441         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11442                                                   &bw_query, NULL);
11443         if (ret != I40E_SUCCESS) {
11444                 PMD_DRV_LOG(ERR,
11445                         "Failed to get switch_comp bandwidth configuration %u",
11446                         hw->aq.asq_last_status);
11447                 return ret;
11448         }
11449
11450         /* store and print out BW info */
11451         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11452         veb->bw_info.bw_max = ets_query.tc_bw_max;
11453         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11454         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11455         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11456                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11457                      I40E_16_BIT_WIDTH);
11458         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11459                 veb->bw_info.bw_ets_share_credits[i] =
11460                                 bw_query.tc_bw_share_credits[i];
11461                 veb->bw_info.bw_ets_credits[i] =
11462                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11463                 /* 4 bits per TC, 4th bit is reserved */
11464                 veb->bw_info.bw_ets_max[i] =
11465                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11466                                   RTE_LEN2MASK(3, uint8_t));
11467                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11468                             veb->bw_info.bw_ets_share_credits[i]);
11469                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11470                             veb->bw_info.bw_ets_credits[i]);
11471                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11472                             veb->bw_info.bw_ets_max[i]);
11473         }
11474
11475         veb->enabled_tc = tc_map;
11476
11477         return ret;
11478 }
11479
11480
11481 /*
11482  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11483  * @vsi: VSI to be configured
11484  * @tc_map: enabled TC bitmap
11485  *
11486  * Returns 0 on success, negative value on failure
11487  */
11488 static enum i40e_status_code
11489 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11490 {
11491         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11492         struct i40e_vsi_context ctxt;
11493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11494         enum i40e_status_code ret = I40E_SUCCESS;
11495         int i;
11496
11497         /* Check if enabled_tc is same as existing or new TCs */
11498         if (vsi->enabled_tc == tc_map)
11499                 return ret;
11500
11501         /* configure tc bandwidth */
11502         memset(&bw_data, 0, sizeof(bw_data));
11503         bw_data.tc_valid_bits = tc_map;
11504         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11505         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11506                 if (tc_map & BIT_ULL(i))
11507                         bw_data.tc_bw_credits[i] = 1;
11508         }
11509         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11510         if (ret) {
11511                 PMD_INIT_LOG(ERR,
11512                         "AQ command Config VSI BW allocation per TC failed = %d",
11513                         hw->aq.asq_last_status);
11514                 goto out;
11515         }
11516         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11517                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11518
11519         /* Update Queue Pairs Mapping for currently enabled UPs */
11520         ctxt.seid = vsi->seid;
11521         ctxt.pf_num = hw->pf_id;
11522         ctxt.vf_num = 0;
11523         ctxt.uplink_seid = vsi->uplink_seid;
11524         ctxt.info = vsi->info;
11525         i40e_get_cap(hw);
11526         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11527         if (ret)
11528                 goto out;
11529
11530         /* Update the VSI after updating the VSI queue-mapping information */
11531         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11532         if (ret) {
11533                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11534                         hw->aq.asq_last_status);
11535                 goto out;
11536         }
11537         /* update the local VSI info with updated queue map */
11538         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11539                                         sizeof(vsi->info.tc_mapping));
11540         rte_memcpy(&vsi->info.queue_mapping,
11541                         &ctxt.info.queue_mapping,
11542                 sizeof(vsi->info.queue_mapping));
11543         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11544         vsi->info.valid_sections = 0;
11545
11546         /* query and update current VSI BW information */
11547         ret = i40e_vsi_get_bw_config(vsi);
11548         if (ret) {
11549                 PMD_INIT_LOG(ERR,
11550                          "Failed updating vsi bw info, err %s aq_err %s",
11551                          i40e_stat_str(hw, ret),
11552                          i40e_aq_str(hw, hw->aq.asq_last_status));
11553                 goto out;
11554         }
11555
11556         vsi->enabled_tc = tc_map;
11557
11558 out:
11559         return ret;
11560 }
11561
11562 /*
11563  * i40e_dcb_hw_configure - program the dcb setting to hw
11564  * @pf: pf the configuration is taken on
11565  * @new_cfg: new configuration
11566  * @tc_map: enabled TC bitmap
11567  *
11568  * Returns 0 on success, negative value on failure
11569  */
11570 static enum i40e_status_code
11571 i40e_dcb_hw_configure(struct i40e_pf *pf,
11572                       struct i40e_dcbx_config *new_cfg,
11573                       uint8_t tc_map)
11574 {
11575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11576         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11577         struct i40e_vsi *main_vsi = pf->main_vsi;
11578         struct i40e_vsi_list *vsi_list;
11579         enum i40e_status_code ret;
11580         int i;
11581         uint32_t val;
11582
11583         /* Use the FW API if FW > v4.4*/
11584         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11585               (hw->aq.fw_maj_ver >= 5))) {
11586                 PMD_INIT_LOG(ERR,
11587                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11588                 return I40E_ERR_FIRMWARE_API_VERSION;
11589         }
11590
11591         /* Check if need reconfiguration */
11592         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11593                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11594                 return I40E_SUCCESS;
11595         }
11596
11597         /* Copy the new config to the current config */
11598         *old_cfg = *new_cfg;
11599         old_cfg->etsrec = old_cfg->etscfg;
11600         ret = i40e_set_dcb_config(hw);
11601         if (ret) {
11602                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11603                          i40e_stat_str(hw, ret),
11604                          i40e_aq_str(hw, hw->aq.asq_last_status));
11605                 return ret;
11606         }
11607         /* set receive Arbiter to RR mode and ETS scheme by default */
11608         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11609                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11610                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11611                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11612                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11613                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11614                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11615                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11616                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11617                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11618                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11619                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11620                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11621         }
11622         /* get local mib to check whether it is configured correctly */
11623         /* IEEE mode */
11624         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11625         /* Get Local DCB Config */
11626         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11627                                      &hw->local_dcbx_config);
11628
11629         /* if Veb is created, need to update TC of it at first */
11630         if (main_vsi->veb) {
11631                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11632                 if (ret)
11633                         PMD_INIT_LOG(WARNING,
11634                                  "Failed configuring TC for VEB seid=%d",
11635                                  main_vsi->veb->seid);
11636         }
11637         /* Update each VSI */
11638         i40e_vsi_config_tc(main_vsi, tc_map);
11639         if (main_vsi->veb) {
11640                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11641                         /* Beside main VSI and VMDQ VSIs, only enable default
11642                          * TC for other VSIs
11643                          */
11644                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11645                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11646                                                          tc_map);
11647                         else
11648                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11649                                                          I40E_DEFAULT_TCMAP);
11650                         if (ret)
11651                                 PMD_INIT_LOG(WARNING,
11652                                         "Failed configuring TC for VSI seid=%d",
11653                                         vsi_list->vsi->seid);
11654                         /* continue */
11655                 }
11656         }
11657         return I40E_SUCCESS;
11658 }
11659
11660 /*
11661  * i40e_dcb_init_configure - initial dcb config
11662  * @dev: device being configured
11663  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11664  *
11665  * Returns 0 on success, negative value on failure
11666  */
11667 int
11668 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11669 {
11670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11672         int i, ret = 0;
11673
11674         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11675                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11676                 return -ENOTSUP;
11677         }
11678
11679         /* DCB initialization:
11680          * Update DCB configuration from the Firmware and configure
11681          * LLDP MIB change event.
11682          */
11683         if (sw_dcb == TRUE) {
11684                 /* Stopping lldp is necessary for DPDK, but it will cause
11685                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11686                  * for successful initialization of DCB is that LLDP is
11687                  * enabled. So it is needed to start lldp before DCB init
11688                  * and stop it after initialization.
11689                  */
11690                 ret = i40e_aq_start_lldp(hw, true, NULL);
11691                 if (ret != I40E_SUCCESS)
11692                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11693
11694                 ret = i40e_init_dcb(hw, true);
11695                 /* If lldp agent is stopped, the return value from
11696                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11697                  * adminq status. Otherwise, it should return success.
11698                  */
11699                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11700                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11701                         memset(&hw->local_dcbx_config, 0,
11702                                 sizeof(struct i40e_dcbx_config));
11703                         /* set dcb default configuration */
11704                         hw->local_dcbx_config.etscfg.willing = 0;
11705                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11706                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11707                         hw->local_dcbx_config.etscfg.tsatable[0] =
11708                                                 I40E_IEEE_TSA_ETS;
11709                         /* all UPs mapping to TC0 */
11710                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11711                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11712                         hw->local_dcbx_config.etsrec =
11713                                 hw->local_dcbx_config.etscfg;
11714                         hw->local_dcbx_config.pfc.willing = 0;
11715                         hw->local_dcbx_config.pfc.pfccap =
11716                                                 I40E_MAX_TRAFFIC_CLASS;
11717                         /* FW needs one App to configure HW */
11718                         hw->local_dcbx_config.numapps = 1;
11719                         hw->local_dcbx_config.app[0].selector =
11720                                                 I40E_APP_SEL_ETHTYPE;
11721                         hw->local_dcbx_config.app[0].priority = 3;
11722                         hw->local_dcbx_config.app[0].protocolid =
11723                                                 I40E_APP_PROTOID_FCOE;
11724                         ret = i40e_set_dcb_config(hw);
11725                         if (ret) {
11726                                 PMD_INIT_LOG(ERR,
11727                                         "default dcb config fails. err = %d, aq_err = %d.",
11728                                         ret, hw->aq.asq_last_status);
11729                                 return -ENOSYS;
11730                         }
11731                 } else {
11732                         PMD_INIT_LOG(ERR,
11733                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11734                                 ret, hw->aq.asq_last_status);
11735                         return -ENOTSUP;
11736                 }
11737
11738                 if (i40e_need_stop_lldp(dev)) {
11739                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11740                         if (ret != I40E_SUCCESS)
11741                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11742                 }
11743         } else {
11744                 ret = i40e_aq_start_lldp(hw, true, NULL);
11745                 if (ret != I40E_SUCCESS)
11746                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11747
11748                 ret = i40e_init_dcb(hw, true);
11749                 if (!ret) {
11750                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11751                                 PMD_INIT_LOG(ERR,
11752                                         "HW doesn't support DCBX offload.");
11753                                 return -ENOTSUP;
11754                         }
11755                 } else {
11756                         PMD_INIT_LOG(ERR,
11757                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11758                                 ret, hw->aq.asq_last_status);
11759                         return -ENOTSUP;
11760                 }
11761         }
11762         return 0;
11763 }
11764
11765 /*
11766  * i40e_dcb_setup - setup dcb related config
11767  * @dev: device being configured
11768  *
11769  * Returns 0 on success, negative value on failure
11770  */
11771 static int
11772 i40e_dcb_setup(struct rte_eth_dev *dev)
11773 {
11774         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11775         struct i40e_dcbx_config dcb_cfg;
11776         uint8_t tc_map = 0;
11777         int ret = 0;
11778
11779         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11780                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11781                 return -ENOTSUP;
11782         }
11783
11784         if (pf->vf_num != 0)
11785                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11786
11787         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11788         if (ret) {
11789                 PMD_INIT_LOG(ERR, "invalid dcb config");
11790                 return -EINVAL;
11791         }
11792         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11793         if (ret) {
11794                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11795                 return -ENOSYS;
11796         }
11797
11798         return 0;
11799 }
11800
11801 static int
11802 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11803                       struct rte_eth_dcb_info *dcb_info)
11804 {
11805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11807         struct i40e_vsi *vsi = pf->main_vsi;
11808         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11809         uint16_t bsf, tc_mapping;
11810         int i, j = 0;
11811
11812         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11813                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11814         else
11815                 dcb_info->nb_tcs = 1;
11816         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11817                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11818         for (i = 0; i < dcb_info->nb_tcs; i++)
11819                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11820
11821         /* get queue mapping if vmdq is disabled */
11822         if (!pf->nb_cfg_vmdq_vsi) {
11823                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11824                         if (!(vsi->enabled_tc & (1 << i)))
11825                                 continue;
11826                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11827                         dcb_info->tc_queue.tc_rxq[j][i].base =
11828                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11829                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11830                         dcb_info->tc_queue.tc_txq[j][i].base =
11831                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11832                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11833                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11834                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11835                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11836                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11837                 }
11838                 return 0;
11839         }
11840
11841         /* get queue mapping if vmdq is enabled */
11842         do {
11843                 vsi = pf->vmdq[j].vsi;
11844                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11845                         if (!(vsi->enabled_tc & (1 << i)))
11846                                 continue;
11847                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11848                         dcb_info->tc_queue.tc_rxq[j][i].base =
11849                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11850                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11851                         dcb_info->tc_queue.tc_txq[j][i].base =
11852                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11853                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11854                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11855                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11856                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11857                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11858                 }
11859                 j++;
11860         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11861         return 0;
11862 }
11863
11864 static int
11865 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11866 {
11867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11870         uint16_t msix_intr;
11871
11872         msix_intr = intr_handle->intr_vec[queue_id];
11873         if (msix_intr == I40E_MISC_VEC_ID)
11874                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11875                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11876                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11877                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11878         else
11879                 I40E_WRITE_REG(hw,
11880                                I40E_PFINT_DYN_CTLN(msix_intr -
11881                                                    I40E_RX_VEC_START),
11882                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11883                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11884                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11885
11886         I40E_WRITE_FLUSH(hw);
11887         rte_intr_ack(&pci_dev->intr_handle);
11888
11889         return 0;
11890 }
11891
11892 static int
11893 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11894 {
11895         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11896         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11898         uint16_t msix_intr;
11899
11900         msix_intr = intr_handle->intr_vec[queue_id];
11901         if (msix_intr == I40E_MISC_VEC_ID)
11902                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11903                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11904         else
11905                 I40E_WRITE_REG(hw,
11906                                I40E_PFINT_DYN_CTLN(msix_intr -
11907                                                    I40E_RX_VEC_START),
11908                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11909         I40E_WRITE_FLUSH(hw);
11910
11911         return 0;
11912 }
11913
11914 /**
11915  * This function is used to check if the register is valid.
11916  * Below is the valid registers list for X722 only:
11917  * 0x2b800--0x2bb00
11918  * 0x38700--0x38a00
11919  * 0x3d800--0x3db00
11920  * 0x208e00--0x209000
11921  * 0x20be00--0x20c000
11922  * 0x263c00--0x264000
11923  * 0x265c00--0x266000
11924  */
11925 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11926 {
11927         if ((type != I40E_MAC_X722) &&
11928             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11929              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11930              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11931              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11932              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11933              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11934              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11935                 return 0;
11936         else
11937                 return 1;
11938 }
11939
11940 static int i40e_get_regs(struct rte_eth_dev *dev,
11941                          struct rte_dev_reg_info *regs)
11942 {
11943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11944         uint32_t *ptr_data = regs->data;
11945         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11946         const struct i40e_reg_info *reg_info;
11947
11948         if (ptr_data == NULL) {
11949                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11950                 regs->width = sizeof(uint32_t);
11951                 return 0;
11952         }
11953
11954         /* The first few registers have to be read using AQ operations */
11955         reg_idx = 0;
11956         while (i40e_regs_adminq[reg_idx].name) {
11957                 reg_info = &i40e_regs_adminq[reg_idx++];
11958                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11959                         for (arr_idx2 = 0;
11960                                         arr_idx2 <= reg_info->count2;
11961                                         arr_idx2++) {
11962                                 reg_offset = arr_idx * reg_info->stride1 +
11963                                         arr_idx2 * reg_info->stride2;
11964                                 reg_offset += reg_info->base_addr;
11965                                 ptr_data[reg_offset >> 2] =
11966                                         i40e_read_rx_ctl(hw, reg_offset);
11967                         }
11968         }
11969
11970         /* The remaining registers can be read using primitives */
11971         reg_idx = 0;
11972         while (i40e_regs_others[reg_idx].name) {
11973                 reg_info = &i40e_regs_others[reg_idx++];
11974                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11975                         for (arr_idx2 = 0;
11976                                         arr_idx2 <= reg_info->count2;
11977                                         arr_idx2++) {
11978                                 reg_offset = arr_idx * reg_info->stride1 +
11979                                         arr_idx2 * reg_info->stride2;
11980                                 reg_offset += reg_info->base_addr;
11981                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11982                                         ptr_data[reg_offset >> 2] = 0;
11983                                 else
11984                                         ptr_data[reg_offset >> 2] =
11985                                                 I40E_READ_REG(hw, reg_offset);
11986                         }
11987         }
11988
11989         return 0;
11990 }
11991
11992 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11993 {
11994         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11995
11996         /* Convert word count to byte count */
11997         return hw->nvm.sr_size << 1;
11998 }
11999
12000 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12001                            struct rte_dev_eeprom_info *eeprom)
12002 {
12003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12004         uint16_t *data = eeprom->data;
12005         uint16_t offset, length, cnt_words;
12006         int ret_code;
12007
12008         offset = eeprom->offset >> 1;
12009         length = eeprom->length >> 1;
12010         cnt_words = length;
12011
12012         if (offset > hw->nvm.sr_size ||
12013                 offset + length > hw->nvm.sr_size) {
12014                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12015                 return -EINVAL;
12016         }
12017
12018         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12019
12020         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12021         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12022                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12023                 return -EIO;
12024         }
12025
12026         return 0;
12027 }
12028
12029 static int i40e_get_module_info(struct rte_eth_dev *dev,
12030                                 struct rte_eth_dev_module_info *modinfo)
12031 {
12032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12033         uint32_t sff8472_comp = 0;
12034         uint32_t sff8472_swap = 0;
12035         uint32_t sff8636_rev = 0;
12036         i40e_status status;
12037         uint32_t type = 0;
12038
12039         /* Check if firmware supports reading module EEPROM. */
12040         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12041                 PMD_DRV_LOG(ERR,
12042                             "Module EEPROM memory read not supported. "
12043                             "Please update the NVM image.\n");
12044                 return -EINVAL;
12045         }
12046
12047         status = i40e_update_link_info(hw);
12048         if (status)
12049                 return -EIO;
12050
12051         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12052                 PMD_DRV_LOG(ERR,
12053                             "Cannot read module EEPROM memory. "
12054                             "No module connected.\n");
12055                 return -EINVAL;
12056         }
12057
12058         type = hw->phy.link_info.module_type[0];
12059
12060         switch (type) {
12061         case I40E_MODULE_TYPE_SFP:
12062                 status = i40e_aq_get_phy_register(hw,
12063                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12064                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12065                                 I40E_MODULE_SFF_8472_COMP,
12066                                 &sff8472_comp, NULL);
12067                 if (status)
12068                         return -EIO;
12069
12070                 status = i40e_aq_get_phy_register(hw,
12071                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12072                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12073                                 I40E_MODULE_SFF_8472_SWAP,
12074                                 &sff8472_swap, NULL);
12075                 if (status)
12076                         return -EIO;
12077
12078                 /* Check if the module requires address swap to access
12079                  * the other EEPROM memory page.
12080                  */
12081                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12082                         PMD_DRV_LOG(WARNING,
12083                                     "Module address swap to access "
12084                                     "page 0xA2 is not supported.\n");
12085                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12086                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12087                 } else if (sff8472_comp == 0x00) {
12088                         /* Module is not SFF-8472 compliant */
12089                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12090                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12091                 } else {
12092                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12093                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12094                 }
12095                 break;
12096         case I40E_MODULE_TYPE_QSFP_PLUS:
12097                 /* Read from memory page 0. */
12098                 status = i40e_aq_get_phy_register(hw,
12099                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12100                                 0, 1,
12101                                 I40E_MODULE_REVISION_ADDR,
12102                                 &sff8636_rev, NULL);
12103                 if (status)
12104                         return -EIO;
12105                 /* Determine revision compliance byte */
12106                 if (sff8636_rev > 0x02) {
12107                         /* Module is SFF-8636 compliant */
12108                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12109                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12110                 } else {
12111                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12112                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12113                 }
12114                 break;
12115         case I40E_MODULE_TYPE_QSFP28:
12116                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12117                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12118                 break;
12119         default:
12120                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12121                 return -EINVAL;
12122         }
12123         return 0;
12124 }
12125
12126 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12127                                   struct rte_dev_eeprom_info *info)
12128 {
12129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12130         bool is_sfp = false;
12131         i40e_status status;
12132         uint8_t *data;
12133         uint32_t value = 0;
12134         uint32_t i;
12135
12136         if (!info || !info->length || !info->data)
12137                 return -EINVAL;
12138
12139         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12140                 is_sfp = true;
12141
12142         data = info->data;
12143         for (i = 0; i < info->length; i++) {
12144                 u32 offset = i + info->offset;
12145                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12146
12147                 /* Check if we need to access the other memory page */
12148                 if (is_sfp) {
12149                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12150                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12151                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12152                         }
12153                 } else {
12154                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12155                                 /* Compute memory page number and offset. */
12156                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12157                                 addr++;
12158                         }
12159                 }
12160                 status = i40e_aq_get_phy_register(hw,
12161                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12162                                 addr, offset, 1, &value, NULL);
12163                 if (status)
12164                         return -EIO;
12165                 data[i] = (uint8_t)value;
12166         }
12167         return 0;
12168 }
12169
12170 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12171                                      struct rte_ether_addr *mac_addr)
12172 {
12173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12175         struct i40e_vsi *vsi = pf->main_vsi;
12176         struct i40e_mac_filter_info mac_filter;
12177         struct i40e_mac_filter *f;
12178         int ret;
12179
12180         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12181                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12182                 return -EINVAL;
12183         }
12184
12185         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12186                 if (rte_is_same_ether_addr(&pf->dev_addr,
12187                                                 &f->mac_info.mac_addr))
12188                         break;
12189         }
12190
12191         if (f == NULL) {
12192                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12193                 return -EIO;
12194         }
12195
12196         mac_filter = f->mac_info;
12197         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12198         if (ret != I40E_SUCCESS) {
12199                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12200                 return -EIO;
12201         }
12202         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12203         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12204         if (ret != I40E_SUCCESS) {
12205                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12206                 return -EIO;
12207         }
12208         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12209
12210         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12211                                         mac_addr->addr_bytes, NULL);
12212         if (ret != I40E_SUCCESS) {
12213                 PMD_DRV_LOG(ERR, "Failed to change mac");
12214                 return -EIO;
12215         }
12216
12217         return 0;
12218 }
12219
12220 static int
12221 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12222 {
12223         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12224         struct rte_eth_dev_data *dev_data = pf->dev_data;
12225         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12226         int ret = 0;
12227
12228         /* check if mtu is within the allowed range */
12229         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12230                 return -EINVAL;
12231
12232         /* mtu setting is forbidden if port is start */
12233         if (dev_data->dev_started) {
12234                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12235                             dev_data->port_id);
12236                 return -EBUSY;
12237         }
12238
12239         if (frame_size > RTE_ETHER_MAX_LEN)
12240                 dev_data->dev_conf.rxmode.offloads |=
12241                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12242         else
12243                 dev_data->dev_conf.rxmode.offloads &=
12244                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12245
12246         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12247
12248         return ret;
12249 }
12250
12251 /* Restore ethertype filter */
12252 static void
12253 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12254 {
12255         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12256         struct i40e_ethertype_filter_list
12257                 *ethertype_list = &pf->ethertype.ethertype_list;
12258         struct i40e_ethertype_filter *f;
12259         struct i40e_control_filter_stats stats;
12260         uint16_t flags;
12261
12262         TAILQ_FOREACH(f, ethertype_list, rules) {
12263                 flags = 0;
12264                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12265                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12266                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12267                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12268                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12269
12270                 memset(&stats, 0, sizeof(stats));
12271                 i40e_aq_add_rem_control_packet_filter(hw,
12272                                             f->input.mac_addr.addr_bytes,
12273                                             f->input.ether_type,
12274                                             flags, pf->main_vsi->seid,
12275                                             f->queue, 1, &stats, NULL);
12276         }
12277         PMD_DRV_LOG(INFO, "Ethertype filter:"
12278                     " mac_etype_used = %u, etype_used = %u,"
12279                     " mac_etype_free = %u, etype_free = %u",
12280                     stats.mac_etype_used, stats.etype_used,
12281                     stats.mac_etype_free, stats.etype_free);
12282 }
12283
12284 /* Restore tunnel filter */
12285 static void
12286 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12287 {
12288         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12289         struct i40e_vsi *vsi;
12290         struct i40e_pf_vf *vf;
12291         struct i40e_tunnel_filter_list
12292                 *tunnel_list = &pf->tunnel.tunnel_list;
12293         struct i40e_tunnel_filter *f;
12294         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12295         bool big_buffer = 0;
12296
12297         TAILQ_FOREACH(f, tunnel_list, rules) {
12298                 if (!f->is_to_vf)
12299                         vsi = pf->main_vsi;
12300                 else {
12301                         vf = &pf->vfs[f->vf_id];
12302                         vsi = vf->vsi;
12303                 }
12304                 memset(&cld_filter, 0, sizeof(cld_filter));
12305                 rte_ether_addr_copy((struct rte_ether_addr *)
12306                                 &f->input.outer_mac,
12307                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12308                 rte_ether_addr_copy((struct rte_ether_addr *)
12309                                 &f->input.inner_mac,
12310                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12311                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12312                 cld_filter.element.flags = f->input.flags;
12313                 cld_filter.element.tenant_id = f->input.tenant_id;
12314                 cld_filter.element.queue_number = f->queue;
12315                 rte_memcpy(cld_filter.general_fields,
12316                            f->input.general_fields,
12317                            sizeof(f->input.general_fields));
12318
12319                 if (((f->input.flags &
12320                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12321                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12322                     ((f->input.flags &
12323                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12324                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12325                     ((f->input.flags &
12326                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12327                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12328                         big_buffer = 1;
12329
12330                 if (big_buffer)
12331                         i40e_aq_add_cloud_filters_bb(hw,
12332                                         vsi->seid, &cld_filter, 1);
12333                 else
12334                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12335                                                   &cld_filter.element, 1);
12336         }
12337 }
12338
12339 /* Restore RSS filter */
12340 static inline void
12341 i40e_rss_filter_restore(struct i40e_pf *pf)
12342 {
12343         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12344         struct i40e_rss_filter *filter;
12345
12346         TAILQ_FOREACH(filter, list, next) {
12347                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12348         }
12349 }
12350
12351 static void
12352 i40e_filter_restore(struct i40e_pf *pf)
12353 {
12354         i40e_ethertype_filter_restore(pf);
12355         i40e_tunnel_filter_restore(pf);
12356         i40e_fdir_filter_restore(pf);
12357         i40e_rss_filter_restore(pf);
12358 }
12359
12360 bool
12361 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12362 {
12363         if (strcmp(dev->device->driver->name, drv->driver.name))
12364                 return false;
12365
12366         return true;
12367 }
12368
12369 bool
12370 is_i40e_supported(struct rte_eth_dev *dev)
12371 {
12372         return is_device_supported(dev, &rte_i40e_pmd);
12373 }
12374
12375 struct i40e_customized_pctype*
12376 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12377 {
12378         int i;
12379
12380         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12381                 if (pf->customized_pctype[i].index == index)
12382                         return &pf->customized_pctype[i];
12383         }
12384         return NULL;
12385 }
12386
12387 static int
12388 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12389                               uint32_t pkg_size, uint32_t proto_num,
12390                               struct rte_pmd_i40e_proto_info *proto,
12391                               enum rte_pmd_i40e_package_op op)
12392 {
12393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12394         uint32_t pctype_num;
12395         struct rte_pmd_i40e_ptype_info *pctype;
12396         uint32_t buff_size;
12397         struct i40e_customized_pctype *new_pctype = NULL;
12398         uint8_t proto_id;
12399         uint8_t pctype_value;
12400         char name[64];
12401         uint32_t i, j, n;
12402         int ret;
12403
12404         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12405             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12406                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12407                 return -1;
12408         }
12409
12410         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12411                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12412                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12413         if (ret) {
12414                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12415                 return -1;
12416         }
12417         if (!pctype_num) {
12418                 PMD_DRV_LOG(INFO, "No new pctype added");
12419                 return -1;
12420         }
12421
12422         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12423         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12424         if (!pctype) {
12425                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12426                 return -1;
12427         }
12428         /* get information about new pctype list */
12429         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12430                                         (uint8_t *)pctype, buff_size,
12431                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12432         if (ret) {
12433                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12434                 rte_free(pctype);
12435                 return -1;
12436         }
12437
12438         /* Update customized pctype. */
12439         for (i = 0; i < pctype_num; i++) {
12440                 pctype_value = pctype[i].ptype_id;
12441                 memset(name, 0, sizeof(name));
12442                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12443                         proto_id = pctype[i].protocols[j];
12444                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12445                                 continue;
12446                         for (n = 0; n < proto_num; n++) {
12447                                 if (proto[n].proto_id != proto_id)
12448                                         continue;
12449                                 strlcat(name, proto[n].name, sizeof(name));
12450                                 strlcat(name, "_", sizeof(name));
12451                                 break;
12452                         }
12453                 }
12454                 name[strlen(name) - 1] = '\0';
12455                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12456                 if (!strcmp(name, "GTPC"))
12457                         new_pctype =
12458                                 i40e_find_customized_pctype(pf,
12459                                                       I40E_CUSTOMIZED_GTPC);
12460                 else if (!strcmp(name, "GTPU_IPV4"))
12461                         new_pctype =
12462                                 i40e_find_customized_pctype(pf,
12463                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12464                 else if (!strcmp(name, "GTPU_IPV6"))
12465                         new_pctype =
12466                                 i40e_find_customized_pctype(pf,
12467                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12468                 else if (!strcmp(name, "GTPU"))
12469                         new_pctype =
12470                                 i40e_find_customized_pctype(pf,
12471                                                       I40E_CUSTOMIZED_GTPU);
12472                 else if (!strcmp(name, "IPV4_L2TPV3"))
12473                         new_pctype =
12474                                 i40e_find_customized_pctype(pf,
12475                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12476                 else if (!strcmp(name, "IPV6_L2TPV3"))
12477                         new_pctype =
12478                                 i40e_find_customized_pctype(pf,
12479                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12480                 else if (!strcmp(name, "IPV4_ESP"))
12481                         new_pctype =
12482                                 i40e_find_customized_pctype(pf,
12483                                                 I40E_CUSTOMIZED_ESP_IPV4);
12484                 else if (!strcmp(name, "IPV6_ESP"))
12485                         new_pctype =
12486                                 i40e_find_customized_pctype(pf,
12487                                                 I40E_CUSTOMIZED_ESP_IPV6);
12488                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12489                         new_pctype =
12490                                 i40e_find_customized_pctype(pf,
12491                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12492                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12493                         new_pctype =
12494                                 i40e_find_customized_pctype(pf,
12495                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12496                 else if (!strcmp(name, "IPV4_AH"))
12497                         new_pctype =
12498                                 i40e_find_customized_pctype(pf,
12499                                                 I40E_CUSTOMIZED_AH_IPV4);
12500                 else if (!strcmp(name, "IPV6_AH"))
12501                         new_pctype =
12502                                 i40e_find_customized_pctype(pf,
12503                                                 I40E_CUSTOMIZED_AH_IPV6);
12504                 if (new_pctype) {
12505                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12506                                 new_pctype->pctype = pctype_value;
12507                                 new_pctype->valid = true;
12508                         } else {
12509                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12510                                 new_pctype->valid = false;
12511                         }
12512                 }
12513         }
12514
12515         rte_free(pctype);
12516         return 0;
12517 }
12518
12519 static int
12520 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12521                              uint32_t pkg_size, uint32_t proto_num,
12522                              struct rte_pmd_i40e_proto_info *proto,
12523                              enum rte_pmd_i40e_package_op op)
12524 {
12525         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12526         uint16_t port_id = dev->data->port_id;
12527         uint32_t ptype_num;
12528         struct rte_pmd_i40e_ptype_info *ptype;
12529         uint32_t buff_size;
12530         uint8_t proto_id;
12531         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12532         uint32_t i, j, n;
12533         bool in_tunnel;
12534         int ret;
12535
12536         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12537             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12538                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12539                 return -1;
12540         }
12541
12542         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12543                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12544                 return 0;
12545         }
12546
12547         /* get information about new ptype num */
12548         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12549                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12550                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12551         if (ret) {
12552                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12553                 return ret;
12554         }
12555         if (!ptype_num) {
12556                 PMD_DRV_LOG(INFO, "No new ptype added");
12557                 return -1;
12558         }
12559
12560         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12561         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12562         if (!ptype) {
12563                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12564                 return -1;
12565         }
12566
12567         /* get information about new ptype list */
12568         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12569                                         (uint8_t *)ptype, buff_size,
12570                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12571         if (ret) {
12572                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12573                 rte_free(ptype);
12574                 return ret;
12575         }
12576
12577         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12578         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12579         if (!ptype_mapping) {
12580                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12581                 rte_free(ptype);
12582                 return -1;
12583         }
12584
12585         /* Update ptype mapping table. */
12586         for (i = 0; i < ptype_num; i++) {
12587                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12588                 ptype_mapping[i].sw_ptype = 0;
12589                 in_tunnel = false;
12590                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12591                         proto_id = ptype[i].protocols[j];
12592                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12593                                 continue;
12594                         for (n = 0; n < proto_num; n++) {
12595                                 if (proto[n].proto_id != proto_id)
12596                                         continue;
12597                                 memset(name, 0, sizeof(name));
12598                                 strcpy(name, proto[n].name);
12599                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12600                                 if (!strncasecmp(name, "PPPOE", 5))
12601                                         ptype_mapping[i].sw_ptype |=
12602                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12603                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12604                                          !in_tunnel) {
12605                                         ptype_mapping[i].sw_ptype |=
12606                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12607                                         ptype_mapping[i].sw_ptype |=
12608                                                 RTE_PTYPE_L4_FRAG;
12609                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12610                                            in_tunnel) {
12611                                         ptype_mapping[i].sw_ptype |=
12612                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12613                                         ptype_mapping[i].sw_ptype |=
12614                                                 RTE_PTYPE_INNER_L4_FRAG;
12615                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12616                                         ptype_mapping[i].sw_ptype |=
12617                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12618                                         in_tunnel = true;
12619                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12620                                            !in_tunnel)
12621                                         ptype_mapping[i].sw_ptype |=
12622                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12623                                 else if (!strncasecmp(name, "IPV4", 4) &&
12624                                          in_tunnel)
12625                                         ptype_mapping[i].sw_ptype |=
12626                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12627                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12628                                          !in_tunnel) {
12629                                         ptype_mapping[i].sw_ptype |=
12630                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12631                                         ptype_mapping[i].sw_ptype |=
12632                                                 RTE_PTYPE_L4_FRAG;
12633                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12634                                            in_tunnel) {
12635                                         ptype_mapping[i].sw_ptype |=
12636                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12637                                         ptype_mapping[i].sw_ptype |=
12638                                                 RTE_PTYPE_INNER_L4_FRAG;
12639                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12640                                         ptype_mapping[i].sw_ptype |=
12641                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12642                                         in_tunnel = true;
12643                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12644                                            !in_tunnel)
12645                                         ptype_mapping[i].sw_ptype |=
12646                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12647                                 else if (!strncasecmp(name, "IPV6", 4) &&
12648                                          in_tunnel)
12649                                         ptype_mapping[i].sw_ptype |=
12650                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12651                                 else if (!strncasecmp(name, "UDP", 3) &&
12652                                          !in_tunnel)
12653                                         ptype_mapping[i].sw_ptype |=
12654                                                 RTE_PTYPE_L4_UDP;
12655                                 else if (!strncasecmp(name, "UDP", 3) &&
12656                                          in_tunnel)
12657                                         ptype_mapping[i].sw_ptype |=
12658                                                 RTE_PTYPE_INNER_L4_UDP;
12659                                 else if (!strncasecmp(name, "TCP", 3) &&
12660                                          !in_tunnel)
12661                                         ptype_mapping[i].sw_ptype |=
12662                                                 RTE_PTYPE_L4_TCP;
12663                                 else if (!strncasecmp(name, "TCP", 3) &&
12664                                          in_tunnel)
12665                                         ptype_mapping[i].sw_ptype |=
12666                                                 RTE_PTYPE_INNER_L4_TCP;
12667                                 else if (!strncasecmp(name, "SCTP", 4) &&
12668                                          !in_tunnel)
12669                                         ptype_mapping[i].sw_ptype |=
12670                                                 RTE_PTYPE_L4_SCTP;
12671                                 else if (!strncasecmp(name, "SCTP", 4) &&
12672                                          in_tunnel)
12673                                         ptype_mapping[i].sw_ptype |=
12674                                                 RTE_PTYPE_INNER_L4_SCTP;
12675                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12676                                           !strncasecmp(name, "ICMPV6", 6)) &&
12677                                          !in_tunnel)
12678                                         ptype_mapping[i].sw_ptype |=
12679                                                 RTE_PTYPE_L4_ICMP;
12680                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12681                                           !strncasecmp(name, "ICMPV6", 6)) &&
12682                                          in_tunnel)
12683                                         ptype_mapping[i].sw_ptype |=
12684                                                 RTE_PTYPE_INNER_L4_ICMP;
12685                                 else if (!strncasecmp(name, "GTPC", 4)) {
12686                                         ptype_mapping[i].sw_ptype |=
12687                                                 RTE_PTYPE_TUNNEL_GTPC;
12688                                         in_tunnel = true;
12689                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12690                                         ptype_mapping[i].sw_ptype |=
12691                                                 RTE_PTYPE_TUNNEL_GTPU;
12692                                         in_tunnel = true;
12693                                 } else if (!strncasecmp(name, "ESP", 3)) {
12694                                         ptype_mapping[i].sw_ptype |=
12695                                                 RTE_PTYPE_TUNNEL_ESP;
12696                                         in_tunnel = true;
12697                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12698                                         ptype_mapping[i].sw_ptype |=
12699                                                 RTE_PTYPE_TUNNEL_GRENAT;
12700                                         in_tunnel = true;
12701                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12702                                            !strncasecmp(name, "L2TPV2", 6) ||
12703                                            !strncasecmp(name, "L2TPV3", 6)) {
12704                                         ptype_mapping[i].sw_ptype |=
12705                                                 RTE_PTYPE_TUNNEL_L2TP;
12706                                         in_tunnel = true;
12707                                 }
12708
12709                                 break;
12710                         }
12711                 }
12712         }
12713
12714         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12715                                                 ptype_num, 0);
12716         if (ret)
12717                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12718
12719         rte_free(ptype_mapping);
12720         rte_free(ptype);
12721         return ret;
12722 }
12723
12724 void
12725 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12726                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12727 {
12728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12729         uint32_t proto_num;
12730         struct rte_pmd_i40e_proto_info *proto;
12731         uint32_t buff_size;
12732         uint32_t i;
12733         int ret;
12734
12735         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12736             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12737                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12738                 return;
12739         }
12740
12741         /* get information about protocol number */
12742         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12743                                        (uint8_t *)&proto_num, sizeof(proto_num),
12744                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12745         if (ret) {
12746                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12747                 return;
12748         }
12749         if (!proto_num) {
12750                 PMD_DRV_LOG(INFO, "No new protocol added");
12751                 return;
12752         }
12753
12754         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12755         proto = rte_zmalloc("new_proto", buff_size, 0);
12756         if (!proto) {
12757                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12758                 return;
12759         }
12760
12761         /* get information about protocol list */
12762         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12763                                         (uint8_t *)proto, buff_size,
12764                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12765         if (ret) {
12766                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12767                 rte_free(proto);
12768                 return;
12769         }
12770
12771         /* Check if GTP is supported. */
12772         for (i = 0; i < proto_num; i++) {
12773                 if (!strncmp(proto[i].name, "GTP", 3)) {
12774                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12775                                 pf->gtp_support = true;
12776                         else
12777                                 pf->gtp_support = false;
12778                         break;
12779                 }
12780         }
12781
12782         /* Check if ESP is supported. */
12783         for (i = 0; i < proto_num; i++) {
12784                 if (!strncmp(proto[i].name, "ESP", 3)) {
12785                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12786                                 pf->esp_support = true;
12787                         else
12788                                 pf->esp_support = false;
12789                         break;
12790                 }
12791         }
12792
12793         /* Update customized pctype info */
12794         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12795                                             proto_num, proto, op);
12796         if (ret)
12797                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12798
12799         /* Update customized ptype info */
12800         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12801                                            proto_num, proto, op);
12802         if (ret)
12803                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12804
12805         rte_free(proto);
12806 }
12807
12808 /* Create a QinQ cloud filter
12809  *
12810  * The Fortville NIC has limited resources for tunnel filters,
12811  * so we can only reuse existing filters.
12812  *
12813  * In step 1 we define which Field Vector fields can be used for
12814  * filter types.
12815  * As we do not have the inner tag defined as a field,
12816  * we have to define it first, by reusing one of L1 entries.
12817  *
12818  * In step 2 we are replacing one of existing filter types with
12819  * a new one for QinQ.
12820  * As we reusing L1 and replacing L2, some of the default filter
12821  * types will disappear,which depends on L1 and L2 entries we reuse.
12822  *
12823  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12824  *
12825  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12826  *              later when we define the cloud filter.
12827  *      a.      Valid_flags.replace_cloud = 0
12828  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12829  *      c.      New_filter = 0x10
12830  *      d.      TR bit = 0xff (optional, not used here)
12831  *      e.      Buffer – 2 entries:
12832  *              i.      Byte 0 = 8 (outer vlan FV index).
12833  *                      Byte 1 = 0 (rsv)
12834  *                      Byte 2-3 = 0x0fff
12835  *              ii.     Byte 0 = 37 (inner vlan FV index).
12836  *                      Byte 1 =0 (rsv)
12837  *                      Byte 2-3 = 0x0fff
12838  *
12839  * Step 2:
12840  * 2.   Create cloud filter using two L1 filters entries: stag and
12841  *              new filter(outer vlan+ inner vlan)
12842  *      a.      Valid_flags.replace_cloud = 1
12843  *      b.      Old_filter = 1 (instead of outer IP)
12844  *      c.      New_filter = 0x10
12845  *      d.      Buffer – 2 entries:
12846  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12847  *                      Byte 1-3 = 0 (rsv)
12848  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12849  *                      Byte 9-11 = 0 (rsv)
12850  */
12851 static int
12852 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12853 {
12854         int ret = -ENOTSUP;
12855         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12856         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12857         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12858         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12859
12860         if (pf->support_multi_driver) {
12861                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12862                 return ret;
12863         }
12864
12865         /* Init */
12866         memset(&filter_replace, 0,
12867                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12868         memset(&filter_replace_buf, 0,
12869                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12870
12871         /* create L1 filter */
12872         filter_replace.old_filter_type =
12873                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12874         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12875         filter_replace.tr_bit = 0;
12876
12877         /* Prepare the buffer, 2 entries */
12878         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12879         filter_replace_buf.data[0] |=
12880                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12881         /* Field Vector 12b mask */
12882         filter_replace_buf.data[2] = 0xff;
12883         filter_replace_buf.data[3] = 0x0f;
12884         filter_replace_buf.data[4] =
12885                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12886         filter_replace_buf.data[4] |=
12887                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12888         /* Field Vector 12b mask */
12889         filter_replace_buf.data[6] = 0xff;
12890         filter_replace_buf.data[7] = 0x0f;
12891         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12892                         &filter_replace_buf);
12893         if (ret != I40E_SUCCESS)
12894                 return ret;
12895
12896         if (filter_replace.old_filter_type !=
12897             filter_replace.new_filter_type)
12898                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12899                             " original: 0x%x, new: 0x%x",
12900                             dev->device->name,
12901                             filter_replace.old_filter_type,
12902                             filter_replace.new_filter_type);
12903
12904         /* Apply the second L2 cloud filter */
12905         memset(&filter_replace, 0,
12906                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12907         memset(&filter_replace_buf, 0,
12908                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12909
12910         /* create L2 filter, input for L2 filter will be L1 filter  */
12911         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12912         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12913         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12914
12915         /* Prepare the buffer, 2 entries */
12916         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12917         filter_replace_buf.data[0] |=
12918                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12919         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12920         filter_replace_buf.data[4] |=
12921                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12922         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12923                         &filter_replace_buf);
12924         if (!ret && (filter_replace.old_filter_type !=
12925                      filter_replace.new_filter_type))
12926                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12927                             " original: 0x%x, new: 0x%x",
12928                             dev->device->name,
12929                             filter_replace.old_filter_type,
12930                             filter_replace.new_filter_type);
12931
12932         return ret;
12933 }
12934
12935 int
12936 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12937                    const struct rte_flow_action_rss *in)
12938 {
12939         if (in->key_len > RTE_DIM(out->key) ||
12940             in->queue_num > RTE_DIM(out->queue))
12941                 return -EINVAL;
12942         if (!in->key && in->key_len)
12943                 return -EINVAL;
12944         out->conf = (struct rte_flow_action_rss){
12945                 .func = in->func,
12946                 .level = in->level,
12947                 .types = in->types,
12948                 .key_len = in->key_len,
12949                 .queue_num = in->queue_num,
12950                 .queue = memcpy(out->queue, in->queue,
12951                                 sizeof(*in->queue) * in->queue_num),
12952         };
12953         if (in->key)
12954                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12955         return 0;
12956 }
12957
12958 /* Write HENA register to enable hash */
12959 static int
12960 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
12961 {
12962         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12963         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
12964         uint64_t hena;
12965         int ret;
12966
12967         ret = i40e_set_rss_key(pf->main_vsi, key,
12968                                rss_conf->conf.key_len);
12969         if (ret)
12970                 return ret;
12971
12972         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
12973         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
12974         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
12975         I40E_WRITE_FLUSH(hw);
12976
12977         return 0;
12978 }
12979
12980 /* Configure hash input set */
12981 static int
12982 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
12983 {
12984         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12985         struct rte_eth_input_set_conf conf;
12986         uint64_t mask0;
12987         int ret = 0;
12988         uint32_t j;
12989         int i;
12990         static const struct {
12991                 uint64_t type;
12992                 enum rte_eth_input_set_field field;
12993         } inset_match_table[] = {
12994                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
12995                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
12996                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
12997                         RTE_ETH_INPUT_SET_L3_DST_IP4},
12998                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
12999                         RTE_ETH_INPUT_SET_UNKNOWN},
13000                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13001                         RTE_ETH_INPUT_SET_UNKNOWN},
13002
13003                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13004                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13005                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13006                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13007                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13008                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13009                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13010                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13011
13012                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13013                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13014                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13015                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13016                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13017                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13018                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13019                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13020
13021                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13022                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13023                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13024                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13025                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13026                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13027                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13028                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13029
13030                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13031                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13032                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13033                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13034                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13035                         RTE_ETH_INPUT_SET_UNKNOWN},
13036                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13037                         RTE_ETH_INPUT_SET_UNKNOWN},
13038
13039                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13040                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13041                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13042                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13043                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13044                         RTE_ETH_INPUT_SET_UNKNOWN},
13045                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13046                         RTE_ETH_INPUT_SET_UNKNOWN},
13047
13048                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13049                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13050                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13051                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13052                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13053                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13054                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13055                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13056
13057                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13058                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13059                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13060                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13061                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13062                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13063                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13064                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13065
13066                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13067                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13068                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13069                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13070                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13071                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13072                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13073                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13074
13075                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13076                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13077                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13078                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13079                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13080                         RTE_ETH_INPUT_SET_UNKNOWN},
13081                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13082                         RTE_ETH_INPUT_SET_UNKNOWN},
13083         };
13084
13085         mask0 = types & pf->adapter->flow_types_mask;
13086         conf.op = RTE_ETH_INPUT_SET_SELECT;
13087         conf.inset_size = 0;
13088         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13089                 if (mask0 & (1ULL << i)) {
13090                         conf.flow_type = i;
13091                         break;
13092                 }
13093         }
13094
13095         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13096                 if ((types & inset_match_table[j].type) ==
13097                     inset_match_table[j].type) {
13098                         if (inset_match_table[j].field ==
13099                             RTE_ETH_INPUT_SET_UNKNOWN)
13100                                 return -EINVAL;
13101
13102                         conf.field[conf.inset_size] =
13103                                 inset_match_table[j].field;
13104                         conf.inset_size++;
13105                 }
13106         }
13107
13108         if (conf.inset_size) {
13109                 ret = i40e_hash_filter_inset_select(hw, &conf);
13110                 if (ret)
13111                         return ret;
13112         }
13113
13114         return ret;
13115 }
13116
13117 /* Look up the conflicted rule then mark it as invalid */
13118 static void
13119 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13120                 struct i40e_rte_flow_rss_conf *conf)
13121 {
13122         struct i40e_rss_filter *rss_item;
13123         uint64_t rss_inset;
13124
13125         /* Clear input set bits before comparing the pctype */
13126         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13127                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13128
13129         /* Look up the conflicted rule then mark it as invalid */
13130         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13131                 if (!rss_item->rss_filter_info.valid)
13132                         continue;
13133
13134                 if (conf->conf.queue_num &&
13135                     rss_item->rss_filter_info.conf.queue_num)
13136                         rss_item->rss_filter_info.valid = false;
13137
13138                 if (conf->conf.types &&
13139                     (rss_item->rss_filter_info.conf.types &
13140                     rss_inset) ==
13141                     (conf->conf.types & rss_inset))
13142                         rss_item->rss_filter_info.valid = false;
13143
13144                 if (conf->conf.func ==
13145                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13146                     rss_item->rss_filter_info.conf.func ==
13147                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13148                         rss_item->rss_filter_info.valid = false;
13149         }
13150 }
13151
13152 /* Configure RSS hash function */
13153 static int
13154 i40e_rss_config_hash_function(struct i40e_pf *pf,
13155                 struct i40e_rte_flow_rss_conf *conf)
13156 {
13157         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13158         uint32_t reg, i;
13159         uint64_t mask0;
13160         uint16_t j;
13161
13162         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13163                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13164                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13165                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13166                         I40E_WRITE_FLUSH(hw);
13167                         i40e_rss_mark_invalid_rule(pf, conf);
13168
13169                         return 0;
13170                 }
13171                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13172
13173                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13174                 I40E_WRITE_FLUSH(hw);
13175                 i40e_rss_mark_invalid_rule(pf, conf);
13176         } else if (conf->conf.func ==
13177                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13178                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13179
13180                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13181                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13182                         if (mask0 & (1UL << i))
13183                                 break;
13184                 }
13185
13186                 if (i == UINT64_BIT)
13187                         return -EINVAL;
13188
13189                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13190                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13191                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13192                                 i40e_write_global_rx_ctl(hw,
13193                                         I40E_GLQF_HSYM(j),
13194                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13195                 }
13196         }
13197
13198         return 0;
13199 }
13200
13201 /* Enable RSS according to the configuration */
13202 static int
13203 i40e_rss_enable_hash(struct i40e_pf *pf,
13204                 struct i40e_rte_flow_rss_conf *conf)
13205 {
13206         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13207         struct i40e_rte_flow_rss_conf rss_conf;
13208
13209         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13210                 return -ENOTSUP;
13211
13212         memset(&rss_conf, 0, sizeof(rss_conf));
13213         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13214
13215         /* Configure hash input set */
13216         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13217                 return -EINVAL;
13218
13219         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13220             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13221                 /* Random default keys */
13222                 static uint32_t rss_key_default[] = {0x6b793944,
13223                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13224                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13225                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13226
13227                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13228                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13229                                 sizeof(uint32_t);
13230                 PMD_DRV_LOG(INFO,
13231                         "No valid RSS key config for i40e, using default\n");
13232         }
13233
13234         rss_conf.conf.types |= rss_info->conf.types;
13235         i40e_rss_hash_set(pf, &rss_conf);
13236
13237         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13238                 i40e_rss_config_hash_function(pf, conf);
13239
13240         i40e_rss_mark_invalid_rule(pf, conf);
13241
13242         return 0;
13243 }
13244
13245 /* Configure RSS queue region */
13246 static int
13247 i40e_rss_config_queue_region(struct i40e_pf *pf,
13248                 struct i40e_rte_flow_rss_conf *conf)
13249 {
13250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13251         uint32_t lut = 0;
13252         uint16_t j, num;
13253         uint32_t i;
13254
13255         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13256          * It's necessary to calculate the actual PF queues that are configured.
13257          */
13258         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13259                 num = i40e_pf_calc_configured_queues_num(pf);
13260         else
13261                 num = pf->dev_data->nb_rx_queues;
13262
13263         num = RTE_MIN(num, conf->conf.queue_num);
13264         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13265                         num);
13266
13267         if (num == 0) {
13268                 PMD_DRV_LOG(ERR,
13269                         "No PF queues are configured to enable RSS for port %u",
13270                         pf->dev_data->port_id);
13271                 return -ENOTSUP;
13272         }
13273
13274         /* Fill in redirection table */
13275         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13276                 if (j == num)
13277                         j = 0;
13278                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13279                         hw->func_caps.rss_table_entry_width) - 1));
13280                 if ((i & 3) == 3)
13281                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13282         }
13283
13284         i40e_rss_mark_invalid_rule(pf, conf);
13285
13286         return 0;
13287 }
13288
13289 /* Configure RSS hash function to default */
13290 static int
13291 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13292                 struct i40e_rte_flow_rss_conf *conf)
13293 {
13294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13295         uint32_t i, reg;
13296         uint64_t mask0;
13297         uint16_t j;
13298
13299         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13300                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13301                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13302                         PMD_DRV_LOG(DEBUG,
13303                                 "Hash function already set to Toeplitz");
13304                         I40E_WRITE_FLUSH(hw);
13305
13306                         return 0;
13307                 }
13308                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13309
13310                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13311                 I40E_WRITE_FLUSH(hw);
13312         } else if (conf->conf.func ==
13313                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13314                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13315
13316                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13317                         if (mask0 & (1UL << i))
13318                                 break;
13319                 }
13320
13321                 if (i == UINT64_BIT)
13322                         return -EINVAL;
13323
13324                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13325                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13326                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13327                                 i40e_write_global_rx_ctl(hw,
13328                                         I40E_GLQF_HSYM(j),
13329                                         0);
13330                 }
13331         }
13332
13333         return 0;
13334 }
13335
13336 /* Disable RSS hash and configure default input set */
13337 static int
13338 i40e_rss_disable_hash(struct i40e_pf *pf,
13339                 struct i40e_rte_flow_rss_conf *conf)
13340 {
13341         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13342         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13343         struct i40e_rte_flow_rss_conf rss_conf;
13344         uint32_t i;
13345
13346         memset(&rss_conf, 0, sizeof(rss_conf));
13347         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13348
13349         /* Disable RSS hash */
13350         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13351         i40e_rss_hash_set(pf, &rss_conf);
13352
13353         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13354                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13355                     !(conf->conf.types & (1ULL << i)))
13356                         continue;
13357
13358                 /* Configure default input set */
13359                 struct rte_eth_input_set_conf input_conf = {
13360                         .op = RTE_ETH_INPUT_SET_SELECT,
13361                         .flow_type = i,
13362                         .inset_size = 1,
13363                 };
13364                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13365                 i40e_hash_filter_inset_select(hw, &input_conf);
13366         }
13367
13368         rss_info->conf.types = rss_conf.conf.types;
13369
13370         i40e_rss_clear_hash_function(pf, conf);
13371
13372         return 0;
13373 }
13374
13375 /* Configure RSS queue region to default */
13376 static int
13377 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13378 {
13379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13380         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13381         uint16_t queue[I40E_MAX_Q_PER_TC];
13382         uint32_t num_rxq, i;
13383         uint32_t lut = 0;
13384         uint16_t j, num;
13385
13386         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13387
13388         for (j = 0; j < num_rxq; j++)
13389                 queue[j] = j;
13390
13391         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13392          * It's necessary to calculate the actual PF queues that are configured.
13393          */
13394         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13395                 num = i40e_pf_calc_configured_queues_num(pf);
13396         else
13397                 num = pf->dev_data->nb_rx_queues;
13398
13399         num = RTE_MIN(num, num_rxq);
13400         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13401                         num);
13402
13403         if (num == 0) {
13404                 PMD_DRV_LOG(ERR,
13405                         "No PF queues are configured to enable RSS for port %u",
13406                         pf->dev_data->port_id);
13407                 return -ENOTSUP;
13408         }
13409
13410         /* Fill in redirection table */
13411         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13412                 if (j == num)
13413                         j = 0;
13414                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13415                         hw->func_caps.rss_table_entry_width) - 1));
13416                 if ((i & 3) == 3)
13417                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13418         }
13419
13420         rss_info->conf.queue_num = 0;
13421         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13422
13423         return 0;
13424 }
13425
13426 int
13427 i40e_config_rss_filter(struct i40e_pf *pf,
13428                 struct i40e_rte_flow_rss_conf *conf, bool add)
13429 {
13430         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13431         struct rte_flow_action_rss update_conf = rss_info->conf;
13432         int ret = 0;
13433
13434         if (add) {
13435                 if (conf->conf.queue_num) {
13436                         /* Configure RSS queue region */
13437                         ret = i40e_rss_config_queue_region(pf, conf);
13438                         if (ret)
13439                                 return ret;
13440
13441                         update_conf.queue_num = conf->conf.queue_num;
13442                         update_conf.queue = conf->conf.queue;
13443                 } else if (conf->conf.func ==
13444                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13445                         /* Configure hash function */
13446                         ret = i40e_rss_config_hash_function(pf, conf);
13447                         if (ret)
13448                                 return ret;
13449
13450                         update_conf.func = conf->conf.func;
13451                 } else {
13452                         /* Configure hash enable and input set */
13453                         ret = i40e_rss_enable_hash(pf, conf);
13454                         if (ret)
13455                                 return ret;
13456
13457                         update_conf.types |= conf->conf.types;
13458                         update_conf.key = conf->conf.key;
13459                         update_conf.key_len = conf->conf.key_len;
13460                 }
13461
13462                 /* Update RSS info in pf */
13463                 if (i40e_rss_conf_init(rss_info, &update_conf))
13464                         return -EINVAL;
13465         } else {
13466                 if (!conf->valid)
13467                         return 0;
13468
13469                 if (conf->conf.queue_num)
13470                         i40e_rss_clear_queue_region(pf);
13471                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13472                         i40e_rss_clear_hash_function(pf, conf);
13473                 else
13474                         i40e_rss_disable_hash(pf, conf);
13475         }
13476
13477         return 0;
13478 }
13479
13480 RTE_INIT(i40e_init_log)
13481 {
13482         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
13483         if (i40e_logtype_init >= 0)
13484                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
13485         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
13486         if (i40e_logtype_driver >= 0)
13487                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
13488
13489 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13490         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
13491         if (i40e_logtype_rx >= 0)
13492                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
13493 #endif
13494
13495 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13496         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
13497         if (i40e_logtype_tx >= 0)
13498                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
13499 #endif
13500
13501 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13502         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
13503         if (i40e_logtype_tx_free >= 0)
13504                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
13505 #endif
13506 }
13507
13508 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13509                               ETH_I40E_FLOATING_VEB_ARG "=1"
13510                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13511                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13512                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13513                               ETH_I40E_USE_LATEST_VEC "=0|1");