drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { .vendor_id = 0, /* sentinel */ },
 447 };
 448
 449 static const struct eth_dev_ops i40e_eth_dev_ops = {
 450         .dev_configure                = i40e_dev_configure,
 451         .dev_start                    = i40e_dev_start,
 452         .dev_stop                     = i40e_dev_stop,
 453         .dev_close                    = i40e_dev_close,
 454         .dev_reset                    = i40e_dev_reset,
 455         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 456         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 457         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 458         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 459         .dev_set_link_up              = i40e_dev_set_link_up,
 460         .dev_set_link_down            = i40e_dev_set_link_down,
 461         .link_update                  = i40e_dev_link_update,
 462         .stats_get                    = i40e_dev_stats_get,
 463         .xstats_get                   = i40e_dev_xstats_get,
 464         .xstats_get_names             = i40e_dev_xstats_get_names,
 465         .stats_reset                  = i40e_dev_stats_reset,
 466         .xstats_reset                 = i40e_dev_stats_reset,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 506         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .get_module_info              = i40e_get_module_info,
 521         .get_module_eeprom            = i40e_get_module_eeprom,
 522         .mac_addr_set                 = i40e_set_default_mac_addr,
 523         .mtu_set                      = i40e_dev_mtu_set,
 524         .tm_ops_get                   = i40e_tm_ops_get,
 525 };
 526
 527 /* store statistics names and its offset in stats structure */
 528 struct rte_i40e_xstats_name_off {
 529         char name[RTE_ETH_XSTATS_NAME_SIZE];
 530         unsigned offset;
 531 };
 532
 533 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 534         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 535         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 536         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 537         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 538         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 539                 rx_unknown_protocol)},
 540         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 541         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 542         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 543         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 544 };
 545
 546 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 547                 sizeof(rte_i40e_stats_strings[0]))
 548
 549 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 550         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 551                 tx_dropped_link_down)},
 552         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 553         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 554                 illegal_bytes)},
 555         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 556         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_local_faults)},
 558         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 559                 mac_remote_faults)},
 560         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 561                 rx_length_errors)},
 562         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 563         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 564         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 565         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 566         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 567         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_127)},
 569         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_255)},
 571         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_511)},
 573         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1023)},
 575         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_1522)},
 577         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_big)},
 579         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_undersize)},
 581         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_oversize)},
 583         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 584                 mac_short_packet_dropped)},
 585         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_fragments)},
 587         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 588         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 589         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_127)},
 591         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_255)},
 593         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_511)},
 595         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1023)},
 597         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_1522)},
 599         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_big)},
 601         {"rx_flow_director_atr_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 603         {"rx_flow_director_sb_match_packets",
 604                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 605         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_status)},
 607         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_status)},
 609         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 tx_lpi_count)},
 611         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 612                 rx_lpi_count)},
 613 };
 614
 615 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 616                 sizeof(rte_i40e_hw_port_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_rx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_rx)},
 623 };
 624
 625 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 626                 sizeof(rte_i40e_rxq_prio_strings[0]))
 627
 628 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 629         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_tx)},
 631         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xoff_tx)},
 633         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xon_2_xoff)},
 635 };
 636
 637 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 638                 sizeof(rte_i40e_txq_prio_strings[0]))
 639
 640 static int
 641 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 642         struct rte_pci_device *pci_dev)
 643 {
 644         char name[RTE_ETH_NAME_MAX_LEN];
 645         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 646         int i, retval;
 647
 648         if (pci_dev->device.devargs) {
 649                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 650                                 &eth_da);
 651                 if (retval)
 652                         return retval;
 653         }
 654
 655         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 656                 sizeof(struct i40e_adapter),
 657                 eth_dev_pci_specific_init, pci_dev,
 658                 eth_i40e_dev_init, NULL);
 659
 660         if (retval || eth_da.nb_representor_ports < 1)
 661                 return retval;
 662
 663         /* probe VF representor ports */
 664         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 665                 pci_dev->device.name);
 666
 667         if (pf_ethdev == NULL)
 668                 return -ENODEV;
 669
 670         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 671                 struct i40e_vf_representor representor = {
 672                         .vf_id = eth_da.representor_ports[i],
 673                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 674                                 pf_ethdev->data->dev_private)->switch_domain_id,
 675                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 676                                 pf_ethdev->data->dev_private)
 677                 };
 678
 679                 /* representor port net_bdf_port */
 680                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 681                         pci_dev->device.name, eth_da.representor_ports[i]);
 682
 683                 retval = rte_eth_dev_create(&pci_dev->device, name,
 684                         sizeof(struct i40e_vf_representor), NULL, NULL,
 685                         i40e_vf_representor_init, &representor);
 686
 687                 if (retval)
 688                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 689                                 "representor %s.", name);
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 696 {
 697         struct rte_eth_dev *ethdev;
 698
 699         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 700         if (!ethdev)
 701                 return -ENODEV;
 702
 703
 704         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 705                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 706         else
 707                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 708 }
 709
 710 static struct rte_pci_driver rte_i40e_pmd = {
 711         .id_table = pci_id_i40e_map,
 712         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 713         .probe = eth_i40e_pci_probe,
 714         .remove = eth_i40e_pci_remove,
 715 };
 716
 717 static inline void
 718 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 719                          uint32_t reg_val)
 720 {
 721         uint32_t ori_reg_val;
 722         struct rte_eth_dev *dev;
 723
 724         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 725         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 726         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 727         if (ori_reg_val != reg_val)
 728                 PMD_DRV_LOG(WARNING,
 729                             "i40e device %s changed global register [0x%08x]."
 730                             " original: 0x%08x, new: 0x%08x",
 731                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 732 }
 733
 734 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 735 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 736 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 737
 738 #ifndef I40E_GLQF_ORT
 739 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 740 #endif
 741 #ifndef I40E_GLQF_PIT
 742 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 743 #endif
 744 #ifndef I40E_GLQF_L3_MAP
 745 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 746 #endif
 747
 748 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 749 {
 750         /*
 751          * Initialize registers for parsing packet type of QinQ
 752          * This should be removed from code once proper
 753          * configuration API is added to avoid configuration conflicts
 754          * between ports of the same device.
 755          */
 756         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 757         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 758 }
 759
 760 static inline void i40e_config_automask(struct i40e_pf *pf)
 761 {
 762         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 763         uint32_t val;
 764
 765         /* INTENA flag is not auto-cleared for interrupt */
 766         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 767         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 768                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 769
 770         /* If support multi-driver, PF will use INT0. */
 771         if (!pf->support_multi_driver)
 772                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 773
 774         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 775 }
 776
 777 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 778
 779 /*
 780  * Add a ethertype filter to drop all flow control frames transmitted
 781  * from VSIs.
 782 */
 783 static void
 784 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 785 {
 786         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 787         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 788                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 789                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 790         int ret;
 791
 792         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 793                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 794                                 pf->main_vsi_seid, 0,
 795                                 TRUE, NULL, NULL);
 796         if (ret)
 797                 PMD_INIT_LOG(ERR,
 798                         "Failed to add filter to drop flow control frames from VSIs.");
 799 }
 800
 801 static int
 802 floating_veb_list_handler(__rte_unused const char *key,
 803                           const char *floating_veb_value,
 804                           void *opaque)
 805 {
 806         int idx = 0;
 807         unsigned int count = 0;
 808         char *end = NULL;
 809         int min, max;
 810         bool *vf_floating_veb = opaque;
 811
 812         while (isblank(*floating_veb_value))
 813                 floating_veb_value++;
 814
 815         /* Reset floating VEB configuration for VFs */
 816         for (idx = 0; idx < I40E_MAX_VF; idx++)
 817                 vf_floating_veb[idx] = false;
 818
 819         min = I40E_MAX_VF;
 820         do {
 821                 while (isblank(*floating_veb_value))
 822                         floating_veb_value++;
 823                 if (*floating_veb_value == '\0')
 824                         return -1;
 825                 errno = 0;
 826                 idx = strtoul(floating_veb_value, &end, 10);
 827                 if (errno || end == NULL)
 828                         return -1;
 829                 while (isblank(*end))
 830                         end++;
 831                 if (*end == '-') {
 832                         min = idx;
 833                 } else if ((*end == ';') || (*end == '\0')) {
 834                         max = idx;
 835                         if (min == I40E_MAX_VF)
 836                                 min = idx;
 837                         if (max >= I40E_MAX_VF)
 838                                 max = I40E_MAX_VF - 1;
 839                         for (idx = min; idx <= max; idx++) {
 840                                 vf_floating_veb[idx] = true;
 841                                 count++;
 842                         }
 843                         min = I40E_MAX_VF;
 844                 } else {
 845                         return -1;
 846                 }
 847                 floating_veb_value = end + 1;
 848         } while (*end != '\0');
 849
 850         if (count == 0)
 851                 return -1;
 852
 853         return 0;
 854 }
 855
 856 static void
 857 config_vf_floating_veb(struct rte_devargs *devargs,
 858                        uint16_t floating_veb,
 859                        bool *vf_floating_veb)
 860 {
 861         struct rte_kvargs *kvlist;
 862         int i;
 863         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 864
 865         if (!floating_veb)
 866                 return;
 867         /* All the VFs attach to the floating VEB by default
 868          * when the floating VEB is enabled.
 869          */
 870         for (i = 0; i < I40E_MAX_VF; i++)
 871                 vf_floating_veb[i] = true;
 872
 873         if (devargs == NULL)
 874                 return;
 875
 876         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 877         if (kvlist == NULL)
 878                 return;
 879
 880         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 881                 rte_kvargs_free(kvlist);
 882                 return;
 883         }
 884         /* When the floating_veb_list parameter exists, all the VFs
 885          * will attach to the legacy VEB firstly, then configure VFs
 886          * to the floating VEB according to the floating_veb_list.
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_list,
 889                                floating_veb_list_handler,
 890                                vf_floating_veb) < 0) {
 891                 rte_kvargs_free(kvlist);
 892                 return;
 893         }
 894         rte_kvargs_free(kvlist);
 895 }
 896
 897 static int
 898 i40e_check_floating_handler(__rte_unused const char *key,
 899                             const char *value,
 900                             __rte_unused void *opaque)
 901 {
 902         if (strcmp(value, "1"))
 903                 return -1;
 904
 905         return 0;
 906 }
 907
 908 static int
 909 is_floating_veb_supported(struct rte_devargs *devargs)
 910 {
 911         struct rte_kvargs *kvlist;
 912         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 913
 914         if (devargs == NULL)
 915                 return 0;
 916
 917         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 918         if (kvlist == NULL)
 919                 return 0;
 920
 921         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 922                 rte_kvargs_free(kvlist);
 923                 return 0;
 924         }
 925         /* Floating VEB is enabled when there's key-value:
 926          * enable_floating_veb=1
 927          */
 928         if (rte_kvargs_process(kvlist, floating_veb_key,
 929                                i40e_check_floating_handler, NULL) < 0) {
 930                 rte_kvargs_free(kvlist);
 931                 return 0;
 932         }
 933         rte_kvargs_free(kvlist);
 934
 935         return 1;
 936 }
 937
 938 static void
 939 config_floating_veb(struct rte_eth_dev *dev)
 940 {
 941         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 942         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 944
 945         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 946
 947         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 948                 pf->floating_veb =
 949                         is_floating_veb_supported(pci_dev->device.devargs);
 950                 config_vf_floating_veb(pci_dev->device.devargs,
 951                                        pf->floating_veb,
 952                                        pf->floating_veb_list);
 953         } else {
 954                 pf->floating_veb = false;
 955         }
 956 }
 957
 958 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 959 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 960
 961 static int
 962 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 963 {
 964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 965         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 966         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 967         int ret;
 968
 969         struct rte_hash_parameters ethertype_hash_params = {
 970                 .name = ethertype_hash_name,
 971                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 972                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 973                 .hash_func = rte_hash_crc,
 974                 .hash_func_init_val = 0,
 975                 .socket_id = rte_socket_id(),
 976         };
 977
 978         /* Initialize ethertype filter rule list and hash */
 979         TAILQ_INIT(&ethertype_rule->ethertype_list);
 980         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 981                  "ethertype_%s", dev->device->name);
 982         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 983         if (!ethertype_rule->hash_table) {
 984                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 985                 return -EINVAL;
 986         }
 987         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 988                                        sizeof(struct i40e_ethertype_filter *) *
 989                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 990                                        0);
 991         if (!ethertype_rule->hash_map) {
 992                 PMD_INIT_LOG(ERR,
 993                              "Failed to allocate memory for ethertype hash map!");
 994                 ret = -ENOMEM;
 995                 goto err_ethertype_hash_map_alloc;
 996         }
 997
 998         return 0;
 999
1000 err_ethertype_hash_map_alloc:
1001         rte_hash_free(ethertype_rule->hash_table);
1002
1003         return ret;
1004 }
1005
1006 static int
1007 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1008 {
1009         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1011         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1012         int ret;
1013
1014         struct rte_hash_parameters tunnel_hash_params = {
1015                 .name = tunnel_hash_name,
1016                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1017                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1018                 .hash_func = rte_hash_crc,
1019                 .hash_func_init_val = 0,
1020                 .socket_id = rte_socket_id(),
1021         };
1022
1023         /* Initialize tunnel filter rule list and hash */
1024         TAILQ_INIT(&tunnel_rule->tunnel_list);
1025         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1026                  "tunnel_%s", dev->device->name);
1027         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1028         if (!tunnel_rule->hash_table) {
1029                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1030                 return -EINVAL;
1031         }
1032         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1033                                     sizeof(struct i40e_tunnel_filter *) *
1034                                     I40E_MAX_TUNNEL_FILTER_NUM,
1035                                     0);
1036         if (!tunnel_rule->hash_map) {
1037                 PMD_INIT_LOG(ERR,
1038                              "Failed to allocate memory for tunnel hash map!");
1039                 ret = -ENOMEM;
1040                 goto err_tunnel_hash_map_alloc;
1041         }
1042
1043         return 0;
1044
1045 err_tunnel_hash_map_alloc:
1046         rte_hash_free(tunnel_rule->hash_table);
1047
1048         return ret;
1049 }
1050
1051 static int
1052 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1053 {
1054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1055         struct i40e_fdir_info *fdir_info = &pf->fdir;
1056         char fdir_hash_name[RTE_HASH_NAMESIZE];
1057         int ret;
1058
1059         struct rte_hash_parameters fdir_hash_params = {
1060                 .name = fdir_hash_name,
1061                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1062                 .key_len = sizeof(struct i40e_fdir_input),
1063                 .hash_func = rte_hash_crc,
1064                 .hash_func_init_val = 0,
1065                 .socket_id = rte_socket_id(),
1066         };
1067
1068         /* Initialize flow director filter rule list and hash */
1069         TAILQ_INIT(&fdir_info->fdir_list);
1070         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1071                  "fdir_%s", dev->device->name);
1072         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1073         if (!fdir_info->hash_table) {
1074                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1075                 return -EINVAL;
1076         }
1077         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078                                           sizeof(struct i40e_fdir_filter *) *
1079                                           I40E_MAX_FDIR_FILTER_NUM,
1080                                           0);
1081         if (!fdir_info->hash_map) {
1082                 PMD_INIT_LOG(ERR,
1083                              "Failed to allocate memory for fdir hash map!");
1084                 ret = -ENOMEM;
1085                 goto err_fdir_hash_map_alloc;
1086         }
1087         return 0;
1088
1089 err_fdir_hash_map_alloc:
1090         rte_hash_free(fdir_info->hash_table);
1091
1092         return ret;
1093 }
1094
1095 static void
1096 i40e_init_customized_info(struct i40e_pf *pf)
1097 {
1098         int i;
1099
1100         /* Initialize customized pctype */
1101         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1102                 pf->customized_pctype[i].index = i;
1103                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1104                 pf->customized_pctype[i].valid = false;
1105         }
1106
1107         pf->gtp_support = false;
1108 }
1109
1110 void
1111 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1112 {
1113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1115         struct i40e_queue_regions *info = &pf->queue_region;
1116         uint16_t i;
1117
1118         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1119                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1120
1121         memset(info, 0, sizeof(struct i40e_queue_regions));
1122 }
1123
1124 static int
1125 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1126                                const char *value,
1127                                void *opaque)
1128 {
1129         struct i40e_pf *pf;
1130         unsigned long support_multi_driver;
1131         char *end;
1132
1133         pf = (struct i40e_pf *)opaque;
1134
1135         errno = 0;
1136         support_multi_driver = strtoul(value, &end, 10);
1137         if (errno != 0 || end == value || *end != 0) {
1138                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1139                 return -(EINVAL);
1140         }
1141
1142         if (support_multi_driver == 1 || support_multi_driver == 0)
1143                 pf->support_multi_driver = (bool)support_multi_driver;
1144         else
1145                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1146                             "enable global configuration by default."
1147                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1148         return 0;
1149 }
1150
1151 static int
1152 i40e_support_multi_driver(struct rte_eth_dev *dev)
1153 {
1154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1155         struct rte_kvargs *kvlist;
1156         int kvargs_count;
1157
1158         /* Enable global configuration by default */
1159         pf->support_multi_driver = false;
1160
1161         if (!dev->device->devargs)
1162                 return 0;
1163
1164         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1165         if (!kvlist)
1166                 return -EINVAL;
1167
1168         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1169         if (!kvargs_count) {
1170                 rte_kvargs_free(kvlist);
1171                 return 0;
1172         }
1173
1174         if (kvargs_count > 1)
1175                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1176                             "the first invalid or last valid one is used !",
1177                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1178
1179         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1180                                i40e_parse_multi_drv_handler, pf) < 0) {
1181                 rte_kvargs_free(kvlist);
1182                 return -EINVAL;
1183         }
1184
1185         rte_kvargs_free(kvlist);
1186         return 0;
1187 }
1188
1189 static int
1190 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1191                                     uint32_t reg_addr, uint64_t reg_val,
1192                                     struct i40e_asq_cmd_details *cmd_details)
1193 {
1194         uint64_t ori_reg_val;
1195         struct rte_eth_dev *dev;
1196         int ret;
1197
1198         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1199         if (ret != I40E_SUCCESS) {
1200                 PMD_DRV_LOG(ERR,
1201                             "Fail to debug read from 0x%08x",
1202                             reg_addr);
1203                 return -EIO;
1204         }
1205         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1206
1207         if (ori_reg_val != reg_val)
1208                 PMD_DRV_LOG(WARNING,
1209                             "i40e device %s changed global register [0x%08x]."
1210                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1211                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1212
1213         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1214 }
1215
1216 static int
1217 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1218                                 const char *value,
1219                                 void *opaque)
1220 {
1221         struct i40e_adapter *ad = opaque;
1222         int use_latest_vec;
1223
1224         use_latest_vec = atoi(value);
1225
1226         if (use_latest_vec != 0 && use_latest_vec != 1)
1227                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1228
1229         ad->use_latest_vec = (uint8_t)use_latest_vec;
1230
1231         return 0;
1232 }
1233
1234 static int
1235 i40e_use_latest_vec(struct rte_eth_dev *dev)
1236 {
1237         struct i40e_adapter *ad =
1238                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1239         struct rte_kvargs *kvlist;
1240         int kvargs_count;
1241
1242         ad->use_latest_vec = false;
1243
1244         if (!dev->device->devargs)
1245                 return 0;
1246
1247         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1248         if (!kvlist)
1249                 return -EINVAL;
1250
1251         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1252         if (!kvargs_count) {
1253                 rte_kvargs_free(kvlist);
1254                 return 0;
1255         }
1256
1257         if (kvargs_count > 1)
1258                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1259                             "the first invalid or last valid one is used !",
1260                             ETH_I40E_USE_LATEST_VEC);
1261
1262         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1263                                 i40e_parse_latest_vec_handler, ad) < 0) {
1264                 rte_kvargs_free(kvlist);
1265                 return -EINVAL;
1266         }
1267
1268         rte_kvargs_free(kvlist);
1269         return 0;
1270 }
1271
1272 static int
1273 read_vf_msg_config(__rte_unused const char *key,
1274                                const char *value,
1275                                void *opaque)
1276 {
1277         struct i40e_vf_msg_cfg *cfg = opaque;
1278
1279         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1280                         &cfg->ignore_second) != 3) {
1281                 memset(cfg, 0, sizeof(*cfg));
1282                 PMD_DRV_LOG(ERR, "format error! example: "
1283                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1284                 return -EINVAL;
1285         }
1286
1287         /*
1288          * If the message validation function been enabled, the 'period'
1289          * and 'ignore_second' must greater than 0.
1290          */
1291         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1292                 memset(cfg, 0, sizeof(*cfg));
1293                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1294                                 " number must be greater than 0!",
1295                                 ETH_I40E_VF_MSG_CFG);
1296                 return -EINVAL;
1297         }
1298
1299         return 0;
1300 }
1301
1302 static int
1303 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1304                 struct i40e_vf_msg_cfg *msg_cfg)
1305 {
1306         struct rte_kvargs *kvlist;
1307         int kvargs_count;
1308         int ret = 0;
1309
1310         memset(msg_cfg, 0, sizeof(*msg_cfg));
1311
1312         if (!dev->device->devargs)
1313                 return ret;
1314
1315         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1316         if (!kvlist)
1317                 return -EINVAL;
1318
1319         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1320         if (!kvargs_count)
1321                 goto free_end;
1322
1323         if (kvargs_count > 1) {
1324                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1325                                 ETH_I40E_VF_MSG_CFG);
1326                 ret = -EINVAL;
1327                 goto free_end;
1328         }
1329
1330         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1331                         read_vf_msg_config, msg_cfg) < 0)
1332                 ret = -EINVAL;
1333
1334 free_end:
1335         rte_kvargs_free(kvlist);
1336         return ret;
1337 }
1338
1339 #define I40E_ALARM_INTERVAL 50000 /* us */
1340
1341 static int
1342 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1343 {
1344         struct rte_pci_device *pci_dev;
1345         struct rte_intr_handle *intr_handle;
1346         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1347         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1348         struct i40e_vsi *vsi;
1349         int ret;
1350         uint32_t len, val;
1351         uint8_t aq_fail = 0;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         dev->dev_ops = &i40e_eth_dev_ops;
1356         dev->rx_pkt_burst = i40e_recv_pkts;
1357         dev->tx_pkt_burst = i40e_xmit_pkts;
1358         dev->tx_pkt_prepare = i40e_prep_pkts;
1359
1360         /* for secondary processes, we don't initialise any further as primary
1361          * has already done this work. Only check we don't need a different
1362          * RX function */
1363         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1364                 i40e_set_rx_function(dev);
1365                 i40e_set_tx_function(dev);
1366                 return 0;
1367         }
1368         i40e_set_default_ptype_table(dev);
1369         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1370         intr_handle = &pci_dev->intr_handle;
1371
1372         rte_eth_copy_pci_info(dev, pci_dev);
1373
1374         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1375         pf->adapter->eth_dev = dev;
1376         pf->dev_data = dev->data;
1377
1378         hw->back = I40E_PF_TO_ADAPTER(pf);
1379         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1380         if (!hw->hw_addr) {
1381                 PMD_INIT_LOG(ERR,
1382                         "Hardware is not available, as address is NULL");
1383                 return -ENODEV;
1384         }
1385
1386         hw->vendor_id = pci_dev->id.vendor_id;
1387         hw->device_id = pci_dev->id.device_id;
1388         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1389         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1390         hw->bus.device = pci_dev->addr.devid;
1391         hw->bus.func = pci_dev->addr.function;
1392         hw->adapter_stopped = 0;
1393         hw->adapter_closed = 0;
1394
1395         /*
1396          * Switch Tag value should not be identical to either the First Tag
1397          * or Second Tag values. So set something other than common Ethertype
1398          * for internal switching.
1399          */
1400         hw->switch_tag = 0xffff;
1401
1402         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1403         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1404                 PMD_INIT_LOG(ERR, "\nERROR: "
1405                         "Firmware recovery mode detected. Limiting functionality.\n"
1406                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1407                         "User Guide for details on firmware recovery mode.");
1408                 return -EIO;
1409         }
1410
1411         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1412         /* Check if need to support multi-driver */
1413         i40e_support_multi_driver(dev);
1414         /* Check if users want the latest supported vec path */
1415         i40e_use_latest_vec(dev);
1416
1417         /* Make sure all is clean before doing PF reset */
1418         i40e_clear_hw(hw);
1419
1420         /* Reset here to make sure all is clean for each PF */
1421         ret = i40e_pf_reset(hw);
1422         if (ret) {
1423                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1424                 return ret;
1425         }
1426
1427         /* Initialize the shared code (base driver) */
1428         ret = i40e_init_shared_code(hw);
1429         if (ret) {
1430                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1431                 return ret;
1432         }
1433
1434         /* Initialize the parameters for adminq */
1435         i40e_init_adminq_parameter(hw);
1436         ret = i40e_init_adminq(hw);
1437         if (ret != I40E_SUCCESS) {
1438                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1439                 return -EIO;
1440         }
1441         /* Firmware of SFP x722 does not support adminq option */
1442         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1443                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1444
1445         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1446                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1447                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1448                      ((hw->nvm.version >> 12) & 0xf),
1449                      ((hw->nvm.version >> 4) & 0xff),
1450                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1451
1452         /* Initialize the hardware */
1453         i40e_hw_init(dev);
1454
1455         i40e_config_automask(pf);
1456
1457         i40e_set_default_pctype_table(dev);
1458
1459         /*
1460          * To work around the NVM issue, initialize registers
1461          * for packet type of QinQ by software.
1462          * It should be removed once issues are fixed in NVM.
1463          */
1464         if (!pf->support_multi_driver)
1465                 i40e_GLQF_reg_init(hw);
1466
1467         /* Initialize the input set for filters (hash and fd) to default value */
1468         i40e_filter_input_set_init(pf);
1469
1470         /* initialise the L3_MAP register */
1471         if (!pf->support_multi_driver) {
1472                 ret = i40e_aq_debug_write_global_register(hw,
1473                                                    I40E_GLQF_L3_MAP(40),
1474                                                    0x00000028,  NULL);
1475                 if (ret)
1476                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1477                                      ret);
1478                 PMD_INIT_LOG(DEBUG,
1479                              "Global register 0x%08x is changed with 0x28",
1480                              I40E_GLQF_L3_MAP(40));
1481         }
1482
1483         /* Need the special FW version to support floating VEB */
1484         config_floating_veb(dev);
1485         /* Clear PXE mode */
1486         i40e_clear_pxe_mode(hw);
1487         i40e_dev_sync_phy_type(hw);
1488
1489         /*
1490          * On X710, performance number is far from the expectation on recent
1491          * firmware versions. The fix for this issue may not be integrated in
1492          * the following firmware version. So the workaround in software driver
1493          * is needed. It needs to modify the initial values of 3 internal only
1494          * registers. Note that the workaround can be removed when it is fixed
1495          * in firmware in the future.
1496          */
1497         i40e_configure_registers(hw);
1498
1499         /* Get hw capabilities */
1500         ret = i40e_get_cap(hw);
1501         if (ret != I40E_SUCCESS) {
1502                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1503                 goto err_get_capabilities;
1504         }
1505
1506         /* Initialize parameters for PF */
1507         ret = i40e_pf_parameter_init(dev);
1508         if (ret != 0) {
1509                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1510                 goto err_parameter_init;
1511         }
1512
1513         /* Initialize the queue management */
1514         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1515         if (ret < 0) {
1516                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1517                 goto err_qp_pool_init;
1518         }
1519         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1520                                 hw->func_caps.num_msix_vectors - 1);
1521         if (ret < 0) {
1522                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1523                 goto err_msix_pool_init;
1524         }
1525
1526         /* Initialize lan hmc */
1527         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1528                                 hw->func_caps.num_rx_qp, 0, 0);
1529         if (ret != I40E_SUCCESS) {
1530                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1531                 goto err_init_lan_hmc;
1532         }
1533
1534         /* Configure lan hmc */
1535         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1536         if (ret != I40E_SUCCESS) {
1537                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1538                 goto err_configure_lan_hmc;
1539         }
1540
1541         /* Get and check the mac address */
1542         i40e_get_mac_addr(hw, hw->mac.addr);
1543         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1544                 PMD_INIT_LOG(ERR, "mac address is not valid");
1545                 ret = -EIO;
1546                 goto err_get_mac_addr;
1547         }
1548         /* Copy the permanent MAC address */
1549         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1550                         (struct rte_ether_addr *)hw->mac.perm_addr);
1551
1552         /* Disable flow control */
1553         hw->fc.requested_mode = I40E_FC_NONE;
1554         i40e_set_fc(hw, &aq_fail, TRUE);
1555
1556         /* Set the global registers with default ether type value */
1557         if (!pf->support_multi_driver) {
1558                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1559                                          RTE_ETHER_TYPE_VLAN);
1560                 if (ret != I40E_SUCCESS) {
1561                         PMD_INIT_LOG(ERR,
1562                                      "Failed to set the default outer "
1563                                      "VLAN ether type");
1564                         goto err_setup_pf_switch;
1565                 }
1566         }
1567
1568         /* PF setup, which includes VSI setup */
1569         ret = i40e_pf_setup(pf);
1570         if (ret) {
1571                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1572                 goto err_setup_pf_switch;
1573         }
1574
1575         vsi = pf->main_vsi;
1576
1577         /* Disable double vlan by default */
1578         i40e_vsi_config_double_vlan(vsi, FALSE);
1579
1580         /* Disable S-TAG identification when floating_veb is disabled */
1581         if (!pf->floating_veb) {
1582                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1583                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1584                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1585                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1586                 }
1587         }
1588
1589         if (!vsi->max_macaddrs)
1590                 len = RTE_ETHER_ADDR_LEN;
1591         else
1592                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1593
1594         /* Should be after VSI initialized */
1595         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1596         if (!dev->data->mac_addrs) {
1597                 PMD_INIT_LOG(ERR,
1598                         "Failed to allocated memory for storing mac address");
1599                 goto err_mac_alloc;
1600         }
1601         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1602                                         &dev->data->mac_addrs[0]);
1603
1604         /* Pass the information to the rte_eth_dev_close() that it should also
1605          * release the private port resources.
1606          */
1607         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1608
1609         /* Init dcb to sw mode by default */
1610         ret = i40e_dcb_init_configure(dev, TRUE);
1611         if (ret != I40E_SUCCESS) {
1612                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1613                 pf->flags &= ~I40E_FLAG_DCB;
1614         }
1615         /* Update HW struct after DCB configuration */
1616         i40e_get_cap(hw);
1617
1618         /* initialize pf host driver to setup SRIOV resource if applicable */
1619         i40e_pf_host_init(dev);
1620
1621         /* register callback func to eal lib */
1622         rte_intr_callback_register(intr_handle,
1623                                    i40e_dev_interrupt_handler, dev);
1624
1625         /* configure and enable device interrupt */
1626         i40e_pf_config_irq0(hw, TRUE);
1627         i40e_pf_enable_irq0(hw);
1628
1629         /* enable uio intr after callback register */
1630         rte_intr_enable(intr_handle);
1631
1632         /* By default disable flexible payload in global configuration */
1633         if (!pf->support_multi_driver)
1634                 i40e_flex_payload_reg_set_default(hw);
1635
1636         /*
1637          * Add an ethertype filter to drop all flow control frames transmitted
1638          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1639          * frames to wire.
1640          */
1641         i40e_add_tx_flow_control_drop_filter(pf);
1642
1643         /* Set the max frame size to 0x2600 by default,
1644          * in case other drivers changed the default value.
1645          */
1646         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1647
1648         /* initialize mirror rule list */
1649         TAILQ_INIT(&pf->mirror_list);
1650
1651         /* initialize Traffic Manager configuration */
1652         i40e_tm_conf_init(dev);
1653
1654         /* Initialize customized information */
1655         i40e_init_customized_info(pf);
1656
1657         ret = i40e_init_ethtype_filter_list(dev);
1658         if (ret < 0)
1659                 goto err_init_ethtype_filter_list;
1660         ret = i40e_init_tunnel_filter_list(dev);
1661         if (ret < 0)
1662                 goto err_init_tunnel_filter_list;
1663         ret = i40e_init_fdir_filter_list(dev);
1664         if (ret < 0)
1665                 goto err_init_fdir_filter_list;
1666
1667         /* initialize queue region configuration */
1668         i40e_init_queue_region_conf(dev);
1669
1670         /* initialize rss configuration from rte_flow */
1671         memset(&pf->rss_info, 0,
1672                 sizeof(struct i40e_rte_flow_rss_conf));
1673
1674         /* reset all stats of the device, including pf and main vsi */
1675         i40e_dev_stats_reset(dev);
1676
1677         return 0;
1678
1679 err_init_fdir_filter_list:
1680         rte_free(pf->tunnel.hash_table);
1681         rte_free(pf->tunnel.hash_map);
1682 err_init_tunnel_filter_list:
1683         rte_free(pf->ethertype.hash_table);
1684         rte_free(pf->ethertype.hash_map);
1685 err_init_ethtype_filter_list:
1686         rte_free(dev->data->mac_addrs);
1687         dev->data->mac_addrs = NULL;
1688 err_mac_alloc:
1689         i40e_vsi_release(pf->main_vsi);
1690 err_setup_pf_switch:
1691 err_get_mac_addr:
1692 err_configure_lan_hmc:
1693         (void)i40e_shutdown_lan_hmc(hw);
1694 err_init_lan_hmc:
1695         i40e_res_pool_destroy(&pf->msix_pool);
1696 err_msix_pool_init:
1697         i40e_res_pool_destroy(&pf->qp_pool);
1698 err_qp_pool_init:
1699 err_parameter_init:
1700 err_get_capabilities:
1701         (void)i40e_shutdown_adminq(hw);
1702
1703         return ret;
1704 }
1705
1706 static void
1707 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1708 {
1709         struct i40e_ethertype_filter *p_ethertype;
1710         struct i40e_ethertype_rule *ethertype_rule;
1711
1712         ethertype_rule = &pf->ethertype;
1713         /* Remove all ethertype filter rules and hash */
1714         if (ethertype_rule->hash_map)
1715                 rte_free(ethertype_rule->hash_map);
1716         if (ethertype_rule->hash_table)
1717                 rte_hash_free(ethertype_rule->hash_table);
1718
1719         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1720                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1721                              p_ethertype, rules);
1722                 rte_free(p_ethertype);
1723         }
1724 }
1725
1726 static void
1727 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1728 {
1729         struct i40e_tunnel_filter *p_tunnel;
1730         struct i40e_tunnel_rule *tunnel_rule;
1731
1732         tunnel_rule = &pf->tunnel;
1733         /* Remove all tunnel director rules and hash */
1734         if (tunnel_rule->hash_map)
1735                 rte_free(tunnel_rule->hash_map);
1736         if (tunnel_rule->hash_table)
1737                 rte_hash_free(tunnel_rule->hash_table);
1738
1739         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1740                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1741                 rte_free(p_tunnel);
1742         }
1743 }
1744
1745 static void
1746 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1747 {
1748         struct i40e_fdir_filter *p_fdir;
1749         struct i40e_fdir_info *fdir_info;
1750
1751         fdir_info = &pf->fdir;
1752         /* Remove all flow director rules and hash */
1753         if (fdir_info->hash_map)
1754                 rte_free(fdir_info->hash_map);
1755         if (fdir_info->hash_table)
1756                 rte_hash_free(fdir_info->hash_table);
1757
1758         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1759                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1760                 rte_free(p_fdir);
1761         }
1762 }
1763
1764 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1765 {
1766         /*
1767          * Disable by default flexible payload
1768          * for corresponding L2/L3/L4 layers.
1769          */
1770         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1771         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1772         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1773 }
1774
1775 static int
1776 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_hw *hw;
1779
1780         PMD_INIT_FUNC_TRACE();
1781
1782         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1783                 return 0;
1784
1785         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786
1787         if (hw->adapter_closed == 0)
1788                 i40e_dev_close(dev);
1789
1790         return 0;
1791 }
1792
1793 static int
1794 i40e_dev_configure(struct rte_eth_dev *dev)
1795 {
1796         struct i40e_adapter *ad =
1797                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1798         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1799         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1801         int i, ret;
1802
1803         ret = i40e_dev_sync_phy_type(hw);
1804         if (ret)
1805                 return ret;
1806
1807         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1808          * bulk allocation or vector Rx preconditions we will reset it.
1809          */
1810         ad->rx_bulk_alloc_allowed = true;
1811         ad->rx_vec_allowed = true;
1812         ad->tx_simple_allowed = true;
1813         ad->tx_vec_allowed = true;
1814
1815         /* Only legacy filter API needs the following fdir config. So when the
1816          * legacy filter API is deprecated, the following codes should also be
1817          * removed.
1818          */
1819         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1820                 ret = i40e_fdir_setup(pf);
1821                 if (ret != I40E_SUCCESS) {
1822                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1823                         return -ENOTSUP;
1824                 }
1825                 ret = i40e_fdir_configure(dev);
1826                 if (ret < 0) {
1827                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1828                         goto err;
1829                 }
1830         } else
1831                 i40e_fdir_teardown(pf);
1832
1833         ret = i40e_dev_init_vlan(dev);
1834         if (ret < 0)
1835                 goto err;
1836
1837         /* VMDQ setup.
1838          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1839          *  RSS setting have different requirements.
1840          *  General PMD driver call sequence are NIC init, configure,
1841          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1842          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1843          *  applicable. So, VMDQ setting has to be done before
1844          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1845          *  For RSS setting, it will try to calculate actual configured RX queue
1846          *  number, which will be available after rx_queue_setup(). dev_start()
1847          *  function is good to place RSS setup.
1848          */
1849         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1850                 ret = i40e_vmdq_setup(dev);
1851                 if (ret)
1852                         goto err;
1853         }
1854
1855         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1856                 ret = i40e_dcb_setup(dev);
1857                 if (ret) {
1858                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1859                         goto err_dcb;
1860                 }
1861         }
1862
1863         TAILQ_INIT(&pf->flow_list);
1864
1865         return 0;
1866
1867 err_dcb:
1868         /* need to release vmdq resource if exists */
1869         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1870                 i40e_vsi_release(pf->vmdq[i].vsi);
1871                 pf->vmdq[i].vsi = NULL;
1872         }
1873         rte_free(pf->vmdq);
1874         pf->vmdq = NULL;
1875 err:
1876         /* Need to release fdir resource if exists.
1877          * Only legacy filter API needs the following fdir config. So when the
1878          * legacy filter API is deprecated, the following code should also be
1879          * removed.
1880          */
1881         i40e_fdir_teardown(pf);
1882         return ret;
1883 }
1884
1885 void
1886 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1887 {
1888         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1889         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1890         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1891         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1892         uint16_t msix_vect = vsi->msix_intr;
1893         uint16_t i;
1894
1895         for (i = 0; i < vsi->nb_qps; i++) {
1896                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1897                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1898                 rte_wmb();
1899         }
1900
1901         if (vsi->type != I40E_VSI_SRIOV) {
1902                 if (!rte_intr_allow_others(intr_handle)) {
1903                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1904                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1905                         I40E_WRITE_REG(hw,
1906                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1907                                        0);
1908                 } else {
1909                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1910                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1911                         I40E_WRITE_REG(hw,
1912                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1913                                                        msix_vect - 1), 0);
1914                 }
1915         } else {
1916                 uint32_t reg;
1917                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1918                         vsi->user_param + (msix_vect - 1);
1919
1920                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1921                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1922         }
1923         I40E_WRITE_FLUSH(hw);
1924 }
1925
1926 static void
1927 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1928                        int base_queue, int nb_queue,
1929                        uint16_t itr_idx)
1930 {
1931         int i;
1932         uint32_t val;
1933         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1934         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1935
1936         /* Bind all RX queues to allocated MSIX interrupt */
1937         for (i = 0; i < nb_queue; i++) {
1938                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1939                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1940                         ((base_queue + i + 1) <<
1941                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1942                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1943                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1944
1945                 if (i == nb_queue - 1)
1946                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1947                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1948         }
1949
1950         /* Write first RX queue to Link list register as the head element */
1951         if (vsi->type != I40E_VSI_SRIOV) {
1952                 uint16_t interval =
1953                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1954
1955                 if (msix_vect == I40E_MISC_VEC_ID) {
1956                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1957                                        (base_queue <<
1958                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1959                                        (0x0 <<
1960                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1963                                        interval);
1964                 } else {
1965                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1966                                        (base_queue <<
1967                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1968                                        (0x0 <<
1969                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1970                         I40E_WRITE_REG(hw,
1971                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1972                                                        msix_vect - 1),
1973                                        interval);
1974                 }
1975         } else {
1976                 uint32_t reg;
1977
1978                 if (msix_vect == I40E_MISC_VEC_ID) {
1979                         I40E_WRITE_REG(hw,
1980                                        I40E_VPINT_LNKLST0(vsi->user_param),
1981                                        (base_queue <<
1982                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1983                                        (0x0 <<
1984                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1985                 } else {
1986                         /* num_msix_vectors_vf needs to minus irq0 */
1987                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1988                                 vsi->user_param + (msix_vect - 1);
1989
1990                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1991                                        (base_queue <<
1992                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1993                                        (0x0 <<
1994                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1995                 }
1996         }
1997
1998         I40E_WRITE_FLUSH(hw);
1999 }
2000
2001 void
2002 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2003 {
2004         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2005         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2006         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2007         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2008         uint16_t msix_vect = vsi->msix_intr;
2009         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2010         uint16_t queue_idx = 0;
2011         int record = 0;
2012         int i;
2013
2014         for (i = 0; i < vsi->nb_qps; i++) {
2015                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2016                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2017         }
2018
2019         /* VF bind interrupt */
2020         if (vsi->type == I40E_VSI_SRIOV) {
2021                 __vsi_queues_bind_intr(vsi, msix_vect,
2022                                        vsi->base_queue, vsi->nb_qps,
2023                                        itr_idx);
2024                 return;
2025         }
2026
2027         /* PF & VMDq bind interrupt */
2028         if (rte_intr_dp_is_en(intr_handle)) {
2029                 if (vsi->type == I40E_VSI_MAIN) {
2030                         queue_idx = 0;
2031                         record = 1;
2032                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2033                         struct i40e_vsi *main_vsi =
2034                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2035                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2036                         record = 1;
2037                 }
2038         }
2039
2040         for (i = 0; i < vsi->nb_used_qps; i++) {
2041                 if (nb_msix <= 1) {
2042                         if (!rte_intr_allow_others(intr_handle))
2043                                 /* allow to share MISC_VEC_ID */
2044                                 msix_vect = I40E_MISC_VEC_ID;
2045
2046                         /* no enough msix_vect, map all to one */
2047                         __vsi_queues_bind_intr(vsi, msix_vect,
2048                                                vsi->base_queue + i,
2049                                                vsi->nb_used_qps - i,
2050                                                itr_idx);
2051                         for (; !!record && i < vsi->nb_used_qps; i++)
2052                                 intr_handle->intr_vec[queue_idx + i] =
2053                                         msix_vect;
2054                         break;
2055                 }
2056                 /* 1:1 queue/msix_vect mapping */
2057                 __vsi_queues_bind_intr(vsi, msix_vect,
2058                                        vsi->base_queue + i, 1,
2059                                        itr_idx);
2060                 if (!!record)
2061                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2062
2063                 msix_vect++;
2064                 nb_msix--;
2065         }
2066 }
2067
2068 static void
2069 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2070 {
2071         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2072         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2073         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2074         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2075         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2076         uint16_t msix_intr, i;
2077
2078         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2079                 for (i = 0; i < vsi->nb_msix; i++) {
2080                         msix_intr = vsi->msix_intr + i;
2081                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2082                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2083                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2084                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2085                 }
2086         else
2087                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2088                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2089                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2090                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2091
2092         I40E_WRITE_FLUSH(hw);
2093 }
2094
2095 static void
2096 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2097 {
2098         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2099         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2100         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2102         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2103         uint16_t msix_intr, i;
2104
2105         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2106                 for (i = 0; i < vsi->nb_msix; i++) {
2107                         msix_intr = vsi->msix_intr + i;
2108                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2109                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2110                 }
2111         else
2112                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2113                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2114
2115         I40E_WRITE_FLUSH(hw);
2116 }
2117
2118 static inline uint8_t
2119 i40e_parse_link_speeds(uint16_t link_speeds)
2120 {
2121         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2122
2123         if (link_speeds & ETH_LINK_SPEED_40G)
2124                 link_speed |= I40E_LINK_SPEED_40GB;
2125         if (link_speeds & ETH_LINK_SPEED_25G)
2126                 link_speed |= I40E_LINK_SPEED_25GB;
2127         if (link_speeds & ETH_LINK_SPEED_20G)
2128                 link_speed |= I40E_LINK_SPEED_20GB;
2129         if (link_speeds & ETH_LINK_SPEED_10G)
2130                 link_speed |= I40E_LINK_SPEED_10GB;
2131         if (link_speeds & ETH_LINK_SPEED_1G)
2132                 link_speed |= I40E_LINK_SPEED_1GB;
2133         if (link_speeds & ETH_LINK_SPEED_100M)
2134                 link_speed |= I40E_LINK_SPEED_100MB;
2135
2136         return link_speed;
2137 }
2138
2139 static int
2140 i40e_phy_conf_link(struct i40e_hw *hw,
2141                    uint8_t abilities,
2142                    uint8_t force_speed,
2143                    bool is_up)
2144 {
2145         enum i40e_status_code status;
2146         struct i40e_aq_get_phy_abilities_resp phy_ab;
2147         struct i40e_aq_set_phy_config phy_conf;
2148         enum i40e_aq_phy_type cnt;
2149         uint8_t avail_speed;
2150         uint32_t phy_type_mask = 0;
2151
2152         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2153                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2154                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2155                         I40E_AQ_PHY_FLAG_LOW_POWER;
2156         int ret = -ENOTSUP;
2157
2158         /* To get phy capabilities of available speeds. */
2159         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2160                                               NULL);
2161         if (status) {
2162                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2163                                 status);
2164                 return ret;
2165         }
2166         avail_speed = phy_ab.link_speed;
2167
2168         /* To get the current phy config. */
2169         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2170                                               NULL);
2171         if (status) {
2172                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2173                                 status);
2174                 return ret;
2175         }
2176
2177         /* If link needs to go up and it is in autoneg mode the speed is OK,
2178          * no need to set up again.
2179          */
2180         if (is_up && phy_ab.phy_type != 0 &&
2181                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2182                      phy_ab.link_speed != 0)
2183                 return I40E_SUCCESS;
2184
2185         memset(&phy_conf, 0, sizeof(phy_conf));
2186
2187         /* bits 0-2 use the values from get_phy_abilities_resp */
2188         abilities &= ~mask;
2189         abilities |= phy_ab.abilities & mask;
2190
2191         phy_conf.abilities = abilities;
2192
2193         /* If link needs to go up, but the force speed is not supported,
2194          * Warn users and config the default available speeds.
2195          */
2196         if (is_up && !(force_speed & avail_speed)) {
2197                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2198                 phy_conf.link_speed = avail_speed;
2199         } else {
2200                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2201         }
2202
2203         /* PHY type mask needs to include each type except PHY type extension */
2204         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2205                 phy_type_mask |= 1 << cnt;
2206
2207         /* use get_phy_abilities_resp value for the rest */
2208         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2209         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2210                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2211                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2212         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2213         phy_conf.eee_capability = phy_ab.eee_capability;
2214         phy_conf.eeer = phy_ab.eeer_val;
2215         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2216
2217         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2218                     phy_ab.abilities, phy_ab.link_speed);
2219         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2220                     phy_conf.abilities, phy_conf.link_speed);
2221
2222         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2223         if (status)
2224                 return ret;
2225
2226         return I40E_SUCCESS;
2227 }
2228
2229 static int
2230 i40e_apply_link_speed(struct rte_eth_dev *dev)
2231 {
2232         uint8_t speed;
2233         uint8_t abilities = 0;
2234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2235         struct rte_eth_conf *conf = &dev->data->dev_conf;
2236
2237         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2238                 conf->link_speeds = ETH_LINK_SPEED_40G |
2239                                     ETH_LINK_SPEED_25G |
2240                                     ETH_LINK_SPEED_20G |
2241                                     ETH_LINK_SPEED_10G |
2242                                     ETH_LINK_SPEED_1G |
2243                                     ETH_LINK_SPEED_100M;
2244         }
2245         speed = i40e_parse_link_speeds(conf->link_speeds);
2246         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2247                      I40E_AQ_PHY_AN_ENABLED |
2248                      I40E_AQ_PHY_LINK_ENABLED;
2249
2250         return i40e_phy_conf_link(hw, abilities, speed, true);
2251 }
2252
2253 static int
2254 i40e_dev_start(struct rte_eth_dev *dev)
2255 {
2256         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2258         struct i40e_vsi *main_vsi = pf->main_vsi;
2259         int ret, i;
2260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2262         uint32_t intr_vector = 0;
2263         struct i40e_vsi *vsi;
2264
2265         hw->adapter_stopped = 0;
2266
2267         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2268                 PMD_INIT_LOG(ERR,
2269                 "Invalid link_speeds for port %u, autonegotiation disabled",
2270                               dev->data->port_id);
2271                 return -EINVAL;
2272         }
2273
2274         rte_intr_disable(intr_handle);
2275
2276         if ((rte_intr_cap_multiple(intr_handle) ||
2277              !RTE_ETH_DEV_SRIOV(dev).active) &&
2278             dev->data->dev_conf.intr_conf.rxq != 0) {
2279                 intr_vector = dev->data->nb_rx_queues;
2280                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2281                 if (ret)
2282                         return ret;
2283         }
2284
2285         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2286                 intr_handle->intr_vec =
2287                         rte_zmalloc("intr_vec",
2288                                     dev->data->nb_rx_queues * sizeof(int),
2289                                     0);
2290                 if (!intr_handle->intr_vec) {
2291                         PMD_INIT_LOG(ERR,
2292                                 "Failed to allocate %d rx_queues intr_vec",
2293                                 dev->data->nb_rx_queues);
2294                         return -ENOMEM;
2295                 }
2296         }
2297
2298         /* Initialize VSI */
2299         ret = i40e_dev_rxtx_init(pf);
2300         if (ret != I40E_SUCCESS) {
2301                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2302                 goto err_up;
2303         }
2304
2305         /* Map queues with MSIX interrupt */
2306         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2307                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2308         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2309         i40e_vsi_enable_queues_intr(main_vsi);
2310
2311         /* Map VMDQ VSI queues with MSIX interrupt */
2312         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2313                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2314                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2315                                           I40E_ITR_INDEX_DEFAULT);
2316                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2317         }
2318
2319         /* enable FDIR MSIX interrupt */
2320         if (pf->fdir.fdir_vsi) {
2321                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2322                                           I40E_ITR_INDEX_NONE);
2323                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2324         }
2325
2326         /* Enable all queues which have been configured */
2327         ret = i40e_dev_switch_queues(pf, TRUE);
2328         if (ret != I40E_SUCCESS) {
2329                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2330                 goto err_up;
2331         }
2332
2333         /* Enable receiving broadcast packets */
2334         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2335         if (ret != I40E_SUCCESS)
2336                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2337
2338         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2339                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2340                                                 true, NULL);
2341                 if (ret != I40E_SUCCESS)
2342                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2343         }
2344
2345         /* Enable the VLAN promiscuous mode. */
2346         if (pf->vfs) {
2347                 for (i = 0; i < pf->vf_num; i++) {
2348                         vsi = pf->vfs[i].vsi;
2349                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2350                                                      true, NULL);
2351                 }
2352         }
2353
2354         /* Enable mac loopback mode */
2355         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2356             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2357                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2358                 if (ret != I40E_SUCCESS) {
2359                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2360                         goto err_up;
2361                 }
2362         }
2363
2364         /* Apply link configure */
2365         ret = i40e_apply_link_speed(dev);
2366         if (I40E_SUCCESS != ret) {
2367                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2368                 goto err_up;
2369         }
2370
2371         if (!rte_intr_allow_others(intr_handle)) {
2372                 rte_intr_callback_unregister(intr_handle,
2373                                              i40e_dev_interrupt_handler,
2374                                              (void *)dev);
2375                 /* configure and enable device interrupt */
2376                 i40e_pf_config_irq0(hw, FALSE);
2377                 i40e_pf_enable_irq0(hw);
2378
2379                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2380                         PMD_INIT_LOG(INFO,
2381                                 "lsc won't enable because of no intr multiplex");
2382         } else {
2383                 ret = i40e_aq_set_phy_int_mask(hw,
2384                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2385                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2386                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2387                 if (ret != I40E_SUCCESS)
2388                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2389
2390                 /* Call get_link_info aq commond to enable/disable LSE */
2391                 i40e_dev_link_update(dev, 0);
2392         }
2393
2394         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2395                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2396                                   i40e_dev_alarm_handler, dev);
2397         } else {
2398                 /* enable uio intr after callback register */
2399                 rte_intr_enable(intr_handle);
2400         }
2401
2402         i40e_filter_restore(pf);
2403
2404         if (pf->tm_conf.root && !pf->tm_conf.committed)
2405                 PMD_DRV_LOG(WARNING,
2406                             "please call hierarchy_commit() "
2407                             "before starting the port");
2408
2409         return I40E_SUCCESS;
2410
2411 err_up:
2412         i40e_dev_switch_queues(pf, FALSE);
2413         i40e_dev_clear_queues(dev);
2414
2415         return ret;
2416 }
2417
2418 static void
2419 i40e_dev_stop(struct rte_eth_dev *dev)
2420 {
2421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2423         struct i40e_vsi *main_vsi = pf->main_vsi;
2424         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2425         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2426         int i;
2427
2428         if (hw->adapter_stopped == 1)
2429                 return;
2430
2431         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2432                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2433                 rte_intr_enable(intr_handle);
2434         }
2435
2436         /* Disable all queues */
2437         i40e_dev_switch_queues(pf, FALSE);
2438
2439         /* un-map queues with interrupt registers */
2440         i40e_vsi_disable_queues_intr(main_vsi);
2441         i40e_vsi_queues_unbind_intr(main_vsi);
2442
2443         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2444                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2445                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2446         }
2447
2448         if (pf->fdir.fdir_vsi) {
2449                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2450                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2451         }
2452         /* Clear all queues and release memory */
2453         i40e_dev_clear_queues(dev);
2454
2455         /* Set link down */
2456         i40e_dev_set_link_down(dev);
2457
2458         if (!rte_intr_allow_others(intr_handle))
2459                 /* resume to the default handler */
2460                 rte_intr_callback_register(intr_handle,
2461                                            i40e_dev_interrupt_handler,
2462                                            (void *)dev);
2463
2464         /* Clean datapath event and queue/vec mapping */
2465         rte_intr_efd_disable(intr_handle);
2466         if (intr_handle->intr_vec) {
2467                 rte_free(intr_handle->intr_vec);
2468                 intr_handle->intr_vec = NULL;
2469         }
2470
2471         /* reset hierarchy commit */
2472         pf->tm_conf.committed = false;
2473
2474         hw->adapter_stopped = 1;
2475
2476         pf->adapter->rss_reta_updated = 0;
2477 }
2478
2479 static void
2480 i40e_dev_close(struct rte_eth_dev *dev)
2481 {
2482         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2483         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2485         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2486         struct i40e_mirror_rule *p_mirror;
2487         struct i40e_filter_control_settings settings;
2488         struct rte_flow *p_flow;
2489         uint32_t reg;
2490         int i;
2491         int ret;
2492         uint8_t aq_fail = 0;
2493         int retries = 0;
2494
2495         PMD_INIT_FUNC_TRACE();
2496
2497         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2498         if (ret)
2499                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2500
2501
2502         i40e_dev_stop(dev);
2503
2504         /* Remove all mirror rules */
2505         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2506                 ret = i40e_aq_del_mirror_rule(hw,
2507                                               pf->main_vsi->veb->seid,
2508                                               p_mirror->rule_type,
2509                                               p_mirror->entries,
2510                                               p_mirror->num_entries,
2511                                               p_mirror->id);
2512                 if (ret < 0)
2513                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2514                                     "status = %d, aq_err = %d.", ret,
2515                                     hw->aq.asq_last_status);
2516
2517                 /* remove mirror software resource anyway */
2518                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2519                 rte_free(p_mirror);
2520                 pf->nb_mirror_rule--;
2521         }
2522
2523         i40e_dev_free_queues(dev);
2524
2525         /* Disable interrupt */
2526         i40e_pf_disable_irq0(hw);
2527         rte_intr_disable(intr_handle);
2528
2529         /*
2530          * Only legacy filter API needs the following fdir config. So when the
2531          * legacy filter API is deprecated, the following code should also be
2532          * removed.
2533          */
2534         i40e_fdir_teardown(pf);
2535
2536         /* shutdown and destroy the HMC */
2537         i40e_shutdown_lan_hmc(hw);
2538
2539         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2540                 i40e_vsi_release(pf->vmdq[i].vsi);
2541                 pf->vmdq[i].vsi = NULL;
2542         }
2543         rte_free(pf->vmdq);
2544         pf->vmdq = NULL;
2545
2546         /* release all the existing VSIs and VEBs */
2547         i40e_vsi_release(pf->main_vsi);
2548
2549         /* shutdown the adminq */
2550         i40e_aq_queue_shutdown(hw, true);
2551         i40e_shutdown_adminq(hw);
2552
2553         i40e_res_pool_destroy(&pf->qp_pool);
2554         i40e_res_pool_destroy(&pf->msix_pool);
2555
2556         /* Disable flexible payload in global configuration */
2557         if (!pf->support_multi_driver)
2558                 i40e_flex_payload_reg_set_default(hw);
2559
2560         /* force a PF reset to clean anything leftover */
2561         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2562         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2563                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2564         I40E_WRITE_FLUSH(hw);
2565
2566         dev->dev_ops = NULL;
2567         dev->rx_pkt_burst = NULL;
2568         dev->tx_pkt_burst = NULL;
2569
2570         /* Clear PXE mode */
2571         i40e_clear_pxe_mode(hw);
2572
2573         /* Unconfigure filter control */
2574         memset(&settings, 0, sizeof(settings));
2575         ret = i40e_set_filter_control(hw, &settings);
2576         if (ret)
2577                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2578                                         ret);
2579
2580         /* Disable flow control */
2581         hw->fc.requested_mode = I40E_FC_NONE;
2582         i40e_set_fc(hw, &aq_fail, TRUE);
2583
2584         /* uninitialize pf host driver */
2585         i40e_pf_host_uninit(dev);
2586
2587         do {
2588                 ret = rte_intr_callback_unregister(intr_handle,
2589                                 i40e_dev_interrupt_handler, dev);
2590                 if (ret >= 0) {
2591                         break;
2592                 } else if (ret != -EAGAIN) {
2593                         PMD_INIT_LOG(ERR,
2594                                  "intr callback unregister failed: %d",
2595                                  ret);
2596                 }
2597                 i40e_msec_delay(500);
2598         } while (retries++ < 5);
2599
2600         i40e_rm_ethtype_filter_list(pf);
2601         i40e_rm_tunnel_filter_list(pf);
2602         i40e_rm_fdir_filter_list(pf);
2603
2604         /* Remove all flows */
2605         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2606                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2607                 rte_free(p_flow);
2608         }
2609
2610         /* Remove all Traffic Manager configuration */
2611         i40e_tm_conf_uninit(dev);
2612
2613         hw->adapter_closed = 1;
2614 }
2615
2616 /*
2617  * Reset PF device only to re-initialize resources in PMD layer
2618  */
2619 static int
2620 i40e_dev_reset(struct rte_eth_dev *dev)
2621 {
2622         int ret;
2623
2624         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2625          * its VF to make them align with it. The detailed notification
2626          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2627          * To avoid unexpected behavior in VF, currently reset of PF with
2628          * SR-IOV activation is not supported. It might be supported later.
2629          */
2630         if (dev->data->sriov.active)
2631                 return -ENOTSUP;
2632
2633         ret = eth_i40e_dev_uninit(dev);
2634         if (ret)
2635                 return ret;
2636
2637         ret = eth_i40e_dev_init(dev, NULL);
2638
2639         return ret;
2640 }
2641
2642 static int
2643 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2644 {
2645         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2647         struct i40e_vsi *vsi = pf->main_vsi;
2648         int status;
2649
2650         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2651                                                      true, NULL, true);
2652         if (status != I40E_SUCCESS) {
2653                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2654                 return -EAGAIN;
2655         }
2656
2657         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2658                                                         TRUE, NULL);
2659         if (status != I40E_SUCCESS) {
2660                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2661                 /* Rollback unicast promiscuous mode */
2662                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2663                                                     false, NULL, true);
2664                 return -EAGAIN;
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int
2671 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2672 {
2673         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         struct i40e_vsi *vsi = pf->main_vsi;
2676         int status;
2677
2678         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2679                                                      false, NULL, true);
2680         if (status != I40E_SUCCESS) {
2681                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2682                 return -EAGAIN;
2683         }
2684
2685         /* must remain in all_multicast mode */
2686         if (dev->data->all_multicast == 1)
2687                 return 0;
2688
2689         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2690                                                         false, NULL);
2691         if (status != I40E_SUCCESS) {
2692                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2693                 /* Rollback unicast promiscuous mode */
2694                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2695                                                     true, NULL, true);
2696                 return -EAGAIN;
2697         }
2698
2699         return 0;
2700 }
2701
2702 static int
2703 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2704 {
2705         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2707         struct i40e_vsi *vsi = pf->main_vsi;
2708         int ret;
2709
2710         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2711         if (ret != I40E_SUCCESS) {
2712                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2713                 return -EAGAIN;
2714         }
2715
2716         return 0;
2717 }
2718
2719 static int
2720 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2721 {
2722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2724         struct i40e_vsi *vsi = pf->main_vsi;
2725         int ret;
2726
2727         if (dev->data->promiscuous == 1)
2728                 return 0; /* must remain in all_multicast mode */
2729
2730         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2731                                 vsi->seid, FALSE, NULL);
2732         if (ret != I40E_SUCCESS) {
2733                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2734                 return -EAGAIN;
2735         }
2736
2737         return 0;
2738 }
2739
2740 /*
2741  * Set device link up.
2742  */
2743 static int
2744 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2745 {
2746         /* re-apply link speed setting */
2747         return i40e_apply_link_speed(dev);
2748 }
2749
2750 /*
2751  * Set device link down.
2752  */
2753 static int
2754 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2755 {
2756         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2757         uint8_t abilities = 0;
2758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759
2760         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2761         return i40e_phy_conf_link(hw, abilities, speed, false);
2762 }
2763
2764 static __rte_always_inline void
2765 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2766 {
2767 /* Link status registers and values*/
2768 #define I40E_PRTMAC_LINKSTA             0x001E2420
2769 #define I40E_REG_LINK_UP                0x40000080
2770 #define I40E_PRTMAC_MACC                0x001E24E0
2771 #define I40E_REG_MACC_25GB              0x00020000
2772 #define I40E_REG_SPEED_MASK             0x38000000
2773 #define I40E_REG_SPEED_0                0x00000000
2774 #define I40E_REG_SPEED_1                0x08000000
2775 #define I40E_REG_SPEED_2                0x10000000
2776 #define I40E_REG_SPEED_3                0x18000000
2777 #define I40E_REG_SPEED_4                0x20000000
2778         uint32_t link_speed;
2779         uint32_t reg_val;
2780
2781         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2782         link_speed = reg_val & I40E_REG_SPEED_MASK;
2783         reg_val &= I40E_REG_LINK_UP;
2784         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2785
2786         if (unlikely(link->link_status == 0))
2787                 return;
2788
2789         /* Parse the link status */
2790         switch (link_speed) {
2791         case I40E_REG_SPEED_0:
2792                 link->link_speed = ETH_SPEED_NUM_100M;
2793                 break;
2794         case I40E_REG_SPEED_1:
2795                 link->link_speed = ETH_SPEED_NUM_1G;
2796                 break;
2797         case I40E_REG_SPEED_2:
2798                 if (hw->mac.type == I40E_MAC_X722)
2799                         link->link_speed = ETH_SPEED_NUM_2_5G;
2800                 else
2801                         link->link_speed = ETH_SPEED_NUM_10G;
2802                 break;
2803         case I40E_REG_SPEED_3:
2804                 if (hw->mac.type == I40E_MAC_X722) {
2805                         link->link_speed = ETH_SPEED_NUM_5G;
2806                 } else {
2807                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2808
2809                         if (reg_val & I40E_REG_MACC_25GB)
2810                                 link->link_speed = ETH_SPEED_NUM_25G;
2811                         else
2812                                 link->link_speed = ETH_SPEED_NUM_40G;
2813                 }
2814                 break;
2815         case I40E_REG_SPEED_4:
2816                 if (hw->mac.type == I40E_MAC_X722)
2817                         link->link_speed = ETH_SPEED_NUM_10G;
2818                 else
2819                         link->link_speed = ETH_SPEED_NUM_20G;
2820                 break;
2821         default:
2822                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2823                 break;
2824         }
2825 }
2826
2827 static __rte_always_inline void
2828 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2829         bool enable_lse, int wait_to_complete)
2830 {
2831 #define CHECK_INTERVAL             100  /* 100ms */
2832 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2833         uint32_t rep_cnt = MAX_REPEAT_TIME;
2834         struct i40e_link_status link_status;
2835         int status;
2836
2837         memset(&link_status, 0, sizeof(link_status));
2838
2839         do {
2840                 memset(&link_status, 0, sizeof(link_status));
2841
2842                 /* Get link status information from hardware */
2843                 status = i40e_aq_get_link_info(hw, enable_lse,
2844                                                 &link_status, NULL);
2845                 if (unlikely(status != I40E_SUCCESS)) {
2846                         link->link_speed = ETH_SPEED_NUM_NONE;
2847                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2848                         PMD_DRV_LOG(ERR, "Failed to get link info");
2849                         return;
2850                 }
2851
2852                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2853                 if (!wait_to_complete || link->link_status)
2854                         break;
2855
2856                 rte_delay_ms(CHECK_INTERVAL);
2857         } while (--rep_cnt);
2858
2859         /* Parse the link status */
2860         switch (link_status.link_speed) {
2861         case I40E_LINK_SPEED_100MB:
2862                 link->link_speed = ETH_SPEED_NUM_100M;
2863                 break;
2864         case I40E_LINK_SPEED_1GB:
2865                 link->link_speed = ETH_SPEED_NUM_1G;
2866                 break;
2867         case I40E_LINK_SPEED_10GB:
2868                 link->link_speed = ETH_SPEED_NUM_10G;
2869                 break;
2870         case I40E_LINK_SPEED_20GB:
2871                 link->link_speed = ETH_SPEED_NUM_20G;
2872                 break;
2873         case I40E_LINK_SPEED_25GB:
2874                 link->link_speed = ETH_SPEED_NUM_25G;
2875                 break;
2876         case I40E_LINK_SPEED_40GB:
2877                 link->link_speed = ETH_SPEED_NUM_40G;
2878                 break;
2879         default:
2880                 link->link_speed = ETH_SPEED_NUM_NONE;
2881                 break;
2882         }
2883 }
2884
2885 int
2886 i40e_dev_link_update(struct rte_eth_dev *dev,
2887                      int wait_to_complete)
2888 {
2889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2890         struct rte_eth_link link;
2891         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2892         int ret;
2893
2894         memset(&link, 0, sizeof(link));
2895
2896         /* i40e uses full duplex only */
2897         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2898         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2899                         ETH_LINK_SPEED_FIXED);
2900
2901         if (!wait_to_complete && !enable_lse)
2902                 update_link_reg(hw, &link);
2903         else
2904                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2905
2906         ret = rte_eth_linkstatus_set(dev, &link);
2907         i40e_notify_all_vfs_link_status(dev);
2908
2909         return ret;
2910 }
2911
2912 /* Get all the statistics of a VSI */
2913 void
2914 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2915 {
2916         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2917         struct i40e_eth_stats *nes = &vsi->eth_stats;
2918         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2919         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2920
2921         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2922                             vsi->offset_loaded, &oes->rx_bytes,
2923                             &nes->rx_bytes);
2924         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2925                             vsi->offset_loaded, &oes->rx_unicast,
2926                             &nes->rx_unicast);
2927         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2928                             vsi->offset_loaded, &oes->rx_multicast,
2929                             &nes->rx_multicast);
2930         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2931                             vsi->offset_loaded, &oes->rx_broadcast,
2932                             &nes->rx_broadcast);
2933         /* exclude CRC bytes */
2934         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2935                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2936
2937         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2938                             &oes->rx_discards, &nes->rx_discards);
2939         /* GLV_REPC not supported */
2940         /* GLV_RMPC not supported */
2941         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2942                             &oes->rx_unknown_protocol,
2943                             &nes->rx_unknown_protocol);
2944         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2945                             vsi->offset_loaded, &oes->tx_bytes,
2946                             &nes->tx_bytes);
2947         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2948                             vsi->offset_loaded, &oes->tx_unicast,
2949                             &nes->tx_unicast);
2950         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2951                             vsi->offset_loaded, &oes->tx_multicast,
2952                             &nes->tx_multicast);
2953         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2954                             vsi->offset_loaded,  &oes->tx_broadcast,
2955                             &nes->tx_broadcast);
2956         /* GLV_TDPC not supported */
2957         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2958                             &oes->tx_errors, &nes->tx_errors);
2959         vsi->offset_loaded = true;
2960
2961         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2962                     vsi->vsi_id);
2963         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2964         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2965         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2966         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2967         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2968         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2969                     nes->rx_unknown_protocol);
2970         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2971         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2972         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2973         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2974         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2975         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2976         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2977                     vsi->vsi_id);
2978 }
2979
2980 static void
2981 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2982 {
2983         unsigned int i;
2984         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2985         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2986
2987         /* Get rx/tx bytes of internal transfer packets */
2988         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2989                         I40E_GLV_GORCL(hw->port),
2990                         pf->offset_loaded,
2991                         &pf->internal_stats_offset.rx_bytes,
2992                         &pf->internal_stats.rx_bytes);
2993
2994         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2995                         I40E_GLV_GOTCL(hw->port),
2996                         pf->offset_loaded,
2997                         &pf->internal_stats_offset.tx_bytes,
2998                         &pf->internal_stats.tx_bytes);
2999         /* Get total internal rx packet count */
3000         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3001                             I40E_GLV_UPRCL(hw->port),
3002                             pf->offset_loaded,
3003                             &pf->internal_stats_offset.rx_unicast,
3004                             &pf->internal_stats.rx_unicast);
3005         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3006                             I40E_GLV_MPRCL(hw->port),
3007                             pf->offset_loaded,
3008                             &pf->internal_stats_offset.rx_multicast,
3009                             &pf->internal_stats.rx_multicast);
3010         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3011                             I40E_GLV_BPRCL(hw->port),
3012                             pf->offset_loaded,
3013                             &pf->internal_stats_offset.rx_broadcast,
3014                             &pf->internal_stats.rx_broadcast);
3015         /* Get total internal tx packet count */
3016         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3017                             I40E_GLV_UPTCL(hw->port),
3018                             pf->offset_loaded,
3019                             &pf->internal_stats_offset.tx_unicast,
3020                             &pf->internal_stats.tx_unicast);
3021         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3022                             I40E_GLV_MPTCL(hw->port),
3023                             pf->offset_loaded,
3024                             &pf->internal_stats_offset.tx_multicast,
3025                             &pf->internal_stats.tx_multicast);
3026         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3027                             I40E_GLV_BPTCL(hw->port),
3028                             pf->offset_loaded,
3029                             &pf->internal_stats_offset.tx_broadcast,
3030                             &pf->internal_stats.tx_broadcast);
3031
3032         /* exclude CRC size */
3033         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3034                 pf->internal_stats.rx_multicast +
3035                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3036
3037         /* Get statistics of struct i40e_eth_stats */
3038         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3039                             I40E_GLPRT_GORCL(hw->port),
3040                             pf->offset_loaded, &os->eth.rx_bytes,
3041                             &ns->eth.rx_bytes);
3042         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3043                             I40E_GLPRT_UPRCL(hw->port),
3044                             pf->offset_loaded, &os->eth.rx_unicast,
3045                             &ns->eth.rx_unicast);
3046         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3047                             I40E_GLPRT_MPRCL(hw->port),
3048                             pf->offset_loaded, &os->eth.rx_multicast,
3049                             &ns->eth.rx_multicast);
3050         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3051                             I40E_GLPRT_BPRCL(hw->port),
3052                             pf->offset_loaded, &os->eth.rx_broadcast,
3053                             &ns->eth.rx_broadcast);
3054         /* Workaround: CRC size should not be included in byte statistics,
3055          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3056          * packet.
3057          */
3058         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3059                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3060
3061         /* exclude internal rx bytes
3062          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3063          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3064          * value.
3065          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3066          */
3067         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3068                 ns->eth.rx_bytes = 0;
3069         else
3070                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3071
3072         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3073                 ns->eth.rx_unicast = 0;
3074         else
3075                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3076
3077         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3078                 ns->eth.rx_multicast = 0;
3079         else
3080                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3081
3082         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3083                 ns->eth.rx_broadcast = 0;
3084         else
3085                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3086
3087         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3088                             pf->offset_loaded, &os->eth.rx_discards,
3089                             &ns->eth.rx_discards);
3090         /* GLPRT_REPC not supported */
3091         /* GLPRT_RMPC not supported */
3092         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3093                             pf->offset_loaded,
3094                             &os->eth.rx_unknown_protocol,
3095                             &ns->eth.rx_unknown_protocol);
3096         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3097                             I40E_GLPRT_GOTCL(hw->port),
3098                             pf->offset_loaded, &os->eth.tx_bytes,
3099                             &ns->eth.tx_bytes);
3100         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3101                             I40E_GLPRT_UPTCL(hw->port),
3102                             pf->offset_loaded, &os->eth.tx_unicast,
3103                             &ns->eth.tx_unicast);
3104         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3105                             I40E_GLPRT_MPTCL(hw->port),
3106                             pf->offset_loaded, &os->eth.tx_multicast,
3107                             &ns->eth.tx_multicast);
3108         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3109                             I40E_GLPRT_BPTCL(hw->port),
3110                             pf->offset_loaded, &os->eth.tx_broadcast,
3111                             &ns->eth.tx_broadcast);
3112         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3113                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3114
3115         /* exclude internal tx bytes
3116          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3117          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3118          * value.
3119          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3120          */
3121         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3122                 ns->eth.tx_bytes = 0;
3123         else
3124                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3125
3126         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3127                 ns->eth.tx_unicast = 0;
3128         else
3129                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3130
3131         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3132                 ns->eth.tx_multicast = 0;
3133         else
3134                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3135
3136         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3137                 ns->eth.tx_broadcast = 0;
3138         else
3139                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3140
3141         /* GLPRT_TEPC not supported */
3142
3143         /* additional port specific stats */
3144         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3145                             pf->offset_loaded, &os->tx_dropped_link_down,
3146                             &ns->tx_dropped_link_down);
3147         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3148                             pf->offset_loaded, &os->crc_errors,
3149                             &ns->crc_errors);
3150         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3151                             pf->offset_loaded, &os->illegal_bytes,
3152                             &ns->illegal_bytes);
3153         /* GLPRT_ERRBC not supported */
3154         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3155                             pf->offset_loaded, &os->mac_local_faults,
3156                             &ns->mac_local_faults);
3157         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3158                             pf->offset_loaded, &os->mac_remote_faults,
3159                             &ns->mac_remote_faults);
3160         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3161                             pf->offset_loaded, &os->rx_length_errors,
3162                             &ns->rx_length_errors);
3163         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3164                             pf->offset_loaded, &os->link_xon_rx,
3165                             &ns->link_xon_rx);
3166         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3167                             pf->offset_loaded, &os->link_xoff_rx,
3168                             &ns->link_xoff_rx);
3169         for (i = 0; i < 8; i++) {
3170                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3171                                     pf->offset_loaded,
3172                                     &os->priority_xon_rx[i],
3173                                     &ns->priority_xon_rx[i]);
3174                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3175                                     pf->offset_loaded,
3176                                     &os->priority_xoff_rx[i],
3177                                     &ns->priority_xoff_rx[i]);
3178         }
3179         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3180                             pf->offset_loaded, &os->link_xon_tx,
3181                             &ns->link_xon_tx);
3182         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3183                             pf->offset_loaded, &os->link_xoff_tx,
3184                             &ns->link_xoff_tx);
3185         for (i = 0; i < 8; i++) {
3186                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3187                                     pf->offset_loaded,
3188                                     &os->priority_xon_tx[i],
3189                                     &ns->priority_xon_tx[i]);
3190                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3191                                     pf->offset_loaded,
3192                                     &os->priority_xoff_tx[i],
3193                                     &ns->priority_xoff_tx[i]);
3194                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3195                                     pf->offset_loaded,
3196                                     &os->priority_xon_2_xoff[i],
3197                                     &ns->priority_xon_2_xoff[i]);
3198         }
3199         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3200                             I40E_GLPRT_PRC64L(hw->port),
3201                             pf->offset_loaded, &os->rx_size_64,
3202                             &ns->rx_size_64);
3203         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3204                             I40E_GLPRT_PRC127L(hw->port),
3205                             pf->offset_loaded, &os->rx_size_127,
3206                             &ns->rx_size_127);
3207         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3208                             I40E_GLPRT_PRC255L(hw->port),
3209                             pf->offset_loaded, &os->rx_size_255,
3210                             &ns->rx_size_255);
3211         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3212                             I40E_GLPRT_PRC511L(hw->port),
3213                             pf->offset_loaded, &os->rx_size_511,
3214                             &ns->rx_size_511);
3215         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3216                             I40E_GLPRT_PRC1023L(hw->port),
3217                             pf->offset_loaded, &os->rx_size_1023,
3218                             &ns->rx_size_1023);
3219         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3220                             I40E_GLPRT_PRC1522L(hw->port),
3221                             pf->offset_loaded, &os->rx_size_1522,
3222                             &ns->rx_size_1522);
3223         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3224                             I40E_GLPRT_PRC9522L(hw->port),
3225                             pf->offset_loaded, &os->rx_size_big,
3226                             &ns->rx_size_big);
3227         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3228                             pf->offset_loaded, &os->rx_undersize,
3229                             &ns->rx_undersize);
3230         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3231                             pf->offset_loaded, &os->rx_fragments,
3232                             &ns->rx_fragments);
3233         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3234                             pf->offset_loaded, &os->rx_oversize,
3235                             &ns->rx_oversize);
3236         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3237                             pf->offset_loaded, &os->rx_jabber,
3238                             &ns->rx_jabber);
3239         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3240                             I40E_GLPRT_PTC64L(hw->port),
3241                             pf->offset_loaded, &os->tx_size_64,
3242                             &ns->tx_size_64);
3243         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3244                             I40E_GLPRT_PTC127L(hw->port),
3245                             pf->offset_loaded, &os->tx_size_127,
3246                             &ns->tx_size_127);
3247         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3248                             I40E_GLPRT_PTC255L(hw->port),
3249                             pf->offset_loaded, &os->tx_size_255,
3250                             &ns->tx_size_255);
3251         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3252                             I40E_GLPRT_PTC511L(hw->port),
3253                             pf->offset_loaded, &os->tx_size_511,
3254                             &ns->tx_size_511);
3255         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3256                             I40E_GLPRT_PTC1023L(hw->port),
3257                             pf->offset_loaded, &os->tx_size_1023,
3258                             &ns->tx_size_1023);
3259         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3260                             I40E_GLPRT_PTC1522L(hw->port),
3261                             pf->offset_loaded, &os->tx_size_1522,
3262                             &ns->tx_size_1522);
3263         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3264                             I40E_GLPRT_PTC9522L(hw->port),
3265                             pf->offset_loaded, &os->tx_size_big,
3266                             &ns->tx_size_big);
3267         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3268                            pf->offset_loaded,
3269                            &os->fd_sb_match, &ns->fd_sb_match);
3270         /* GLPRT_MSPDC not supported */
3271         /* GLPRT_XEC not supported */
3272
3273         pf->offset_loaded = true;
3274
3275         if (pf->main_vsi)
3276                 i40e_update_vsi_stats(pf->main_vsi);
3277 }
3278
3279 /* Get all statistics of a port */
3280 static int
3281 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3282 {
3283         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3286         struct i40e_vsi *vsi;
3287         unsigned i;
3288
3289         /* call read registers - updates values, now write them to struct */
3290         i40e_read_stats_registers(pf, hw);
3291
3292         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3293                         pf->main_vsi->eth_stats.rx_multicast +
3294                         pf->main_vsi->eth_stats.rx_broadcast -
3295                         pf->main_vsi->eth_stats.rx_discards;
3296         stats->opackets = ns->eth.tx_unicast +
3297                         ns->eth.tx_multicast +
3298                         ns->eth.tx_broadcast;
3299         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3300         stats->obytes   = ns->eth.tx_bytes;
3301         stats->oerrors  = ns->eth.tx_errors +
3302                         pf->main_vsi->eth_stats.tx_errors;
3303
3304         /* Rx Errors */
3305         stats->imissed  = ns->eth.rx_discards +
3306                         pf->main_vsi->eth_stats.rx_discards;
3307         stats->ierrors  = ns->crc_errors +
3308                         ns->rx_length_errors + ns->rx_undersize +
3309                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3310
3311         if (pf->vfs) {
3312                 for (i = 0; i < pf->vf_num; i++) {
3313                         vsi = pf->vfs[i].vsi;
3314                         i40e_update_vsi_stats(vsi);
3315
3316                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3317                                         vsi->eth_stats.rx_multicast +
3318                                         vsi->eth_stats.rx_broadcast -
3319                                         vsi->eth_stats.rx_discards);
3320                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3321                         stats->oerrors  += vsi->eth_stats.tx_errors;
3322                         stats->imissed  += vsi->eth_stats.rx_discards;
3323                 }
3324         }
3325
3326         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3327         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3328         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3329         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3330         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3331         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3332         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3333                     ns->eth.rx_unknown_protocol);
3334         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3335         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3336         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3337         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3338         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3339         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3340
3341         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3342                     ns->tx_dropped_link_down);
3343         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3344         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3345                     ns->illegal_bytes);
3346         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3347         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3348                     ns->mac_local_faults);
3349         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3350                     ns->mac_remote_faults);
3351         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3352                     ns->rx_length_errors);
3353         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3354         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3355         for (i = 0; i < 8; i++) {
3356                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3357                                 i, ns->priority_xon_rx[i]);
3358                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3359                                 i, ns->priority_xoff_rx[i]);
3360         }
3361         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3362         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3363         for (i = 0; i < 8; i++) {
3364                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3365                                 i, ns->priority_xon_tx[i]);
3366                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3367                                 i, ns->priority_xoff_tx[i]);
3368                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3369                                 i, ns->priority_xon_2_xoff[i]);
3370         }
3371         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3372         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3373         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3374         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3375         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3376         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3377         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3378         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3379         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3380         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3381         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3382         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3383         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3384         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3385         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3386         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3387         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3388         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3389         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3390                         ns->mac_short_packet_dropped);
3391         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3392                     ns->checksum_error);
3393         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3394         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3395         return 0;
3396 }
3397
3398 /* Reset the statistics */
3399 static int
3400 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3401 {
3402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404
3405         /* Mark PF and VSI stats to update the offset, aka "reset" */
3406         pf->offset_loaded = false;
3407         if (pf->main_vsi)
3408                 pf->main_vsi->offset_loaded = false;
3409
3410         /* read the stats, reading current register values into offset */
3411         i40e_read_stats_registers(pf, hw);
3412
3413         return 0;
3414 }
3415
3416 static uint32_t
3417 i40e_xstats_calc_num(void)
3418 {
3419         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3420                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3421                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3422 }
3423
3424 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3425                                      struct rte_eth_xstat_name *xstats_names,
3426                                      __rte_unused unsigned limit)
3427 {
3428         unsigned count = 0;
3429         unsigned i, prio;
3430
3431         if (xstats_names == NULL)
3432                 return i40e_xstats_calc_num();
3433
3434         /* Note: limit checked in rte_eth_xstats_names() */
3435
3436         /* Get stats from i40e_eth_stats struct */
3437         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3438                 strlcpy(xstats_names[count].name,
3439                         rte_i40e_stats_strings[i].name,
3440                         sizeof(xstats_names[count].name));
3441                 count++;
3442         }
3443
3444         /* Get individiual stats from i40e_hw_port struct */
3445         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3446                 strlcpy(xstats_names[count].name,
3447                         rte_i40e_hw_port_strings[i].name,
3448                         sizeof(xstats_names[count].name));
3449                 count++;
3450         }
3451
3452         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3453                 for (prio = 0; prio < 8; prio++) {
3454                         snprintf(xstats_names[count].name,
3455                                  sizeof(xstats_names[count].name),
3456                                  "rx_priority%u_%s", prio,
3457                                  rte_i40e_rxq_prio_strings[i].name);
3458                         count++;
3459                 }
3460         }
3461
3462         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3463                 for (prio = 0; prio < 8; prio++) {
3464                         snprintf(xstats_names[count].name,
3465                                  sizeof(xstats_names[count].name),
3466                                  "tx_priority%u_%s", prio,
3467                                  rte_i40e_txq_prio_strings[i].name);
3468                         count++;
3469                 }
3470         }
3471         return count;
3472 }
3473
3474 static int
3475 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3476                     unsigned n)
3477 {
3478         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3479         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3480         unsigned i, count, prio;
3481         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3482
3483         count = i40e_xstats_calc_num();
3484         if (n < count)
3485                 return count;
3486
3487         i40e_read_stats_registers(pf, hw);
3488
3489         if (xstats == NULL)
3490                 return 0;
3491
3492         count = 0;
3493
3494         /* Get stats from i40e_eth_stats struct */
3495         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3496                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3497                         rte_i40e_stats_strings[i].offset);
3498                 xstats[count].id = count;
3499                 count++;
3500         }
3501
3502         /* Get individiual stats from i40e_hw_port struct */
3503         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3504                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3505                         rte_i40e_hw_port_strings[i].offset);
3506                 xstats[count].id = count;
3507                 count++;
3508         }
3509
3510         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3511                 for (prio = 0; prio < 8; prio++) {
3512                         xstats[count].value =
3513                                 *(uint64_t *)(((char *)hw_stats) +
3514                                 rte_i40e_rxq_prio_strings[i].offset +
3515                                 (sizeof(uint64_t) * prio));
3516                         xstats[count].id = count;
3517                         count++;
3518                 }
3519         }
3520
3521         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3522                 for (prio = 0; prio < 8; prio++) {
3523                         xstats[count].value =
3524                                 *(uint64_t *)(((char *)hw_stats) +
3525                                 rte_i40e_txq_prio_strings[i].offset +
3526                                 (sizeof(uint64_t) * prio));
3527                         xstats[count].id = count;
3528                         count++;
3529                 }
3530         }
3531
3532         return count;
3533 }
3534
3535 static int
3536 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3537 {
3538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3539         u32 full_ver;
3540         u8 ver, patch;
3541         u16 build;
3542         int ret;
3543
3544         full_ver = hw->nvm.oem_ver;
3545         ver = (u8)(full_ver >> 24);
3546         build = (u16)((full_ver >> 8) & 0xffff);
3547         patch = (u8)(full_ver & 0xff);
3548
3549         ret = snprintf(fw_version, fw_size,
3550                  "%d.%d%d 0x%08x %d.%d.%d",
3551                  ((hw->nvm.version >> 12) & 0xf),
3552                  ((hw->nvm.version >> 4) & 0xff),
3553                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3554                  ver, build, patch);
3555
3556         ret += 1; /* add the size of '\0' */
3557         if (fw_size < (u32)ret)
3558                 return ret;
3559         else
3560                 return 0;
3561 }
3562
3563 /*
3564  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3565  * the Rx data path does not hang if the FW LLDP is stopped.
3566  * return true if lldp need to stop
3567  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3568  */
3569 static bool
3570 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3571 {
3572         double nvm_ver;
3573         char ver_str[64] = {0};
3574         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3575
3576         i40e_fw_version_get(dev, ver_str, 64);
3577         nvm_ver = atof(ver_str);
3578         if ((hw->mac.type == I40E_MAC_X722 ||
3579              hw->mac.type == I40E_MAC_X722_VF) &&
3580              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3581                 return true;
3582         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3583                 return true;
3584
3585         return false;
3586 }
3587
3588 static int
3589 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3590 {
3591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3593         struct i40e_vsi *vsi = pf->main_vsi;
3594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3595
3596         dev_info->max_rx_queues = vsi->nb_qps;
3597         dev_info->max_tx_queues = vsi->nb_qps;
3598         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3599         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3600         dev_info->max_mac_addrs = vsi->max_macaddrs;
3601         dev_info->max_vfs = pci_dev->max_vfs;
3602         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3603         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3604         dev_info->rx_queue_offload_capa = 0;
3605         dev_info->rx_offload_capa =
3606                 DEV_RX_OFFLOAD_VLAN_STRIP |
3607                 DEV_RX_OFFLOAD_QINQ_STRIP |
3608                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3609                 DEV_RX_OFFLOAD_UDP_CKSUM |
3610                 DEV_RX_OFFLOAD_TCP_CKSUM |
3611                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3612                 DEV_RX_OFFLOAD_KEEP_CRC |
3613                 DEV_RX_OFFLOAD_SCATTER |
3614                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3615                 DEV_RX_OFFLOAD_VLAN_FILTER |
3616                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3617
3618         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3619         dev_info->tx_offload_capa =
3620                 DEV_TX_OFFLOAD_VLAN_INSERT |
3621                 DEV_TX_OFFLOAD_QINQ_INSERT |
3622                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3623                 DEV_TX_OFFLOAD_UDP_CKSUM |
3624                 DEV_TX_OFFLOAD_TCP_CKSUM |
3625                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3626                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3627                 DEV_TX_OFFLOAD_TCP_TSO |
3628                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3629                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3630                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3631                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3632                 DEV_TX_OFFLOAD_MULTI_SEGS |
3633                 dev_info->tx_queue_offload_capa;
3634         dev_info->dev_capa =
3635                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3636                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3637
3638         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3639                                                 sizeof(uint32_t);
3640         dev_info->reta_size = pf->hash_lut_size;
3641         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3642
3643         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3644                 .rx_thresh = {
3645                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3646                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3647                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3648                 },
3649                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3650                 .rx_drop_en = 0,
3651                 .offloads = 0,
3652         };
3653
3654         dev_info->default_txconf = (struct rte_eth_txconf) {
3655                 .tx_thresh = {
3656                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3657                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3658                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3659                 },
3660                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3661                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3662                 .offloads = 0,
3663         };
3664
3665         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3666                 .nb_max = I40E_MAX_RING_DESC,
3667                 .nb_min = I40E_MIN_RING_DESC,
3668                 .nb_align = I40E_ALIGN_RING_DESC,
3669         };
3670
3671         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3672                 .nb_max = I40E_MAX_RING_DESC,
3673                 .nb_min = I40E_MIN_RING_DESC,
3674                 .nb_align = I40E_ALIGN_RING_DESC,
3675                 .nb_seg_max = I40E_TX_MAX_SEG,
3676                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3677         };
3678
3679         if (pf->flags & I40E_FLAG_VMDQ) {
3680                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3681                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3682                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3683                                                 pf->max_nb_vmdq_vsi;
3684                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3685                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3686                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3687         }
3688
3689         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3690                 /* For XL710 */
3691                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3692                 dev_info->default_rxportconf.nb_queues = 2;
3693                 dev_info->default_txportconf.nb_queues = 2;
3694                 if (dev->data->nb_rx_queues == 1)
3695                         dev_info->default_rxportconf.ring_size = 2048;
3696                 else
3697                         dev_info->default_rxportconf.ring_size = 1024;
3698                 if (dev->data->nb_tx_queues == 1)
3699                         dev_info->default_txportconf.ring_size = 1024;
3700                 else
3701                         dev_info->default_txportconf.ring_size = 512;
3702
3703         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3704                 /* For XXV710 */
3705                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3706                 dev_info->default_rxportconf.nb_queues = 1;
3707                 dev_info->default_txportconf.nb_queues = 1;
3708                 dev_info->default_rxportconf.ring_size = 256;
3709                 dev_info->default_txportconf.ring_size = 256;
3710         } else {
3711                 /* For X710 */
3712                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3713                 dev_info->default_rxportconf.nb_queues = 1;
3714                 dev_info->default_txportconf.nb_queues = 1;
3715                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3716                         dev_info->default_rxportconf.ring_size = 512;
3717                         dev_info->default_txportconf.ring_size = 256;
3718                 } else {
3719                         dev_info->default_rxportconf.ring_size = 256;
3720                         dev_info->default_txportconf.ring_size = 256;
3721                 }
3722         }
3723         dev_info->default_rxportconf.burst_size = 32;
3724         dev_info->default_txportconf.burst_size = 32;
3725
3726         return 0;
3727 }
3728
3729 static int
3730 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3731 {
3732         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3733         struct i40e_vsi *vsi = pf->main_vsi;
3734         PMD_INIT_FUNC_TRACE();
3735
3736         if (on)
3737                 return i40e_vsi_add_vlan(vsi, vlan_id);
3738         else
3739                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3740 }
3741
3742 static int
3743 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3744                                 enum rte_vlan_type vlan_type,
3745                                 uint16_t tpid, int qinq)
3746 {
3747         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3748         uint64_t reg_r = 0;
3749         uint64_t reg_w = 0;
3750         uint16_t reg_id = 3;
3751         int ret;
3752
3753         if (qinq) {
3754                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3755                         reg_id = 2;
3756         }
3757
3758         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3759                                           &reg_r, NULL);
3760         if (ret != I40E_SUCCESS) {
3761                 PMD_DRV_LOG(ERR,
3762                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3763                            reg_id);
3764                 return -EIO;
3765         }
3766         PMD_DRV_LOG(DEBUG,
3767                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3768                     reg_id, reg_r);
3769
3770         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3771         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3772         if (reg_r == reg_w) {
3773                 PMD_DRV_LOG(DEBUG, "No need to write");
3774                 return 0;
3775         }
3776
3777         ret = i40e_aq_debug_write_global_register(hw,
3778                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3779                                            reg_w, NULL);
3780         if (ret != I40E_SUCCESS) {
3781                 PMD_DRV_LOG(ERR,
3782                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3783                             reg_id);
3784                 return -EIO;
3785         }
3786         PMD_DRV_LOG(DEBUG,
3787                     "Global register 0x%08x is changed with value 0x%08x",
3788                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3789
3790         return 0;
3791 }
3792
3793 static int
3794 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3795                    enum rte_vlan_type vlan_type,
3796                    uint16_t tpid)
3797 {
3798         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3800         int qinq = dev->data->dev_conf.rxmode.offloads &
3801                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3802         int ret = 0;
3803
3804         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3805              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3806             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3807                 PMD_DRV_LOG(ERR,
3808                             "Unsupported vlan type.");
3809                 return -EINVAL;
3810         }
3811
3812         if (pf->support_multi_driver) {
3813                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3814                 return -ENOTSUP;
3815         }
3816
3817         /* 802.1ad frames ability is added in NVM API 1.7*/
3818         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3819                 if (qinq) {
3820                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3821                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3822                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3823                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3824                 } else {
3825                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3826                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3827                 }
3828                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3829                 if (ret != I40E_SUCCESS) {
3830                         PMD_DRV_LOG(ERR,
3831                                     "Set switch config failed aq_err: %d",
3832                                     hw->aq.asq_last_status);
3833                         ret = -EIO;
3834                 }
3835         } else
3836                 /* If NVM API < 1.7, keep the register setting */
3837                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3838                                                       tpid, qinq);
3839
3840         return ret;
3841 }
3842
3843 static int
3844 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3845 {
3846         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3847         struct i40e_vsi *vsi = pf->main_vsi;
3848         struct rte_eth_rxmode *rxmode;
3849
3850         if (mask & ETH_QINQ_STRIP_MASK) {
3851                 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3852                 return -ENOTSUP;
3853         }
3854
3855         rxmode = &dev->data->dev_conf.rxmode;
3856         if (mask & ETH_VLAN_FILTER_MASK) {
3857                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3858                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3859                 else
3860                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3861         }
3862
3863         if (mask & ETH_VLAN_STRIP_MASK) {
3864                 /* Enable or disable VLAN stripping */
3865                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3866                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3867                 else
3868                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3869         }
3870
3871         if (mask & ETH_VLAN_EXTEND_MASK) {
3872                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3873                         i40e_vsi_config_double_vlan(vsi, TRUE);
3874                         /* Set global registers with default ethertype. */
3875                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3876                                            RTE_ETHER_TYPE_VLAN);
3877                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3878                                            RTE_ETHER_TYPE_VLAN);
3879                 }
3880                 else
3881                         i40e_vsi_config_double_vlan(vsi, FALSE);
3882         }
3883
3884         return 0;
3885 }
3886
3887 static void
3888 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3889                           __rte_unused uint16_t queue,
3890                           __rte_unused int on)
3891 {
3892         PMD_INIT_FUNC_TRACE();
3893 }
3894
3895 static int
3896 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3897 {
3898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3899         struct i40e_vsi *vsi = pf->main_vsi;
3900         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3901         struct i40e_vsi_vlan_pvid_info info;
3902
3903         memset(&info, 0, sizeof(info));
3904         info.on = on;
3905         if (info.on)
3906                 info.config.pvid = pvid;
3907         else {
3908                 info.config.reject.tagged =
3909                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3910                 info.config.reject.untagged =
3911                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3912         }
3913
3914         return i40e_vsi_vlan_pvid_set(vsi, &info);
3915 }
3916
3917 static int
3918 i40e_dev_led_on(struct rte_eth_dev *dev)
3919 {
3920         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         uint32_t mode = i40e_led_get(hw);
3922
3923         if (mode == 0)
3924                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3925
3926         return 0;
3927 }
3928
3929 static int
3930 i40e_dev_led_off(struct rte_eth_dev *dev)
3931 {
3932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3933         uint32_t mode = i40e_led_get(hw);
3934
3935         if (mode != 0)
3936                 i40e_led_set(hw, 0, false);
3937
3938         return 0;
3939 }
3940
3941 static int
3942 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3943 {
3944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3945         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3946
3947         fc_conf->pause_time = pf->fc_conf.pause_time;
3948
3949         /* read out from register, in case they are modified by other port */
3950         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3951                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3952         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3953                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3954
3955         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3956         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3957
3958          /* Return current mode according to actual setting*/
3959         switch (hw->fc.current_mode) {
3960         case I40E_FC_FULL:
3961                 fc_conf->mode = RTE_FC_FULL;
3962                 break;
3963         case I40E_FC_TX_PAUSE:
3964                 fc_conf->mode = RTE_FC_TX_PAUSE;
3965                 break;
3966         case I40E_FC_RX_PAUSE:
3967                 fc_conf->mode = RTE_FC_RX_PAUSE;
3968                 break;
3969         case I40E_FC_NONE:
3970         default:
3971                 fc_conf->mode = RTE_FC_NONE;
3972         };
3973
3974         return 0;
3975 }
3976
3977 static int
3978 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3979 {
3980         uint32_t mflcn_reg, fctrl_reg, reg;
3981         uint32_t max_high_water;
3982         uint8_t i, aq_failure;
3983         int err;
3984         struct i40e_hw *hw;
3985         struct i40e_pf *pf;
3986         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3987                 [RTE_FC_NONE] = I40E_FC_NONE,
3988                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3989                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3990                 [RTE_FC_FULL] = I40E_FC_FULL
3991         };
3992
3993         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3994
3995         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3996         if ((fc_conf->high_water > max_high_water) ||
3997                         (fc_conf->high_water < fc_conf->low_water)) {
3998                 PMD_INIT_LOG(ERR,
3999                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4000                         max_high_water);
4001                 return -EINVAL;
4002         }
4003
4004         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4006         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4007
4008         pf->fc_conf.pause_time = fc_conf->pause_time;
4009         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4010         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4011
4012         PMD_INIT_FUNC_TRACE();
4013
4014         /* All the link flow control related enable/disable register
4015          * configuration is handle by the F/W
4016          */
4017         err = i40e_set_fc(hw, &aq_failure, true);
4018         if (err < 0)
4019                 return -ENOSYS;
4020
4021         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4022                 /* Configure flow control refresh threshold,
4023                  * the value for stat_tx_pause_refresh_timer[8]
4024                  * is used for global pause operation.
4025                  */
4026
4027                 I40E_WRITE_REG(hw,
4028                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4029                                pf->fc_conf.pause_time);
4030
4031                 /* configure the timer value included in transmitted pause
4032                  * frame,
4033                  * the value for stat_tx_pause_quanta[8] is used for global
4034                  * pause operation
4035                  */
4036                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4037                                pf->fc_conf.pause_time);
4038
4039                 fctrl_reg = I40E_READ_REG(hw,
4040                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4041
4042                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4043                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4044                 else
4045                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4046
4047                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4048                                fctrl_reg);
4049         } else {
4050                 /* Configure pause time (2 TCs per register) */
4051                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4052                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4053                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4054
4055                 /* Configure flow control refresh threshold value */
4056                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4057                                pf->fc_conf.pause_time / 2);
4058
4059                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4060
4061                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4062                  *depending on configuration
4063                  */
4064                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4065                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4066                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4067                 } else {
4068                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4069                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4070                 }
4071
4072                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4073         }
4074
4075         if (!pf->support_multi_driver) {
4076                 /* config water marker both based on the packets and bytes */
4077                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4078                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4079                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4080                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4081                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4082                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4083                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4084                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4085                                   << I40E_KILOSHIFT);
4086                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4087                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4088                                    << I40E_KILOSHIFT);
4089         } else {
4090                 PMD_DRV_LOG(ERR,
4091                             "Water marker configuration is not supported.");
4092         }
4093
4094         I40E_WRITE_FLUSH(hw);
4095
4096         return 0;
4097 }
4098
4099 static int
4100 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4101                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4102 {
4103         PMD_INIT_FUNC_TRACE();
4104
4105         return -ENOSYS;
4106 }
4107
4108 /* Add a MAC address, and update filters */
4109 static int
4110 i40e_macaddr_add(struct rte_eth_dev *dev,
4111                  struct rte_ether_addr *mac_addr,
4112                  __rte_unused uint32_t index,
4113                  uint32_t pool)
4114 {
4115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4116         struct i40e_mac_filter_info mac_filter;
4117         struct i40e_vsi *vsi;
4118         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4119         int ret;
4120
4121         /* If VMDQ not enabled or configured, return */
4122         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4123                           !pf->nb_cfg_vmdq_vsi)) {
4124                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4125                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4126                         pool);
4127                 return -ENOTSUP;
4128         }
4129
4130         if (pool > pf->nb_cfg_vmdq_vsi) {
4131                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4132                                 pool, pf->nb_cfg_vmdq_vsi);
4133                 return -EINVAL;
4134         }
4135
4136         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4137         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4138                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4139         else
4140                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4141
4142         if (pool == 0)
4143                 vsi = pf->main_vsi;
4144         else
4145                 vsi = pf->vmdq[pool - 1].vsi;
4146
4147         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4148         if (ret != I40E_SUCCESS) {
4149                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4150                 return -ENODEV;
4151         }
4152         return 0;
4153 }
4154
4155 /* Remove a MAC address, and update filters */
4156 static void
4157 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4158 {
4159         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4160         struct i40e_vsi *vsi;
4161         struct rte_eth_dev_data *data = dev->data;
4162         struct rte_ether_addr *macaddr;
4163         int ret;
4164         uint32_t i;
4165         uint64_t pool_sel;
4166
4167         macaddr = &(data->mac_addrs[index]);
4168
4169         pool_sel = dev->data->mac_pool_sel[index];
4170
4171         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4172                 if (pool_sel & (1ULL << i)) {
4173                         if (i == 0)
4174                                 vsi = pf->main_vsi;
4175                         else {
4176                                 /* No VMDQ pool enabled or configured */
4177                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4178                                         (i > pf->nb_cfg_vmdq_vsi)) {
4179                                         PMD_DRV_LOG(ERR,
4180                                                 "No VMDQ pool enabled/configured");
4181                                         return;
4182                                 }
4183                                 vsi = pf->vmdq[i - 1].vsi;
4184                         }
4185                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4186
4187                         if (ret) {
4188                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4189                                 return;
4190                         }
4191                 }
4192         }
4193 }
4194
4195 /* Set perfect match or hash match of MAC and VLAN for a VF */
4196 static int
4197 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4198                  struct rte_eth_mac_filter *filter,
4199                  bool add)
4200 {
4201         struct i40e_hw *hw;
4202         struct i40e_mac_filter_info mac_filter;
4203         struct rte_ether_addr old_mac;
4204         struct rte_ether_addr *new_mac;
4205         struct i40e_pf_vf *vf = NULL;
4206         uint16_t vf_id;
4207         int ret;
4208
4209         if (pf == NULL) {
4210                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4211                 return -EINVAL;
4212         }
4213         hw = I40E_PF_TO_HW(pf);
4214
4215         if (filter == NULL) {
4216                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4217                 return -EINVAL;
4218         }
4219
4220         new_mac = &filter->mac_addr;
4221
4222         if (rte_is_zero_ether_addr(new_mac)) {
4223                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4224                 return -EINVAL;
4225         }
4226
4227         vf_id = filter->dst_id;
4228
4229         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4230                 PMD_DRV_LOG(ERR, "Invalid argument.");
4231                 return -EINVAL;
4232         }
4233         vf = &pf->vfs[vf_id];
4234
4235         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4236                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4237                 return -EINVAL;
4238         }
4239
4240         if (add) {
4241                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4242                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4243                                 RTE_ETHER_ADDR_LEN);
4244                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4245                                  RTE_ETHER_ADDR_LEN);
4246
4247                 mac_filter.filter_type = filter->filter_type;
4248                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4249                 if (ret != I40E_SUCCESS) {
4250                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4251                         return -1;
4252                 }
4253                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4254         } else {
4255                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4256                                 RTE_ETHER_ADDR_LEN);
4257                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4258                 if (ret != I40E_SUCCESS) {
4259                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4260                         return -1;
4261                 }
4262
4263                 /* Clear device address as it has been removed */
4264                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4265                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4266         }
4267
4268         return 0;
4269 }
4270
4271 /* MAC filter handle */
4272 static int
4273 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4274                 void *arg)
4275 {
4276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4277         struct rte_eth_mac_filter *filter;
4278         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4279         int ret = I40E_NOT_SUPPORTED;
4280
4281         filter = (struct rte_eth_mac_filter *)(arg);
4282
4283         switch (filter_op) {
4284         case RTE_ETH_FILTER_NOP:
4285                 ret = I40E_SUCCESS;
4286                 break;
4287         case RTE_ETH_FILTER_ADD:
4288                 i40e_pf_disable_irq0(hw);
4289                 if (filter->is_vf)
4290                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4291                 i40e_pf_enable_irq0(hw);
4292                 break;
4293         case RTE_ETH_FILTER_DELETE:
4294                 i40e_pf_disable_irq0(hw);
4295                 if (filter->is_vf)
4296                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4297                 i40e_pf_enable_irq0(hw);
4298                 break;
4299         default:
4300                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4301                 ret = I40E_ERR_PARAM;
4302                 break;
4303         }
4304
4305         return ret;
4306 }
4307
4308 static int
4309 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4310 {
4311         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4312         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4313         uint32_t reg;
4314         int ret;
4315
4316         if (!lut)
4317                 return -EINVAL;
4318
4319         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4320                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4321                                           vsi->type != I40E_VSI_SRIOV,
4322                                           lut, lut_size);
4323                 if (ret) {
4324                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4325                         return ret;
4326                 }
4327         } else {
4328                 uint32_t *lut_dw = (uint32_t *)lut;
4329                 uint16_t i, lut_size_dw = lut_size / 4;
4330
4331                 if (vsi->type == I40E_VSI_SRIOV) {
4332                         for (i = 0; i <= lut_size_dw; i++) {
4333                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4334                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4335                         }
4336                 } else {
4337                         for (i = 0; i < lut_size_dw; i++)
4338                                 lut_dw[i] = I40E_READ_REG(hw,
4339                                                           I40E_PFQF_HLUT(i));
4340                 }
4341         }
4342
4343         return 0;
4344 }
4345
4346 int
4347 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4348 {
4349         struct i40e_pf *pf;
4350         struct i40e_hw *hw;
4351         int ret;
4352
4353         if (!vsi || !lut)
4354                 return -EINVAL;
4355
4356         pf = I40E_VSI_TO_PF(vsi);
4357         hw = I40E_VSI_TO_HW(vsi);
4358
4359         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4360                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4361                                           vsi->type != I40E_VSI_SRIOV,
4362                                           lut, lut_size);
4363                 if (ret) {
4364                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4365                         return ret;
4366                 }
4367         } else {
4368                 uint32_t *lut_dw = (uint32_t *)lut;
4369                 uint16_t i, lut_size_dw = lut_size / 4;
4370
4371                 if (vsi->type == I40E_VSI_SRIOV) {
4372                         for (i = 0; i < lut_size_dw; i++)
4373                                 I40E_WRITE_REG(
4374                                         hw,
4375                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4376                                         lut_dw[i]);
4377                 } else {
4378                         for (i = 0; i < lut_size_dw; i++)
4379                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4380                                                lut_dw[i]);
4381                 }
4382                 I40E_WRITE_FLUSH(hw);
4383         }
4384
4385         return 0;
4386 }
4387
4388 static int
4389 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4390                          struct rte_eth_rss_reta_entry64 *reta_conf,
4391                          uint16_t reta_size)
4392 {
4393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4394         uint16_t i, lut_size = pf->hash_lut_size;
4395         uint16_t idx, shift;
4396         uint8_t *lut;
4397         int ret;
4398
4399         if (reta_size != lut_size ||
4400                 reta_size > ETH_RSS_RETA_SIZE_512) {
4401                 PMD_DRV_LOG(ERR,
4402                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4403                         reta_size, lut_size);
4404                 return -EINVAL;
4405         }
4406
4407         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4408         if (!lut) {
4409                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4410                 return -ENOMEM;
4411         }
4412         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4413         if (ret)
4414                 goto out;
4415         for (i = 0; i < reta_size; i++) {
4416                 idx = i / RTE_RETA_GROUP_SIZE;
4417                 shift = i % RTE_RETA_GROUP_SIZE;
4418                 if (reta_conf[idx].mask & (1ULL << shift))
4419                         lut[i] = reta_conf[idx].reta[shift];
4420         }
4421         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4422
4423         pf->adapter->rss_reta_updated = 1;
4424
4425 out:
4426         rte_free(lut);
4427
4428         return ret;
4429 }
4430
4431 static int
4432 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4433                         struct rte_eth_rss_reta_entry64 *reta_conf,
4434                         uint16_t reta_size)
4435 {
4436         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4437         uint16_t i, lut_size = pf->hash_lut_size;
4438         uint16_t idx, shift;
4439         uint8_t *lut;
4440         int ret;
4441
4442         if (reta_size != lut_size ||
4443                 reta_size > ETH_RSS_RETA_SIZE_512) {
4444                 PMD_DRV_LOG(ERR,
4445                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4446                         reta_size, lut_size);
4447                 return -EINVAL;
4448         }
4449
4450         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4451         if (!lut) {
4452                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4453                 return -ENOMEM;
4454         }
4455
4456         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4457         if (ret)
4458                 goto out;
4459         for (i = 0; i < reta_size; i++) {
4460                 idx = i / RTE_RETA_GROUP_SIZE;
4461                 shift = i % RTE_RETA_GROUP_SIZE;
4462                 if (reta_conf[idx].mask & (1ULL << shift))
4463                         reta_conf[idx].reta[shift] = lut[i];
4464         }
4465
4466 out:
4467         rte_free(lut);
4468
4469         return ret;
4470 }
4471
4472 /**
4473  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4474  * @hw:   pointer to the HW structure
4475  * @mem:  pointer to mem struct to fill out
4476  * @size: size of memory requested
4477  * @alignment: what to align the allocation to
4478  **/
4479 enum i40e_status_code
4480 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4481                         struct i40e_dma_mem *mem,
4482                         u64 size,
4483                         u32 alignment)
4484 {
4485         const struct rte_memzone *mz = NULL;
4486         char z_name[RTE_MEMZONE_NAMESIZE];
4487
4488         if (!mem)
4489                 return I40E_ERR_PARAM;
4490
4491         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4492         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4493                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4494         if (!mz)
4495                 return I40E_ERR_NO_MEMORY;
4496
4497         mem->size = size;
4498         mem->va = mz->addr;
4499         mem->pa = mz->iova;
4500         mem->zone = (const void *)mz;
4501         PMD_DRV_LOG(DEBUG,
4502                 "memzone %s allocated with physical address: %"PRIu64,
4503                 mz->name, mem->pa);
4504
4505         return I40E_SUCCESS;
4506 }
4507
4508 /**
4509  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4510  * @hw:   pointer to the HW structure
4511  * @mem:  ptr to mem struct to free
4512  **/
4513 enum i40e_status_code
4514 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4515                     struct i40e_dma_mem *mem)
4516 {
4517         if (!mem)
4518                 return I40E_ERR_PARAM;
4519
4520         PMD_DRV_LOG(DEBUG,
4521                 "memzone %s to be freed with physical address: %"PRIu64,
4522                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4523         rte_memzone_free((const struct rte_memzone *)mem->zone);
4524         mem->zone = NULL;
4525         mem->va = NULL;
4526         mem->pa = (u64)0;
4527
4528         return I40E_SUCCESS;
4529 }
4530
4531 /**
4532  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4533  * @hw:   pointer to the HW structure
4534  * @mem:  pointer to mem struct to fill out
4535  * @size: size of memory requested
4536  **/
4537 enum i40e_status_code
4538 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4539                          struct i40e_virt_mem *mem,
4540                          u32 size)
4541 {
4542         if (!mem)
4543                 return I40E_ERR_PARAM;
4544
4545         mem->size = size;
4546         mem->va = rte_zmalloc("i40e", size, 0);
4547
4548         if (mem->va)
4549                 return I40E_SUCCESS;
4550         else
4551                 return I40E_ERR_NO_MEMORY;
4552 }
4553
4554 /**
4555  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4556  * @hw:   pointer to the HW structure
4557  * @mem:  pointer to mem struct to free
4558  **/
4559 enum i40e_status_code
4560 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4561                      struct i40e_virt_mem *mem)
4562 {
4563         if (!mem)
4564                 return I40E_ERR_PARAM;
4565
4566         rte_free(mem->va);
4567         mem->va = NULL;
4568
4569         return I40E_SUCCESS;
4570 }
4571
4572 void
4573 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4574 {
4575         rte_spinlock_init(&sp->spinlock);
4576 }
4577
4578 void
4579 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4580 {
4581         rte_spinlock_lock(&sp->spinlock);
4582 }
4583
4584 void
4585 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4586 {
4587         rte_spinlock_unlock(&sp->spinlock);
4588 }
4589
4590 void
4591 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4592 {
4593         return;
4594 }
4595
4596 /**
4597  * Get the hardware capabilities, which will be parsed
4598  * and saved into struct i40e_hw.
4599  */
4600 static int
4601 i40e_get_cap(struct i40e_hw *hw)
4602 {
4603         struct i40e_aqc_list_capabilities_element_resp *buf;
4604         uint16_t len, size = 0;
4605         int ret;
4606
4607         /* Calculate a huge enough buff for saving response data temporarily */
4608         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4609                                                 I40E_MAX_CAP_ELE_NUM;
4610         buf = rte_zmalloc("i40e", len, 0);
4611         if (!buf) {
4612                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4613                 return I40E_ERR_NO_MEMORY;
4614         }
4615
4616         /* Get, parse the capabilities and save it to hw */
4617         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4618                         i40e_aqc_opc_list_func_capabilities, NULL);
4619         if (ret != I40E_SUCCESS)
4620                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4621
4622         /* Free the temporary buffer after being used */
4623         rte_free(buf);
4624
4625         return ret;
4626 }
4627
4628 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4629
4630 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4631                 const char *value,
4632                 void *opaque)
4633 {
4634         struct i40e_pf *pf;
4635         unsigned long num;
4636         char *end;
4637
4638         pf = (struct i40e_pf *)opaque;
4639         RTE_SET_USED(key);
4640
4641         errno = 0;
4642         num = strtoul(value, &end, 0);
4643         if (errno != 0 || end == value || *end != 0) {
4644                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4645                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4646                 return -(EINVAL);
4647         }
4648
4649         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4650                 pf->vf_nb_qp_max = (uint16_t)num;
4651         else
4652                 /* here return 0 to make next valid same argument work */
4653                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4654                             "power of 2 and equal or less than 16 !, Now it is "
4655                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4656
4657         return 0;
4658 }
4659
4660 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4661 {
4662         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4663         struct rte_kvargs *kvlist;
4664         int kvargs_count;
4665
4666         /* set default queue number per VF as 4 */
4667         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4668
4669         if (dev->device->devargs == NULL)
4670                 return 0;
4671
4672         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4673         if (kvlist == NULL)
4674                 return -(EINVAL);
4675
4676         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4677         if (!kvargs_count) {
4678                 rte_kvargs_free(kvlist);
4679                 return 0;
4680         }
4681
4682         if (kvargs_count > 1)
4683                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4684                             "the first invalid or last valid one is used !",
4685                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4686
4687         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4688                            i40e_pf_parse_vf_queue_number_handler, pf);
4689
4690         rte_kvargs_free(kvlist);
4691
4692         return 0;
4693 }
4694
4695 static int
4696 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4697 {
4698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4699         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4700         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4701         uint16_t qp_count = 0, vsi_count = 0;
4702
4703         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4704                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4705                 return -EINVAL;
4706         }
4707
4708         i40e_pf_config_vf_rxq_number(dev);
4709
4710         /* Add the parameter init for LFC */
4711         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4712         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4713         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4714
4715         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4716         pf->max_num_vsi = hw->func_caps.num_vsis;
4717         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4718         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4719
4720         /* FDir queue/VSI allocation */
4721         pf->fdir_qp_offset = 0;
4722         if (hw->func_caps.fd) {
4723                 pf->flags |= I40E_FLAG_FDIR;
4724                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4725         } else {
4726                 pf->fdir_nb_qps = 0;
4727         }
4728         qp_count += pf->fdir_nb_qps;
4729         vsi_count += 1;
4730
4731         /* LAN queue/VSI allocation */
4732         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4733         if (!hw->func_caps.rss) {
4734                 pf->lan_nb_qps = 1;
4735         } else {
4736                 pf->flags |= I40E_FLAG_RSS;
4737                 if (hw->mac.type == I40E_MAC_X722)
4738                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4739                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4740         }
4741         qp_count += pf->lan_nb_qps;
4742         vsi_count += 1;
4743
4744         /* VF queue/VSI allocation */
4745         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4746         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4747                 pf->flags |= I40E_FLAG_SRIOV;
4748                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4749                 pf->vf_num = pci_dev->max_vfs;
4750                 PMD_DRV_LOG(DEBUG,
4751                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4752                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4753         } else {
4754                 pf->vf_nb_qps = 0;
4755                 pf->vf_num = 0;
4756         }
4757         qp_count += pf->vf_nb_qps * pf->vf_num;
4758         vsi_count += pf->vf_num;
4759
4760         /* VMDq queue/VSI allocation */
4761         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4762         pf->vmdq_nb_qps = 0;
4763         pf->max_nb_vmdq_vsi = 0;
4764         if (hw->func_caps.vmdq) {
4765                 if (qp_count < hw->func_caps.num_tx_qp &&
4766                         vsi_count < hw->func_caps.num_vsis) {
4767                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4768                                 qp_count) / pf->vmdq_nb_qp_max;
4769
4770                         /* Limit the maximum number of VMDq vsi to the maximum
4771                          * ethdev can support
4772                          */
4773                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4774                                 hw->func_caps.num_vsis - vsi_count);
4775                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4776                                 ETH_64_POOLS);
4777                         if (pf->max_nb_vmdq_vsi) {
4778                                 pf->flags |= I40E_FLAG_VMDQ;
4779                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4780                                 PMD_DRV_LOG(DEBUG,
4781                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4782                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4783                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4784                         } else {
4785                                 PMD_DRV_LOG(INFO,
4786                                         "No enough queues left for VMDq");
4787                         }
4788                 } else {
4789                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4790                 }
4791         }
4792         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4793         vsi_count += pf->max_nb_vmdq_vsi;
4794
4795         if (hw->func_caps.dcb)
4796                 pf->flags |= I40E_FLAG_DCB;
4797
4798         if (qp_count > hw->func_caps.num_tx_qp) {
4799                 PMD_DRV_LOG(ERR,
4800                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4801                         qp_count, hw->func_caps.num_tx_qp);
4802                 return -EINVAL;
4803         }
4804         if (vsi_count > hw->func_caps.num_vsis) {
4805                 PMD_DRV_LOG(ERR,
4806                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4807                         vsi_count, hw->func_caps.num_vsis);
4808                 return -EINVAL;
4809         }
4810
4811         return 0;
4812 }
4813
4814 static int
4815 i40e_pf_get_switch_config(struct i40e_pf *pf)
4816 {
4817         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4818         struct i40e_aqc_get_switch_config_resp *switch_config;
4819         struct i40e_aqc_switch_config_element_resp *element;
4820         uint16_t start_seid = 0, num_reported;
4821         int ret;
4822
4823         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4824                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4825         if (!switch_config) {
4826                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4827                 return -ENOMEM;
4828         }
4829
4830         /* Get the switch configurations */
4831         ret = i40e_aq_get_switch_config(hw, switch_config,
4832                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4833         if (ret != I40E_SUCCESS) {
4834                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4835                 goto fail;
4836         }
4837         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4838         if (num_reported != 1) { /* The number should be 1 */
4839                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4840                 goto fail;
4841         }
4842
4843         /* Parse the switch configuration elements */
4844         element = &(switch_config->element[0]);
4845         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4846                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4847                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4848         } else
4849                 PMD_DRV_LOG(INFO, "Unknown element type");
4850
4851 fail:
4852         rte_free(switch_config);
4853
4854         return ret;
4855 }
4856
4857 static int
4858 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4859                         uint32_t num)
4860 {
4861         struct pool_entry *entry;
4862
4863         if (pool == NULL || num == 0)
4864                 return -EINVAL;
4865
4866         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4867         if (entry == NULL) {
4868                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4869                 return -ENOMEM;
4870         }
4871
4872         /* queue heap initialize */
4873         pool->num_free = num;
4874         pool->num_alloc = 0;
4875         pool->base = base;
4876         LIST_INIT(&pool->alloc_list);
4877         LIST_INIT(&pool->free_list);
4878
4879         /* Initialize element  */
4880         entry->base = 0;
4881         entry->len = num;
4882
4883         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4884         return 0;
4885 }
4886
4887 static void
4888 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4889 {
4890         struct pool_entry *entry, *next_entry;
4891
4892         if (pool == NULL)
4893                 return;
4894
4895         for (entry = LIST_FIRST(&pool->alloc_list);
4896                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4897                         entry = next_entry) {
4898                 LIST_REMOVE(entry, next);
4899                 rte_free(entry);
4900         }
4901
4902         for (entry = LIST_FIRST(&pool->free_list);
4903                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4904                         entry = next_entry) {
4905                 LIST_REMOVE(entry, next);
4906                 rte_free(entry);
4907         }
4908
4909         pool->num_free = 0;
4910         pool->num_alloc = 0;
4911         pool->base = 0;
4912         LIST_INIT(&pool->alloc_list);
4913         LIST_INIT(&pool->free_list);
4914 }
4915
4916 static int
4917 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4918                        uint32_t base)
4919 {
4920         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4921         uint32_t pool_offset;
4922         int insert;
4923
4924         if (pool == NULL) {
4925                 PMD_DRV_LOG(ERR, "Invalid parameter");
4926                 return -EINVAL;
4927         }
4928
4929         pool_offset = base - pool->base;
4930         /* Lookup in alloc list */
4931         LIST_FOREACH(entry, &pool->alloc_list, next) {
4932                 if (entry->base == pool_offset) {
4933                         valid_entry = entry;
4934                         LIST_REMOVE(entry, next);
4935                         break;
4936                 }
4937         }
4938
4939         /* Not find, return */
4940         if (valid_entry == NULL) {
4941                 PMD_DRV_LOG(ERR, "Failed to find entry");
4942                 return -EINVAL;
4943         }
4944
4945         /**
4946          * Found it, move it to free list  and try to merge.
4947          * In order to make merge easier, always sort it by qbase.
4948          * Find adjacent prev and last entries.
4949          */
4950         prev = next = NULL;
4951         LIST_FOREACH(entry, &pool->free_list, next) {
4952                 if (entry->base > valid_entry->base) {
4953                         next = entry;
4954                         break;
4955                 }
4956                 prev = entry;
4957         }
4958
4959         insert = 0;
4960         /* Try to merge with next one*/
4961         if (next != NULL) {
4962                 /* Merge with next one */
4963                 if (valid_entry->base + valid_entry->len == next->base) {
4964                         next->base = valid_entry->base;
4965                         next->len += valid_entry->len;
4966                         rte_free(valid_entry);
4967                         valid_entry = next;
4968                         insert = 1;
4969                 }
4970         }
4971
4972         if (prev != NULL) {
4973                 /* Merge with previous one */
4974                 if (prev->base + prev->len == valid_entry->base) {
4975                         prev->len += valid_entry->len;
4976                         /* If it merge with next one, remove next node */
4977                         if (insert == 1) {
4978                                 LIST_REMOVE(valid_entry, next);
4979                                 rte_free(valid_entry);
4980                         } else {
4981                                 rte_free(valid_entry);
4982                                 insert = 1;
4983                         }
4984                 }
4985         }
4986
4987         /* Not find any entry to merge, insert */
4988         if (insert == 0) {
4989                 if (prev != NULL)
4990                         LIST_INSERT_AFTER(prev, valid_entry, next);
4991                 else if (next != NULL)
4992                         LIST_INSERT_BEFORE(next, valid_entry, next);
4993                 else /* It's empty list, insert to head */
4994                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4995         }
4996
4997         pool->num_free += valid_entry->len;
4998         pool->num_alloc -= valid_entry->len;
4999
5000         return 0;
5001 }
5002
5003 static int
5004 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5005                        uint16_t num)
5006 {
5007         struct pool_entry *entry, *valid_entry;
5008
5009         if (pool == NULL || num == 0) {
5010                 PMD_DRV_LOG(ERR, "Invalid parameter");
5011                 return -EINVAL;
5012         }
5013
5014         if (pool->num_free < num) {
5015                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5016                             num, pool->num_free);
5017                 return -ENOMEM;
5018         }
5019
5020         valid_entry = NULL;
5021         /* Lookup  in free list and find most fit one */
5022         LIST_FOREACH(entry, &pool->free_list, next) {
5023                 if (entry->len >= num) {
5024                         /* Find best one */
5025                         if (entry->len == num) {
5026                                 valid_entry = entry;
5027                                 break;
5028                         }
5029                         if (valid_entry == NULL || valid_entry->len > entry->len)
5030                                 valid_entry = entry;
5031                 }
5032         }
5033
5034         /* Not find one to satisfy the request, return */
5035         if (valid_entry == NULL) {
5036                 PMD_DRV_LOG(ERR, "No valid entry found");
5037                 return -ENOMEM;
5038         }
5039         /**
5040          * The entry have equal queue number as requested,
5041          * remove it from alloc_list.
5042          */
5043         if (valid_entry->len == num) {
5044                 LIST_REMOVE(valid_entry, next);
5045         } else {
5046                 /**
5047                  * The entry have more numbers than requested,
5048                  * create a new entry for alloc_list and minus its
5049                  * queue base and number in free_list.
5050                  */
5051                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5052                 if (entry == NULL) {
5053                         PMD_DRV_LOG(ERR,
5054                                 "Failed to allocate memory for resource pool");
5055                         return -ENOMEM;
5056                 }
5057                 entry->base = valid_entry->base;
5058                 entry->len = num;
5059                 valid_entry->base += num;
5060                 valid_entry->len -= num;
5061                 valid_entry = entry;
5062         }
5063
5064         /* Insert it into alloc list, not sorted */
5065         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5066
5067         pool->num_free -= valid_entry->len;
5068         pool->num_alloc += valid_entry->len;
5069
5070         return valid_entry->base + pool->base;
5071 }
5072
5073 /**
5074  * bitmap_is_subset - Check whether src2 is subset of src1
5075  **/
5076 static inline int
5077 bitmap_is_subset(uint8_t src1, uint8_t src2)
5078 {
5079         return !((src1 ^ src2) & src2);
5080 }
5081
5082 static enum i40e_status_code
5083 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5084 {
5085         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5086
5087         /* If DCB is not supported, only default TC is supported */
5088         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5089                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5090                 return I40E_NOT_SUPPORTED;
5091         }
5092
5093         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5094                 PMD_DRV_LOG(ERR,
5095                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5096                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5097                 return I40E_NOT_SUPPORTED;
5098         }
5099         return I40E_SUCCESS;
5100 }
5101
5102 int
5103 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5104                                 struct i40e_vsi_vlan_pvid_info *info)
5105 {
5106         struct i40e_hw *hw;
5107         struct i40e_vsi_context ctxt;
5108         uint8_t vlan_flags = 0;
5109         int ret;
5110
5111         if (vsi == NULL || info == NULL) {
5112                 PMD_DRV_LOG(ERR, "invalid parameters");
5113                 return I40E_ERR_PARAM;
5114         }
5115
5116         if (info->on) {
5117                 vsi->info.pvid = info->config.pvid;
5118                 /**
5119                  * If insert pvid is enabled, only tagged pkts are
5120                  * allowed to be sent out.
5121                  */
5122                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5123                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5124         } else {
5125                 vsi->info.pvid = 0;
5126                 if (info->config.reject.tagged == 0)
5127                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5128
5129                 if (info->config.reject.untagged == 0)
5130                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5131         }
5132         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5133                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5134         vsi->info.port_vlan_flags |= vlan_flags;
5135         vsi->info.valid_sections =
5136                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5137         memset(&ctxt, 0, sizeof(ctxt));
5138         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5139         ctxt.seid = vsi->seid;
5140
5141         hw = I40E_VSI_TO_HW(vsi);
5142         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5143         if (ret != I40E_SUCCESS)
5144                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5145
5146         return ret;
5147 }
5148
5149 static int
5150 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5151 {
5152         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5153         int i, ret;
5154         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5155
5156         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5157         if (ret != I40E_SUCCESS)
5158                 return ret;
5159
5160         if (!vsi->seid) {
5161                 PMD_DRV_LOG(ERR, "seid not valid");
5162                 return -EINVAL;
5163         }
5164
5165         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5166         tc_bw_data.tc_valid_bits = enabled_tcmap;
5167         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5168                 tc_bw_data.tc_bw_credits[i] =
5169                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5170
5171         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5172         if (ret != I40E_SUCCESS) {
5173                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5174                 return ret;
5175         }
5176
5177         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5178                                         sizeof(vsi->info.qs_handle));
5179         return I40E_SUCCESS;
5180 }
5181
5182 static enum i40e_status_code
5183 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5184                                  struct i40e_aqc_vsi_properties_data *info,
5185                                  uint8_t enabled_tcmap)
5186 {
5187         enum i40e_status_code ret;
5188         int i, total_tc = 0;
5189         uint16_t qpnum_per_tc, bsf, qp_idx;
5190
5191         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5192         if (ret != I40E_SUCCESS)
5193                 return ret;
5194
5195         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5196                 if (enabled_tcmap & (1 << i))
5197                         total_tc++;
5198         if (total_tc == 0)
5199                 total_tc = 1;
5200         vsi->enabled_tc = enabled_tcmap;
5201
5202         /* Number of queues per enabled TC */
5203         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5204         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5205         bsf = rte_bsf32(qpnum_per_tc);
5206
5207         /* Adjust the queue number to actual queues that can be applied */
5208         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5209                 vsi->nb_qps = qpnum_per_tc * total_tc;
5210
5211         /**
5212          * Configure TC and queue mapping parameters, for enabled TC,
5213          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5214          * default queue will serve it.
5215          */
5216         qp_idx = 0;
5217         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5218                 if (vsi->enabled_tc & (1 << i)) {
5219                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5220                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5221                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5222                         qp_idx += qpnum_per_tc;
5223                 } else
5224                         info->tc_mapping[i] = 0;
5225         }
5226
5227         /* Associate queue number with VSI */
5228         if (vsi->type == I40E_VSI_SRIOV) {
5229                 info->mapping_flags |=
5230                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5231                 for (i = 0; i < vsi->nb_qps; i++)
5232                         info->queue_mapping[i] =
5233                                 rte_cpu_to_le_16(vsi->base_queue + i);
5234         } else {
5235                 info->mapping_flags |=
5236                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5237                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5238         }
5239         info->valid_sections |=
5240                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5241
5242         return I40E_SUCCESS;
5243 }
5244
5245 static int
5246 i40e_veb_release(struct i40e_veb *veb)
5247 {
5248         struct i40e_vsi *vsi;
5249         struct i40e_hw *hw;
5250
5251         if (veb == NULL)
5252                 return -EINVAL;
5253
5254         if (!TAILQ_EMPTY(&veb->head)) {
5255                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5256                 return -EACCES;
5257         }
5258         /* associate_vsi field is NULL for floating VEB */
5259         if (veb->associate_vsi != NULL) {
5260                 vsi = veb->associate_vsi;
5261                 hw = I40E_VSI_TO_HW(vsi);
5262
5263                 vsi->uplink_seid = veb->uplink_seid;
5264                 vsi->veb = NULL;
5265         } else {
5266                 veb->associate_pf->main_vsi->floating_veb = NULL;
5267                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5268         }
5269
5270         i40e_aq_delete_element(hw, veb->seid, NULL);
5271         rte_free(veb);
5272         return I40E_SUCCESS;
5273 }
5274
5275 /* Setup a veb */
5276 static struct i40e_veb *
5277 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5278 {
5279         struct i40e_veb *veb;
5280         int ret;
5281         struct i40e_hw *hw;
5282
5283         if (pf == NULL) {
5284                 PMD_DRV_LOG(ERR,
5285                             "veb setup failed, associated PF shouldn't null");
5286                 return NULL;
5287         }
5288         hw = I40E_PF_TO_HW(pf);
5289
5290         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5291         if (!veb) {
5292                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5293                 goto fail;
5294         }
5295
5296         veb->associate_vsi = vsi;
5297         veb->associate_pf = pf;
5298         TAILQ_INIT(&veb->head);
5299         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5300
5301         /* create floating veb if vsi is NULL */
5302         if (vsi != NULL) {
5303                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5304                                       I40E_DEFAULT_TCMAP, false,
5305                                       &veb->seid, false, NULL);
5306         } else {
5307                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5308                                       true, &veb->seid, false, NULL);
5309         }
5310
5311         if (ret != I40E_SUCCESS) {
5312                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5313                             hw->aq.asq_last_status);
5314                 goto fail;
5315         }
5316         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5317
5318         /* get statistics index */
5319         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5320                                 &veb->stats_idx, NULL, NULL, NULL);
5321         if (ret != I40E_SUCCESS) {
5322                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5323                             hw->aq.asq_last_status);
5324                 goto fail;
5325         }
5326         /* Get VEB bandwidth, to be implemented */
5327         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5328         if (vsi)
5329                 vsi->uplink_seid = veb->seid;
5330
5331         return veb;
5332 fail:
5333         rte_free(veb);
5334         return NULL;
5335 }
5336
5337 int
5338 i40e_vsi_release(struct i40e_vsi *vsi)
5339 {
5340         struct i40e_pf *pf;
5341         struct i40e_hw *hw;
5342         struct i40e_vsi_list *vsi_list;
5343         void *temp;
5344         int ret;
5345         struct i40e_mac_filter *f;
5346         uint16_t user_param;
5347
5348         if (!vsi)
5349                 return I40E_SUCCESS;
5350
5351         if (!vsi->adapter)
5352                 return -EFAULT;
5353
5354         user_param = vsi->user_param;
5355
5356         pf = I40E_VSI_TO_PF(vsi);
5357         hw = I40E_VSI_TO_HW(vsi);
5358
5359         /* VSI has child to attach, release child first */
5360         if (vsi->veb) {
5361                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5362                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5363                                 return -1;
5364                 }
5365                 i40e_veb_release(vsi->veb);
5366         }
5367
5368         if (vsi->floating_veb) {
5369                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5370                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5371                                 return -1;
5372                 }
5373         }
5374
5375         /* Remove all macvlan filters of the VSI */
5376         i40e_vsi_remove_all_macvlan_filter(vsi);
5377         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5378                 rte_free(f);
5379
5380         if (vsi->type != I40E_VSI_MAIN &&
5381             ((vsi->type != I40E_VSI_SRIOV) ||
5382             !pf->floating_veb_list[user_param])) {
5383                 /* Remove vsi from parent's sibling list */
5384                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5385                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5386                         return I40E_ERR_PARAM;
5387                 }
5388                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5389                                 &vsi->sib_vsi_list, list);
5390
5391                 /* Remove all switch element of the VSI */
5392                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5393                 if (ret != I40E_SUCCESS)
5394                         PMD_DRV_LOG(ERR, "Failed to delete element");
5395         }
5396
5397         if ((vsi->type == I40E_VSI_SRIOV) &&
5398             pf->floating_veb_list[user_param]) {
5399                 /* Remove vsi from parent's sibling list */
5400                 if (vsi->parent_vsi == NULL ||
5401                     vsi->parent_vsi->floating_veb == NULL) {
5402                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5403                         return I40E_ERR_PARAM;
5404                 }
5405                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5406                              &vsi->sib_vsi_list, list);
5407
5408                 /* Remove all switch element of the VSI */
5409                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5410                 if (ret != I40E_SUCCESS)
5411                         PMD_DRV_LOG(ERR, "Failed to delete element");
5412         }
5413
5414         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5415
5416         if (vsi->type != I40E_VSI_SRIOV)
5417                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5418         rte_free(vsi);
5419
5420         return I40E_SUCCESS;
5421 }
5422
5423 static int
5424 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5425 {
5426         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5427         struct i40e_aqc_remove_macvlan_element_data def_filter;
5428         struct i40e_mac_filter_info filter;
5429         int ret;
5430
5431         if (vsi->type != I40E_VSI_MAIN)
5432                 return I40E_ERR_CONFIG;
5433         memset(&def_filter, 0, sizeof(def_filter));
5434         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5435                                         ETH_ADDR_LEN);
5436         def_filter.vlan_tag = 0;
5437         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5438                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5439         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5440         if (ret != I40E_SUCCESS) {
5441                 struct i40e_mac_filter *f;
5442                 struct rte_ether_addr *mac;
5443
5444                 PMD_DRV_LOG(DEBUG,
5445                             "Cannot remove the default macvlan filter");
5446                 /* It needs to add the permanent mac into mac list */
5447                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5448                 if (f == NULL) {
5449                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5450                         return I40E_ERR_NO_MEMORY;
5451                 }
5452                 mac = &f->mac_info.mac_addr;
5453                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5454                                 ETH_ADDR_LEN);
5455                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5456                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5457                 vsi->mac_num++;
5458
5459                 return ret;
5460         }
5461         rte_memcpy(&filter.mac_addr,
5462                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5463         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5464         return i40e_vsi_add_mac(vsi, &filter);
5465 }
5466
5467 /*
5468  * i40e_vsi_get_bw_config - Query VSI BW Information
5469  * @vsi: the VSI to be queried
5470  *
5471  * Returns 0 on success, negative value on failure
5472  */
5473 static enum i40e_status_code
5474 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5475 {
5476         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5477         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5478         struct i40e_hw *hw = &vsi->adapter->hw;
5479         i40e_status ret;
5480         int i;
5481         uint32_t bw_max;
5482
5483         memset(&bw_config, 0, sizeof(bw_config));
5484         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5485         if (ret != I40E_SUCCESS) {
5486                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5487                             hw->aq.asq_last_status);
5488                 return ret;
5489         }
5490
5491         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5492         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5493                                         &ets_sla_config, NULL);
5494         if (ret != I40E_SUCCESS) {
5495                 PMD_DRV_LOG(ERR,
5496                         "VSI failed to get TC bandwdith configuration %u",
5497                         hw->aq.asq_last_status);
5498                 return ret;
5499         }
5500
5501         /* store and print out BW info */
5502         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5503         vsi->bw_info.bw_max = bw_config.max_bw;
5504         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5505         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5506         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5507                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5508                      I40E_16_BIT_WIDTH);
5509         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5510                 vsi->bw_info.bw_ets_share_credits[i] =
5511                                 ets_sla_config.share_credits[i];
5512                 vsi->bw_info.bw_ets_credits[i] =
5513                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5514                 /* 4 bits per TC, 4th bit is reserved */
5515                 vsi->bw_info.bw_ets_max[i] =
5516                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5517                                   RTE_LEN2MASK(3, uint8_t));
5518                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5519                             vsi->bw_info.bw_ets_share_credits[i]);
5520                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5521                             vsi->bw_info.bw_ets_credits[i]);
5522                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5523                             vsi->bw_info.bw_ets_max[i]);
5524         }
5525
5526         return I40E_SUCCESS;
5527 }
5528
5529 /* i40e_enable_pf_lb
5530  * @pf: pointer to the pf structure
5531  *
5532  * allow loopback on pf
5533  */
5534 static inline void
5535 i40e_enable_pf_lb(struct i40e_pf *pf)
5536 {
5537         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5538         struct i40e_vsi_context ctxt;
5539         int ret;
5540
5541         /* Use the FW API if FW >= v5.0 */
5542         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5543                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5544                 return;
5545         }
5546
5547         memset(&ctxt, 0, sizeof(ctxt));
5548         ctxt.seid = pf->main_vsi_seid;
5549         ctxt.pf_num = hw->pf_id;
5550         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5551         if (ret) {
5552                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5553                             ret, hw->aq.asq_last_status);
5554                 return;
5555         }
5556         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5557         ctxt.info.valid_sections =
5558                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5559         ctxt.info.switch_id |=
5560                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5561
5562         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5563         if (ret)
5564                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5565                             hw->aq.asq_last_status);
5566 }
5567
5568 /* Setup a VSI */
5569 struct i40e_vsi *
5570 i40e_vsi_setup(struct i40e_pf *pf,
5571                enum i40e_vsi_type type,
5572                struct i40e_vsi *uplink_vsi,
5573                uint16_t user_param)
5574 {
5575         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5576         struct i40e_vsi *vsi;
5577         struct i40e_mac_filter_info filter;
5578         int ret;
5579         struct i40e_vsi_context ctxt;
5580         struct rte_ether_addr broadcast =
5581                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5582
5583         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5584             uplink_vsi == NULL) {
5585                 PMD_DRV_LOG(ERR,
5586                         "VSI setup failed, VSI link shouldn't be NULL");
5587                 return NULL;
5588         }
5589
5590         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5591                 PMD_DRV_LOG(ERR,
5592                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5593                 return NULL;
5594         }
5595
5596         /* two situations
5597          * 1.type is not MAIN and uplink vsi is not NULL
5598          * If uplink vsi didn't setup VEB, create one first under veb field
5599          * 2.type is SRIOV and the uplink is NULL
5600          * If floating VEB is NULL, create one veb under floating veb field
5601          */
5602
5603         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5604             uplink_vsi->veb == NULL) {
5605                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5606
5607                 if (uplink_vsi->veb == NULL) {
5608                         PMD_DRV_LOG(ERR, "VEB setup failed");
5609                         return NULL;
5610                 }
5611                 /* set ALLOWLOOPBACk on pf, when veb is created */
5612                 i40e_enable_pf_lb(pf);
5613         }
5614
5615         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5616             pf->main_vsi->floating_veb == NULL) {
5617                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5618
5619                 if (pf->main_vsi->floating_veb == NULL) {
5620                         PMD_DRV_LOG(ERR, "VEB setup failed");
5621                         return NULL;
5622                 }
5623         }
5624
5625         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5626         if (!vsi) {
5627                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5628                 return NULL;
5629         }
5630         TAILQ_INIT(&vsi->mac_list);
5631         vsi->type = type;
5632         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5633         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5634         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5635         vsi->user_param = user_param;
5636         vsi->vlan_anti_spoof_on = 0;
5637         vsi->vlan_filter_on = 0;
5638         /* Allocate queues */
5639         switch (vsi->type) {
5640         case I40E_VSI_MAIN  :
5641                 vsi->nb_qps = pf->lan_nb_qps;
5642                 break;
5643         case I40E_VSI_SRIOV :
5644                 vsi->nb_qps = pf->vf_nb_qps;
5645                 break;
5646         case I40E_VSI_VMDQ2:
5647                 vsi->nb_qps = pf->vmdq_nb_qps;
5648                 break;
5649         case I40E_VSI_FDIR:
5650                 vsi->nb_qps = pf->fdir_nb_qps;
5651                 break;
5652         default:
5653                 goto fail_mem;
5654         }
5655         /*
5656          * The filter status descriptor is reported in rx queue 0,
5657          * while the tx queue for fdir filter programming has no
5658          * such constraints, can be non-zero queues.
5659          * To simplify it, choose FDIR vsi use queue 0 pair.
5660          * To make sure it will use queue 0 pair, queue allocation
5661          * need be done before this function is called
5662          */
5663         if (type != I40E_VSI_FDIR) {
5664                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5665                         if (ret < 0) {
5666                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5667                                                 vsi->seid, ret);
5668                                 goto fail_mem;
5669                         }
5670                         vsi->base_queue = ret;
5671         } else
5672                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5673
5674         /* VF has MSIX interrupt in VF range, don't allocate here */
5675         if (type == I40E_VSI_MAIN) {
5676                 if (pf->support_multi_driver) {
5677                         /* If support multi-driver, need to use INT0 instead of
5678                          * allocating from msix pool. The Msix pool is init from
5679                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5680                          * to 1 without calling i40e_res_pool_alloc.
5681                          */
5682                         vsi->msix_intr = 0;
5683                         vsi->nb_msix = 1;
5684                 } else {
5685                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5686                                                   RTE_MIN(vsi->nb_qps,
5687                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5688                         if (ret < 0) {
5689                                 PMD_DRV_LOG(ERR,
5690                                             "VSI MAIN %d get heap failed %d",
5691                                             vsi->seid, ret);
5692                                 goto fail_queue_alloc;
5693                         }
5694                         vsi->msix_intr = ret;
5695                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5696                                                RTE_MAX_RXTX_INTR_VEC_ID);
5697                 }
5698         } else if (type != I40E_VSI_SRIOV) {
5699                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5700                 if (ret < 0) {
5701                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5702                         goto fail_queue_alloc;
5703                 }
5704                 vsi->msix_intr = ret;
5705                 vsi->nb_msix = 1;
5706         } else {
5707                 vsi->msix_intr = 0;
5708                 vsi->nb_msix = 0;
5709         }
5710
5711         /* Add VSI */
5712         if (type == I40E_VSI_MAIN) {
5713                 /* For main VSI, no need to add since it's default one */
5714                 vsi->uplink_seid = pf->mac_seid;
5715                 vsi->seid = pf->main_vsi_seid;
5716                 /* Bind queues with specific MSIX interrupt */
5717                 /**
5718                  * Needs 2 interrupt at least, one for misc cause which will
5719                  * enabled from OS side, Another for queues binding the
5720                  * interrupt from device side only.
5721                  */
5722
5723                 /* Get default VSI parameters from hardware */
5724                 memset(&ctxt, 0, sizeof(ctxt));
5725                 ctxt.seid = vsi->seid;
5726                 ctxt.pf_num = hw->pf_id;
5727                 ctxt.uplink_seid = vsi->uplink_seid;
5728                 ctxt.vf_num = 0;
5729                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5730                 if (ret != I40E_SUCCESS) {
5731                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5732                         goto fail_msix_alloc;
5733                 }
5734                 rte_memcpy(&vsi->info, &ctxt.info,
5735                         sizeof(struct i40e_aqc_vsi_properties_data));
5736                 vsi->vsi_id = ctxt.vsi_number;
5737                 vsi->info.valid_sections = 0;
5738
5739                 /* Configure tc, enabled TC0 only */
5740                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5741                         I40E_SUCCESS) {
5742                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5743                         goto fail_msix_alloc;
5744                 }
5745
5746                 /* TC, queue mapping */
5747                 memset(&ctxt, 0, sizeof(ctxt));
5748                 vsi->info.valid_sections |=
5749                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5750                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5751                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5752                 rte_memcpy(&ctxt.info, &vsi->info,
5753                         sizeof(struct i40e_aqc_vsi_properties_data));
5754                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5755                                                 I40E_DEFAULT_TCMAP);
5756                 if (ret != I40E_SUCCESS) {
5757                         PMD_DRV_LOG(ERR,
5758                                 "Failed to configure TC queue mapping");
5759                         goto fail_msix_alloc;
5760                 }
5761                 ctxt.seid = vsi->seid;
5762                 ctxt.pf_num = hw->pf_id;
5763                 ctxt.uplink_seid = vsi->uplink_seid;
5764                 ctxt.vf_num = 0;
5765
5766                 /* Update VSI parameters */
5767                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5768                 if (ret != I40E_SUCCESS) {
5769                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5770                         goto fail_msix_alloc;
5771                 }
5772
5773                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5774                                                 sizeof(vsi->info.tc_mapping));
5775                 rte_memcpy(&vsi->info.queue_mapping,
5776                                 &ctxt.info.queue_mapping,
5777                         sizeof(vsi->info.queue_mapping));
5778                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5779                 vsi->info.valid_sections = 0;
5780
5781                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5782                                 ETH_ADDR_LEN);
5783
5784                 /**
5785                  * Updating default filter settings are necessary to prevent
5786                  * reception of tagged packets.
5787                  * Some old firmware configurations load a default macvlan
5788                  * filter which accepts both tagged and untagged packets.
5789                  * The updating is to use a normal filter instead if needed.
5790                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5791                  * The firmware with correct configurations load the default
5792                  * macvlan filter which is expected and cannot be removed.
5793                  */
5794                 i40e_update_default_filter_setting(vsi);
5795                 i40e_config_qinq(hw, vsi);
5796         } else if (type == I40E_VSI_SRIOV) {
5797                 memset(&ctxt, 0, sizeof(ctxt));
5798                 /**
5799                  * For other VSI, the uplink_seid equals to uplink VSI's
5800                  * uplink_seid since they share same VEB
5801                  */
5802                 if (uplink_vsi == NULL)
5803                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5804                 else
5805                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5806                 ctxt.pf_num = hw->pf_id;
5807                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5808                 ctxt.uplink_seid = vsi->uplink_seid;
5809                 ctxt.connection_type = 0x1;
5810                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5811
5812                 /* Use the VEB configuration if FW >= v5.0 */
5813                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5814                         /* Configure switch ID */
5815                         ctxt.info.valid_sections |=
5816                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5817                         ctxt.info.switch_id =
5818                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5819                 }
5820
5821                 /* Configure port/vlan */
5822                 ctxt.info.valid_sections |=
5823                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5824                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5825                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5826                                                 hw->func_caps.enabled_tcmap);
5827                 if (ret != I40E_SUCCESS) {
5828                         PMD_DRV_LOG(ERR,
5829                                 "Failed to configure TC queue mapping");
5830                         goto fail_msix_alloc;
5831                 }
5832
5833                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5834                 ctxt.info.valid_sections |=
5835                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5836                 /**
5837                  * Since VSI is not created yet, only configure parameter,
5838                  * will add vsi below.
5839                  */
5840
5841                 i40e_config_qinq(hw, vsi);
5842         } else if (type == I40E_VSI_VMDQ2) {
5843                 memset(&ctxt, 0, sizeof(ctxt));
5844                 /*
5845                  * For other VSI, the uplink_seid equals to uplink VSI's
5846                  * uplink_seid since they share same VEB
5847                  */
5848                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5849                 ctxt.pf_num = hw->pf_id;
5850                 ctxt.vf_num = 0;
5851                 ctxt.uplink_seid = vsi->uplink_seid;
5852                 ctxt.connection_type = 0x1;
5853                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5854
5855                 ctxt.info.valid_sections |=
5856                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5857                 /* user_param carries flag to enable loop back */
5858                 if (user_param) {
5859                         ctxt.info.switch_id =
5860                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5861                         ctxt.info.switch_id |=
5862                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5863                 }
5864
5865                 /* Configure port/vlan */
5866                 ctxt.info.valid_sections |=
5867                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5868                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5869                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5870                                                 I40E_DEFAULT_TCMAP);
5871                 if (ret != I40E_SUCCESS) {
5872                         PMD_DRV_LOG(ERR,
5873                                 "Failed to configure TC queue mapping");
5874                         goto fail_msix_alloc;
5875                 }
5876                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5877                 ctxt.info.valid_sections |=
5878                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5879         } else if (type == I40E_VSI_FDIR) {
5880                 memset(&ctxt, 0, sizeof(ctxt));
5881                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5882                 ctxt.pf_num = hw->pf_id;
5883                 ctxt.vf_num = 0;
5884                 ctxt.uplink_seid = vsi->uplink_seid;
5885                 ctxt.connection_type = 0x1;     /* regular data port */
5886                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5887                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5888                                                 I40E_DEFAULT_TCMAP);
5889                 if (ret != I40E_SUCCESS) {
5890                         PMD_DRV_LOG(ERR,
5891                                 "Failed to configure TC queue mapping.");
5892                         goto fail_msix_alloc;
5893                 }
5894                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5895                 ctxt.info.valid_sections |=
5896                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5897         } else {
5898                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5899                 goto fail_msix_alloc;
5900         }
5901
5902         if (vsi->type != I40E_VSI_MAIN) {
5903                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5904                 if (ret != I40E_SUCCESS) {
5905                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5906                                     hw->aq.asq_last_status);
5907                         goto fail_msix_alloc;
5908                 }
5909                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5910                 vsi->info.valid_sections = 0;
5911                 vsi->seid = ctxt.seid;
5912                 vsi->vsi_id = ctxt.vsi_number;
5913                 vsi->sib_vsi_list.vsi = vsi;
5914                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5915                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5916                                           &vsi->sib_vsi_list, list);
5917                 } else {
5918                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5919                                           &vsi->sib_vsi_list, list);
5920                 }
5921         }
5922
5923         /* MAC/VLAN configuration */
5924         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5925         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5926
5927         ret = i40e_vsi_add_mac(vsi, &filter);
5928         if (ret != I40E_SUCCESS) {
5929                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5930                 goto fail_msix_alloc;
5931         }
5932
5933         /* Get VSI BW information */
5934         i40e_vsi_get_bw_config(vsi);
5935         return vsi;
5936 fail_msix_alloc:
5937         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5938 fail_queue_alloc:
5939         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5940 fail_mem:
5941         rte_free(vsi);
5942         return NULL;
5943 }
5944
5945 /* Configure vlan filter on or off */
5946 int
5947 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5948 {
5949         int i, num;
5950         struct i40e_mac_filter *f;
5951         void *temp;
5952         struct i40e_mac_filter_info *mac_filter;
5953         enum rte_mac_filter_type desired_filter;
5954         int ret = I40E_SUCCESS;
5955
5956         if (on) {
5957                 /* Filter to match MAC and VLAN */
5958                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5959         } else {
5960                 /* Filter to match only MAC */
5961                 desired_filter = RTE_MAC_PERFECT_MATCH;
5962         }
5963
5964         num = vsi->mac_num;
5965
5966         mac_filter = rte_zmalloc("mac_filter_info_data",
5967                                  num * sizeof(*mac_filter), 0);
5968         if (mac_filter == NULL) {
5969                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5970                 return I40E_ERR_NO_MEMORY;
5971         }
5972
5973         i = 0;
5974
5975         /* Remove all existing mac */
5976         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5977                 mac_filter[i] = f->mac_info;
5978                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5979                 if (ret) {
5980                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5981                                     on ? "enable" : "disable");
5982                         goto DONE;
5983                 }
5984                 i++;
5985         }
5986
5987         /* Override with new filter */
5988         for (i = 0; i < num; i++) {
5989                 mac_filter[i].filter_type = desired_filter;
5990                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5991                 if (ret) {
5992                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5993                                     on ? "enable" : "disable");
5994                         goto DONE;
5995                 }
5996         }
5997
5998 DONE:
5999         rte_free(mac_filter);
6000         return ret;
6001 }
6002
6003 /* Configure vlan stripping on or off */
6004 int
6005 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6006 {
6007         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6008         struct i40e_vsi_context ctxt;
6009         uint8_t vlan_flags;
6010         int ret = I40E_SUCCESS;
6011
6012         /* Check if it has been already on or off */
6013         if (vsi->info.valid_sections &
6014                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6015                 if (on) {
6016                         if ((vsi->info.port_vlan_flags &
6017                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6018                                 return 0; /* already on */
6019                 } else {
6020                         if ((vsi->info.port_vlan_flags &
6021                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6022                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6023                                 return 0; /* already off */
6024                 }
6025         }
6026
6027         if (on)
6028                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6029         else
6030                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6031         vsi->info.valid_sections =
6032                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6033         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6034         vsi->info.port_vlan_flags |= vlan_flags;
6035         ctxt.seid = vsi->seid;
6036         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6037         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6038         if (ret)
6039                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6040                             on ? "enable" : "disable");
6041
6042         return ret;
6043 }
6044
6045 static int
6046 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6047 {
6048         struct rte_eth_dev_data *data = dev->data;
6049         int ret;
6050         int mask = 0;
6051
6052         /* Apply vlan offload setting */
6053         mask = ETH_VLAN_STRIP_MASK |
6054                ETH_VLAN_FILTER_MASK |
6055                ETH_VLAN_EXTEND_MASK;
6056         ret = i40e_vlan_offload_set(dev, mask);
6057         if (ret) {
6058                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6059                 return ret;
6060         }
6061
6062         /* Apply pvid setting */
6063         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6064                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6065         if (ret)
6066                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6067
6068         return ret;
6069 }
6070
6071 static int
6072 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6073 {
6074         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6075
6076         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6077 }
6078
6079 static int
6080 i40e_update_flow_control(struct i40e_hw *hw)
6081 {
6082 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6083         struct i40e_link_status link_status;
6084         uint32_t rxfc = 0, txfc = 0, reg;
6085         uint8_t an_info;
6086         int ret;
6087
6088         memset(&link_status, 0, sizeof(link_status));
6089         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6090         if (ret != I40E_SUCCESS) {
6091                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6092                 goto write_reg; /* Disable flow control */
6093         }
6094
6095         an_info = hw->phy.link_info.an_info;
6096         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6097                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6098                 ret = I40E_ERR_NOT_READY;
6099                 goto write_reg; /* Disable flow control */
6100         }
6101         /**
6102          * If link auto negotiation is enabled, flow control needs to
6103          * be configured according to it
6104          */
6105         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6106         case I40E_LINK_PAUSE_RXTX:
6107                 rxfc = 1;
6108                 txfc = 1;
6109                 hw->fc.current_mode = I40E_FC_FULL;
6110                 break;
6111         case I40E_AQ_LINK_PAUSE_RX:
6112                 rxfc = 1;
6113                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6114                 break;
6115         case I40E_AQ_LINK_PAUSE_TX:
6116                 txfc = 1;
6117                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6118                 break;
6119         default:
6120                 hw->fc.current_mode = I40E_FC_NONE;
6121                 break;
6122         }
6123
6124 write_reg:
6125         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6126                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6127         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6128         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6129         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6130         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6131
6132         return ret;
6133 }
6134
6135 /* PF setup */
6136 static int
6137 i40e_pf_setup(struct i40e_pf *pf)
6138 {
6139         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6140         struct i40e_filter_control_settings settings;
6141         struct i40e_vsi *vsi;
6142         int ret;
6143
6144         /* Clear all stats counters */
6145         pf->offset_loaded = FALSE;
6146         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6147         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6148         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6149         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6150
6151         ret = i40e_pf_get_switch_config(pf);
6152         if (ret != I40E_SUCCESS) {
6153                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6154                 return ret;
6155         }
6156
6157         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6158         if (ret)
6159                 PMD_INIT_LOG(WARNING,
6160                         "failed to allocate switch domain for device %d", ret);
6161
6162         if (pf->flags & I40E_FLAG_FDIR) {
6163                 /* make queue allocated first, let FDIR use queue pair 0*/
6164                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6165                 if (ret != I40E_FDIR_QUEUE_ID) {
6166                         PMD_DRV_LOG(ERR,
6167                                 "queue allocation fails for FDIR: ret =%d",
6168                                 ret);
6169                         pf->flags &= ~I40E_FLAG_FDIR;
6170                 }
6171         }
6172         /*  main VSI setup */
6173         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6174         if (!vsi) {
6175                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6176                 return I40E_ERR_NOT_READY;
6177         }
6178         pf->main_vsi = vsi;
6179
6180         /* Configure filter control */
6181         memset(&settings, 0, sizeof(settings));
6182         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6183                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6184         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6185                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6186         else {
6187                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6188                         hw->func_caps.rss_table_size);
6189                 return I40E_ERR_PARAM;
6190         }
6191         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6192                 hw->func_caps.rss_table_size);
6193         pf->hash_lut_size = hw->func_caps.rss_table_size;
6194
6195         /* Enable ethtype and macvlan filters */
6196         settings.enable_ethtype = TRUE;
6197         settings.enable_macvlan = TRUE;
6198         ret = i40e_set_filter_control(hw, &settings);
6199         if (ret)
6200                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6201                                                                 ret);
6202
6203         /* Update flow control according to the auto negotiation */
6204         i40e_update_flow_control(hw);
6205
6206         return I40E_SUCCESS;
6207 }
6208
6209 int
6210 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6211 {
6212         uint32_t reg;
6213         uint16_t j;
6214
6215         /**
6216          * Set or clear TX Queue Disable flags,
6217          * which is required by hardware.
6218          */
6219         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6220         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6221
6222         /* Wait until the request is finished */
6223         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6224                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6225                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6226                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6227                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6228                                                         & 0x1))) {
6229                         break;
6230                 }
6231         }
6232         if (on) {
6233                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6234                         return I40E_SUCCESS; /* already on, skip next steps */
6235
6236                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6237                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6238         } else {
6239                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6240                         return I40E_SUCCESS; /* already off, skip next steps */
6241                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6242         }
6243         /* Write the register */
6244         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6245         /* Check the result */
6246         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6247                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6248                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6249                 if (on) {
6250                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6251                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6252                                 break;
6253                 } else {
6254                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6255                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6256                                 break;
6257                 }
6258         }
6259         /* Check if it is timeout */
6260         if (j >= I40E_CHK_Q_ENA_COUNT) {
6261                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6262                             (on ? "enable" : "disable"), q_idx);
6263                 return I40E_ERR_TIMEOUT;
6264         }
6265
6266         return I40E_SUCCESS;
6267 }
6268
6269 /* Swith on or off the tx queues */
6270 static int
6271 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6272 {
6273         struct rte_eth_dev_data *dev_data = pf->dev_data;
6274         struct i40e_tx_queue *txq;
6275         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6276         uint16_t i;
6277         int ret;
6278
6279         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6280                 txq = dev_data->tx_queues[i];
6281                 /* Don't operate the queue if not configured or
6282                  * if starting only per queue */
6283                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6284                         continue;
6285                 if (on)
6286                         ret = i40e_dev_tx_queue_start(dev, i);
6287                 else
6288                         ret = i40e_dev_tx_queue_stop(dev, i);
6289                 if ( ret != I40E_SUCCESS)
6290                         return ret;
6291         }
6292
6293         return I40E_SUCCESS;
6294 }
6295
6296 int
6297 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6298 {
6299         uint32_t reg;
6300         uint16_t j;
6301
6302         /* Wait until the request is finished */
6303         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6304                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6305                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6306                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6307                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6308                         break;
6309         }
6310
6311         if (on) {
6312                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6313                         return I40E_SUCCESS; /* Already on, skip next steps */
6314                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6315         } else {
6316                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6317                         return I40E_SUCCESS; /* Already off, skip next steps */
6318                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6319         }
6320
6321         /* Write the register */
6322         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6323         /* Check the result */
6324         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6325                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6326                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6327                 if (on) {
6328                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6329                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6330                                 break;
6331                 } else {
6332                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6333                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6334                                 break;
6335                 }
6336         }
6337
6338         /* Check if it is timeout */
6339         if (j >= I40E_CHK_Q_ENA_COUNT) {
6340                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6341                             (on ? "enable" : "disable"), q_idx);
6342                 return I40E_ERR_TIMEOUT;
6343         }
6344
6345         return I40E_SUCCESS;
6346 }
6347 /* Switch on or off the rx queues */
6348 static int
6349 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6350 {
6351         struct rte_eth_dev_data *dev_data = pf->dev_data;
6352         struct i40e_rx_queue *rxq;
6353         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6354         uint16_t i;
6355         int ret;
6356
6357         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6358                 rxq = dev_data->rx_queues[i];
6359                 /* Don't operate the queue if not configured or
6360                  * if starting only per queue */
6361                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6362                         continue;
6363                 if (on)
6364                         ret = i40e_dev_rx_queue_start(dev, i);
6365                 else
6366                         ret = i40e_dev_rx_queue_stop(dev, i);
6367                 if (ret != I40E_SUCCESS)
6368                         return ret;
6369         }
6370
6371         return I40E_SUCCESS;
6372 }
6373
6374 /* Switch on or off all the rx/tx queues */
6375 int
6376 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6377 {
6378         int ret;
6379
6380         if (on) {
6381                 /* enable rx queues before enabling tx queues */
6382                 ret = i40e_dev_switch_rx_queues(pf, on);
6383                 if (ret) {
6384                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6385                         return ret;
6386                 }
6387                 ret = i40e_dev_switch_tx_queues(pf, on);
6388         } else {
6389                 /* Stop tx queues before stopping rx queues */
6390                 ret = i40e_dev_switch_tx_queues(pf, on);
6391                 if (ret) {
6392                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6393                         return ret;
6394                 }
6395                 ret = i40e_dev_switch_rx_queues(pf, on);
6396         }
6397
6398         return ret;
6399 }
6400
6401 /* Initialize VSI for TX */
6402 static int
6403 i40e_dev_tx_init(struct i40e_pf *pf)
6404 {
6405         struct rte_eth_dev_data *data = pf->dev_data;
6406         uint16_t i;
6407         uint32_t ret = I40E_SUCCESS;
6408         struct i40e_tx_queue *txq;
6409
6410         for (i = 0; i < data->nb_tx_queues; i++) {
6411                 txq = data->tx_queues[i];
6412                 if (!txq || !txq->q_set)
6413                         continue;
6414                 ret = i40e_tx_queue_init(txq);
6415                 if (ret != I40E_SUCCESS)
6416                         break;
6417         }
6418         if (ret == I40E_SUCCESS)
6419                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6420                                      ->eth_dev);
6421
6422         return ret;
6423 }
6424
6425 /* Initialize VSI for RX */
6426 static int
6427 i40e_dev_rx_init(struct i40e_pf *pf)
6428 {
6429         struct rte_eth_dev_data *data = pf->dev_data;
6430         int ret = I40E_SUCCESS;
6431         uint16_t i;
6432         struct i40e_rx_queue *rxq;
6433
6434         i40e_pf_config_mq_rx(pf);
6435         for (i = 0; i < data->nb_rx_queues; i++) {
6436                 rxq = data->rx_queues[i];
6437                 if (!rxq || !rxq->q_set)
6438                         continue;
6439
6440                 ret = i40e_rx_queue_init(rxq);
6441                 if (ret != I40E_SUCCESS) {
6442                         PMD_DRV_LOG(ERR,
6443                                 "Failed to do RX queue initialization");
6444                         break;
6445                 }
6446         }
6447         if (ret == I40E_SUCCESS)
6448                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6449                                      ->eth_dev);
6450
6451         return ret;
6452 }
6453
6454 static int
6455 i40e_dev_rxtx_init(struct i40e_pf *pf)
6456 {
6457         int err;
6458
6459         err = i40e_dev_tx_init(pf);
6460         if (err) {
6461                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6462                 return err;
6463         }
6464         err = i40e_dev_rx_init(pf);
6465         if (err) {
6466                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6467                 return err;
6468         }
6469
6470         return err;
6471 }
6472
6473 static int
6474 i40e_vmdq_setup(struct rte_eth_dev *dev)
6475 {
6476         struct rte_eth_conf *conf = &dev->data->dev_conf;
6477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6478         int i, err, conf_vsis, j, loop;
6479         struct i40e_vsi *vsi;
6480         struct i40e_vmdq_info *vmdq_info;
6481         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6482         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6483
6484         /*
6485          * Disable interrupt to avoid message from VF. Furthermore, it will
6486          * avoid race condition in VSI creation/destroy.
6487          */
6488         i40e_pf_disable_irq0(hw);
6489
6490         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6491                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6492                 return -ENOTSUP;
6493         }
6494
6495         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6496         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6497                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6498                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6499                         pf->max_nb_vmdq_vsi);
6500                 return -ENOTSUP;
6501         }
6502
6503         if (pf->vmdq != NULL) {
6504                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6505                 return 0;
6506         }
6507
6508         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6509                                 sizeof(*vmdq_info) * conf_vsis, 0);
6510
6511         if (pf->vmdq == NULL) {
6512                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6513                 return -ENOMEM;
6514         }
6515
6516         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6517
6518         /* Create VMDQ VSI */
6519         for (i = 0; i < conf_vsis; i++) {
6520                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6521                                 vmdq_conf->enable_loop_back);
6522                 if (vsi == NULL) {
6523                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6524                         err = -1;
6525                         goto err_vsi_setup;
6526                 }
6527                 vmdq_info = &pf->vmdq[i];
6528                 vmdq_info->pf = pf;
6529                 vmdq_info->vsi = vsi;
6530         }
6531         pf->nb_cfg_vmdq_vsi = conf_vsis;
6532
6533         /* Configure Vlan */
6534         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6535         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6536                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6537                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6538                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6539                                         vmdq_conf->pool_map[i].vlan_id, j);
6540
6541                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6542                                                 vmdq_conf->pool_map[i].vlan_id);
6543                                 if (err) {
6544                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6545                                         err = -1;
6546                                         goto err_vsi_setup;
6547                                 }
6548                         }
6549                 }
6550         }
6551
6552         i40e_pf_enable_irq0(hw);
6553
6554         return 0;
6555
6556 err_vsi_setup:
6557         for (i = 0; i < conf_vsis; i++)
6558                 if (pf->vmdq[i].vsi == NULL)
6559                         break;
6560                 else
6561                         i40e_vsi_release(pf->vmdq[i].vsi);
6562
6563         rte_free(pf->vmdq);
6564         pf->vmdq = NULL;
6565         i40e_pf_enable_irq0(hw);
6566         return err;
6567 }
6568
6569 static void
6570 i40e_stat_update_32(struct i40e_hw *hw,
6571                    uint32_t reg,
6572                    bool offset_loaded,
6573                    uint64_t *offset,
6574                    uint64_t *stat)
6575 {
6576         uint64_t new_data;
6577
6578         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6579         if (!offset_loaded)
6580                 *offset = new_data;
6581
6582         if (new_data >= *offset)
6583                 *stat = (uint64_t)(new_data - *offset);
6584         else
6585                 *stat = (uint64_t)((new_data +
6586                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6587 }
6588
6589 static void
6590 i40e_stat_update_48(struct i40e_hw *hw,
6591                    uint32_t hireg,
6592                    uint32_t loreg,
6593                    bool offset_loaded,
6594                    uint64_t *offset,
6595                    uint64_t *stat)
6596 {
6597         uint64_t new_data;
6598
6599         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6600         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6601                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6602
6603         if (!offset_loaded)
6604                 *offset = new_data;
6605
6606         if (new_data >= *offset)
6607                 *stat = new_data - *offset;
6608         else
6609                 *stat = (uint64_t)((new_data +
6610                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6611
6612         *stat &= I40E_48_BIT_MASK;
6613 }
6614
6615 /* Disable IRQ0 */
6616 void
6617 i40e_pf_disable_irq0(struct i40e_hw *hw)
6618 {
6619         /* Disable all interrupt types */
6620         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6621                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6622         I40E_WRITE_FLUSH(hw);
6623 }
6624
6625 /* Enable IRQ0 */
6626 void
6627 i40e_pf_enable_irq0(struct i40e_hw *hw)
6628 {
6629         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6630                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6631                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6632                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6633         I40E_WRITE_FLUSH(hw);
6634 }
6635
6636 static void
6637 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6638 {
6639         /* read pending request and disable first */
6640         i40e_pf_disable_irq0(hw);
6641         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6642         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6643                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6644
6645         if (no_queue)
6646                 /* Link no queues with irq0 */
6647                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6648                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6649 }
6650
6651 static void
6652 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6653 {
6654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6656         int i;
6657         uint16_t abs_vf_id;
6658         uint32_t index, offset, val;
6659
6660         if (!pf->vfs)
6661                 return;
6662         /**
6663          * Try to find which VF trigger a reset, use absolute VF id to access
6664          * since the reg is global register.
6665          */
6666         for (i = 0; i < pf->vf_num; i++) {
6667                 abs_vf_id = hw->func_caps.vf_base_id + i;
6668                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6669                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6670                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6671                 /* VFR event occurred */
6672                 if (val & (0x1 << offset)) {
6673                         int ret;
6674
6675                         /* Clear the event first */
6676                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6677                                                         (0x1 << offset));
6678                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6679                         /**
6680                          * Only notify a VF reset event occurred,
6681                          * don't trigger another SW reset
6682                          */
6683                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6684                         if (ret != I40E_SUCCESS)
6685                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6686                 }
6687         }
6688 }
6689
6690 static void
6691 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6692 {
6693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6694         int i;
6695
6696         for (i = 0; i < pf->vf_num; i++)
6697                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6698 }
6699
6700 static void
6701 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6702 {
6703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6704         struct i40e_arq_event_info info;
6705         uint16_t pending, opcode;
6706         int ret;
6707
6708         info.buf_len = I40E_AQ_BUF_SZ;
6709         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6710         if (!info.msg_buf) {
6711                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6712                 return;
6713         }
6714
6715         pending = 1;
6716         while (pending) {
6717                 ret = i40e_clean_arq_element(hw, &info, &pending);
6718
6719                 if (ret != I40E_SUCCESS) {
6720                         PMD_DRV_LOG(INFO,
6721                                 "Failed to read msg from AdminQ, aq_err: %u",
6722                                 hw->aq.asq_last_status);
6723                         break;
6724                 }
6725                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6726
6727                 switch (opcode) {
6728                 case i40e_aqc_opc_send_msg_to_pf:
6729                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6730                         i40e_pf_host_handle_vf_msg(dev,
6731                                         rte_le_to_cpu_16(info.desc.retval),
6732                                         rte_le_to_cpu_32(info.desc.cookie_high),
6733                                         rte_le_to_cpu_32(info.desc.cookie_low),
6734                                         info.msg_buf,
6735                                         info.msg_len);
6736                         break;
6737                 case i40e_aqc_opc_get_link_status:
6738                         ret = i40e_dev_link_update(dev, 0);
6739                         if (!ret)
6740                                 _rte_eth_dev_callback_process(dev,
6741                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6742                         break;
6743                 default:
6744                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6745                                     opcode);
6746                         break;
6747                 }
6748         }
6749         rte_free(info.msg_buf);
6750 }
6751
6752 /**
6753  * Interrupt handler triggered by NIC  for handling
6754  * specific interrupt.
6755  *
6756  * @param handle
6757  *  Pointer to interrupt handle.
6758  * @param param
6759  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6760  *
6761  * @return
6762  *  void
6763  */
6764 static void
6765 i40e_dev_interrupt_handler(void *param)
6766 {
6767         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6768         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6769         uint32_t icr0;
6770
6771         /* Disable interrupt */
6772         i40e_pf_disable_irq0(hw);
6773
6774         /* read out interrupt causes */
6775         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6776
6777         /* No interrupt event indicated */
6778         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6779                 PMD_DRV_LOG(INFO, "No interrupt event");
6780                 goto done;
6781         }
6782         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6783                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6784         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6785                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6786         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6787                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6788         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6789                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6790         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6791                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6792         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6793                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6794         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6795                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6796
6797         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6798                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6799                 i40e_dev_handle_vfr_event(dev);
6800         }
6801         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6802                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6803                 i40e_dev_handle_aq_msg(dev);
6804         }
6805
6806 done:
6807         /* Enable interrupt */
6808         i40e_pf_enable_irq0(hw);
6809 }
6810
6811 static void
6812 i40e_dev_alarm_handler(void *param)
6813 {
6814         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6816         uint32_t icr0;
6817
6818         /* Disable interrupt */
6819         i40e_pf_disable_irq0(hw);
6820
6821         /* read out interrupt causes */
6822         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6823
6824         /* No interrupt event indicated */
6825         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6826                 goto done;
6827         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6828                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6829         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6830                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6831         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6832                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6833         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6834                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6835         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6836                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6837         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6838                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6839         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6840                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6841
6842         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6843                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6844                 i40e_dev_handle_vfr_event(dev);
6845         }
6846         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6847                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6848                 i40e_dev_handle_aq_msg(dev);
6849         }
6850
6851 done:
6852         /* Enable interrupt */
6853         i40e_pf_enable_irq0(hw);
6854         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6855                           i40e_dev_alarm_handler, dev);
6856 }
6857
6858 int
6859 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6860                          struct i40e_macvlan_filter *filter,
6861                          int total)
6862 {
6863         int ele_num, ele_buff_size;
6864         int num, actual_num, i;
6865         uint16_t flags;
6866         int ret = I40E_SUCCESS;
6867         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6868         struct i40e_aqc_add_macvlan_element_data *req_list;
6869
6870         if (filter == NULL  || total == 0)
6871                 return I40E_ERR_PARAM;
6872         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6873         ele_buff_size = hw->aq.asq_buf_size;
6874
6875         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6876         if (req_list == NULL) {
6877                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6878                 return I40E_ERR_NO_MEMORY;
6879         }
6880
6881         num = 0;
6882         do {
6883                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6884                 memset(req_list, 0, ele_buff_size);
6885
6886                 for (i = 0; i < actual_num; i++) {
6887                         rte_memcpy(req_list[i].mac_addr,
6888                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6889                         req_list[i].vlan_tag =
6890                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6891
6892                         switch (filter[num + i].filter_type) {
6893                         case RTE_MAC_PERFECT_MATCH:
6894                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6895                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6896                                 break;
6897                         case RTE_MACVLAN_PERFECT_MATCH:
6898                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6899                                 break;
6900                         case RTE_MAC_HASH_MATCH:
6901                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6902                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6903                                 break;
6904                         case RTE_MACVLAN_HASH_MATCH:
6905                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6906                                 break;
6907                         default:
6908                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6909                                 ret = I40E_ERR_PARAM;
6910                                 goto DONE;
6911                         }
6912
6913                         req_list[i].queue_number = 0;
6914
6915                         req_list[i].flags = rte_cpu_to_le_16(flags);
6916                 }
6917
6918                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6919                                                 actual_num, NULL);
6920                 if (ret != I40E_SUCCESS) {
6921                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6922                         goto DONE;
6923                 }
6924                 num += actual_num;
6925         } while (num < total);
6926
6927 DONE:
6928         rte_free(req_list);
6929         return ret;
6930 }
6931
6932 int
6933 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6934                             struct i40e_macvlan_filter *filter,
6935                             int total)
6936 {
6937         int ele_num, ele_buff_size;
6938         int num, actual_num, i;
6939         uint16_t flags;
6940         int ret = I40E_SUCCESS;
6941         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6942         struct i40e_aqc_remove_macvlan_element_data *req_list;
6943
6944         if (filter == NULL  || total == 0)
6945                 return I40E_ERR_PARAM;
6946
6947         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6948         ele_buff_size = hw->aq.asq_buf_size;
6949
6950         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6951         if (req_list == NULL) {
6952                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6953                 return I40E_ERR_NO_MEMORY;
6954         }
6955
6956         num = 0;
6957         do {
6958                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6959                 memset(req_list, 0, ele_buff_size);
6960
6961                 for (i = 0; i < actual_num; i++) {
6962                         rte_memcpy(req_list[i].mac_addr,
6963                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6964                         req_list[i].vlan_tag =
6965                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6966
6967                         switch (filter[num + i].filter_type) {
6968                         case RTE_MAC_PERFECT_MATCH:
6969                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6970                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6971                                 break;
6972                         case RTE_MACVLAN_PERFECT_MATCH:
6973                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6974                                 break;
6975                         case RTE_MAC_HASH_MATCH:
6976                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6977                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6978                                 break;
6979                         case RTE_MACVLAN_HASH_MATCH:
6980                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6981                                 break;
6982                         default:
6983                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6984                                 ret = I40E_ERR_PARAM;
6985                                 goto DONE;
6986                         }
6987                         req_list[i].flags = rte_cpu_to_le_16(flags);
6988                 }
6989
6990                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6991                                                 actual_num, NULL);
6992                 if (ret != I40E_SUCCESS) {
6993                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6994                         goto DONE;
6995                 }
6996                 num += actual_num;
6997         } while (num < total);
6998
6999 DONE:
7000         rte_free(req_list);
7001         return ret;
7002 }
7003
7004 /* Find out specific MAC filter */
7005 static struct i40e_mac_filter *
7006 i40e_find_mac_filter(struct i40e_vsi *vsi,
7007                          struct rte_ether_addr *macaddr)
7008 {
7009         struct i40e_mac_filter *f;
7010
7011         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7012                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7013                         return f;
7014         }
7015
7016         return NULL;
7017 }
7018
7019 static bool
7020 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7021                          uint16_t vlan_id)
7022 {
7023         uint32_t vid_idx, vid_bit;
7024
7025         if (vlan_id > ETH_VLAN_ID_MAX)
7026                 return 0;
7027
7028         vid_idx = I40E_VFTA_IDX(vlan_id);
7029         vid_bit = I40E_VFTA_BIT(vlan_id);
7030
7031         if (vsi->vfta[vid_idx] & vid_bit)
7032                 return 1;
7033         else
7034                 return 0;
7035 }
7036
7037 static void
7038 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7039                        uint16_t vlan_id, bool on)
7040 {
7041         uint32_t vid_idx, vid_bit;
7042
7043         vid_idx = I40E_VFTA_IDX(vlan_id);
7044         vid_bit = I40E_VFTA_BIT(vlan_id);
7045
7046         if (on)
7047                 vsi->vfta[vid_idx] |= vid_bit;
7048         else
7049                 vsi->vfta[vid_idx] &= ~vid_bit;
7050 }
7051
7052 void
7053 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7054                      uint16_t vlan_id, bool on)
7055 {
7056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7057         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7058         int ret;
7059
7060         if (vlan_id > ETH_VLAN_ID_MAX)
7061                 return;
7062
7063         i40e_store_vlan_filter(vsi, vlan_id, on);
7064
7065         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7066                 return;
7067
7068         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7069
7070         if (on) {
7071                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7072                                        &vlan_data, 1, NULL);
7073                 if (ret != I40E_SUCCESS)
7074                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7075         } else {
7076                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7077                                           &vlan_data, 1, NULL);
7078                 if (ret != I40E_SUCCESS)
7079                         PMD_DRV_LOG(ERR,
7080                                     "Failed to remove vlan filter");
7081         }
7082 }
7083
7084 /**
7085  * Find all vlan options for specific mac addr,
7086  * return with actual vlan found.
7087  */
7088 int
7089 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7090                            struct i40e_macvlan_filter *mv_f,
7091                            int num, struct rte_ether_addr *addr)
7092 {
7093         int i;
7094         uint32_t j, k;
7095
7096         /**
7097          * Not to use i40e_find_vlan_filter to decrease the loop time,
7098          * although the code looks complex.
7099           */
7100         if (num < vsi->vlan_num)
7101                 return I40E_ERR_PARAM;
7102
7103         i = 0;
7104         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7105                 if (vsi->vfta[j]) {
7106                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7107                                 if (vsi->vfta[j] & (1 << k)) {
7108                                         if (i > num - 1) {
7109                                                 PMD_DRV_LOG(ERR,
7110                                                         "vlan number doesn't match");
7111                                                 return I40E_ERR_PARAM;
7112                                         }
7113                                         rte_memcpy(&mv_f[i].macaddr,
7114                                                         addr, ETH_ADDR_LEN);
7115                                         mv_f[i].vlan_id =
7116                                                 j * I40E_UINT32_BIT_SIZE + k;
7117                                         i++;
7118                                 }
7119                         }
7120                 }
7121         }
7122         return I40E_SUCCESS;
7123 }
7124
7125 static inline int
7126 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7127                            struct i40e_macvlan_filter *mv_f,
7128                            int num,
7129                            uint16_t vlan)
7130 {
7131         int i = 0;
7132         struct i40e_mac_filter *f;
7133
7134         if (num < vsi->mac_num)
7135                 return I40E_ERR_PARAM;
7136
7137         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7138                 if (i > num - 1) {
7139                         PMD_DRV_LOG(ERR, "buffer number not match");
7140                         return I40E_ERR_PARAM;
7141                 }
7142                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7143                                 ETH_ADDR_LEN);
7144                 mv_f[i].vlan_id = vlan;
7145                 mv_f[i].filter_type = f->mac_info.filter_type;
7146                 i++;
7147         }
7148
7149         return I40E_SUCCESS;
7150 }
7151
7152 static int
7153 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7154 {
7155         int i, j, num;
7156         struct i40e_mac_filter *f;
7157         struct i40e_macvlan_filter *mv_f;
7158         int ret = I40E_SUCCESS;
7159
7160         if (vsi == NULL || vsi->mac_num == 0)
7161                 return I40E_ERR_PARAM;
7162
7163         /* Case that no vlan is set */
7164         if (vsi->vlan_num == 0)
7165                 num = vsi->mac_num;
7166         else
7167                 num = vsi->mac_num * vsi->vlan_num;
7168
7169         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7170         if (mv_f == NULL) {
7171                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7172                 return I40E_ERR_NO_MEMORY;
7173         }
7174
7175         i = 0;
7176         if (vsi->vlan_num == 0) {
7177                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7178                         rte_memcpy(&mv_f[i].macaddr,
7179                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7180                         mv_f[i].filter_type = f->mac_info.filter_type;
7181                         mv_f[i].vlan_id = 0;
7182                         i++;
7183                 }
7184         } else {
7185                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7186                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7187                                         vsi->vlan_num, &f->mac_info.mac_addr);
7188                         if (ret != I40E_SUCCESS)
7189                                 goto DONE;
7190                         for (j = i; j < i + vsi->vlan_num; j++)
7191                                 mv_f[j].filter_type = f->mac_info.filter_type;
7192                         i += vsi->vlan_num;
7193                 }
7194         }
7195
7196         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7197 DONE:
7198         rte_free(mv_f);
7199
7200         return ret;
7201 }
7202
7203 int
7204 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7205 {
7206         struct i40e_macvlan_filter *mv_f;
7207         int mac_num;
7208         int ret = I40E_SUCCESS;
7209
7210         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7211                 return I40E_ERR_PARAM;
7212
7213         /* If it's already set, just return */
7214         if (i40e_find_vlan_filter(vsi,vlan))
7215                 return I40E_SUCCESS;
7216
7217         mac_num = vsi->mac_num;
7218
7219         if (mac_num == 0) {
7220                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7221                 return I40E_ERR_PARAM;
7222         }
7223
7224         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7225
7226         if (mv_f == NULL) {
7227                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7228                 return I40E_ERR_NO_MEMORY;
7229         }
7230
7231         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7232
7233         if (ret != I40E_SUCCESS)
7234                 goto DONE;
7235
7236         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7237
7238         if (ret != I40E_SUCCESS)
7239                 goto DONE;
7240
7241         i40e_set_vlan_filter(vsi, vlan, 1);
7242
7243         vsi->vlan_num++;
7244         ret = I40E_SUCCESS;
7245 DONE:
7246         rte_free(mv_f);
7247         return ret;
7248 }
7249
7250 int
7251 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7252 {
7253         struct i40e_macvlan_filter *mv_f;
7254         int mac_num;
7255         int ret = I40E_SUCCESS;
7256
7257         /**
7258          * Vlan 0 is the generic filter for untagged packets
7259          * and can't be removed.
7260          */
7261         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7262                 return I40E_ERR_PARAM;
7263
7264         /* If can't find it, just return */
7265         if (!i40e_find_vlan_filter(vsi, vlan))
7266                 return I40E_ERR_PARAM;
7267
7268         mac_num = vsi->mac_num;
7269
7270         if (mac_num == 0) {
7271                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7272                 return I40E_ERR_PARAM;
7273         }
7274
7275         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7276
7277         if (mv_f == NULL) {
7278                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7279                 return I40E_ERR_NO_MEMORY;
7280         }
7281
7282         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7283
7284         if (ret != I40E_SUCCESS)
7285                 goto DONE;
7286
7287         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7288
7289         if (ret != I40E_SUCCESS)
7290                 goto DONE;
7291
7292         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7293         if (vsi->vlan_num == 1) {
7294                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7295                 if (ret != I40E_SUCCESS)
7296                         goto DONE;
7297
7298                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7299                 if (ret != I40E_SUCCESS)
7300                         goto DONE;
7301         }
7302
7303         i40e_set_vlan_filter(vsi, vlan, 0);
7304
7305         vsi->vlan_num--;
7306         ret = I40E_SUCCESS;
7307 DONE:
7308         rte_free(mv_f);
7309         return ret;
7310 }
7311
7312 int
7313 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7314 {
7315         struct i40e_mac_filter *f;
7316         struct i40e_macvlan_filter *mv_f;
7317         int i, vlan_num = 0;
7318         int ret = I40E_SUCCESS;
7319
7320         /* If it's add and we've config it, return */
7321         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7322         if (f != NULL)
7323                 return I40E_SUCCESS;
7324         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7325                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7326
7327                 /**
7328                  * If vlan_num is 0, that's the first time to add mac,
7329                  * set mask for vlan_id 0.
7330                  */
7331                 if (vsi->vlan_num == 0) {
7332                         i40e_set_vlan_filter(vsi, 0, 1);
7333                         vsi->vlan_num = 1;
7334                 }
7335                 vlan_num = vsi->vlan_num;
7336         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7337                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7338                 vlan_num = 1;
7339
7340         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7341         if (mv_f == NULL) {
7342                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7343                 return I40E_ERR_NO_MEMORY;
7344         }
7345
7346         for (i = 0; i < vlan_num; i++) {
7347                 mv_f[i].filter_type = mac_filter->filter_type;
7348                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7349                                 ETH_ADDR_LEN);
7350         }
7351
7352         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7353                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7354                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7355                                         &mac_filter->mac_addr);
7356                 if (ret != I40E_SUCCESS)
7357                         goto DONE;
7358         }
7359
7360         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7361         if (ret != I40E_SUCCESS)
7362                 goto DONE;
7363
7364         /* Add the mac addr into mac list */
7365         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7366         if (f == NULL) {
7367                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7368                 ret = I40E_ERR_NO_MEMORY;
7369                 goto DONE;
7370         }
7371         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7372                         ETH_ADDR_LEN);
7373         f->mac_info.filter_type = mac_filter->filter_type;
7374         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7375         vsi->mac_num++;
7376
7377         ret = I40E_SUCCESS;
7378 DONE:
7379         rte_free(mv_f);
7380
7381         return ret;
7382 }
7383
7384 int
7385 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7386 {
7387         struct i40e_mac_filter *f;
7388         struct i40e_macvlan_filter *mv_f;
7389         int i, vlan_num;
7390         enum rte_mac_filter_type filter_type;
7391         int ret = I40E_SUCCESS;
7392
7393         /* Can't find it, return an error */
7394         f = i40e_find_mac_filter(vsi, addr);
7395         if (f == NULL)
7396                 return I40E_ERR_PARAM;
7397
7398         vlan_num = vsi->vlan_num;
7399         filter_type = f->mac_info.filter_type;
7400         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7401                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7402                 if (vlan_num == 0) {
7403                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7404                         return I40E_ERR_PARAM;
7405                 }
7406         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7407                         filter_type == RTE_MAC_HASH_MATCH)
7408                 vlan_num = 1;
7409
7410         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7411         if (mv_f == NULL) {
7412                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7413                 return I40E_ERR_NO_MEMORY;
7414         }
7415
7416         for (i = 0; i < vlan_num; i++) {
7417                 mv_f[i].filter_type = filter_type;
7418                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7419                                 ETH_ADDR_LEN);
7420         }
7421         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7422                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7423                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7424                 if (ret != I40E_SUCCESS)
7425                         goto DONE;
7426         }
7427
7428         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7429         if (ret != I40E_SUCCESS)
7430                 goto DONE;
7431
7432         /* Remove the mac addr into mac list */
7433         TAILQ_REMOVE(&vsi->mac_list, f, next);
7434         rte_free(f);
7435         vsi->mac_num--;
7436
7437         ret = I40E_SUCCESS;
7438 DONE:
7439         rte_free(mv_f);
7440         return ret;
7441 }
7442
7443 /* Configure hash enable flags for RSS */
7444 uint64_t
7445 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7446 {
7447         uint64_t hena = 0;
7448         int i;
7449
7450         if (!flags)
7451                 return hena;
7452
7453         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7454                 if (flags & (1ULL << i))
7455                         hena |= adapter->pctypes_tbl[i];
7456         }
7457
7458         return hena;
7459 }
7460
7461 /* Parse the hash enable flags */
7462 uint64_t
7463 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7464 {
7465         uint64_t rss_hf = 0;
7466
7467         if (!flags)
7468                 return rss_hf;
7469         int i;
7470
7471         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7472                 if (flags & adapter->pctypes_tbl[i])
7473                         rss_hf |= (1ULL << i);
7474         }
7475         return rss_hf;
7476 }
7477
7478 /* Disable RSS */
7479 static void
7480 i40e_pf_disable_rss(struct i40e_pf *pf)
7481 {
7482         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7483
7484         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7485         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7486         I40E_WRITE_FLUSH(hw);
7487 }
7488
7489 int
7490 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7491 {
7492         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7494         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7495                            I40E_VFQF_HKEY_MAX_INDEX :
7496                            I40E_PFQF_HKEY_MAX_INDEX;
7497         int ret = 0;
7498
7499         if (!key || key_len == 0) {
7500                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7501                 return 0;
7502         } else if (key_len != (key_idx + 1) *
7503                 sizeof(uint32_t)) {
7504                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7505                 return -EINVAL;
7506         }
7507
7508         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7509                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7510                         (struct i40e_aqc_get_set_rss_key_data *)key;
7511
7512                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7513                 if (ret)
7514                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7515         } else {
7516                 uint32_t *hash_key = (uint32_t *)key;
7517                 uint16_t i;
7518
7519                 if (vsi->type == I40E_VSI_SRIOV) {
7520                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7521                                 I40E_WRITE_REG(
7522                                         hw,
7523                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7524                                         hash_key[i]);
7525
7526                 } else {
7527                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7528                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7529                                                hash_key[i]);
7530                 }
7531                 I40E_WRITE_FLUSH(hw);
7532         }
7533
7534         return ret;
7535 }
7536
7537 static int
7538 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7539 {
7540         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7541         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7542         uint32_t reg;
7543         int ret;
7544
7545         if (!key || !key_len)
7546                 return 0;
7547
7548         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7549                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7550                         (struct i40e_aqc_get_set_rss_key_data *)key);
7551                 if (ret) {
7552                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7553                         return ret;
7554                 }
7555         } else {
7556                 uint32_t *key_dw = (uint32_t *)key;
7557                 uint16_t i;
7558
7559                 if (vsi->type == I40E_VSI_SRIOV) {
7560                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7561                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7562                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7563                         }
7564                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7565                                    sizeof(uint32_t);
7566                 } else {
7567                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7568                                 reg = I40E_PFQF_HKEY(i);
7569                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7570                         }
7571                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7572                                    sizeof(uint32_t);
7573                 }
7574         }
7575         return 0;
7576 }
7577
7578 static int
7579 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7580 {
7581         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7582         uint64_t hena;
7583         int ret;
7584
7585         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7586                                rss_conf->rss_key_len);
7587         if (ret)
7588                 return ret;
7589
7590         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7591         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7592         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7593         I40E_WRITE_FLUSH(hw);
7594
7595         return 0;
7596 }
7597
7598 static int
7599 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7600                          struct rte_eth_rss_conf *rss_conf)
7601 {
7602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7604         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7605         uint64_t hena;
7606
7607         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7608         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7609
7610         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7611                 if (rss_hf != 0) /* Enable RSS */
7612                         return -EINVAL;
7613                 return 0; /* Nothing to do */
7614         }
7615         /* RSS enabled */
7616         if (rss_hf == 0) /* Disable RSS */
7617                 return -EINVAL;
7618
7619         return i40e_hw_rss_hash_set(pf, rss_conf);
7620 }
7621
7622 static int
7623 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7624                            struct rte_eth_rss_conf *rss_conf)
7625 {
7626         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7627         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7628         uint64_t hena;
7629         int ret;
7630
7631         if (!rss_conf)
7632                 return -EINVAL;
7633
7634         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7635                          &rss_conf->rss_key_len);
7636         if (ret)
7637                 return ret;
7638
7639         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7640         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7641         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7642
7643         return 0;
7644 }
7645
7646 static int
7647 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7648 {
7649         switch (filter_type) {
7650         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7651                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7652                 break;
7653         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7654                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7655                 break;
7656         case RTE_TUNNEL_FILTER_IMAC_TENID:
7657                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7658                 break;
7659         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7660                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7661                 break;
7662         case ETH_TUNNEL_FILTER_IMAC:
7663                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7664                 break;
7665         case ETH_TUNNEL_FILTER_OIP:
7666                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7667                 break;
7668         case ETH_TUNNEL_FILTER_IIP:
7669                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7670                 break;
7671         default:
7672                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7673                 return -EINVAL;
7674         }
7675
7676         return 0;
7677 }
7678
7679 /* Convert tunnel filter structure */
7680 static int
7681 i40e_tunnel_filter_convert(
7682         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7683         struct i40e_tunnel_filter *tunnel_filter)
7684 {
7685         rte_ether_addr_copy((struct rte_ether_addr *)
7686                         &cld_filter->element.outer_mac,
7687                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7688         rte_ether_addr_copy((struct rte_ether_addr *)
7689                         &cld_filter->element.inner_mac,
7690                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7691         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7692         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7693              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7694             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7695                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7696         else
7697                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7698         tunnel_filter->input.flags = cld_filter->element.flags;
7699         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7700         tunnel_filter->queue = cld_filter->element.queue_number;
7701         rte_memcpy(tunnel_filter->input.general_fields,
7702                    cld_filter->general_fields,
7703                    sizeof(cld_filter->general_fields));
7704
7705         return 0;
7706 }
7707
7708 /* Check if there exists the tunnel filter */
7709 struct i40e_tunnel_filter *
7710 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7711                              const struct i40e_tunnel_filter_input *input)
7712 {
7713         int ret;
7714
7715         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7716         if (ret < 0)
7717                 return NULL;
7718
7719         return tunnel_rule->hash_map[ret];
7720 }
7721
7722 /* Add a tunnel filter into the SW list */
7723 static int
7724 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7725                              struct i40e_tunnel_filter *tunnel_filter)
7726 {
7727         struct i40e_tunnel_rule *rule = &pf->tunnel;
7728         int ret;
7729
7730         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7731         if (ret < 0) {
7732                 PMD_DRV_LOG(ERR,
7733                             "Failed to insert tunnel filter to hash table %d!",
7734                             ret);
7735                 return ret;
7736         }
7737         rule->hash_map[ret] = tunnel_filter;
7738
7739         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7740
7741         return 0;
7742 }
7743
7744 /* Delete a tunnel filter from the SW list */
7745 int
7746 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7747                           struct i40e_tunnel_filter_input *input)
7748 {
7749         struct i40e_tunnel_rule *rule = &pf->tunnel;
7750         struct i40e_tunnel_filter *tunnel_filter;
7751         int ret;
7752
7753         ret = rte_hash_del_key(rule->hash_table, input);
7754         if (ret < 0) {
7755                 PMD_DRV_LOG(ERR,
7756                             "Failed to delete tunnel filter to hash table %d!",
7757                             ret);
7758                 return ret;
7759         }
7760         tunnel_filter = rule->hash_map[ret];
7761         rule->hash_map[ret] = NULL;
7762
7763         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7764         rte_free(tunnel_filter);
7765
7766         return 0;
7767 }
7768
7769 int
7770 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7771                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7772                         uint8_t add)
7773 {
7774         uint16_t ip_type;
7775         uint32_t ipv4_addr, ipv4_addr_le;
7776         uint8_t i, tun_type = 0;
7777         /* internal varialbe to convert ipv6 byte order */
7778         uint32_t convert_ipv6[4];
7779         int val, ret = 0;
7780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7781         struct i40e_vsi *vsi = pf->main_vsi;
7782         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7783         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7784         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7785         struct i40e_tunnel_filter *tunnel, *node;
7786         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7787
7788         cld_filter = rte_zmalloc("tunnel_filter",
7789                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7790         0);
7791
7792         if (NULL == cld_filter) {
7793                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7794                 return -ENOMEM;
7795         }
7796         pfilter = cld_filter;
7797
7798         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7799                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7800         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7801                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7802
7803         pfilter->element.inner_vlan =
7804                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7805         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7806                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7807                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7808                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7809                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7810                                 &ipv4_addr_le,
7811                                 sizeof(pfilter->element.ipaddr.v4.data));
7812         } else {
7813                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7814                 for (i = 0; i < 4; i++) {
7815                         convert_ipv6[i] =
7816                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7817                 }
7818                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7819                            &convert_ipv6,
7820                            sizeof(pfilter->element.ipaddr.v6.data));
7821         }
7822
7823         /* check tunneled type */
7824         switch (tunnel_filter->tunnel_type) {
7825         case RTE_TUNNEL_TYPE_VXLAN:
7826                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7827                 break;
7828         case RTE_TUNNEL_TYPE_NVGRE:
7829                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7830                 break;
7831         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7832                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7833                 break;
7834         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7835                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7836                 break;
7837         default:
7838                 /* Other tunnel types is not supported. */
7839                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7840                 rte_free(cld_filter);
7841                 return -EINVAL;
7842         }
7843
7844         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7845                                        &pfilter->element.flags);
7846         if (val < 0) {
7847                 rte_free(cld_filter);
7848                 return -EINVAL;
7849         }
7850
7851         pfilter->element.flags |= rte_cpu_to_le_16(
7852                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7853                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7854         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7855         pfilter->element.queue_number =
7856                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7857
7858         /* Check if there is the filter in SW list */
7859         memset(&check_filter, 0, sizeof(check_filter));
7860         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7861         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7862         if (add && node) {
7863                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7864                 rte_free(cld_filter);
7865                 return -EINVAL;
7866         }
7867
7868         if (!add && !node) {
7869                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7870                 rte_free(cld_filter);
7871                 return -EINVAL;
7872         }
7873
7874         if (add) {
7875                 ret = i40e_aq_add_cloud_filters(hw,
7876                                         vsi->seid, &cld_filter->element, 1);
7877                 if (ret < 0) {
7878                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7879                         rte_free(cld_filter);
7880                         return -ENOTSUP;
7881                 }
7882                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7883                 if (tunnel == NULL) {
7884                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7885                         rte_free(cld_filter);
7886                         return -ENOMEM;
7887                 }
7888
7889                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7890                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7891                 if (ret < 0)
7892                         rte_free(tunnel);
7893         } else {
7894                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7895                                                    &cld_filter->element, 1);
7896                 if (ret < 0) {
7897                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7898                         rte_free(cld_filter);
7899                         return -ENOTSUP;
7900                 }
7901                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7902         }
7903
7904         rte_free(cld_filter);
7905         return ret;
7906 }
7907
7908 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7909 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7910 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7911 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7912 #define I40E_TR_GRE_KEY_MASK                    0x400
7913 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7914 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7915
7916 static enum
7917 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7918 {
7919         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7920         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7921         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7922         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7923         enum i40e_status_code status = I40E_SUCCESS;
7924
7925         if (pf->support_multi_driver) {
7926                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7927                 return I40E_NOT_SUPPORTED;
7928         }
7929
7930         memset(&filter_replace, 0,
7931                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7932         memset(&filter_replace_buf, 0,
7933                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7934
7935         /* create L1 filter */
7936         filter_replace.old_filter_type =
7937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7938         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7939         filter_replace.tr_bit = 0;
7940
7941         /* Prepare the buffer, 3 entries */
7942         filter_replace_buf.data[0] =
7943                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7944         filter_replace_buf.data[0] |=
7945                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7946         filter_replace_buf.data[2] = 0xFF;
7947         filter_replace_buf.data[3] = 0xFF;
7948         filter_replace_buf.data[4] =
7949                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7950         filter_replace_buf.data[4] |=
7951                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7952         filter_replace_buf.data[7] = 0xF0;
7953         filter_replace_buf.data[8]
7954                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7955         filter_replace_buf.data[8] |=
7956                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7957         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7958                 I40E_TR_GENEVE_KEY_MASK |
7959                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7960         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7961                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7962                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7963
7964         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7965                                                &filter_replace_buf);
7966         if (!status && (filter_replace.old_filter_type !=
7967                         filter_replace.new_filter_type))
7968                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7969                             " original: 0x%x, new: 0x%x",
7970                             dev->device->name,
7971                             filter_replace.old_filter_type,
7972                             filter_replace.new_filter_type);
7973
7974         return status;
7975 }
7976
7977 static enum
7978 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7979 {
7980         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7981         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7982         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7983         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7984         enum i40e_status_code status = I40E_SUCCESS;
7985
7986         if (pf->support_multi_driver) {
7987                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7988                 return I40E_NOT_SUPPORTED;
7989         }
7990
7991         /* For MPLSoUDP */
7992         memset(&filter_replace, 0,
7993                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7994         memset(&filter_replace_buf, 0,
7995                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7996         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7997                 I40E_AQC_MIRROR_CLOUD_FILTER;
7998         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7999         filter_replace.new_filter_type =
8000                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8001         /* Prepare the buffer, 2 entries */
8002         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8003         filter_replace_buf.data[0] |=
8004                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8005         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8006         filter_replace_buf.data[4] |=
8007                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8009                                                &filter_replace_buf);
8010         if (status < 0)
8011                 return status;
8012         if (filter_replace.old_filter_type !=
8013             filter_replace.new_filter_type)
8014                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8015                             " original: 0x%x, new: 0x%x",
8016                             dev->device->name,
8017                             filter_replace.old_filter_type,
8018                             filter_replace.new_filter_type);
8019
8020         /* For MPLSoGRE */
8021         memset(&filter_replace, 0,
8022                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8023         memset(&filter_replace_buf, 0,
8024                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8025
8026         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8027                 I40E_AQC_MIRROR_CLOUD_FILTER;
8028         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8029         filter_replace.new_filter_type =
8030                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8031         /* Prepare the buffer, 2 entries */
8032         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8033         filter_replace_buf.data[0] |=
8034                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8035         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8036         filter_replace_buf.data[4] |=
8037                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8038
8039         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8040                                                &filter_replace_buf);
8041         if (!status && (filter_replace.old_filter_type !=
8042                         filter_replace.new_filter_type))
8043                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8044                             " original: 0x%x, new: 0x%x",
8045                             dev->device->name,
8046                             filter_replace.old_filter_type,
8047                             filter_replace.new_filter_type);
8048
8049         return status;
8050 }
8051
8052 static enum i40e_status_code
8053 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8054 {
8055         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8056         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8057         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8058         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8059         enum i40e_status_code status = I40E_SUCCESS;
8060
8061         if (pf->support_multi_driver) {
8062                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8063                 return I40E_NOT_SUPPORTED;
8064         }
8065
8066         /* For GTP-C */
8067         memset(&filter_replace, 0,
8068                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8069         memset(&filter_replace_buf, 0,
8070                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8071         /* create L1 filter */
8072         filter_replace.old_filter_type =
8073                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8074         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8075         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8076                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8077         /* Prepare the buffer, 2 entries */
8078         filter_replace_buf.data[0] =
8079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8080         filter_replace_buf.data[0] |=
8081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8082         filter_replace_buf.data[2] = 0xFF;
8083         filter_replace_buf.data[3] = 0xFF;
8084         filter_replace_buf.data[4] =
8085                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8086         filter_replace_buf.data[4] |=
8087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8088         filter_replace_buf.data[6] = 0xFF;
8089         filter_replace_buf.data[7] = 0xFF;
8090         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8091                                                &filter_replace_buf);
8092         if (status < 0)
8093                 return status;
8094         if (filter_replace.old_filter_type !=
8095             filter_replace.new_filter_type)
8096                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8097                             " original: 0x%x, new: 0x%x",
8098                             dev->device->name,
8099                             filter_replace.old_filter_type,
8100                             filter_replace.new_filter_type);
8101
8102         /* for GTP-U */
8103         memset(&filter_replace, 0,
8104                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8105         memset(&filter_replace_buf, 0,
8106                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8107         /* create L1 filter */
8108         filter_replace.old_filter_type =
8109                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8110         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8111         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8113         /* Prepare the buffer, 2 entries */
8114         filter_replace_buf.data[0] =
8115                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8116         filter_replace_buf.data[0] |=
8117                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8118         filter_replace_buf.data[2] = 0xFF;
8119         filter_replace_buf.data[3] = 0xFF;
8120         filter_replace_buf.data[4] =
8121                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8122         filter_replace_buf.data[4] |=
8123                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8124         filter_replace_buf.data[6] = 0xFF;
8125         filter_replace_buf.data[7] = 0xFF;
8126
8127         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8128                                                &filter_replace_buf);
8129         if (!status && (filter_replace.old_filter_type !=
8130                         filter_replace.new_filter_type))
8131                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8132                             " original: 0x%x, new: 0x%x",
8133                             dev->device->name,
8134                             filter_replace.old_filter_type,
8135                             filter_replace.new_filter_type);
8136
8137         return status;
8138 }
8139
8140 static enum
8141 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8142 {
8143         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8144         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8145         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8146         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8147         enum i40e_status_code status = I40E_SUCCESS;
8148
8149         if (pf->support_multi_driver) {
8150                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8151                 return I40E_NOT_SUPPORTED;
8152         }
8153
8154         /* for GTP-C */
8155         memset(&filter_replace, 0,
8156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8157         memset(&filter_replace_buf, 0,
8158                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8159         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8160         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8161         filter_replace.new_filter_type =
8162                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8163         /* Prepare the buffer, 2 entries */
8164         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8165         filter_replace_buf.data[0] |=
8166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8167         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8168         filter_replace_buf.data[4] |=
8169                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8170         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8171                                                &filter_replace_buf);
8172         if (status < 0)
8173                 return status;
8174         if (filter_replace.old_filter_type !=
8175             filter_replace.new_filter_type)
8176                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8177                             " original: 0x%x, new: 0x%x",
8178                             dev->device->name,
8179                             filter_replace.old_filter_type,
8180                             filter_replace.new_filter_type);
8181
8182         /* for GTP-U */
8183         memset(&filter_replace, 0,
8184                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8185         memset(&filter_replace_buf, 0,
8186                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8187         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8188         filter_replace.old_filter_type =
8189                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8190         filter_replace.new_filter_type =
8191                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8192         /* Prepare the buffer, 2 entries */
8193         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8194         filter_replace_buf.data[0] |=
8195                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8196         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8197         filter_replace_buf.data[4] |=
8198                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8199
8200         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8201                                                &filter_replace_buf);
8202         if (!status && (filter_replace.old_filter_type !=
8203                         filter_replace.new_filter_type))
8204                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8205                             " original: 0x%x, new: 0x%x",
8206                             dev->device->name,
8207                             filter_replace.old_filter_type,
8208                             filter_replace.new_filter_type);
8209
8210         return status;
8211 }
8212
8213 int
8214 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8215                       struct i40e_tunnel_filter_conf *tunnel_filter,
8216                       uint8_t add)
8217 {
8218         uint16_t ip_type;
8219         uint32_t ipv4_addr, ipv4_addr_le;
8220         uint8_t i, tun_type = 0;
8221         /* internal variable to convert ipv6 byte order */
8222         uint32_t convert_ipv6[4];
8223         int val, ret = 0;
8224         struct i40e_pf_vf *vf = NULL;
8225         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8226         struct i40e_vsi *vsi;
8227         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8228         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8229         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8230         struct i40e_tunnel_filter *tunnel, *node;
8231         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8232         uint32_t teid_le;
8233         bool big_buffer = 0;
8234
8235         cld_filter = rte_zmalloc("tunnel_filter",
8236                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8237                          0);
8238
8239         if (cld_filter == NULL) {
8240                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8241                 return -ENOMEM;
8242         }
8243         pfilter = cld_filter;
8244
8245         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8246                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8247         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8248                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8249
8250         pfilter->element.inner_vlan =
8251                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8252         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8253                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8254                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8255                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8256                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8257                                 &ipv4_addr_le,
8258                                 sizeof(pfilter->element.ipaddr.v4.data));
8259         } else {
8260                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8261                 for (i = 0; i < 4; i++) {
8262                         convert_ipv6[i] =
8263                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8264                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8265                 }
8266                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8267                            &convert_ipv6,
8268                            sizeof(pfilter->element.ipaddr.v6.data));
8269         }
8270
8271         /* check tunneled type */
8272         switch (tunnel_filter->tunnel_type) {
8273         case I40E_TUNNEL_TYPE_VXLAN:
8274                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8275                 break;
8276         case I40E_TUNNEL_TYPE_NVGRE:
8277                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8278                 break;
8279         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8280                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8281                 break;
8282         case I40E_TUNNEL_TYPE_MPLSoUDP:
8283                 if (!pf->mpls_replace_flag) {
8284                         i40e_replace_mpls_l1_filter(pf);
8285                         i40e_replace_mpls_cloud_filter(pf);
8286                         pf->mpls_replace_flag = 1;
8287                 }
8288                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8289                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8290                         teid_le >> 4;
8291                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8292                         (teid_le & 0xF) << 12;
8293                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8294                         0x40;
8295                 big_buffer = 1;
8296                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8297                 break;
8298         case I40E_TUNNEL_TYPE_MPLSoGRE:
8299                 if (!pf->mpls_replace_flag) {
8300                         i40e_replace_mpls_l1_filter(pf);
8301                         i40e_replace_mpls_cloud_filter(pf);
8302                         pf->mpls_replace_flag = 1;
8303                 }
8304                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8305                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8306                         teid_le >> 4;
8307                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8308                         (teid_le & 0xF) << 12;
8309                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8310                         0x0;
8311                 big_buffer = 1;
8312                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8313                 break;
8314         case I40E_TUNNEL_TYPE_GTPC:
8315                 if (!pf->gtp_replace_flag) {
8316                         i40e_replace_gtp_l1_filter(pf);
8317                         i40e_replace_gtp_cloud_filter(pf);
8318                         pf->gtp_replace_flag = 1;
8319                 }
8320                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8321                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8322                         (teid_le >> 16) & 0xFFFF;
8323                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8324                         teid_le & 0xFFFF;
8325                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8326                         0x0;
8327                 big_buffer = 1;
8328                 break;
8329         case I40E_TUNNEL_TYPE_GTPU:
8330                 if (!pf->gtp_replace_flag) {
8331                         i40e_replace_gtp_l1_filter(pf);
8332                         i40e_replace_gtp_cloud_filter(pf);
8333                         pf->gtp_replace_flag = 1;
8334                 }
8335                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8336                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8337                         (teid_le >> 16) & 0xFFFF;
8338                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8339                         teid_le & 0xFFFF;
8340                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8341                         0x0;
8342                 big_buffer = 1;
8343                 break;
8344         case I40E_TUNNEL_TYPE_QINQ:
8345                 if (!pf->qinq_replace_flag) {
8346                         ret = i40e_cloud_filter_qinq_create(pf);
8347                         if (ret < 0)
8348                                 PMD_DRV_LOG(DEBUG,
8349                                             "QinQ tunnel filter already created.");
8350                         pf->qinq_replace_flag = 1;
8351                 }
8352                 /*      Add in the General fields the values of
8353                  *      the Outer and Inner VLAN
8354                  *      Big Buffer should be set, see changes in
8355                  *      i40e_aq_add_cloud_filters
8356                  */
8357                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8358                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8359                 big_buffer = 1;
8360                 break;
8361         default:
8362                 /* Other tunnel types is not supported. */
8363                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8364                 rte_free(cld_filter);
8365                 return -EINVAL;
8366         }
8367
8368         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8369                 pfilter->element.flags =
8370                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8371         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8372                 pfilter->element.flags =
8373                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8374         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8375                 pfilter->element.flags =
8376                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8377         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8378                 pfilter->element.flags =
8379                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8380         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8381                 pfilter->element.flags |=
8382                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8383         else {
8384                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8385                                                 &pfilter->element.flags);
8386                 if (val < 0) {
8387                         rte_free(cld_filter);
8388                         return -EINVAL;
8389                 }
8390         }
8391
8392         pfilter->element.flags |= rte_cpu_to_le_16(
8393                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8394                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8395         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8396         pfilter->element.queue_number =
8397                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8398
8399         if (!tunnel_filter->is_to_vf)
8400                 vsi = pf->main_vsi;
8401         else {
8402                 if (tunnel_filter->vf_id >= pf->vf_num) {
8403                         PMD_DRV_LOG(ERR, "Invalid argument.");
8404                         rte_free(cld_filter);
8405                         return -EINVAL;
8406                 }
8407                 vf = &pf->vfs[tunnel_filter->vf_id];
8408                 vsi = vf->vsi;
8409         }
8410
8411         /* Check if there is the filter in SW list */
8412         memset(&check_filter, 0, sizeof(check_filter));
8413         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8414         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8415         check_filter.vf_id = tunnel_filter->vf_id;
8416         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8417         if (add && node) {
8418                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8419                 rte_free(cld_filter);
8420                 return -EINVAL;
8421         }
8422
8423         if (!add && !node) {
8424                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8425                 rte_free(cld_filter);
8426                 return -EINVAL;
8427         }
8428
8429         if (add) {
8430                 if (big_buffer)
8431                         ret = i40e_aq_add_cloud_filters_bb(hw,
8432                                                    vsi->seid, cld_filter, 1);
8433                 else
8434                         ret = i40e_aq_add_cloud_filters(hw,
8435                                         vsi->seid, &cld_filter->element, 1);
8436                 if (ret < 0) {
8437                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8438                         rte_free(cld_filter);
8439                         return -ENOTSUP;
8440                 }
8441                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8442                 if (tunnel == NULL) {
8443                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8444                         rte_free(cld_filter);
8445                         return -ENOMEM;
8446                 }
8447
8448                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8449                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8450                 if (ret < 0)
8451                         rte_free(tunnel);
8452         } else {
8453                 if (big_buffer)
8454                         ret = i40e_aq_rem_cloud_filters_bb(
8455                                 hw, vsi->seid, cld_filter, 1);
8456                 else
8457                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8458                                                 &cld_filter->element, 1);
8459                 if (ret < 0) {
8460                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8461                         rte_free(cld_filter);
8462                         return -ENOTSUP;
8463                 }
8464                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8465         }
8466
8467         rte_free(cld_filter);
8468         return ret;
8469 }
8470
8471 static int
8472 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8473 {
8474         uint8_t i;
8475
8476         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8477                 if (pf->vxlan_ports[i] == port)
8478                         return i;
8479         }
8480
8481         return -1;
8482 }
8483
8484 static int
8485 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8486 {
8487         int  idx, ret;
8488         uint8_t filter_idx = 0;
8489         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8490
8491         idx = i40e_get_vxlan_port_idx(pf, port);
8492
8493         /* Check if port already exists */
8494         if (idx >= 0) {
8495                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8496                 return -EINVAL;
8497         }
8498
8499         /* Now check if there is space to add the new port */
8500         idx = i40e_get_vxlan_port_idx(pf, 0);
8501         if (idx < 0) {
8502                 PMD_DRV_LOG(ERR,
8503                         "Maximum number of UDP ports reached, not adding port %d",
8504                         port);
8505                 return -ENOSPC;
8506         }
8507
8508         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8509                                         &filter_idx, NULL);
8510         if (ret < 0) {
8511                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8512                 return -1;
8513         }
8514
8515         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8516                          port,  filter_idx);
8517
8518         /* New port: add it and mark its index in the bitmap */
8519         pf->vxlan_ports[idx] = port;
8520         pf->vxlan_bitmap |= (1 << idx);
8521
8522         if (!(pf->flags & I40E_FLAG_VXLAN))
8523                 pf->flags |= I40E_FLAG_VXLAN;
8524
8525         return 0;
8526 }
8527
8528 static int
8529 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8530 {
8531         int idx;
8532         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8533
8534         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8535                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8536                 return -EINVAL;
8537         }
8538
8539         idx = i40e_get_vxlan_port_idx(pf, port);
8540
8541         if (idx < 0) {
8542                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8543                 return -EINVAL;
8544         }
8545
8546         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8547                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8548                 return -1;
8549         }
8550
8551         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8552                         port, idx);
8553
8554         pf->vxlan_ports[idx] = 0;
8555         pf->vxlan_bitmap &= ~(1 << idx);
8556
8557         if (!pf->vxlan_bitmap)
8558                 pf->flags &= ~I40E_FLAG_VXLAN;
8559
8560         return 0;
8561 }
8562
8563 /* Add UDP tunneling port */
8564 static int
8565 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8566                              struct rte_eth_udp_tunnel *udp_tunnel)
8567 {
8568         int ret = 0;
8569         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8570
8571         if (udp_tunnel == NULL)
8572                 return -EINVAL;
8573
8574         switch (udp_tunnel->prot_type) {
8575         case RTE_TUNNEL_TYPE_VXLAN:
8576                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8577                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8578                 break;
8579         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8580                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8581                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8582                 break;
8583         case RTE_TUNNEL_TYPE_GENEVE:
8584         case RTE_TUNNEL_TYPE_TEREDO:
8585                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8586                 ret = -1;
8587                 break;
8588
8589         default:
8590                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8591                 ret = -1;
8592                 break;
8593         }
8594
8595         return ret;
8596 }
8597
8598 /* Remove UDP tunneling port */
8599 static int
8600 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8601                              struct rte_eth_udp_tunnel *udp_tunnel)
8602 {
8603         int ret = 0;
8604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8605
8606         if (udp_tunnel == NULL)
8607                 return -EINVAL;
8608
8609         switch (udp_tunnel->prot_type) {
8610         case RTE_TUNNEL_TYPE_VXLAN:
8611         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8612                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8613                 break;
8614         case RTE_TUNNEL_TYPE_GENEVE:
8615         case RTE_TUNNEL_TYPE_TEREDO:
8616                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8617                 ret = -1;
8618                 break;
8619         default:
8620                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8621                 ret = -1;
8622                 break;
8623         }
8624
8625         return ret;
8626 }
8627
8628 /* Calculate the maximum number of contiguous PF queues that are configured */
8629 static int
8630 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8631 {
8632         struct rte_eth_dev_data *data = pf->dev_data;
8633         int i, num;
8634         struct i40e_rx_queue *rxq;
8635
8636         num = 0;
8637         for (i = 0; i < pf->lan_nb_qps; i++) {
8638                 rxq = data->rx_queues[i];
8639                 if (rxq && rxq->q_set)
8640                         num++;
8641                 else
8642                         break;
8643         }
8644
8645         return num;
8646 }
8647
8648 /* Configure RSS */
8649 static int
8650 i40e_pf_config_rss(struct i40e_pf *pf)
8651 {
8652         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8653         struct rte_eth_rss_conf rss_conf;
8654         uint32_t i, lut = 0;
8655         uint16_t j, num;
8656
8657         /*
8658          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8659          * It's necessary to calculate the actual PF queues that are configured.
8660          */
8661         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8662                 num = i40e_pf_calc_configured_queues_num(pf);
8663         else
8664                 num = pf->dev_data->nb_rx_queues;
8665
8666         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8667         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8668                         num);
8669
8670         if (num == 0) {
8671                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8672                 return -ENOTSUP;
8673         }
8674
8675         if (pf->adapter->rss_reta_updated == 0) {
8676                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8677                         if (j == num)
8678                                 j = 0;
8679                         lut = (lut << 8) | (j & ((0x1 <<
8680                                 hw->func_caps.rss_table_entry_width) - 1));
8681                         if ((i & 3) == 3)
8682                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8683                                                rte_bswap32(lut));
8684                 }
8685         }
8686
8687         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8688         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8689                 i40e_pf_disable_rss(pf);
8690                 return 0;
8691         }
8692         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8693                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8694                 /* Random default keys */
8695                 static uint32_t rss_key_default[] = {0x6b793944,
8696                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8697                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8698                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8699
8700                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8701                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8702                                                         sizeof(uint32_t);
8703         }
8704
8705         return i40e_hw_rss_hash_set(pf, &rss_conf);
8706 }
8707
8708 static int
8709 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8710                                struct rte_eth_tunnel_filter_conf *filter)
8711 {
8712         if (pf == NULL || filter == NULL) {
8713                 PMD_DRV_LOG(ERR, "Invalid parameter");
8714                 return -EINVAL;
8715         }
8716
8717         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8718                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8719                 return -EINVAL;
8720         }
8721
8722         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8723                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8724                 return -EINVAL;
8725         }
8726
8727         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8728                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8729                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8730                 return -EINVAL;
8731         }
8732
8733         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8734                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8735                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8736                 return -EINVAL;
8737         }
8738
8739         return 0;
8740 }
8741
8742 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8743 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8744 static int
8745 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8746 {
8747         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8748         uint32_t val, reg;
8749         int ret = -EINVAL;
8750
8751         if (pf->support_multi_driver) {
8752                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8753                 return -ENOTSUP;
8754         }
8755
8756         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8757         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8758
8759         if (len == 3) {
8760                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8761         } else if (len == 4) {
8762                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8763         } else {
8764                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8765                 return ret;
8766         }
8767
8768         if (reg != val) {
8769                 ret = i40e_aq_debug_write_global_register(hw,
8770                                                    I40E_GL_PRS_FVBM(2),
8771                                                    reg, NULL);
8772                 if (ret != 0)
8773                         return ret;
8774                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8775                             "with value 0x%08x",
8776                             I40E_GL_PRS_FVBM(2), reg);
8777         } else {
8778                 ret = 0;
8779         }
8780         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8781                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8782
8783         return ret;
8784 }
8785
8786 static int
8787 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8788 {
8789         int ret = -EINVAL;
8790
8791         if (!hw || !cfg)
8792                 return -EINVAL;
8793
8794         switch (cfg->cfg_type) {
8795         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8796                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8797                 break;
8798         default:
8799                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8800                 break;
8801         }
8802
8803         return ret;
8804 }
8805
8806 static int
8807 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8808                                enum rte_filter_op filter_op,
8809                                void *arg)
8810 {
8811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8812         int ret = I40E_ERR_PARAM;
8813
8814         switch (filter_op) {
8815         case RTE_ETH_FILTER_SET:
8816                 ret = i40e_dev_global_config_set(hw,
8817                         (struct rte_eth_global_cfg *)arg);
8818                 break;
8819         default:
8820                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8821                 break;
8822         }
8823
8824         return ret;
8825 }
8826
8827 static int
8828 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8829                           enum rte_filter_op filter_op,
8830                           void *arg)
8831 {
8832         struct rte_eth_tunnel_filter_conf *filter;
8833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8834         int ret = I40E_SUCCESS;
8835
8836         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8837
8838         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8839                 return I40E_ERR_PARAM;
8840
8841         switch (filter_op) {
8842         case RTE_ETH_FILTER_NOP:
8843                 if (!(pf->flags & I40E_FLAG_VXLAN))
8844                         ret = I40E_NOT_SUPPORTED;
8845                 break;
8846         case RTE_ETH_FILTER_ADD:
8847                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8848                 break;
8849         case RTE_ETH_FILTER_DELETE:
8850                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8851                 break;
8852         default:
8853                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8854                 ret = I40E_ERR_PARAM;
8855                 break;
8856         }
8857
8858         return ret;
8859 }
8860
8861 static int
8862 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8863 {
8864         int ret = 0;
8865         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8866
8867         /* RSS setup */
8868         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8869                 ret = i40e_pf_config_rss(pf);
8870         else
8871                 i40e_pf_disable_rss(pf);
8872
8873         return ret;
8874 }
8875
8876 /* Get the symmetric hash enable configurations per port */
8877 static void
8878 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8879 {
8880         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8881
8882         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8883 }
8884
8885 /* Set the symmetric hash enable configurations per port */
8886 static void
8887 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8888 {
8889         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8890
8891         if (enable > 0) {
8892                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8893                         PMD_DRV_LOG(INFO,
8894                                 "Symmetric hash has already been enabled");
8895                         return;
8896                 }
8897                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8898         } else {
8899                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8900                         PMD_DRV_LOG(INFO,
8901                                 "Symmetric hash has already been disabled");
8902                         return;
8903                 }
8904                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8905         }
8906         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8907         I40E_WRITE_FLUSH(hw);
8908 }
8909
8910 /*
8911  * Get global configurations of hash function type and symmetric hash enable
8912  * per flow type (pctype). Note that global configuration means it affects all
8913  * the ports on the same NIC.
8914  */
8915 static int
8916 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8917                                    struct rte_eth_hash_global_conf *g_cfg)
8918 {
8919         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8920         uint32_t reg;
8921         uint16_t i, j;
8922
8923         memset(g_cfg, 0, sizeof(*g_cfg));
8924         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8925         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8926                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8927         else
8928                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8929         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8930                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8931
8932         /*
8933          * As i40e supports less than 64 flow types, only first 64 bits need to
8934          * be checked.
8935          */
8936         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8937                 g_cfg->valid_bit_mask[i] = 0ULL;
8938                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8939         }
8940
8941         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8942
8943         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8944                 if (!adapter->pctypes_tbl[i])
8945                         continue;
8946                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8947                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8948                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8949                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8950                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8951                                         g_cfg->sym_hash_enable_mask[0] |=
8952                                                                 (1ULL << i);
8953                                 }
8954                         }
8955                 }
8956         }
8957
8958         return 0;
8959 }
8960
8961 static int
8962 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8963                               const struct rte_eth_hash_global_conf *g_cfg)
8964 {
8965         uint32_t i;
8966         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8967
8968         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8969                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8970                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8971                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8972                                                 g_cfg->hash_func);
8973                 return -EINVAL;
8974         }
8975
8976         /*
8977          * As i40e supports less than 64 flow types, only first 64 bits need to
8978          * be checked.
8979          */
8980         mask0 = g_cfg->valid_bit_mask[0];
8981         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8982                 if (i == 0) {
8983                         /* Check if any unsupported flow type configured */
8984                         if ((mask0 | i40e_mask) ^ i40e_mask)
8985                                 goto mask_err;
8986                 } else {
8987                         if (g_cfg->valid_bit_mask[i])
8988                                 goto mask_err;
8989                 }
8990         }
8991
8992         return 0;
8993
8994 mask_err:
8995         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8996
8997         return -EINVAL;
8998 }
8999
9000 /*
9001  * Set global configurations of hash function type and symmetric hash enable
9002  * per flow type (pctype). Note any modifying global configuration will affect
9003  * all the ports on the same NIC.
9004  */
9005 static int
9006 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9007                                    struct rte_eth_hash_global_conf *g_cfg)
9008 {
9009         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9010         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9011         int ret;
9012         uint16_t i, j;
9013         uint32_t reg;
9014         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9015
9016         if (pf->support_multi_driver) {
9017                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9018                 return -ENOTSUP;
9019         }
9020
9021         /* Check the input parameters */
9022         ret = i40e_hash_global_config_check(adapter, g_cfg);
9023         if (ret < 0)
9024                 return ret;
9025
9026         /*
9027          * As i40e supports less than 64 flow types, only first 64 bits need to
9028          * be configured.
9029          */
9030         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9031                 if (mask0 & (1UL << i)) {
9032                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9033                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9034
9035                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9036                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9037                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9038                                         i40e_write_global_rx_ctl(hw,
9039                                                           I40E_GLQF_HSYM(j),
9040                                                           reg);
9041                         }
9042                 }
9043         }
9044
9045         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9046         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9047                 /* Toeplitz */
9048                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9049                         PMD_DRV_LOG(DEBUG,
9050                                 "Hash function already set to Toeplitz");
9051                         goto out;
9052                 }
9053                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9054         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9055                 /* Simple XOR */
9056                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9057                         PMD_DRV_LOG(DEBUG,
9058                                 "Hash function already set to Simple XOR");
9059                         goto out;
9060                 }
9061                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9062         } else
9063                 /* Use the default, and keep it as it is */
9064                 goto out;
9065
9066         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9067
9068 out:
9069         I40E_WRITE_FLUSH(hw);
9070
9071         return 0;
9072 }
9073
9074 /**
9075  * Valid input sets for hash and flow director filters per PCTYPE
9076  */
9077 static uint64_t
9078 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9079                 enum rte_filter_type filter)
9080 {
9081         uint64_t valid;
9082
9083         static const uint64_t valid_hash_inset_table[] = {
9084                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9085                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9086                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9087                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9088                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9089                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9090                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9091                         I40E_INSET_FLEX_PAYLOAD,
9092                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9093                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9094                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9095                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9096                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9097                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9098                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9099                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9100                         I40E_INSET_FLEX_PAYLOAD,
9101                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9102                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9103                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9104                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9105                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9106                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9107                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9108                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9109                         I40E_INSET_FLEX_PAYLOAD,
9110                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9111                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9112                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9113                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9114                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9115                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9116                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9117                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9118                         I40E_INSET_FLEX_PAYLOAD,
9119                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9120                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9121                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9122                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9123                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9124                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9125                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9126                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9127                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9128                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9129                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9130                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9132                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9133                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9134                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9135                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9136                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9137                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9138                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9139                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9141                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9142                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9143                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9144                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9145                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9146                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9147                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9148                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9150                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9151                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9152                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9153                         I40E_INSET_FLEX_PAYLOAD,
9154                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9155                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9156                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9157                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9158                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9159                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9160                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9161                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9162                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9166                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9167                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9168                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9169                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9170                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9171                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9172                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9173                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9174                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9175                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9176                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9177                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9178                         I40E_INSET_FLEX_PAYLOAD,
9179                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9180                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9181                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9182                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9183                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9184                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9185                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9186                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9187                         I40E_INSET_FLEX_PAYLOAD,
9188                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9189                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9190                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9192                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9193                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9194                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9195                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9196                         I40E_INSET_FLEX_PAYLOAD,
9197                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9198                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9199                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9201                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9202                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9203                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9204                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9205                         I40E_INSET_FLEX_PAYLOAD,
9206                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9207                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9208                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9209                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9210                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9211                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9212                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9213                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9214                         I40E_INSET_FLEX_PAYLOAD,
9215                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9216                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9217                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9219                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9220                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9221                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9222                         I40E_INSET_FLEX_PAYLOAD,
9223                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9224                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9225                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9226                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9227                         I40E_INSET_FLEX_PAYLOAD,
9228         };
9229
9230         /**
9231          * Flow director supports only fields defined in
9232          * union rte_eth_fdir_flow.
9233          */
9234         static const uint64_t valid_fdir_inset_table[] = {
9235                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9236                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9237                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9238                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9239                 I40E_INSET_IPV4_TTL,
9240                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9241                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9242                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9243                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9244                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9245                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9246                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9247                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9248                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9249                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9250                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9251                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9254                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9259                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9264                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9265                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9267                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9269                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9270                 I40E_INSET_SCTP_VT,
9271                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9275                 I40E_INSET_IPV4_TTL,
9276                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9279                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9280                 I40E_INSET_IPV6_HOP_LIMIT,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9283                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9284                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9286                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9287                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9288                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9290                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9291                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9292                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9293                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9295                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9297                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9300                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9302                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9304                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9305                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9306                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9308                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9309                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9310                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9311                 I40E_INSET_SCTP_VT,
9312                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9314                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9315                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9316                 I40E_INSET_IPV6_HOP_LIMIT,
9317                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9318                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9319                 I40E_INSET_LAST_ETHER_TYPE,
9320         };
9321
9322         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9323                 return 0;
9324         if (filter == RTE_ETH_FILTER_HASH)
9325                 valid = valid_hash_inset_table[pctype];
9326         else
9327                 valid = valid_fdir_inset_table[pctype];
9328
9329         return valid;
9330 }
9331
9332 /**
9333  * Validate if the input set is allowed for a specific PCTYPE
9334  */
9335 int
9336 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9337                 enum rte_filter_type filter, uint64_t inset)
9338 {
9339         uint64_t valid;
9340
9341         valid = i40e_get_valid_input_set(pctype, filter);
9342         if (inset & (~valid))
9343                 return -EINVAL;
9344
9345         return 0;
9346 }
9347
9348 /* default input set fields combination per pctype */
9349 uint64_t
9350 i40e_get_default_input_set(uint16_t pctype)
9351 {
9352         static const uint64_t default_inset_table[] = {
9353                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9354                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9355                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9356                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9357                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9358                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9359                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9360                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9361                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9362                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9363                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9364                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9365                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9366                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9367                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9368                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9369                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9370                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9371                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9372                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9373                         I40E_INSET_SCTP_VT,
9374                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9375                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9376                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9377                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9378                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9379                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9380                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9381                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9382                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9384                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9385                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9386                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9387                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9388                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9390                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9391                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9392                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9393                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9394                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9395                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9396                         I40E_INSET_SCTP_VT,
9397                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9398                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9399                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9400                         I40E_INSET_LAST_ETHER_TYPE,
9401         };
9402
9403         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9404                 return 0;
9405
9406         return default_inset_table[pctype];
9407 }
9408
9409 /**
9410  * Parse the input set from index to logical bit masks
9411  */
9412 static int
9413 i40e_parse_input_set(uint64_t *inset,
9414                      enum i40e_filter_pctype pctype,
9415                      enum rte_eth_input_set_field *field,
9416                      uint16_t size)
9417 {
9418         uint16_t i, j;
9419         int ret = -EINVAL;
9420
9421         static const struct {
9422                 enum rte_eth_input_set_field field;
9423                 uint64_t inset;
9424         } inset_convert_table[] = {
9425                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9426                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9427                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9428                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9429                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9430                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9431                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9432                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9433                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9434                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9435                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9436                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9437                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9438                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9439                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9440                         I40E_INSET_IPV6_NEXT_HDR},
9441                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9442                         I40E_INSET_IPV6_HOP_LIMIT},
9443                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9444                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9445                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9446                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9447                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9448                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9449                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9450                         I40E_INSET_SCTP_VT},
9451                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9452                         I40E_INSET_TUNNEL_DMAC},
9453                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9454                         I40E_INSET_VLAN_TUNNEL},
9455                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9456                         I40E_INSET_TUNNEL_ID},
9457                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9458                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9459                         I40E_INSET_FLEX_PAYLOAD_W1},
9460                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9461                         I40E_INSET_FLEX_PAYLOAD_W2},
9462                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9463                         I40E_INSET_FLEX_PAYLOAD_W3},
9464                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9465                         I40E_INSET_FLEX_PAYLOAD_W4},
9466                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9467                         I40E_INSET_FLEX_PAYLOAD_W5},
9468                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9469                         I40E_INSET_FLEX_PAYLOAD_W6},
9470                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9471                         I40E_INSET_FLEX_PAYLOAD_W7},
9472                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9473                         I40E_INSET_FLEX_PAYLOAD_W8},
9474         };
9475
9476         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9477                 return ret;
9478
9479         /* Only one item allowed for default or all */
9480         if (size == 1) {
9481                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9482                         *inset = i40e_get_default_input_set(pctype);
9483                         return 0;
9484                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9485                         *inset = I40E_INSET_NONE;
9486                         return 0;
9487                 }
9488         }
9489
9490         for (i = 0, *inset = 0; i < size; i++) {
9491                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9492                         if (field[i] == inset_convert_table[j].field) {
9493                                 *inset |= inset_convert_table[j].inset;
9494                                 break;
9495                         }
9496                 }
9497
9498                 /* It contains unsupported input set, return immediately */
9499                 if (j == RTE_DIM(inset_convert_table))
9500                         return ret;
9501         }
9502
9503         return 0;
9504 }
9505
9506 /**
9507  * Translate the input set from bit masks to register aware bit masks
9508  * and vice versa
9509  */
9510 uint64_t
9511 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9512 {
9513         uint64_t val = 0;
9514         uint16_t i;
9515
9516         struct inset_map {
9517                 uint64_t inset;
9518                 uint64_t inset_reg;
9519         };
9520
9521         static const struct inset_map inset_map_common[] = {
9522                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9523                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9524                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9525                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9526                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9527                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9528                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9529                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9530                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9531                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9532                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9533                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9534                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9535                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9536                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9537                 {I40E_INSET_TUNNEL_DMAC,
9538                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9539                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9540                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9541                 {I40E_INSET_TUNNEL_SRC_PORT,
9542                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9543                 {I40E_INSET_TUNNEL_DST_PORT,
9544                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9545                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9546                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9547                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9548                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9549                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9550                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9551                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9552                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9553                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9554         };
9555
9556     /* some different registers map in x722*/
9557         static const struct inset_map inset_map_diff_x722[] = {
9558                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9559                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9560                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9561                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9562         };
9563
9564         static const struct inset_map inset_map_diff_not_x722[] = {
9565                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9566                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9567                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9568                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9569         };
9570
9571         if (input == 0)
9572                 return val;
9573
9574         /* Translate input set to register aware inset */
9575         if (type == I40E_MAC_X722) {
9576                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9577                         if (input & inset_map_diff_x722[i].inset)
9578                                 val |= inset_map_diff_x722[i].inset_reg;
9579                 }
9580         } else {
9581                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9582                         if (input & inset_map_diff_not_x722[i].inset)
9583                                 val |= inset_map_diff_not_x722[i].inset_reg;
9584                 }
9585         }
9586
9587         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9588                 if (input & inset_map_common[i].inset)
9589                         val |= inset_map_common[i].inset_reg;
9590         }
9591
9592         return val;
9593 }
9594
9595 int
9596 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9597 {
9598         uint8_t i, idx = 0;
9599         uint64_t inset_need_mask = inset;
9600
9601         static const struct {
9602                 uint64_t inset;
9603                 uint32_t mask;
9604         } inset_mask_map[] = {
9605                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9606                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9607                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9608                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9609                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9610                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9611                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9612                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9613         };
9614
9615         if (!inset || !mask || !nb_elem)
9616                 return 0;
9617
9618         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9619                 /* Clear the inset bit, if no MASK is required,
9620                  * for example proto + ttl
9621                  */
9622                 if ((inset & inset_mask_map[i].inset) ==
9623                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9624                         inset_need_mask &= ~inset_mask_map[i].inset;
9625                 if (!inset_need_mask)
9626                         return 0;
9627         }
9628         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9629                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9630                     inset_mask_map[i].inset) {
9631                         if (idx >= nb_elem) {
9632                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9633                                 return -EINVAL;
9634                         }
9635                         mask[idx] = inset_mask_map[i].mask;
9636                         idx++;
9637                 }
9638         }
9639
9640         return idx;
9641 }
9642
9643 void
9644 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9645 {
9646         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9647
9648         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9649         if (reg != val)
9650                 i40e_write_rx_ctl(hw, addr, val);
9651         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9652                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9653 }
9654
9655 void
9656 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9657 {
9658         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9659         struct rte_eth_dev *dev;
9660
9661         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9662         if (reg != val) {
9663                 i40e_write_rx_ctl(hw, addr, val);
9664                 PMD_DRV_LOG(WARNING,
9665                             "i40e device %s changed global register [0x%08x]."
9666                             " original: 0x%08x, new: 0x%08x",
9667                             dev->device->name, addr, reg,
9668                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9669         }
9670 }
9671
9672 static void
9673 i40e_filter_input_set_init(struct i40e_pf *pf)
9674 {
9675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9676         enum i40e_filter_pctype pctype;
9677         uint64_t input_set, inset_reg;
9678         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9679         int num, i;
9680         uint16_t flow_type;
9681
9682         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9683              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9684                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9685
9686                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9687                         continue;
9688
9689                 input_set = i40e_get_default_input_set(pctype);
9690
9691                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9692                                                    I40E_INSET_MASK_NUM_REG);
9693                 if (num < 0)
9694                         return;
9695                 if (pf->support_multi_driver && num > 0) {
9696                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9697                         return;
9698                 }
9699                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9700                                         input_set);
9701
9702                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9703                                       (uint32_t)(inset_reg & UINT32_MAX));
9704                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9705                                      (uint32_t)((inset_reg >>
9706                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9707                 if (!pf->support_multi_driver) {
9708                         i40e_check_write_global_reg(hw,
9709                                             I40E_GLQF_HASH_INSET(0, pctype),
9710                                             (uint32_t)(inset_reg & UINT32_MAX));
9711                         i40e_check_write_global_reg(hw,
9712                                              I40E_GLQF_HASH_INSET(1, pctype),
9713                                              (uint32_t)((inset_reg >>
9714                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9715
9716                         for (i = 0; i < num; i++) {
9717                                 i40e_check_write_global_reg(hw,
9718                                                     I40E_GLQF_FD_MSK(i, pctype),
9719                                                     mask_reg[i]);
9720                                 i40e_check_write_global_reg(hw,
9721                                                   I40E_GLQF_HASH_MSK(i, pctype),
9722                                                   mask_reg[i]);
9723                         }
9724                         /*clear unused mask registers of the pctype */
9725                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9726                                 i40e_check_write_global_reg(hw,
9727                                                     I40E_GLQF_FD_MSK(i, pctype),
9728                                                     0);
9729                                 i40e_check_write_global_reg(hw,
9730                                                   I40E_GLQF_HASH_MSK(i, pctype),
9731                                                   0);
9732                         }
9733                 } else {
9734                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9735                 }
9736                 I40E_WRITE_FLUSH(hw);
9737
9738                 /* store the default input set */
9739                 if (!pf->support_multi_driver)
9740                         pf->hash_input_set[pctype] = input_set;
9741                 pf->fdir.input_set[pctype] = input_set;
9742         }
9743 }
9744
9745 int
9746 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9747                          struct rte_eth_input_set_conf *conf)
9748 {
9749         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9750         enum i40e_filter_pctype pctype;
9751         uint64_t input_set, inset_reg = 0;
9752         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9753         int ret, i, num;
9754
9755         if (!conf) {
9756                 PMD_DRV_LOG(ERR, "Invalid pointer");
9757                 return -EFAULT;
9758         }
9759         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9760             conf->op != RTE_ETH_INPUT_SET_ADD) {
9761                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9762                 return -EINVAL;
9763         }
9764
9765         if (pf->support_multi_driver) {
9766                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9767                 return -ENOTSUP;
9768         }
9769
9770         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9771         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9772                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9773                 return -EINVAL;
9774         }
9775
9776         if (hw->mac.type == I40E_MAC_X722) {
9777                 /* get translated pctype value in fd pctype register */
9778                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9779                         I40E_GLQF_FD_PCTYPES((int)pctype));
9780         }
9781
9782         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9783                                    conf->inset_size);
9784         if (ret) {
9785                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9786                 return -EINVAL;
9787         }
9788
9789         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9790                 /* get inset value in register */
9791                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9792                 inset_reg <<= I40E_32_BIT_WIDTH;
9793                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9794                 input_set |= pf->hash_input_set[pctype];
9795         }
9796         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9797                                            I40E_INSET_MASK_NUM_REG);
9798         if (num < 0)
9799                 return -EINVAL;
9800
9801         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9802
9803         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9804                                     (uint32_t)(inset_reg & UINT32_MAX));
9805         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9806                                     (uint32_t)((inset_reg >>
9807                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9808
9809         for (i = 0; i < num; i++)
9810                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9811                                             mask_reg[i]);
9812         /*clear unused mask registers of the pctype */
9813         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9814                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9815                                             0);
9816         I40E_WRITE_FLUSH(hw);
9817
9818         pf->hash_input_set[pctype] = input_set;
9819         return 0;
9820 }
9821
9822 int
9823 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9824                          struct rte_eth_input_set_conf *conf)
9825 {
9826         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9827         enum i40e_filter_pctype pctype;
9828         uint64_t input_set, inset_reg = 0;
9829         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9830         int ret, i, num;
9831
9832         if (!hw || !conf) {
9833                 PMD_DRV_LOG(ERR, "Invalid pointer");
9834                 return -EFAULT;
9835         }
9836         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9837             conf->op != RTE_ETH_INPUT_SET_ADD) {
9838                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9839                 return -EINVAL;
9840         }
9841
9842         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9843
9844         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9845                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9846                 return -EINVAL;
9847         }
9848
9849         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9850                                    conf->inset_size);
9851         if (ret) {
9852                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9853                 return -EINVAL;
9854         }
9855
9856         /* get inset value in register */
9857         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9858         inset_reg <<= I40E_32_BIT_WIDTH;
9859         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9860
9861         /* Can not change the inset reg for flex payload for fdir,
9862          * it is done by writing I40E_PRTQF_FD_FLXINSET
9863          * in i40e_set_flex_mask_on_pctype.
9864          */
9865         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9866                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9867         else
9868                 input_set |= pf->fdir.input_set[pctype];
9869         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9870                                            I40E_INSET_MASK_NUM_REG);
9871         if (num < 0)
9872                 return -EINVAL;
9873         if (pf->support_multi_driver && num > 0) {
9874                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9875                 return -ENOTSUP;
9876         }
9877
9878         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9879
9880         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9881                               (uint32_t)(inset_reg & UINT32_MAX));
9882         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9883                              (uint32_t)((inset_reg >>
9884                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9885
9886         if (!pf->support_multi_driver) {
9887                 for (i = 0; i < num; i++)
9888                         i40e_check_write_global_reg(hw,
9889                                                     I40E_GLQF_FD_MSK(i, pctype),
9890                                                     mask_reg[i]);
9891                 /*clear unused mask registers of the pctype */
9892                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9893                         i40e_check_write_global_reg(hw,
9894                                                     I40E_GLQF_FD_MSK(i, pctype),
9895                                                     0);
9896         } else {
9897                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9898         }
9899         I40E_WRITE_FLUSH(hw);
9900
9901         pf->fdir.input_set[pctype] = input_set;
9902         return 0;
9903 }
9904
9905 static int
9906 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9907 {
9908         int ret = 0;
9909
9910         if (!hw || !info) {
9911                 PMD_DRV_LOG(ERR, "Invalid pointer");
9912                 return -EFAULT;
9913         }
9914
9915         switch (info->info_type) {
9916         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9917                 i40e_get_symmetric_hash_enable_per_port(hw,
9918                                         &(info->info.enable));
9919                 break;
9920         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9921                 ret = i40e_get_hash_filter_global_config(hw,
9922                                 &(info->info.global_conf));
9923                 break;
9924         default:
9925                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9926                                                         info->info_type);
9927                 ret = -EINVAL;
9928                 break;
9929         }
9930
9931         return ret;
9932 }
9933
9934 static int
9935 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9936 {
9937         int ret = 0;
9938
9939         if (!hw || !info) {
9940                 PMD_DRV_LOG(ERR, "Invalid pointer");
9941                 return -EFAULT;
9942         }
9943
9944         switch (info->info_type) {
9945         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9946                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9947                 break;
9948         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9949                 ret = i40e_set_hash_filter_global_config(hw,
9950                                 &(info->info.global_conf));
9951                 break;
9952         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9953                 ret = i40e_hash_filter_inset_select(hw,
9954                                                &(info->info.input_set_conf));
9955                 break;
9956
9957         default:
9958                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9959                                                         info->info_type);
9960                 ret = -EINVAL;
9961                 break;
9962         }
9963
9964         return ret;
9965 }
9966
9967 /* Operations for hash function */
9968 static int
9969 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9970                       enum rte_filter_op filter_op,
9971                       void *arg)
9972 {
9973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9974         int ret = 0;
9975
9976         switch (filter_op) {
9977         case RTE_ETH_FILTER_NOP:
9978                 break;
9979         case RTE_ETH_FILTER_GET:
9980                 ret = i40e_hash_filter_get(hw,
9981                         (struct rte_eth_hash_filter_info *)arg);
9982                 break;
9983         case RTE_ETH_FILTER_SET:
9984                 ret = i40e_hash_filter_set(hw,
9985                         (struct rte_eth_hash_filter_info *)arg);
9986                 break;
9987         default:
9988                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9989                                                                 filter_op);
9990                 ret = -ENOTSUP;
9991                 break;
9992         }
9993
9994         return ret;
9995 }
9996
9997 /* Convert ethertype filter structure */
9998 static int
9999 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10000                               struct i40e_ethertype_filter *filter)
10001 {
10002         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10003                 RTE_ETHER_ADDR_LEN);
10004         filter->input.ether_type = input->ether_type;
10005         filter->flags = input->flags;
10006         filter->queue = input->queue;
10007
10008         return 0;
10009 }
10010
10011 /* Check if there exists the ehtertype filter */
10012 struct i40e_ethertype_filter *
10013 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10014                                 const struct i40e_ethertype_filter_input *input)
10015 {
10016         int ret;
10017
10018         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10019         if (ret < 0)
10020                 return NULL;
10021
10022         return ethertype_rule->hash_map[ret];
10023 }
10024
10025 /* Add ethertype filter in SW list */
10026 static int
10027 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10028                                 struct i40e_ethertype_filter *filter)
10029 {
10030         struct i40e_ethertype_rule *rule = &pf->ethertype;
10031         int ret;
10032
10033         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10034         if (ret < 0) {
10035                 PMD_DRV_LOG(ERR,
10036                             "Failed to insert ethertype filter"
10037                             " to hash table %d!",
10038                             ret);
10039                 return ret;
10040         }
10041         rule->hash_map[ret] = filter;
10042
10043         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10044
10045         return 0;
10046 }
10047
10048 /* Delete ethertype filter in SW list */
10049 int
10050 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10051                              struct i40e_ethertype_filter_input *input)
10052 {
10053         struct i40e_ethertype_rule *rule = &pf->ethertype;
10054         struct i40e_ethertype_filter *filter;
10055         int ret;
10056
10057         ret = rte_hash_del_key(rule->hash_table, input);
10058         if (ret < 0) {
10059                 PMD_DRV_LOG(ERR,
10060                             "Failed to delete ethertype filter"
10061                             " to hash table %d!",
10062                             ret);
10063                 return ret;
10064         }
10065         filter = rule->hash_map[ret];
10066         rule->hash_map[ret] = NULL;
10067
10068         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10069         rte_free(filter);
10070
10071         return 0;
10072 }
10073
10074 /*
10075  * Configure ethertype filter, which can director packet by filtering
10076  * with mac address and ether_type or only ether_type
10077  */
10078 int
10079 i40e_ethertype_filter_set(struct i40e_pf *pf,
10080                         struct rte_eth_ethertype_filter *filter,
10081                         bool add)
10082 {
10083         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10084         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10085         struct i40e_ethertype_filter *ethertype_filter, *node;
10086         struct i40e_ethertype_filter check_filter;
10087         struct i40e_control_filter_stats stats;
10088         uint16_t flags = 0;
10089         int ret;
10090
10091         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10092                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10093                 return -EINVAL;
10094         }
10095         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10096                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10097                 PMD_DRV_LOG(ERR,
10098                         "unsupported ether_type(0x%04x) in control packet filter.",
10099                         filter->ether_type);
10100                 return -EINVAL;
10101         }
10102         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10103                 PMD_DRV_LOG(WARNING,
10104                         "filter vlan ether_type in first tag is not supported.");
10105
10106         /* Check if there is the filter in SW list */
10107         memset(&check_filter, 0, sizeof(check_filter));
10108         i40e_ethertype_filter_convert(filter, &check_filter);
10109         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10110                                                &check_filter.input);
10111         if (add && node) {
10112                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10113                 return -EINVAL;
10114         }
10115
10116         if (!add && !node) {
10117                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10118                 return -EINVAL;
10119         }
10120
10121         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10122                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10123         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10124                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10125         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10126
10127         memset(&stats, 0, sizeof(stats));
10128         ret = i40e_aq_add_rem_control_packet_filter(hw,
10129                         filter->mac_addr.addr_bytes,
10130                         filter->ether_type, flags,
10131                         pf->main_vsi->seid,
10132                         filter->queue, add, &stats, NULL);
10133
10134         PMD_DRV_LOG(INFO,
10135                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10136                 ret, stats.mac_etype_used, stats.etype_used,
10137                 stats.mac_etype_free, stats.etype_free);
10138         if (ret < 0)
10139                 return -ENOSYS;
10140
10141         /* Add or delete a filter in SW list */
10142         if (add) {
10143                 ethertype_filter = rte_zmalloc("ethertype_filter",
10144                                        sizeof(*ethertype_filter), 0);
10145                 if (ethertype_filter == NULL) {
10146                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10147                         return -ENOMEM;
10148                 }
10149
10150                 rte_memcpy(ethertype_filter, &check_filter,
10151                            sizeof(check_filter));
10152                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10153                 if (ret < 0)
10154                         rte_free(ethertype_filter);
10155         } else {
10156                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10157         }
10158
10159         return ret;
10160 }
10161
10162 /*
10163  * Handle operations for ethertype filter.
10164  */
10165 static int
10166 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10167                                 enum rte_filter_op filter_op,
10168                                 void *arg)
10169 {
10170         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10171         int ret = 0;
10172
10173         if (filter_op == RTE_ETH_FILTER_NOP)
10174                 return ret;
10175
10176         if (arg == NULL) {
10177                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10178                             filter_op);
10179                 return -EINVAL;
10180         }
10181
10182         switch (filter_op) {
10183         case RTE_ETH_FILTER_ADD:
10184                 ret = i40e_ethertype_filter_set(pf,
10185                         (struct rte_eth_ethertype_filter *)arg,
10186                         TRUE);
10187                 break;
10188         case RTE_ETH_FILTER_DELETE:
10189                 ret = i40e_ethertype_filter_set(pf,
10190                         (struct rte_eth_ethertype_filter *)arg,
10191                         FALSE);
10192                 break;
10193         default:
10194                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10195                 ret = -ENOSYS;
10196                 break;
10197         }
10198         return ret;
10199 }
10200
10201 static int
10202 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10203                      enum rte_filter_type filter_type,
10204                      enum rte_filter_op filter_op,
10205                      void *arg)
10206 {
10207         int ret = 0;
10208
10209         if (dev == NULL)
10210                 return -EINVAL;
10211
10212         switch (filter_type) {
10213         case RTE_ETH_FILTER_NONE:
10214                 /* For global configuration */
10215                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10216                 break;
10217         case RTE_ETH_FILTER_HASH:
10218                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10219                 break;
10220         case RTE_ETH_FILTER_MACVLAN:
10221                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10222                 break;
10223         case RTE_ETH_FILTER_ETHERTYPE:
10224                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10225                 break;
10226         case RTE_ETH_FILTER_TUNNEL:
10227                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10228                 break;
10229         case RTE_ETH_FILTER_FDIR:
10230                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10231                 break;
10232         case RTE_ETH_FILTER_GENERIC:
10233                 if (filter_op != RTE_ETH_FILTER_GET)
10234                         return -EINVAL;
10235                 *(const void **)arg = &i40e_flow_ops;
10236                 break;
10237         default:
10238                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10239                                                         filter_type);
10240                 ret = -EINVAL;
10241                 break;
10242         }
10243
10244         return ret;
10245 }
10246
10247 /*
10248  * Check and enable Extended Tag.
10249  * Enabling Extended Tag is important for 40G performance.
10250  */
10251 static void
10252 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10253 {
10254         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10255         uint32_t buf = 0;
10256         int ret;
10257
10258         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10259                                       PCI_DEV_CAP_REG);
10260         if (ret < 0) {
10261                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10262                             PCI_DEV_CAP_REG);
10263                 return;
10264         }
10265         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10266                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10267                 return;
10268         }
10269
10270         buf = 0;
10271         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10272                                       PCI_DEV_CTRL_REG);
10273         if (ret < 0) {
10274                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10275                             PCI_DEV_CTRL_REG);
10276                 return;
10277         }
10278         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10279                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10280                 return;
10281         }
10282         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10283         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10284                                        PCI_DEV_CTRL_REG);
10285         if (ret < 0) {
10286                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10287                             PCI_DEV_CTRL_REG);
10288                 return;
10289         }
10290 }
10291
10292 /*
10293  * As some registers wouldn't be reset unless a global hardware reset,
10294  * hardware initialization is needed to put those registers into an
10295  * expected initial state.
10296  */
10297 static void
10298 i40e_hw_init(struct rte_eth_dev *dev)
10299 {
10300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10301
10302         i40e_enable_extended_tag(dev);
10303
10304         /* clear the PF Queue Filter control register */
10305         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10306
10307         /* Disable symmetric hash per port */
10308         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10309 }
10310
10311 /*
10312  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10313  * however this function will return only one highest pctype index,
10314  * which is not quite correct. This is known problem of i40e driver
10315  * and needs to be fixed later.
10316  */
10317 enum i40e_filter_pctype
10318 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10319 {
10320         int i;
10321         uint64_t pctype_mask;
10322
10323         if (flow_type < I40E_FLOW_TYPE_MAX) {
10324                 pctype_mask = adapter->pctypes_tbl[flow_type];
10325                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10326                         if (pctype_mask & (1ULL << i))
10327                                 return (enum i40e_filter_pctype)i;
10328                 }
10329         }
10330         return I40E_FILTER_PCTYPE_INVALID;
10331 }
10332
10333 uint16_t
10334 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10335                         enum i40e_filter_pctype pctype)
10336 {
10337         uint16_t flowtype;
10338         uint64_t pctype_mask = 1ULL << pctype;
10339
10340         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10341              flowtype++) {
10342                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10343                         return flowtype;
10344         }
10345
10346         return RTE_ETH_FLOW_UNKNOWN;
10347 }
10348
10349 /*
10350  * On X710, performance number is far from the expectation on recent firmware
10351  * versions; on XL710, performance number is also far from the expectation on
10352  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10353  * mode is enabled and port MAC address is equal to the packet destination MAC
10354  * address. The fix for this issue may not be integrated in the following
10355  * firmware version. So the workaround in software driver is needed. It needs
10356  * to modify the initial values of 3 internal only registers for both X710 and
10357  * XL710. Note that the values for X710 or XL710 could be different, and the
10358  * workaround can be removed when it is fixed in firmware in the future.
10359  */
10360
10361 /* For both X710 and XL710 */
10362 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10363 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10364 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10365
10366 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10367 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10368
10369 /* For X722 */
10370 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10371 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10372
10373 /* For X710 */
10374 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10375 /* For XL710 */
10376 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10377 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10378
10379 /*
10380  * GL_SWR_PM_UP_THR:
10381  * The value is not impacted from the link speed, its value is set according
10382  * to the total number of ports for a better pipe-monitor configuration.
10383  */
10384 static bool
10385 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10386 {
10387 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10388                 .device_id = (dev),   \
10389                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10390
10391 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10392                 .device_id = (dev),   \
10393                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10394
10395         static const struct {
10396                 uint16_t device_id;
10397                 uint32_t val;
10398         } swr_pm_table[] = {
10399                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10400                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10401                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10402                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10403
10404                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10405                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10406                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10407                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10408                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10409                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10410                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10411         };
10412         uint32_t i;
10413
10414         if (value == NULL) {
10415                 PMD_DRV_LOG(ERR, "value is NULL");
10416                 return false;
10417         }
10418
10419         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10420                 if (hw->device_id == swr_pm_table[i].device_id) {
10421                         *value = swr_pm_table[i].val;
10422
10423                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10424                                     "value - 0x%08x",
10425                                     hw->device_id, *value);
10426                         return true;
10427                 }
10428         }
10429
10430         return false;
10431 }
10432
10433 static int
10434 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10435 {
10436         enum i40e_status_code status;
10437         struct i40e_aq_get_phy_abilities_resp phy_ab;
10438         int ret = -ENOTSUP;
10439         int retries = 0;
10440
10441         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10442                                               NULL);
10443
10444         while (status) {
10445                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10446                         status);
10447                 retries++;
10448                 rte_delay_us(100000);
10449                 if  (retries < 5)
10450                         status = i40e_aq_get_phy_capabilities(hw, false,
10451                                         true, &phy_ab, NULL);
10452                 else
10453                         return ret;
10454         }
10455         return 0;
10456 }
10457
10458 static void
10459 i40e_configure_registers(struct i40e_hw *hw)
10460 {
10461         static struct {
10462                 uint32_t addr;
10463                 uint64_t val;
10464         } reg_table[] = {
10465                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10466                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10467                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10468         };
10469         uint64_t reg;
10470         uint32_t i;
10471         int ret;
10472
10473         for (i = 0; i < RTE_DIM(reg_table); i++) {
10474                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10475                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10476                                 reg_table[i].val =
10477                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10478                         else /* For X710/XL710/XXV710 */
10479                                 if (hw->aq.fw_maj_ver < 6)
10480                                         reg_table[i].val =
10481                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10482                                 else
10483                                         reg_table[i].val =
10484                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10485                 }
10486
10487                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10488                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10489                                 reg_table[i].val =
10490                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10491                         else /* For X710/XL710/XXV710 */
10492                                 reg_table[i].val =
10493                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10494                 }
10495
10496                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10497                         uint32_t cfg_val;
10498
10499                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10500                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10501                                             "GL_SWR_PM_UP_THR value fixup",
10502                                             hw->device_id);
10503                                 continue;
10504                         }
10505
10506                         reg_table[i].val = cfg_val;
10507                 }
10508
10509                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10510                                                         &reg, NULL);
10511                 if (ret < 0) {
10512                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10513                                                         reg_table[i].addr);
10514                         break;
10515                 }
10516                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10517                                                 reg_table[i].addr, reg);
10518                 if (reg == reg_table[i].val)
10519                         continue;
10520
10521                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10522                                                 reg_table[i].val, NULL);
10523                 if (ret < 0) {
10524                         PMD_DRV_LOG(ERR,
10525                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10526                                 reg_table[i].val, reg_table[i].addr);
10527                         break;
10528                 }
10529                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10530                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10531         }
10532 }
10533
10534 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10535 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10536 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10537 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10538 static int
10539 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10540 {
10541         uint32_t reg;
10542         int ret;
10543
10544         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10545                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10546                 return -EINVAL;
10547         }
10548
10549         /* Configure for double VLAN RX stripping */
10550         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10551         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10552                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10553                 ret = i40e_aq_debug_write_register(hw,
10554                                                    I40E_VSI_TSR(vsi->vsi_id),
10555                                                    reg, NULL);
10556                 if (ret < 0) {
10557                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10558                                     vsi->vsi_id);
10559                         return I40E_ERR_CONFIG;
10560                 }
10561         }
10562
10563         /* Configure for double VLAN TX insertion */
10564         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10565         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10566                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10567                 ret = i40e_aq_debug_write_register(hw,
10568                                                    I40E_VSI_L2TAGSTXVALID(
10569                                                    vsi->vsi_id), reg, NULL);
10570                 if (ret < 0) {
10571                         PMD_DRV_LOG(ERR,
10572                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10573                                 vsi->vsi_id);
10574                         return I40E_ERR_CONFIG;
10575                 }
10576         }
10577
10578         return 0;
10579 }
10580
10581 /**
10582  * i40e_aq_add_mirror_rule
10583  * @hw: pointer to the hardware structure
10584  * @seid: VEB seid to add mirror rule to
10585  * @dst_id: destination vsi seid
10586  * @entries: Buffer which contains the entities to be mirrored
10587  * @count: number of entities contained in the buffer
10588  * @rule_id:the rule_id of the rule to be added
10589  *
10590  * Add a mirror rule for a given veb.
10591  *
10592  **/
10593 static enum i40e_status_code
10594 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10595                         uint16_t seid, uint16_t dst_id,
10596                         uint16_t rule_type, uint16_t *entries,
10597                         uint16_t count, uint16_t *rule_id)
10598 {
10599         struct i40e_aq_desc desc;
10600         struct i40e_aqc_add_delete_mirror_rule cmd;
10601         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10602                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10603                 &desc.params.raw;
10604         uint16_t buff_len;
10605         enum i40e_status_code status;
10606
10607         i40e_fill_default_direct_cmd_desc(&desc,
10608                                           i40e_aqc_opc_add_mirror_rule);
10609         memset(&cmd, 0, sizeof(cmd));
10610
10611         buff_len = sizeof(uint16_t) * count;
10612         desc.datalen = rte_cpu_to_le_16(buff_len);
10613         if (buff_len > 0)
10614                 desc.flags |= rte_cpu_to_le_16(
10615                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10616         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10617                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10618         cmd.num_entries = rte_cpu_to_le_16(count);
10619         cmd.seid = rte_cpu_to_le_16(seid);
10620         cmd.destination = rte_cpu_to_le_16(dst_id);
10621
10622         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10623         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10624         PMD_DRV_LOG(INFO,
10625                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10626                 hw->aq.asq_last_status, resp->rule_id,
10627                 resp->mirror_rules_used, resp->mirror_rules_free);
10628         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10629
10630         return status;
10631 }
10632
10633 /**
10634  * i40e_aq_del_mirror_rule
10635  * @hw: pointer to the hardware structure
10636  * @seid: VEB seid to add mirror rule to
10637  * @entries: Buffer which contains the entities to be mirrored
10638  * @count: number of entities contained in the buffer
10639  * @rule_id:the rule_id of the rule to be delete
10640  *
10641  * Delete a mirror rule for a given veb.
10642  *
10643  **/
10644 static enum i40e_status_code
10645 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10646                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10647                 uint16_t count, uint16_t rule_id)
10648 {
10649         struct i40e_aq_desc desc;
10650         struct i40e_aqc_add_delete_mirror_rule cmd;
10651         uint16_t buff_len = 0;
10652         enum i40e_status_code status;
10653         void *buff = NULL;
10654
10655         i40e_fill_default_direct_cmd_desc(&desc,
10656                                           i40e_aqc_opc_delete_mirror_rule);
10657         memset(&cmd, 0, sizeof(cmd));
10658         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10659                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10660                                                           I40E_AQ_FLAG_RD));
10661                 cmd.num_entries = count;
10662                 buff_len = sizeof(uint16_t) * count;
10663                 desc.datalen = rte_cpu_to_le_16(buff_len);
10664                 buff = (void *)entries;
10665         } else
10666                 /* rule id is filled in destination field for deleting mirror rule */
10667                 cmd.destination = rte_cpu_to_le_16(rule_id);
10668
10669         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10670                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10671         cmd.seid = rte_cpu_to_le_16(seid);
10672
10673         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10674         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10675
10676         return status;
10677 }
10678
10679 /**
10680  * i40e_mirror_rule_set
10681  * @dev: pointer to the hardware structure
10682  * @mirror_conf: mirror rule info
10683  * @sw_id: mirror rule's sw_id
10684  * @on: enable/disable
10685  *
10686  * set a mirror rule.
10687  *
10688  **/
10689 static int
10690 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10691                         struct rte_eth_mirror_conf *mirror_conf,
10692                         uint8_t sw_id, uint8_t on)
10693 {
10694         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10696         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10697         struct i40e_mirror_rule *parent = NULL;
10698         uint16_t seid, dst_seid, rule_id;
10699         uint16_t i, j = 0;
10700         int ret;
10701
10702         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10703
10704         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10705                 PMD_DRV_LOG(ERR,
10706                         "mirror rule can not be configured without veb or vfs.");
10707                 return -ENOSYS;
10708         }
10709         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10710                 PMD_DRV_LOG(ERR, "mirror table is full.");
10711                 return -ENOSPC;
10712         }
10713         if (mirror_conf->dst_pool > pf->vf_num) {
10714                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10715                                  mirror_conf->dst_pool);
10716                 return -EINVAL;
10717         }
10718
10719         seid = pf->main_vsi->veb->seid;
10720
10721         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10722                 if (sw_id <= it->index) {
10723                         mirr_rule = it;
10724                         break;
10725                 }
10726                 parent = it;
10727         }
10728         if (mirr_rule && sw_id == mirr_rule->index) {
10729                 if (on) {
10730                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10731                         return -EEXIST;
10732                 } else {
10733                         ret = i40e_aq_del_mirror_rule(hw, seid,
10734                                         mirr_rule->rule_type,
10735                                         mirr_rule->entries,
10736                                         mirr_rule->num_entries, mirr_rule->id);
10737                         if (ret < 0) {
10738                                 PMD_DRV_LOG(ERR,
10739                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10740                                         ret, hw->aq.asq_last_status);
10741                                 return -ENOSYS;
10742                         }
10743                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10744                         rte_free(mirr_rule);
10745                         pf->nb_mirror_rule--;
10746                         return 0;
10747                 }
10748         } else if (!on) {
10749                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10750                 return -ENOENT;
10751         }
10752
10753         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10754                                 sizeof(struct i40e_mirror_rule) , 0);
10755         if (!mirr_rule) {
10756                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10757                 return I40E_ERR_NO_MEMORY;
10758         }
10759         switch (mirror_conf->rule_type) {
10760         case ETH_MIRROR_VLAN:
10761                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10762                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10763                                 mirr_rule->entries[j] =
10764                                         mirror_conf->vlan.vlan_id[i];
10765                                 j++;
10766                         }
10767                 }
10768                 if (j == 0) {
10769                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10770                         rte_free(mirr_rule);
10771                         return -EINVAL;
10772                 }
10773                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10774                 break;
10775         case ETH_MIRROR_VIRTUAL_POOL_UP:
10776         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10777                 /* check if the specified pool bit is out of range */
10778                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10779                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10780                         rte_free(mirr_rule);
10781                         return -EINVAL;
10782                 }
10783                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10784                         if (mirror_conf->pool_mask & (1ULL << i)) {
10785                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10786                                 j++;
10787                         }
10788                 }
10789                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10790                         /* add pf vsi to entries */
10791                         mirr_rule->entries[j] = pf->main_vsi_seid;
10792                         j++;
10793                 }
10794                 if (j == 0) {
10795                         PMD_DRV_LOG(ERR, "pool is not specified.");
10796                         rte_free(mirr_rule);
10797                         return -EINVAL;
10798                 }
10799                 /* egress and ingress in aq commands means from switch but not port */
10800                 mirr_rule->rule_type =
10801                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10802                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10803                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10804                 break;
10805         case ETH_MIRROR_UPLINK_PORT:
10806                 /* egress and ingress in aq commands means from switch but not port*/
10807                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10808                 break;
10809         case ETH_MIRROR_DOWNLINK_PORT:
10810                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10811                 break;
10812         default:
10813                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10814                         mirror_conf->rule_type);
10815                 rte_free(mirr_rule);
10816                 return -EINVAL;
10817         }
10818
10819         /* If the dst_pool is equal to vf_num, consider it as PF */
10820         if (mirror_conf->dst_pool == pf->vf_num)
10821                 dst_seid = pf->main_vsi_seid;
10822         else
10823                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10824
10825         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10826                                       mirr_rule->rule_type, mirr_rule->entries,
10827                                       j, &rule_id);
10828         if (ret < 0) {
10829                 PMD_DRV_LOG(ERR,
10830                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10831                         ret, hw->aq.asq_last_status);
10832                 rte_free(mirr_rule);
10833                 return -ENOSYS;
10834         }
10835
10836         mirr_rule->index = sw_id;
10837         mirr_rule->num_entries = j;
10838         mirr_rule->id = rule_id;
10839         mirr_rule->dst_vsi_seid = dst_seid;
10840
10841         if (parent)
10842                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10843         else
10844                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10845
10846         pf->nb_mirror_rule++;
10847         return 0;
10848 }
10849
10850 /**
10851  * i40e_mirror_rule_reset
10852  * @dev: pointer to the device
10853  * @sw_id: mirror rule's sw_id
10854  *
10855  * reset a mirror rule.
10856  *
10857  **/
10858 static int
10859 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10860 {
10861         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10862         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10863         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10864         uint16_t seid;
10865         int ret;
10866
10867         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10868
10869         seid = pf->main_vsi->veb->seid;
10870
10871         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10872                 if (sw_id == it->index) {
10873                         mirr_rule = it;
10874                         break;
10875                 }
10876         }
10877         if (mirr_rule) {
10878                 ret = i40e_aq_del_mirror_rule(hw, seid,
10879                                 mirr_rule->rule_type,
10880                                 mirr_rule->entries,
10881                                 mirr_rule->num_entries, mirr_rule->id);
10882                 if (ret < 0) {
10883                         PMD_DRV_LOG(ERR,
10884                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10885                                 ret, hw->aq.asq_last_status);
10886                         return -ENOSYS;
10887                 }
10888                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10889                 rte_free(mirr_rule);
10890                 pf->nb_mirror_rule--;
10891         } else {
10892                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10893                 return -ENOENT;
10894         }
10895         return 0;
10896 }
10897
10898 static uint64_t
10899 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10900 {
10901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10902         uint64_t systim_cycles;
10903
10904         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10905         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10906                         << 32;
10907
10908         return systim_cycles;
10909 }
10910
10911 static uint64_t
10912 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10913 {
10914         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10915         uint64_t rx_tstamp;
10916
10917         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10918         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10919                         << 32;
10920
10921         return rx_tstamp;
10922 }
10923
10924 static uint64_t
10925 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10926 {
10927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10928         uint64_t tx_tstamp;
10929
10930         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10931         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10932                         << 32;
10933
10934         return tx_tstamp;
10935 }
10936
10937 static void
10938 i40e_start_timecounters(struct rte_eth_dev *dev)
10939 {
10940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10941         struct i40e_adapter *adapter = dev->data->dev_private;
10942         struct rte_eth_link link;
10943         uint32_t tsync_inc_l;
10944         uint32_t tsync_inc_h;
10945
10946         /* Get current link speed. */
10947         i40e_dev_link_update(dev, 1);
10948         rte_eth_linkstatus_get(dev, &link);
10949
10950         switch (link.link_speed) {
10951         case ETH_SPEED_NUM_40G:
10952         case ETH_SPEED_NUM_25G:
10953                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10954                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10955                 break;
10956         case ETH_SPEED_NUM_10G:
10957                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10958                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10959                 break;
10960         case ETH_SPEED_NUM_1G:
10961                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10962                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10963                 break;
10964         default:
10965                 tsync_inc_l = 0x0;
10966                 tsync_inc_h = 0x0;
10967         }
10968
10969         /* Set the timesync increment value. */
10970         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10971         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10972
10973         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10974         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10975         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10976
10977         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10978         adapter->systime_tc.cc_shift = 0;
10979         adapter->systime_tc.nsec_mask = 0;
10980
10981         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10982         adapter->rx_tstamp_tc.cc_shift = 0;
10983         adapter->rx_tstamp_tc.nsec_mask = 0;
10984
10985         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10986         adapter->tx_tstamp_tc.cc_shift = 0;
10987         adapter->tx_tstamp_tc.nsec_mask = 0;
10988 }
10989
10990 static int
10991 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10992 {
10993         struct i40e_adapter *adapter = dev->data->dev_private;
10994
10995         adapter->systime_tc.nsec += delta;
10996         adapter->rx_tstamp_tc.nsec += delta;
10997         adapter->tx_tstamp_tc.nsec += delta;
10998
10999         return 0;
11000 }
11001
11002 static int
11003 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11004 {
11005         uint64_t ns;
11006         struct i40e_adapter *adapter = dev->data->dev_private;
11007
11008         ns = rte_timespec_to_ns(ts);
11009
11010         /* Set the timecounters to a new value. */
11011         adapter->systime_tc.nsec = ns;
11012         adapter->rx_tstamp_tc.nsec = ns;
11013         adapter->tx_tstamp_tc.nsec = ns;
11014
11015         return 0;
11016 }
11017
11018 static int
11019 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11020 {
11021         uint64_t ns, systime_cycles;
11022         struct i40e_adapter *adapter = dev->data->dev_private;
11023
11024         systime_cycles = i40e_read_systime_cyclecounter(dev);
11025         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11026         *ts = rte_ns_to_timespec(ns);
11027
11028         return 0;
11029 }
11030
11031 static int
11032 i40e_timesync_enable(struct rte_eth_dev *dev)
11033 {
11034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11035         uint32_t tsync_ctl_l;
11036         uint32_t tsync_ctl_h;
11037
11038         /* Stop the timesync system time. */
11039         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11040         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11041         /* Reset the timesync system time value. */
11042         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11043         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11044
11045         i40e_start_timecounters(dev);
11046
11047         /* Clear timesync registers. */
11048         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11049         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11050         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11051         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11052         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11053         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11054
11055         /* Enable timestamping of PTP packets. */
11056         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11057         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11058
11059         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11060         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11061         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11062
11063         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11064         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11065
11066         return 0;
11067 }
11068
11069 static int
11070 i40e_timesync_disable(struct rte_eth_dev *dev)
11071 {
11072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11073         uint32_t tsync_ctl_l;
11074         uint32_t tsync_ctl_h;
11075
11076         /* Disable timestamping of transmitted PTP packets. */
11077         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11078         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11079
11080         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11081         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11082
11083         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11084         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11085
11086         /* Reset the timesync increment value. */
11087         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11088         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11089
11090         return 0;
11091 }
11092
11093 static int
11094 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11095                                 struct timespec *timestamp, uint32_t flags)
11096 {
11097         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11098         struct i40e_adapter *adapter = dev->data->dev_private;
11099         uint32_t sync_status;
11100         uint32_t index = flags & 0x03;
11101         uint64_t rx_tstamp_cycles;
11102         uint64_t ns;
11103
11104         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11105         if ((sync_status & (1 << index)) == 0)
11106                 return -EINVAL;
11107
11108         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11109         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11110         *timestamp = rte_ns_to_timespec(ns);
11111
11112         return 0;
11113 }
11114
11115 static int
11116 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11117                                 struct timespec *timestamp)
11118 {
11119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11120         struct i40e_adapter *adapter = dev->data->dev_private;
11121         uint32_t sync_status;
11122         uint64_t tx_tstamp_cycles;
11123         uint64_t ns;
11124
11125         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11126         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11127                 return -EINVAL;
11128
11129         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11130         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11131         *timestamp = rte_ns_to_timespec(ns);
11132
11133         return 0;
11134 }
11135
11136 /*
11137  * i40e_parse_dcb_configure - parse dcb configure from user
11138  * @dev: the device being configured
11139  * @dcb_cfg: pointer of the result of parse
11140  * @*tc_map: bit map of enabled traffic classes
11141  *
11142  * Returns 0 on success, negative value on failure
11143  */
11144 static int
11145 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11146                          struct i40e_dcbx_config *dcb_cfg,
11147                          uint8_t *tc_map)
11148 {
11149         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11150         uint8_t i, tc_bw, bw_lf;
11151
11152         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11153
11154         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11155         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11156                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11157                 return -EINVAL;
11158         }
11159
11160         /* assume each tc has the same bw */
11161         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11162         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11163                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11164         /* to ensure the sum of tcbw is equal to 100 */
11165         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11166         for (i = 0; i < bw_lf; i++)
11167                 dcb_cfg->etscfg.tcbwtable[i]++;
11168
11169         /* assume each tc has the same Transmission Selection Algorithm */
11170         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11171                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11172
11173         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11174                 dcb_cfg->etscfg.prioritytable[i] =
11175                                 dcb_rx_conf->dcb_tc[i];
11176
11177         /* FW needs one App to configure HW */
11178         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11179         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11180         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11181         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11182
11183         if (dcb_rx_conf->nb_tcs == 0)
11184                 *tc_map = 1; /* tc0 only */
11185         else
11186                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11187
11188         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11189                 dcb_cfg->pfc.willing = 0;
11190                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11191                 dcb_cfg->pfc.pfcenable = *tc_map;
11192         }
11193         return 0;
11194 }
11195
11196
11197 static enum i40e_status_code
11198 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11199                               struct i40e_aqc_vsi_properties_data *info,
11200                               uint8_t enabled_tcmap)
11201 {
11202         enum i40e_status_code ret;
11203         int i, total_tc = 0;
11204         uint16_t qpnum_per_tc, bsf, qp_idx;
11205         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11206         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11207         uint16_t used_queues;
11208
11209         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11210         if (ret != I40E_SUCCESS)
11211                 return ret;
11212
11213         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11214                 if (enabled_tcmap & (1 << i))
11215                         total_tc++;
11216         }
11217         if (total_tc == 0)
11218                 total_tc = 1;
11219         vsi->enabled_tc = enabled_tcmap;
11220
11221         /* different VSI has different queues assigned */
11222         if (vsi->type == I40E_VSI_MAIN)
11223                 used_queues = dev_data->nb_rx_queues -
11224                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11225         else if (vsi->type == I40E_VSI_VMDQ2)
11226                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11227         else {
11228                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11229                 return I40E_ERR_NO_AVAILABLE_VSI;
11230         }
11231
11232         qpnum_per_tc = used_queues / total_tc;
11233         /* Number of queues per enabled TC */
11234         if (qpnum_per_tc == 0) {
11235                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11236                 return I40E_ERR_INVALID_QP_ID;
11237         }
11238         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11239                                 I40E_MAX_Q_PER_TC);
11240         bsf = rte_bsf32(qpnum_per_tc);
11241
11242         /**
11243          * Configure TC and queue mapping parameters, for enabled TC,
11244          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11245          * default queue will serve it.
11246          */
11247         qp_idx = 0;
11248         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11249                 if (vsi->enabled_tc & (1 << i)) {
11250                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11251                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11252                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11253                         qp_idx += qpnum_per_tc;
11254                 } else
11255                         info->tc_mapping[i] = 0;
11256         }
11257
11258         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11259         if (vsi->type == I40E_VSI_SRIOV) {
11260                 info->mapping_flags |=
11261                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11262                 for (i = 0; i < vsi->nb_qps; i++)
11263                         info->queue_mapping[i] =
11264                                 rte_cpu_to_le_16(vsi->base_queue + i);
11265         } else {
11266                 info->mapping_flags |=
11267                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11268                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11269         }
11270         info->valid_sections |=
11271                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11272
11273         return I40E_SUCCESS;
11274 }
11275
11276 /*
11277  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11278  * @veb: VEB to be configured
11279  * @tc_map: enabled TC bitmap
11280  *
11281  * Returns 0 on success, negative value on failure
11282  */
11283 static enum i40e_status_code
11284 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11285 {
11286         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11287         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11288         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11289         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11290         enum i40e_status_code ret = I40E_SUCCESS;
11291         int i;
11292         uint32_t bw_max;
11293
11294         /* Check if enabled_tc is same as existing or new TCs */
11295         if (veb->enabled_tc == tc_map)
11296                 return ret;
11297
11298         /* configure tc bandwidth */
11299         memset(&veb_bw, 0, sizeof(veb_bw));
11300         veb_bw.tc_valid_bits = tc_map;
11301         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11302         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11303                 if (tc_map & BIT_ULL(i))
11304                         veb_bw.tc_bw_share_credits[i] = 1;
11305         }
11306         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11307                                                    &veb_bw, NULL);
11308         if (ret) {
11309                 PMD_INIT_LOG(ERR,
11310                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11311                         hw->aq.asq_last_status);
11312                 return ret;
11313         }
11314
11315         memset(&ets_query, 0, sizeof(ets_query));
11316         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11317                                                    &ets_query, NULL);
11318         if (ret != I40E_SUCCESS) {
11319                 PMD_DRV_LOG(ERR,
11320                         "Failed to get switch_comp ETS configuration %u",
11321                         hw->aq.asq_last_status);
11322                 return ret;
11323         }
11324         memset(&bw_query, 0, sizeof(bw_query));
11325         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11326                                                   &bw_query, NULL);
11327         if (ret != I40E_SUCCESS) {
11328                 PMD_DRV_LOG(ERR,
11329                         "Failed to get switch_comp bandwidth configuration %u",
11330                         hw->aq.asq_last_status);
11331                 return ret;
11332         }
11333
11334         /* store and print out BW info */
11335         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11336         veb->bw_info.bw_max = ets_query.tc_bw_max;
11337         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11338         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11339         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11340                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11341                      I40E_16_BIT_WIDTH);
11342         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11343                 veb->bw_info.bw_ets_share_credits[i] =
11344                                 bw_query.tc_bw_share_credits[i];
11345                 veb->bw_info.bw_ets_credits[i] =
11346                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11347                 /* 4 bits per TC, 4th bit is reserved */
11348                 veb->bw_info.bw_ets_max[i] =
11349                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11350                                   RTE_LEN2MASK(3, uint8_t));
11351                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11352                             veb->bw_info.bw_ets_share_credits[i]);
11353                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11354                             veb->bw_info.bw_ets_credits[i]);
11355                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11356                             veb->bw_info.bw_ets_max[i]);
11357         }
11358
11359         veb->enabled_tc = tc_map;
11360
11361         return ret;
11362 }
11363
11364
11365 /*
11366  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11367  * @vsi: VSI to be configured
11368  * @tc_map: enabled TC bitmap
11369  *
11370  * Returns 0 on success, negative value on failure
11371  */
11372 static enum i40e_status_code
11373 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11374 {
11375         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11376         struct i40e_vsi_context ctxt;
11377         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11378         enum i40e_status_code ret = I40E_SUCCESS;
11379         int i;
11380
11381         /* Check if enabled_tc is same as existing or new TCs */
11382         if (vsi->enabled_tc == tc_map)
11383                 return ret;
11384
11385         /* configure tc bandwidth */
11386         memset(&bw_data, 0, sizeof(bw_data));
11387         bw_data.tc_valid_bits = tc_map;
11388         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11389         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11390                 if (tc_map & BIT_ULL(i))
11391                         bw_data.tc_bw_credits[i] = 1;
11392         }
11393         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11394         if (ret) {
11395                 PMD_INIT_LOG(ERR,
11396                         "AQ command Config VSI BW allocation per TC failed = %d",
11397                         hw->aq.asq_last_status);
11398                 goto out;
11399         }
11400         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11401                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11402
11403         /* Update Queue Pairs Mapping for currently enabled UPs */
11404         ctxt.seid = vsi->seid;
11405         ctxt.pf_num = hw->pf_id;
11406         ctxt.vf_num = 0;
11407         ctxt.uplink_seid = vsi->uplink_seid;
11408         ctxt.info = vsi->info;
11409         i40e_get_cap(hw);
11410         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11411         if (ret)
11412                 goto out;
11413
11414         /* Update the VSI after updating the VSI queue-mapping information */
11415         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11416         if (ret) {
11417                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11418                         hw->aq.asq_last_status);
11419                 goto out;
11420         }
11421         /* update the local VSI info with updated queue map */
11422         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11423                                         sizeof(vsi->info.tc_mapping));
11424         rte_memcpy(&vsi->info.queue_mapping,
11425                         &ctxt.info.queue_mapping,
11426                 sizeof(vsi->info.queue_mapping));
11427         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11428         vsi->info.valid_sections = 0;
11429
11430         /* query and update current VSI BW information */
11431         ret = i40e_vsi_get_bw_config(vsi);
11432         if (ret) {
11433                 PMD_INIT_LOG(ERR,
11434                          "Failed updating vsi bw info, err %s aq_err %s",
11435                          i40e_stat_str(hw, ret),
11436                          i40e_aq_str(hw, hw->aq.asq_last_status));
11437                 goto out;
11438         }
11439
11440         vsi->enabled_tc = tc_map;
11441
11442 out:
11443         return ret;
11444 }
11445
11446 /*
11447  * i40e_dcb_hw_configure - program the dcb setting to hw
11448  * @pf: pf the configuration is taken on
11449  * @new_cfg: new configuration
11450  * @tc_map: enabled TC bitmap
11451  *
11452  * Returns 0 on success, negative value on failure
11453  */
11454 static enum i40e_status_code
11455 i40e_dcb_hw_configure(struct i40e_pf *pf,
11456                       struct i40e_dcbx_config *new_cfg,
11457                       uint8_t tc_map)
11458 {
11459         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11460         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11461         struct i40e_vsi *main_vsi = pf->main_vsi;
11462         struct i40e_vsi_list *vsi_list;
11463         enum i40e_status_code ret;
11464         int i;
11465         uint32_t val;
11466
11467         /* Use the FW API if FW > v4.4*/
11468         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11469               (hw->aq.fw_maj_ver >= 5))) {
11470                 PMD_INIT_LOG(ERR,
11471                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11472                 return I40E_ERR_FIRMWARE_API_VERSION;
11473         }
11474
11475         /* Check if need reconfiguration */
11476         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11477                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11478                 return I40E_SUCCESS;
11479         }
11480
11481         /* Copy the new config to the current config */
11482         *old_cfg = *new_cfg;
11483         old_cfg->etsrec = old_cfg->etscfg;
11484         ret = i40e_set_dcb_config(hw);
11485         if (ret) {
11486                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11487                          i40e_stat_str(hw, ret),
11488                          i40e_aq_str(hw, hw->aq.asq_last_status));
11489                 return ret;
11490         }
11491         /* set receive Arbiter to RR mode and ETS scheme by default */
11492         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11493                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11494                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11495                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11496                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11497                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11498                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11499                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11500                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11501                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11502                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11503                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11504                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11505         }
11506         /* get local mib to check whether it is configured correctly */
11507         /* IEEE mode */
11508         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11509         /* Get Local DCB Config */
11510         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11511                                      &hw->local_dcbx_config);
11512
11513         /* if Veb is created, need to update TC of it at first */
11514         if (main_vsi->veb) {
11515                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11516                 if (ret)
11517                         PMD_INIT_LOG(WARNING,
11518                                  "Failed configuring TC for VEB seid=%d",
11519                                  main_vsi->veb->seid);
11520         }
11521         /* Update each VSI */
11522         i40e_vsi_config_tc(main_vsi, tc_map);
11523         if (main_vsi->veb) {
11524                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11525                         /* Beside main VSI and VMDQ VSIs, only enable default
11526                          * TC for other VSIs
11527                          */
11528                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11529                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11530                                                          tc_map);
11531                         else
11532                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11533                                                          I40E_DEFAULT_TCMAP);
11534                         if (ret)
11535                                 PMD_INIT_LOG(WARNING,
11536                                         "Failed configuring TC for VSI seid=%d",
11537                                         vsi_list->vsi->seid);
11538                         /* continue */
11539                 }
11540         }
11541         return I40E_SUCCESS;
11542 }
11543
11544 /*
11545  * i40e_dcb_init_configure - initial dcb config
11546  * @dev: device being configured
11547  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11548  *
11549  * Returns 0 on success, negative value on failure
11550  */
11551 int
11552 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11553 {
11554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11555         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11556         int i, ret = 0;
11557
11558         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11559                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11560                 return -ENOTSUP;
11561         }
11562
11563         /* DCB initialization:
11564          * Update DCB configuration from the Firmware and configure
11565          * LLDP MIB change event.
11566          */
11567         if (sw_dcb == TRUE) {
11568                 if (i40e_need_stop_lldp(dev)) {
11569                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11570                         if (ret != I40E_SUCCESS)
11571                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11572                 }
11573
11574                 ret = i40e_init_dcb(hw);
11575                 /* If lldp agent is stopped, the return value from
11576                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11577                  * adminq status. Otherwise, it should return success.
11578                  */
11579                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11580                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11581                         memset(&hw->local_dcbx_config, 0,
11582                                 sizeof(struct i40e_dcbx_config));
11583                         /* set dcb default configuration */
11584                         hw->local_dcbx_config.etscfg.willing = 0;
11585                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11586                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11587                         hw->local_dcbx_config.etscfg.tsatable[0] =
11588                                                 I40E_IEEE_TSA_ETS;
11589                         /* all UPs mapping to TC0 */
11590                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11591                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11592                         hw->local_dcbx_config.etsrec =
11593                                 hw->local_dcbx_config.etscfg;
11594                         hw->local_dcbx_config.pfc.willing = 0;
11595                         hw->local_dcbx_config.pfc.pfccap =
11596                                                 I40E_MAX_TRAFFIC_CLASS;
11597                         /* FW needs one App to configure HW */
11598                         hw->local_dcbx_config.numapps = 1;
11599                         hw->local_dcbx_config.app[0].selector =
11600                                                 I40E_APP_SEL_ETHTYPE;
11601                         hw->local_dcbx_config.app[0].priority = 3;
11602                         hw->local_dcbx_config.app[0].protocolid =
11603                                                 I40E_APP_PROTOID_FCOE;
11604                         ret = i40e_set_dcb_config(hw);
11605                         if (ret) {
11606                                 PMD_INIT_LOG(ERR,
11607                                         "default dcb config fails. err = %d, aq_err = %d.",
11608                                         ret, hw->aq.asq_last_status);
11609                                 return -ENOSYS;
11610                         }
11611                 } else {
11612                         PMD_INIT_LOG(ERR,
11613                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11614                                 ret, hw->aq.asq_last_status);
11615                         return -ENOTSUP;
11616                 }
11617         } else {
11618                 ret = i40e_aq_start_lldp(hw, NULL);
11619                 if (ret != I40E_SUCCESS)
11620                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11621
11622                 ret = i40e_init_dcb(hw);
11623                 if (!ret) {
11624                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11625                                 PMD_INIT_LOG(ERR,
11626                                         "HW doesn't support DCBX offload.");
11627                                 return -ENOTSUP;
11628                         }
11629                 } else {
11630                         PMD_INIT_LOG(ERR,
11631                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11632                                 ret, hw->aq.asq_last_status);
11633                         return -ENOTSUP;
11634                 }
11635         }
11636         return 0;
11637 }
11638
11639 /*
11640  * i40e_dcb_setup - setup dcb related config
11641  * @dev: device being configured
11642  *
11643  * Returns 0 on success, negative value on failure
11644  */
11645 static int
11646 i40e_dcb_setup(struct rte_eth_dev *dev)
11647 {
11648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11649         struct i40e_dcbx_config dcb_cfg;
11650         uint8_t tc_map = 0;
11651         int ret = 0;
11652
11653         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11654                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11655                 return -ENOTSUP;
11656         }
11657
11658         if (pf->vf_num != 0)
11659                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11660
11661         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11662         if (ret) {
11663                 PMD_INIT_LOG(ERR, "invalid dcb config");
11664                 return -EINVAL;
11665         }
11666         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11667         if (ret) {
11668                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11669                 return -ENOSYS;
11670         }
11671
11672         return 0;
11673 }
11674
11675 static int
11676 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11677                       struct rte_eth_dcb_info *dcb_info)
11678 {
11679         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11681         struct i40e_vsi *vsi = pf->main_vsi;
11682         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11683         uint16_t bsf, tc_mapping;
11684         int i, j = 0;
11685
11686         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11687                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11688         else
11689                 dcb_info->nb_tcs = 1;
11690         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11691                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11692         for (i = 0; i < dcb_info->nb_tcs; i++)
11693                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11694
11695         /* get queue mapping if vmdq is disabled */
11696         if (!pf->nb_cfg_vmdq_vsi) {
11697                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11698                         if (!(vsi->enabled_tc & (1 << i)))
11699                                 continue;
11700                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11701                         dcb_info->tc_queue.tc_rxq[j][i].base =
11702                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11703                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11704                         dcb_info->tc_queue.tc_txq[j][i].base =
11705                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11706                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11707                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11708                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11709                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11710                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11711                 }
11712                 return 0;
11713         }
11714
11715         /* get queue mapping if vmdq is enabled */
11716         do {
11717                 vsi = pf->vmdq[j].vsi;
11718                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11719                         if (!(vsi->enabled_tc & (1 << i)))
11720                                 continue;
11721                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11722                         dcb_info->tc_queue.tc_rxq[j][i].base =
11723                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11724                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11725                         dcb_info->tc_queue.tc_txq[j][i].base =
11726                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11727                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11728                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11729                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11730                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11731                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11732                 }
11733                 j++;
11734         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11735         return 0;
11736 }
11737
11738 static int
11739 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11740 {
11741         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11742         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11743         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11744         uint16_t msix_intr;
11745
11746         msix_intr = intr_handle->intr_vec[queue_id];
11747         if (msix_intr == I40E_MISC_VEC_ID)
11748                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11749                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11750                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11751                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11752         else
11753                 I40E_WRITE_REG(hw,
11754                                I40E_PFINT_DYN_CTLN(msix_intr -
11755                                                    I40E_RX_VEC_START),
11756                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11757                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11758                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11759
11760         I40E_WRITE_FLUSH(hw);
11761         rte_intr_ack(&pci_dev->intr_handle);
11762
11763         return 0;
11764 }
11765
11766 static int
11767 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11768 {
11769         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11770         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11772         uint16_t msix_intr;
11773
11774         msix_intr = intr_handle->intr_vec[queue_id];
11775         if (msix_intr == I40E_MISC_VEC_ID)
11776                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11777                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11778         else
11779                 I40E_WRITE_REG(hw,
11780                                I40E_PFINT_DYN_CTLN(msix_intr -
11781                                                    I40E_RX_VEC_START),
11782                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11783         I40E_WRITE_FLUSH(hw);
11784
11785         return 0;
11786 }
11787
11788 /**
11789  * This function is used to check if the register is valid.
11790  * Below is the valid registers list for X722 only:
11791  * 0x2b800--0x2bb00
11792  * 0x38700--0x38a00
11793  * 0x3d800--0x3db00
11794  * 0x208e00--0x209000
11795  * 0x20be00--0x20c000
11796  * 0x263c00--0x264000
11797  * 0x265c00--0x266000
11798  */
11799 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11800 {
11801         if ((type != I40E_MAC_X722) &&
11802             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11803              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11804              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11805              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11806              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11807              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11808              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11809                 return 0;
11810         else
11811                 return 1;
11812 }
11813
11814 static int i40e_get_regs(struct rte_eth_dev *dev,
11815                          struct rte_dev_reg_info *regs)
11816 {
11817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11818         uint32_t *ptr_data = regs->data;
11819         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11820         const struct i40e_reg_info *reg_info;
11821
11822         if (ptr_data == NULL) {
11823                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11824                 regs->width = sizeof(uint32_t);
11825                 return 0;
11826         }
11827
11828         /* The first few registers have to be read using AQ operations */
11829         reg_idx = 0;
11830         while (i40e_regs_adminq[reg_idx].name) {
11831                 reg_info = &i40e_regs_adminq[reg_idx++];
11832                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11833                         for (arr_idx2 = 0;
11834                                         arr_idx2 <= reg_info->count2;
11835                                         arr_idx2++) {
11836                                 reg_offset = arr_idx * reg_info->stride1 +
11837                                         arr_idx2 * reg_info->stride2;
11838                                 reg_offset += reg_info->base_addr;
11839                                 ptr_data[reg_offset >> 2] =
11840                                         i40e_read_rx_ctl(hw, reg_offset);
11841                         }
11842         }
11843
11844         /* The remaining registers can be read using primitives */
11845         reg_idx = 0;
11846         while (i40e_regs_others[reg_idx].name) {
11847                 reg_info = &i40e_regs_others[reg_idx++];
11848                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11849                         for (arr_idx2 = 0;
11850                                         arr_idx2 <= reg_info->count2;
11851                                         arr_idx2++) {
11852                                 reg_offset = arr_idx * reg_info->stride1 +
11853                                         arr_idx2 * reg_info->stride2;
11854                                 reg_offset += reg_info->base_addr;
11855                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11856                                         ptr_data[reg_offset >> 2] = 0;
11857                                 else
11858                                         ptr_data[reg_offset >> 2] =
11859                                                 I40E_READ_REG(hw, reg_offset);
11860                         }
11861         }
11862
11863         return 0;
11864 }
11865
11866 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11867 {
11868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11869
11870         /* Convert word count to byte count */
11871         return hw->nvm.sr_size << 1;
11872 }
11873
11874 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11875                            struct rte_dev_eeprom_info *eeprom)
11876 {
11877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11878         uint16_t *data = eeprom->data;
11879         uint16_t offset, length, cnt_words;
11880         int ret_code;
11881
11882         offset = eeprom->offset >> 1;
11883         length = eeprom->length >> 1;
11884         cnt_words = length;
11885
11886         if (offset > hw->nvm.sr_size ||
11887                 offset + length > hw->nvm.sr_size) {
11888                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11889                 return -EINVAL;
11890         }
11891
11892         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11893
11894         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11895         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11896                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11897                 return -EIO;
11898         }
11899
11900         return 0;
11901 }
11902
11903 static int i40e_get_module_info(struct rte_eth_dev *dev,
11904                                 struct rte_eth_dev_module_info *modinfo)
11905 {
11906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11907         uint32_t sff8472_comp = 0;
11908         uint32_t sff8472_swap = 0;
11909         uint32_t sff8636_rev = 0;
11910         i40e_status status;
11911         uint32_t type = 0;
11912
11913         /* Check if firmware supports reading module EEPROM. */
11914         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11915                 PMD_DRV_LOG(ERR,
11916                             "Module EEPROM memory read not supported. "
11917                             "Please update the NVM image.\n");
11918                 return -EINVAL;
11919         }
11920
11921         status = i40e_update_link_info(hw);
11922         if (status)
11923                 return -EIO;
11924
11925         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11926                 PMD_DRV_LOG(ERR,
11927                             "Cannot read module EEPROM memory. "
11928                             "No module connected.\n");
11929                 return -EINVAL;
11930         }
11931
11932         type = hw->phy.link_info.module_type[0];
11933
11934         switch (type) {
11935         case I40E_MODULE_TYPE_SFP:
11936                 status = i40e_aq_get_phy_register(hw,
11937                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11938                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11939                                 I40E_MODULE_SFF_8472_COMP,
11940                                 &sff8472_comp, NULL);
11941                 if (status)
11942                         return -EIO;
11943
11944                 status = i40e_aq_get_phy_register(hw,
11945                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11946                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11947                                 I40E_MODULE_SFF_8472_SWAP,
11948                                 &sff8472_swap, NULL);
11949                 if (status)
11950                         return -EIO;
11951
11952                 /* Check if the module requires address swap to access
11953                  * the other EEPROM memory page.
11954                  */
11955                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11956                         PMD_DRV_LOG(WARNING,
11957                                     "Module address swap to access "
11958                                     "page 0xA2 is not supported.\n");
11959                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11960                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11961                 } else if (sff8472_comp == 0x00) {
11962                         /* Module is not SFF-8472 compliant */
11963                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11964                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11965                 } else {
11966                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11967                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11968                 }
11969                 break;
11970         case I40E_MODULE_TYPE_QSFP_PLUS:
11971                 /* Read from memory page 0. */
11972                 status = i40e_aq_get_phy_register(hw,
11973                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11974                                 0, 1,
11975                                 I40E_MODULE_REVISION_ADDR,
11976                                 &sff8636_rev, NULL);
11977                 if (status)
11978                         return -EIO;
11979                 /* Determine revision compliance byte */
11980                 if (sff8636_rev > 0x02) {
11981                         /* Module is SFF-8636 compliant */
11982                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11983                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11984                 } else {
11985                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11986                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11987                 }
11988                 break;
11989         case I40E_MODULE_TYPE_QSFP28:
11990                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11991                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11992                 break;
11993         default:
11994                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11995                 return -EINVAL;
11996         }
11997         return 0;
11998 }
11999
12000 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12001                                   struct rte_dev_eeprom_info *info)
12002 {
12003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12004         bool is_sfp = false;
12005         i40e_status status;
12006         uint8_t *data;
12007         uint32_t value = 0;
12008         uint32_t i;
12009
12010         if (!info || !info->length || !info->data)
12011                 return -EINVAL;
12012
12013         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12014                 is_sfp = true;
12015
12016         data = info->data;
12017         for (i = 0; i < info->length; i++) {
12018                 u32 offset = i + info->offset;
12019                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12020
12021                 /* Check if we need to access the other memory page */
12022                 if (is_sfp) {
12023                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12024                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12025                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12026                         }
12027                 } else {
12028                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12029                                 /* Compute memory page number and offset. */
12030                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12031                                 addr++;
12032                         }
12033                 }
12034                 status = i40e_aq_get_phy_register(hw,
12035                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12036                                 addr, offset, 1, &value, NULL);
12037                 if (status)
12038                         return -EIO;
12039                 data[i] = (uint8_t)value;
12040         }
12041         return 0;
12042 }
12043
12044 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12045                                      struct rte_ether_addr *mac_addr)
12046 {
12047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12049         struct i40e_vsi *vsi = pf->main_vsi;
12050         struct i40e_mac_filter_info mac_filter;
12051         struct i40e_mac_filter *f;
12052         int ret;
12053
12054         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12055                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12056                 return -EINVAL;
12057         }
12058
12059         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12060                 if (rte_is_same_ether_addr(&pf->dev_addr,
12061                                                 &f->mac_info.mac_addr))
12062                         break;
12063         }
12064
12065         if (f == NULL) {
12066                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12067                 return -EIO;
12068         }
12069
12070         mac_filter = f->mac_info;
12071         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12072         if (ret != I40E_SUCCESS) {
12073                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12074                 return -EIO;
12075         }
12076         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12077         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12078         if (ret != I40E_SUCCESS) {
12079                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12080                 return -EIO;
12081         }
12082         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12083
12084         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12085                                         mac_addr->addr_bytes, NULL);
12086         if (ret != I40E_SUCCESS) {
12087                 PMD_DRV_LOG(ERR, "Failed to change mac");
12088                 return -EIO;
12089         }
12090
12091         return 0;
12092 }
12093
12094 static int
12095 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12096 {
12097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12098         struct rte_eth_dev_data *dev_data = pf->dev_data;
12099         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12100         int ret = 0;
12101
12102         /* check if mtu is within the allowed range */
12103         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12104                 return -EINVAL;
12105
12106         /* mtu setting is forbidden if port is start */
12107         if (dev_data->dev_started) {
12108                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12109                             dev_data->port_id);
12110                 return -EBUSY;
12111         }
12112
12113         if (frame_size > RTE_ETHER_MAX_LEN)
12114                 dev_data->dev_conf.rxmode.offloads |=
12115                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12116         else
12117                 dev_data->dev_conf.rxmode.offloads &=
12118                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12119
12120         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12121
12122         return ret;
12123 }
12124
12125 /* Restore ethertype filter */
12126 static void
12127 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12128 {
12129         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12130         struct i40e_ethertype_filter_list
12131                 *ethertype_list = &pf->ethertype.ethertype_list;
12132         struct i40e_ethertype_filter *f;
12133         struct i40e_control_filter_stats stats;
12134         uint16_t flags;
12135
12136         TAILQ_FOREACH(f, ethertype_list, rules) {
12137                 flags = 0;
12138                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12139                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12140                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12141                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12142                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12143
12144                 memset(&stats, 0, sizeof(stats));
12145                 i40e_aq_add_rem_control_packet_filter(hw,
12146                                             f->input.mac_addr.addr_bytes,
12147                                             f->input.ether_type,
12148                                             flags, pf->main_vsi->seid,
12149                                             f->queue, 1, &stats, NULL);
12150         }
12151         PMD_DRV_LOG(INFO, "Ethertype filter:"
12152                     " mac_etype_used = %u, etype_used = %u,"
12153                     " mac_etype_free = %u, etype_free = %u",
12154                     stats.mac_etype_used, stats.etype_used,
12155                     stats.mac_etype_free, stats.etype_free);
12156 }
12157
12158 /* Restore tunnel filter */
12159 static void
12160 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12161 {
12162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12163         struct i40e_vsi *vsi;
12164         struct i40e_pf_vf *vf;
12165         struct i40e_tunnel_filter_list
12166                 *tunnel_list = &pf->tunnel.tunnel_list;
12167         struct i40e_tunnel_filter *f;
12168         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12169         bool big_buffer = 0;
12170
12171         TAILQ_FOREACH(f, tunnel_list, rules) {
12172                 if (!f->is_to_vf)
12173                         vsi = pf->main_vsi;
12174                 else {
12175                         vf = &pf->vfs[f->vf_id];
12176                         vsi = vf->vsi;
12177                 }
12178                 memset(&cld_filter, 0, sizeof(cld_filter));
12179                 rte_ether_addr_copy((struct rte_ether_addr *)
12180                                 &f->input.outer_mac,
12181                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12182                 rte_ether_addr_copy((struct rte_ether_addr *)
12183                                 &f->input.inner_mac,
12184                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12185                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12186                 cld_filter.element.flags = f->input.flags;
12187                 cld_filter.element.tenant_id = f->input.tenant_id;
12188                 cld_filter.element.queue_number = f->queue;
12189                 rte_memcpy(cld_filter.general_fields,
12190                            f->input.general_fields,
12191                            sizeof(f->input.general_fields));
12192
12193                 if (((f->input.flags &
12194                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12195                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12196                     ((f->input.flags &
12197                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12198                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12199                     ((f->input.flags &
12200                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12201                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12202                         big_buffer = 1;
12203
12204                 if (big_buffer)
12205                         i40e_aq_add_cloud_filters_bb(hw,
12206                                         vsi->seid, &cld_filter, 1);
12207                 else
12208                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12209                                                   &cld_filter.element, 1);
12210         }
12211 }
12212
12213 /* Restore rss filter */
12214 static inline void
12215 i40e_rss_filter_restore(struct i40e_pf *pf)
12216 {
12217         struct i40e_rte_flow_rss_conf *conf =
12218                                         &pf->rss_info;
12219         if (conf->conf.queue_num)
12220                 i40e_config_rss_filter(pf, conf, TRUE);
12221 }
12222
12223 static void
12224 i40e_filter_restore(struct i40e_pf *pf)
12225 {
12226         i40e_ethertype_filter_restore(pf);
12227         i40e_tunnel_filter_restore(pf);
12228         i40e_fdir_filter_restore(pf);
12229         i40e_rss_filter_restore(pf);
12230 }
12231
12232 bool
12233 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12234 {
12235         if (strcmp(dev->device->driver->name, drv->driver.name))
12236                 return false;
12237
12238         return true;
12239 }
12240
12241 bool
12242 is_i40e_supported(struct rte_eth_dev *dev)
12243 {
12244         return is_device_supported(dev, &rte_i40e_pmd);
12245 }
12246
12247 struct i40e_customized_pctype*
12248 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12249 {
12250         int i;
12251
12252         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12253                 if (pf->customized_pctype[i].index == index)
12254                         return &pf->customized_pctype[i];
12255         }
12256         return NULL;
12257 }
12258
12259 static int
12260 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12261                               uint32_t pkg_size, uint32_t proto_num,
12262                               struct rte_pmd_i40e_proto_info *proto,
12263                               enum rte_pmd_i40e_package_op op)
12264 {
12265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12266         uint32_t pctype_num;
12267         struct rte_pmd_i40e_ptype_info *pctype;
12268         uint32_t buff_size;
12269         struct i40e_customized_pctype *new_pctype = NULL;
12270         uint8_t proto_id;
12271         uint8_t pctype_value;
12272         char name[64];
12273         uint32_t i, j, n;
12274         int ret;
12275
12276         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12277             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12278                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12279                 return -1;
12280         }
12281
12282         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12283                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12284                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12285         if (ret) {
12286                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12287                 return -1;
12288         }
12289         if (!pctype_num) {
12290                 PMD_DRV_LOG(INFO, "No new pctype added");
12291                 return -1;
12292         }
12293
12294         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12295         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12296         if (!pctype) {
12297                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12298                 return -1;
12299         }
12300         /* get information about new pctype list */
12301         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12302                                         (uint8_t *)pctype, buff_size,
12303                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12304         if (ret) {
12305                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12306                 rte_free(pctype);
12307                 return -1;
12308         }
12309
12310         /* Update customized pctype. */
12311         for (i = 0; i < pctype_num; i++) {
12312                 pctype_value = pctype[i].ptype_id;
12313                 memset(name, 0, sizeof(name));
12314                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12315                         proto_id = pctype[i].protocols[j];
12316                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12317                                 continue;
12318                         for (n = 0; n < proto_num; n++) {
12319                                 if (proto[n].proto_id != proto_id)
12320                                         continue;
12321                                 strlcat(name, proto[n].name, sizeof(name));
12322                                 strlcat(name, "_", sizeof(name));
12323                                 break;
12324                         }
12325                 }
12326                 name[strlen(name) - 1] = '\0';
12327                 if (!strcmp(name, "GTPC"))
12328                         new_pctype =
12329                                 i40e_find_customized_pctype(pf,
12330                                                       I40E_CUSTOMIZED_GTPC);
12331                 else if (!strcmp(name, "GTPU_IPV4"))
12332                         new_pctype =
12333                                 i40e_find_customized_pctype(pf,
12334                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12335                 else if (!strcmp(name, "GTPU_IPV6"))
12336                         new_pctype =
12337                                 i40e_find_customized_pctype(pf,
12338                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12339                 else if (!strcmp(name, "GTPU"))
12340                         new_pctype =
12341                                 i40e_find_customized_pctype(pf,
12342                                                       I40E_CUSTOMIZED_GTPU);
12343                 if (new_pctype) {
12344                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12345                                 new_pctype->pctype = pctype_value;
12346                                 new_pctype->valid = true;
12347                         } else {
12348                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12349                                 new_pctype->valid = false;
12350                         }
12351                 }
12352         }
12353
12354         rte_free(pctype);
12355         return 0;
12356 }
12357
12358 static int
12359 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12360                              uint32_t pkg_size, uint32_t proto_num,
12361                              struct rte_pmd_i40e_proto_info *proto,
12362                              enum rte_pmd_i40e_package_op op)
12363 {
12364         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12365         uint16_t port_id = dev->data->port_id;
12366         uint32_t ptype_num;
12367         struct rte_pmd_i40e_ptype_info *ptype;
12368         uint32_t buff_size;
12369         uint8_t proto_id;
12370         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12371         uint32_t i, j, n;
12372         bool in_tunnel;
12373         int ret;
12374
12375         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12376             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12377                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12378                 return -1;
12379         }
12380
12381         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12382                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12383                 return 0;
12384         }
12385
12386         /* get information about new ptype num */
12387         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12388                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12389                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12390         if (ret) {
12391                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12392                 return ret;
12393         }
12394         if (!ptype_num) {
12395                 PMD_DRV_LOG(INFO, "No new ptype added");
12396                 return -1;
12397         }
12398
12399         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12400         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12401         if (!ptype) {
12402                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12403                 return -1;
12404         }
12405
12406         /* get information about new ptype list */
12407         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12408                                         (uint8_t *)ptype, buff_size,
12409                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12410         if (ret) {
12411                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12412                 rte_free(ptype);
12413                 return ret;
12414         }
12415
12416         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12417         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12418         if (!ptype_mapping) {
12419                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12420                 rte_free(ptype);
12421                 return -1;
12422         }
12423
12424         /* Update ptype mapping table. */
12425         for (i = 0; i < ptype_num; i++) {
12426                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12427                 ptype_mapping[i].sw_ptype = 0;
12428                 in_tunnel = false;
12429                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12430                         proto_id = ptype[i].protocols[j];
12431                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12432                                 continue;
12433                         for (n = 0; n < proto_num; n++) {
12434                                 if (proto[n].proto_id != proto_id)
12435                                         continue;
12436                                 memset(name, 0, sizeof(name));
12437                                 strcpy(name, proto[n].name);
12438                                 if (!strncasecmp(name, "PPPOE", 5))
12439                                         ptype_mapping[i].sw_ptype |=
12440                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12441                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12442                                          !in_tunnel) {
12443                                         ptype_mapping[i].sw_ptype |=
12444                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12445                                         ptype_mapping[i].sw_ptype |=
12446                                                 RTE_PTYPE_L4_FRAG;
12447                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12448                                            in_tunnel) {
12449                                         ptype_mapping[i].sw_ptype |=
12450                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12451                                         ptype_mapping[i].sw_ptype |=
12452                                                 RTE_PTYPE_INNER_L4_FRAG;
12453                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12454                                         ptype_mapping[i].sw_ptype |=
12455                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12456                                         in_tunnel = true;
12457                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12458                                            !in_tunnel)
12459                                         ptype_mapping[i].sw_ptype |=
12460                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12461                                 else if (!strncasecmp(name, "IPV4", 4) &&
12462                                          in_tunnel)
12463                                         ptype_mapping[i].sw_ptype |=
12464                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12465                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12466                                          !in_tunnel) {
12467                                         ptype_mapping[i].sw_ptype |=
12468                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12469                                         ptype_mapping[i].sw_ptype |=
12470                                                 RTE_PTYPE_L4_FRAG;
12471                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12472                                            in_tunnel) {
12473                                         ptype_mapping[i].sw_ptype |=
12474                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12475                                         ptype_mapping[i].sw_ptype |=
12476                                                 RTE_PTYPE_INNER_L4_FRAG;
12477                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12478                                         ptype_mapping[i].sw_ptype |=
12479                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12480                                         in_tunnel = true;
12481                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12482                                            !in_tunnel)
12483                                         ptype_mapping[i].sw_ptype |=
12484                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12485                                 else if (!strncasecmp(name, "IPV6", 4) &&
12486                                          in_tunnel)
12487                                         ptype_mapping[i].sw_ptype |=
12488                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12489                                 else if (!strncasecmp(name, "UDP", 3) &&
12490                                          !in_tunnel)
12491                                         ptype_mapping[i].sw_ptype |=
12492                                                 RTE_PTYPE_L4_UDP;
12493                                 else if (!strncasecmp(name, "UDP", 3) &&
12494                                          in_tunnel)
12495                                         ptype_mapping[i].sw_ptype |=
12496                                                 RTE_PTYPE_INNER_L4_UDP;
12497                                 else if (!strncasecmp(name, "TCP", 3) &&
12498                                          !in_tunnel)
12499                                         ptype_mapping[i].sw_ptype |=
12500                                                 RTE_PTYPE_L4_TCP;
12501                                 else if (!strncasecmp(name, "TCP", 3) &&
12502                                          in_tunnel)
12503                                         ptype_mapping[i].sw_ptype |=
12504                                                 RTE_PTYPE_INNER_L4_TCP;
12505                                 else if (!strncasecmp(name, "SCTP", 4) &&
12506                                          !in_tunnel)
12507                                         ptype_mapping[i].sw_ptype |=
12508                                                 RTE_PTYPE_L4_SCTP;
12509                                 else if (!strncasecmp(name, "SCTP", 4) &&
12510                                          in_tunnel)
12511                                         ptype_mapping[i].sw_ptype |=
12512                                                 RTE_PTYPE_INNER_L4_SCTP;
12513                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12514                                           !strncasecmp(name, "ICMPV6", 6)) &&
12515                                          !in_tunnel)
12516                                         ptype_mapping[i].sw_ptype |=
12517                                                 RTE_PTYPE_L4_ICMP;
12518                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12519                                           !strncasecmp(name, "ICMPV6", 6)) &&
12520                                          in_tunnel)
12521                                         ptype_mapping[i].sw_ptype |=
12522                                                 RTE_PTYPE_INNER_L4_ICMP;
12523                                 else if (!strncasecmp(name, "GTPC", 4)) {
12524                                         ptype_mapping[i].sw_ptype |=
12525                                                 RTE_PTYPE_TUNNEL_GTPC;
12526                                         in_tunnel = true;
12527                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12528                                         ptype_mapping[i].sw_ptype |=
12529                                                 RTE_PTYPE_TUNNEL_GTPU;
12530                                         in_tunnel = true;
12531                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12532                                         ptype_mapping[i].sw_ptype |=
12533                                                 RTE_PTYPE_TUNNEL_GRENAT;
12534                                         in_tunnel = true;
12535                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12536                                            !strncasecmp(name, "L2TPV2", 6)) {
12537                                         ptype_mapping[i].sw_ptype |=
12538                                                 RTE_PTYPE_TUNNEL_L2TP;
12539                                         in_tunnel = true;
12540                                 }
12541
12542                                 break;
12543                         }
12544                 }
12545         }
12546
12547         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12548                                                 ptype_num, 0);
12549         if (ret)
12550                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12551
12552         rte_free(ptype_mapping);
12553         rte_free(ptype);
12554         return ret;
12555 }
12556
12557 void
12558 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12559                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12560 {
12561         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12562         uint32_t proto_num;
12563         struct rte_pmd_i40e_proto_info *proto;
12564         uint32_t buff_size;
12565         uint32_t i;
12566         int ret;
12567
12568         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12569             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12570                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12571                 return;
12572         }
12573
12574         /* get information about protocol number */
12575         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12576                                        (uint8_t *)&proto_num, sizeof(proto_num),
12577                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12578         if (ret) {
12579                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12580                 return;
12581         }
12582         if (!proto_num) {
12583                 PMD_DRV_LOG(INFO, "No new protocol added");
12584                 return;
12585         }
12586
12587         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12588         proto = rte_zmalloc("new_proto", buff_size, 0);
12589         if (!proto) {
12590                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12591                 return;
12592         }
12593
12594         /* get information about protocol list */
12595         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12596                                         (uint8_t *)proto, buff_size,
12597                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12598         if (ret) {
12599                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12600                 rte_free(proto);
12601                 return;
12602         }
12603
12604         /* Check if GTP is supported. */
12605         for (i = 0; i < proto_num; i++) {
12606                 if (!strncmp(proto[i].name, "GTP", 3)) {
12607                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12608                                 pf->gtp_support = true;
12609                         else
12610                                 pf->gtp_support = false;
12611                         break;
12612                 }
12613         }
12614
12615         /* Update customized pctype info */
12616         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12617                                             proto_num, proto, op);
12618         if (ret)
12619                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12620
12621         /* Update customized ptype info */
12622         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12623                                            proto_num, proto, op);
12624         if (ret)
12625                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12626
12627         rte_free(proto);
12628 }
12629
12630 /* Create a QinQ cloud filter
12631  *
12632  * The Fortville NIC has limited resources for tunnel filters,
12633  * so we can only reuse existing filters.
12634  *
12635  * In step 1 we define which Field Vector fields can be used for
12636  * filter types.
12637  * As we do not have the inner tag defined as a field,
12638  * we have to define it first, by reusing one of L1 entries.
12639  *
12640  * In step 2 we are replacing one of existing filter types with
12641  * a new one for QinQ.
12642  * As we reusing L1 and replacing L2, some of the default filter
12643  * types will disappear,which depends on L1 and L2 entries we reuse.
12644  *
12645  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12646  *
12647  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12648  *              later when we define the cloud filter.
12649  *      a.      Valid_flags.replace_cloud = 0
12650  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12651  *      c.      New_filter = 0x10
12652  *      d.      TR bit = 0xff (optional, not used here)
12653  *      e.      Buffer – 2 entries:
12654  *              i.      Byte 0 = 8 (outer vlan FV index).
12655  *                      Byte 1 = 0 (rsv)
12656  *                      Byte 2-3 = 0x0fff
12657  *              ii.     Byte 0 = 37 (inner vlan FV index).
12658  *                      Byte 1 =0 (rsv)
12659  *                      Byte 2-3 = 0x0fff
12660  *
12661  * Step 2:
12662  * 2.   Create cloud filter using two L1 filters entries: stag and
12663  *              new filter(outer vlan+ inner vlan)
12664  *      a.      Valid_flags.replace_cloud = 1
12665  *      b.      Old_filter = 1 (instead of outer IP)
12666  *      c.      New_filter = 0x10
12667  *      d.      Buffer – 2 entries:
12668  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12669  *                      Byte 1-3 = 0 (rsv)
12670  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12671  *                      Byte 9-11 = 0 (rsv)
12672  */
12673 static int
12674 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12675 {
12676         int ret = -ENOTSUP;
12677         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12678         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12680         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12681
12682         if (pf->support_multi_driver) {
12683                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12684                 return ret;
12685         }
12686
12687         /* Init */
12688         memset(&filter_replace, 0,
12689                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12690         memset(&filter_replace_buf, 0,
12691                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12692
12693         /* create L1 filter */
12694         filter_replace.old_filter_type =
12695                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12696         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12697         filter_replace.tr_bit = 0;
12698
12699         /* Prepare the buffer, 2 entries */
12700         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12701         filter_replace_buf.data[0] |=
12702                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12703         /* Field Vector 12b mask */
12704         filter_replace_buf.data[2] = 0xff;
12705         filter_replace_buf.data[3] = 0x0f;
12706         filter_replace_buf.data[4] =
12707                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12708         filter_replace_buf.data[4] |=
12709                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12710         /* Field Vector 12b mask */
12711         filter_replace_buf.data[6] = 0xff;
12712         filter_replace_buf.data[7] = 0x0f;
12713         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12714                         &filter_replace_buf);
12715         if (ret != I40E_SUCCESS)
12716                 return ret;
12717
12718         if (filter_replace.old_filter_type !=
12719             filter_replace.new_filter_type)
12720                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12721                             " original: 0x%x, new: 0x%x",
12722                             dev->device->name,
12723                             filter_replace.old_filter_type,
12724                             filter_replace.new_filter_type);
12725
12726         /* Apply the second L2 cloud filter */
12727         memset(&filter_replace, 0,
12728                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12729         memset(&filter_replace_buf, 0,
12730                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12731
12732         /* create L2 filter, input for L2 filter will be L1 filter  */
12733         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12734         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12735         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12736
12737         /* Prepare the buffer, 2 entries */
12738         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12739         filter_replace_buf.data[0] |=
12740                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12741         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12742         filter_replace_buf.data[4] |=
12743                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12744         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12745                         &filter_replace_buf);
12746         if (!ret && (filter_replace.old_filter_type !=
12747                      filter_replace.new_filter_type))
12748                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12749                             " original: 0x%x, new: 0x%x",
12750                             dev->device->name,
12751                             filter_replace.old_filter_type,
12752                             filter_replace.new_filter_type);
12753
12754         return ret;
12755 }
12756
12757 int
12758 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12759                    const struct rte_flow_action_rss *in)
12760 {
12761         if (in->key_len > RTE_DIM(out->key) ||
12762             in->queue_num > RTE_DIM(out->queue))
12763                 return -EINVAL;
12764         if (!in->key && in->key_len)
12765                 return -EINVAL;
12766         out->conf = (struct rte_flow_action_rss){
12767                 .func = in->func,
12768                 .level = in->level,
12769                 .types = in->types,
12770                 .key_len = in->key_len,
12771                 .queue_num = in->queue_num,
12772                 .queue = memcpy(out->queue, in->queue,
12773                                 sizeof(*in->queue) * in->queue_num),
12774         };
12775         if (in->key)
12776                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12777         return 0;
12778 }
12779
12780 int
12781 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12782                      const struct rte_flow_action_rss *with)
12783 {
12784         return (comp->func == with->func &&
12785                 comp->level == with->level &&
12786                 comp->types == with->types &&
12787                 comp->key_len == with->key_len &&
12788                 comp->queue_num == with->queue_num &&
12789                 !memcmp(comp->key, with->key, with->key_len) &&
12790                 !memcmp(comp->queue, with->queue,
12791                         sizeof(*with->queue) * with->queue_num));
12792 }
12793
12794 int
12795 i40e_config_rss_filter(struct i40e_pf *pf,
12796                 struct i40e_rte_flow_rss_conf *conf, bool add)
12797 {
12798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12799         uint32_t i, lut = 0;
12800         uint16_t j, num;
12801         struct rte_eth_rss_conf rss_conf = {
12802                 .rss_key = conf->conf.key_len ?
12803                         (void *)(uintptr_t)conf->conf.key : NULL,
12804                 .rss_key_len = conf->conf.key_len,
12805                 .rss_hf = conf->conf.types,
12806         };
12807         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12808
12809         if (!add) {
12810                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12811                         i40e_pf_disable_rss(pf);
12812                         memset(rss_info, 0,
12813                                 sizeof(struct i40e_rte_flow_rss_conf));
12814                         return 0;
12815                 }
12816                 return -EINVAL;
12817         }
12818
12819         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12820          * It's necessary to calculate the actual PF queues that are configured.
12821          */
12822         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12823                 num = i40e_pf_calc_configured_queues_num(pf);
12824         else
12825                 num = pf->dev_data->nb_rx_queues;
12826
12827         num = RTE_MIN(num, conf->conf.queue_num);
12828         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12829                         num);
12830
12831         if (num == 0) {
12832                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12833                 return -ENOTSUP;
12834         }
12835
12836         /* Fill in redirection table */
12837         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12838                 if (j == num)
12839                         j = 0;
12840                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12841                         hw->func_caps.rss_table_entry_width) - 1));
12842                 if ((i & 3) == 3)
12843                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12844         }
12845
12846         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12847                 i40e_pf_disable_rss(pf);
12848                 return 0;
12849         }
12850         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12851                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12852                 /* Random default keys */
12853                 static uint32_t rss_key_default[] = {0x6b793944,
12854                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12855                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12856                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12857
12858                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12859                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12860                                                         sizeof(uint32_t);
12861                 PMD_DRV_LOG(INFO,
12862                         "No valid RSS key config for i40e, using default\n");
12863         }
12864
12865         i40e_hw_rss_hash_set(pf, &rss_conf);
12866
12867         if (i40e_rss_conf_init(rss_info, &conf->conf))
12868                 return -EINVAL;
12869
12870         return 0;
12871 }
12872
12873 RTE_INIT(i40e_init_log)
12874 {
12875         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12876         if (i40e_logtype_init >= 0)
12877                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12878         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12879         if (i40e_logtype_driver >= 0)
12880                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12881
12882 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12883         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12884         if (i40e_logtype_rx >= 0)
12885                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12886 #endif
12887
12888 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12889         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12890         if (i40e_logtype_tx >= 0)
12891                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12892 #endif
12893
12894 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12895         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12896         if (i40e_logtype_tx_free >= 0)
12897                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12898 #endif
12899 }
12900
12901 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12902                               ETH_I40E_FLOATING_VEB_ARG "=1"
12903                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12904                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12905                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12906                               ETH_I40E_USE_LATEST_VEC "=0|1");