drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51
  52 /* Maximun number of capability elements */
  53 #define I40E_MAX_CAP_ELE_NUM       128
  54
  55 /* Wait count and interval */
  56 #define I40E_CHK_Q_ENA_COUNT       1000
  57 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  58
  59 /* Maximun number of VSI */
  60 #define I40E_MAX_NUM_VSIS          (384UL)
  61
  62 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  63
  64 /* Flow control default timer */
  65 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  66
  67 /* Flow control enable fwd bit */
  68 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  69
  70 /* Receive Packet Buffer size */
  71 #define I40E_RXPBSIZE (968 * 1024)
  72
  73 /* Kilobytes shift */
  74 #define I40E_KILOSHIFT 10
  75
  76 /* Flow control default high water */
  77 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  78
  79 /* Flow control default low water */
  80 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Receive Average Packet Size in Byte*/
  83 #define I40E_PACKET_AVERAGE_SIZE 128
  84
  85 /* Mask of PF interrupt causes */
  86 #define I40E_PFINT_ICR0_ENA_MASK ( \
  87                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  89                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  90                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  91                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 /* Additional timesync values. */
 111 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 112 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 113 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 114 #define I40E_PRTTSYN_TSYNENA     0x80000000
 115 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 116 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 /**
 119  * Below are values for writing un-exposed registers suggested
 120  * by silicon experts
 121  */
 122 /* Destination MAC address */
 123 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 124 /* Source MAC address */
 125 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 126 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 128 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 130 /* Single VLAN tag in the inner L2 header */
 131 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 132 /* Source IPv4 address */
 133 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 134 /* Destination IPv4 address */
 135 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 136 /* Source IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 138 /* Destination IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 140 /* IPv4 Protocol for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 142 /* IPv4 Time to Live for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 144 /* IPv4 Type of Service (TOS) */
 145 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 146 /* IPv4 Protocol */
 147 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 148 /* IPv4 Time to Live */
 149 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 150 /* Source IPv6 address */
 151 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 152 /* Destination IPv6 address */
 153 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 154 /* IPv6 Traffic Class (TC) */
 155 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 156 /* IPv6 Next Header */
 157 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 158 /* IPv6 Hop Limit */
 159 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 160 /* Source L4 port */
 161 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 162 /* Destination L4 port */
 163 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 164 /* SCTP verification tag */
 165 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 166 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 167 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 168 /* Source port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 170 /* Destination port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 172 /* UDP Tunneling ID, NVGRE/GRE key */
 173 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 174 /* Last ether type */
 175 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 176 /* Tunneling outer destination IPv4 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 178 /* Tunneling outer destination IPv6 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 180 /* 1st word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 182 /* 2nd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 184 /* 3rd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 186 /* 4th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 188 /* 5th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 190 /* 6th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 192 /* 7th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 194 /* 8th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 196 /* all 8 words flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 198 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 199
 200 #define I40E_TRANSLATE_INSET 0
 201 #define I40E_TRANSLATE_REG   1
 202
 203 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 204 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 205 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 206 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 207 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 208 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 209
 210 /* PCI offset for querying capability */
 211 #define PCI_DEV_CAP_REG            0xA4
 212 /* PCI offset for enabling/disabling Extended Tag */
 213 #define PCI_DEV_CTRL_REG           0xA8
 214 /* Bit mask of Extended Tag capability */
 215 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 216 /* Bit shift of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 218 /* Bit mask of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 220
 221 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 222 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 223 static int i40e_dev_configure(struct rte_eth_dev *dev);
 224 static int i40e_dev_start(struct rte_eth_dev *dev);
 225 static void i40e_dev_stop(struct rte_eth_dev *dev);
 226 static void i40e_dev_close(struct rte_eth_dev *dev);
 227 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 229 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 233 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 234 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_stats *stats);
 236 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_xstat *xstats, unsigned n);
 238 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 239                                      struct rte_eth_xstat_name *xstats_names,
 240                                      unsigned limit);
 241 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 245                              struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct rte_ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static void i40e_dev_alarm_handler(void *param);
 294 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 295                                 uint32_t base, uint32_t num);
 296 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 297 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 298                         uint32_t base);
 299 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 300                         uint16_t num);
 301 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 302 static int i40e_veb_release(struct i40e_veb *veb);
 303 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 304                                                 struct i40e_vsi *vsi);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400 static int i40e_pf_config_rss(struct i40e_pf *pf);
 401
 402 static const char *const valid_keys[] = {
 403         ETH_I40E_FLOATING_VEB_ARG,
 404         ETH_I40E_FLOATING_VEB_LIST_ARG,
 405         ETH_I40E_SUPPORT_MULTI_DRIVER,
 406         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 407         ETH_I40E_USE_LATEST_VEC,
 408         ETH_I40E_VF_MSG_CFG,
 409         NULL};
 410
 411 static const struct rte_pci_id pci_id_i40e_map[] = {
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 438         { .vendor_id = 0, /* sentinel */ },
 439 };
 440
 441 static const struct eth_dev_ops i40e_eth_dev_ops = {
 442         .dev_configure                = i40e_dev_configure,
 443         .dev_start                    = i40e_dev_start,
 444         .dev_stop                     = i40e_dev_stop,
 445         .dev_close                    = i40e_dev_close,
 446         .dev_reset                    = i40e_dev_reset,
 447         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 448         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 449         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 450         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 451         .dev_set_link_up              = i40e_dev_set_link_up,
 452         .dev_set_link_down            = i40e_dev_set_link_down,
 453         .link_update                  = i40e_dev_link_update,
 454         .stats_get                    = i40e_dev_stats_get,
 455         .xstats_get                   = i40e_dev_xstats_get,
 456         .xstats_get_names             = i40e_dev_xstats_get_names,
 457         .stats_reset                  = i40e_dev_stats_reset,
 458         .xstats_reset                 = i40e_dev_stats_reset,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 498         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517         .tx_done_cleanup              = i40e_tx_done_cleanup,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int
 634 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         char name[RTE_ETH_NAME_MAX_LEN];
 638         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 639         int i, retval;
 640
 641         if (pci_dev->device.devargs) {
 642                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 643                                 &eth_da);
 644                 if (retval)
 645                         return retval;
 646         }
 647
 648         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 649                 sizeof(struct i40e_adapter),
 650                 eth_dev_pci_specific_init, pci_dev,
 651                 eth_i40e_dev_init, NULL);
 652
 653         if (retval || eth_da.nb_representor_ports < 1)
 654                 return retval;
 655
 656         /* probe VF representor ports */
 657         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 658                 pci_dev->device.name);
 659
 660         if (pf_ethdev == NULL)
 661                 return -ENODEV;
 662
 663         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 664                 struct i40e_vf_representor representor = {
 665                         .vf_id = eth_da.representor_ports[i],
 666                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 667                                 pf_ethdev->data->dev_private)->switch_domain_id,
 668                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 669                                 pf_ethdev->data->dev_private)
 670                 };
 671
 672                 /* representor port net_bdf_port */
 673                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 674                         pci_dev->device.name, eth_da.representor_ports[i]);
 675
 676                 retval = rte_eth_dev_create(&pci_dev->device, name,
 677                         sizeof(struct i40e_vf_representor), NULL, NULL,
 678                         i40e_vf_representor_init, &representor);
 679
 680                 if (retval)
 681                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 682                                 "representor %s.", name);
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 689 {
 690         struct rte_eth_dev *ethdev;
 691
 692         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 693         if (!ethdev)
 694                 return 0;
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_pci_generic_remove(pci_dev,
 698                                         i40e_vf_representor_uninit);
 699         else
 700                 return rte_eth_dev_pci_generic_remove(pci_dev,
 701                                                 eth_i40e_dev_uninit);
 702 }
 703
 704 static struct rte_pci_driver rte_i40e_pmd = {
 705         .id_table = pci_id_i40e_map,
 706         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 707         .probe = eth_i40e_pci_probe,
 708         .remove = eth_i40e_pci_remove,
 709 };
 710
 711 static inline void
 712 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 713                          uint32_t reg_val)
 714 {
 715         uint32_t ori_reg_val;
 716         struct rte_eth_dev *dev;
 717
 718         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 719         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 720         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 721         if (ori_reg_val != reg_val)
 722                 PMD_DRV_LOG(WARNING,
 723                             "i40e device %s changed global register [0x%08x]."
 724                             " original: 0x%08x, new: 0x%08x",
 725                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 731
 732 #ifndef I40E_GLQF_ORT
 733 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_PIT
 736 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 737 #endif
 738 #ifndef I40E_GLQF_L3_MAP
 739 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 740 #endif
 741
 742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 743 {
 744         /*
 745          * Initialize registers for parsing packet type of QinQ
 746          * This should be removed from code once proper
 747          * configuration API is added to avoid configuration conflicts
 748          * between ports of the same device.
 749          */
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 751         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 752 }
 753
 754 static inline void i40e_config_automask(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint32_t val;
 758
 759         /* INTENA flag is not auto-cleared for interrupt */
 760         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 761         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 762                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 763
 764         /* If support multi-driver, PF will use INT0. */
 765         if (!pf->support_multi_driver)
 766                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 767
 768         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 769 }
 770
 771 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 772
 773 /*
 774  * Add a ethertype filter to drop all flow control frames transmitted
 775  * from VSIs.
 776 */
 777 static void
 778 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 779 {
 780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 781         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 783                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 784         int ret;
 785
 786         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 787                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 788                                 pf->main_vsi_seid, 0,
 789                                 TRUE, NULL, NULL);
 790         if (ret)
 791                 PMD_INIT_LOG(ERR,
 792                         "Failed to add filter to drop flow control frames from VSIs.");
 793 }
 794
 795 static int
 796 floating_veb_list_handler(__rte_unused const char *key,
 797                           const char *floating_veb_value,
 798                           void *opaque)
 799 {
 800         int idx = 0;
 801         unsigned int count = 0;
 802         char *end = NULL;
 803         int min, max;
 804         bool *vf_floating_veb = opaque;
 805
 806         while (isblank(*floating_veb_value))
 807                 floating_veb_value++;
 808
 809         /* Reset floating VEB configuration for VFs */
 810         for (idx = 0; idx < I40E_MAX_VF; idx++)
 811                 vf_floating_veb[idx] = false;
 812
 813         min = I40E_MAX_VF;
 814         do {
 815                 while (isblank(*floating_veb_value))
 816                         floating_veb_value++;
 817                 if (*floating_veb_value == '\0')
 818                         return -1;
 819                 errno = 0;
 820                 idx = strtoul(floating_veb_value, &end, 10);
 821                 if (errno || end == NULL)
 822                         return -1;
 823                 while (isblank(*end))
 824                         end++;
 825                 if (*end == '-') {
 826                         min = idx;
 827                 } else if ((*end == ';') || (*end == '\0')) {
 828                         max = idx;
 829                         if (min == I40E_MAX_VF)
 830                                 min = idx;
 831                         if (max >= I40E_MAX_VF)
 832                                 max = I40E_MAX_VF - 1;
 833                         for (idx = min; idx <= max; idx++) {
 834                                 vf_floating_veb[idx] = true;
 835                                 count++;
 836                         }
 837                         min = I40E_MAX_VF;
 838                 } else {
 839                         return -1;
 840                 }
 841                 floating_veb_value = end + 1;
 842         } while (*end != '\0');
 843
 844         if (count == 0)
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static void
 851 config_vf_floating_veb(struct rte_devargs *devargs,
 852                        uint16_t floating_veb,
 853                        bool *vf_floating_veb)
 854 {
 855         struct rte_kvargs *kvlist;
 856         int i;
 857         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 858
 859         if (!floating_veb)
 860                 return;
 861         /* All the VFs attach to the floating VEB by default
 862          * when the floating VEB is enabled.
 863          */
 864         for (i = 0; i < I40E_MAX_VF; i++)
 865                 vf_floating_veb[i] = true;
 866
 867         if (devargs == NULL)
 868                 return;
 869
 870         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 871         if (kvlist == NULL)
 872                 return;
 873
 874         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 875                 rte_kvargs_free(kvlist);
 876                 return;
 877         }
 878         /* When the floating_veb_list parameter exists, all the VFs
 879          * will attach to the legacy VEB firstly, then configure VFs
 880          * to the floating VEB according to the floating_veb_list.
 881          */
 882         if (rte_kvargs_process(kvlist, floating_veb_list,
 883                                floating_veb_list_handler,
 884                                vf_floating_veb) < 0) {
 885                 rte_kvargs_free(kvlist);
 886                 return;
 887         }
 888         rte_kvargs_free(kvlist);
 889 }
 890
 891 static int
 892 i40e_check_floating_handler(__rte_unused const char *key,
 893                             const char *value,
 894                             __rte_unused void *opaque)
 895 {
 896         if (strcmp(value, "1"))
 897                 return -1;
 898
 899         return 0;
 900 }
 901
 902 static int
 903 is_floating_veb_supported(struct rte_devargs *devargs)
 904 {
 905         struct rte_kvargs *kvlist;
 906         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 907
 908         if (devargs == NULL)
 909                 return 0;
 910
 911         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 912         if (kvlist == NULL)
 913                 return 0;
 914
 915         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 916                 rte_kvargs_free(kvlist);
 917                 return 0;
 918         }
 919         /* Floating VEB is enabled when there's key-value:
 920          * enable_floating_veb=1
 921          */
 922         if (rte_kvargs_process(kvlist, floating_veb_key,
 923                                i40e_check_floating_handler, NULL) < 0) {
 924                 rte_kvargs_free(kvlist);
 925                 return 0;
 926         }
 927         rte_kvargs_free(kvlist);
 928
 929         return 1;
 930 }
 931
 932 static void
 933 config_floating_veb(struct rte_eth_dev *dev)
 934 {
 935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938
 939         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 940
 941         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 942                 pf->floating_veb =
 943                         is_floating_veb_supported(pci_dev->device.devargs);
 944                 config_vf_floating_veb(pci_dev->device.devargs,
 945                                        pf->floating_veb,
 946                                        pf->floating_veb_list);
 947         } else {
 948                 pf->floating_veb = false;
 949         }
 950 }
 951
 952 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 953 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 954
 955 static int
 956 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 957 {
 958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 959         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 960         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 961         int ret;
 962
 963         struct rte_hash_parameters ethertype_hash_params = {
 964                 .name = ethertype_hash_name,
 965                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 966                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 967                 .hash_func = rte_hash_crc,
 968                 .hash_func_init_val = 0,
 969                 .socket_id = rte_socket_id(),
 970         };
 971
 972         /* Initialize ethertype filter rule list and hash */
 973         TAILQ_INIT(&ethertype_rule->ethertype_list);
 974         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 975                  "ethertype_%s", dev->device->name);
 976         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 977         if (!ethertype_rule->hash_table) {
 978                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 979                 return -EINVAL;
 980         }
 981         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 982                                        sizeof(struct i40e_ethertype_filter *) *
 983                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 984                                        0);
 985         if (!ethertype_rule->hash_map) {
 986                 PMD_INIT_LOG(ERR,
 987                              "Failed to allocate memory for ethertype hash map!");
 988                 ret = -ENOMEM;
 989                 goto err_ethertype_hash_map_alloc;
 990         }
 991
 992         return 0;
 993
 994 err_ethertype_hash_map_alloc:
 995         rte_hash_free(ethertype_rule->hash_table);
 996
 997         return ret;
 998 }
 999
1000 static int
1001 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 {
1003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1005         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006         int ret;
1007
1008         struct rte_hash_parameters tunnel_hash_params = {
1009                 .name = tunnel_hash_name,
1010                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1011                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1012                 .hash_func = rte_hash_crc,
1013                 .hash_func_init_val = 0,
1014                 .socket_id = rte_socket_id(),
1015         };
1016
1017         /* Initialize tunnel filter rule list and hash */
1018         TAILQ_INIT(&tunnel_rule->tunnel_list);
1019         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1020                  "tunnel_%s", dev->device->name);
1021         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1022         if (!tunnel_rule->hash_table) {
1023                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024                 return -EINVAL;
1025         }
1026         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1027                                     sizeof(struct i40e_tunnel_filter *) *
1028                                     I40E_MAX_TUNNEL_FILTER_NUM,
1029                                     0);
1030         if (!tunnel_rule->hash_map) {
1031                 PMD_INIT_LOG(ERR,
1032                              "Failed to allocate memory for tunnel hash map!");
1033                 ret = -ENOMEM;
1034                 goto err_tunnel_hash_map_alloc;
1035         }
1036
1037         return 0;
1038
1039 err_tunnel_hash_map_alloc:
1040         rte_hash_free(tunnel_rule->hash_table);
1041
1042         return ret;
1043 }
1044
1045 static int
1046 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1050         struct i40e_fdir_info *fdir_info = &pf->fdir;
1051         char fdir_hash_name[RTE_HASH_NAMESIZE];
1052         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1053         uint32_t best = hw->func_caps.fd_filters_best_effort;
1054         struct rte_bitmap *bmp = NULL;
1055         uint32_t bmp_size;
1056         void *mem = NULL;
1057         uint32_t i = 0;
1058         int ret;
1059
1060         struct rte_hash_parameters fdir_hash_params = {
1061                 .name = fdir_hash_name,
1062                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1063                 .key_len = sizeof(struct i40e_fdir_input),
1064                 .hash_func = rte_hash_crc,
1065                 .hash_func_init_val = 0,
1066                 .socket_id = rte_socket_id(),
1067         };
1068
1069         /* Initialize flow director filter rule list and hash */
1070         TAILQ_INIT(&fdir_info->fdir_list);
1071         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1072                  "fdir_%s", dev->device->name);
1073         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1074         if (!fdir_info->hash_table) {
1075                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1076                 return -EINVAL;
1077         }
1078
1079         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1080                                           sizeof(struct i40e_fdir_filter *) *
1081                                           I40E_MAX_FDIR_FILTER_NUM,
1082                                           0);
1083         if (!fdir_info->hash_map) {
1084                 PMD_INIT_LOG(ERR,
1085                              "Failed to allocate memory for fdir hash map!");
1086                 ret = -ENOMEM;
1087                 goto err_fdir_hash_map_alloc;
1088         }
1089
1090         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1091                         sizeof(struct i40e_fdir_filter) *
1092                         I40E_MAX_FDIR_FILTER_NUM,
1093                         0);
1094
1095         if (!fdir_info->fdir_filter_array) {
1096                 PMD_INIT_LOG(ERR,
1097                              "Failed to allocate memory for fdir filter array!");
1098                 ret = -ENOMEM;
1099                 goto err_fdir_filter_array_alloc;
1100         }
1101
1102         fdir_info->fdir_space_size = alloc + best;
1103         fdir_info->fdir_actual_cnt = 0;
1104         fdir_info->fdir_guarantee_total_space = alloc;
1105         fdir_info->fdir_guarantee_free_space =
1106                 fdir_info->fdir_guarantee_total_space;
1107
1108         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1109
1110         fdir_info->fdir_flow_pool.pool =
1111                         rte_zmalloc("i40e_fdir_entry",
1112                                 sizeof(struct i40e_fdir_entry) *
1113                                 fdir_info->fdir_space_size,
1114                                 0);
1115
1116         if (!fdir_info->fdir_flow_pool.pool) {
1117                 PMD_INIT_LOG(ERR,
1118                              "Failed to allocate memory for bitmap flow!");
1119                 ret = -ENOMEM;
1120                 goto err_fdir_bitmap_flow_alloc;
1121         }
1122
1123         for (i = 0; i < fdir_info->fdir_space_size; i++)
1124                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1125
1126         bmp_size =
1127                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1128         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1129         if (mem == NULL) {
1130                 PMD_INIT_LOG(ERR,
1131                              "Failed to allocate memory for fdir bitmap!");
1132                 ret = -ENOMEM;
1133                 goto err_fdir_mem_alloc;
1134         }
1135         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1136         if (bmp == NULL) {
1137                 PMD_INIT_LOG(ERR,
1138                              "Failed to initialization fdir bitmap!");
1139                 ret = -ENOMEM;
1140                 goto err_fdir_bmp_alloc;
1141         }
1142         for (i = 0; i < fdir_info->fdir_space_size; i++)
1143                 rte_bitmap_set(bmp, i);
1144
1145         fdir_info->fdir_flow_pool.bitmap = bmp;
1146
1147         return 0;
1148
1149 err_fdir_bmp_alloc:
1150         rte_free(mem);
1151 err_fdir_mem_alloc:
1152         rte_free(fdir_info->fdir_flow_pool.pool);
1153 err_fdir_bitmap_flow_alloc:
1154         rte_free(fdir_info->fdir_filter_array);
1155 err_fdir_filter_array_alloc:
1156         rte_free(fdir_info->hash_map);
1157 err_fdir_hash_map_alloc:
1158         rte_hash_free(fdir_info->hash_table);
1159
1160         return ret;
1161 }
1162
1163 static void
1164 i40e_init_customized_info(struct i40e_pf *pf)
1165 {
1166         int i;
1167
1168         /* Initialize customized pctype */
1169         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1170                 pf->customized_pctype[i].index = i;
1171                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1172                 pf->customized_pctype[i].valid = false;
1173         }
1174
1175         pf->gtp_support = false;
1176         pf->esp_support = false;
1177 }
1178
1179 static void
1180 i40e_init_filter_invalidation(struct i40e_pf *pf)
1181 {
1182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1183         struct i40e_fdir_info *fdir_info = &pf->fdir;
1184         uint32_t glqf_ctl_reg = 0;
1185
1186         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1187         if (!pf->support_multi_driver) {
1188                 fdir_info->fdir_invalprio = 1;
1189                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1190                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1191                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1192         } else {
1193                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1194                         fdir_info->fdir_invalprio = 1;
1195                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1196                 } else {
1197                         fdir_info->fdir_invalprio = 0;
1198                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1199                 }
1200         }
1201 }
1202
1203 void
1204 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1205 {
1206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1208         struct i40e_queue_regions *info = &pf->queue_region;
1209         uint16_t i;
1210
1211         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1212                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1213
1214         memset(info, 0, sizeof(struct i40e_queue_regions));
1215 }
1216
1217 static int
1218 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1219                                const char *value,
1220                                void *opaque)
1221 {
1222         struct i40e_pf *pf;
1223         unsigned long support_multi_driver;
1224         char *end;
1225
1226         pf = (struct i40e_pf *)opaque;
1227
1228         errno = 0;
1229         support_multi_driver = strtoul(value, &end, 10);
1230         if (errno != 0 || end == value || *end != 0) {
1231                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1232                 return -(EINVAL);
1233         }
1234
1235         if (support_multi_driver == 1 || support_multi_driver == 0)
1236                 pf->support_multi_driver = (bool)support_multi_driver;
1237         else
1238                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1239                             "enable global configuration by default."
1240                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1241         return 0;
1242 }
1243
1244 static int
1245 i40e_support_multi_driver(struct rte_eth_dev *dev)
1246 {
1247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1248         struct rte_kvargs *kvlist;
1249         int kvargs_count;
1250
1251         /* Enable global configuration by default */
1252         pf->support_multi_driver = false;
1253
1254         if (!dev->device->devargs)
1255                 return 0;
1256
1257         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1258         if (!kvlist)
1259                 return -EINVAL;
1260
1261         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1262         if (!kvargs_count) {
1263                 rte_kvargs_free(kvlist);
1264                 return 0;
1265         }
1266
1267         if (kvargs_count > 1)
1268                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1269                             "the first invalid or last valid one is used !",
1270                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1271
1272         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1273                                i40e_parse_multi_drv_handler, pf) < 0) {
1274                 rte_kvargs_free(kvlist);
1275                 return -EINVAL;
1276         }
1277
1278         rte_kvargs_free(kvlist);
1279         return 0;
1280 }
1281
1282 static int
1283 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1284                                     uint32_t reg_addr, uint64_t reg_val,
1285                                     struct i40e_asq_cmd_details *cmd_details)
1286 {
1287         uint64_t ori_reg_val;
1288         struct rte_eth_dev *dev;
1289         int ret;
1290
1291         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1292         if (ret != I40E_SUCCESS) {
1293                 PMD_DRV_LOG(ERR,
1294                             "Fail to debug read from 0x%08x",
1295                             reg_addr);
1296                 return -EIO;
1297         }
1298         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1299
1300         if (ori_reg_val != reg_val)
1301                 PMD_DRV_LOG(WARNING,
1302                             "i40e device %s changed global register [0x%08x]."
1303                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1304                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1305
1306         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1307 }
1308
1309 static int
1310 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1311                                 const char *value,
1312                                 void *opaque)
1313 {
1314         struct i40e_adapter *ad = opaque;
1315         int use_latest_vec;
1316
1317         use_latest_vec = atoi(value);
1318
1319         if (use_latest_vec != 0 && use_latest_vec != 1)
1320                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1321
1322         ad->use_latest_vec = (uint8_t)use_latest_vec;
1323
1324         return 0;
1325 }
1326
1327 static int
1328 i40e_use_latest_vec(struct rte_eth_dev *dev)
1329 {
1330         struct i40e_adapter *ad =
1331                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1332         struct rte_kvargs *kvlist;
1333         int kvargs_count;
1334
1335         ad->use_latest_vec = false;
1336
1337         if (!dev->device->devargs)
1338                 return 0;
1339
1340         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1341         if (!kvlist)
1342                 return -EINVAL;
1343
1344         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1345         if (!kvargs_count) {
1346                 rte_kvargs_free(kvlist);
1347                 return 0;
1348         }
1349
1350         if (kvargs_count > 1)
1351                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1352                             "the first invalid or last valid one is used !",
1353                             ETH_I40E_USE_LATEST_VEC);
1354
1355         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1356                                 i40e_parse_latest_vec_handler, ad) < 0) {
1357                 rte_kvargs_free(kvlist);
1358                 return -EINVAL;
1359         }
1360
1361         rte_kvargs_free(kvlist);
1362         return 0;
1363 }
1364
1365 static int
1366 read_vf_msg_config(__rte_unused const char *key,
1367                                const char *value,
1368                                void *opaque)
1369 {
1370         struct i40e_vf_msg_cfg *cfg = opaque;
1371
1372         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1373                         &cfg->ignore_second) != 3) {
1374                 memset(cfg, 0, sizeof(*cfg));
1375                 PMD_DRV_LOG(ERR, "format error! example: "
1376                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1377                 return -EINVAL;
1378         }
1379
1380         /*
1381          * If the message validation function been enabled, the 'period'
1382          * and 'ignore_second' must greater than 0.
1383          */
1384         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1385                 memset(cfg, 0, sizeof(*cfg));
1386                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1387                                 " number must be greater than 0!",
1388                                 ETH_I40E_VF_MSG_CFG);
1389                 return -EINVAL;
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int
1396 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1397                 struct i40e_vf_msg_cfg *msg_cfg)
1398 {
1399         struct rte_kvargs *kvlist;
1400         int kvargs_count;
1401         int ret = 0;
1402
1403         memset(msg_cfg, 0, sizeof(*msg_cfg));
1404
1405         if (!dev->device->devargs)
1406                 return ret;
1407
1408         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1409         if (!kvlist)
1410                 return -EINVAL;
1411
1412         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1413         if (!kvargs_count)
1414                 goto free_end;
1415
1416         if (kvargs_count > 1) {
1417                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1418                                 ETH_I40E_VF_MSG_CFG);
1419                 ret = -EINVAL;
1420                 goto free_end;
1421         }
1422
1423         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1424                         read_vf_msg_config, msg_cfg) < 0)
1425                 ret = -EINVAL;
1426
1427 free_end:
1428         rte_kvargs_free(kvlist);
1429         return ret;
1430 }
1431
1432 #define I40E_ALARM_INTERVAL 50000 /* us */
1433
1434 static int
1435 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1436 {
1437         struct rte_pci_device *pci_dev;
1438         struct rte_intr_handle *intr_handle;
1439         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1441         struct i40e_vsi *vsi;
1442         int ret;
1443         uint32_t len, val;
1444         uint8_t aq_fail = 0;
1445
1446         PMD_INIT_FUNC_TRACE();
1447
1448         dev->dev_ops = &i40e_eth_dev_ops;
1449         dev->rx_pkt_burst = i40e_recv_pkts;
1450         dev->tx_pkt_burst = i40e_xmit_pkts;
1451         dev->tx_pkt_prepare = i40e_prep_pkts;
1452
1453         /* for secondary processes, we don't initialise any further as primary
1454          * has already done this work. Only check we don't need a different
1455          * RX function */
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457                 i40e_set_rx_function(dev);
1458                 i40e_set_tx_function(dev);
1459                 return 0;
1460         }
1461         i40e_set_default_ptype_table(dev);
1462         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463         intr_handle = &pci_dev->intr_handle;
1464
1465         rte_eth_copy_pci_info(dev, pci_dev);
1466
1467         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1468         pf->adapter->eth_dev = dev;
1469         pf->dev_data = dev->data;
1470
1471         hw->back = I40E_PF_TO_ADAPTER(pf);
1472         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1473         if (!hw->hw_addr) {
1474                 PMD_INIT_LOG(ERR,
1475                         "Hardware is not available, as address is NULL");
1476                 return -ENODEV;
1477         }
1478
1479         hw->vendor_id = pci_dev->id.vendor_id;
1480         hw->device_id = pci_dev->id.device_id;
1481         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1482         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1483         hw->bus.device = pci_dev->addr.devid;
1484         hw->bus.func = pci_dev->addr.function;
1485         hw->adapter_stopped = 0;
1486         hw->adapter_closed = 0;
1487
1488         /* Init switch device pointer */
1489         hw->switch_dev = NULL;
1490
1491         /*
1492          * Switch Tag value should not be identical to either the First Tag
1493          * or Second Tag values. So set something other than common Ethertype
1494          * for internal switching.
1495          */
1496         hw->switch_tag = 0xffff;
1497
1498         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1499         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1500                 PMD_INIT_LOG(ERR, "\nERROR: "
1501                         "Firmware recovery mode detected. Limiting functionality.\n"
1502                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1503                         "User Guide for details on firmware recovery mode.");
1504                 return -EIO;
1505         }
1506
1507         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1508         /* Check if need to support multi-driver */
1509         i40e_support_multi_driver(dev);
1510         /* Check if users want the latest supported vec path */
1511         i40e_use_latest_vec(dev);
1512
1513         /* Make sure all is clean before doing PF reset */
1514         i40e_clear_hw(hw);
1515
1516         /* Reset here to make sure all is clean for each PF */
1517         ret = i40e_pf_reset(hw);
1518         if (ret) {
1519                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1520                 return ret;
1521         }
1522
1523         /* Initialize the shared code (base driver) */
1524         ret = i40e_init_shared_code(hw);
1525         if (ret) {
1526                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1527                 return ret;
1528         }
1529
1530         /* Initialize the parameters for adminq */
1531         i40e_init_adminq_parameter(hw);
1532         ret = i40e_init_adminq(hw);
1533         if (ret != I40E_SUCCESS) {
1534                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1535                 return -EIO;
1536         }
1537         /* Firmware of SFP x722 does not support adminq option */
1538         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1539                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1540
1541         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1542                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1543                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1544                      ((hw->nvm.version >> 12) & 0xf),
1545                      ((hw->nvm.version >> 4) & 0xff),
1546                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1547
1548         /* Initialize the hardware */
1549         i40e_hw_init(dev);
1550
1551         i40e_config_automask(pf);
1552
1553         i40e_set_default_pctype_table(dev);
1554
1555         /*
1556          * To work around the NVM issue, initialize registers
1557          * for packet type of QinQ by software.
1558          * It should be removed once issues are fixed in NVM.
1559          */
1560         if (!pf->support_multi_driver)
1561                 i40e_GLQF_reg_init(hw);
1562
1563         /* Initialize the input set for filters (hash and fd) to default value */
1564         i40e_filter_input_set_init(pf);
1565
1566         /* initialise the L3_MAP register */
1567         if (!pf->support_multi_driver) {
1568                 ret = i40e_aq_debug_write_global_register(hw,
1569                                                    I40E_GLQF_L3_MAP(40),
1570                                                    0x00000028,  NULL);
1571                 if (ret)
1572                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1573                                      ret);
1574                 PMD_INIT_LOG(DEBUG,
1575                              "Global register 0x%08x is changed with 0x28",
1576                              I40E_GLQF_L3_MAP(40));
1577         }
1578
1579         /* Need the special FW version to support floating VEB */
1580         config_floating_veb(dev);
1581         /* Clear PXE mode */
1582         i40e_clear_pxe_mode(hw);
1583         i40e_dev_sync_phy_type(hw);
1584
1585         /*
1586          * On X710, performance number is far from the expectation on recent
1587          * firmware versions. The fix for this issue may not be integrated in
1588          * the following firmware version. So the workaround in software driver
1589          * is needed. It needs to modify the initial values of 3 internal only
1590          * registers. Note that the workaround can be removed when it is fixed
1591          * in firmware in the future.
1592          */
1593         i40e_configure_registers(hw);
1594
1595         /* Get hw capabilities */
1596         ret = i40e_get_cap(hw);
1597         if (ret != I40E_SUCCESS) {
1598                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1599                 goto err_get_capabilities;
1600         }
1601
1602         /* Initialize parameters for PF */
1603         ret = i40e_pf_parameter_init(dev);
1604         if (ret != 0) {
1605                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1606                 goto err_parameter_init;
1607         }
1608
1609         /* Initialize the queue management */
1610         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1611         if (ret < 0) {
1612                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1613                 goto err_qp_pool_init;
1614         }
1615         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1616                                 hw->func_caps.num_msix_vectors - 1);
1617         if (ret < 0) {
1618                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1619                 goto err_msix_pool_init;
1620         }
1621
1622         /* Initialize lan hmc */
1623         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1624                                 hw->func_caps.num_rx_qp, 0, 0);
1625         if (ret != I40E_SUCCESS) {
1626                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1627                 goto err_init_lan_hmc;
1628         }
1629
1630         /* Configure lan hmc */
1631         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1632         if (ret != I40E_SUCCESS) {
1633                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1634                 goto err_configure_lan_hmc;
1635         }
1636
1637         /* Get and check the mac address */
1638         i40e_get_mac_addr(hw, hw->mac.addr);
1639         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1640                 PMD_INIT_LOG(ERR, "mac address is not valid");
1641                 ret = -EIO;
1642                 goto err_get_mac_addr;
1643         }
1644         /* Copy the permanent MAC address */
1645         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1646                         (struct rte_ether_addr *)hw->mac.perm_addr);
1647
1648         /* Disable flow control */
1649         hw->fc.requested_mode = I40E_FC_NONE;
1650         i40e_set_fc(hw, &aq_fail, TRUE);
1651
1652         /* Set the global registers with default ether type value */
1653         if (!pf->support_multi_driver) {
1654                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1655                                          RTE_ETHER_TYPE_VLAN);
1656                 if (ret != I40E_SUCCESS) {
1657                         PMD_INIT_LOG(ERR,
1658                                      "Failed to set the default outer "
1659                                      "VLAN ether type");
1660                         goto err_setup_pf_switch;
1661                 }
1662         }
1663
1664         /* PF setup, which includes VSI setup */
1665         ret = i40e_pf_setup(pf);
1666         if (ret) {
1667                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1668                 goto err_setup_pf_switch;
1669         }
1670
1671         vsi = pf->main_vsi;
1672
1673         /* Disable double vlan by default */
1674         i40e_vsi_config_double_vlan(vsi, FALSE);
1675
1676         /* Disable S-TAG identification when floating_veb is disabled */
1677         if (!pf->floating_veb) {
1678                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1679                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1680                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1681                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1682                 }
1683         }
1684
1685         if (!vsi->max_macaddrs)
1686                 len = RTE_ETHER_ADDR_LEN;
1687         else
1688                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1689
1690         /* Should be after VSI initialized */
1691         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1692         if (!dev->data->mac_addrs) {
1693                 PMD_INIT_LOG(ERR,
1694                         "Failed to allocated memory for storing mac address");
1695                 goto err_mac_alloc;
1696         }
1697         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1698                                         &dev->data->mac_addrs[0]);
1699
1700         /* Pass the information to the rte_eth_dev_close() that it should also
1701          * release the private port resources.
1702          */
1703         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1704
1705         /* Init dcb to sw mode by default */
1706         ret = i40e_dcb_init_configure(dev, TRUE);
1707         if (ret != I40E_SUCCESS) {
1708                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1709                 pf->flags &= ~I40E_FLAG_DCB;
1710         }
1711         /* Update HW struct after DCB configuration */
1712         i40e_get_cap(hw);
1713
1714         /* initialize pf host driver to setup SRIOV resource if applicable */
1715         i40e_pf_host_init(dev);
1716
1717         /* register callback func to eal lib */
1718         rte_intr_callback_register(intr_handle,
1719                                    i40e_dev_interrupt_handler, dev);
1720
1721         /* configure and enable device interrupt */
1722         i40e_pf_config_irq0(hw, TRUE);
1723         i40e_pf_enable_irq0(hw);
1724
1725         /* enable uio intr after callback register */
1726         rte_intr_enable(intr_handle);
1727
1728         /* By default disable flexible payload in global configuration */
1729         if (!pf->support_multi_driver)
1730                 i40e_flex_payload_reg_set_default(hw);
1731
1732         /*
1733          * Add an ethertype filter to drop all flow control frames transmitted
1734          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1735          * frames to wire.
1736          */
1737         i40e_add_tx_flow_control_drop_filter(pf);
1738
1739         /* Set the max frame size to 0x2600 by default,
1740          * in case other drivers changed the default value.
1741          */
1742         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1743
1744         /* initialize mirror rule list */
1745         TAILQ_INIT(&pf->mirror_list);
1746
1747         /* initialize RSS rule list */
1748         TAILQ_INIT(&pf->rss_config_list);
1749
1750         /* initialize Traffic Manager configuration */
1751         i40e_tm_conf_init(dev);
1752
1753         /* Initialize customized information */
1754         i40e_init_customized_info(pf);
1755
1756         /* Initialize the filter invalidation configuration */
1757         i40e_init_filter_invalidation(pf);
1758
1759         ret = i40e_init_ethtype_filter_list(dev);
1760         if (ret < 0)
1761                 goto err_init_ethtype_filter_list;
1762         ret = i40e_init_tunnel_filter_list(dev);
1763         if (ret < 0)
1764                 goto err_init_tunnel_filter_list;
1765         ret = i40e_init_fdir_filter_list(dev);
1766         if (ret < 0)
1767                 goto err_init_fdir_filter_list;
1768
1769         /* initialize queue region configuration */
1770         i40e_init_queue_region_conf(dev);
1771
1772         /* initialize RSS configuration from rte_flow */
1773         memset(&pf->rss_info, 0,
1774                 sizeof(struct i40e_rte_flow_rss_conf));
1775
1776         /* reset all stats of the device, including pf and main vsi */
1777         i40e_dev_stats_reset(dev);
1778
1779         return 0;
1780
1781 err_init_fdir_filter_list:
1782         rte_free(pf->tunnel.hash_table);
1783         rte_free(pf->tunnel.hash_map);
1784 err_init_tunnel_filter_list:
1785         rte_free(pf->ethertype.hash_table);
1786         rte_free(pf->ethertype.hash_map);
1787 err_init_ethtype_filter_list:
1788         rte_free(dev->data->mac_addrs);
1789         dev->data->mac_addrs = NULL;
1790 err_mac_alloc:
1791         i40e_vsi_release(pf->main_vsi);
1792 err_setup_pf_switch:
1793 err_get_mac_addr:
1794 err_configure_lan_hmc:
1795         (void)i40e_shutdown_lan_hmc(hw);
1796 err_init_lan_hmc:
1797         i40e_res_pool_destroy(&pf->msix_pool);
1798 err_msix_pool_init:
1799         i40e_res_pool_destroy(&pf->qp_pool);
1800 err_qp_pool_init:
1801 err_parameter_init:
1802 err_get_capabilities:
1803         (void)i40e_shutdown_adminq(hw);
1804
1805         return ret;
1806 }
1807
1808 static void
1809 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1810 {
1811         struct i40e_ethertype_filter *p_ethertype;
1812         struct i40e_ethertype_rule *ethertype_rule;
1813
1814         ethertype_rule = &pf->ethertype;
1815         /* Remove all ethertype filter rules and hash */
1816         if (ethertype_rule->hash_map)
1817                 rte_free(ethertype_rule->hash_map);
1818         if (ethertype_rule->hash_table)
1819                 rte_hash_free(ethertype_rule->hash_table);
1820
1821         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1822                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1823                              p_ethertype, rules);
1824                 rte_free(p_ethertype);
1825         }
1826 }
1827
1828 static void
1829 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1830 {
1831         struct i40e_tunnel_filter *p_tunnel;
1832         struct i40e_tunnel_rule *tunnel_rule;
1833
1834         tunnel_rule = &pf->tunnel;
1835         /* Remove all tunnel director rules and hash */
1836         if (tunnel_rule->hash_map)
1837                 rte_free(tunnel_rule->hash_map);
1838         if (tunnel_rule->hash_table)
1839                 rte_hash_free(tunnel_rule->hash_table);
1840
1841         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1842                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1843                 rte_free(p_tunnel);
1844         }
1845 }
1846
1847 static void
1848 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1849 {
1850         struct i40e_fdir_filter *p_fdir;
1851         struct i40e_fdir_info *fdir_info;
1852
1853         fdir_info = &pf->fdir;
1854
1855         /* Remove all flow director rules */
1856         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1857                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1858 }
1859
1860 static void
1861 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1862 {
1863         struct i40e_fdir_info *fdir_info;
1864
1865         fdir_info = &pf->fdir;
1866
1867         /* flow director memory cleanup */
1868         if (fdir_info->hash_map)
1869                 rte_free(fdir_info->hash_map);
1870         if (fdir_info->hash_table)
1871                 rte_hash_free(fdir_info->hash_table);
1872         if (fdir_info->fdir_flow_pool.bitmap)
1873                 rte_bitmap_free(fdir_info->fdir_flow_pool.bitmap);
1874         if (fdir_info->fdir_flow_pool.pool)
1875                 rte_free(fdir_info->fdir_flow_pool.pool);
1876         if (fdir_info->fdir_filter_array)
1877                 rte_free(fdir_info->fdir_filter_array);
1878 }
1879
1880 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1881 {
1882         /*
1883          * Disable by default flexible payload
1884          * for corresponding L2/L3/L4 layers.
1885          */
1886         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1887         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1888         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1889 }
1890
1891 static int
1892 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1893 {
1894         struct i40e_hw *hw;
1895
1896         PMD_INIT_FUNC_TRACE();
1897
1898         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899                 return 0;
1900
1901         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902
1903         if (hw->adapter_closed == 0)
1904                 i40e_dev_close(dev);
1905
1906         return 0;
1907 }
1908
1909 static int
1910 i40e_dev_configure(struct rte_eth_dev *dev)
1911 {
1912         struct i40e_adapter *ad =
1913                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1917         int i, ret;
1918
1919         ret = i40e_dev_sync_phy_type(hw);
1920         if (ret)
1921                 return ret;
1922
1923         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1924          * bulk allocation or vector Rx preconditions we will reset it.
1925          */
1926         ad->rx_bulk_alloc_allowed = true;
1927         ad->rx_vec_allowed = true;
1928         ad->tx_simple_allowed = true;
1929         ad->tx_vec_allowed = true;
1930
1931         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1932                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1933
1934         /* Only legacy filter API needs the following fdir config. So when the
1935          * legacy filter API is deprecated, the following codes should also be
1936          * removed.
1937          */
1938         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1939                 ret = i40e_fdir_setup(pf);
1940                 if (ret != I40E_SUCCESS) {
1941                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1942                         return -ENOTSUP;
1943                 }
1944                 ret = i40e_fdir_configure(dev);
1945                 if (ret < 0) {
1946                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1947                         goto err;
1948                 }
1949         } else
1950                 i40e_fdir_teardown(pf);
1951
1952         ret = i40e_dev_init_vlan(dev);
1953         if (ret < 0)
1954                 goto err;
1955
1956         /* VMDQ setup.
1957          *  General PMD driver call sequence are NIC init, configure,
1958          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1959          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1960          *  applicable. So, VMDQ setting has to be done before
1961          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1962          *  For RSS setting, it will try to calculate actual configured RX queue
1963          *  number, which will be available after rx_queue_setup(). dev_start()
1964          *  function is good to place RSS setup.
1965          */
1966         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1967                 ret = i40e_vmdq_setup(dev);
1968                 if (ret)
1969                         goto err;
1970         }
1971
1972         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1973                 ret = i40e_dcb_setup(dev);
1974                 if (ret) {
1975                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1976                         goto err_dcb;
1977                 }
1978         }
1979
1980         TAILQ_INIT(&pf->flow_list);
1981
1982         return 0;
1983
1984 err_dcb:
1985         /* need to release vmdq resource if exists */
1986         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1987                 i40e_vsi_release(pf->vmdq[i].vsi);
1988                 pf->vmdq[i].vsi = NULL;
1989         }
1990         rte_free(pf->vmdq);
1991         pf->vmdq = NULL;
1992 err:
1993         /* Need to release fdir resource if exists.
1994          * Only legacy filter API needs the following fdir config. So when the
1995          * legacy filter API is deprecated, the following code should also be
1996          * removed.
1997          */
1998         i40e_fdir_teardown(pf);
1999         return ret;
2000 }
2001
2002 void
2003 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2004 {
2005         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2006         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2007         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2008         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2009         uint16_t msix_vect = vsi->msix_intr;
2010         uint16_t i;
2011
2012         for (i = 0; i < vsi->nb_qps; i++) {
2013                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2014                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2015                 rte_wmb();
2016         }
2017
2018         if (vsi->type != I40E_VSI_SRIOV) {
2019                 if (!rte_intr_allow_others(intr_handle)) {
2020                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2021                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2022                         I40E_WRITE_REG(hw,
2023                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2024                                        0);
2025                 } else {
2026                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2027                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2028                         I40E_WRITE_REG(hw,
2029                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2030                                                        msix_vect - 1), 0);
2031                 }
2032         } else {
2033                 uint32_t reg;
2034                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2035                         vsi->user_param + (msix_vect - 1);
2036
2037                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2038                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2039         }
2040         I40E_WRITE_FLUSH(hw);
2041 }
2042
2043 static void
2044 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2045                        int base_queue, int nb_queue,
2046                        uint16_t itr_idx)
2047 {
2048         int i;
2049         uint32_t val;
2050         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2051         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2052
2053         /* Bind all RX queues to allocated MSIX interrupt */
2054         for (i = 0; i < nb_queue; i++) {
2055                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2056                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2057                         ((base_queue + i + 1) <<
2058                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2059                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2060                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2061
2062                 if (i == nb_queue - 1)
2063                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2064                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2065         }
2066
2067         /* Write first RX queue to Link list register as the head element */
2068         if (vsi->type != I40E_VSI_SRIOV) {
2069                 uint16_t interval =
2070                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2071
2072                 if (msix_vect == I40E_MISC_VEC_ID) {
2073                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2074                                        (base_queue <<
2075                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2076                                        (0x0 <<
2077                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2078                         I40E_WRITE_REG(hw,
2079                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2080                                        interval);
2081                 } else {
2082                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2083                                        (base_queue <<
2084                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2085                                        (0x0 <<
2086                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2087                         I40E_WRITE_REG(hw,
2088                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2089                                                        msix_vect - 1),
2090                                        interval);
2091                 }
2092         } else {
2093                 uint32_t reg;
2094
2095                 if (msix_vect == I40E_MISC_VEC_ID) {
2096                         I40E_WRITE_REG(hw,
2097                                        I40E_VPINT_LNKLST0(vsi->user_param),
2098                                        (base_queue <<
2099                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2100                                        (0x0 <<
2101                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2102                 } else {
2103                         /* num_msix_vectors_vf needs to minus irq0 */
2104                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2105                                 vsi->user_param + (msix_vect - 1);
2106
2107                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2108                                        (base_queue <<
2109                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2110                                        (0x0 <<
2111                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2112                 }
2113         }
2114
2115         I40E_WRITE_FLUSH(hw);
2116 }
2117
2118 int
2119 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2120 {
2121         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2124         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2125         uint16_t msix_vect = vsi->msix_intr;
2126         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2127         uint16_t queue_idx = 0;
2128         int record = 0;
2129         int i;
2130
2131         for (i = 0; i < vsi->nb_qps; i++) {
2132                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2133                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2134         }
2135
2136         /* VF bind interrupt */
2137         if (vsi->type == I40E_VSI_SRIOV) {
2138                 if (vsi->nb_msix == 0) {
2139                         PMD_DRV_LOG(ERR, "No msix resource");
2140                         return -EINVAL;
2141                 }
2142                 __vsi_queues_bind_intr(vsi, msix_vect,
2143                                        vsi->base_queue, vsi->nb_qps,
2144                                        itr_idx);
2145                 return 0;
2146         }
2147
2148         /* PF & VMDq bind interrupt */
2149         if (rte_intr_dp_is_en(intr_handle)) {
2150                 if (vsi->type == I40E_VSI_MAIN) {
2151                         queue_idx = 0;
2152                         record = 1;
2153                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2154                         struct i40e_vsi *main_vsi =
2155                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2156                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2157                         record = 1;
2158                 }
2159         }
2160
2161         for (i = 0; i < vsi->nb_used_qps; i++) {
2162                 if (vsi->nb_msix == 0) {
2163                         PMD_DRV_LOG(ERR, "No msix resource");
2164                         return -EINVAL;
2165                 } else if (nb_msix <= 1) {
2166                         if (!rte_intr_allow_others(intr_handle))
2167                                 /* allow to share MISC_VEC_ID */
2168                                 msix_vect = I40E_MISC_VEC_ID;
2169
2170                         /* no enough msix_vect, map all to one */
2171                         __vsi_queues_bind_intr(vsi, msix_vect,
2172                                                vsi->base_queue + i,
2173                                                vsi->nb_used_qps - i,
2174                                                itr_idx);
2175                         for (; !!record && i < vsi->nb_used_qps; i++)
2176                                 intr_handle->intr_vec[queue_idx + i] =
2177                                         msix_vect;
2178                         break;
2179                 }
2180                 /* 1:1 queue/msix_vect mapping */
2181                 __vsi_queues_bind_intr(vsi, msix_vect,
2182                                        vsi->base_queue + i, 1,
2183                                        itr_idx);
2184                 if (!!record)
2185                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2186
2187                 msix_vect++;
2188                 nb_msix--;
2189         }
2190
2191         return 0;
2192 }
2193
2194 void
2195 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2196 {
2197         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2198         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2199         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2200         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2201         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2202         uint16_t msix_intr, i;
2203
2204         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2205                 for (i = 0; i < vsi->nb_msix; i++) {
2206                         msix_intr = vsi->msix_intr + i;
2207                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2208                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2209                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2210                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2211                 }
2212         else
2213                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2214                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2215                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2216                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2217
2218         I40E_WRITE_FLUSH(hw);
2219 }
2220
2221 void
2222 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2223 {
2224         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2225         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2226         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2227         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2228         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2229         uint16_t msix_intr, i;
2230
2231         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2232                 for (i = 0; i < vsi->nb_msix; i++) {
2233                         msix_intr = vsi->msix_intr + i;
2234                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2235                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2236                 }
2237         else
2238                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2239                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2240
2241         I40E_WRITE_FLUSH(hw);
2242 }
2243
2244 static inline uint8_t
2245 i40e_parse_link_speeds(uint16_t link_speeds)
2246 {
2247         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2248
2249         if (link_speeds & ETH_LINK_SPEED_40G)
2250                 link_speed |= I40E_LINK_SPEED_40GB;
2251         if (link_speeds & ETH_LINK_SPEED_25G)
2252                 link_speed |= I40E_LINK_SPEED_25GB;
2253         if (link_speeds & ETH_LINK_SPEED_20G)
2254                 link_speed |= I40E_LINK_SPEED_20GB;
2255         if (link_speeds & ETH_LINK_SPEED_10G)
2256                 link_speed |= I40E_LINK_SPEED_10GB;
2257         if (link_speeds & ETH_LINK_SPEED_1G)
2258                 link_speed |= I40E_LINK_SPEED_1GB;
2259         if (link_speeds & ETH_LINK_SPEED_100M)
2260                 link_speed |= I40E_LINK_SPEED_100MB;
2261
2262         return link_speed;
2263 }
2264
2265 static int
2266 i40e_phy_conf_link(struct i40e_hw *hw,
2267                    uint8_t abilities,
2268                    uint8_t force_speed,
2269                    bool is_up)
2270 {
2271         enum i40e_status_code status;
2272         struct i40e_aq_get_phy_abilities_resp phy_ab;
2273         struct i40e_aq_set_phy_config phy_conf;
2274         enum i40e_aq_phy_type cnt;
2275         uint8_t avail_speed;
2276         uint32_t phy_type_mask = 0;
2277
2278         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2279                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2280                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2281                         I40E_AQ_PHY_FLAG_LOW_POWER;
2282         int ret = -ENOTSUP;
2283
2284         /* To get phy capabilities of available speeds. */
2285         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2286                                               NULL);
2287         if (status) {
2288                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2289                                 status);
2290                 return ret;
2291         }
2292         avail_speed = phy_ab.link_speed;
2293
2294         /* To get the current phy config. */
2295         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2296                                               NULL);
2297         if (status) {
2298                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2299                                 status);
2300                 return ret;
2301         }
2302
2303         /* If link needs to go up and it is in autoneg mode the speed is OK,
2304          * no need to set up again.
2305          */
2306         if (is_up && phy_ab.phy_type != 0 &&
2307                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2308                      phy_ab.link_speed != 0)
2309                 return I40E_SUCCESS;
2310
2311         memset(&phy_conf, 0, sizeof(phy_conf));
2312
2313         /* bits 0-2 use the values from get_phy_abilities_resp */
2314         abilities &= ~mask;
2315         abilities |= phy_ab.abilities & mask;
2316
2317         phy_conf.abilities = abilities;
2318
2319         /* If link needs to go up, but the force speed is not supported,
2320          * Warn users and config the default available speeds.
2321          */
2322         if (is_up && !(force_speed & avail_speed)) {
2323                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2324                 phy_conf.link_speed = avail_speed;
2325         } else {
2326                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2327         }
2328
2329         /* PHY type mask needs to include each type except PHY type extension */
2330         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2331                 phy_type_mask |= 1 << cnt;
2332
2333         /* use get_phy_abilities_resp value for the rest */
2334         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2335         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2336                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2337                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2338         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2339         phy_conf.eee_capability = phy_ab.eee_capability;
2340         phy_conf.eeer = phy_ab.eeer_val;
2341         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2342
2343         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2344                     phy_ab.abilities, phy_ab.link_speed);
2345         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2346                     phy_conf.abilities, phy_conf.link_speed);
2347
2348         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2349         if (status)
2350                 return ret;
2351
2352         return I40E_SUCCESS;
2353 }
2354
2355 static int
2356 i40e_apply_link_speed(struct rte_eth_dev *dev)
2357 {
2358         uint8_t speed;
2359         uint8_t abilities = 0;
2360         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2361         struct rte_eth_conf *conf = &dev->data->dev_conf;
2362
2363         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2364                      I40E_AQ_PHY_LINK_ENABLED;
2365
2366         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2367                 conf->link_speeds = ETH_LINK_SPEED_40G |
2368                                     ETH_LINK_SPEED_25G |
2369                                     ETH_LINK_SPEED_20G |
2370                                     ETH_LINK_SPEED_10G |
2371                                     ETH_LINK_SPEED_1G |
2372                                     ETH_LINK_SPEED_100M;
2373
2374                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2375         } else {
2376                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2377         }
2378         speed = i40e_parse_link_speeds(conf->link_speeds);
2379
2380         return i40e_phy_conf_link(hw, abilities, speed, true);
2381 }
2382
2383 static int
2384 i40e_dev_start(struct rte_eth_dev *dev)
2385 {
2386         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388         struct i40e_vsi *main_vsi = pf->main_vsi;
2389         int ret, i;
2390         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2391         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2392         uint32_t intr_vector = 0;
2393         struct i40e_vsi *vsi;
2394         uint16_t nb_rxq, nb_txq;
2395
2396         hw->adapter_stopped = 0;
2397
2398         rte_intr_disable(intr_handle);
2399
2400         if ((rte_intr_cap_multiple(intr_handle) ||
2401              !RTE_ETH_DEV_SRIOV(dev).active) &&
2402             dev->data->dev_conf.intr_conf.rxq != 0) {
2403                 intr_vector = dev->data->nb_rx_queues;
2404                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2405                 if (ret)
2406                         return ret;
2407         }
2408
2409         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2410                 intr_handle->intr_vec =
2411                         rte_zmalloc("intr_vec",
2412                                     dev->data->nb_rx_queues * sizeof(int),
2413                                     0);
2414                 if (!intr_handle->intr_vec) {
2415                         PMD_INIT_LOG(ERR,
2416                                 "Failed to allocate %d rx_queues intr_vec",
2417                                 dev->data->nb_rx_queues);
2418                         return -ENOMEM;
2419                 }
2420         }
2421
2422         /* Initialize VSI */
2423         ret = i40e_dev_rxtx_init(pf);
2424         if (ret != I40E_SUCCESS) {
2425                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2426                 return ret;
2427         }
2428
2429         /* Map queues with MSIX interrupt */
2430         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2431                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2432         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2433         if (ret < 0)
2434                 return ret;
2435         i40e_vsi_enable_queues_intr(main_vsi);
2436
2437         /* Map VMDQ VSI queues with MSIX interrupt */
2438         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2439                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2440                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2441                                                 I40E_ITR_INDEX_DEFAULT);
2442                 if (ret < 0)
2443                         return ret;
2444                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2445         }
2446
2447         /* Enable all queues which have been configured */
2448         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2449                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2450                 if (ret)
2451                         goto rx_err;
2452         }
2453
2454         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2455                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2456                 if (ret)
2457                         goto tx_err;
2458         }
2459
2460         /* Enable receiving broadcast packets */
2461         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2462         if (ret != I40E_SUCCESS)
2463                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2464
2465         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2466                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2467                                                 true, NULL);
2468                 if (ret != I40E_SUCCESS)
2469                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2470         }
2471
2472         /* Enable the VLAN promiscuous mode. */
2473         if (pf->vfs) {
2474                 for (i = 0; i < pf->vf_num; i++) {
2475                         vsi = pf->vfs[i].vsi;
2476                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2477                                                      true, NULL);
2478                 }
2479         }
2480
2481         /* Enable mac loopback mode */
2482         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2483             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2484                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2485                 if (ret != I40E_SUCCESS) {
2486                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2487                         goto tx_err;
2488                 }
2489         }
2490
2491         /* Apply link configure */
2492         ret = i40e_apply_link_speed(dev);
2493         if (I40E_SUCCESS != ret) {
2494                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2495                 goto tx_err;
2496         }
2497
2498         if (!rte_intr_allow_others(intr_handle)) {
2499                 rte_intr_callback_unregister(intr_handle,
2500                                              i40e_dev_interrupt_handler,
2501                                              (void *)dev);
2502                 /* configure and enable device interrupt */
2503                 i40e_pf_config_irq0(hw, FALSE);
2504                 i40e_pf_enable_irq0(hw);
2505
2506                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2507                         PMD_INIT_LOG(INFO,
2508                                 "lsc won't enable because of no intr multiplex");
2509         } else {
2510                 ret = i40e_aq_set_phy_int_mask(hw,
2511                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2512                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2513                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2514                 if (ret != I40E_SUCCESS)
2515                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2516
2517                 /* Call get_link_info aq commond to enable/disable LSE */
2518                 i40e_dev_link_update(dev, 0);
2519         }
2520
2521         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2522                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2523                                   i40e_dev_alarm_handler, dev);
2524         } else {
2525                 /* enable uio intr after callback register */
2526                 rte_intr_enable(intr_handle);
2527         }
2528
2529         i40e_filter_restore(pf);
2530
2531         if (pf->tm_conf.root && !pf->tm_conf.committed)
2532                 PMD_DRV_LOG(WARNING,
2533                             "please call hierarchy_commit() "
2534                             "before starting the port");
2535
2536         return I40E_SUCCESS;
2537
2538 tx_err:
2539         for (i = 0; i < nb_txq; i++)
2540                 i40e_dev_tx_queue_stop(dev, i);
2541 rx_err:
2542         for (i = 0; i < nb_rxq; i++)
2543                 i40e_dev_rx_queue_stop(dev, i);
2544
2545         return ret;
2546 }
2547
2548 static void
2549 i40e_dev_stop(struct rte_eth_dev *dev)
2550 {
2551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2552         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553         struct i40e_vsi *main_vsi = pf->main_vsi;
2554         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2555         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2556         int i;
2557
2558         if (hw->adapter_stopped == 1)
2559                 return;
2560
2561         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2562                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2563                 rte_intr_enable(intr_handle);
2564         }
2565
2566         /* Disable all queues */
2567         for (i = 0; i < dev->data->nb_tx_queues; i++)
2568                 i40e_dev_tx_queue_stop(dev, i);
2569
2570         for (i = 0; i < dev->data->nb_rx_queues; i++)
2571                 i40e_dev_rx_queue_stop(dev, i);
2572
2573         /* un-map queues with interrupt registers */
2574         i40e_vsi_disable_queues_intr(main_vsi);
2575         i40e_vsi_queues_unbind_intr(main_vsi);
2576
2577         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2578                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2579                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2580         }
2581
2582         /* Clear all queues and release memory */
2583         i40e_dev_clear_queues(dev);
2584
2585         /* Set link down */
2586         i40e_dev_set_link_down(dev);
2587
2588         if (!rte_intr_allow_others(intr_handle))
2589                 /* resume to the default handler */
2590                 rte_intr_callback_register(intr_handle,
2591                                            i40e_dev_interrupt_handler,
2592                                            (void *)dev);
2593
2594         /* Clean datapath event and queue/vec mapping */
2595         rte_intr_efd_disable(intr_handle);
2596         if (intr_handle->intr_vec) {
2597                 rte_free(intr_handle->intr_vec);
2598                 intr_handle->intr_vec = NULL;
2599         }
2600
2601         /* reset hierarchy commit */
2602         pf->tm_conf.committed = false;
2603
2604         hw->adapter_stopped = 1;
2605
2606         pf->adapter->rss_reta_updated = 0;
2607 }
2608
2609 static void
2610 i40e_dev_close(struct rte_eth_dev *dev)
2611 {
2612         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2615         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2616         struct i40e_mirror_rule *p_mirror;
2617         struct i40e_filter_control_settings settings;
2618         struct rte_flow *p_flow;
2619         uint32_t reg;
2620         int i;
2621         int ret;
2622         uint8_t aq_fail = 0;
2623         int retries = 0;
2624
2625         PMD_INIT_FUNC_TRACE();
2626
2627         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2628         if (ret)
2629                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2630
2631
2632         i40e_dev_stop(dev);
2633
2634         /* Remove all mirror rules */
2635         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2636                 ret = i40e_aq_del_mirror_rule(hw,
2637                                               pf->main_vsi->veb->seid,
2638                                               p_mirror->rule_type,
2639                                               p_mirror->entries,
2640                                               p_mirror->num_entries,
2641                                               p_mirror->id);
2642                 if (ret < 0)
2643                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2644                                     "status = %d, aq_err = %d.", ret,
2645                                     hw->aq.asq_last_status);
2646
2647                 /* remove mirror software resource anyway */
2648                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2649                 rte_free(p_mirror);
2650                 pf->nb_mirror_rule--;
2651         }
2652
2653         i40e_dev_free_queues(dev);
2654
2655         /* Disable interrupt */
2656         i40e_pf_disable_irq0(hw);
2657         rte_intr_disable(intr_handle);
2658
2659         /*
2660          * Only legacy filter API needs the following fdir config. So when the
2661          * legacy filter API is deprecated, the following code should also be
2662          * removed.
2663          */
2664         i40e_fdir_teardown(pf);
2665
2666         /* shutdown and destroy the HMC */
2667         i40e_shutdown_lan_hmc(hw);
2668
2669         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2670                 i40e_vsi_release(pf->vmdq[i].vsi);
2671                 pf->vmdq[i].vsi = NULL;
2672         }
2673         rte_free(pf->vmdq);
2674         pf->vmdq = NULL;
2675
2676         /* release all the existing VSIs and VEBs */
2677         i40e_vsi_release(pf->main_vsi);
2678
2679         /* shutdown the adminq */
2680         i40e_aq_queue_shutdown(hw, true);
2681         i40e_shutdown_adminq(hw);
2682
2683         i40e_res_pool_destroy(&pf->qp_pool);
2684         i40e_res_pool_destroy(&pf->msix_pool);
2685
2686         /* Disable flexible payload in global configuration */
2687         if (!pf->support_multi_driver)
2688                 i40e_flex_payload_reg_set_default(hw);
2689
2690         /* force a PF reset to clean anything leftover */
2691         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2692         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2693                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2694         I40E_WRITE_FLUSH(hw);
2695
2696         dev->dev_ops = NULL;
2697         dev->rx_pkt_burst = NULL;
2698         dev->tx_pkt_burst = NULL;
2699
2700         /* Clear PXE mode */
2701         i40e_clear_pxe_mode(hw);
2702
2703         /* Unconfigure filter control */
2704         memset(&settings, 0, sizeof(settings));
2705         ret = i40e_set_filter_control(hw, &settings);
2706         if (ret)
2707                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2708                                         ret);
2709
2710         /* Disable flow control */
2711         hw->fc.requested_mode = I40E_FC_NONE;
2712         i40e_set_fc(hw, &aq_fail, TRUE);
2713
2714         /* uninitialize pf host driver */
2715         i40e_pf_host_uninit(dev);
2716
2717         do {
2718                 ret = rte_intr_callback_unregister(intr_handle,
2719                                 i40e_dev_interrupt_handler, dev);
2720                 if (ret >= 0 || ret == -ENOENT) {
2721                         break;
2722                 } else if (ret != -EAGAIN) {
2723                         PMD_INIT_LOG(ERR,
2724                                  "intr callback unregister failed: %d",
2725                                  ret);
2726                 }
2727                 i40e_msec_delay(500);
2728         } while (retries++ < 5);
2729
2730         i40e_rm_ethtype_filter_list(pf);
2731         i40e_rm_tunnel_filter_list(pf);
2732         i40e_rm_fdir_filter_list(pf);
2733
2734         /* Remove all flows */
2735         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2736                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2737                 /* Do not free FDIR flows since they are static allocated */
2738                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2739                         rte_free(p_flow);
2740         }
2741
2742         /* release the fdir static allocated memory */
2743         i40e_fdir_memory_cleanup(pf);
2744
2745         /* Remove all Traffic Manager configuration */
2746         i40e_tm_conf_uninit(dev);
2747
2748         hw->adapter_closed = 1;
2749 }
2750
2751 /*
2752  * Reset PF device only to re-initialize resources in PMD layer
2753  */
2754 static int
2755 i40e_dev_reset(struct rte_eth_dev *dev)
2756 {
2757         int ret;
2758
2759         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2760          * its VF to make them align with it. The detailed notification
2761          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2762          * To avoid unexpected behavior in VF, currently reset of PF with
2763          * SR-IOV activation is not supported. It might be supported later.
2764          */
2765         if (dev->data->sriov.active)
2766                 return -ENOTSUP;
2767
2768         ret = eth_i40e_dev_uninit(dev);
2769         if (ret)
2770                 return ret;
2771
2772         ret = eth_i40e_dev_init(dev, NULL);
2773
2774         return ret;
2775 }
2776
2777 static int
2778 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2779 {
2780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782         struct i40e_vsi *vsi = pf->main_vsi;
2783         int status;
2784
2785         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2786                                                      true, NULL, true);
2787         if (status != I40E_SUCCESS) {
2788                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2789                 return -EAGAIN;
2790         }
2791
2792         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2793                                                         TRUE, NULL);
2794         if (status != I40E_SUCCESS) {
2795                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2796                 /* Rollback unicast promiscuous mode */
2797                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2798                                                     false, NULL, true);
2799                 return -EAGAIN;
2800         }
2801
2802         return 0;
2803 }
2804
2805 static int
2806 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2807 {
2808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810         struct i40e_vsi *vsi = pf->main_vsi;
2811         int status;
2812
2813         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2814                                                      false, NULL, true);
2815         if (status != I40E_SUCCESS) {
2816                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2817                 return -EAGAIN;
2818         }
2819
2820         /* must remain in all_multicast mode */
2821         if (dev->data->all_multicast == 1)
2822                 return 0;
2823
2824         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2825                                                         false, NULL);
2826         if (status != I40E_SUCCESS) {
2827                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2828                 /* Rollback unicast promiscuous mode */
2829                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2830                                                     true, NULL, true);
2831                 return -EAGAIN;
2832         }
2833
2834         return 0;
2835 }
2836
2837 static int
2838 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2839 {
2840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         struct i40e_vsi *vsi = pf->main_vsi;
2843         int ret;
2844
2845         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2846         if (ret != I40E_SUCCESS) {
2847                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2848                 return -EAGAIN;
2849         }
2850
2851         return 0;
2852 }
2853
2854 static int
2855 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2856 {
2857         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859         struct i40e_vsi *vsi = pf->main_vsi;
2860         int ret;
2861
2862         if (dev->data->promiscuous == 1)
2863                 return 0; /* must remain in all_multicast mode */
2864
2865         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2866                                 vsi->seid, FALSE, NULL);
2867         if (ret != I40E_SUCCESS) {
2868                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2869                 return -EAGAIN;
2870         }
2871
2872         return 0;
2873 }
2874
2875 /*
2876  * Set device link up.
2877  */
2878 static int
2879 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2880 {
2881         /* re-apply link speed setting */
2882         return i40e_apply_link_speed(dev);
2883 }
2884
2885 /*
2886  * Set device link down.
2887  */
2888 static int
2889 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2890 {
2891         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2892         uint8_t abilities = 0;
2893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2894
2895         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2896         return i40e_phy_conf_link(hw, abilities, speed, false);
2897 }
2898
2899 static __rte_always_inline void
2900 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2901 {
2902 /* Link status registers and values*/
2903 #define I40E_PRTMAC_LINKSTA             0x001E2420
2904 #define I40E_REG_LINK_UP                0x40000080
2905 #define I40E_PRTMAC_MACC                0x001E24E0
2906 #define I40E_REG_MACC_25GB              0x00020000
2907 #define I40E_REG_SPEED_MASK             0x38000000
2908 #define I40E_REG_SPEED_0                0x00000000
2909 #define I40E_REG_SPEED_1                0x08000000
2910 #define I40E_REG_SPEED_2                0x10000000
2911 #define I40E_REG_SPEED_3                0x18000000
2912 #define I40E_REG_SPEED_4                0x20000000
2913         uint32_t link_speed;
2914         uint32_t reg_val;
2915
2916         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2917         link_speed = reg_val & I40E_REG_SPEED_MASK;
2918         reg_val &= I40E_REG_LINK_UP;
2919         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2920
2921         if (unlikely(link->link_status == 0))
2922                 return;
2923
2924         /* Parse the link status */
2925         switch (link_speed) {
2926         case I40E_REG_SPEED_0:
2927                 link->link_speed = ETH_SPEED_NUM_100M;
2928                 break;
2929         case I40E_REG_SPEED_1:
2930                 link->link_speed = ETH_SPEED_NUM_1G;
2931                 break;
2932         case I40E_REG_SPEED_2:
2933                 if (hw->mac.type == I40E_MAC_X722)
2934                         link->link_speed = ETH_SPEED_NUM_2_5G;
2935                 else
2936                         link->link_speed = ETH_SPEED_NUM_10G;
2937                 break;
2938         case I40E_REG_SPEED_3:
2939                 if (hw->mac.type == I40E_MAC_X722) {
2940                         link->link_speed = ETH_SPEED_NUM_5G;
2941                 } else {
2942                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2943
2944                         if (reg_val & I40E_REG_MACC_25GB)
2945                                 link->link_speed = ETH_SPEED_NUM_25G;
2946                         else
2947                                 link->link_speed = ETH_SPEED_NUM_40G;
2948                 }
2949                 break;
2950         case I40E_REG_SPEED_4:
2951                 if (hw->mac.type == I40E_MAC_X722)
2952                         link->link_speed = ETH_SPEED_NUM_10G;
2953                 else
2954                         link->link_speed = ETH_SPEED_NUM_20G;
2955                 break;
2956         default:
2957                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2958                 break;
2959         }
2960 }
2961
2962 static __rte_always_inline void
2963 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2964         bool enable_lse, int wait_to_complete)
2965 {
2966 #define CHECK_INTERVAL             100  /* 100ms */
2967 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2968         uint32_t rep_cnt = MAX_REPEAT_TIME;
2969         struct i40e_link_status link_status;
2970         int status;
2971
2972         memset(&link_status, 0, sizeof(link_status));
2973
2974         do {
2975                 memset(&link_status, 0, sizeof(link_status));
2976
2977                 /* Get link status information from hardware */
2978                 status = i40e_aq_get_link_info(hw, enable_lse,
2979                                                 &link_status, NULL);
2980                 if (unlikely(status != I40E_SUCCESS)) {
2981                         link->link_speed = ETH_SPEED_NUM_NONE;
2982                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2983                         PMD_DRV_LOG(ERR, "Failed to get link info");
2984                         return;
2985                 }
2986
2987                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2988                 if (!wait_to_complete || link->link_status)
2989                         break;
2990
2991                 rte_delay_ms(CHECK_INTERVAL);
2992         } while (--rep_cnt);
2993
2994         /* Parse the link status */
2995         switch (link_status.link_speed) {
2996         case I40E_LINK_SPEED_100MB:
2997                 link->link_speed = ETH_SPEED_NUM_100M;
2998                 break;
2999         case I40E_LINK_SPEED_1GB:
3000                 link->link_speed = ETH_SPEED_NUM_1G;
3001                 break;
3002         case I40E_LINK_SPEED_10GB:
3003                 link->link_speed = ETH_SPEED_NUM_10G;
3004                 break;
3005         case I40E_LINK_SPEED_20GB:
3006                 link->link_speed = ETH_SPEED_NUM_20G;
3007                 break;
3008         case I40E_LINK_SPEED_25GB:
3009                 link->link_speed = ETH_SPEED_NUM_25G;
3010                 break;
3011         case I40E_LINK_SPEED_40GB:
3012                 link->link_speed = ETH_SPEED_NUM_40G;
3013                 break;
3014         default:
3015                 link->link_speed = ETH_SPEED_NUM_NONE;
3016                 break;
3017         }
3018 }
3019
3020 int
3021 i40e_dev_link_update(struct rte_eth_dev *dev,
3022                      int wait_to_complete)
3023 {
3024         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3025         struct rte_eth_link link;
3026         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3027         int ret;
3028
3029         memset(&link, 0, sizeof(link));
3030
3031         /* i40e uses full duplex only */
3032         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3033         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3034                         ETH_LINK_SPEED_FIXED);
3035
3036         if (!wait_to_complete && !enable_lse)
3037                 update_link_reg(hw, &link);
3038         else
3039                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3040
3041         if (hw->switch_dev)
3042                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3043
3044         ret = rte_eth_linkstatus_set(dev, &link);
3045         i40e_notify_all_vfs_link_status(dev);
3046
3047         return ret;
3048 }
3049
3050 /* Get all the statistics of a VSI */
3051 void
3052 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3053 {
3054         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3055         struct i40e_eth_stats *nes = &vsi->eth_stats;
3056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3057         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3058
3059         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3060                             vsi->offset_loaded, &oes->rx_bytes,
3061                             &nes->rx_bytes);
3062         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3063                             vsi->offset_loaded, &oes->rx_unicast,
3064                             &nes->rx_unicast);
3065         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3066                             vsi->offset_loaded, &oes->rx_multicast,
3067                             &nes->rx_multicast);
3068         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3069                             vsi->offset_loaded, &oes->rx_broadcast,
3070                             &nes->rx_broadcast);
3071         /* exclude CRC bytes */
3072         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3073                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3074
3075         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3076                             &oes->rx_discards, &nes->rx_discards);
3077         /* GLV_REPC not supported */
3078         /* GLV_RMPC not supported */
3079         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3080                             &oes->rx_unknown_protocol,
3081                             &nes->rx_unknown_protocol);
3082         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3083                             vsi->offset_loaded, &oes->tx_bytes,
3084                             &nes->tx_bytes);
3085         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3086                             vsi->offset_loaded, &oes->tx_unicast,
3087                             &nes->tx_unicast);
3088         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3089                             vsi->offset_loaded, &oes->tx_multicast,
3090                             &nes->tx_multicast);
3091         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3092                             vsi->offset_loaded,  &oes->tx_broadcast,
3093                             &nes->tx_broadcast);
3094         /* GLV_TDPC not supported */
3095         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3096                             &oes->tx_errors, &nes->tx_errors);
3097         vsi->offset_loaded = true;
3098
3099         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3100                     vsi->vsi_id);
3101         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3102         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3103         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3104         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3105         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3106         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3107                     nes->rx_unknown_protocol);
3108         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3109         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3110         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3111         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3112         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3113         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3114         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3115                     vsi->vsi_id);
3116 }
3117
3118 static void
3119 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3120 {
3121         unsigned int i;
3122         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3123         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3124
3125         /* Get rx/tx bytes of internal transfer packets */
3126         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3127                         I40E_GLV_GORCL(hw->port),
3128                         pf->offset_loaded,
3129                         &pf->internal_stats_offset.rx_bytes,
3130                         &pf->internal_stats.rx_bytes);
3131
3132         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3133                         I40E_GLV_GOTCL(hw->port),
3134                         pf->offset_loaded,
3135                         &pf->internal_stats_offset.tx_bytes,
3136                         &pf->internal_stats.tx_bytes);
3137         /* Get total internal rx packet count */
3138         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3139                             I40E_GLV_UPRCL(hw->port),
3140                             pf->offset_loaded,
3141                             &pf->internal_stats_offset.rx_unicast,
3142                             &pf->internal_stats.rx_unicast);
3143         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3144                             I40E_GLV_MPRCL(hw->port),
3145                             pf->offset_loaded,
3146                             &pf->internal_stats_offset.rx_multicast,
3147                             &pf->internal_stats.rx_multicast);
3148         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3149                             I40E_GLV_BPRCL(hw->port),
3150                             pf->offset_loaded,
3151                             &pf->internal_stats_offset.rx_broadcast,
3152                             &pf->internal_stats.rx_broadcast);
3153         /* Get total internal tx packet count */
3154         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3155                             I40E_GLV_UPTCL(hw->port),
3156                             pf->offset_loaded,
3157                             &pf->internal_stats_offset.tx_unicast,
3158                             &pf->internal_stats.tx_unicast);
3159         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3160                             I40E_GLV_MPTCL(hw->port),
3161                             pf->offset_loaded,
3162                             &pf->internal_stats_offset.tx_multicast,
3163                             &pf->internal_stats.tx_multicast);
3164         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3165                             I40E_GLV_BPTCL(hw->port),
3166                             pf->offset_loaded,
3167                             &pf->internal_stats_offset.tx_broadcast,
3168                             &pf->internal_stats.tx_broadcast);
3169
3170         /* exclude CRC size */
3171         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3172                 pf->internal_stats.rx_multicast +
3173                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3174
3175         /* Get statistics of struct i40e_eth_stats */
3176         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3177                             I40E_GLPRT_GORCL(hw->port),
3178                             pf->offset_loaded, &os->eth.rx_bytes,
3179                             &ns->eth.rx_bytes);
3180         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3181                             I40E_GLPRT_UPRCL(hw->port),
3182                             pf->offset_loaded, &os->eth.rx_unicast,
3183                             &ns->eth.rx_unicast);
3184         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3185                             I40E_GLPRT_MPRCL(hw->port),
3186                             pf->offset_loaded, &os->eth.rx_multicast,
3187                             &ns->eth.rx_multicast);
3188         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3189                             I40E_GLPRT_BPRCL(hw->port),
3190                             pf->offset_loaded, &os->eth.rx_broadcast,
3191                             &ns->eth.rx_broadcast);
3192         /* Workaround: CRC size should not be included in byte statistics,
3193          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3194          * packet.
3195          */
3196         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3197                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3198
3199         /* exclude internal rx bytes
3200          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3201          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3202          * value.
3203          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3204          */
3205         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3206                 ns->eth.rx_bytes = 0;
3207         else
3208                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3209
3210         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3211                 ns->eth.rx_unicast = 0;
3212         else
3213                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3214
3215         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3216                 ns->eth.rx_multicast = 0;
3217         else
3218                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3219
3220         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3221                 ns->eth.rx_broadcast = 0;
3222         else
3223                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3224
3225         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3226                             pf->offset_loaded, &os->eth.rx_discards,
3227                             &ns->eth.rx_discards);
3228         /* GLPRT_REPC not supported */
3229         /* GLPRT_RMPC not supported */
3230         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3231                             pf->offset_loaded,
3232                             &os->eth.rx_unknown_protocol,
3233                             &ns->eth.rx_unknown_protocol);
3234         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3235                             I40E_GLPRT_GOTCL(hw->port),
3236                             pf->offset_loaded, &os->eth.tx_bytes,
3237                             &ns->eth.tx_bytes);
3238         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3239                             I40E_GLPRT_UPTCL(hw->port),
3240                             pf->offset_loaded, &os->eth.tx_unicast,
3241                             &ns->eth.tx_unicast);
3242         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3243                             I40E_GLPRT_MPTCL(hw->port),
3244                             pf->offset_loaded, &os->eth.tx_multicast,
3245                             &ns->eth.tx_multicast);
3246         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3247                             I40E_GLPRT_BPTCL(hw->port),
3248                             pf->offset_loaded, &os->eth.tx_broadcast,
3249                             &ns->eth.tx_broadcast);
3250         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3251                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3252
3253         /* exclude internal tx bytes
3254          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3255          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3256          * value.
3257          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3258          */
3259         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3260                 ns->eth.tx_bytes = 0;
3261         else
3262                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3263
3264         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3265                 ns->eth.tx_unicast = 0;
3266         else
3267                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3268
3269         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3270                 ns->eth.tx_multicast = 0;
3271         else
3272                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3273
3274         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3275                 ns->eth.tx_broadcast = 0;
3276         else
3277                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3278
3279         /* GLPRT_TEPC not supported */
3280
3281         /* additional port specific stats */
3282         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3283                             pf->offset_loaded, &os->tx_dropped_link_down,
3284                             &ns->tx_dropped_link_down);
3285         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3286                             pf->offset_loaded, &os->crc_errors,
3287                             &ns->crc_errors);
3288         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3289                             pf->offset_loaded, &os->illegal_bytes,
3290                             &ns->illegal_bytes);
3291         /* GLPRT_ERRBC not supported */
3292         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3293                             pf->offset_loaded, &os->mac_local_faults,
3294                             &ns->mac_local_faults);
3295         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3296                             pf->offset_loaded, &os->mac_remote_faults,
3297                             &ns->mac_remote_faults);
3298         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3299                             pf->offset_loaded, &os->rx_length_errors,
3300                             &ns->rx_length_errors);
3301         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3302                             pf->offset_loaded, &os->link_xon_rx,
3303                             &ns->link_xon_rx);
3304         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3305                             pf->offset_loaded, &os->link_xoff_rx,
3306                             &ns->link_xoff_rx);
3307         for (i = 0; i < 8; i++) {
3308                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3309                                     pf->offset_loaded,
3310                                     &os->priority_xon_rx[i],
3311                                     &ns->priority_xon_rx[i]);
3312                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3313                                     pf->offset_loaded,
3314                                     &os->priority_xoff_rx[i],
3315                                     &ns->priority_xoff_rx[i]);
3316         }
3317         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3318                             pf->offset_loaded, &os->link_xon_tx,
3319                             &ns->link_xon_tx);
3320         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3321                             pf->offset_loaded, &os->link_xoff_tx,
3322                             &ns->link_xoff_tx);
3323         for (i = 0; i < 8; i++) {
3324                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3325                                     pf->offset_loaded,
3326                                     &os->priority_xon_tx[i],
3327                                     &ns->priority_xon_tx[i]);
3328                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3329                                     pf->offset_loaded,
3330                                     &os->priority_xoff_tx[i],
3331                                     &ns->priority_xoff_tx[i]);
3332                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3333                                     pf->offset_loaded,
3334                                     &os->priority_xon_2_xoff[i],
3335                                     &ns->priority_xon_2_xoff[i]);
3336         }
3337         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3338                             I40E_GLPRT_PRC64L(hw->port),
3339                             pf->offset_loaded, &os->rx_size_64,
3340                             &ns->rx_size_64);
3341         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3342                             I40E_GLPRT_PRC127L(hw->port),
3343                             pf->offset_loaded, &os->rx_size_127,
3344                             &ns->rx_size_127);
3345         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3346                             I40E_GLPRT_PRC255L(hw->port),
3347                             pf->offset_loaded, &os->rx_size_255,
3348                             &ns->rx_size_255);
3349         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3350                             I40E_GLPRT_PRC511L(hw->port),
3351                             pf->offset_loaded, &os->rx_size_511,
3352                             &ns->rx_size_511);
3353         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3354                             I40E_GLPRT_PRC1023L(hw->port),
3355                             pf->offset_loaded, &os->rx_size_1023,
3356                             &ns->rx_size_1023);
3357         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3358                             I40E_GLPRT_PRC1522L(hw->port),
3359                             pf->offset_loaded, &os->rx_size_1522,
3360                             &ns->rx_size_1522);
3361         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3362                             I40E_GLPRT_PRC9522L(hw->port),
3363                             pf->offset_loaded, &os->rx_size_big,
3364                             &ns->rx_size_big);
3365         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3366                             pf->offset_loaded, &os->rx_undersize,
3367                             &ns->rx_undersize);
3368         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3369                             pf->offset_loaded, &os->rx_fragments,
3370                             &ns->rx_fragments);
3371         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3372                             pf->offset_loaded, &os->rx_oversize,
3373                             &ns->rx_oversize);
3374         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3375                             pf->offset_loaded, &os->rx_jabber,
3376                             &ns->rx_jabber);
3377         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3378                             I40E_GLPRT_PTC64L(hw->port),
3379                             pf->offset_loaded, &os->tx_size_64,
3380                             &ns->tx_size_64);
3381         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3382                             I40E_GLPRT_PTC127L(hw->port),
3383                             pf->offset_loaded, &os->tx_size_127,
3384                             &ns->tx_size_127);
3385         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3386                             I40E_GLPRT_PTC255L(hw->port),
3387                             pf->offset_loaded, &os->tx_size_255,
3388                             &ns->tx_size_255);
3389         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3390                             I40E_GLPRT_PTC511L(hw->port),
3391                             pf->offset_loaded, &os->tx_size_511,
3392                             &ns->tx_size_511);
3393         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3394                             I40E_GLPRT_PTC1023L(hw->port),
3395                             pf->offset_loaded, &os->tx_size_1023,
3396                             &ns->tx_size_1023);
3397         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3398                             I40E_GLPRT_PTC1522L(hw->port),
3399                             pf->offset_loaded, &os->tx_size_1522,
3400                             &ns->tx_size_1522);
3401         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3402                             I40E_GLPRT_PTC9522L(hw->port),
3403                             pf->offset_loaded, &os->tx_size_big,
3404                             &ns->tx_size_big);
3405         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3406                            pf->offset_loaded,
3407                            &os->fd_sb_match, &ns->fd_sb_match);
3408         /* GLPRT_MSPDC not supported */
3409         /* GLPRT_XEC not supported */
3410
3411         pf->offset_loaded = true;
3412
3413         if (pf->main_vsi)
3414                 i40e_update_vsi_stats(pf->main_vsi);
3415 }
3416
3417 /* Get all statistics of a port */
3418 static int
3419 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3420 {
3421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3423         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3424         struct i40e_vsi *vsi;
3425         unsigned i;
3426
3427         /* call read registers - updates values, now write them to struct */
3428         i40e_read_stats_registers(pf, hw);
3429
3430         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3431                         pf->main_vsi->eth_stats.rx_multicast +
3432                         pf->main_vsi->eth_stats.rx_broadcast -
3433                         pf->main_vsi->eth_stats.rx_discards;
3434         stats->opackets = ns->eth.tx_unicast +
3435                         ns->eth.tx_multicast +
3436                         ns->eth.tx_broadcast;
3437         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3438         stats->obytes   = ns->eth.tx_bytes;
3439         stats->oerrors  = ns->eth.tx_errors +
3440                         pf->main_vsi->eth_stats.tx_errors;
3441
3442         /* Rx Errors */
3443         stats->imissed  = ns->eth.rx_discards +
3444                         pf->main_vsi->eth_stats.rx_discards;
3445         stats->ierrors  = ns->crc_errors +
3446                         ns->rx_length_errors + ns->rx_undersize +
3447                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3448
3449         if (pf->vfs) {
3450                 for (i = 0; i < pf->vf_num; i++) {
3451                         vsi = pf->vfs[i].vsi;
3452                         i40e_update_vsi_stats(vsi);
3453
3454                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3455                                         vsi->eth_stats.rx_multicast +
3456                                         vsi->eth_stats.rx_broadcast -
3457                                         vsi->eth_stats.rx_discards);
3458                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3459                         stats->oerrors  += vsi->eth_stats.tx_errors;
3460                         stats->imissed  += vsi->eth_stats.rx_discards;
3461                 }
3462         }
3463
3464         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3465         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3466         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3467         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3468         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3469         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3470         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3471                     ns->eth.rx_unknown_protocol);
3472         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3473         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3474         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3475         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3476         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3477         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3478
3479         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3480                     ns->tx_dropped_link_down);
3481         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3482         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3483                     ns->illegal_bytes);
3484         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3485         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3486                     ns->mac_local_faults);
3487         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3488                     ns->mac_remote_faults);
3489         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3490                     ns->rx_length_errors);
3491         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3492         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3493         for (i = 0; i < 8; i++) {
3494                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3495                                 i, ns->priority_xon_rx[i]);
3496                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3497                                 i, ns->priority_xoff_rx[i]);
3498         }
3499         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3500         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3501         for (i = 0; i < 8; i++) {
3502                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3503                                 i, ns->priority_xon_tx[i]);
3504                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3505                                 i, ns->priority_xoff_tx[i]);
3506                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3507                                 i, ns->priority_xon_2_xoff[i]);
3508         }
3509         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3510         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3511         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3512         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3513         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3514         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3515         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3516         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3517         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3518         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3519         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3520         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3521         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3522         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3523         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3524         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3525         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3526         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3527         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3528                         ns->mac_short_packet_dropped);
3529         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3530                     ns->checksum_error);
3531         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3532         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3533         return 0;
3534 }
3535
3536 /* Reset the statistics */
3537 static int
3538 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3539 {
3540         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542
3543         /* Mark PF and VSI stats to update the offset, aka "reset" */
3544         pf->offset_loaded = false;
3545         if (pf->main_vsi)
3546                 pf->main_vsi->offset_loaded = false;
3547
3548         /* read the stats, reading current register values into offset */
3549         i40e_read_stats_registers(pf, hw);
3550
3551         return 0;
3552 }
3553
3554 static uint32_t
3555 i40e_xstats_calc_num(void)
3556 {
3557         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3558                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3559                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3560 }
3561
3562 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3563                                      struct rte_eth_xstat_name *xstats_names,
3564                                      __rte_unused unsigned limit)
3565 {
3566         unsigned count = 0;
3567         unsigned i, prio;
3568
3569         if (xstats_names == NULL)
3570                 return i40e_xstats_calc_num();
3571
3572         /* Note: limit checked in rte_eth_xstats_names() */
3573
3574         /* Get stats from i40e_eth_stats struct */
3575         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3576                 strlcpy(xstats_names[count].name,
3577                         rte_i40e_stats_strings[i].name,
3578                         sizeof(xstats_names[count].name));
3579                 count++;
3580         }
3581
3582         /* Get individiual stats from i40e_hw_port struct */
3583         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3584                 strlcpy(xstats_names[count].name,
3585                         rte_i40e_hw_port_strings[i].name,
3586                         sizeof(xstats_names[count].name));
3587                 count++;
3588         }
3589
3590         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3591                 for (prio = 0; prio < 8; prio++) {
3592                         snprintf(xstats_names[count].name,
3593                                  sizeof(xstats_names[count].name),
3594                                  "rx_priority%u_%s", prio,
3595                                  rte_i40e_rxq_prio_strings[i].name);
3596                         count++;
3597                 }
3598         }
3599
3600         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3601                 for (prio = 0; prio < 8; prio++) {
3602                         snprintf(xstats_names[count].name,
3603                                  sizeof(xstats_names[count].name),
3604                                  "tx_priority%u_%s", prio,
3605                                  rte_i40e_txq_prio_strings[i].name);
3606                         count++;
3607                 }
3608         }
3609         return count;
3610 }
3611
3612 static int
3613 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3614                     unsigned n)
3615 {
3616         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         unsigned i, count, prio;
3619         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3620
3621         count = i40e_xstats_calc_num();
3622         if (n < count)
3623                 return count;
3624
3625         i40e_read_stats_registers(pf, hw);
3626
3627         if (xstats == NULL)
3628                 return 0;
3629
3630         count = 0;
3631
3632         /* Get stats from i40e_eth_stats struct */
3633         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3634                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3635                         rte_i40e_stats_strings[i].offset);
3636                 xstats[count].id = count;
3637                 count++;
3638         }
3639
3640         /* Get individiual stats from i40e_hw_port struct */
3641         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3642                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3643                         rte_i40e_hw_port_strings[i].offset);
3644                 xstats[count].id = count;
3645                 count++;
3646         }
3647
3648         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3649                 for (prio = 0; prio < 8; prio++) {
3650                         xstats[count].value =
3651                                 *(uint64_t *)(((char *)hw_stats) +
3652                                 rte_i40e_rxq_prio_strings[i].offset +
3653                                 (sizeof(uint64_t) * prio));
3654                         xstats[count].id = count;
3655                         count++;
3656                 }
3657         }
3658
3659         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3660                 for (prio = 0; prio < 8; prio++) {
3661                         xstats[count].value =
3662                                 *(uint64_t *)(((char *)hw_stats) +
3663                                 rte_i40e_txq_prio_strings[i].offset +
3664                                 (sizeof(uint64_t) * prio));
3665                         xstats[count].id = count;
3666                         count++;
3667                 }
3668         }
3669
3670         return count;
3671 }
3672
3673 static int
3674 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3675 {
3676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3677         u32 full_ver;
3678         u8 ver, patch;
3679         u16 build;
3680         int ret;
3681
3682         full_ver = hw->nvm.oem_ver;
3683         ver = (u8)(full_ver >> 24);
3684         build = (u16)((full_ver >> 8) & 0xffff);
3685         patch = (u8)(full_ver & 0xff);
3686
3687         ret = snprintf(fw_version, fw_size,
3688                  "%d.%d%d 0x%08x %d.%d.%d",
3689                  ((hw->nvm.version >> 12) & 0xf),
3690                  ((hw->nvm.version >> 4) & 0xff),
3691                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3692                  ver, build, patch);
3693
3694         ret += 1; /* add the size of '\0' */
3695         if (fw_size < (u32)ret)
3696                 return ret;
3697         else
3698                 return 0;
3699 }
3700
3701 /*
3702  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3703  * the Rx data path does not hang if the FW LLDP is stopped.
3704  * return true if lldp need to stop
3705  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3706  */
3707 static bool
3708 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3709 {
3710         double nvm_ver;
3711         char ver_str[64] = {0};
3712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3713
3714         i40e_fw_version_get(dev, ver_str, 64);
3715         nvm_ver = atof(ver_str);
3716         if ((hw->mac.type == I40E_MAC_X722 ||
3717              hw->mac.type == I40E_MAC_X722_VF) &&
3718              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3719                 return true;
3720         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3721                 return true;
3722
3723         return false;
3724 }
3725
3726 static int
3727 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3728 {
3729         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3730         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3731         struct i40e_vsi *vsi = pf->main_vsi;
3732         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3733
3734         dev_info->max_rx_queues = vsi->nb_qps;
3735         dev_info->max_tx_queues = vsi->nb_qps;
3736         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3737         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3738         dev_info->max_mac_addrs = vsi->max_macaddrs;
3739         dev_info->max_vfs = pci_dev->max_vfs;
3740         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3741         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3742         dev_info->rx_queue_offload_capa = 0;
3743         dev_info->rx_offload_capa =
3744                 DEV_RX_OFFLOAD_VLAN_STRIP |
3745                 DEV_RX_OFFLOAD_QINQ_STRIP |
3746                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3747                 DEV_RX_OFFLOAD_UDP_CKSUM |
3748                 DEV_RX_OFFLOAD_TCP_CKSUM |
3749                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3750                 DEV_RX_OFFLOAD_KEEP_CRC |
3751                 DEV_RX_OFFLOAD_SCATTER |
3752                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3753                 DEV_RX_OFFLOAD_VLAN_FILTER |
3754                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3755                 DEV_RX_OFFLOAD_RSS_HASH;
3756
3757         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3758         dev_info->tx_offload_capa =
3759                 DEV_TX_OFFLOAD_VLAN_INSERT |
3760                 DEV_TX_OFFLOAD_QINQ_INSERT |
3761                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3762                 DEV_TX_OFFLOAD_UDP_CKSUM |
3763                 DEV_TX_OFFLOAD_TCP_CKSUM |
3764                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3765                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3766                 DEV_TX_OFFLOAD_TCP_TSO |
3767                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3768                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3769                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3770                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3771                 DEV_TX_OFFLOAD_MULTI_SEGS |
3772                 dev_info->tx_queue_offload_capa;
3773         dev_info->dev_capa =
3774                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3775                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3776
3777         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3778                                                 sizeof(uint32_t);
3779         dev_info->reta_size = pf->hash_lut_size;
3780         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3781
3782         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3783                 .rx_thresh = {
3784                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3785                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3786                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3787                 },
3788                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3789                 .rx_drop_en = 0,
3790                 .offloads = 0,
3791         };
3792
3793         dev_info->default_txconf = (struct rte_eth_txconf) {
3794                 .tx_thresh = {
3795                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3796                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3797                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3798                 },
3799                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3800                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3801                 .offloads = 0,
3802         };
3803
3804         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3805                 .nb_max = I40E_MAX_RING_DESC,
3806                 .nb_min = I40E_MIN_RING_DESC,
3807                 .nb_align = I40E_ALIGN_RING_DESC,
3808         };
3809
3810         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3811                 .nb_max = I40E_MAX_RING_DESC,
3812                 .nb_min = I40E_MIN_RING_DESC,
3813                 .nb_align = I40E_ALIGN_RING_DESC,
3814                 .nb_seg_max = I40E_TX_MAX_SEG,
3815                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3816         };
3817
3818         if (pf->flags & I40E_FLAG_VMDQ) {
3819                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3820                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3821                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3822                                                 pf->max_nb_vmdq_vsi;
3823                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3824                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3825                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3826         }
3827
3828         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3829                 /* For XL710 */
3830                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3831                 dev_info->default_rxportconf.nb_queues = 2;
3832                 dev_info->default_txportconf.nb_queues = 2;
3833                 if (dev->data->nb_rx_queues == 1)
3834                         dev_info->default_rxportconf.ring_size = 2048;
3835                 else
3836                         dev_info->default_rxportconf.ring_size = 1024;
3837                 if (dev->data->nb_tx_queues == 1)
3838                         dev_info->default_txportconf.ring_size = 1024;
3839                 else
3840                         dev_info->default_txportconf.ring_size = 512;
3841
3842         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3843                 /* For XXV710 */
3844                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3845                 dev_info->default_rxportconf.nb_queues = 1;
3846                 dev_info->default_txportconf.nb_queues = 1;
3847                 dev_info->default_rxportconf.ring_size = 256;
3848                 dev_info->default_txportconf.ring_size = 256;
3849         } else {
3850                 /* For X710 */
3851                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3852                 dev_info->default_rxportconf.nb_queues = 1;
3853                 dev_info->default_txportconf.nb_queues = 1;
3854                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3855                         dev_info->default_rxportconf.ring_size = 512;
3856                         dev_info->default_txportconf.ring_size = 256;
3857                 } else {
3858                         dev_info->default_rxportconf.ring_size = 256;
3859                         dev_info->default_txportconf.ring_size = 256;
3860                 }
3861         }
3862         dev_info->default_rxportconf.burst_size = 32;
3863         dev_info->default_txportconf.burst_size = 32;
3864
3865         return 0;
3866 }
3867
3868 static int
3869 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3870 {
3871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3872         struct i40e_vsi *vsi = pf->main_vsi;
3873         PMD_INIT_FUNC_TRACE();
3874
3875         if (on)
3876                 return i40e_vsi_add_vlan(vsi, vlan_id);
3877         else
3878                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3879 }
3880
3881 static int
3882 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3883                                 enum rte_vlan_type vlan_type,
3884                                 uint16_t tpid, int qinq)
3885 {
3886         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3887         uint64_t reg_r = 0;
3888         uint64_t reg_w = 0;
3889         uint16_t reg_id = 3;
3890         int ret;
3891
3892         if (qinq) {
3893                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3894                         reg_id = 2;
3895         }
3896
3897         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3898                                           &reg_r, NULL);
3899         if (ret != I40E_SUCCESS) {
3900                 PMD_DRV_LOG(ERR,
3901                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3902                            reg_id);
3903                 return -EIO;
3904         }
3905         PMD_DRV_LOG(DEBUG,
3906                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3907                     reg_id, reg_r);
3908
3909         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3910         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3911         if (reg_r == reg_w) {
3912                 PMD_DRV_LOG(DEBUG, "No need to write");
3913                 return 0;
3914         }
3915
3916         ret = i40e_aq_debug_write_global_register(hw,
3917                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3918                                            reg_w, NULL);
3919         if (ret != I40E_SUCCESS) {
3920                 PMD_DRV_LOG(ERR,
3921                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3922                             reg_id);
3923                 return -EIO;
3924         }
3925         PMD_DRV_LOG(DEBUG,
3926                     "Global register 0x%08x is changed with value 0x%08x",
3927                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3928
3929         return 0;
3930 }
3931
3932 static int
3933 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3934                    enum rte_vlan_type vlan_type,
3935                    uint16_t tpid)
3936 {
3937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3939         int qinq = dev->data->dev_conf.rxmode.offloads &
3940                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3941         int ret = 0;
3942
3943         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3944              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3945             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3946                 PMD_DRV_LOG(ERR,
3947                             "Unsupported vlan type.");
3948                 return -EINVAL;
3949         }
3950
3951         if (pf->support_multi_driver) {
3952                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3953                 return -ENOTSUP;
3954         }
3955
3956         /* 802.1ad frames ability is added in NVM API 1.7*/
3957         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3958                 if (qinq) {
3959                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3960                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3961                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3962                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3963                 } else {
3964                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3965                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3966                 }
3967                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3968                 if (ret != I40E_SUCCESS) {
3969                         PMD_DRV_LOG(ERR,
3970                                     "Set switch config failed aq_err: %d",
3971                                     hw->aq.asq_last_status);
3972                         ret = -EIO;
3973                 }
3974         } else
3975                 /* If NVM API < 1.7, keep the register setting */
3976                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3977                                                       tpid, qinq);
3978
3979         return ret;
3980 }
3981
3982 static int
3983 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3984 {
3985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3986         struct i40e_vsi *vsi = pf->main_vsi;
3987         struct rte_eth_rxmode *rxmode;
3988
3989         rxmode = &dev->data->dev_conf.rxmode;
3990         if (mask & ETH_VLAN_FILTER_MASK) {
3991                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3992                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3993                 else
3994                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3995         }
3996
3997         if (mask & ETH_VLAN_STRIP_MASK) {
3998                 /* Enable or disable VLAN stripping */
3999                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4000                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4001                 else
4002                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4003         }
4004
4005         if (mask & ETH_VLAN_EXTEND_MASK) {
4006                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4007                         i40e_vsi_config_double_vlan(vsi, TRUE);
4008                         /* Set global registers with default ethertype. */
4009                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4010                                            RTE_ETHER_TYPE_VLAN);
4011                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4012                                            RTE_ETHER_TYPE_VLAN);
4013                 }
4014                 else
4015                         i40e_vsi_config_double_vlan(vsi, FALSE);
4016         }
4017
4018         return 0;
4019 }
4020
4021 static void
4022 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4023                           __rte_unused uint16_t queue,
4024                           __rte_unused int on)
4025 {
4026         PMD_INIT_FUNC_TRACE();
4027 }
4028
4029 static int
4030 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4031 {
4032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4033         struct i40e_vsi *vsi = pf->main_vsi;
4034         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4035         struct i40e_vsi_vlan_pvid_info info;
4036
4037         memset(&info, 0, sizeof(info));
4038         info.on = on;
4039         if (info.on)
4040                 info.config.pvid = pvid;
4041         else {
4042                 info.config.reject.tagged =
4043                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4044                 info.config.reject.untagged =
4045                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4046         }
4047
4048         return i40e_vsi_vlan_pvid_set(vsi, &info);
4049 }
4050
4051 static int
4052 i40e_dev_led_on(struct rte_eth_dev *dev)
4053 {
4054         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         uint32_t mode = i40e_led_get(hw);
4056
4057         if (mode == 0)
4058                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4059
4060         return 0;
4061 }
4062
4063 static int
4064 i40e_dev_led_off(struct rte_eth_dev *dev)
4065 {
4066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4067         uint32_t mode = i40e_led_get(hw);
4068
4069         if (mode != 0)
4070                 i40e_led_set(hw, 0, false);
4071
4072         return 0;
4073 }
4074
4075 static int
4076 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4077 {
4078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080
4081         fc_conf->pause_time = pf->fc_conf.pause_time;
4082
4083         /* read out from register, in case they are modified by other port */
4084         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4085                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4086         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4087                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4088
4089         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4090         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4091
4092          /* Return current mode according to actual setting*/
4093         switch (hw->fc.current_mode) {
4094         case I40E_FC_FULL:
4095                 fc_conf->mode = RTE_FC_FULL;
4096                 break;
4097         case I40E_FC_TX_PAUSE:
4098                 fc_conf->mode = RTE_FC_TX_PAUSE;
4099                 break;
4100         case I40E_FC_RX_PAUSE:
4101                 fc_conf->mode = RTE_FC_RX_PAUSE;
4102                 break;
4103         case I40E_FC_NONE:
4104         default:
4105                 fc_conf->mode = RTE_FC_NONE;
4106         };
4107
4108         return 0;
4109 }
4110
4111 static int
4112 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4113 {
4114         uint32_t mflcn_reg, fctrl_reg, reg;
4115         uint32_t max_high_water;
4116         uint8_t i, aq_failure;
4117         int err;
4118         struct i40e_hw *hw;
4119         struct i40e_pf *pf;
4120         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4121                 [RTE_FC_NONE] = I40E_FC_NONE,
4122                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4123                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4124                 [RTE_FC_FULL] = I40E_FC_FULL
4125         };
4126
4127         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4128
4129         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4130         if ((fc_conf->high_water > max_high_water) ||
4131                         (fc_conf->high_water < fc_conf->low_water)) {
4132                 PMD_INIT_LOG(ERR,
4133                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4134                         max_high_water);
4135                 return -EINVAL;
4136         }
4137
4138         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4140         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4141
4142         pf->fc_conf.pause_time = fc_conf->pause_time;
4143         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4144         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4145
4146         PMD_INIT_FUNC_TRACE();
4147
4148         /* All the link flow control related enable/disable register
4149          * configuration is handle by the F/W
4150          */
4151         err = i40e_set_fc(hw, &aq_failure, true);
4152         if (err < 0)
4153                 return -ENOSYS;
4154
4155         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4156                 /* Configure flow control refresh threshold,
4157                  * the value for stat_tx_pause_refresh_timer[8]
4158                  * is used for global pause operation.
4159                  */
4160
4161                 I40E_WRITE_REG(hw,
4162                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4163                                pf->fc_conf.pause_time);
4164
4165                 /* configure the timer value included in transmitted pause
4166                  * frame,
4167                  * the value for stat_tx_pause_quanta[8] is used for global
4168                  * pause operation
4169                  */
4170                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4171                                pf->fc_conf.pause_time);
4172
4173                 fctrl_reg = I40E_READ_REG(hw,
4174                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4175
4176                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4177                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4178                 else
4179                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4180
4181                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4182                                fctrl_reg);
4183         } else {
4184                 /* Configure pause time (2 TCs per register) */
4185                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4186                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4187                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4188
4189                 /* Configure flow control refresh threshold value */
4190                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4191                                pf->fc_conf.pause_time / 2);
4192
4193                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4194
4195                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4196                  *depending on configuration
4197                  */
4198                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4199                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4200                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4201                 } else {
4202                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4203                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4204                 }
4205
4206                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4207         }
4208
4209         if (!pf->support_multi_driver) {
4210                 /* config water marker both based on the packets and bytes */
4211                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4212                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4213                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4214                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4215                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4216                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4217                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4218                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4219                                   << I40E_KILOSHIFT);
4220                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4221                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4222                                    << I40E_KILOSHIFT);
4223         } else {
4224                 PMD_DRV_LOG(ERR,
4225                             "Water marker configuration is not supported.");
4226         }
4227
4228         I40E_WRITE_FLUSH(hw);
4229
4230         return 0;
4231 }
4232
4233 static int
4234 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4235                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4236 {
4237         PMD_INIT_FUNC_TRACE();
4238
4239         return -ENOSYS;
4240 }
4241
4242 /* Add a MAC address, and update filters */
4243 static int
4244 i40e_macaddr_add(struct rte_eth_dev *dev,
4245                  struct rte_ether_addr *mac_addr,
4246                  __rte_unused uint32_t index,
4247                  uint32_t pool)
4248 {
4249         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4250         struct i40e_mac_filter_info mac_filter;
4251         struct i40e_vsi *vsi;
4252         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4253         int ret;
4254
4255         /* If VMDQ not enabled or configured, return */
4256         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4257                           !pf->nb_cfg_vmdq_vsi)) {
4258                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4259                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4260                         pool);
4261                 return -ENOTSUP;
4262         }
4263
4264         if (pool > pf->nb_cfg_vmdq_vsi) {
4265                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4266                                 pool, pf->nb_cfg_vmdq_vsi);
4267                 return -EINVAL;
4268         }
4269
4270         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4271         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4272                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4273         else
4274                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4275
4276         if (pool == 0)
4277                 vsi = pf->main_vsi;
4278         else
4279                 vsi = pf->vmdq[pool - 1].vsi;
4280
4281         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4282         if (ret != I40E_SUCCESS) {
4283                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4284                 return -ENODEV;
4285         }
4286         return 0;
4287 }
4288
4289 /* Remove a MAC address, and update filters */
4290 static void
4291 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4292 {
4293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4294         struct i40e_vsi *vsi;
4295         struct rte_eth_dev_data *data = dev->data;
4296         struct rte_ether_addr *macaddr;
4297         int ret;
4298         uint32_t i;
4299         uint64_t pool_sel;
4300
4301         macaddr = &(data->mac_addrs[index]);
4302
4303         pool_sel = dev->data->mac_pool_sel[index];
4304
4305         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4306                 if (pool_sel & (1ULL << i)) {
4307                         if (i == 0)
4308                                 vsi = pf->main_vsi;
4309                         else {
4310                                 /* No VMDQ pool enabled or configured */
4311                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4312                                         (i > pf->nb_cfg_vmdq_vsi)) {
4313                                         PMD_DRV_LOG(ERR,
4314                                                 "No VMDQ pool enabled/configured");
4315                                         return;
4316                                 }
4317                                 vsi = pf->vmdq[i - 1].vsi;
4318                         }
4319                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4320
4321                         if (ret) {
4322                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4323                                 return;
4324                         }
4325                 }
4326         }
4327 }
4328
4329 /* Set perfect match or hash match of MAC and VLAN for a VF */
4330 static int
4331 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4332                  struct rte_eth_mac_filter *filter,
4333                  bool add)
4334 {
4335         struct i40e_hw *hw;
4336         struct i40e_mac_filter_info mac_filter;
4337         struct rte_ether_addr old_mac;
4338         struct rte_ether_addr *new_mac;
4339         struct i40e_pf_vf *vf = NULL;
4340         uint16_t vf_id;
4341         int ret;
4342
4343         if (pf == NULL) {
4344                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4345                 return -EINVAL;
4346         }
4347         hw = I40E_PF_TO_HW(pf);
4348
4349         if (filter == NULL) {
4350                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4351                 return -EINVAL;
4352         }
4353
4354         new_mac = &filter->mac_addr;
4355
4356         if (rte_is_zero_ether_addr(new_mac)) {
4357                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4358                 return -EINVAL;
4359         }
4360
4361         vf_id = filter->dst_id;
4362
4363         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4364                 PMD_DRV_LOG(ERR, "Invalid argument.");
4365                 return -EINVAL;
4366         }
4367         vf = &pf->vfs[vf_id];
4368
4369         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4370                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4371                 return -EINVAL;
4372         }
4373
4374         if (add) {
4375                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4376                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4377                                 RTE_ETHER_ADDR_LEN);
4378                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4379                                  RTE_ETHER_ADDR_LEN);
4380
4381                 mac_filter.filter_type = filter->filter_type;
4382                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4383                 if (ret != I40E_SUCCESS) {
4384                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4385                         return -1;
4386                 }
4387                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4388         } else {
4389                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4390                                 RTE_ETHER_ADDR_LEN);
4391                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4392                 if (ret != I40E_SUCCESS) {
4393                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4394                         return -1;
4395                 }
4396
4397                 /* Clear device address as it has been removed */
4398                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4399                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4400         }
4401
4402         return 0;
4403 }
4404
4405 /* MAC filter handle */
4406 static int
4407 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4408                 void *arg)
4409 {
4410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4411         struct rte_eth_mac_filter *filter;
4412         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4413         int ret = I40E_NOT_SUPPORTED;
4414
4415         filter = (struct rte_eth_mac_filter *)(arg);
4416
4417         switch (filter_op) {
4418         case RTE_ETH_FILTER_NOP:
4419                 ret = I40E_SUCCESS;
4420                 break;
4421         case RTE_ETH_FILTER_ADD:
4422                 i40e_pf_disable_irq0(hw);
4423                 if (filter->is_vf)
4424                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4425                 i40e_pf_enable_irq0(hw);
4426                 break;
4427         case RTE_ETH_FILTER_DELETE:
4428                 i40e_pf_disable_irq0(hw);
4429                 if (filter->is_vf)
4430                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4431                 i40e_pf_enable_irq0(hw);
4432                 break;
4433         default:
4434                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4435                 ret = I40E_ERR_PARAM;
4436                 break;
4437         }
4438
4439         return ret;
4440 }
4441
4442 static int
4443 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4444 {
4445         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4446         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4447         uint32_t reg;
4448         int ret;
4449
4450         if (!lut)
4451                 return -EINVAL;
4452
4453         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4454                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4455                                           vsi->type != I40E_VSI_SRIOV,
4456                                           lut, lut_size);
4457                 if (ret) {
4458                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4459                         return ret;
4460                 }
4461         } else {
4462                 uint32_t *lut_dw = (uint32_t *)lut;
4463                 uint16_t i, lut_size_dw = lut_size / 4;
4464
4465                 if (vsi->type == I40E_VSI_SRIOV) {
4466                         for (i = 0; i <= lut_size_dw; i++) {
4467                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4468                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4469                         }
4470                 } else {
4471                         for (i = 0; i < lut_size_dw; i++)
4472                                 lut_dw[i] = I40E_READ_REG(hw,
4473                                                           I40E_PFQF_HLUT(i));
4474                 }
4475         }
4476
4477         return 0;
4478 }
4479
4480 int
4481 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4482 {
4483         struct i40e_pf *pf;
4484         struct i40e_hw *hw;
4485         int ret;
4486
4487         if (!vsi || !lut)
4488                 return -EINVAL;
4489
4490         pf = I40E_VSI_TO_PF(vsi);
4491         hw = I40E_VSI_TO_HW(vsi);
4492
4493         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4494                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4495                                           vsi->type != I40E_VSI_SRIOV,
4496                                           lut, lut_size);
4497                 if (ret) {
4498                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4499                         return ret;
4500                 }
4501         } else {
4502                 uint32_t *lut_dw = (uint32_t *)lut;
4503                 uint16_t i, lut_size_dw = lut_size / 4;
4504
4505                 if (vsi->type == I40E_VSI_SRIOV) {
4506                         for (i = 0; i < lut_size_dw; i++)
4507                                 I40E_WRITE_REG(
4508                                         hw,
4509                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4510                                         lut_dw[i]);
4511                 } else {
4512                         for (i = 0; i < lut_size_dw; i++)
4513                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4514                                                lut_dw[i]);
4515                 }
4516                 I40E_WRITE_FLUSH(hw);
4517         }
4518
4519         return 0;
4520 }
4521
4522 static int
4523 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4524                          struct rte_eth_rss_reta_entry64 *reta_conf,
4525                          uint16_t reta_size)
4526 {
4527         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4528         uint16_t i, lut_size = pf->hash_lut_size;
4529         uint16_t idx, shift;
4530         uint8_t *lut;
4531         int ret;
4532
4533         if (reta_size != lut_size ||
4534                 reta_size > ETH_RSS_RETA_SIZE_512) {
4535                 PMD_DRV_LOG(ERR,
4536                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4537                         reta_size, lut_size);
4538                 return -EINVAL;
4539         }
4540
4541         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4542         if (!lut) {
4543                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4544                 return -ENOMEM;
4545         }
4546         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4547         if (ret)
4548                 goto out;
4549         for (i = 0; i < reta_size; i++) {
4550                 idx = i / RTE_RETA_GROUP_SIZE;
4551                 shift = i % RTE_RETA_GROUP_SIZE;
4552                 if (reta_conf[idx].mask & (1ULL << shift))
4553                         lut[i] = reta_conf[idx].reta[shift];
4554         }
4555         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4556
4557         pf->adapter->rss_reta_updated = 1;
4558
4559 out:
4560         rte_free(lut);
4561
4562         return ret;
4563 }
4564
4565 static int
4566 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4567                         struct rte_eth_rss_reta_entry64 *reta_conf,
4568                         uint16_t reta_size)
4569 {
4570         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4571         uint16_t i, lut_size = pf->hash_lut_size;
4572         uint16_t idx, shift;
4573         uint8_t *lut;
4574         int ret;
4575
4576         if (reta_size != lut_size ||
4577                 reta_size > ETH_RSS_RETA_SIZE_512) {
4578                 PMD_DRV_LOG(ERR,
4579                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4580                         reta_size, lut_size);
4581                 return -EINVAL;
4582         }
4583
4584         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4585         if (!lut) {
4586                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4587                 return -ENOMEM;
4588         }
4589
4590         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4591         if (ret)
4592                 goto out;
4593         for (i = 0; i < reta_size; i++) {
4594                 idx = i / RTE_RETA_GROUP_SIZE;
4595                 shift = i % RTE_RETA_GROUP_SIZE;
4596                 if (reta_conf[idx].mask & (1ULL << shift))
4597                         reta_conf[idx].reta[shift] = lut[i];
4598         }
4599
4600 out:
4601         rte_free(lut);
4602
4603         return ret;
4604 }
4605
4606 /**
4607  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4608  * @hw:   pointer to the HW structure
4609  * @mem:  pointer to mem struct to fill out
4610  * @size: size of memory requested
4611  * @alignment: what to align the allocation to
4612  **/
4613 enum i40e_status_code
4614 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4615                         struct i40e_dma_mem *mem,
4616                         u64 size,
4617                         u32 alignment)
4618 {
4619         const struct rte_memzone *mz = NULL;
4620         char z_name[RTE_MEMZONE_NAMESIZE];
4621
4622         if (!mem)
4623                 return I40E_ERR_PARAM;
4624
4625         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4626         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4627                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4628         if (!mz)
4629                 return I40E_ERR_NO_MEMORY;
4630
4631         mem->size = size;
4632         mem->va = mz->addr;
4633         mem->pa = mz->iova;
4634         mem->zone = (const void *)mz;
4635         PMD_DRV_LOG(DEBUG,
4636                 "memzone %s allocated with physical address: %"PRIu64,
4637                 mz->name, mem->pa);
4638
4639         return I40E_SUCCESS;
4640 }
4641
4642 /**
4643  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4644  * @hw:   pointer to the HW structure
4645  * @mem:  ptr to mem struct to free
4646  **/
4647 enum i40e_status_code
4648 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4649                     struct i40e_dma_mem *mem)
4650 {
4651         if (!mem)
4652                 return I40E_ERR_PARAM;
4653
4654         PMD_DRV_LOG(DEBUG,
4655                 "memzone %s to be freed with physical address: %"PRIu64,
4656                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4657         rte_memzone_free((const struct rte_memzone *)mem->zone);
4658         mem->zone = NULL;
4659         mem->va = NULL;
4660         mem->pa = (u64)0;
4661
4662         return I40E_SUCCESS;
4663 }
4664
4665 /**
4666  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4667  * @hw:   pointer to the HW structure
4668  * @mem:  pointer to mem struct to fill out
4669  * @size: size of memory requested
4670  **/
4671 enum i40e_status_code
4672 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4673                          struct i40e_virt_mem *mem,
4674                          u32 size)
4675 {
4676         if (!mem)
4677                 return I40E_ERR_PARAM;
4678
4679         mem->size = size;
4680         mem->va = rte_zmalloc("i40e", size, 0);
4681
4682         if (mem->va)
4683                 return I40E_SUCCESS;
4684         else
4685                 return I40E_ERR_NO_MEMORY;
4686 }
4687
4688 /**
4689  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4690  * @hw:   pointer to the HW structure
4691  * @mem:  pointer to mem struct to free
4692  **/
4693 enum i40e_status_code
4694 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4695                      struct i40e_virt_mem *mem)
4696 {
4697         if (!mem)
4698                 return I40E_ERR_PARAM;
4699
4700         rte_free(mem->va);
4701         mem->va = NULL;
4702
4703         return I40E_SUCCESS;
4704 }
4705
4706 void
4707 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4708 {
4709         rte_spinlock_init(&sp->spinlock);
4710 }
4711
4712 void
4713 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4714 {
4715         rte_spinlock_lock(&sp->spinlock);
4716 }
4717
4718 void
4719 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4720 {
4721         rte_spinlock_unlock(&sp->spinlock);
4722 }
4723
4724 void
4725 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4726 {
4727         return;
4728 }
4729
4730 /**
4731  * Get the hardware capabilities, which will be parsed
4732  * and saved into struct i40e_hw.
4733  */
4734 static int
4735 i40e_get_cap(struct i40e_hw *hw)
4736 {
4737         struct i40e_aqc_list_capabilities_element_resp *buf;
4738         uint16_t len, size = 0;
4739         int ret;
4740
4741         /* Calculate a huge enough buff for saving response data temporarily */
4742         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4743                                                 I40E_MAX_CAP_ELE_NUM;
4744         buf = rte_zmalloc("i40e", len, 0);
4745         if (!buf) {
4746                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4747                 return I40E_ERR_NO_MEMORY;
4748         }
4749
4750         /* Get, parse the capabilities and save it to hw */
4751         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4752                         i40e_aqc_opc_list_func_capabilities, NULL);
4753         if (ret != I40E_SUCCESS)
4754                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4755
4756         /* Free the temporary buffer after being used */
4757         rte_free(buf);
4758
4759         return ret;
4760 }
4761
4762 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4763
4764 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4765                 const char *value,
4766                 void *opaque)
4767 {
4768         struct i40e_pf *pf;
4769         unsigned long num;
4770         char *end;
4771
4772         pf = (struct i40e_pf *)opaque;
4773         RTE_SET_USED(key);
4774
4775         errno = 0;
4776         num = strtoul(value, &end, 0);
4777         if (errno != 0 || end == value || *end != 0) {
4778                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4779                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4780                 return -(EINVAL);
4781         }
4782
4783         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4784                 pf->vf_nb_qp_max = (uint16_t)num;
4785         else
4786                 /* here return 0 to make next valid same argument work */
4787                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4788                             "power of 2 and equal or less than 16 !, Now it is "
4789                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4790
4791         return 0;
4792 }
4793
4794 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4795 {
4796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4797         struct rte_kvargs *kvlist;
4798         int kvargs_count;
4799
4800         /* set default queue number per VF as 4 */
4801         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4802
4803         if (dev->device->devargs == NULL)
4804                 return 0;
4805
4806         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4807         if (kvlist == NULL)
4808                 return -(EINVAL);
4809
4810         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4811         if (!kvargs_count) {
4812                 rte_kvargs_free(kvlist);
4813                 return 0;
4814         }
4815
4816         if (kvargs_count > 1)
4817                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4818                             "the first invalid or last valid one is used !",
4819                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4820
4821         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4822                            i40e_pf_parse_vf_queue_number_handler, pf);
4823
4824         rte_kvargs_free(kvlist);
4825
4826         return 0;
4827 }
4828
4829 static int
4830 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4831 {
4832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4833         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4835         uint16_t qp_count = 0, vsi_count = 0;
4836
4837         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4838                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4839                 return -EINVAL;
4840         }
4841
4842         i40e_pf_config_vf_rxq_number(dev);
4843
4844         /* Add the parameter init for LFC */
4845         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4846         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4847         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4848
4849         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4850         pf->max_num_vsi = hw->func_caps.num_vsis;
4851         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4852         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4853
4854         /* FDir queue/VSI allocation */
4855         pf->fdir_qp_offset = 0;
4856         if (hw->func_caps.fd) {
4857                 pf->flags |= I40E_FLAG_FDIR;
4858                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4859         } else {
4860                 pf->fdir_nb_qps = 0;
4861         }
4862         qp_count += pf->fdir_nb_qps;
4863         vsi_count += 1;
4864
4865         /* LAN queue/VSI allocation */
4866         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4867         if (!hw->func_caps.rss) {
4868                 pf->lan_nb_qps = 1;
4869         } else {
4870                 pf->flags |= I40E_FLAG_RSS;
4871                 if (hw->mac.type == I40E_MAC_X722)
4872                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4873                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4874         }
4875         qp_count += pf->lan_nb_qps;
4876         vsi_count += 1;
4877
4878         /* VF queue/VSI allocation */
4879         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4880         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4881                 pf->flags |= I40E_FLAG_SRIOV;
4882                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4883                 pf->vf_num = pci_dev->max_vfs;
4884                 PMD_DRV_LOG(DEBUG,
4885                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4886                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4887         } else {
4888                 pf->vf_nb_qps = 0;
4889                 pf->vf_num = 0;
4890         }
4891         qp_count += pf->vf_nb_qps * pf->vf_num;
4892         vsi_count += pf->vf_num;
4893
4894         /* VMDq queue/VSI allocation */
4895         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4896         pf->vmdq_nb_qps = 0;
4897         pf->max_nb_vmdq_vsi = 0;
4898         if (hw->func_caps.vmdq) {
4899                 if (qp_count < hw->func_caps.num_tx_qp &&
4900                         vsi_count < hw->func_caps.num_vsis) {
4901                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4902                                 qp_count) / pf->vmdq_nb_qp_max;
4903
4904                         /* Limit the maximum number of VMDq vsi to the maximum
4905                          * ethdev can support
4906                          */
4907                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4908                                 hw->func_caps.num_vsis - vsi_count);
4909                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4910                                 ETH_64_POOLS);
4911                         if (pf->max_nb_vmdq_vsi) {
4912                                 pf->flags |= I40E_FLAG_VMDQ;
4913                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4914                                 PMD_DRV_LOG(DEBUG,
4915                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4916                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4917                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4918                         } else {
4919                                 PMD_DRV_LOG(INFO,
4920                                         "No enough queues left for VMDq");
4921                         }
4922                 } else {
4923                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4924                 }
4925         }
4926         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4927         vsi_count += pf->max_nb_vmdq_vsi;
4928
4929         if (hw->func_caps.dcb)
4930                 pf->flags |= I40E_FLAG_DCB;
4931
4932         if (qp_count > hw->func_caps.num_tx_qp) {
4933                 PMD_DRV_LOG(ERR,
4934                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4935                         qp_count, hw->func_caps.num_tx_qp);
4936                 return -EINVAL;
4937         }
4938         if (vsi_count > hw->func_caps.num_vsis) {
4939                 PMD_DRV_LOG(ERR,
4940                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4941                         vsi_count, hw->func_caps.num_vsis);
4942                 return -EINVAL;
4943         }
4944
4945         return 0;
4946 }
4947
4948 static int
4949 i40e_pf_get_switch_config(struct i40e_pf *pf)
4950 {
4951         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4952         struct i40e_aqc_get_switch_config_resp *switch_config;
4953         struct i40e_aqc_switch_config_element_resp *element;
4954         uint16_t start_seid = 0, num_reported;
4955         int ret;
4956
4957         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4958                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4959         if (!switch_config) {
4960                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4961                 return -ENOMEM;
4962         }
4963
4964         /* Get the switch configurations */
4965         ret = i40e_aq_get_switch_config(hw, switch_config,
4966                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4967         if (ret != I40E_SUCCESS) {
4968                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4969                 goto fail;
4970         }
4971         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4972         if (num_reported != 1) { /* The number should be 1 */
4973                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4974                 goto fail;
4975         }
4976
4977         /* Parse the switch configuration elements */
4978         element = &(switch_config->element[0]);
4979         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4980                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4981                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4982         } else
4983                 PMD_DRV_LOG(INFO, "Unknown element type");
4984
4985 fail:
4986         rte_free(switch_config);
4987
4988         return ret;
4989 }
4990
4991 static int
4992 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4993                         uint32_t num)
4994 {
4995         struct pool_entry *entry;
4996
4997         if (pool == NULL || num == 0)
4998                 return -EINVAL;
4999
5000         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
5001         if (entry == NULL) {
5002                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
5003                 return -ENOMEM;
5004         }
5005
5006         /* queue heap initialize */
5007         pool->num_free = num;
5008         pool->num_alloc = 0;
5009         pool->base = base;
5010         LIST_INIT(&pool->alloc_list);
5011         LIST_INIT(&pool->free_list);
5012
5013         /* Initialize element  */
5014         entry->base = 0;
5015         entry->len = num;
5016
5017         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5018         return 0;
5019 }
5020
5021 static void
5022 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5023 {
5024         struct pool_entry *entry, *next_entry;
5025
5026         if (pool == NULL)
5027                 return;
5028
5029         for (entry = LIST_FIRST(&pool->alloc_list);
5030                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5031                         entry = next_entry) {
5032                 LIST_REMOVE(entry, next);
5033                 rte_free(entry);
5034         }
5035
5036         for (entry = LIST_FIRST(&pool->free_list);
5037                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5038                         entry = next_entry) {
5039                 LIST_REMOVE(entry, next);
5040                 rte_free(entry);
5041         }
5042
5043         pool->num_free = 0;
5044         pool->num_alloc = 0;
5045         pool->base = 0;
5046         LIST_INIT(&pool->alloc_list);
5047         LIST_INIT(&pool->free_list);
5048 }
5049
5050 static int
5051 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5052                        uint32_t base)
5053 {
5054         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5055         uint32_t pool_offset;
5056         uint16_t len;
5057         int insert;
5058
5059         if (pool == NULL) {
5060                 PMD_DRV_LOG(ERR, "Invalid parameter");
5061                 return -EINVAL;
5062         }
5063
5064         pool_offset = base - pool->base;
5065         /* Lookup in alloc list */
5066         LIST_FOREACH(entry, &pool->alloc_list, next) {
5067                 if (entry->base == pool_offset) {
5068                         valid_entry = entry;
5069                         LIST_REMOVE(entry, next);
5070                         break;
5071                 }
5072         }
5073
5074         /* Not find, return */
5075         if (valid_entry == NULL) {
5076                 PMD_DRV_LOG(ERR, "Failed to find entry");
5077                 return -EINVAL;
5078         }
5079
5080         /**
5081          * Found it, move it to free list  and try to merge.
5082          * In order to make merge easier, always sort it by qbase.
5083          * Find adjacent prev and last entries.
5084          */
5085         prev = next = NULL;
5086         LIST_FOREACH(entry, &pool->free_list, next) {
5087                 if (entry->base > valid_entry->base) {
5088                         next = entry;
5089                         break;
5090                 }
5091                 prev = entry;
5092         }
5093
5094         insert = 0;
5095         len = valid_entry->len;
5096         /* Try to merge with next one*/
5097         if (next != NULL) {
5098                 /* Merge with next one */
5099                 if (valid_entry->base + len == next->base) {
5100                         next->base = valid_entry->base;
5101                         next->len += len;
5102                         rte_free(valid_entry);
5103                         valid_entry = next;
5104                         insert = 1;
5105                 }
5106         }
5107
5108         if (prev != NULL) {
5109                 /* Merge with previous one */
5110                 if (prev->base + prev->len == valid_entry->base) {
5111                         prev->len += len;
5112                         /* If it merge with next one, remove next node */
5113                         if (insert == 1) {
5114                                 LIST_REMOVE(valid_entry, next);
5115                                 rte_free(valid_entry);
5116                                 valid_entry = NULL;
5117                         } else {
5118                                 rte_free(valid_entry);
5119                                 valid_entry = NULL;
5120                                 insert = 1;
5121                         }
5122                 }
5123         }
5124
5125         /* Not find any entry to merge, insert */
5126         if (insert == 0) {
5127                 if (prev != NULL)
5128                         LIST_INSERT_AFTER(prev, valid_entry, next);
5129                 else if (next != NULL)
5130                         LIST_INSERT_BEFORE(next, valid_entry, next);
5131                 else /* It's empty list, insert to head */
5132                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5133         }
5134
5135         pool->num_free += len;
5136         pool->num_alloc -= len;
5137
5138         return 0;
5139 }
5140
5141 static int
5142 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5143                        uint16_t num)
5144 {
5145         struct pool_entry *entry, *valid_entry;
5146
5147         if (pool == NULL || num == 0) {
5148                 PMD_DRV_LOG(ERR, "Invalid parameter");
5149                 return -EINVAL;
5150         }
5151
5152         if (pool->num_free < num) {
5153                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5154                             num, pool->num_free);
5155                 return -ENOMEM;
5156         }
5157
5158         valid_entry = NULL;
5159         /* Lookup  in free list and find most fit one */
5160         LIST_FOREACH(entry, &pool->free_list, next) {
5161                 if (entry->len >= num) {
5162                         /* Find best one */
5163                         if (entry->len == num) {
5164                                 valid_entry = entry;
5165                                 break;
5166                         }
5167                         if (valid_entry == NULL || valid_entry->len > entry->len)
5168                                 valid_entry = entry;
5169                 }
5170         }
5171
5172         /* Not find one to satisfy the request, return */
5173         if (valid_entry == NULL) {
5174                 PMD_DRV_LOG(ERR, "No valid entry found");
5175                 return -ENOMEM;
5176         }
5177         /**
5178          * The entry have equal queue number as requested,
5179          * remove it from alloc_list.
5180          */
5181         if (valid_entry->len == num) {
5182                 LIST_REMOVE(valid_entry, next);
5183         } else {
5184                 /**
5185                  * The entry have more numbers than requested,
5186                  * create a new entry for alloc_list and minus its
5187                  * queue base and number in free_list.
5188                  */
5189                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5190                 if (entry == NULL) {
5191                         PMD_DRV_LOG(ERR,
5192                                 "Failed to allocate memory for resource pool");
5193                         return -ENOMEM;
5194                 }
5195                 entry->base = valid_entry->base;
5196                 entry->len = num;
5197                 valid_entry->base += num;
5198                 valid_entry->len -= num;
5199                 valid_entry = entry;
5200         }
5201
5202         /* Insert it into alloc list, not sorted */
5203         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5204
5205         pool->num_free -= valid_entry->len;
5206         pool->num_alloc += valid_entry->len;
5207
5208         return valid_entry->base + pool->base;
5209 }
5210
5211 /**
5212  * bitmap_is_subset - Check whether src2 is subset of src1
5213  **/
5214 static inline int
5215 bitmap_is_subset(uint8_t src1, uint8_t src2)
5216 {
5217         return !((src1 ^ src2) & src2);
5218 }
5219
5220 static enum i40e_status_code
5221 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5222 {
5223         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5224
5225         /* If DCB is not supported, only default TC is supported */
5226         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5227                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5228                 return I40E_NOT_SUPPORTED;
5229         }
5230
5231         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5232                 PMD_DRV_LOG(ERR,
5233                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5234                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5235                 return I40E_NOT_SUPPORTED;
5236         }
5237         return I40E_SUCCESS;
5238 }
5239
5240 int
5241 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5242                                 struct i40e_vsi_vlan_pvid_info *info)
5243 {
5244         struct i40e_hw *hw;
5245         struct i40e_vsi_context ctxt;
5246         uint8_t vlan_flags = 0;
5247         int ret;
5248
5249         if (vsi == NULL || info == NULL) {
5250                 PMD_DRV_LOG(ERR, "invalid parameters");
5251                 return I40E_ERR_PARAM;
5252         }
5253
5254         if (info->on) {
5255                 vsi->info.pvid = info->config.pvid;
5256                 /**
5257                  * If insert pvid is enabled, only tagged pkts are
5258                  * allowed to be sent out.
5259                  */
5260                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5261                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5262         } else {
5263                 vsi->info.pvid = 0;
5264                 if (info->config.reject.tagged == 0)
5265                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5266
5267                 if (info->config.reject.untagged == 0)
5268                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5269         }
5270         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5271                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5272         vsi->info.port_vlan_flags |= vlan_flags;
5273         vsi->info.valid_sections =
5274                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5275         memset(&ctxt, 0, sizeof(ctxt));
5276         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5277         ctxt.seid = vsi->seid;
5278
5279         hw = I40E_VSI_TO_HW(vsi);
5280         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5281         if (ret != I40E_SUCCESS)
5282                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5283
5284         return ret;
5285 }
5286
5287 static int
5288 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5289 {
5290         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5291         int i, ret;
5292         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5293
5294         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5295         if (ret != I40E_SUCCESS)
5296                 return ret;
5297
5298         if (!vsi->seid) {
5299                 PMD_DRV_LOG(ERR, "seid not valid");
5300                 return -EINVAL;
5301         }
5302
5303         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5304         tc_bw_data.tc_valid_bits = enabled_tcmap;
5305         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5306                 tc_bw_data.tc_bw_credits[i] =
5307                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5308
5309         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5310         if (ret != I40E_SUCCESS) {
5311                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5312                 return ret;
5313         }
5314
5315         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5316                                         sizeof(vsi->info.qs_handle));
5317         return I40E_SUCCESS;
5318 }
5319
5320 static enum i40e_status_code
5321 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5322                                  struct i40e_aqc_vsi_properties_data *info,
5323                                  uint8_t enabled_tcmap)
5324 {
5325         enum i40e_status_code ret;
5326         int i, total_tc = 0;
5327         uint16_t qpnum_per_tc, bsf, qp_idx;
5328
5329         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5330         if (ret != I40E_SUCCESS)
5331                 return ret;
5332
5333         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5334                 if (enabled_tcmap & (1 << i))
5335                         total_tc++;
5336         if (total_tc == 0)
5337                 total_tc = 1;
5338         vsi->enabled_tc = enabled_tcmap;
5339
5340         /* Number of queues per enabled TC */
5341         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5342         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5343         bsf = rte_bsf32(qpnum_per_tc);
5344
5345         /* Adjust the queue number to actual queues that can be applied */
5346         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5347                 vsi->nb_qps = qpnum_per_tc * total_tc;
5348
5349         /**
5350          * Configure TC and queue mapping parameters, for enabled TC,
5351          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5352          * default queue will serve it.
5353          */
5354         qp_idx = 0;
5355         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5356                 if (vsi->enabled_tc & (1 << i)) {
5357                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5358                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5359                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5360                         qp_idx += qpnum_per_tc;
5361                 } else
5362                         info->tc_mapping[i] = 0;
5363         }
5364
5365         /* Associate queue number with VSI */
5366         if (vsi->type == I40E_VSI_SRIOV) {
5367                 info->mapping_flags |=
5368                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5369                 for (i = 0; i < vsi->nb_qps; i++)
5370                         info->queue_mapping[i] =
5371                                 rte_cpu_to_le_16(vsi->base_queue + i);
5372         } else {
5373                 info->mapping_flags |=
5374                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5375                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5376         }
5377         info->valid_sections |=
5378                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5379
5380         return I40E_SUCCESS;
5381 }
5382
5383 static int
5384 i40e_veb_release(struct i40e_veb *veb)
5385 {
5386         struct i40e_vsi *vsi;
5387         struct i40e_hw *hw;
5388
5389         if (veb == NULL)
5390                 return -EINVAL;
5391
5392         if (!TAILQ_EMPTY(&veb->head)) {
5393                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5394                 return -EACCES;
5395         }
5396         /* associate_vsi field is NULL for floating VEB */
5397         if (veb->associate_vsi != NULL) {
5398                 vsi = veb->associate_vsi;
5399                 hw = I40E_VSI_TO_HW(vsi);
5400
5401                 vsi->uplink_seid = veb->uplink_seid;
5402                 vsi->veb = NULL;
5403         } else {
5404                 veb->associate_pf->main_vsi->floating_veb = NULL;
5405                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5406         }
5407
5408         i40e_aq_delete_element(hw, veb->seid, NULL);
5409         rte_free(veb);
5410         return I40E_SUCCESS;
5411 }
5412
5413 /* Setup a veb */
5414 static struct i40e_veb *
5415 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5416 {
5417         struct i40e_veb *veb;
5418         int ret;
5419         struct i40e_hw *hw;
5420
5421         if (pf == NULL) {
5422                 PMD_DRV_LOG(ERR,
5423                             "veb setup failed, associated PF shouldn't null");
5424                 return NULL;
5425         }
5426         hw = I40E_PF_TO_HW(pf);
5427
5428         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5429         if (!veb) {
5430                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5431                 goto fail;
5432         }
5433
5434         veb->associate_vsi = vsi;
5435         veb->associate_pf = pf;
5436         TAILQ_INIT(&veb->head);
5437         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5438
5439         /* create floating veb if vsi is NULL */
5440         if (vsi != NULL) {
5441                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5442                                       I40E_DEFAULT_TCMAP, false,
5443                                       &veb->seid, false, NULL);
5444         } else {
5445                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5446                                       true, &veb->seid, false, NULL);
5447         }
5448
5449         if (ret != I40E_SUCCESS) {
5450                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5451                             hw->aq.asq_last_status);
5452                 goto fail;
5453         }
5454         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5455
5456         /* get statistics index */
5457         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5458                                 &veb->stats_idx, NULL, NULL, NULL);
5459         if (ret != I40E_SUCCESS) {
5460                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5461                             hw->aq.asq_last_status);
5462                 goto fail;
5463         }
5464         /* Get VEB bandwidth, to be implemented */
5465         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5466         if (vsi)
5467                 vsi->uplink_seid = veb->seid;
5468
5469         return veb;
5470 fail:
5471         rte_free(veb);
5472         return NULL;
5473 }
5474
5475 int
5476 i40e_vsi_release(struct i40e_vsi *vsi)
5477 {
5478         struct i40e_pf *pf;
5479         struct i40e_hw *hw;
5480         struct i40e_vsi_list *vsi_list;
5481         void *temp;
5482         int ret;
5483         struct i40e_mac_filter *f;
5484         uint16_t user_param;
5485
5486         if (!vsi)
5487                 return I40E_SUCCESS;
5488
5489         if (!vsi->adapter)
5490                 return -EFAULT;
5491
5492         user_param = vsi->user_param;
5493
5494         pf = I40E_VSI_TO_PF(vsi);
5495         hw = I40E_VSI_TO_HW(vsi);
5496
5497         /* VSI has child to attach, release child first */
5498         if (vsi->veb) {
5499                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5500                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5501                                 return -1;
5502                 }
5503                 i40e_veb_release(vsi->veb);
5504         }
5505
5506         if (vsi->floating_veb) {
5507                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5508                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5509                                 return -1;
5510                 }
5511         }
5512
5513         /* Remove all macvlan filters of the VSI */
5514         i40e_vsi_remove_all_macvlan_filter(vsi);
5515         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5516                 rte_free(f);
5517
5518         if (vsi->type != I40E_VSI_MAIN &&
5519             ((vsi->type != I40E_VSI_SRIOV) ||
5520             !pf->floating_veb_list[user_param])) {
5521                 /* Remove vsi from parent's sibling list */
5522                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5523                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5524                         return I40E_ERR_PARAM;
5525                 }
5526                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5527                                 &vsi->sib_vsi_list, list);
5528
5529                 /* Remove all switch element of the VSI */
5530                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5531                 if (ret != I40E_SUCCESS)
5532                         PMD_DRV_LOG(ERR, "Failed to delete element");
5533         }
5534
5535         if ((vsi->type == I40E_VSI_SRIOV) &&
5536             pf->floating_veb_list[user_param]) {
5537                 /* Remove vsi from parent's sibling list */
5538                 if (vsi->parent_vsi == NULL ||
5539                     vsi->parent_vsi->floating_veb == NULL) {
5540                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5541                         return I40E_ERR_PARAM;
5542                 }
5543                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5544                              &vsi->sib_vsi_list, list);
5545
5546                 /* Remove all switch element of the VSI */
5547                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5548                 if (ret != I40E_SUCCESS)
5549                         PMD_DRV_LOG(ERR, "Failed to delete element");
5550         }
5551
5552         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5553
5554         if (vsi->type != I40E_VSI_SRIOV)
5555                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5556         rte_free(vsi);
5557
5558         return I40E_SUCCESS;
5559 }
5560
5561 static int
5562 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5563 {
5564         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5565         struct i40e_aqc_remove_macvlan_element_data def_filter;
5566         struct i40e_mac_filter_info filter;
5567         int ret;
5568
5569         if (vsi->type != I40E_VSI_MAIN)
5570                 return I40E_ERR_CONFIG;
5571         memset(&def_filter, 0, sizeof(def_filter));
5572         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5573                                         ETH_ADDR_LEN);
5574         def_filter.vlan_tag = 0;
5575         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5576                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5577         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5578         if (ret != I40E_SUCCESS) {
5579                 struct i40e_mac_filter *f;
5580                 struct rte_ether_addr *mac;
5581
5582                 PMD_DRV_LOG(DEBUG,
5583                             "Cannot remove the default macvlan filter");
5584                 /* It needs to add the permanent mac into mac list */
5585                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5586                 if (f == NULL) {
5587                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5588                         return I40E_ERR_NO_MEMORY;
5589                 }
5590                 mac = &f->mac_info.mac_addr;
5591                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5592                                 ETH_ADDR_LEN);
5593                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5594                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5595                 vsi->mac_num++;
5596
5597                 return ret;
5598         }
5599         rte_memcpy(&filter.mac_addr,
5600                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5601         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5602         return i40e_vsi_add_mac(vsi, &filter);
5603 }
5604
5605 /*
5606  * i40e_vsi_get_bw_config - Query VSI BW Information
5607  * @vsi: the VSI to be queried
5608  *
5609  * Returns 0 on success, negative value on failure
5610  */
5611 static enum i40e_status_code
5612 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5613 {
5614         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5615         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5616         struct i40e_hw *hw = &vsi->adapter->hw;
5617         i40e_status ret;
5618         int i;
5619         uint32_t bw_max;
5620
5621         memset(&bw_config, 0, sizeof(bw_config));
5622         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5623         if (ret != I40E_SUCCESS) {
5624                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5625                             hw->aq.asq_last_status);
5626                 return ret;
5627         }
5628
5629         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5630         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5631                                         &ets_sla_config, NULL);
5632         if (ret != I40E_SUCCESS) {
5633                 PMD_DRV_LOG(ERR,
5634                         "VSI failed to get TC bandwdith configuration %u",
5635                         hw->aq.asq_last_status);
5636                 return ret;
5637         }
5638
5639         /* store and print out BW info */
5640         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5641         vsi->bw_info.bw_max = bw_config.max_bw;
5642         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5643         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5644         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5645                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5646                      I40E_16_BIT_WIDTH);
5647         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5648                 vsi->bw_info.bw_ets_share_credits[i] =
5649                                 ets_sla_config.share_credits[i];
5650                 vsi->bw_info.bw_ets_credits[i] =
5651                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5652                 /* 4 bits per TC, 4th bit is reserved */
5653                 vsi->bw_info.bw_ets_max[i] =
5654                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5655                                   RTE_LEN2MASK(3, uint8_t));
5656                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5657                             vsi->bw_info.bw_ets_share_credits[i]);
5658                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5659                             vsi->bw_info.bw_ets_credits[i]);
5660                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5661                             vsi->bw_info.bw_ets_max[i]);
5662         }
5663
5664         return I40E_SUCCESS;
5665 }
5666
5667 /* i40e_enable_pf_lb
5668  * @pf: pointer to the pf structure
5669  *
5670  * allow loopback on pf
5671  */
5672 static inline void
5673 i40e_enable_pf_lb(struct i40e_pf *pf)
5674 {
5675         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5676         struct i40e_vsi_context ctxt;
5677         int ret;
5678
5679         /* Use the FW API if FW >= v5.0 */
5680         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5681                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5682                 return;
5683         }
5684
5685         memset(&ctxt, 0, sizeof(ctxt));
5686         ctxt.seid = pf->main_vsi_seid;
5687         ctxt.pf_num = hw->pf_id;
5688         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5689         if (ret) {
5690                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5691                             ret, hw->aq.asq_last_status);
5692                 return;
5693         }
5694         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5695         ctxt.info.valid_sections =
5696                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5697         ctxt.info.switch_id |=
5698                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5699
5700         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5701         if (ret)
5702                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5703                             hw->aq.asq_last_status);
5704 }
5705
5706 /* Setup a VSI */
5707 struct i40e_vsi *
5708 i40e_vsi_setup(struct i40e_pf *pf,
5709                enum i40e_vsi_type type,
5710                struct i40e_vsi *uplink_vsi,
5711                uint16_t user_param)
5712 {
5713         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5714         struct i40e_vsi *vsi;
5715         struct i40e_mac_filter_info filter;
5716         int ret;
5717         struct i40e_vsi_context ctxt;
5718         struct rte_ether_addr broadcast =
5719                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5720
5721         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5722             uplink_vsi == NULL) {
5723                 PMD_DRV_LOG(ERR,
5724                         "VSI setup failed, VSI link shouldn't be NULL");
5725                 return NULL;
5726         }
5727
5728         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5729                 PMD_DRV_LOG(ERR,
5730                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5731                 return NULL;
5732         }
5733
5734         /* two situations
5735          * 1.type is not MAIN and uplink vsi is not NULL
5736          * If uplink vsi didn't setup VEB, create one first under veb field
5737          * 2.type is SRIOV and the uplink is NULL
5738          * If floating VEB is NULL, create one veb under floating veb field
5739          */
5740
5741         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5742             uplink_vsi->veb == NULL) {
5743                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5744
5745                 if (uplink_vsi->veb == NULL) {
5746                         PMD_DRV_LOG(ERR, "VEB setup failed");
5747                         return NULL;
5748                 }
5749                 /* set ALLOWLOOPBACk on pf, when veb is created */
5750                 i40e_enable_pf_lb(pf);
5751         }
5752
5753         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5754             pf->main_vsi->floating_veb == NULL) {
5755                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5756
5757                 if (pf->main_vsi->floating_veb == NULL) {
5758                         PMD_DRV_LOG(ERR, "VEB setup failed");
5759                         return NULL;
5760                 }
5761         }
5762
5763         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5764         if (!vsi) {
5765                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5766                 return NULL;
5767         }
5768         TAILQ_INIT(&vsi->mac_list);
5769         vsi->type = type;
5770         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5771         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5772         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5773         vsi->user_param = user_param;
5774         vsi->vlan_anti_spoof_on = 0;
5775         vsi->vlan_filter_on = 0;
5776         /* Allocate queues */
5777         switch (vsi->type) {
5778         case I40E_VSI_MAIN  :
5779                 vsi->nb_qps = pf->lan_nb_qps;
5780                 break;
5781         case I40E_VSI_SRIOV :
5782                 vsi->nb_qps = pf->vf_nb_qps;
5783                 break;
5784         case I40E_VSI_VMDQ2:
5785                 vsi->nb_qps = pf->vmdq_nb_qps;
5786                 break;
5787         case I40E_VSI_FDIR:
5788                 vsi->nb_qps = pf->fdir_nb_qps;
5789                 break;
5790         default:
5791                 goto fail_mem;
5792         }
5793         /*
5794          * The filter status descriptor is reported in rx queue 0,
5795          * while the tx queue for fdir filter programming has no
5796          * such constraints, can be non-zero queues.
5797          * To simplify it, choose FDIR vsi use queue 0 pair.
5798          * To make sure it will use queue 0 pair, queue allocation
5799          * need be done before this function is called
5800          */
5801         if (type != I40E_VSI_FDIR) {
5802                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5803                         if (ret < 0) {
5804                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5805                                                 vsi->seid, ret);
5806                                 goto fail_mem;
5807                         }
5808                         vsi->base_queue = ret;
5809         } else
5810                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5811
5812         /* VF has MSIX interrupt in VF range, don't allocate here */
5813         if (type == I40E_VSI_MAIN) {
5814                 if (pf->support_multi_driver) {
5815                         /* If support multi-driver, need to use INT0 instead of
5816                          * allocating from msix pool. The Msix pool is init from
5817                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5818                          * to 1 without calling i40e_res_pool_alloc.
5819                          */
5820                         vsi->msix_intr = 0;
5821                         vsi->nb_msix = 1;
5822                 } else {
5823                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5824                                                   RTE_MIN(vsi->nb_qps,
5825                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5826                         if (ret < 0) {
5827                                 PMD_DRV_LOG(ERR,
5828                                             "VSI MAIN %d get heap failed %d",
5829                                             vsi->seid, ret);
5830                                 goto fail_queue_alloc;
5831                         }
5832                         vsi->msix_intr = ret;
5833                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5834                                                RTE_MAX_RXTX_INTR_VEC_ID);
5835                 }
5836         } else if (type != I40E_VSI_SRIOV) {
5837                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5838                 if (ret < 0) {
5839                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5840                         if (type != I40E_VSI_FDIR)
5841                                 goto fail_queue_alloc;
5842                         vsi->msix_intr = 0;
5843                         vsi->nb_msix = 0;
5844                 } else {
5845                         vsi->msix_intr = ret;
5846                         vsi->nb_msix = 1;
5847                 }
5848         } else {
5849                 vsi->msix_intr = 0;
5850                 vsi->nb_msix = 0;
5851         }
5852
5853         /* Add VSI */
5854         if (type == I40E_VSI_MAIN) {
5855                 /* For main VSI, no need to add since it's default one */
5856                 vsi->uplink_seid = pf->mac_seid;
5857                 vsi->seid = pf->main_vsi_seid;
5858                 /* Bind queues with specific MSIX interrupt */
5859                 /**
5860                  * Needs 2 interrupt at least, one for misc cause which will
5861                  * enabled from OS side, Another for queues binding the
5862                  * interrupt from device side only.
5863                  */
5864
5865                 /* Get default VSI parameters from hardware */
5866                 memset(&ctxt, 0, sizeof(ctxt));
5867                 ctxt.seid = vsi->seid;
5868                 ctxt.pf_num = hw->pf_id;
5869                 ctxt.uplink_seid = vsi->uplink_seid;
5870                 ctxt.vf_num = 0;
5871                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5872                 if (ret != I40E_SUCCESS) {
5873                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5874                         goto fail_msix_alloc;
5875                 }
5876                 rte_memcpy(&vsi->info, &ctxt.info,
5877                         sizeof(struct i40e_aqc_vsi_properties_data));
5878                 vsi->vsi_id = ctxt.vsi_number;
5879                 vsi->info.valid_sections = 0;
5880
5881                 /* Configure tc, enabled TC0 only */
5882                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5883                         I40E_SUCCESS) {
5884                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5885                         goto fail_msix_alloc;
5886                 }
5887
5888                 /* TC, queue mapping */
5889                 memset(&ctxt, 0, sizeof(ctxt));
5890                 vsi->info.valid_sections |=
5891                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5892                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5893                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5894                 rte_memcpy(&ctxt.info, &vsi->info,
5895                         sizeof(struct i40e_aqc_vsi_properties_data));
5896                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5897                                                 I40E_DEFAULT_TCMAP);
5898                 if (ret != I40E_SUCCESS) {
5899                         PMD_DRV_LOG(ERR,
5900                                 "Failed to configure TC queue mapping");
5901                         goto fail_msix_alloc;
5902                 }
5903                 ctxt.seid = vsi->seid;
5904                 ctxt.pf_num = hw->pf_id;
5905                 ctxt.uplink_seid = vsi->uplink_seid;
5906                 ctxt.vf_num = 0;
5907
5908                 /* Update VSI parameters */
5909                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5910                 if (ret != I40E_SUCCESS) {
5911                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5912                         goto fail_msix_alloc;
5913                 }
5914
5915                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5916                                                 sizeof(vsi->info.tc_mapping));
5917                 rte_memcpy(&vsi->info.queue_mapping,
5918                                 &ctxt.info.queue_mapping,
5919                         sizeof(vsi->info.queue_mapping));
5920                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5921                 vsi->info.valid_sections = 0;
5922
5923                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5924                                 ETH_ADDR_LEN);
5925
5926                 /**
5927                  * Updating default filter settings are necessary to prevent
5928                  * reception of tagged packets.
5929                  * Some old firmware configurations load a default macvlan
5930                  * filter which accepts both tagged and untagged packets.
5931                  * The updating is to use a normal filter instead if needed.
5932                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5933                  * The firmware with correct configurations load the default
5934                  * macvlan filter which is expected and cannot be removed.
5935                  */
5936                 i40e_update_default_filter_setting(vsi);
5937                 i40e_config_qinq(hw, vsi);
5938         } else if (type == I40E_VSI_SRIOV) {
5939                 memset(&ctxt, 0, sizeof(ctxt));
5940                 /**
5941                  * For other VSI, the uplink_seid equals to uplink VSI's
5942                  * uplink_seid since they share same VEB
5943                  */
5944                 if (uplink_vsi == NULL)
5945                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5946                 else
5947                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5948                 ctxt.pf_num = hw->pf_id;
5949                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5950                 ctxt.uplink_seid = vsi->uplink_seid;
5951                 ctxt.connection_type = 0x1;
5952                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5953
5954                 /* Use the VEB configuration if FW >= v5.0 */
5955                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5956                         /* Configure switch ID */
5957                         ctxt.info.valid_sections |=
5958                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5959                         ctxt.info.switch_id =
5960                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5961                 }
5962
5963                 /* Configure port/vlan */
5964                 ctxt.info.valid_sections |=
5965                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5966                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5967                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5968                                                 hw->func_caps.enabled_tcmap);
5969                 if (ret != I40E_SUCCESS) {
5970                         PMD_DRV_LOG(ERR,
5971                                 "Failed to configure TC queue mapping");
5972                         goto fail_msix_alloc;
5973                 }
5974
5975                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5976                 ctxt.info.valid_sections |=
5977                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5978                 /**
5979                  * Since VSI is not created yet, only configure parameter,
5980                  * will add vsi below.
5981                  */
5982
5983                 i40e_config_qinq(hw, vsi);
5984         } else if (type == I40E_VSI_VMDQ2) {
5985                 memset(&ctxt, 0, sizeof(ctxt));
5986                 /*
5987                  * For other VSI, the uplink_seid equals to uplink VSI's
5988                  * uplink_seid since they share same VEB
5989                  */
5990                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5991                 ctxt.pf_num = hw->pf_id;
5992                 ctxt.vf_num = 0;
5993                 ctxt.uplink_seid = vsi->uplink_seid;
5994                 ctxt.connection_type = 0x1;
5995                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5996
5997                 ctxt.info.valid_sections |=
5998                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5999                 /* user_param carries flag to enable loop back */
6000                 if (user_param) {
6001                         ctxt.info.switch_id =
6002                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
6003                         ctxt.info.switch_id |=
6004                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6005                 }
6006
6007                 /* Configure port/vlan */
6008                 ctxt.info.valid_sections |=
6009                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6010                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6011                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6012                                                 I40E_DEFAULT_TCMAP);
6013                 if (ret != I40E_SUCCESS) {
6014                         PMD_DRV_LOG(ERR,
6015                                 "Failed to configure TC queue mapping");
6016                         goto fail_msix_alloc;
6017                 }
6018                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6019                 ctxt.info.valid_sections |=
6020                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6021         } else if (type == I40E_VSI_FDIR) {
6022                 memset(&ctxt, 0, sizeof(ctxt));
6023                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6024                 ctxt.pf_num = hw->pf_id;
6025                 ctxt.vf_num = 0;
6026                 ctxt.uplink_seid = vsi->uplink_seid;
6027                 ctxt.connection_type = 0x1;     /* regular data port */
6028                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6029                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6030                                                 I40E_DEFAULT_TCMAP);
6031                 if (ret != I40E_SUCCESS) {
6032                         PMD_DRV_LOG(ERR,
6033                                 "Failed to configure TC queue mapping.");
6034                         goto fail_msix_alloc;
6035                 }
6036                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6037                 ctxt.info.valid_sections |=
6038                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6039         } else {
6040                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6041                 goto fail_msix_alloc;
6042         }
6043
6044         if (vsi->type != I40E_VSI_MAIN) {
6045                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6046                 if (ret != I40E_SUCCESS) {
6047                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6048                                     hw->aq.asq_last_status);
6049                         goto fail_msix_alloc;
6050                 }
6051                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6052                 vsi->info.valid_sections = 0;
6053                 vsi->seid = ctxt.seid;
6054                 vsi->vsi_id = ctxt.vsi_number;
6055                 vsi->sib_vsi_list.vsi = vsi;
6056                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6057                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6058                                           &vsi->sib_vsi_list, list);
6059                 } else {
6060                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6061                                           &vsi->sib_vsi_list, list);
6062                 }
6063         }
6064
6065         /* MAC/VLAN configuration */
6066         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6067         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
6068
6069         ret = i40e_vsi_add_mac(vsi, &filter);
6070         if (ret != I40E_SUCCESS) {
6071                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6072                 goto fail_msix_alloc;
6073         }
6074
6075         /* Get VSI BW information */
6076         i40e_vsi_get_bw_config(vsi);
6077         return vsi;
6078 fail_msix_alloc:
6079         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6080 fail_queue_alloc:
6081         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6082 fail_mem:
6083         rte_free(vsi);
6084         return NULL;
6085 }
6086
6087 /* Configure vlan filter on or off */
6088 int
6089 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6090 {
6091         int i, num;
6092         struct i40e_mac_filter *f;
6093         void *temp;
6094         struct i40e_mac_filter_info *mac_filter;
6095         enum rte_mac_filter_type desired_filter;
6096         int ret = I40E_SUCCESS;
6097
6098         if (on) {
6099                 /* Filter to match MAC and VLAN */
6100                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6101         } else {
6102                 /* Filter to match only MAC */
6103                 desired_filter = RTE_MAC_PERFECT_MATCH;
6104         }
6105
6106         num = vsi->mac_num;
6107
6108         mac_filter = rte_zmalloc("mac_filter_info_data",
6109                                  num * sizeof(*mac_filter), 0);
6110         if (mac_filter == NULL) {
6111                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6112                 return I40E_ERR_NO_MEMORY;
6113         }
6114
6115         i = 0;
6116
6117         /* Remove all existing mac */
6118         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6119                 mac_filter[i] = f->mac_info;
6120                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6121                 if (ret) {
6122                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6123                                     on ? "enable" : "disable");
6124                         goto DONE;
6125                 }
6126                 i++;
6127         }
6128
6129         /* Override with new filter */
6130         for (i = 0; i < num; i++) {
6131                 mac_filter[i].filter_type = desired_filter;
6132                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6133                 if (ret) {
6134                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6135                                     on ? "enable" : "disable");
6136                         goto DONE;
6137                 }
6138         }
6139
6140 DONE:
6141         rte_free(mac_filter);
6142         return ret;
6143 }
6144
6145 /* Configure vlan stripping on or off */
6146 int
6147 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6148 {
6149         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6150         struct i40e_vsi_context ctxt;
6151         uint8_t vlan_flags;
6152         int ret = I40E_SUCCESS;
6153
6154         /* Check if it has been already on or off */
6155         if (vsi->info.valid_sections &
6156                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6157                 if (on) {
6158                         if ((vsi->info.port_vlan_flags &
6159                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6160                                 return 0; /* already on */
6161                 } else {
6162                         if ((vsi->info.port_vlan_flags &
6163                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6164                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6165                                 return 0; /* already off */
6166                 }
6167         }
6168
6169         if (on)
6170                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6171         else
6172                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6173         vsi->info.valid_sections =
6174                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6175         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6176         vsi->info.port_vlan_flags |= vlan_flags;
6177         ctxt.seid = vsi->seid;
6178         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6179         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6180         if (ret)
6181                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6182                             on ? "enable" : "disable");
6183
6184         return ret;
6185 }
6186
6187 static int
6188 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6189 {
6190         struct rte_eth_dev_data *data = dev->data;
6191         int ret;
6192         int mask = 0;
6193
6194         /* Apply vlan offload setting */
6195         mask = ETH_VLAN_STRIP_MASK |
6196                ETH_VLAN_FILTER_MASK |
6197                ETH_VLAN_EXTEND_MASK;
6198         ret = i40e_vlan_offload_set(dev, mask);
6199         if (ret) {
6200                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6201                 return ret;
6202         }
6203
6204         /* Apply pvid setting */
6205         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6206                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6207         if (ret)
6208                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6209
6210         return ret;
6211 }
6212
6213 static int
6214 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6215 {
6216         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6217
6218         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6219 }
6220
6221 static int
6222 i40e_update_flow_control(struct i40e_hw *hw)
6223 {
6224 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6225         struct i40e_link_status link_status;
6226         uint32_t rxfc = 0, txfc = 0, reg;
6227         uint8_t an_info;
6228         int ret;
6229
6230         memset(&link_status, 0, sizeof(link_status));
6231         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6232         if (ret != I40E_SUCCESS) {
6233                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6234                 goto write_reg; /* Disable flow control */
6235         }
6236
6237         an_info = hw->phy.link_info.an_info;
6238         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6239                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6240                 ret = I40E_ERR_NOT_READY;
6241                 goto write_reg; /* Disable flow control */
6242         }
6243         /**
6244          * If link auto negotiation is enabled, flow control needs to
6245          * be configured according to it
6246          */
6247         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6248         case I40E_LINK_PAUSE_RXTX:
6249                 rxfc = 1;
6250                 txfc = 1;
6251                 hw->fc.current_mode = I40E_FC_FULL;
6252                 break;
6253         case I40E_AQ_LINK_PAUSE_RX:
6254                 rxfc = 1;
6255                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6256                 break;
6257         case I40E_AQ_LINK_PAUSE_TX:
6258                 txfc = 1;
6259                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6260                 break;
6261         default:
6262                 hw->fc.current_mode = I40E_FC_NONE;
6263                 break;
6264         }
6265
6266 write_reg:
6267         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6268                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6269         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6270         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6271         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6272         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6273
6274         return ret;
6275 }
6276
6277 /* PF setup */
6278 static int
6279 i40e_pf_setup(struct i40e_pf *pf)
6280 {
6281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6282         struct i40e_filter_control_settings settings;
6283         struct i40e_vsi *vsi;
6284         int ret;
6285
6286         /* Clear all stats counters */
6287         pf->offset_loaded = FALSE;
6288         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6289         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6290         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6291         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6292
6293         ret = i40e_pf_get_switch_config(pf);
6294         if (ret != I40E_SUCCESS) {
6295                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6296                 return ret;
6297         }
6298
6299         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6300         if (ret)
6301                 PMD_INIT_LOG(WARNING,
6302                         "failed to allocate switch domain for device %d", ret);
6303
6304         if (pf->flags & I40E_FLAG_FDIR) {
6305                 /* make queue allocated first, let FDIR use queue pair 0*/
6306                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6307                 if (ret != I40E_FDIR_QUEUE_ID) {
6308                         PMD_DRV_LOG(ERR,
6309                                 "queue allocation fails for FDIR: ret =%d",
6310                                 ret);
6311                         pf->flags &= ~I40E_FLAG_FDIR;
6312                 }
6313         }
6314         /*  main VSI setup */
6315         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6316         if (!vsi) {
6317                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6318                 return I40E_ERR_NOT_READY;
6319         }
6320         pf->main_vsi = vsi;
6321
6322         /* Configure filter control */
6323         memset(&settings, 0, sizeof(settings));
6324         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6325                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6326         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6327                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6328         else {
6329                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6330                         hw->func_caps.rss_table_size);
6331                 return I40E_ERR_PARAM;
6332         }
6333         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6334                 hw->func_caps.rss_table_size);
6335         pf->hash_lut_size = hw->func_caps.rss_table_size;
6336
6337         /* Enable ethtype and macvlan filters */
6338         settings.enable_ethtype = TRUE;
6339         settings.enable_macvlan = TRUE;
6340         ret = i40e_set_filter_control(hw, &settings);
6341         if (ret)
6342                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6343                                                                 ret);
6344
6345         /* Update flow control according to the auto negotiation */
6346         i40e_update_flow_control(hw);
6347
6348         return I40E_SUCCESS;
6349 }
6350
6351 int
6352 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6353 {
6354         uint32_t reg;
6355         uint16_t j;
6356
6357         /**
6358          * Set or clear TX Queue Disable flags,
6359          * which is required by hardware.
6360          */
6361         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6362         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6363
6364         /* Wait until the request is finished */
6365         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6366                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6367                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6368                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6369                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6370                                                         & 0x1))) {
6371                         break;
6372                 }
6373         }
6374         if (on) {
6375                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6376                         return I40E_SUCCESS; /* already on, skip next steps */
6377
6378                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6379                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6380         } else {
6381                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6382                         return I40E_SUCCESS; /* already off, skip next steps */
6383                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6384         }
6385         /* Write the register */
6386         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6387         /* Check the result */
6388         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6389                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6390                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6391                 if (on) {
6392                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6393                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6394                                 break;
6395                 } else {
6396                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6397                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6398                                 break;
6399                 }
6400         }
6401         /* Check if it is timeout */
6402         if (j >= I40E_CHK_Q_ENA_COUNT) {
6403                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6404                             (on ? "enable" : "disable"), q_idx);
6405                 return I40E_ERR_TIMEOUT;
6406         }
6407
6408         return I40E_SUCCESS;
6409 }
6410
6411 int
6412 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6413 {
6414         uint32_t reg;
6415         uint16_t j;
6416
6417         /* Wait until the request is finished */
6418         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6419                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6420                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6421                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6422                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6423                         break;
6424         }
6425
6426         if (on) {
6427                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6428                         return I40E_SUCCESS; /* Already on, skip next steps */
6429                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6430         } else {
6431                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6432                         return I40E_SUCCESS; /* Already off, skip next steps */
6433                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6434         }
6435
6436         /* Write the register */
6437         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6438         /* Check the result */
6439         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6440                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6441                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6442                 if (on) {
6443                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6444                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6445                                 break;
6446                 } else {
6447                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6448                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6449                                 break;
6450                 }
6451         }
6452
6453         /* Check if it is timeout */
6454         if (j >= I40E_CHK_Q_ENA_COUNT) {
6455                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6456                             (on ? "enable" : "disable"), q_idx);
6457                 return I40E_ERR_TIMEOUT;
6458         }
6459
6460         return I40E_SUCCESS;
6461 }
6462
6463 /* Initialize VSI for TX */
6464 static int
6465 i40e_dev_tx_init(struct i40e_pf *pf)
6466 {
6467         struct rte_eth_dev_data *data = pf->dev_data;
6468         uint16_t i;
6469         uint32_t ret = I40E_SUCCESS;
6470         struct i40e_tx_queue *txq;
6471
6472         for (i = 0; i < data->nb_tx_queues; i++) {
6473                 txq = data->tx_queues[i];
6474                 if (!txq || !txq->q_set)
6475                         continue;
6476                 ret = i40e_tx_queue_init(txq);
6477                 if (ret != I40E_SUCCESS)
6478                         break;
6479         }
6480         if (ret == I40E_SUCCESS)
6481                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6482                                      ->eth_dev);
6483
6484         return ret;
6485 }
6486
6487 /* Initialize VSI for RX */
6488 static int
6489 i40e_dev_rx_init(struct i40e_pf *pf)
6490 {
6491         struct rte_eth_dev_data *data = pf->dev_data;
6492         int ret = I40E_SUCCESS;
6493         uint16_t i;
6494         struct i40e_rx_queue *rxq;
6495
6496         i40e_pf_config_rss(pf);
6497         for (i = 0; i < data->nb_rx_queues; i++) {
6498                 rxq = data->rx_queues[i];
6499                 if (!rxq || !rxq->q_set)
6500                         continue;
6501
6502                 ret = i40e_rx_queue_init(rxq);
6503                 if (ret != I40E_SUCCESS) {
6504                         PMD_DRV_LOG(ERR,
6505                                 "Failed to do RX queue initialization");
6506                         break;
6507                 }
6508         }
6509         if (ret == I40E_SUCCESS)
6510                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6511                                      ->eth_dev);
6512
6513         return ret;
6514 }
6515
6516 static int
6517 i40e_dev_rxtx_init(struct i40e_pf *pf)
6518 {
6519         int err;
6520
6521         err = i40e_dev_tx_init(pf);
6522         if (err) {
6523                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6524                 return err;
6525         }
6526         err = i40e_dev_rx_init(pf);
6527         if (err) {
6528                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6529                 return err;
6530         }
6531
6532         return err;
6533 }
6534
6535 static int
6536 i40e_vmdq_setup(struct rte_eth_dev *dev)
6537 {
6538         struct rte_eth_conf *conf = &dev->data->dev_conf;
6539         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6540         int i, err, conf_vsis, j, loop;
6541         struct i40e_vsi *vsi;
6542         struct i40e_vmdq_info *vmdq_info;
6543         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6544         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6545
6546         /*
6547          * Disable interrupt to avoid message from VF. Furthermore, it will
6548          * avoid race condition in VSI creation/destroy.
6549          */
6550         i40e_pf_disable_irq0(hw);
6551
6552         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6553                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6554                 return -ENOTSUP;
6555         }
6556
6557         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6558         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6559                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6560                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6561                         pf->max_nb_vmdq_vsi);
6562                 return -ENOTSUP;
6563         }
6564
6565         if (pf->vmdq != NULL) {
6566                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6567                 return 0;
6568         }
6569
6570         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6571                                 sizeof(*vmdq_info) * conf_vsis, 0);
6572
6573         if (pf->vmdq == NULL) {
6574                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6575                 return -ENOMEM;
6576         }
6577
6578         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6579
6580         /* Create VMDQ VSI */
6581         for (i = 0; i < conf_vsis; i++) {
6582                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6583                                 vmdq_conf->enable_loop_back);
6584                 if (vsi == NULL) {
6585                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6586                         err = -1;
6587                         goto err_vsi_setup;
6588                 }
6589                 vmdq_info = &pf->vmdq[i];
6590                 vmdq_info->pf = pf;
6591                 vmdq_info->vsi = vsi;
6592         }
6593         pf->nb_cfg_vmdq_vsi = conf_vsis;
6594
6595         /* Configure Vlan */
6596         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6597         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6598                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6599                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6600                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6601                                         vmdq_conf->pool_map[i].vlan_id, j);
6602
6603                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6604                                                 vmdq_conf->pool_map[i].vlan_id);
6605                                 if (err) {
6606                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6607                                         err = -1;
6608                                         goto err_vsi_setup;
6609                                 }
6610                         }
6611                 }
6612         }
6613
6614         i40e_pf_enable_irq0(hw);
6615
6616         return 0;
6617
6618 err_vsi_setup:
6619         for (i = 0; i < conf_vsis; i++)
6620                 if (pf->vmdq[i].vsi == NULL)
6621                         break;
6622                 else
6623                         i40e_vsi_release(pf->vmdq[i].vsi);
6624
6625         rte_free(pf->vmdq);
6626         pf->vmdq = NULL;
6627         i40e_pf_enable_irq0(hw);
6628         return err;
6629 }
6630
6631 static void
6632 i40e_stat_update_32(struct i40e_hw *hw,
6633                    uint32_t reg,
6634                    bool offset_loaded,
6635                    uint64_t *offset,
6636                    uint64_t *stat)
6637 {
6638         uint64_t new_data;
6639
6640         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6641         if (!offset_loaded)
6642                 *offset = new_data;
6643
6644         if (new_data >= *offset)
6645                 *stat = (uint64_t)(new_data - *offset);
6646         else
6647                 *stat = (uint64_t)((new_data +
6648                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6649 }
6650
6651 static void
6652 i40e_stat_update_48(struct i40e_hw *hw,
6653                    uint32_t hireg,
6654                    uint32_t loreg,
6655                    bool offset_loaded,
6656                    uint64_t *offset,
6657                    uint64_t *stat)
6658 {
6659         uint64_t new_data;
6660
6661         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6662         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6663                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6664
6665         if (!offset_loaded)
6666                 *offset = new_data;
6667
6668         if (new_data >= *offset)
6669                 *stat = new_data - *offset;
6670         else
6671                 *stat = (uint64_t)((new_data +
6672                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6673
6674         *stat &= I40E_48_BIT_MASK;
6675 }
6676
6677 /* Disable IRQ0 */
6678 void
6679 i40e_pf_disable_irq0(struct i40e_hw *hw)
6680 {
6681         /* Disable all interrupt types */
6682         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6683                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6684         I40E_WRITE_FLUSH(hw);
6685 }
6686
6687 /* Enable IRQ0 */
6688 void
6689 i40e_pf_enable_irq0(struct i40e_hw *hw)
6690 {
6691         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6692                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6693                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6694                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6695         I40E_WRITE_FLUSH(hw);
6696 }
6697
6698 static void
6699 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6700 {
6701         /* read pending request and disable first */
6702         i40e_pf_disable_irq0(hw);
6703         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6704         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6705                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6706
6707         if (no_queue)
6708                 /* Link no queues with irq0 */
6709                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6710                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6711 }
6712
6713 static void
6714 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6715 {
6716         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6718         int i;
6719         uint16_t abs_vf_id;
6720         uint32_t index, offset, val;
6721
6722         if (!pf->vfs)
6723                 return;
6724         /**
6725          * Try to find which VF trigger a reset, use absolute VF id to access
6726          * since the reg is global register.
6727          */
6728         for (i = 0; i < pf->vf_num; i++) {
6729                 abs_vf_id = hw->func_caps.vf_base_id + i;
6730                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6731                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6732                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6733                 /* VFR event occurred */
6734                 if (val & (0x1 << offset)) {
6735                         int ret;
6736
6737                         /* Clear the event first */
6738                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6739                                                         (0x1 << offset));
6740                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6741                         /**
6742                          * Only notify a VF reset event occurred,
6743                          * don't trigger another SW reset
6744                          */
6745                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6746                         if (ret != I40E_SUCCESS)
6747                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6748                 }
6749         }
6750 }
6751
6752 static void
6753 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6754 {
6755         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6756         int i;
6757
6758         for (i = 0; i < pf->vf_num; i++)
6759                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6760 }
6761
6762 static void
6763 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6764 {
6765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6766         struct i40e_arq_event_info info;
6767         uint16_t pending, opcode;
6768         int ret;
6769
6770         info.buf_len = I40E_AQ_BUF_SZ;
6771         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6772         if (!info.msg_buf) {
6773                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6774                 return;
6775         }
6776
6777         pending = 1;
6778         while (pending) {
6779                 ret = i40e_clean_arq_element(hw, &info, &pending);
6780
6781                 if (ret != I40E_SUCCESS) {
6782                         PMD_DRV_LOG(INFO,
6783                                 "Failed to read msg from AdminQ, aq_err: %u",
6784                                 hw->aq.asq_last_status);
6785                         break;
6786                 }
6787                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6788
6789                 switch (opcode) {
6790                 case i40e_aqc_opc_send_msg_to_pf:
6791                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6792                         i40e_pf_host_handle_vf_msg(dev,
6793                                         rte_le_to_cpu_16(info.desc.retval),
6794                                         rte_le_to_cpu_32(info.desc.cookie_high),
6795                                         rte_le_to_cpu_32(info.desc.cookie_low),
6796                                         info.msg_buf,
6797                                         info.msg_len);
6798                         break;
6799                 case i40e_aqc_opc_get_link_status:
6800                         ret = i40e_dev_link_update(dev, 0);
6801                         if (!ret)
6802                                 _rte_eth_dev_callback_process(dev,
6803                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6804                         break;
6805                 default:
6806                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6807                                     opcode);
6808                         break;
6809                 }
6810         }
6811         rte_free(info.msg_buf);
6812 }
6813
6814 static void
6815 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6816 {
6817 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6818 #define I40E_MDD_CLEAR16 0xFFFF
6819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6820         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6821         bool mdd_detected = false;
6822         struct i40e_pf_vf *vf;
6823         uint32_t reg;
6824         int i;
6825
6826         /* find what triggered the MDD event */
6827         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6828         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6829                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6830                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6831                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6832                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6833                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6834                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6835                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6836                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6837                                         hw->func_caps.base_queue;
6838                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6839                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6840                                 event, queue, pf_num, vf_num, dev->data->name);
6841                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6842                 mdd_detected = true;
6843         }
6844         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6845         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6846                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6847                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6848                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6849                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6850                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6851                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6852                                         hw->func_caps.base_queue;
6853
6854                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6855                                 "queue %d of function 0x%02x device %s\n",
6856                                         event, queue, func, dev->data->name);
6857                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6858                 mdd_detected = true;
6859         }
6860
6861         if (mdd_detected) {
6862                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6863                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6864                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6865                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6866                 }
6867                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6868                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6869                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6870                                         I40E_MDD_CLEAR16);
6871                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6872                 }
6873         }
6874
6875         /* see if one of the VFs needs its hand slapped */
6876         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6877                 vf = &pf->vfs[i];
6878                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6879                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6880                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6881                                         I40E_MDD_CLEAR16);
6882                         vf->num_mdd_events++;
6883                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6884                                         PRIu64 "times\n",
6885                                         i, vf->num_mdd_events);
6886                 }
6887
6888                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6889                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6890                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6891                                         I40E_MDD_CLEAR16);
6892                         vf->num_mdd_events++;
6893                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6894                                         PRIu64 "times\n",
6895                                         i, vf->num_mdd_events);
6896                 }
6897         }
6898 }
6899
6900 /**
6901  * Interrupt handler triggered by NIC  for handling
6902  * specific interrupt.
6903  *
6904  * @param handle
6905  *  Pointer to interrupt handle.
6906  * @param param
6907  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6908  *
6909  * @return
6910  *  void
6911  */
6912 static void
6913 i40e_dev_interrupt_handler(void *param)
6914 {
6915         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6917         uint32_t icr0;
6918
6919         /* Disable interrupt */
6920         i40e_pf_disable_irq0(hw);
6921
6922         /* read out interrupt causes */
6923         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6924
6925         /* No interrupt event indicated */
6926         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6927                 PMD_DRV_LOG(INFO, "No interrupt event");
6928                 goto done;
6929         }
6930         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6931                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6932         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6933                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6934                 i40e_handle_mdd_event(dev);
6935         }
6936         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6937                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6938         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6939                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6940         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6941                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6942         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6943                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6944         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6945                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6946
6947         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6948                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6949                 i40e_dev_handle_vfr_event(dev);
6950         }
6951         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6952                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6953                 i40e_dev_handle_aq_msg(dev);
6954         }
6955
6956 done:
6957         /* Enable interrupt */
6958         i40e_pf_enable_irq0(hw);
6959 }
6960
6961 static void
6962 i40e_dev_alarm_handler(void *param)
6963 {
6964         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6966         uint32_t icr0;
6967
6968         /* Disable interrupt */
6969         i40e_pf_disable_irq0(hw);
6970
6971         /* read out interrupt causes */
6972         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6973
6974         /* No interrupt event indicated */
6975         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6976                 goto done;
6977         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6978                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6979         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6980                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6981                 i40e_handle_mdd_event(dev);
6982         }
6983         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6984                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6985         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6986                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6987         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6988                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6989         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6990                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6991         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6992                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6993
6994         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6995                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6996                 i40e_dev_handle_vfr_event(dev);
6997         }
6998         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6999                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
7000                 i40e_dev_handle_aq_msg(dev);
7001         }
7002
7003 done:
7004         /* Enable interrupt */
7005         i40e_pf_enable_irq0(hw);
7006         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7007                           i40e_dev_alarm_handler, dev);
7008 }
7009
7010 int
7011 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7012                          struct i40e_macvlan_filter *filter,
7013                          int total)
7014 {
7015         int ele_num, ele_buff_size;
7016         int num, actual_num, i;
7017         uint16_t flags;
7018         int ret = I40E_SUCCESS;
7019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7020         struct i40e_aqc_add_macvlan_element_data *req_list;
7021
7022         if (filter == NULL  || total == 0)
7023                 return I40E_ERR_PARAM;
7024         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7025         ele_buff_size = hw->aq.asq_buf_size;
7026
7027         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7028         if (req_list == NULL) {
7029                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7030                 return I40E_ERR_NO_MEMORY;
7031         }
7032
7033         num = 0;
7034         do {
7035                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7036                 memset(req_list, 0, ele_buff_size);
7037
7038                 for (i = 0; i < actual_num; i++) {
7039                         rte_memcpy(req_list[i].mac_addr,
7040                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7041                         req_list[i].vlan_tag =
7042                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7043
7044                         switch (filter[num + i].filter_type) {
7045                         case RTE_MAC_PERFECT_MATCH:
7046                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7047                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7048                                 break;
7049                         case RTE_MACVLAN_PERFECT_MATCH:
7050                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7051                                 break;
7052                         case RTE_MAC_HASH_MATCH:
7053                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7054                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7055                                 break;
7056                         case RTE_MACVLAN_HASH_MATCH:
7057                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7058                                 break;
7059                         default:
7060                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7061                                 ret = I40E_ERR_PARAM;
7062                                 goto DONE;
7063                         }
7064
7065                         req_list[i].queue_number = 0;
7066
7067                         req_list[i].flags = rte_cpu_to_le_16(flags);
7068                 }
7069
7070                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7071                                                 actual_num, NULL);
7072                 if (ret != I40E_SUCCESS) {
7073                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7074                         goto DONE;
7075                 }
7076                 num += actual_num;
7077         } while (num < total);
7078
7079 DONE:
7080         rte_free(req_list);
7081         return ret;
7082 }
7083
7084 int
7085 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7086                             struct i40e_macvlan_filter *filter,
7087                             int total)
7088 {
7089         int ele_num, ele_buff_size;
7090         int num, actual_num, i;
7091         uint16_t flags;
7092         int ret = I40E_SUCCESS;
7093         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7094         struct i40e_aqc_remove_macvlan_element_data *req_list;
7095
7096         if (filter == NULL  || total == 0)
7097                 return I40E_ERR_PARAM;
7098
7099         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7100         ele_buff_size = hw->aq.asq_buf_size;
7101
7102         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7103         if (req_list == NULL) {
7104                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7105                 return I40E_ERR_NO_MEMORY;
7106         }
7107
7108         num = 0;
7109         do {
7110                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7111                 memset(req_list, 0, ele_buff_size);
7112
7113                 for (i = 0; i < actual_num; i++) {
7114                         rte_memcpy(req_list[i].mac_addr,
7115                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7116                         req_list[i].vlan_tag =
7117                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7118
7119                         switch (filter[num + i].filter_type) {
7120                         case RTE_MAC_PERFECT_MATCH:
7121                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7122                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7123                                 break;
7124                         case RTE_MACVLAN_PERFECT_MATCH:
7125                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7126                                 break;
7127                         case RTE_MAC_HASH_MATCH:
7128                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7129                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7130                                 break;
7131                         case RTE_MACVLAN_HASH_MATCH:
7132                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7133                                 break;
7134                         default:
7135                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7136                                 ret = I40E_ERR_PARAM;
7137                                 goto DONE;
7138                         }
7139                         req_list[i].flags = rte_cpu_to_le_16(flags);
7140                 }
7141
7142                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7143                                                 actual_num, NULL);
7144                 if (ret != I40E_SUCCESS) {
7145                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7146                         goto DONE;
7147                 }
7148                 num += actual_num;
7149         } while (num < total);
7150
7151 DONE:
7152         rte_free(req_list);
7153         return ret;
7154 }
7155
7156 /* Find out specific MAC filter */
7157 static struct i40e_mac_filter *
7158 i40e_find_mac_filter(struct i40e_vsi *vsi,
7159                          struct rte_ether_addr *macaddr)
7160 {
7161         struct i40e_mac_filter *f;
7162
7163         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7164                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7165                         return f;
7166         }
7167
7168         return NULL;
7169 }
7170
7171 static bool
7172 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7173                          uint16_t vlan_id)
7174 {
7175         uint32_t vid_idx, vid_bit;
7176
7177         if (vlan_id > ETH_VLAN_ID_MAX)
7178                 return 0;
7179
7180         vid_idx = I40E_VFTA_IDX(vlan_id);
7181         vid_bit = I40E_VFTA_BIT(vlan_id);
7182
7183         if (vsi->vfta[vid_idx] & vid_bit)
7184                 return 1;
7185         else
7186                 return 0;
7187 }
7188
7189 static void
7190 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7191                        uint16_t vlan_id, bool on)
7192 {
7193         uint32_t vid_idx, vid_bit;
7194
7195         vid_idx = I40E_VFTA_IDX(vlan_id);
7196         vid_bit = I40E_VFTA_BIT(vlan_id);
7197
7198         if (on)
7199                 vsi->vfta[vid_idx] |= vid_bit;
7200         else
7201                 vsi->vfta[vid_idx] &= ~vid_bit;
7202 }
7203
7204 void
7205 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7206                      uint16_t vlan_id, bool on)
7207 {
7208         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7209         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7210         int ret;
7211
7212         if (vlan_id > ETH_VLAN_ID_MAX)
7213                 return;
7214
7215         i40e_store_vlan_filter(vsi, vlan_id, on);
7216
7217         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7218                 return;
7219
7220         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7221
7222         if (on) {
7223                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7224                                        &vlan_data, 1, NULL);
7225                 if (ret != I40E_SUCCESS)
7226                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7227         } else {
7228                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7229                                           &vlan_data, 1, NULL);
7230                 if (ret != I40E_SUCCESS)
7231                         PMD_DRV_LOG(ERR,
7232                                     "Failed to remove vlan filter");
7233         }
7234 }
7235
7236 /**
7237  * Find all vlan options for specific mac addr,
7238  * return with actual vlan found.
7239  */
7240 int
7241 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7242                            struct i40e_macvlan_filter *mv_f,
7243                            int num, struct rte_ether_addr *addr)
7244 {
7245         int i;
7246         uint32_t j, k;
7247
7248         /**
7249          * Not to use i40e_find_vlan_filter to decrease the loop time,
7250          * although the code looks complex.
7251           */
7252         if (num < vsi->vlan_num)
7253                 return I40E_ERR_PARAM;
7254
7255         i = 0;
7256         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7257                 if (vsi->vfta[j]) {
7258                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7259                                 if (vsi->vfta[j] & (1 << k)) {
7260                                         if (i > num - 1) {
7261                                                 PMD_DRV_LOG(ERR,
7262                                                         "vlan number doesn't match");
7263                                                 return I40E_ERR_PARAM;
7264                                         }
7265                                         rte_memcpy(&mv_f[i].macaddr,
7266                                                         addr, ETH_ADDR_LEN);
7267                                         mv_f[i].vlan_id =
7268                                                 j * I40E_UINT32_BIT_SIZE + k;
7269                                         i++;
7270                                 }
7271                         }
7272                 }
7273         }
7274         return I40E_SUCCESS;
7275 }
7276
7277 static inline int
7278 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7279                            struct i40e_macvlan_filter *mv_f,
7280                            int num,
7281                            uint16_t vlan)
7282 {
7283         int i = 0;
7284         struct i40e_mac_filter *f;
7285
7286         if (num < vsi->mac_num)
7287                 return I40E_ERR_PARAM;
7288
7289         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7290                 if (i > num - 1) {
7291                         PMD_DRV_LOG(ERR, "buffer number not match");
7292                         return I40E_ERR_PARAM;
7293                 }
7294                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7295                                 ETH_ADDR_LEN);
7296                 mv_f[i].vlan_id = vlan;
7297                 mv_f[i].filter_type = f->mac_info.filter_type;
7298                 i++;
7299         }
7300
7301         return I40E_SUCCESS;
7302 }
7303
7304 static int
7305 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7306 {
7307         int i, j, num;
7308         struct i40e_mac_filter *f;
7309         struct i40e_macvlan_filter *mv_f;
7310         int ret = I40E_SUCCESS;
7311
7312         if (vsi == NULL || vsi->mac_num == 0)
7313                 return I40E_ERR_PARAM;
7314
7315         /* Case that no vlan is set */
7316         if (vsi->vlan_num == 0)
7317                 num = vsi->mac_num;
7318         else
7319                 num = vsi->mac_num * vsi->vlan_num;
7320
7321         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7322         if (mv_f == NULL) {
7323                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7324                 return I40E_ERR_NO_MEMORY;
7325         }
7326
7327         i = 0;
7328         if (vsi->vlan_num == 0) {
7329                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7330                         rte_memcpy(&mv_f[i].macaddr,
7331                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7332                         mv_f[i].filter_type = f->mac_info.filter_type;
7333                         mv_f[i].vlan_id = 0;
7334                         i++;
7335                 }
7336         } else {
7337                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7338                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7339                                         vsi->vlan_num, &f->mac_info.mac_addr);
7340                         if (ret != I40E_SUCCESS)
7341                                 goto DONE;
7342                         for (j = i; j < i + vsi->vlan_num; j++)
7343                                 mv_f[j].filter_type = f->mac_info.filter_type;
7344                         i += vsi->vlan_num;
7345                 }
7346         }
7347
7348         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7349 DONE:
7350         rte_free(mv_f);
7351
7352         return ret;
7353 }
7354
7355 int
7356 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7357 {
7358         struct i40e_macvlan_filter *mv_f;
7359         int mac_num;
7360         int ret = I40E_SUCCESS;
7361
7362         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7363                 return I40E_ERR_PARAM;
7364
7365         /* If it's already set, just return */
7366         if (i40e_find_vlan_filter(vsi,vlan))
7367                 return I40E_SUCCESS;
7368
7369         mac_num = vsi->mac_num;
7370
7371         if (mac_num == 0) {
7372                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7373                 return I40E_ERR_PARAM;
7374         }
7375
7376         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7377
7378         if (mv_f == NULL) {
7379                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7380                 return I40E_ERR_NO_MEMORY;
7381         }
7382
7383         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7384
7385         if (ret != I40E_SUCCESS)
7386                 goto DONE;
7387
7388         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7389
7390         if (ret != I40E_SUCCESS)
7391                 goto DONE;
7392
7393         i40e_set_vlan_filter(vsi, vlan, 1);
7394
7395         vsi->vlan_num++;
7396         ret = I40E_SUCCESS;
7397 DONE:
7398         rte_free(mv_f);
7399         return ret;
7400 }
7401
7402 int
7403 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7404 {
7405         struct i40e_macvlan_filter *mv_f;
7406         int mac_num;
7407         int ret = I40E_SUCCESS;
7408
7409         /**
7410          * Vlan 0 is the generic filter for untagged packets
7411          * and can't be removed.
7412          */
7413         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7414                 return I40E_ERR_PARAM;
7415
7416         /* If can't find it, just return */
7417         if (!i40e_find_vlan_filter(vsi, vlan))
7418                 return I40E_ERR_PARAM;
7419
7420         mac_num = vsi->mac_num;
7421
7422         if (mac_num == 0) {
7423                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7424                 return I40E_ERR_PARAM;
7425         }
7426
7427         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7428
7429         if (mv_f == NULL) {
7430                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7431                 return I40E_ERR_NO_MEMORY;
7432         }
7433
7434         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7435
7436         if (ret != I40E_SUCCESS)
7437                 goto DONE;
7438
7439         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7440
7441         if (ret != I40E_SUCCESS)
7442                 goto DONE;
7443
7444         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7445         if (vsi->vlan_num == 1) {
7446                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7447                 if (ret != I40E_SUCCESS)
7448                         goto DONE;
7449
7450                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7451                 if (ret != I40E_SUCCESS)
7452                         goto DONE;
7453         }
7454
7455         i40e_set_vlan_filter(vsi, vlan, 0);
7456
7457         vsi->vlan_num--;
7458         ret = I40E_SUCCESS;
7459 DONE:
7460         rte_free(mv_f);
7461         return ret;
7462 }
7463
7464 int
7465 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7466 {
7467         struct i40e_mac_filter *f;
7468         struct i40e_macvlan_filter *mv_f;
7469         int i, vlan_num = 0;
7470         int ret = I40E_SUCCESS;
7471
7472         /* If it's add and we've config it, return */
7473         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7474         if (f != NULL)
7475                 return I40E_SUCCESS;
7476         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7477                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7478
7479                 /**
7480                  * If vlan_num is 0, that's the first time to add mac,
7481                  * set mask for vlan_id 0.
7482                  */
7483                 if (vsi->vlan_num == 0) {
7484                         i40e_set_vlan_filter(vsi, 0, 1);
7485                         vsi->vlan_num = 1;
7486                 }
7487                 vlan_num = vsi->vlan_num;
7488         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7489                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7490                 vlan_num = 1;
7491
7492         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7493         if (mv_f == NULL) {
7494                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7495                 return I40E_ERR_NO_MEMORY;
7496         }
7497
7498         for (i = 0; i < vlan_num; i++) {
7499                 mv_f[i].filter_type = mac_filter->filter_type;
7500                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7501                                 ETH_ADDR_LEN);
7502         }
7503
7504         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7505                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7506                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7507                                         &mac_filter->mac_addr);
7508                 if (ret != I40E_SUCCESS)
7509                         goto DONE;
7510         }
7511
7512         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7513         if (ret != I40E_SUCCESS)
7514                 goto DONE;
7515
7516         /* Add the mac addr into mac list */
7517         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7518         if (f == NULL) {
7519                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7520                 ret = I40E_ERR_NO_MEMORY;
7521                 goto DONE;
7522         }
7523         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7524                         ETH_ADDR_LEN);
7525         f->mac_info.filter_type = mac_filter->filter_type;
7526         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7527         vsi->mac_num++;
7528
7529         ret = I40E_SUCCESS;
7530 DONE:
7531         rte_free(mv_f);
7532
7533         return ret;
7534 }
7535
7536 int
7537 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7538 {
7539         struct i40e_mac_filter *f;
7540         struct i40e_macvlan_filter *mv_f;
7541         int i, vlan_num;
7542         enum rte_mac_filter_type filter_type;
7543         int ret = I40E_SUCCESS;
7544
7545         /* Can't find it, return an error */
7546         f = i40e_find_mac_filter(vsi, addr);
7547         if (f == NULL)
7548                 return I40E_ERR_PARAM;
7549
7550         vlan_num = vsi->vlan_num;
7551         filter_type = f->mac_info.filter_type;
7552         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7553                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7554                 if (vlan_num == 0) {
7555                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7556                         return I40E_ERR_PARAM;
7557                 }
7558         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7559                         filter_type == RTE_MAC_HASH_MATCH)
7560                 vlan_num = 1;
7561
7562         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7563         if (mv_f == NULL) {
7564                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7565                 return I40E_ERR_NO_MEMORY;
7566         }
7567
7568         for (i = 0; i < vlan_num; i++) {
7569                 mv_f[i].filter_type = filter_type;
7570                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7571                                 ETH_ADDR_LEN);
7572         }
7573         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7574                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7575                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7576                 if (ret != I40E_SUCCESS)
7577                         goto DONE;
7578         }
7579
7580         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7581         if (ret != I40E_SUCCESS)
7582                 goto DONE;
7583
7584         /* Remove the mac addr into mac list */
7585         TAILQ_REMOVE(&vsi->mac_list, f, next);
7586         rte_free(f);
7587         vsi->mac_num--;
7588
7589         ret = I40E_SUCCESS;
7590 DONE:
7591         rte_free(mv_f);
7592         return ret;
7593 }
7594
7595 /* Configure hash enable flags for RSS */
7596 uint64_t
7597 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7598 {
7599         uint64_t hena = 0;
7600         int i;
7601
7602         if (!flags)
7603                 return hena;
7604
7605         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7606                 if (flags & (1ULL << i))
7607                         hena |= adapter->pctypes_tbl[i];
7608         }
7609
7610         return hena;
7611 }
7612
7613 /* Parse the hash enable flags */
7614 uint64_t
7615 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7616 {
7617         uint64_t rss_hf = 0;
7618
7619         if (!flags)
7620                 return rss_hf;
7621         int i;
7622
7623         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7624                 if (flags & adapter->pctypes_tbl[i])
7625                         rss_hf |= (1ULL << i);
7626         }
7627         return rss_hf;
7628 }
7629
7630 /* Disable RSS */
7631 static void
7632 i40e_pf_disable_rss(struct i40e_pf *pf)
7633 {
7634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7635
7636         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7637         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7638         I40E_WRITE_FLUSH(hw);
7639 }
7640
7641 int
7642 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7643 {
7644         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7645         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7646         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7647                            I40E_VFQF_HKEY_MAX_INDEX :
7648                            I40E_PFQF_HKEY_MAX_INDEX;
7649         int ret = 0;
7650
7651         if (!key || key_len == 0) {
7652                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7653                 return 0;
7654         } else if (key_len != (key_idx + 1) *
7655                 sizeof(uint32_t)) {
7656                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7657                 return -EINVAL;
7658         }
7659
7660         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7661                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7662                         (struct i40e_aqc_get_set_rss_key_data *)key;
7663
7664                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7665                 if (ret)
7666                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7667         } else {
7668                 uint32_t *hash_key = (uint32_t *)key;
7669                 uint16_t i;
7670
7671                 if (vsi->type == I40E_VSI_SRIOV) {
7672                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7673                                 I40E_WRITE_REG(
7674                                         hw,
7675                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7676                                         hash_key[i]);
7677
7678                 } else {
7679                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7680                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7681                                                hash_key[i]);
7682                 }
7683                 I40E_WRITE_FLUSH(hw);
7684         }
7685
7686         return ret;
7687 }
7688
7689 static int
7690 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7691 {
7692         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7693         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7694         uint32_t reg;
7695         int ret;
7696
7697         if (!key || !key_len)
7698                 return 0;
7699
7700         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7701                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7702                         (struct i40e_aqc_get_set_rss_key_data *)key);
7703                 if (ret) {
7704                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7705                         return ret;
7706                 }
7707         } else {
7708                 uint32_t *key_dw = (uint32_t *)key;
7709                 uint16_t i;
7710
7711                 if (vsi->type == I40E_VSI_SRIOV) {
7712                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7713                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7714                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7715                         }
7716                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7717                                    sizeof(uint32_t);
7718                 } else {
7719                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7720                                 reg = I40E_PFQF_HKEY(i);
7721                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7722                         }
7723                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7724                                    sizeof(uint32_t);
7725                 }
7726         }
7727         return 0;
7728 }
7729
7730 static int
7731 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7732 {
7733         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7734         uint64_t hena;
7735         int ret;
7736
7737         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7738                                rss_conf->rss_key_len);
7739         if (ret)
7740                 return ret;
7741
7742         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7743         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7744         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7745         I40E_WRITE_FLUSH(hw);
7746
7747         return 0;
7748 }
7749
7750 static int
7751 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7752                          struct rte_eth_rss_conf *rss_conf)
7753 {
7754         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7755         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7757         uint64_t hena;
7758
7759         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7760         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7761
7762         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7763                 if (rss_hf != 0) /* Enable RSS */
7764                         return -EINVAL;
7765                 return 0; /* Nothing to do */
7766         }
7767         /* RSS enabled */
7768         if (rss_hf == 0) /* Disable RSS */
7769                 return -EINVAL;
7770
7771         return i40e_hw_rss_hash_set(pf, rss_conf);
7772 }
7773
7774 static int
7775 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7776                            struct rte_eth_rss_conf *rss_conf)
7777 {
7778         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7779         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7780         uint64_t hena;
7781         int ret;
7782
7783         if (!rss_conf)
7784                 return -EINVAL;
7785
7786         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7787                          &rss_conf->rss_key_len);
7788         if (ret)
7789                 return ret;
7790
7791         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7792         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7793         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7794
7795         return 0;
7796 }
7797
7798 static int
7799 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7800 {
7801         switch (filter_type) {
7802         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7803                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7804                 break;
7805         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7806                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7807                 break;
7808         case RTE_TUNNEL_FILTER_IMAC_TENID:
7809                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7810                 break;
7811         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7812                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7813                 break;
7814         case ETH_TUNNEL_FILTER_IMAC:
7815                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7816                 break;
7817         case ETH_TUNNEL_FILTER_OIP:
7818                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7819                 break;
7820         case ETH_TUNNEL_FILTER_IIP:
7821                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7822                 break;
7823         default:
7824                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7825                 return -EINVAL;
7826         }
7827
7828         return 0;
7829 }
7830
7831 /* Convert tunnel filter structure */
7832 static int
7833 i40e_tunnel_filter_convert(
7834         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7835         struct i40e_tunnel_filter *tunnel_filter)
7836 {
7837         rte_ether_addr_copy((struct rte_ether_addr *)
7838                         &cld_filter->element.outer_mac,
7839                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7840         rte_ether_addr_copy((struct rte_ether_addr *)
7841                         &cld_filter->element.inner_mac,
7842                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7843         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7844         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7845              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7846             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7847                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7848         else
7849                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7850         tunnel_filter->input.flags = cld_filter->element.flags;
7851         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7852         tunnel_filter->queue = cld_filter->element.queue_number;
7853         rte_memcpy(tunnel_filter->input.general_fields,
7854                    cld_filter->general_fields,
7855                    sizeof(cld_filter->general_fields));
7856
7857         return 0;
7858 }
7859
7860 /* Check if there exists the tunnel filter */
7861 struct i40e_tunnel_filter *
7862 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7863                              const struct i40e_tunnel_filter_input *input)
7864 {
7865         int ret;
7866
7867         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7868         if (ret < 0)
7869                 return NULL;
7870
7871         return tunnel_rule->hash_map[ret];
7872 }
7873
7874 /* Add a tunnel filter into the SW list */
7875 static int
7876 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7877                              struct i40e_tunnel_filter *tunnel_filter)
7878 {
7879         struct i40e_tunnel_rule *rule = &pf->tunnel;
7880         int ret;
7881
7882         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7883         if (ret < 0) {
7884                 PMD_DRV_LOG(ERR,
7885                             "Failed to insert tunnel filter to hash table %d!",
7886                             ret);
7887                 return ret;
7888         }
7889         rule->hash_map[ret] = tunnel_filter;
7890
7891         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7892
7893         return 0;
7894 }
7895
7896 /* Delete a tunnel filter from the SW list */
7897 int
7898 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7899                           struct i40e_tunnel_filter_input *input)
7900 {
7901         struct i40e_tunnel_rule *rule = &pf->tunnel;
7902         struct i40e_tunnel_filter *tunnel_filter;
7903         int ret;
7904
7905         ret = rte_hash_del_key(rule->hash_table, input);
7906         if (ret < 0) {
7907                 PMD_DRV_LOG(ERR,
7908                             "Failed to delete tunnel filter to hash table %d!",
7909                             ret);
7910                 return ret;
7911         }
7912         tunnel_filter = rule->hash_map[ret];
7913         rule->hash_map[ret] = NULL;
7914
7915         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7916         rte_free(tunnel_filter);
7917
7918         return 0;
7919 }
7920
7921 int
7922 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7923                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7924                         uint8_t add)
7925 {
7926         uint16_t ip_type;
7927         uint32_t ipv4_addr, ipv4_addr_le;
7928         uint8_t i, tun_type = 0;
7929         /* internal varialbe to convert ipv6 byte order */
7930         uint32_t convert_ipv6[4];
7931         int val, ret = 0;
7932         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7933         struct i40e_vsi *vsi = pf->main_vsi;
7934         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7935         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7936         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7937         struct i40e_tunnel_filter *tunnel, *node;
7938         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7939
7940         cld_filter = rte_zmalloc("tunnel_filter",
7941                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7942         0);
7943
7944         if (NULL == cld_filter) {
7945                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7946                 return -ENOMEM;
7947         }
7948         pfilter = cld_filter;
7949
7950         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7951                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7952         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7953                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7954
7955         pfilter->element.inner_vlan =
7956                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7957         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7958                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7959                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7960                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7961                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7962                                 &ipv4_addr_le,
7963                                 sizeof(pfilter->element.ipaddr.v4.data));
7964         } else {
7965                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7966                 for (i = 0; i < 4; i++) {
7967                         convert_ipv6[i] =
7968                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7969                 }
7970                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7971                            &convert_ipv6,
7972                            sizeof(pfilter->element.ipaddr.v6.data));
7973         }
7974
7975         /* check tunneled type */
7976         switch (tunnel_filter->tunnel_type) {
7977         case RTE_TUNNEL_TYPE_VXLAN:
7978                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7979                 break;
7980         case RTE_TUNNEL_TYPE_NVGRE:
7981                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7982                 break;
7983         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7984                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7985                 break;
7986         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7987                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7988                 break;
7989         default:
7990                 /* Other tunnel types is not supported. */
7991                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7992                 rte_free(cld_filter);
7993                 return -EINVAL;
7994         }
7995
7996         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7997                                        &pfilter->element.flags);
7998         if (val < 0) {
7999                 rte_free(cld_filter);
8000                 return -EINVAL;
8001         }
8002
8003         pfilter->element.flags |= rte_cpu_to_le_16(
8004                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8005                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8006         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8007         pfilter->element.queue_number =
8008                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8009
8010         /* Check if there is the filter in SW list */
8011         memset(&check_filter, 0, sizeof(check_filter));
8012         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8013         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8014         if (add && node) {
8015                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8016                 rte_free(cld_filter);
8017                 return -EINVAL;
8018         }
8019
8020         if (!add && !node) {
8021                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8022                 rte_free(cld_filter);
8023                 return -EINVAL;
8024         }
8025
8026         if (add) {
8027                 ret = i40e_aq_add_cloud_filters(hw,
8028                                         vsi->seid, &cld_filter->element, 1);
8029                 if (ret < 0) {
8030                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8031                         rte_free(cld_filter);
8032                         return -ENOTSUP;
8033                 }
8034                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8035                 if (tunnel == NULL) {
8036                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8037                         rte_free(cld_filter);
8038                         return -ENOMEM;
8039                 }
8040
8041                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8042                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8043                 if (ret < 0)
8044                         rte_free(tunnel);
8045         } else {
8046                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8047                                                    &cld_filter->element, 1);
8048                 if (ret < 0) {
8049                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8050                         rte_free(cld_filter);
8051                         return -ENOTSUP;
8052                 }
8053                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8054         }
8055
8056         rte_free(cld_filter);
8057         return ret;
8058 }
8059
8060 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8061 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
8062 #define I40E_TR_GENEVE_KEY_MASK                 0x8
8063 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
8064 #define I40E_TR_GRE_KEY_MASK                    0x400
8065 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
8066 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
8067 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8068 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8069 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8070 #define I40E_DIRECTION_INGRESS_KEY              0x8000
8071 #define I40E_TR_L4_TYPE_TCP                     0x2
8072 #define I40E_TR_L4_TYPE_UDP                     0x4
8073 #define I40E_TR_L4_TYPE_SCTP                    0x8
8074
8075 static enum
8076 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8077 {
8078         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8079         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8080         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8081         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8082         enum i40e_status_code status = I40E_SUCCESS;
8083
8084         if (pf->support_multi_driver) {
8085                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8086                 return I40E_NOT_SUPPORTED;
8087         }
8088
8089         memset(&filter_replace, 0,
8090                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8091         memset(&filter_replace_buf, 0,
8092                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8093
8094         /* create L1 filter */
8095         filter_replace.old_filter_type =
8096                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8097         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8098         filter_replace.tr_bit = 0;
8099
8100         /* Prepare the buffer, 3 entries */
8101         filter_replace_buf.data[0] =
8102                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8103         filter_replace_buf.data[0] |=
8104                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8105         filter_replace_buf.data[2] = 0xFF;
8106         filter_replace_buf.data[3] = 0xFF;
8107         filter_replace_buf.data[4] =
8108                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8109         filter_replace_buf.data[4] |=
8110                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8111         filter_replace_buf.data[7] = 0xF0;
8112         filter_replace_buf.data[8]
8113                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8114         filter_replace_buf.data[8] |=
8115                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8116         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8117                 I40E_TR_GENEVE_KEY_MASK |
8118                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8119         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8120                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8121                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8122
8123         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8124                                                &filter_replace_buf);
8125         if (!status && (filter_replace.old_filter_type !=
8126                         filter_replace.new_filter_type))
8127                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8128                             " original: 0x%x, new: 0x%x",
8129                             dev->device->name,
8130                             filter_replace.old_filter_type,
8131                             filter_replace.new_filter_type);
8132
8133         return status;
8134 }
8135
8136 static enum
8137 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8138 {
8139         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8140         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8141         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8142         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8143         enum i40e_status_code status = I40E_SUCCESS;
8144
8145         if (pf->support_multi_driver) {
8146                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8147                 return I40E_NOT_SUPPORTED;
8148         }
8149
8150         /* For MPLSoUDP */
8151         memset(&filter_replace, 0,
8152                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8153         memset(&filter_replace_buf, 0,
8154                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8155         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8156                 I40E_AQC_MIRROR_CLOUD_FILTER;
8157         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8158         filter_replace.new_filter_type =
8159                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8160         /* Prepare the buffer, 2 entries */
8161         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8162         filter_replace_buf.data[0] |=
8163                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8164         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8165         filter_replace_buf.data[4] |=
8166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8167         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8168                                                &filter_replace_buf);
8169         if (status < 0)
8170                 return status;
8171         if (filter_replace.old_filter_type !=
8172             filter_replace.new_filter_type)
8173                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8174                             " original: 0x%x, new: 0x%x",
8175                             dev->device->name,
8176                             filter_replace.old_filter_type,
8177                             filter_replace.new_filter_type);
8178
8179         /* For MPLSoGRE */
8180         memset(&filter_replace, 0,
8181                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8182         memset(&filter_replace_buf, 0,
8183                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8184
8185         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8186                 I40E_AQC_MIRROR_CLOUD_FILTER;
8187         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8188         filter_replace.new_filter_type =
8189                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8190         /* Prepare the buffer, 2 entries */
8191         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8192         filter_replace_buf.data[0] |=
8193                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8194         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8195         filter_replace_buf.data[4] |=
8196                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8197
8198         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8199                                                &filter_replace_buf);
8200         if (!status && (filter_replace.old_filter_type !=
8201                         filter_replace.new_filter_type))
8202                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8203                             " original: 0x%x, new: 0x%x",
8204                             dev->device->name,
8205                             filter_replace.old_filter_type,
8206                             filter_replace.new_filter_type);
8207
8208         return status;
8209 }
8210
8211 static enum i40e_status_code
8212 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8213 {
8214         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8215         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8216         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8217         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8218         enum i40e_status_code status = I40E_SUCCESS;
8219
8220         if (pf->support_multi_driver) {
8221                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8222                 return I40E_NOT_SUPPORTED;
8223         }
8224
8225         /* For GTP-C */
8226         memset(&filter_replace, 0,
8227                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8228         memset(&filter_replace_buf, 0,
8229                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8230         /* create L1 filter */
8231         filter_replace.old_filter_type =
8232                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8233         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8234         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8235                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8236         /* Prepare the buffer, 2 entries */
8237         filter_replace_buf.data[0] =
8238                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8239         filter_replace_buf.data[0] |=
8240                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8241         filter_replace_buf.data[2] = 0xFF;
8242         filter_replace_buf.data[3] = 0xFF;
8243         filter_replace_buf.data[4] =
8244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8245         filter_replace_buf.data[4] |=
8246                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8247         filter_replace_buf.data[6] = 0xFF;
8248         filter_replace_buf.data[7] = 0xFF;
8249         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8250                                                &filter_replace_buf);
8251         if (status < 0)
8252                 return status;
8253         if (filter_replace.old_filter_type !=
8254             filter_replace.new_filter_type)
8255                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8256                             " original: 0x%x, new: 0x%x",
8257                             dev->device->name,
8258                             filter_replace.old_filter_type,
8259                             filter_replace.new_filter_type);
8260
8261         /* for GTP-U */
8262         memset(&filter_replace, 0,
8263                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8264         memset(&filter_replace_buf, 0,
8265                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8266         /* create L1 filter */
8267         filter_replace.old_filter_type =
8268                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8269         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8270         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8271                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8272         /* Prepare the buffer, 2 entries */
8273         filter_replace_buf.data[0] =
8274                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8275         filter_replace_buf.data[0] |=
8276                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8277         filter_replace_buf.data[2] = 0xFF;
8278         filter_replace_buf.data[3] = 0xFF;
8279         filter_replace_buf.data[4] =
8280                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8281         filter_replace_buf.data[4] |=
8282                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8283         filter_replace_buf.data[6] = 0xFF;
8284         filter_replace_buf.data[7] = 0xFF;
8285
8286         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8287                                                &filter_replace_buf);
8288         if (!status && (filter_replace.old_filter_type !=
8289                         filter_replace.new_filter_type))
8290                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8291                             " original: 0x%x, new: 0x%x",
8292                             dev->device->name,
8293                             filter_replace.old_filter_type,
8294                             filter_replace.new_filter_type);
8295
8296         return status;
8297 }
8298
8299 static enum
8300 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8301 {
8302         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8303         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8304         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8305         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8306         enum i40e_status_code status = I40E_SUCCESS;
8307
8308         if (pf->support_multi_driver) {
8309                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8310                 return I40E_NOT_SUPPORTED;
8311         }
8312
8313         /* for GTP-C */
8314         memset(&filter_replace, 0,
8315                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8316         memset(&filter_replace_buf, 0,
8317                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8318         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8319         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8320         filter_replace.new_filter_type =
8321                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8322         /* Prepare the buffer, 2 entries */
8323         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8324         filter_replace_buf.data[0] |=
8325                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8326         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8327         filter_replace_buf.data[4] |=
8328                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8329         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8330                                                &filter_replace_buf);
8331         if (status < 0)
8332                 return status;
8333         if (filter_replace.old_filter_type !=
8334             filter_replace.new_filter_type)
8335                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8336                             " original: 0x%x, new: 0x%x",
8337                             dev->device->name,
8338                             filter_replace.old_filter_type,
8339                             filter_replace.new_filter_type);
8340
8341         /* for GTP-U */
8342         memset(&filter_replace, 0,
8343                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8344         memset(&filter_replace_buf, 0,
8345                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8346         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8347         filter_replace.old_filter_type =
8348                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8349         filter_replace.new_filter_type =
8350                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8351         /* Prepare the buffer, 2 entries */
8352         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8353         filter_replace_buf.data[0] |=
8354                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8355         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8356         filter_replace_buf.data[4] |=
8357                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8358
8359         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8360                                                &filter_replace_buf);
8361         if (!status && (filter_replace.old_filter_type !=
8362                         filter_replace.new_filter_type))
8363                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8364                             " original: 0x%x, new: 0x%x",
8365                             dev->device->name,
8366                             filter_replace.old_filter_type,
8367                             filter_replace.new_filter_type);
8368
8369         return status;
8370 }
8371
8372 static enum i40e_status_code
8373 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8374                             enum i40e_l4_port_type l4_port_type)
8375 {
8376         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8377         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8378         enum i40e_status_code status = I40E_SUCCESS;
8379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8380         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8381
8382         if (pf->support_multi_driver) {
8383                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8384                 return I40E_NOT_SUPPORTED;
8385         }
8386
8387         memset(&filter_replace, 0,
8388                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8389         memset(&filter_replace_buf, 0,
8390                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8391
8392         /* create L1 filter */
8393         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8394                 filter_replace.old_filter_type =
8395                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8396                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8397                 filter_replace_buf.data[8] =
8398                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8399         } else {
8400                 filter_replace.old_filter_type =
8401                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8402                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8403                 filter_replace_buf.data[8] =
8404                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8405         }
8406
8407         filter_replace.tr_bit = 0;
8408         /* Prepare the buffer, 3 entries */
8409         filter_replace_buf.data[0] =
8410                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8411         filter_replace_buf.data[0] |=
8412                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8413         filter_replace_buf.data[2] = 0x00;
8414         filter_replace_buf.data[3] =
8415                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8416         filter_replace_buf.data[4] =
8417                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8418         filter_replace_buf.data[4] |=
8419                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8420         filter_replace_buf.data[5] = 0x00;
8421         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8422                 I40E_TR_L4_TYPE_TCP |
8423                 I40E_TR_L4_TYPE_SCTP;
8424         filter_replace_buf.data[7] = 0x00;
8425         filter_replace_buf.data[8] |=
8426                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8427         filter_replace_buf.data[9] = 0x00;
8428         filter_replace_buf.data[10] = 0xFF;
8429         filter_replace_buf.data[11] = 0xFF;
8430
8431         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8432                                                &filter_replace_buf);
8433         if (!status && filter_replace.old_filter_type !=
8434             filter_replace.new_filter_type)
8435                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8436                             " original: 0x%x, new: 0x%x",
8437                             dev->device->name,
8438                             filter_replace.old_filter_type,
8439                             filter_replace.new_filter_type);
8440
8441         return status;
8442 }
8443
8444 static enum i40e_status_code
8445 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8446                                enum i40e_l4_port_type l4_port_type)
8447 {
8448         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8449         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8450         enum i40e_status_code status = I40E_SUCCESS;
8451         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8452         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8453
8454         if (pf->support_multi_driver) {
8455                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8456                 return I40E_NOT_SUPPORTED;
8457         }
8458
8459         memset(&filter_replace, 0,
8460                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8461         memset(&filter_replace_buf, 0,
8462                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8463
8464         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8465                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8466                 filter_replace.new_filter_type =
8467                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8468                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8469         } else {
8470                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8471                 filter_replace.new_filter_type =
8472                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8473                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8474         }
8475
8476         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8477         filter_replace.tr_bit = 0;
8478         /* Prepare the buffer, 2 entries */
8479         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8480         filter_replace_buf.data[0] |=
8481                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8482         filter_replace_buf.data[4] |=
8483                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8484         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8485                                                &filter_replace_buf);
8486
8487         if (!status && filter_replace.old_filter_type !=
8488             filter_replace.new_filter_type)
8489                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8490                             " original: 0x%x, new: 0x%x",
8491                             dev->device->name,
8492                             filter_replace.old_filter_type,
8493                             filter_replace.new_filter_type);
8494
8495         return status;
8496 }
8497
8498 int
8499 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8500                       struct i40e_tunnel_filter_conf *tunnel_filter,
8501                       uint8_t add)
8502 {
8503         uint16_t ip_type;
8504         uint32_t ipv4_addr, ipv4_addr_le;
8505         uint8_t i, tun_type = 0;
8506         /* internal variable to convert ipv6 byte order */
8507         uint32_t convert_ipv6[4];
8508         int val, ret = 0;
8509         struct i40e_pf_vf *vf = NULL;
8510         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8511         struct i40e_vsi *vsi;
8512         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8513         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8514         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8515         struct i40e_tunnel_filter *tunnel, *node;
8516         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8517         uint32_t teid_le;
8518         bool big_buffer = 0;
8519
8520         cld_filter = rte_zmalloc("tunnel_filter",
8521                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8522                          0);
8523
8524         if (cld_filter == NULL) {
8525                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8526                 return -ENOMEM;
8527         }
8528         pfilter = cld_filter;
8529
8530         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8531                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8532         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8533                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8534
8535         pfilter->element.inner_vlan =
8536                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8537         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8538                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8539                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8540                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8541                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8542                                 &ipv4_addr_le,
8543                                 sizeof(pfilter->element.ipaddr.v4.data));
8544         } else {
8545                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8546                 for (i = 0; i < 4; i++) {
8547                         convert_ipv6[i] =
8548                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8549                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8550                 }
8551                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8552                            &convert_ipv6,
8553                            sizeof(pfilter->element.ipaddr.v6.data));
8554         }
8555
8556         /* check tunneled type */
8557         switch (tunnel_filter->tunnel_type) {
8558         case I40E_TUNNEL_TYPE_VXLAN:
8559                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8560                 break;
8561         case I40E_TUNNEL_TYPE_NVGRE:
8562                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8563                 break;
8564         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8565                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8566                 break;
8567         case I40E_TUNNEL_TYPE_MPLSoUDP:
8568                 if (!pf->mpls_replace_flag) {
8569                         i40e_replace_mpls_l1_filter(pf);
8570                         i40e_replace_mpls_cloud_filter(pf);
8571                         pf->mpls_replace_flag = 1;
8572                 }
8573                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8574                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8575                         teid_le >> 4;
8576                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8577                         (teid_le & 0xF) << 12;
8578                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8579                         0x40;
8580                 big_buffer = 1;
8581                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8582                 break;
8583         case I40E_TUNNEL_TYPE_MPLSoGRE:
8584                 if (!pf->mpls_replace_flag) {
8585                         i40e_replace_mpls_l1_filter(pf);
8586                         i40e_replace_mpls_cloud_filter(pf);
8587                         pf->mpls_replace_flag = 1;
8588                 }
8589                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8590                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8591                         teid_le >> 4;
8592                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8593                         (teid_le & 0xF) << 12;
8594                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8595                         0x0;
8596                 big_buffer = 1;
8597                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8598                 break;
8599         case I40E_TUNNEL_TYPE_GTPC:
8600                 if (!pf->gtp_replace_flag) {
8601                         i40e_replace_gtp_l1_filter(pf);
8602                         i40e_replace_gtp_cloud_filter(pf);
8603                         pf->gtp_replace_flag = 1;
8604                 }
8605                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8606                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8607                         (teid_le >> 16) & 0xFFFF;
8608                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8609                         teid_le & 0xFFFF;
8610                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8611                         0x0;
8612                 big_buffer = 1;
8613                 break;
8614         case I40E_TUNNEL_TYPE_GTPU:
8615                 if (!pf->gtp_replace_flag) {
8616                         i40e_replace_gtp_l1_filter(pf);
8617                         i40e_replace_gtp_cloud_filter(pf);
8618                         pf->gtp_replace_flag = 1;
8619                 }
8620                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8621                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8622                         (teid_le >> 16) & 0xFFFF;
8623                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8624                         teid_le & 0xFFFF;
8625                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8626                         0x0;
8627                 big_buffer = 1;
8628                 break;
8629         case I40E_TUNNEL_TYPE_QINQ:
8630                 if (!pf->qinq_replace_flag) {
8631                         ret = i40e_cloud_filter_qinq_create(pf);
8632                         if (ret < 0)
8633                                 PMD_DRV_LOG(DEBUG,
8634                                             "QinQ tunnel filter already created.");
8635                         pf->qinq_replace_flag = 1;
8636                 }
8637                 /*      Add in the General fields the values of
8638                  *      the Outer and Inner VLAN
8639                  *      Big Buffer should be set, see changes in
8640                  *      i40e_aq_add_cloud_filters
8641                  */
8642                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8643                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8644                 big_buffer = 1;
8645                 break;
8646         case I40E_CLOUD_TYPE_UDP:
8647         case I40E_CLOUD_TYPE_TCP:
8648         case I40E_CLOUD_TYPE_SCTP:
8649                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8650                         if (!pf->sport_replace_flag) {
8651                                 i40e_replace_port_l1_filter(pf,
8652                                                 tunnel_filter->l4_port_type);
8653                                 i40e_replace_port_cloud_filter(pf,
8654                                                 tunnel_filter->l4_port_type);
8655                                 pf->sport_replace_flag = 1;
8656                         }
8657                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8658                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8659                                 I40E_DIRECTION_INGRESS_KEY;
8660
8661                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8662                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8663                                         I40E_TR_L4_TYPE_UDP;
8664                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8665                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8666                                         I40E_TR_L4_TYPE_TCP;
8667                         else
8668                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8669                                         I40E_TR_L4_TYPE_SCTP;
8670
8671                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8672                                 (teid_le >> 16) & 0xFFFF;
8673                         big_buffer = 1;
8674                 } else {
8675                         if (!pf->dport_replace_flag) {
8676                                 i40e_replace_port_l1_filter(pf,
8677                                                 tunnel_filter->l4_port_type);
8678                                 i40e_replace_port_cloud_filter(pf,
8679                                                 tunnel_filter->l4_port_type);
8680                                 pf->dport_replace_flag = 1;
8681                         }
8682                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8683                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8684                                 I40E_DIRECTION_INGRESS_KEY;
8685
8686                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8687                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8688                                         I40E_TR_L4_TYPE_UDP;
8689                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8690                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8691                                         I40E_TR_L4_TYPE_TCP;
8692                         else
8693                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8694                                         I40E_TR_L4_TYPE_SCTP;
8695
8696                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8697                                 (teid_le >> 16) & 0xFFFF;
8698                         big_buffer = 1;
8699                 }
8700
8701                 break;
8702         default:
8703                 /* Other tunnel types is not supported. */
8704                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8705                 rte_free(cld_filter);
8706                 return -EINVAL;
8707         }
8708
8709         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8710                 pfilter->element.flags =
8711                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8712         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8713                 pfilter->element.flags =
8714                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8715         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8716                 pfilter->element.flags =
8717                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8718         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8719                 pfilter->element.flags =
8720                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8721         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8722                 pfilter->element.flags |=
8723                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8724         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8725                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8726                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8727                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8728                         pfilter->element.flags |=
8729                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8730                 else
8731                         pfilter->element.flags |=
8732                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8733         } else {
8734                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8735                                                 &pfilter->element.flags);
8736                 if (val < 0) {
8737                         rte_free(cld_filter);
8738                         return -EINVAL;
8739                 }
8740         }
8741
8742         pfilter->element.flags |= rte_cpu_to_le_16(
8743                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8744                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8745         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8746         pfilter->element.queue_number =
8747                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8748
8749         if (!tunnel_filter->is_to_vf)
8750                 vsi = pf->main_vsi;
8751         else {
8752                 if (tunnel_filter->vf_id >= pf->vf_num) {
8753                         PMD_DRV_LOG(ERR, "Invalid argument.");
8754                         rte_free(cld_filter);
8755                         return -EINVAL;
8756                 }
8757                 vf = &pf->vfs[tunnel_filter->vf_id];
8758                 vsi = vf->vsi;
8759         }
8760
8761         /* Check if there is the filter in SW list */
8762         memset(&check_filter, 0, sizeof(check_filter));
8763         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8764         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8765         check_filter.vf_id = tunnel_filter->vf_id;
8766         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8767         if (add && node) {
8768                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8769                 rte_free(cld_filter);
8770                 return -EINVAL;
8771         }
8772
8773         if (!add && !node) {
8774                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8775                 rte_free(cld_filter);
8776                 return -EINVAL;
8777         }
8778
8779         if (add) {
8780                 if (big_buffer)
8781                         ret = i40e_aq_add_cloud_filters_bb(hw,
8782                                                    vsi->seid, cld_filter, 1);
8783                 else
8784                         ret = i40e_aq_add_cloud_filters(hw,
8785                                         vsi->seid, &cld_filter->element, 1);
8786                 if (ret < 0) {
8787                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8788                         rte_free(cld_filter);
8789                         return -ENOTSUP;
8790                 }
8791                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8792                 if (tunnel == NULL) {
8793                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8794                         rte_free(cld_filter);
8795                         return -ENOMEM;
8796                 }
8797
8798                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8799                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8800                 if (ret < 0)
8801                         rte_free(tunnel);
8802         } else {
8803                 if (big_buffer)
8804                         ret = i40e_aq_rem_cloud_filters_bb(
8805                                 hw, vsi->seid, cld_filter, 1);
8806                 else
8807                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8808                                                 &cld_filter->element, 1);
8809                 if (ret < 0) {
8810                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8811                         rte_free(cld_filter);
8812                         return -ENOTSUP;
8813                 }
8814                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8815         }
8816
8817         rte_free(cld_filter);
8818         return ret;
8819 }
8820
8821 static int
8822 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8823 {
8824         uint8_t i;
8825
8826         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8827                 if (pf->vxlan_ports[i] == port)
8828                         return i;
8829         }
8830
8831         return -1;
8832 }
8833
8834 static int
8835 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8836 {
8837         int  idx, ret;
8838         uint8_t filter_idx = 0;
8839         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8840
8841         idx = i40e_get_vxlan_port_idx(pf, port);
8842
8843         /* Check if port already exists */
8844         if (idx >= 0) {
8845                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8846                 return -EINVAL;
8847         }
8848
8849         /* Now check if there is space to add the new port */
8850         idx = i40e_get_vxlan_port_idx(pf, 0);
8851         if (idx < 0) {
8852                 PMD_DRV_LOG(ERR,
8853                         "Maximum number of UDP ports reached, not adding port %d",
8854                         port);
8855                 return -ENOSPC;
8856         }
8857
8858         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8859                                         &filter_idx, NULL);
8860         if (ret < 0) {
8861                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8862                 return -1;
8863         }
8864
8865         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8866                          port,  filter_idx);
8867
8868         /* New port: add it and mark its index in the bitmap */
8869         pf->vxlan_ports[idx] = port;
8870         pf->vxlan_bitmap |= (1 << idx);
8871
8872         if (!(pf->flags & I40E_FLAG_VXLAN))
8873                 pf->flags |= I40E_FLAG_VXLAN;
8874
8875         return 0;
8876 }
8877
8878 static int
8879 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8880 {
8881         int idx;
8882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8883
8884         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8885                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8886                 return -EINVAL;
8887         }
8888
8889         idx = i40e_get_vxlan_port_idx(pf, port);
8890
8891         if (idx < 0) {
8892                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8893                 return -EINVAL;
8894         }
8895
8896         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8897                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8898                 return -1;
8899         }
8900
8901         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8902                         port, idx);
8903
8904         pf->vxlan_ports[idx] = 0;
8905         pf->vxlan_bitmap &= ~(1 << idx);
8906
8907         if (!pf->vxlan_bitmap)
8908                 pf->flags &= ~I40E_FLAG_VXLAN;
8909
8910         return 0;
8911 }
8912
8913 /* Add UDP tunneling port */
8914 static int
8915 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8916                              struct rte_eth_udp_tunnel *udp_tunnel)
8917 {
8918         int ret = 0;
8919         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8920
8921         if (udp_tunnel == NULL)
8922                 return -EINVAL;
8923
8924         switch (udp_tunnel->prot_type) {
8925         case RTE_TUNNEL_TYPE_VXLAN:
8926                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8927                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8928                 break;
8929         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8930                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8931                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8932                 break;
8933         case RTE_TUNNEL_TYPE_GENEVE:
8934         case RTE_TUNNEL_TYPE_TEREDO:
8935                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8936                 ret = -1;
8937                 break;
8938
8939         default:
8940                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8941                 ret = -1;
8942                 break;
8943         }
8944
8945         return ret;
8946 }
8947
8948 /* Remove UDP tunneling port */
8949 static int
8950 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8951                              struct rte_eth_udp_tunnel *udp_tunnel)
8952 {
8953         int ret = 0;
8954         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8955
8956         if (udp_tunnel == NULL)
8957                 return -EINVAL;
8958
8959         switch (udp_tunnel->prot_type) {
8960         case RTE_TUNNEL_TYPE_VXLAN:
8961         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8962                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8963                 break;
8964         case RTE_TUNNEL_TYPE_GENEVE:
8965         case RTE_TUNNEL_TYPE_TEREDO:
8966                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8967                 ret = -1;
8968                 break;
8969         default:
8970                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8971                 ret = -1;
8972                 break;
8973         }
8974
8975         return ret;
8976 }
8977
8978 /* Calculate the maximum number of contiguous PF queues that are configured */
8979 static int
8980 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8981 {
8982         struct rte_eth_dev_data *data = pf->dev_data;
8983         int i, num;
8984         struct i40e_rx_queue *rxq;
8985
8986         num = 0;
8987         for (i = 0; i < pf->lan_nb_qps; i++) {
8988                 rxq = data->rx_queues[i];
8989                 if (rxq && rxq->q_set)
8990                         num++;
8991                 else
8992                         break;
8993         }
8994
8995         return num;
8996 }
8997
8998 /* Configure RSS */
8999 static int
9000 i40e_pf_config_rss(struct i40e_pf *pf)
9001 {
9002         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9003         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9004         struct rte_eth_rss_conf rss_conf;
9005         uint32_t i, lut = 0;
9006         uint16_t j, num;
9007
9008         /*
9009          * If both VMDQ and RSS enabled, not all of PF queues are configured.
9010          * It's necessary to calculate the actual PF queues that are configured.
9011          */
9012         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
9013                 num = i40e_pf_calc_configured_queues_num(pf);
9014         else
9015                 num = pf->dev_data->nb_rx_queues;
9016
9017         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
9018         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
9019                         num);
9020
9021         if (num == 0) {
9022                 PMD_INIT_LOG(ERR,
9023                         "No PF queues are configured to enable RSS for port %u",
9024                         pf->dev_data->port_id);
9025                 return -ENOTSUP;
9026         }
9027
9028         if (pf->adapter->rss_reta_updated == 0) {
9029                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
9030                         if (j == num)
9031                                 j = 0;
9032                         lut = (lut << 8) | (j & ((0x1 <<
9033                                 hw->func_caps.rss_table_entry_width) - 1));
9034                         if ((i & 3) == 3)
9035                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
9036                                                rte_bswap32(lut));
9037                 }
9038         }
9039
9040         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
9041         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
9042             !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
9043                 i40e_pf_disable_rss(pf);
9044                 return 0;
9045         }
9046         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
9047                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
9048                 /* Random default keys */
9049                 static uint32_t rss_key_default[] = {0x6b793944,
9050                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
9051                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9052                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9053
9054                 rss_conf.rss_key = (uint8_t *)rss_key_default;
9055                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9056                                                         sizeof(uint32_t);
9057         }
9058
9059         return i40e_hw_rss_hash_set(pf, &rss_conf);
9060 }
9061
9062 static int
9063 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9064                                struct rte_eth_tunnel_filter_conf *filter)
9065 {
9066         if (pf == NULL || filter == NULL) {
9067                 PMD_DRV_LOG(ERR, "Invalid parameter");
9068                 return -EINVAL;
9069         }
9070
9071         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9072                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9073                 return -EINVAL;
9074         }
9075
9076         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9077                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9078                 return -EINVAL;
9079         }
9080
9081         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9082                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9083                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9084                 return -EINVAL;
9085         }
9086
9087         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9088                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9089                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9090                 return -EINVAL;
9091         }
9092
9093         return 0;
9094 }
9095
9096 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9097 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9098 int
9099 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9100 {
9101         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9102         uint32_t val, reg;
9103         int ret = -EINVAL;
9104
9105         if (pf->support_multi_driver) {
9106                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9107                 return -ENOTSUP;
9108         }
9109
9110         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9111         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9112
9113         if (len == 3) {
9114                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9115         } else if (len == 4) {
9116                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9117         } else {
9118                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9119                 return ret;
9120         }
9121
9122         if (reg != val) {
9123                 ret = i40e_aq_debug_write_global_register(hw,
9124                                                    I40E_GL_PRS_FVBM(2),
9125                                                    reg, NULL);
9126                 if (ret != 0)
9127                         return ret;
9128                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9129                             "with value 0x%08x",
9130                             I40E_GL_PRS_FVBM(2), reg);
9131         } else {
9132                 ret = 0;
9133         }
9134         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9135                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9136
9137         return ret;
9138 }
9139
9140 static int
9141 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9142 {
9143         int ret = -EINVAL;
9144
9145         if (!hw || !cfg)
9146                 return -EINVAL;
9147
9148         switch (cfg->cfg_type) {
9149         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9150                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9151                 break;
9152         default:
9153                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9154                 break;
9155         }
9156
9157         return ret;
9158 }
9159
9160 static int
9161 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9162                                enum rte_filter_op filter_op,
9163                                void *arg)
9164 {
9165         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9166         int ret = I40E_ERR_PARAM;
9167
9168         switch (filter_op) {
9169         case RTE_ETH_FILTER_SET:
9170                 ret = i40e_dev_global_config_set(hw,
9171                         (struct rte_eth_global_cfg *)arg);
9172                 break;
9173         default:
9174                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9175                 break;
9176         }
9177
9178         return ret;
9179 }
9180
9181 static int
9182 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9183                           enum rte_filter_op filter_op,
9184                           void *arg)
9185 {
9186         struct rte_eth_tunnel_filter_conf *filter;
9187         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9188         int ret = I40E_SUCCESS;
9189
9190         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9191
9192         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9193                 return I40E_ERR_PARAM;
9194
9195         switch (filter_op) {
9196         case RTE_ETH_FILTER_NOP:
9197                 if (!(pf->flags & I40E_FLAG_VXLAN))
9198                         ret = I40E_NOT_SUPPORTED;
9199                 break;
9200         case RTE_ETH_FILTER_ADD:
9201                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9202                 break;
9203         case RTE_ETH_FILTER_DELETE:
9204                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9205                 break;
9206         default:
9207                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9208                 ret = I40E_ERR_PARAM;
9209                 break;
9210         }
9211
9212         return ret;
9213 }
9214
9215 /* Get the symmetric hash enable configurations per port */
9216 static void
9217 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9218 {
9219         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9220
9221         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9222 }
9223
9224 /* Set the symmetric hash enable configurations per port */
9225 static void
9226 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9227 {
9228         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9229
9230         if (enable > 0) {
9231                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9232                         PMD_DRV_LOG(INFO,
9233                                 "Symmetric hash has already been enabled");
9234                         return;
9235                 }
9236                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9237         } else {
9238                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9239                         PMD_DRV_LOG(INFO,
9240                                 "Symmetric hash has already been disabled");
9241                         return;
9242                 }
9243                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9244         }
9245         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9246         I40E_WRITE_FLUSH(hw);
9247 }
9248
9249 /*
9250  * Get global configurations of hash function type and symmetric hash enable
9251  * per flow type (pctype). Note that global configuration means it affects all
9252  * the ports on the same NIC.
9253  */
9254 static int
9255 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9256                                    struct rte_eth_hash_global_conf *g_cfg)
9257 {
9258         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9259         uint32_t reg;
9260         uint16_t i, j;
9261
9262         memset(g_cfg, 0, sizeof(*g_cfg));
9263         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9264         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9265                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9266         else
9267                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9268         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9269                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9270
9271         /*
9272          * As i40e supports less than 64 flow types, only first 64 bits need to
9273          * be checked.
9274          */
9275         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9276                 g_cfg->valid_bit_mask[i] = 0ULL;
9277                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9278         }
9279
9280         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9281
9282         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9283                 if (!adapter->pctypes_tbl[i])
9284                         continue;
9285                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9286                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9287                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9288                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9289                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9290                                         g_cfg->sym_hash_enable_mask[0] |=
9291                                                                 (1ULL << i);
9292                                 }
9293                         }
9294                 }
9295         }
9296
9297         return 0;
9298 }
9299
9300 static int
9301 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9302                               const struct rte_eth_hash_global_conf *g_cfg)
9303 {
9304         uint32_t i;
9305         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9306
9307         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9308                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9309                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9310                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9311                                                 g_cfg->hash_func);
9312                 return -EINVAL;
9313         }
9314
9315         /*
9316          * As i40e supports less than 64 flow types, only first 64 bits need to
9317          * be checked.
9318          */
9319         mask0 = g_cfg->valid_bit_mask[0];
9320         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9321                 if (i == 0) {
9322                         /* Check if any unsupported flow type configured */
9323                         if ((mask0 | i40e_mask) ^ i40e_mask)
9324                                 goto mask_err;
9325                 } else {
9326                         if (g_cfg->valid_bit_mask[i])
9327                                 goto mask_err;
9328                 }
9329         }
9330
9331         return 0;
9332
9333 mask_err:
9334         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9335
9336         return -EINVAL;
9337 }
9338
9339 /*
9340  * Set global configurations of hash function type and symmetric hash enable
9341  * per flow type (pctype). Note any modifying global configuration will affect
9342  * all the ports on the same NIC.
9343  */
9344 static int
9345 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9346                                    struct rte_eth_hash_global_conf *g_cfg)
9347 {
9348         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9349         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9350         int ret;
9351         uint16_t i, j;
9352         uint32_t reg;
9353         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9354
9355         if (pf->support_multi_driver) {
9356                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9357                 return -ENOTSUP;
9358         }
9359
9360         /* Check the input parameters */
9361         ret = i40e_hash_global_config_check(adapter, g_cfg);
9362         if (ret < 0)
9363                 return ret;
9364
9365         /*
9366          * As i40e supports less than 64 flow types, only first 64 bits need to
9367          * be configured.
9368          */
9369         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9370                 if (mask0 & (1UL << i)) {
9371                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9372                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9373
9374                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9375                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9376                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9377                                         i40e_write_global_rx_ctl(hw,
9378                                                           I40E_GLQF_HSYM(j),
9379                                                           reg);
9380                         }
9381                 }
9382         }
9383
9384         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9385         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9386                 /* Toeplitz */
9387                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9388                         PMD_DRV_LOG(DEBUG,
9389                                 "Hash function already set to Toeplitz");
9390                         goto out;
9391                 }
9392                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9393         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9394                 /* Simple XOR */
9395                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9396                         PMD_DRV_LOG(DEBUG,
9397                                 "Hash function already set to Simple XOR");
9398                         goto out;
9399                 }
9400                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9401         } else
9402                 /* Use the default, and keep it as it is */
9403                 goto out;
9404
9405         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9406
9407 out:
9408         I40E_WRITE_FLUSH(hw);
9409
9410         return 0;
9411 }
9412
9413 /**
9414  * Valid input sets for hash and flow director filters per PCTYPE
9415  */
9416 static uint64_t
9417 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9418                 enum rte_filter_type filter)
9419 {
9420         uint64_t valid;
9421
9422         static const uint64_t valid_hash_inset_table[] = {
9423                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9424                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9425                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9426                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9427                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9428                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9429                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9430                         I40E_INSET_FLEX_PAYLOAD,
9431                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9432                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9433                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9434                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9435                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9436                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9437                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9438                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9439                         I40E_INSET_FLEX_PAYLOAD,
9440                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9441                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9442                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9443                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9444                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9445                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9446                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9447                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9448                         I40E_INSET_FLEX_PAYLOAD,
9449                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9450                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9451                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9452                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9453                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9454                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9455                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9456                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9457                         I40E_INSET_FLEX_PAYLOAD,
9458                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9459                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9460                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9461                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9462                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9463                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9466                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9467                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9468                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9469                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9470                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9471                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9472                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9475                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9476                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9477                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9478                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9479                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9480                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9481                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9482                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9483                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9484                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9485                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9486                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9487                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9488                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9489                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9490                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9491                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9492                         I40E_INSET_FLEX_PAYLOAD,
9493                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9494                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9495                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9496                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9497                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9498                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9499                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9500                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9501                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9502                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9503                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9504                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9505                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9506                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9507                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9508                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9509                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9510                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9511                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9512                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9513                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9514                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9515                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9516                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9517                         I40E_INSET_FLEX_PAYLOAD,
9518                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9519                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9520                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9521                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9522                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9523                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9524                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9525                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9526                         I40E_INSET_FLEX_PAYLOAD,
9527                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9528                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9529                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9530                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9531                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9532                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9533                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9534                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9535                         I40E_INSET_FLEX_PAYLOAD,
9536                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9537                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9538                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9539                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9540                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9541                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9542                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9543                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9544                         I40E_INSET_FLEX_PAYLOAD,
9545                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9546                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9547                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9548                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9549                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9550                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9551                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9552                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9553                         I40E_INSET_FLEX_PAYLOAD,
9554                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9555                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9556                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9557                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9558                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9559                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9560                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9561                         I40E_INSET_FLEX_PAYLOAD,
9562                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9563                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9564                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9565                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9566                         I40E_INSET_FLEX_PAYLOAD,
9567         };
9568
9569         /**
9570          * Flow director supports only fields defined in
9571          * union rte_eth_fdir_flow.
9572          */
9573         static const uint64_t valid_fdir_inset_table[] = {
9574                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9575                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9576                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9577                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9578                 I40E_INSET_IPV4_TTL,
9579                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9580                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9581                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9582                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9583                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9584                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9585                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9586                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9587                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9588                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9589                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9590                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9591                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9592                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9593                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9594                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9595                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9596                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9597                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9598                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9599                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9600                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9601                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9602                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9603                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9604                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9605                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9606                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9607                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9608                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9609                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9610                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9611                 I40E_INSET_SCTP_VT,
9612                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9613                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9614                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9615                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9616                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9617                 I40E_INSET_IPV4_TTL,
9618                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9619                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9620                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9621                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9622                 I40E_INSET_IPV6_HOP_LIMIT,
9623                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9624                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9625                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9626                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9627                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9628                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9629                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9630                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9631                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9632                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9633                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9634                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9635                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9636                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9637                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9638                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9639                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9640                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9641                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9642                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9643                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9644                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9645                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9646                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9647                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9649                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9650                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9651                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9652                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9653                 I40E_INSET_SCTP_VT,
9654                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9655                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9656                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9657                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9658                 I40E_INSET_IPV6_HOP_LIMIT,
9659                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9660                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9661                 I40E_INSET_LAST_ETHER_TYPE,
9662         };
9663
9664         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9665                 return 0;
9666         if (filter == RTE_ETH_FILTER_HASH)
9667                 valid = valid_hash_inset_table[pctype];
9668         else
9669                 valid = valid_fdir_inset_table[pctype];
9670
9671         return valid;
9672 }
9673
9674 /**
9675  * Validate if the input set is allowed for a specific PCTYPE
9676  */
9677 int
9678 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9679                 enum rte_filter_type filter, uint64_t inset)
9680 {
9681         uint64_t valid;
9682
9683         valid = i40e_get_valid_input_set(pctype, filter);
9684         if (inset & (~valid))
9685                 return -EINVAL;
9686
9687         return 0;
9688 }
9689
9690 /* default input set fields combination per pctype */
9691 uint64_t
9692 i40e_get_default_input_set(uint16_t pctype)
9693 {
9694         static const uint64_t default_inset_table[] = {
9695                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9696                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9697                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9698                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9699                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9700                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9701                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9702                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9703                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9704                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9705                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9706                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9707                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9708                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9709                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9710                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9711                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9712                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9713                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9714                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9715                         I40E_INSET_SCTP_VT,
9716                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9717                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9718                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9719                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9720                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9721                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9722                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9723                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9724                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9725                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9726                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9727                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9728                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9729                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9730                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9731                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9732                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9733                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9734                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9735                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9736                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9737                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9738                         I40E_INSET_SCTP_VT,
9739                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9740                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9741                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9742                         I40E_INSET_LAST_ETHER_TYPE,
9743         };
9744
9745         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9746                 return 0;
9747
9748         return default_inset_table[pctype];
9749 }
9750
9751 /**
9752  * Parse the input set from index to logical bit masks
9753  */
9754 static int
9755 i40e_parse_input_set(uint64_t *inset,
9756                      enum i40e_filter_pctype pctype,
9757                      enum rte_eth_input_set_field *field,
9758                      uint16_t size)
9759 {
9760         uint16_t i, j;
9761         int ret = -EINVAL;
9762
9763         static const struct {
9764                 enum rte_eth_input_set_field field;
9765                 uint64_t inset;
9766         } inset_convert_table[] = {
9767                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9768                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9769                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9770                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9771                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9772                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9773                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9774                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9775                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9776                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9777                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9778                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9779                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9780                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9781                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9782                         I40E_INSET_IPV6_NEXT_HDR},
9783                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9784                         I40E_INSET_IPV6_HOP_LIMIT},
9785                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9786                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9787                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9788                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9789                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9790                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9791                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9792                         I40E_INSET_SCTP_VT},
9793                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9794                         I40E_INSET_TUNNEL_DMAC},
9795                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9796                         I40E_INSET_VLAN_TUNNEL},
9797                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9798                         I40E_INSET_TUNNEL_ID},
9799                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9800                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9801                         I40E_INSET_FLEX_PAYLOAD_W1},
9802                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9803                         I40E_INSET_FLEX_PAYLOAD_W2},
9804                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9805                         I40E_INSET_FLEX_PAYLOAD_W3},
9806                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9807                         I40E_INSET_FLEX_PAYLOAD_W4},
9808                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9809                         I40E_INSET_FLEX_PAYLOAD_W5},
9810                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9811                         I40E_INSET_FLEX_PAYLOAD_W6},
9812                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9813                         I40E_INSET_FLEX_PAYLOAD_W7},
9814                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9815                         I40E_INSET_FLEX_PAYLOAD_W8},
9816         };
9817
9818         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9819                 return ret;
9820
9821         /* Only one item allowed for default or all */
9822         if (size == 1) {
9823                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9824                         *inset = i40e_get_default_input_set(pctype);
9825                         return 0;
9826                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9827                         *inset = I40E_INSET_NONE;
9828                         return 0;
9829                 }
9830         }
9831
9832         for (i = 0, *inset = 0; i < size; i++) {
9833                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9834                         if (field[i] == inset_convert_table[j].field) {
9835                                 *inset |= inset_convert_table[j].inset;
9836                                 break;
9837                         }
9838                 }
9839
9840                 /* It contains unsupported input set, return immediately */
9841                 if (j == RTE_DIM(inset_convert_table))
9842                         return ret;
9843         }
9844
9845         return 0;
9846 }
9847
9848 /**
9849  * Translate the input set from bit masks to register aware bit masks
9850  * and vice versa
9851  */
9852 uint64_t
9853 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9854 {
9855         uint64_t val = 0;
9856         uint16_t i;
9857
9858         struct inset_map {
9859                 uint64_t inset;
9860                 uint64_t inset_reg;
9861         };
9862
9863         static const struct inset_map inset_map_common[] = {
9864                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9865                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9866                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9867                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9868                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9869                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9870                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9871                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9872                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9873                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9874                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9875                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9876                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9877                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9878                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9879                 {I40E_INSET_TUNNEL_DMAC,
9880                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9881                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9882                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9883                 {I40E_INSET_TUNNEL_SRC_PORT,
9884                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9885                 {I40E_INSET_TUNNEL_DST_PORT,
9886                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9887                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9888                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9889                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9890                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9891                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9892                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9893                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9894                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9895                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9896         };
9897
9898     /* some different registers map in x722*/
9899         static const struct inset_map inset_map_diff_x722[] = {
9900                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9901                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9902                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9903                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9904         };
9905
9906         static const struct inset_map inset_map_diff_not_x722[] = {
9907                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9908                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9909                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9910                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9911         };
9912
9913         if (input == 0)
9914                 return val;
9915
9916         /* Translate input set to register aware inset */
9917         if (type == I40E_MAC_X722) {
9918                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9919                         if (input & inset_map_diff_x722[i].inset)
9920                                 val |= inset_map_diff_x722[i].inset_reg;
9921                 }
9922         } else {
9923                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9924                         if (input & inset_map_diff_not_x722[i].inset)
9925                                 val |= inset_map_diff_not_x722[i].inset_reg;
9926                 }
9927         }
9928
9929         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9930                 if (input & inset_map_common[i].inset)
9931                         val |= inset_map_common[i].inset_reg;
9932         }
9933
9934         return val;
9935 }
9936
9937 int
9938 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9939 {
9940         uint8_t i, idx = 0;
9941         uint64_t inset_need_mask = inset;
9942
9943         static const struct {
9944                 uint64_t inset;
9945                 uint32_t mask;
9946         } inset_mask_map[] = {
9947                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9948                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9949                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9950                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9951                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9952                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9953                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9954                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9955         };
9956
9957         if (!inset || !mask || !nb_elem)
9958                 return 0;
9959
9960         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9961                 /* Clear the inset bit, if no MASK is required,
9962                  * for example proto + ttl
9963                  */
9964                 if ((inset & inset_mask_map[i].inset) ==
9965                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9966                         inset_need_mask &= ~inset_mask_map[i].inset;
9967                 if (!inset_need_mask)
9968                         return 0;
9969         }
9970         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9971                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9972                     inset_mask_map[i].inset) {
9973                         if (idx >= nb_elem) {
9974                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9975                                 return -EINVAL;
9976                         }
9977                         mask[idx] = inset_mask_map[i].mask;
9978                         idx++;
9979                 }
9980         }
9981
9982         return idx;
9983 }
9984
9985 void
9986 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9987 {
9988         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9989
9990         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9991         if (reg != val)
9992                 i40e_write_rx_ctl(hw, addr, val);
9993         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9994                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9995 }
9996
9997 void
9998 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9999 {
10000         uint32_t reg = i40e_read_rx_ctl(hw, addr);
10001         struct rte_eth_dev *dev;
10002
10003         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
10004         if (reg != val) {
10005                 i40e_write_rx_ctl(hw, addr, val);
10006                 PMD_DRV_LOG(WARNING,
10007                             "i40e device %s changed global register [0x%08x]."
10008                             " original: 0x%08x, new: 0x%08x",
10009                             dev->device->name, addr, reg,
10010                             (uint32_t)i40e_read_rx_ctl(hw, addr));
10011         }
10012 }
10013
10014 static void
10015 i40e_filter_input_set_init(struct i40e_pf *pf)
10016 {
10017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10018         enum i40e_filter_pctype pctype;
10019         uint64_t input_set, inset_reg;
10020         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10021         int num, i;
10022         uint16_t flow_type;
10023
10024         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
10025              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
10026                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
10027
10028                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
10029                         continue;
10030
10031                 input_set = i40e_get_default_input_set(pctype);
10032
10033                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10034                                                    I40E_INSET_MASK_NUM_REG);
10035                 if (num < 0)
10036                         return;
10037                 if (pf->support_multi_driver && num > 0) {
10038                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10039                         return;
10040                 }
10041                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
10042                                         input_set);
10043
10044                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10045                                       (uint32_t)(inset_reg & UINT32_MAX));
10046                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10047                                      (uint32_t)((inset_reg >>
10048                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
10049                 if (!pf->support_multi_driver) {
10050                         i40e_check_write_global_reg(hw,
10051                                             I40E_GLQF_HASH_INSET(0, pctype),
10052                                             (uint32_t)(inset_reg & UINT32_MAX));
10053                         i40e_check_write_global_reg(hw,
10054                                              I40E_GLQF_HASH_INSET(1, pctype),
10055                                              (uint32_t)((inset_reg >>
10056                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
10057
10058                         for (i = 0; i < num; i++) {
10059                                 i40e_check_write_global_reg(hw,
10060                                                     I40E_GLQF_FD_MSK(i, pctype),
10061                                                     mask_reg[i]);
10062                                 i40e_check_write_global_reg(hw,
10063                                                   I40E_GLQF_HASH_MSK(i, pctype),
10064                                                   mask_reg[i]);
10065                         }
10066                         /*clear unused mask registers of the pctype */
10067                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10068                                 i40e_check_write_global_reg(hw,
10069                                                     I40E_GLQF_FD_MSK(i, pctype),
10070                                                     0);
10071                                 i40e_check_write_global_reg(hw,
10072                                                   I40E_GLQF_HASH_MSK(i, pctype),
10073                                                   0);
10074                         }
10075                 } else {
10076                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10077                 }
10078                 I40E_WRITE_FLUSH(hw);
10079
10080                 /* store the default input set */
10081                 if (!pf->support_multi_driver)
10082                         pf->hash_input_set[pctype] = input_set;
10083                 pf->fdir.input_set[pctype] = input_set;
10084         }
10085 }
10086
10087 int
10088 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10089                          struct rte_eth_input_set_conf *conf)
10090 {
10091         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10092         enum i40e_filter_pctype pctype;
10093         uint64_t input_set, inset_reg = 0;
10094         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10095         int ret, i, num;
10096
10097         if (!conf) {
10098                 PMD_DRV_LOG(ERR, "Invalid pointer");
10099                 return -EFAULT;
10100         }
10101         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10102             conf->op != RTE_ETH_INPUT_SET_ADD) {
10103                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10104                 return -EINVAL;
10105         }
10106
10107         if (pf->support_multi_driver) {
10108                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10109                 return -ENOTSUP;
10110         }
10111
10112         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10113         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10114                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10115                 return -EINVAL;
10116         }
10117
10118         if (hw->mac.type == I40E_MAC_X722) {
10119                 /* get translated pctype value in fd pctype register */
10120                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10121                         I40E_GLQF_FD_PCTYPES((int)pctype));
10122         }
10123
10124         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10125                                    conf->inset_size);
10126         if (ret) {
10127                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10128                 return -EINVAL;
10129         }
10130
10131         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10132                 /* get inset value in register */
10133                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10134                 inset_reg <<= I40E_32_BIT_WIDTH;
10135                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10136                 input_set |= pf->hash_input_set[pctype];
10137         }
10138         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10139                                            I40E_INSET_MASK_NUM_REG);
10140         if (num < 0)
10141                 return -EINVAL;
10142
10143         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10144
10145         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10146                                     (uint32_t)(inset_reg & UINT32_MAX));
10147         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10148                                     (uint32_t)((inset_reg >>
10149                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10150
10151         for (i = 0; i < num; i++)
10152                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10153                                             mask_reg[i]);
10154         /*clear unused mask registers of the pctype */
10155         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10156                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10157                                             0);
10158         I40E_WRITE_FLUSH(hw);
10159
10160         pf->hash_input_set[pctype] = input_set;
10161         return 0;
10162 }
10163
10164 int
10165 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10166                          struct rte_eth_input_set_conf *conf)
10167 {
10168         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10169         enum i40e_filter_pctype pctype;
10170         uint64_t input_set, inset_reg = 0;
10171         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10172         int ret, i, num;
10173
10174         if (!hw || !conf) {
10175                 PMD_DRV_LOG(ERR, "Invalid pointer");
10176                 return -EFAULT;
10177         }
10178         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10179             conf->op != RTE_ETH_INPUT_SET_ADD) {
10180                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10181                 return -EINVAL;
10182         }
10183
10184         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10185
10186         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10187                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10188                 return -EINVAL;
10189         }
10190
10191         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10192                                    conf->inset_size);
10193         if (ret) {
10194                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10195                 return -EINVAL;
10196         }
10197
10198         /* get inset value in register */
10199         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10200         inset_reg <<= I40E_32_BIT_WIDTH;
10201         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10202
10203         /* Can not change the inset reg for flex payload for fdir,
10204          * it is done by writing I40E_PRTQF_FD_FLXINSET
10205          * in i40e_set_flex_mask_on_pctype.
10206          */
10207         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10208                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10209         else
10210                 input_set |= pf->fdir.input_set[pctype];
10211         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10212                                            I40E_INSET_MASK_NUM_REG);
10213         if (num < 0)
10214                 return -EINVAL;
10215         if (pf->support_multi_driver && num > 0) {
10216                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10217                 return -ENOTSUP;
10218         }
10219
10220         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10221
10222         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10223                               (uint32_t)(inset_reg & UINT32_MAX));
10224         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10225                              (uint32_t)((inset_reg >>
10226                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10227
10228         if (!pf->support_multi_driver) {
10229                 for (i = 0; i < num; i++)
10230                         i40e_check_write_global_reg(hw,
10231                                                     I40E_GLQF_FD_MSK(i, pctype),
10232                                                     mask_reg[i]);
10233                 /*clear unused mask registers of the pctype */
10234                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10235                         i40e_check_write_global_reg(hw,
10236                                                     I40E_GLQF_FD_MSK(i, pctype),
10237                                                     0);
10238         } else {
10239                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10240         }
10241         I40E_WRITE_FLUSH(hw);
10242
10243         pf->fdir.input_set[pctype] = input_set;
10244         return 0;
10245 }
10246
10247 static int
10248 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10249 {
10250         int ret = 0;
10251
10252         if (!hw || !info) {
10253                 PMD_DRV_LOG(ERR, "Invalid pointer");
10254                 return -EFAULT;
10255         }
10256
10257         switch (info->info_type) {
10258         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10259                 i40e_get_symmetric_hash_enable_per_port(hw,
10260                                         &(info->info.enable));
10261                 break;
10262         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10263                 ret = i40e_get_hash_filter_global_config(hw,
10264                                 &(info->info.global_conf));
10265                 break;
10266         default:
10267                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10268                                                         info->info_type);
10269                 ret = -EINVAL;
10270                 break;
10271         }
10272
10273         return ret;
10274 }
10275
10276 static int
10277 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10278 {
10279         int ret = 0;
10280
10281         if (!hw || !info) {
10282                 PMD_DRV_LOG(ERR, "Invalid pointer");
10283                 return -EFAULT;
10284         }
10285
10286         switch (info->info_type) {
10287         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10288                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10289                 break;
10290         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10291                 ret = i40e_set_hash_filter_global_config(hw,
10292                                 &(info->info.global_conf));
10293                 break;
10294         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10295                 ret = i40e_hash_filter_inset_select(hw,
10296                                                &(info->info.input_set_conf));
10297                 break;
10298
10299         default:
10300                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10301                                                         info->info_type);
10302                 ret = -EINVAL;
10303                 break;
10304         }
10305
10306         return ret;
10307 }
10308
10309 /* Operations for hash function */
10310 static int
10311 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10312                       enum rte_filter_op filter_op,
10313                       void *arg)
10314 {
10315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10316         int ret = 0;
10317
10318         switch (filter_op) {
10319         case RTE_ETH_FILTER_NOP:
10320                 break;
10321         case RTE_ETH_FILTER_GET:
10322                 ret = i40e_hash_filter_get(hw,
10323                         (struct rte_eth_hash_filter_info *)arg);
10324                 break;
10325         case RTE_ETH_FILTER_SET:
10326                 ret = i40e_hash_filter_set(hw,
10327                         (struct rte_eth_hash_filter_info *)arg);
10328                 break;
10329         default:
10330                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10331                                                                 filter_op);
10332                 ret = -ENOTSUP;
10333                 break;
10334         }
10335
10336         return ret;
10337 }
10338
10339 /* Convert ethertype filter structure */
10340 static int
10341 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10342                               struct i40e_ethertype_filter *filter)
10343 {
10344         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10345                 RTE_ETHER_ADDR_LEN);
10346         filter->input.ether_type = input->ether_type;
10347         filter->flags = input->flags;
10348         filter->queue = input->queue;
10349
10350         return 0;
10351 }
10352
10353 /* Check if there exists the ehtertype filter */
10354 struct i40e_ethertype_filter *
10355 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10356                                 const struct i40e_ethertype_filter_input *input)
10357 {
10358         int ret;
10359
10360         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10361         if (ret < 0)
10362                 return NULL;
10363
10364         return ethertype_rule->hash_map[ret];
10365 }
10366
10367 /* Add ethertype filter in SW list */
10368 static int
10369 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10370                                 struct i40e_ethertype_filter *filter)
10371 {
10372         struct i40e_ethertype_rule *rule = &pf->ethertype;
10373         int ret;
10374
10375         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10376         if (ret < 0) {
10377                 PMD_DRV_LOG(ERR,
10378                             "Failed to insert ethertype filter"
10379                             " to hash table %d!",
10380                             ret);
10381                 return ret;
10382         }
10383         rule->hash_map[ret] = filter;
10384
10385         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10386
10387         return 0;
10388 }
10389
10390 /* Delete ethertype filter in SW list */
10391 int
10392 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10393                              struct i40e_ethertype_filter_input *input)
10394 {
10395         struct i40e_ethertype_rule *rule = &pf->ethertype;
10396         struct i40e_ethertype_filter *filter;
10397         int ret;
10398
10399         ret = rte_hash_del_key(rule->hash_table, input);
10400         if (ret < 0) {
10401                 PMD_DRV_LOG(ERR,
10402                             "Failed to delete ethertype filter"
10403                             " to hash table %d!",
10404                             ret);
10405                 return ret;
10406         }
10407         filter = rule->hash_map[ret];
10408         rule->hash_map[ret] = NULL;
10409
10410         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10411         rte_free(filter);
10412
10413         return 0;
10414 }
10415
10416 /*
10417  * Configure ethertype filter, which can director packet by filtering
10418  * with mac address and ether_type or only ether_type
10419  */
10420 int
10421 i40e_ethertype_filter_set(struct i40e_pf *pf,
10422                         struct rte_eth_ethertype_filter *filter,
10423                         bool add)
10424 {
10425         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10426         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10427         struct i40e_ethertype_filter *ethertype_filter, *node;
10428         struct i40e_ethertype_filter check_filter;
10429         struct i40e_control_filter_stats stats;
10430         uint16_t flags = 0;
10431         int ret;
10432
10433         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10434                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10435                 return -EINVAL;
10436         }
10437         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10438                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10439                 PMD_DRV_LOG(ERR,
10440                         "unsupported ether_type(0x%04x) in control packet filter.",
10441                         filter->ether_type);
10442                 return -EINVAL;
10443         }
10444         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10445                 PMD_DRV_LOG(WARNING,
10446                         "filter vlan ether_type in first tag is not supported.");
10447
10448         /* Check if there is the filter in SW list */
10449         memset(&check_filter, 0, sizeof(check_filter));
10450         i40e_ethertype_filter_convert(filter, &check_filter);
10451         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10452                                                &check_filter.input);
10453         if (add && node) {
10454                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10455                 return -EINVAL;
10456         }
10457
10458         if (!add && !node) {
10459                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10460                 return -EINVAL;
10461         }
10462
10463         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10464                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10465         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10466                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10467         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10468
10469         memset(&stats, 0, sizeof(stats));
10470         ret = i40e_aq_add_rem_control_packet_filter(hw,
10471                         filter->mac_addr.addr_bytes,
10472                         filter->ether_type, flags,
10473                         pf->main_vsi->seid,
10474                         filter->queue, add, &stats, NULL);
10475
10476         PMD_DRV_LOG(INFO,
10477                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10478                 ret, stats.mac_etype_used, stats.etype_used,
10479                 stats.mac_etype_free, stats.etype_free);
10480         if (ret < 0)
10481                 return -ENOSYS;
10482
10483         /* Add or delete a filter in SW list */
10484         if (add) {
10485                 ethertype_filter = rte_zmalloc("ethertype_filter",
10486                                        sizeof(*ethertype_filter), 0);
10487                 if (ethertype_filter == NULL) {
10488                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10489                         return -ENOMEM;
10490                 }
10491
10492                 rte_memcpy(ethertype_filter, &check_filter,
10493                            sizeof(check_filter));
10494                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10495                 if (ret < 0)
10496                         rte_free(ethertype_filter);
10497         } else {
10498                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10499         }
10500
10501         return ret;
10502 }
10503
10504 /*
10505  * Handle operations for ethertype filter.
10506  */
10507 static int
10508 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10509                                 enum rte_filter_op filter_op,
10510                                 void *arg)
10511 {
10512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10513         int ret = 0;
10514
10515         if (filter_op == RTE_ETH_FILTER_NOP)
10516                 return ret;
10517
10518         if (arg == NULL) {
10519                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10520                             filter_op);
10521                 return -EINVAL;
10522         }
10523
10524         switch (filter_op) {
10525         case RTE_ETH_FILTER_ADD:
10526                 ret = i40e_ethertype_filter_set(pf,
10527                         (struct rte_eth_ethertype_filter *)arg,
10528                         TRUE);
10529                 break;
10530         case RTE_ETH_FILTER_DELETE:
10531                 ret = i40e_ethertype_filter_set(pf,
10532                         (struct rte_eth_ethertype_filter *)arg,
10533                         FALSE);
10534                 break;
10535         default:
10536                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10537                 ret = -ENOSYS;
10538                 break;
10539         }
10540         return ret;
10541 }
10542
10543 static int
10544 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10545                      enum rte_filter_type filter_type,
10546                      enum rte_filter_op filter_op,
10547                      void *arg)
10548 {
10549         int ret = 0;
10550
10551         if (dev == NULL)
10552                 return -EINVAL;
10553
10554         switch (filter_type) {
10555         case RTE_ETH_FILTER_NONE:
10556                 /* For global configuration */
10557                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10558                 break;
10559         case RTE_ETH_FILTER_HASH:
10560                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10561                 break;
10562         case RTE_ETH_FILTER_MACVLAN:
10563                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10564                 break;
10565         case RTE_ETH_FILTER_ETHERTYPE:
10566                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10567                 break;
10568         case RTE_ETH_FILTER_TUNNEL:
10569                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10570                 break;
10571         case RTE_ETH_FILTER_FDIR:
10572                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10573                 break;
10574         case RTE_ETH_FILTER_GENERIC:
10575                 if (filter_op != RTE_ETH_FILTER_GET)
10576                         return -EINVAL;
10577                 *(const void **)arg = &i40e_flow_ops;
10578                 break;
10579         default:
10580                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10581                                                         filter_type);
10582                 ret = -EINVAL;
10583                 break;
10584         }
10585
10586         return ret;
10587 }
10588
10589 /*
10590  * Check and enable Extended Tag.
10591  * Enabling Extended Tag is important for 40G performance.
10592  */
10593 static void
10594 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10595 {
10596         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10597         uint32_t buf = 0;
10598         int ret;
10599
10600         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10601                                       PCI_DEV_CAP_REG);
10602         if (ret < 0) {
10603                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10604                             PCI_DEV_CAP_REG);
10605                 return;
10606         }
10607         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10608                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10609                 return;
10610         }
10611
10612         buf = 0;
10613         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10614                                       PCI_DEV_CTRL_REG);
10615         if (ret < 0) {
10616                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10617                             PCI_DEV_CTRL_REG);
10618                 return;
10619         }
10620         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10621                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10622                 return;
10623         }
10624         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10625         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10626                                        PCI_DEV_CTRL_REG);
10627         if (ret < 0) {
10628                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10629                             PCI_DEV_CTRL_REG);
10630                 return;
10631         }
10632 }
10633
10634 /*
10635  * As some registers wouldn't be reset unless a global hardware reset,
10636  * hardware initialization is needed to put those registers into an
10637  * expected initial state.
10638  */
10639 static void
10640 i40e_hw_init(struct rte_eth_dev *dev)
10641 {
10642         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10643
10644         i40e_enable_extended_tag(dev);
10645
10646         /* clear the PF Queue Filter control register */
10647         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10648
10649         /* Disable symmetric hash per port */
10650         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10651 }
10652
10653 /*
10654  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10655  * however this function will return only one highest pctype index,
10656  * which is not quite correct. This is known problem of i40e driver
10657  * and needs to be fixed later.
10658  */
10659 enum i40e_filter_pctype
10660 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10661 {
10662         int i;
10663         uint64_t pctype_mask;
10664
10665         if (flow_type < I40E_FLOW_TYPE_MAX) {
10666                 pctype_mask = adapter->pctypes_tbl[flow_type];
10667                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10668                         if (pctype_mask & (1ULL << i))
10669                                 return (enum i40e_filter_pctype)i;
10670                 }
10671         }
10672         return I40E_FILTER_PCTYPE_INVALID;
10673 }
10674
10675 uint16_t
10676 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10677                         enum i40e_filter_pctype pctype)
10678 {
10679         uint16_t flowtype;
10680         uint64_t pctype_mask = 1ULL << pctype;
10681
10682         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10683              flowtype++) {
10684                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10685                         return flowtype;
10686         }
10687
10688         return RTE_ETH_FLOW_UNKNOWN;
10689 }
10690
10691 /*
10692  * On X710, performance number is far from the expectation on recent firmware
10693  * versions; on XL710, performance number is also far from the expectation on
10694  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10695  * mode is enabled and port MAC address is equal to the packet destination MAC
10696  * address. The fix for this issue may not be integrated in the following
10697  * firmware version. So the workaround in software driver is needed. It needs
10698  * to modify the initial values of 3 internal only registers for both X710 and
10699  * XL710. Note that the values for X710 or XL710 could be different, and the
10700  * workaround can be removed when it is fixed in firmware in the future.
10701  */
10702
10703 /* For both X710 and XL710 */
10704 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10705 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10706 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10707
10708 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10709 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10710
10711 /* For X722 */
10712 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10713 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10714
10715 /* For X710 */
10716 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10717 /* For XL710 */
10718 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10719 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10720
10721 /*
10722  * GL_SWR_PM_UP_THR:
10723  * The value is not impacted from the link speed, its value is set according
10724  * to the total number of ports for a better pipe-monitor configuration.
10725  */
10726 static bool
10727 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10728 {
10729 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10730                 .device_id = (dev),   \
10731                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10732
10733 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10734                 .device_id = (dev),   \
10735                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10736
10737         static const struct {
10738                 uint16_t device_id;
10739                 uint32_t val;
10740         } swr_pm_table[] = {
10741                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10742                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10743                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10744                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10745                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10746
10747                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10748                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10749                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10750                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10751                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10752                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10753                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10754         };
10755         uint32_t i;
10756
10757         if (value == NULL) {
10758                 PMD_DRV_LOG(ERR, "value is NULL");
10759                 return false;
10760         }
10761
10762         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10763                 if (hw->device_id == swr_pm_table[i].device_id) {
10764                         *value = swr_pm_table[i].val;
10765
10766                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10767                                     "value - 0x%08x",
10768                                     hw->device_id, *value);
10769                         return true;
10770                 }
10771         }
10772
10773         return false;
10774 }
10775
10776 static int
10777 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10778 {
10779         enum i40e_status_code status;
10780         struct i40e_aq_get_phy_abilities_resp phy_ab;
10781         int ret = -ENOTSUP;
10782         int retries = 0;
10783
10784         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10785                                               NULL);
10786
10787         while (status) {
10788                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10789                         status);
10790                 retries++;
10791                 rte_delay_us(100000);
10792                 if  (retries < 5)
10793                         status = i40e_aq_get_phy_capabilities(hw, false,
10794                                         true, &phy_ab, NULL);
10795                 else
10796                         return ret;
10797         }
10798         return 0;
10799 }
10800
10801 static void
10802 i40e_configure_registers(struct i40e_hw *hw)
10803 {
10804         static struct {
10805                 uint32_t addr;
10806                 uint64_t val;
10807         } reg_table[] = {
10808                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10809                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10810                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10811         };
10812         uint64_t reg;
10813         uint32_t i;
10814         int ret;
10815
10816         for (i = 0; i < RTE_DIM(reg_table); i++) {
10817                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10818                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10819                                 reg_table[i].val =
10820                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10821                         else /* For X710/XL710/XXV710 */
10822                                 if (hw->aq.fw_maj_ver < 6)
10823                                         reg_table[i].val =
10824                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10825                                 else
10826                                         reg_table[i].val =
10827                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10828                 }
10829
10830                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10831                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10832                                 reg_table[i].val =
10833                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10834                         else /* For X710/XL710/XXV710 */
10835                                 reg_table[i].val =
10836                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10837                 }
10838
10839                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10840                         uint32_t cfg_val;
10841
10842                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10843                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10844                                             "GL_SWR_PM_UP_THR value fixup",
10845                                             hw->device_id);
10846                                 continue;
10847                         }
10848
10849                         reg_table[i].val = cfg_val;
10850                 }
10851
10852                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10853                                                         &reg, NULL);
10854                 if (ret < 0) {
10855                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10856                                                         reg_table[i].addr);
10857                         break;
10858                 }
10859                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10860                                                 reg_table[i].addr, reg);
10861                 if (reg == reg_table[i].val)
10862                         continue;
10863
10864                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10865                                                 reg_table[i].val, NULL);
10866                 if (ret < 0) {
10867                         PMD_DRV_LOG(ERR,
10868                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10869                                 reg_table[i].val, reg_table[i].addr);
10870                         break;
10871                 }
10872                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10873                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10874         }
10875 }
10876
10877 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10878 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10879 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10880 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10881 static int
10882 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10883 {
10884         uint32_t reg;
10885         int ret;
10886
10887         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10888                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10889                 return -EINVAL;
10890         }
10891
10892         /* Configure for double VLAN RX stripping */
10893         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10894         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10895                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10896                 ret = i40e_aq_debug_write_register(hw,
10897                                                    I40E_VSI_TSR(vsi->vsi_id),
10898                                                    reg, NULL);
10899                 if (ret < 0) {
10900                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10901                                     vsi->vsi_id);
10902                         return I40E_ERR_CONFIG;
10903                 }
10904         }
10905
10906         /* Configure for double VLAN TX insertion */
10907         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10908         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10909                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10910                 ret = i40e_aq_debug_write_register(hw,
10911                                                    I40E_VSI_L2TAGSTXVALID(
10912                                                    vsi->vsi_id), reg, NULL);
10913                 if (ret < 0) {
10914                         PMD_DRV_LOG(ERR,
10915                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10916                                 vsi->vsi_id);
10917                         return I40E_ERR_CONFIG;
10918                 }
10919         }
10920
10921         return 0;
10922 }
10923
10924 /**
10925  * i40e_aq_add_mirror_rule
10926  * @hw: pointer to the hardware structure
10927  * @seid: VEB seid to add mirror rule to
10928  * @dst_id: destination vsi seid
10929  * @entries: Buffer which contains the entities to be mirrored
10930  * @count: number of entities contained in the buffer
10931  * @rule_id:the rule_id of the rule to be added
10932  *
10933  * Add a mirror rule for a given veb.
10934  *
10935  **/
10936 static enum i40e_status_code
10937 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10938                         uint16_t seid, uint16_t dst_id,
10939                         uint16_t rule_type, uint16_t *entries,
10940                         uint16_t count, uint16_t *rule_id)
10941 {
10942         struct i40e_aq_desc desc;
10943         struct i40e_aqc_add_delete_mirror_rule cmd;
10944         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10945                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10946                 &desc.params.raw;
10947         uint16_t buff_len;
10948         enum i40e_status_code status;
10949
10950         i40e_fill_default_direct_cmd_desc(&desc,
10951                                           i40e_aqc_opc_add_mirror_rule);
10952         memset(&cmd, 0, sizeof(cmd));
10953
10954         buff_len = sizeof(uint16_t) * count;
10955         desc.datalen = rte_cpu_to_le_16(buff_len);
10956         if (buff_len > 0)
10957                 desc.flags |= rte_cpu_to_le_16(
10958                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10959         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10960                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10961         cmd.num_entries = rte_cpu_to_le_16(count);
10962         cmd.seid = rte_cpu_to_le_16(seid);
10963         cmd.destination = rte_cpu_to_le_16(dst_id);
10964
10965         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10966         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10967         PMD_DRV_LOG(INFO,
10968                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10969                 hw->aq.asq_last_status, resp->rule_id,
10970                 resp->mirror_rules_used, resp->mirror_rules_free);
10971         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10972
10973         return status;
10974 }
10975
10976 /**
10977  * i40e_aq_del_mirror_rule
10978  * @hw: pointer to the hardware structure
10979  * @seid: VEB seid to add mirror rule to
10980  * @entries: Buffer which contains the entities to be mirrored
10981  * @count: number of entities contained in the buffer
10982  * @rule_id:the rule_id of the rule to be delete
10983  *
10984  * Delete a mirror rule for a given veb.
10985  *
10986  **/
10987 static enum i40e_status_code
10988 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10989                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10990                 uint16_t count, uint16_t rule_id)
10991 {
10992         struct i40e_aq_desc desc;
10993         struct i40e_aqc_add_delete_mirror_rule cmd;
10994         uint16_t buff_len = 0;
10995         enum i40e_status_code status;
10996         void *buff = NULL;
10997
10998         i40e_fill_default_direct_cmd_desc(&desc,
10999                                           i40e_aqc_opc_delete_mirror_rule);
11000         memset(&cmd, 0, sizeof(cmd));
11001         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
11002                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
11003                                                           I40E_AQ_FLAG_RD));
11004                 cmd.num_entries = count;
11005                 buff_len = sizeof(uint16_t) * count;
11006                 desc.datalen = rte_cpu_to_le_16(buff_len);
11007                 buff = (void *)entries;
11008         } else
11009                 /* rule id is filled in destination field for deleting mirror rule */
11010                 cmd.destination = rte_cpu_to_le_16(rule_id);
11011
11012         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
11013                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
11014         cmd.seid = rte_cpu_to_le_16(seid);
11015
11016         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
11017         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
11018
11019         return status;
11020 }
11021
11022 /**
11023  * i40e_mirror_rule_set
11024  * @dev: pointer to the hardware structure
11025  * @mirror_conf: mirror rule info
11026  * @sw_id: mirror rule's sw_id
11027  * @on: enable/disable
11028  *
11029  * set a mirror rule.
11030  *
11031  **/
11032 static int
11033 i40e_mirror_rule_set(struct rte_eth_dev *dev,
11034                         struct rte_eth_mirror_conf *mirror_conf,
11035                         uint8_t sw_id, uint8_t on)
11036 {
11037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11039         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11040         struct i40e_mirror_rule *parent = NULL;
11041         uint16_t seid, dst_seid, rule_id;
11042         uint16_t i, j = 0;
11043         int ret;
11044
11045         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
11046
11047         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
11048                 PMD_DRV_LOG(ERR,
11049                         "mirror rule can not be configured without veb or vfs.");
11050                 return -ENOSYS;
11051         }
11052         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
11053                 PMD_DRV_LOG(ERR, "mirror table is full.");
11054                 return -ENOSPC;
11055         }
11056         if (mirror_conf->dst_pool > pf->vf_num) {
11057                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11058                                  mirror_conf->dst_pool);
11059                 return -EINVAL;
11060         }
11061
11062         seid = pf->main_vsi->veb->seid;
11063
11064         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11065                 if (sw_id <= it->index) {
11066                         mirr_rule = it;
11067                         break;
11068                 }
11069                 parent = it;
11070         }
11071         if (mirr_rule && sw_id == mirr_rule->index) {
11072                 if (on) {
11073                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11074                         return -EEXIST;
11075                 } else {
11076                         ret = i40e_aq_del_mirror_rule(hw, seid,
11077                                         mirr_rule->rule_type,
11078                                         mirr_rule->entries,
11079                                         mirr_rule->num_entries, mirr_rule->id);
11080                         if (ret < 0) {
11081                                 PMD_DRV_LOG(ERR,
11082                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11083                                         ret, hw->aq.asq_last_status);
11084                                 return -ENOSYS;
11085                         }
11086                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11087                         rte_free(mirr_rule);
11088                         pf->nb_mirror_rule--;
11089                         return 0;
11090                 }
11091         } else if (!on) {
11092                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11093                 return -ENOENT;
11094         }
11095
11096         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11097                                 sizeof(struct i40e_mirror_rule) , 0);
11098         if (!mirr_rule) {
11099                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11100                 return I40E_ERR_NO_MEMORY;
11101         }
11102         switch (mirror_conf->rule_type) {
11103         case ETH_MIRROR_VLAN:
11104                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11105                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11106                                 mirr_rule->entries[j] =
11107                                         mirror_conf->vlan.vlan_id[i];
11108                                 j++;
11109                         }
11110                 }
11111                 if (j == 0) {
11112                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11113                         rte_free(mirr_rule);
11114                         return -EINVAL;
11115                 }
11116                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11117                 break;
11118         case ETH_MIRROR_VIRTUAL_POOL_UP:
11119         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11120                 /* check if the specified pool bit is out of range */
11121                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11122                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11123                         rte_free(mirr_rule);
11124                         return -EINVAL;
11125                 }
11126                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11127                         if (mirror_conf->pool_mask & (1ULL << i)) {
11128                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11129                                 j++;
11130                         }
11131                 }
11132                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11133                         /* add pf vsi to entries */
11134                         mirr_rule->entries[j] = pf->main_vsi_seid;
11135                         j++;
11136                 }
11137                 if (j == 0) {
11138                         PMD_DRV_LOG(ERR, "pool is not specified.");
11139                         rte_free(mirr_rule);
11140                         return -EINVAL;
11141                 }
11142                 /* egress and ingress in aq commands means from switch but not port */
11143                 mirr_rule->rule_type =
11144                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11145                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11146                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11147                 break;
11148         case ETH_MIRROR_UPLINK_PORT:
11149                 /* egress and ingress in aq commands means from switch but not port*/
11150                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11151                 break;
11152         case ETH_MIRROR_DOWNLINK_PORT:
11153                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11154                 break;
11155         default:
11156                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11157                         mirror_conf->rule_type);
11158                 rte_free(mirr_rule);
11159                 return -EINVAL;
11160         }
11161
11162         /* If the dst_pool is equal to vf_num, consider it as PF */
11163         if (mirror_conf->dst_pool == pf->vf_num)
11164                 dst_seid = pf->main_vsi_seid;
11165         else
11166                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11167
11168         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11169                                       mirr_rule->rule_type, mirr_rule->entries,
11170                                       j, &rule_id);
11171         if (ret < 0) {
11172                 PMD_DRV_LOG(ERR,
11173                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11174                         ret, hw->aq.asq_last_status);
11175                 rte_free(mirr_rule);
11176                 return -ENOSYS;
11177         }
11178
11179         mirr_rule->index = sw_id;
11180         mirr_rule->num_entries = j;
11181         mirr_rule->id = rule_id;
11182         mirr_rule->dst_vsi_seid = dst_seid;
11183
11184         if (parent)
11185                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11186         else
11187                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11188
11189         pf->nb_mirror_rule++;
11190         return 0;
11191 }
11192
11193 /**
11194  * i40e_mirror_rule_reset
11195  * @dev: pointer to the device
11196  * @sw_id: mirror rule's sw_id
11197  *
11198  * reset a mirror rule.
11199  *
11200  **/
11201 static int
11202 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11203 {
11204         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11205         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11206         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11207         uint16_t seid;
11208         int ret;
11209
11210         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11211
11212         seid = pf->main_vsi->veb->seid;
11213
11214         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11215                 if (sw_id == it->index) {
11216                         mirr_rule = it;
11217                         break;
11218                 }
11219         }
11220         if (mirr_rule) {
11221                 ret = i40e_aq_del_mirror_rule(hw, seid,
11222                                 mirr_rule->rule_type,
11223                                 mirr_rule->entries,
11224                                 mirr_rule->num_entries, mirr_rule->id);
11225                 if (ret < 0) {
11226                         PMD_DRV_LOG(ERR,
11227                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11228                                 ret, hw->aq.asq_last_status);
11229                         return -ENOSYS;
11230                 }
11231                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11232                 rte_free(mirr_rule);
11233                 pf->nb_mirror_rule--;
11234         } else {
11235                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11236                 return -ENOENT;
11237         }
11238         return 0;
11239 }
11240
11241 static uint64_t
11242 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11243 {
11244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11245         uint64_t systim_cycles;
11246
11247         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11248         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11249                         << 32;
11250
11251         return systim_cycles;
11252 }
11253
11254 static uint64_t
11255 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11256 {
11257         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11258         uint64_t rx_tstamp;
11259
11260         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11261         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11262                         << 32;
11263
11264         return rx_tstamp;
11265 }
11266
11267 static uint64_t
11268 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11269 {
11270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11271         uint64_t tx_tstamp;
11272
11273         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11274         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11275                         << 32;
11276
11277         return tx_tstamp;
11278 }
11279
11280 static void
11281 i40e_start_timecounters(struct rte_eth_dev *dev)
11282 {
11283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11284         struct i40e_adapter *adapter = dev->data->dev_private;
11285         struct rte_eth_link link;
11286         uint32_t tsync_inc_l;
11287         uint32_t tsync_inc_h;
11288
11289         /* Get current link speed. */
11290         i40e_dev_link_update(dev, 1);
11291         rte_eth_linkstatus_get(dev, &link);
11292
11293         switch (link.link_speed) {
11294         case ETH_SPEED_NUM_40G:
11295         case ETH_SPEED_NUM_25G:
11296                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11297                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11298                 break;
11299         case ETH_SPEED_NUM_10G:
11300                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11301                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11302                 break;
11303         case ETH_SPEED_NUM_1G:
11304                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11305                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11306                 break;
11307         default:
11308                 tsync_inc_l = 0x0;
11309                 tsync_inc_h = 0x0;
11310         }
11311
11312         /* Set the timesync increment value. */
11313         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11314         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11315
11316         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11317         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11318         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11319
11320         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11321         adapter->systime_tc.cc_shift = 0;
11322         adapter->systime_tc.nsec_mask = 0;
11323
11324         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11325         adapter->rx_tstamp_tc.cc_shift = 0;
11326         adapter->rx_tstamp_tc.nsec_mask = 0;
11327
11328         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11329         adapter->tx_tstamp_tc.cc_shift = 0;
11330         adapter->tx_tstamp_tc.nsec_mask = 0;
11331 }
11332
11333 static int
11334 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11335 {
11336         struct i40e_adapter *adapter = dev->data->dev_private;
11337
11338         adapter->systime_tc.nsec += delta;
11339         adapter->rx_tstamp_tc.nsec += delta;
11340         adapter->tx_tstamp_tc.nsec += delta;
11341
11342         return 0;
11343 }
11344
11345 static int
11346 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11347 {
11348         uint64_t ns;
11349         struct i40e_adapter *adapter = dev->data->dev_private;
11350
11351         ns = rte_timespec_to_ns(ts);
11352
11353         /* Set the timecounters to a new value. */
11354         adapter->systime_tc.nsec = ns;
11355         adapter->rx_tstamp_tc.nsec = ns;
11356         adapter->tx_tstamp_tc.nsec = ns;
11357
11358         return 0;
11359 }
11360
11361 static int
11362 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11363 {
11364         uint64_t ns, systime_cycles;
11365         struct i40e_adapter *adapter = dev->data->dev_private;
11366
11367         systime_cycles = i40e_read_systime_cyclecounter(dev);
11368         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11369         *ts = rte_ns_to_timespec(ns);
11370
11371         return 0;
11372 }
11373
11374 static int
11375 i40e_timesync_enable(struct rte_eth_dev *dev)
11376 {
11377         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11378         uint32_t tsync_ctl_l;
11379         uint32_t tsync_ctl_h;
11380
11381         /* Stop the timesync system time. */
11382         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11383         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11384         /* Reset the timesync system time value. */
11385         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11386         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11387
11388         i40e_start_timecounters(dev);
11389
11390         /* Clear timesync registers. */
11391         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11392         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11393         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11394         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11395         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11396         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11397
11398         /* Enable timestamping of PTP packets. */
11399         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11400         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11401
11402         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11403         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11404         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11405
11406         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11407         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11408
11409         return 0;
11410 }
11411
11412 static int
11413 i40e_timesync_disable(struct rte_eth_dev *dev)
11414 {
11415         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11416         uint32_t tsync_ctl_l;
11417         uint32_t tsync_ctl_h;
11418
11419         /* Disable timestamping of transmitted PTP packets. */
11420         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11421         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11422
11423         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11424         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11425
11426         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11427         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11428
11429         /* Reset the timesync increment value. */
11430         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11431         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11432
11433         return 0;
11434 }
11435
11436 static int
11437 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11438                                 struct timespec *timestamp, uint32_t flags)
11439 {
11440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11441         struct i40e_adapter *adapter = dev->data->dev_private;
11442         uint32_t sync_status;
11443         uint32_t index = flags & 0x03;
11444         uint64_t rx_tstamp_cycles;
11445         uint64_t ns;
11446
11447         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11448         if ((sync_status & (1 << index)) == 0)
11449                 return -EINVAL;
11450
11451         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11452         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11453         *timestamp = rte_ns_to_timespec(ns);
11454
11455         return 0;
11456 }
11457
11458 static int
11459 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11460                                 struct timespec *timestamp)
11461 {
11462         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11463         struct i40e_adapter *adapter = dev->data->dev_private;
11464         uint32_t sync_status;
11465         uint64_t tx_tstamp_cycles;
11466         uint64_t ns;
11467
11468         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11469         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11470                 return -EINVAL;
11471
11472         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11473         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11474         *timestamp = rte_ns_to_timespec(ns);
11475
11476         return 0;
11477 }
11478
11479 /*
11480  * i40e_parse_dcb_configure - parse dcb configure from user
11481  * @dev: the device being configured
11482  * @dcb_cfg: pointer of the result of parse
11483  * @*tc_map: bit map of enabled traffic classes
11484  *
11485  * Returns 0 on success, negative value on failure
11486  */
11487 static int
11488 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11489                          struct i40e_dcbx_config *dcb_cfg,
11490                          uint8_t *tc_map)
11491 {
11492         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11493         uint8_t i, tc_bw, bw_lf;
11494
11495         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11496
11497         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11498         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11499                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11500                 return -EINVAL;
11501         }
11502
11503         /* assume each tc has the same bw */
11504         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11505         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11506                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11507         /* to ensure the sum of tcbw is equal to 100 */
11508         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11509         for (i = 0; i < bw_lf; i++)
11510                 dcb_cfg->etscfg.tcbwtable[i]++;
11511
11512         /* assume each tc has the same Transmission Selection Algorithm */
11513         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11514                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11515
11516         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11517                 dcb_cfg->etscfg.prioritytable[i] =
11518                                 dcb_rx_conf->dcb_tc[i];
11519
11520         /* FW needs one App to configure HW */
11521         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11522         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11523         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11524         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11525
11526         if (dcb_rx_conf->nb_tcs == 0)
11527                 *tc_map = 1; /* tc0 only */
11528         else
11529                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11530
11531         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11532                 dcb_cfg->pfc.willing = 0;
11533                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11534                 dcb_cfg->pfc.pfcenable = *tc_map;
11535         }
11536         return 0;
11537 }
11538
11539
11540 static enum i40e_status_code
11541 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11542                               struct i40e_aqc_vsi_properties_data *info,
11543                               uint8_t enabled_tcmap)
11544 {
11545         enum i40e_status_code ret;
11546         int i, total_tc = 0;
11547         uint16_t qpnum_per_tc, bsf, qp_idx;
11548         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11549         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11550         uint16_t used_queues;
11551
11552         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11553         if (ret != I40E_SUCCESS)
11554                 return ret;
11555
11556         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11557                 if (enabled_tcmap & (1 << i))
11558                         total_tc++;
11559         }
11560         if (total_tc == 0)
11561                 total_tc = 1;
11562         vsi->enabled_tc = enabled_tcmap;
11563
11564         /* different VSI has different queues assigned */
11565         if (vsi->type == I40E_VSI_MAIN)
11566                 used_queues = dev_data->nb_rx_queues -
11567                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11568         else if (vsi->type == I40E_VSI_VMDQ2)
11569                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11570         else {
11571                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11572                 return I40E_ERR_NO_AVAILABLE_VSI;
11573         }
11574
11575         qpnum_per_tc = used_queues / total_tc;
11576         /* Number of queues per enabled TC */
11577         if (qpnum_per_tc == 0) {
11578                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11579                 return I40E_ERR_INVALID_QP_ID;
11580         }
11581         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11582                                 I40E_MAX_Q_PER_TC);
11583         bsf = rte_bsf32(qpnum_per_tc);
11584
11585         /**
11586          * Configure TC and queue mapping parameters, for enabled TC,
11587          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11588          * default queue will serve it.
11589          */
11590         qp_idx = 0;
11591         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11592                 if (vsi->enabled_tc & (1 << i)) {
11593                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11594                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11595                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11596                         qp_idx += qpnum_per_tc;
11597                 } else
11598                         info->tc_mapping[i] = 0;
11599         }
11600
11601         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11602         if (vsi->type == I40E_VSI_SRIOV) {
11603                 info->mapping_flags |=
11604                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11605                 for (i = 0; i < vsi->nb_qps; i++)
11606                         info->queue_mapping[i] =
11607                                 rte_cpu_to_le_16(vsi->base_queue + i);
11608         } else {
11609                 info->mapping_flags |=
11610                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11611                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11612         }
11613         info->valid_sections |=
11614                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11615
11616         return I40E_SUCCESS;
11617 }
11618
11619 /*
11620  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11621  * @veb: VEB to be configured
11622  * @tc_map: enabled TC bitmap
11623  *
11624  * Returns 0 on success, negative value on failure
11625  */
11626 static enum i40e_status_code
11627 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11628 {
11629         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11630         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11631         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11632         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11633         enum i40e_status_code ret = I40E_SUCCESS;
11634         int i;
11635         uint32_t bw_max;
11636
11637         /* Check if enabled_tc is same as existing or new TCs */
11638         if (veb->enabled_tc == tc_map)
11639                 return ret;
11640
11641         /* configure tc bandwidth */
11642         memset(&veb_bw, 0, sizeof(veb_bw));
11643         veb_bw.tc_valid_bits = tc_map;
11644         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11645         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11646                 if (tc_map & BIT_ULL(i))
11647                         veb_bw.tc_bw_share_credits[i] = 1;
11648         }
11649         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11650                                                    &veb_bw, NULL);
11651         if (ret) {
11652                 PMD_INIT_LOG(ERR,
11653                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11654                         hw->aq.asq_last_status);
11655                 return ret;
11656         }
11657
11658         memset(&ets_query, 0, sizeof(ets_query));
11659         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11660                                                    &ets_query, NULL);
11661         if (ret != I40E_SUCCESS) {
11662                 PMD_DRV_LOG(ERR,
11663                         "Failed to get switch_comp ETS configuration %u",
11664                         hw->aq.asq_last_status);
11665                 return ret;
11666         }
11667         memset(&bw_query, 0, sizeof(bw_query));
11668         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11669                                                   &bw_query, NULL);
11670         if (ret != I40E_SUCCESS) {
11671                 PMD_DRV_LOG(ERR,
11672                         "Failed to get switch_comp bandwidth configuration %u",
11673                         hw->aq.asq_last_status);
11674                 return ret;
11675         }
11676
11677         /* store and print out BW info */
11678         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11679         veb->bw_info.bw_max = ets_query.tc_bw_max;
11680         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11681         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11682         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11683                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11684                      I40E_16_BIT_WIDTH);
11685         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11686                 veb->bw_info.bw_ets_share_credits[i] =
11687                                 bw_query.tc_bw_share_credits[i];
11688                 veb->bw_info.bw_ets_credits[i] =
11689                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11690                 /* 4 bits per TC, 4th bit is reserved */
11691                 veb->bw_info.bw_ets_max[i] =
11692                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11693                                   RTE_LEN2MASK(3, uint8_t));
11694                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11695                             veb->bw_info.bw_ets_share_credits[i]);
11696                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11697                             veb->bw_info.bw_ets_credits[i]);
11698                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11699                             veb->bw_info.bw_ets_max[i]);
11700         }
11701
11702         veb->enabled_tc = tc_map;
11703
11704         return ret;
11705 }
11706
11707
11708 /*
11709  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11710  * @vsi: VSI to be configured
11711  * @tc_map: enabled TC bitmap
11712  *
11713  * Returns 0 on success, negative value on failure
11714  */
11715 static enum i40e_status_code
11716 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11717 {
11718         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11719         struct i40e_vsi_context ctxt;
11720         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11721         enum i40e_status_code ret = I40E_SUCCESS;
11722         int i;
11723
11724         /* Check if enabled_tc is same as existing or new TCs */
11725         if (vsi->enabled_tc == tc_map)
11726                 return ret;
11727
11728         /* configure tc bandwidth */
11729         memset(&bw_data, 0, sizeof(bw_data));
11730         bw_data.tc_valid_bits = tc_map;
11731         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11732         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11733                 if (tc_map & BIT_ULL(i))
11734                         bw_data.tc_bw_credits[i] = 1;
11735         }
11736         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11737         if (ret) {
11738                 PMD_INIT_LOG(ERR,
11739                         "AQ command Config VSI BW allocation per TC failed = %d",
11740                         hw->aq.asq_last_status);
11741                 goto out;
11742         }
11743         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11744                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11745
11746         /* Update Queue Pairs Mapping for currently enabled UPs */
11747         ctxt.seid = vsi->seid;
11748         ctxt.pf_num = hw->pf_id;
11749         ctxt.vf_num = 0;
11750         ctxt.uplink_seid = vsi->uplink_seid;
11751         ctxt.info = vsi->info;
11752         i40e_get_cap(hw);
11753         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11754         if (ret)
11755                 goto out;
11756
11757         /* Update the VSI after updating the VSI queue-mapping information */
11758         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11759         if (ret) {
11760                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11761                         hw->aq.asq_last_status);
11762                 goto out;
11763         }
11764         /* update the local VSI info with updated queue map */
11765         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11766                                         sizeof(vsi->info.tc_mapping));
11767         rte_memcpy(&vsi->info.queue_mapping,
11768                         &ctxt.info.queue_mapping,
11769                 sizeof(vsi->info.queue_mapping));
11770         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11771         vsi->info.valid_sections = 0;
11772
11773         /* query and update current VSI BW information */
11774         ret = i40e_vsi_get_bw_config(vsi);
11775         if (ret) {
11776                 PMD_INIT_LOG(ERR,
11777                          "Failed updating vsi bw info, err %s aq_err %s",
11778                          i40e_stat_str(hw, ret),
11779                          i40e_aq_str(hw, hw->aq.asq_last_status));
11780                 goto out;
11781         }
11782
11783         vsi->enabled_tc = tc_map;
11784
11785 out:
11786         return ret;
11787 }
11788
11789 /*
11790  * i40e_dcb_hw_configure - program the dcb setting to hw
11791  * @pf: pf the configuration is taken on
11792  * @new_cfg: new configuration
11793  * @tc_map: enabled TC bitmap
11794  *
11795  * Returns 0 on success, negative value on failure
11796  */
11797 static enum i40e_status_code
11798 i40e_dcb_hw_configure(struct i40e_pf *pf,
11799                       struct i40e_dcbx_config *new_cfg,
11800                       uint8_t tc_map)
11801 {
11802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11803         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11804         struct i40e_vsi *main_vsi = pf->main_vsi;
11805         struct i40e_vsi_list *vsi_list;
11806         enum i40e_status_code ret;
11807         int i;
11808         uint32_t val;
11809
11810         /* Use the FW API if FW > v4.4*/
11811         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11812               (hw->aq.fw_maj_ver >= 5))) {
11813                 PMD_INIT_LOG(ERR,
11814                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11815                 return I40E_ERR_FIRMWARE_API_VERSION;
11816         }
11817
11818         /* Check if need reconfiguration */
11819         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11820                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11821                 return I40E_SUCCESS;
11822         }
11823
11824         /* Copy the new config to the current config */
11825         *old_cfg = *new_cfg;
11826         old_cfg->etsrec = old_cfg->etscfg;
11827         ret = i40e_set_dcb_config(hw);
11828         if (ret) {
11829                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11830                          i40e_stat_str(hw, ret),
11831                          i40e_aq_str(hw, hw->aq.asq_last_status));
11832                 return ret;
11833         }
11834         /* set receive Arbiter to RR mode and ETS scheme by default */
11835         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11836                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11837                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11838                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11839                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11840                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11841                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11842                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11843                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11844                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11845                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11846                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11847                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11848         }
11849         /* get local mib to check whether it is configured correctly */
11850         /* IEEE mode */
11851         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11852         /* Get Local DCB Config */
11853         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11854                                      &hw->local_dcbx_config);
11855
11856         /* if Veb is created, need to update TC of it at first */
11857         if (main_vsi->veb) {
11858                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11859                 if (ret)
11860                         PMD_INIT_LOG(WARNING,
11861                                  "Failed configuring TC for VEB seid=%d",
11862                                  main_vsi->veb->seid);
11863         }
11864         /* Update each VSI */
11865         i40e_vsi_config_tc(main_vsi, tc_map);
11866         if (main_vsi->veb) {
11867                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11868                         /* Beside main VSI and VMDQ VSIs, only enable default
11869                          * TC for other VSIs
11870                          */
11871                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11872                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11873                                                          tc_map);
11874                         else
11875                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11876                                                          I40E_DEFAULT_TCMAP);
11877                         if (ret)
11878                                 PMD_INIT_LOG(WARNING,
11879                                         "Failed configuring TC for VSI seid=%d",
11880                                         vsi_list->vsi->seid);
11881                         /* continue */
11882                 }
11883         }
11884         return I40E_SUCCESS;
11885 }
11886
11887 /*
11888  * i40e_dcb_init_configure - initial dcb config
11889  * @dev: device being configured
11890  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11891  *
11892  * Returns 0 on success, negative value on failure
11893  */
11894 int
11895 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11896 {
11897         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11899         int i, ret = 0;
11900
11901         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11902                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11903                 return -ENOTSUP;
11904         }
11905
11906         /* DCB initialization:
11907          * Update DCB configuration from the Firmware and configure
11908          * LLDP MIB change event.
11909          */
11910         if (sw_dcb == TRUE) {
11911                 /* Stopping lldp is necessary for DPDK, but it will cause
11912                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11913                  * for successful initialization of DCB is that LLDP is
11914                  * enabled. So it is needed to start lldp before DCB init
11915                  * and stop it after initialization.
11916                  */
11917                 ret = i40e_aq_start_lldp(hw, true, NULL);
11918                 if (ret != I40E_SUCCESS)
11919                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11920
11921                 ret = i40e_init_dcb(hw, true);
11922                 /* If lldp agent is stopped, the return value from
11923                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11924                  * adminq status. Otherwise, it should return success.
11925                  */
11926                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11927                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11928                         memset(&hw->local_dcbx_config, 0,
11929                                 sizeof(struct i40e_dcbx_config));
11930                         /* set dcb default configuration */
11931                         hw->local_dcbx_config.etscfg.willing = 0;
11932                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11933                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11934                         hw->local_dcbx_config.etscfg.tsatable[0] =
11935                                                 I40E_IEEE_TSA_ETS;
11936                         /* all UPs mapping to TC0 */
11937                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11938                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11939                         hw->local_dcbx_config.etsrec =
11940                                 hw->local_dcbx_config.etscfg;
11941                         hw->local_dcbx_config.pfc.willing = 0;
11942                         hw->local_dcbx_config.pfc.pfccap =
11943                                                 I40E_MAX_TRAFFIC_CLASS;
11944                         /* FW needs one App to configure HW */
11945                         hw->local_dcbx_config.numapps = 1;
11946                         hw->local_dcbx_config.app[0].selector =
11947                                                 I40E_APP_SEL_ETHTYPE;
11948                         hw->local_dcbx_config.app[0].priority = 3;
11949                         hw->local_dcbx_config.app[0].protocolid =
11950                                                 I40E_APP_PROTOID_FCOE;
11951                         ret = i40e_set_dcb_config(hw);
11952                         if (ret) {
11953                                 PMD_INIT_LOG(ERR,
11954                                         "default dcb config fails. err = %d, aq_err = %d.",
11955                                         ret, hw->aq.asq_last_status);
11956                                 return -ENOSYS;
11957                         }
11958                 } else {
11959                         PMD_INIT_LOG(ERR,
11960                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11961                                 ret, hw->aq.asq_last_status);
11962                         return -ENOTSUP;
11963                 }
11964
11965                 if (i40e_need_stop_lldp(dev)) {
11966                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11967                         if (ret != I40E_SUCCESS)
11968                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11969                 }
11970         } else {
11971                 ret = i40e_aq_start_lldp(hw, true, NULL);
11972                 if (ret != I40E_SUCCESS)
11973                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11974
11975                 ret = i40e_init_dcb(hw, true);
11976                 if (!ret) {
11977                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11978                                 PMD_INIT_LOG(ERR,
11979                                         "HW doesn't support DCBX offload.");
11980                                 return -ENOTSUP;
11981                         }
11982                 } else {
11983                         PMD_INIT_LOG(ERR,
11984                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11985                                 ret, hw->aq.asq_last_status);
11986                         return -ENOTSUP;
11987                 }
11988         }
11989         return 0;
11990 }
11991
11992 /*
11993  * i40e_dcb_setup - setup dcb related config
11994  * @dev: device being configured
11995  *
11996  * Returns 0 on success, negative value on failure
11997  */
11998 static int
11999 i40e_dcb_setup(struct rte_eth_dev *dev)
12000 {
12001         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12002         struct i40e_dcbx_config dcb_cfg;
12003         uint8_t tc_map = 0;
12004         int ret = 0;
12005
12006         if ((pf->flags & I40E_FLAG_DCB) == 0) {
12007                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
12008                 return -ENOTSUP;
12009         }
12010
12011         if (pf->vf_num != 0)
12012                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
12013
12014         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
12015         if (ret) {
12016                 PMD_INIT_LOG(ERR, "invalid dcb config");
12017                 return -EINVAL;
12018         }
12019         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
12020         if (ret) {
12021                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
12022                 return -ENOSYS;
12023         }
12024
12025         return 0;
12026 }
12027
12028 static int
12029 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
12030                       struct rte_eth_dcb_info *dcb_info)
12031 {
12032         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12033         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12034         struct i40e_vsi *vsi = pf->main_vsi;
12035         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
12036         uint16_t bsf, tc_mapping;
12037         int i, j = 0;
12038
12039         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
12040                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
12041         else
12042                 dcb_info->nb_tcs = 1;
12043         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
12044                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
12045         for (i = 0; i < dcb_info->nb_tcs; i++)
12046                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
12047
12048         /* get queue mapping if vmdq is disabled */
12049         if (!pf->nb_cfg_vmdq_vsi) {
12050                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12051                         if (!(vsi->enabled_tc & (1 << i)))
12052                                 continue;
12053                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12054                         dcb_info->tc_queue.tc_rxq[j][i].base =
12055                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12056                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12057                         dcb_info->tc_queue.tc_txq[j][i].base =
12058                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12059                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12060                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12061                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12062                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12063                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12064                 }
12065                 return 0;
12066         }
12067
12068         /* get queue mapping if vmdq is enabled */
12069         do {
12070                 vsi = pf->vmdq[j].vsi;
12071                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12072                         if (!(vsi->enabled_tc & (1 << i)))
12073                                 continue;
12074                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12075                         dcb_info->tc_queue.tc_rxq[j][i].base =
12076                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12077                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12078                         dcb_info->tc_queue.tc_txq[j][i].base =
12079                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12080                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12081                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12082                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12083                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12084                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12085                 }
12086                 j++;
12087         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12088         return 0;
12089 }
12090
12091 static int
12092 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12093 {
12094         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12095         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12096         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12097         uint16_t msix_intr;
12098
12099         msix_intr = intr_handle->intr_vec[queue_id];
12100         if (msix_intr == I40E_MISC_VEC_ID)
12101                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12102                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12103                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12104                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12105         else
12106                 I40E_WRITE_REG(hw,
12107                                I40E_PFINT_DYN_CTLN(msix_intr -
12108                                                    I40E_RX_VEC_START),
12109                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12110                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12111                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12112
12113         I40E_WRITE_FLUSH(hw);
12114         rte_intr_ack(&pci_dev->intr_handle);
12115
12116         return 0;
12117 }
12118
12119 static int
12120 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12121 {
12122         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12123         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12125         uint16_t msix_intr;
12126
12127         msix_intr = intr_handle->intr_vec[queue_id];
12128         if (msix_intr == I40E_MISC_VEC_ID)
12129                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12130                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12131         else
12132                 I40E_WRITE_REG(hw,
12133                                I40E_PFINT_DYN_CTLN(msix_intr -
12134                                                    I40E_RX_VEC_START),
12135                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12136         I40E_WRITE_FLUSH(hw);
12137
12138         return 0;
12139 }
12140
12141 /**
12142  * This function is used to check if the register is valid.
12143  * Below is the valid registers list for X722 only:
12144  * 0x2b800--0x2bb00
12145  * 0x38700--0x38a00
12146  * 0x3d800--0x3db00
12147  * 0x208e00--0x209000
12148  * 0x20be00--0x20c000
12149  * 0x263c00--0x264000
12150  * 0x265c00--0x266000
12151  */
12152 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12153 {
12154         if ((type != I40E_MAC_X722) &&
12155             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12156              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12157              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12158              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12159              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12160              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12161              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12162                 return 0;
12163         else
12164                 return 1;
12165 }
12166
12167 static int i40e_get_regs(struct rte_eth_dev *dev,
12168                          struct rte_dev_reg_info *regs)
12169 {
12170         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12171         uint32_t *ptr_data = regs->data;
12172         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12173         const struct i40e_reg_info *reg_info;
12174
12175         if (ptr_data == NULL) {
12176                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12177                 regs->width = sizeof(uint32_t);
12178                 return 0;
12179         }
12180
12181         /* The first few registers have to be read using AQ operations */
12182         reg_idx = 0;
12183         while (i40e_regs_adminq[reg_idx].name) {
12184                 reg_info = &i40e_regs_adminq[reg_idx++];
12185                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12186                         for (arr_idx2 = 0;
12187                                         arr_idx2 <= reg_info->count2;
12188                                         arr_idx2++) {
12189                                 reg_offset = arr_idx * reg_info->stride1 +
12190                                         arr_idx2 * reg_info->stride2;
12191                                 reg_offset += reg_info->base_addr;
12192                                 ptr_data[reg_offset >> 2] =
12193                                         i40e_read_rx_ctl(hw, reg_offset);
12194                         }
12195         }
12196
12197         /* The remaining registers can be read using primitives */
12198         reg_idx = 0;
12199         while (i40e_regs_others[reg_idx].name) {
12200                 reg_info = &i40e_regs_others[reg_idx++];
12201                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12202                         for (arr_idx2 = 0;
12203                                         arr_idx2 <= reg_info->count2;
12204                                         arr_idx2++) {
12205                                 reg_offset = arr_idx * reg_info->stride1 +
12206                                         arr_idx2 * reg_info->stride2;
12207                                 reg_offset += reg_info->base_addr;
12208                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12209                                         ptr_data[reg_offset >> 2] = 0;
12210                                 else
12211                                         ptr_data[reg_offset >> 2] =
12212                                                 I40E_READ_REG(hw, reg_offset);
12213                         }
12214         }
12215
12216         return 0;
12217 }
12218
12219 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12220 {
12221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12222
12223         /* Convert word count to byte count */
12224         return hw->nvm.sr_size << 1;
12225 }
12226
12227 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12228                            struct rte_dev_eeprom_info *eeprom)
12229 {
12230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12231         uint16_t *data = eeprom->data;
12232         uint16_t offset, length, cnt_words;
12233         int ret_code;
12234
12235         offset = eeprom->offset >> 1;
12236         length = eeprom->length >> 1;
12237         cnt_words = length;
12238
12239         if (offset > hw->nvm.sr_size ||
12240                 offset + length > hw->nvm.sr_size) {
12241                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12242                 return -EINVAL;
12243         }
12244
12245         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12246
12247         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12248         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12249                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12250                 return -EIO;
12251         }
12252
12253         return 0;
12254 }
12255
12256 static int i40e_get_module_info(struct rte_eth_dev *dev,
12257                                 struct rte_eth_dev_module_info *modinfo)
12258 {
12259         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12260         uint32_t sff8472_comp = 0;
12261         uint32_t sff8472_swap = 0;
12262         uint32_t sff8636_rev = 0;
12263         i40e_status status;
12264         uint32_t type = 0;
12265
12266         /* Check if firmware supports reading module EEPROM. */
12267         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12268                 PMD_DRV_LOG(ERR,
12269                             "Module EEPROM memory read not supported. "
12270                             "Please update the NVM image.\n");
12271                 return -EINVAL;
12272         }
12273
12274         status = i40e_update_link_info(hw);
12275         if (status)
12276                 return -EIO;
12277
12278         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12279                 PMD_DRV_LOG(ERR,
12280                             "Cannot read module EEPROM memory. "
12281                             "No module connected.\n");
12282                 return -EINVAL;
12283         }
12284
12285         type = hw->phy.link_info.module_type[0];
12286
12287         switch (type) {
12288         case I40E_MODULE_TYPE_SFP:
12289                 status = i40e_aq_get_phy_register(hw,
12290                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12291                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12292                                 I40E_MODULE_SFF_8472_COMP,
12293                                 &sff8472_comp, NULL);
12294                 if (status)
12295                         return -EIO;
12296
12297                 status = i40e_aq_get_phy_register(hw,
12298                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12299                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12300                                 I40E_MODULE_SFF_8472_SWAP,
12301                                 &sff8472_swap, NULL);
12302                 if (status)
12303                         return -EIO;
12304
12305                 /* Check if the module requires address swap to access
12306                  * the other EEPROM memory page.
12307                  */
12308                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12309                         PMD_DRV_LOG(WARNING,
12310                                     "Module address swap to access "
12311                                     "page 0xA2 is not supported.\n");
12312                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12313                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12314                 } else if (sff8472_comp == 0x00) {
12315                         /* Module is not SFF-8472 compliant */
12316                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12317                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12318                 } else {
12319                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12320                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12321                 }
12322                 break;
12323         case I40E_MODULE_TYPE_QSFP_PLUS:
12324                 /* Read from memory page 0. */
12325                 status = i40e_aq_get_phy_register(hw,
12326                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12327                                 0, 1,
12328                                 I40E_MODULE_REVISION_ADDR,
12329                                 &sff8636_rev, NULL);
12330                 if (status)
12331                         return -EIO;
12332                 /* Determine revision compliance byte */
12333                 if (sff8636_rev > 0x02) {
12334                         /* Module is SFF-8636 compliant */
12335                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12336                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12337                 } else {
12338                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12339                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12340                 }
12341                 break;
12342         case I40E_MODULE_TYPE_QSFP28:
12343                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12344                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12345                 break;
12346         default:
12347                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12348                 return -EINVAL;
12349         }
12350         return 0;
12351 }
12352
12353 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12354                                   struct rte_dev_eeprom_info *info)
12355 {
12356         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12357         bool is_sfp = false;
12358         i40e_status status;
12359         uint8_t *data;
12360         uint32_t value = 0;
12361         uint32_t i;
12362
12363         if (!info || !info->length || !info->data)
12364                 return -EINVAL;
12365
12366         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12367                 is_sfp = true;
12368
12369         data = info->data;
12370         for (i = 0; i < info->length; i++) {
12371                 u32 offset = i + info->offset;
12372                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12373
12374                 /* Check if we need to access the other memory page */
12375                 if (is_sfp) {
12376                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12377                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12378                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12379                         }
12380                 } else {
12381                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12382                                 /* Compute memory page number and offset. */
12383                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12384                                 addr++;
12385                         }
12386                 }
12387                 status = i40e_aq_get_phy_register(hw,
12388                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12389                                 addr, 1, offset, &value, NULL);
12390                 if (status)
12391                         return -EIO;
12392                 data[i] = (uint8_t)value;
12393         }
12394         return 0;
12395 }
12396
12397 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12398                                      struct rte_ether_addr *mac_addr)
12399 {
12400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12401         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12402         struct i40e_vsi *vsi = pf->main_vsi;
12403         struct i40e_mac_filter_info mac_filter;
12404         struct i40e_mac_filter *f;
12405         int ret;
12406
12407         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12408                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12409                 return -EINVAL;
12410         }
12411
12412         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12413                 if (rte_is_same_ether_addr(&pf->dev_addr,
12414                                                 &f->mac_info.mac_addr))
12415                         break;
12416         }
12417
12418         if (f == NULL) {
12419                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12420                 return -EIO;
12421         }
12422
12423         mac_filter = f->mac_info;
12424         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12425         if (ret != I40E_SUCCESS) {
12426                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12427                 return -EIO;
12428         }
12429         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12430         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12431         if (ret != I40E_SUCCESS) {
12432                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12433                 return -EIO;
12434         }
12435         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12436
12437         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12438                                         mac_addr->addr_bytes, NULL);
12439         if (ret != I40E_SUCCESS) {
12440                 PMD_DRV_LOG(ERR, "Failed to change mac");
12441                 return -EIO;
12442         }
12443
12444         return 0;
12445 }
12446
12447 static int
12448 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12449 {
12450         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12451         struct rte_eth_dev_data *dev_data = pf->dev_data;
12452         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12453         int ret = 0;
12454
12455         /* check if mtu is within the allowed range */
12456         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12457                 return -EINVAL;
12458
12459         /* mtu setting is forbidden if port is start */
12460         if (dev_data->dev_started) {
12461                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12462                             dev_data->port_id);
12463                 return -EBUSY;
12464         }
12465
12466         if (frame_size > RTE_ETHER_MAX_LEN)
12467                 dev_data->dev_conf.rxmode.offloads |=
12468                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12469         else
12470                 dev_data->dev_conf.rxmode.offloads &=
12471                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12472
12473         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12474
12475         return ret;
12476 }
12477
12478 /* Restore ethertype filter */
12479 static void
12480 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12481 {
12482         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12483         struct i40e_ethertype_filter_list
12484                 *ethertype_list = &pf->ethertype.ethertype_list;
12485         struct i40e_ethertype_filter *f;
12486         struct i40e_control_filter_stats stats;
12487         uint16_t flags;
12488
12489         TAILQ_FOREACH(f, ethertype_list, rules) {
12490                 flags = 0;
12491                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12492                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12493                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12494                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12495                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12496
12497                 memset(&stats, 0, sizeof(stats));
12498                 i40e_aq_add_rem_control_packet_filter(hw,
12499                                             f->input.mac_addr.addr_bytes,
12500                                             f->input.ether_type,
12501                                             flags, pf->main_vsi->seid,
12502                                             f->queue, 1, &stats, NULL);
12503         }
12504         PMD_DRV_LOG(INFO, "Ethertype filter:"
12505                     " mac_etype_used = %u, etype_used = %u,"
12506                     " mac_etype_free = %u, etype_free = %u",
12507                     stats.mac_etype_used, stats.etype_used,
12508                     stats.mac_etype_free, stats.etype_free);
12509 }
12510
12511 /* Restore tunnel filter */
12512 static void
12513 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12514 {
12515         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12516         struct i40e_vsi *vsi;
12517         struct i40e_pf_vf *vf;
12518         struct i40e_tunnel_filter_list
12519                 *tunnel_list = &pf->tunnel.tunnel_list;
12520         struct i40e_tunnel_filter *f;
12521         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12522         bool big_buffer = 0;
12523
12524         TAILQ_FOREACH(f, tunnel_list, rules) {
12525                 if (!f->is_to_vf)
12526                         vsi = pf->main_vsi;
12527                 else {
12528                         vf = &pf->vfs[f->vf_id];
12529                         vsi = vf->vsi;
12530                 }
12531                 memset(&cld_filter, 0, sizeof(cld_filter));
12532                 rte_ether_addr_copy((struct rte_ether_addr *)
12533                                 &f->input.outer_mac,
12534                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12535                 rte_ether_addr_copy((struct rte_ether_addr *)
12536                                 &f->input.inner_mac,
12537                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12538                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12539                 cld_filter.element.flags = f->input.flags;
12540                 cld_filter.element.tenant_id = f->input.tenant_id;
12541                 cld_filter.element.queue_number = f->queue;
12542                 rte_memcpy(cld_filter.general_fields,
12543                            f->input.general_fields,
12544                            sizeof(f->input.general_fields));
12545
12546                 if (((f->input.flags &
12547                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12548                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12549                     ((f->input.flags &
12550                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12551                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12552                     ((f->input.flags &
12553                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12554                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12555                         big_buffer = 1;
12556
12557                 if (big_buffer)
12558                         i40e_aq_add_cloud_filters_bb(hw,
12559                                         vsi->seid, &cld_filter, 1);
12560                 else
12561                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12562                                                   &cld_filter.element, 1);
12563         }
12564 }
12565
12566 /* Restore RSS filter */
12567 static inline void
12568 i40e_rss_filter_restore(struct i40e_pf *pf)
12569 {
12570         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12571         struct i40e_rss_filter *filter;
12572
12573         TAILQ_FOREACH(filter, list, next) {
12574                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12575         }
12576 }
12577
12578 static void
12579 i40e_filter_restore(struct i40e_pf *pf)
12580 {
12581         i40e_ethertype_filter_restore(pf);
12582         i40e_tunnel_filter_restore(pf);
12583         i40e_fdir_filter_restore(pf);
12584         i40e_rss_filter_restore(pf);
12585 }
12586
12587 bool
12588 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12589 {
12590         if (strcmp(dev->device->driver->name, drv->driver.name))
12591                 return false;
12592
12593         return true;
12594 }
12595
12596 bool
12597 is_i40e_supported(struct rte_eth_dev *dev)
12598 {
12599         return is_device_supported(dev, &rte_i40e_pmd);
12600 }
12601
12602 struct i40e_customized_pctype*
12603 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12604 {
12605         int i;
12606
12607         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12608                 if (pf->customized_pctype[i].index == index)
12609                         return &pf->customized_pctype[i];
12610         }
12611         return NULL;
12612 }
12613
12614 static int
12615 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12616                               uint32_t pkg_size, uint32_t proto_num,
12617                               struct rte_pmd_i40e_proto_info *proto,
12618                               enum rte_pmd_i40e_package_op op)
12619 {
12620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12621         uint32_t pctype_num;
12622         struct rte_pmd_i40e_ptype_info *pctype;
12623         uint32_t buff_size;
12624         struct i40e_customized_pctype *new_pctype = NULL;
12625         uint8_t proto_id;
12626         uint8_t pctype_value;
12627         char name[64];
12628         uint32_t i, j, n;
12629         int ret;
12630
12631         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12632             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12633                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12634                 return -1;
12635         }
12636
12637         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12638                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12639                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12640         if (ret) {
12641                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12642                 return -1;
12643         }
12644         if (!pctype_num) {
12645                 PMD_DRV_LOG(INFO, "No new pctype added");
12646                 return -1;
12647         }
12648
12649         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12650         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12651         if (!pctype) {
12652                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12653                 return -1;
12654         }
12655         /* get information about new pctype list */
12656         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12657                                         (uint8_t *)pctype, buff_size,
12658                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12659         if (ret) {
12660                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12661                 rte_free(pctype);
12662                 return -1;
12663         }
12664
12665         /* Update customized pctype. */
12666         for (i = 0; i < pctype_num; i++) {
12667                 pctype_value = pctype[i].ptype_id;
12668                 memset(name, 0, sizeof(name));
12669                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12670                         proto_id = pctype[i].protocols[j];
12671                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12672                                 continue;
12673                         for (n = 0; n < proto_num; n++) {
12674                                 if (proto[n].proto_id != proto_id)
12675                                         continue;
12676                                 strlcat(name, proto[n].name, sizeof(name));
12677                                 strlcat(name, "_", sizeof(name));
12678                                 break;
12679                         }
12680                 }
12681                 name[strlen(name) - 1] = '\0';
12682                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12683                 if (!strcmp(name, "GTPC"))
12684                         new_pctype =
12685                                 i40e_find_customized_pctype(pf,
12686                                                       I40E_CUSTOMIZED_GTPC);
12687                 else if (!strcmp(name, "GTPU_IPV4"))
12688                         new_pctype =
12689                                 i40e_find_customized_pctype(pf,
12690                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12691                 else if (!strcmp(name, "GTPU_IPV6"))
12692                         new_pctype =
12693                                 i40e_find_customized_pctype(pf,
12694                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12695                 else if (!strcmp(name, "GTPU"))
12696                         new_pctype =
12697                                 i40e_find_customized_pctype(pf,
12698                                                       I40E_CUSTOMIZED_GTPU);
12699                 else if (!strcmp(name, "IPV4_L2TPV3"))
12700                         new_pctype =
12701                                 i40e_find_customized_pctype(pf,
12702                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12703                 else if (!strcmp(name, "IPV6_L2TPV3"))
12704                         new_pctype =
12705                                 i40e_find_customized_pctype(pf,
12706                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12707                 else if (!strcmp(name, "IPV4_ESP"))
12708                         new_pctype =
12709                                 i40e_find_customized_pctype(pf,
12710                                                 I40E_CUSTOMIZED_ESP_IPV4);
12711                 else if (!strcmp(name, "IPV6_ESP"))
12712                         new_pctype =
12713                                 i40e_find_customized_pctype(pf,
12714                                                 I40E_CUSTOMIZED_ESP_IPV6);
12715                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12716                         new_pctype =
12717                                 i40e_find_customized_pctype(pf,
12718                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12719                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12720                         new_pctype =
12721                                 i40e_find_customized_pctype(pf,
12722                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12723                 else if (!strcmp(name, "IPV4_AH"))
12724                         new_pctype =
12725                                 i40e_find_customized_pctype(pf,
12726                                                 I40E_CUSTOMIZED_AH_IPV4);
12727                 else if (!strcmp(name, "IPV6_AH"))
12728                         new_pctype =
12729                                 i40e_find_customized_pctype(pf,
12730                                                 I40E_CUSTOMIZED_AH_IPV6);
12731                 if (new_pctype) {
12732                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12733                                 new_pctype->pctype = pctype_value;
12734                                 new_pctype->valid = true;
12735                         } else {
12736                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12737                                 new_pctype->valid = false;
12738                         }
12739                 }
12740         }
12741
12742         rte_free(pctype);
12743         return 0;
12744 }
12745
12746 static int
12747 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12748                              uint32_t pkg_size, uint32_t proto_num,
12749                              struct rte_pmd_i40e_proto_info *proto,
12750                              enum rte_pmd_i40e_package_op op)
12751 {
12752         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12753         uint16_t port_id = dev->data->port_id;
12754         uint32_t ptype_num;
12755         struct rte_pmd_i40e_ptype_info *ptype;
12756         uint32_t buff_size;
12757         uint8_t proto_id;
12758         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12759         uint32_t i, j, n;
12760         bool in_tunnel;
12761         int ret;
12762
12763         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12764             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12765                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12766                 return -1;
12767         }
12768
12769         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12770                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12771                 return 0;
12772         }
12773
12774         /* get information about new ptype num */
12775         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12776                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12777                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12778         if (ret) {
12779                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12780                 return ret;
12781         }
12782         if (!ptype_num) {
12783                 PMD_DRV_LOG(INFO, "No new ptype added");
12784                 return -1;
12785         }
12786
12787         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12788         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12789         if (!ptype) {
12790                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12791                 return -1;
12792         }
12793
12794         /* get information about new ptype list */
12795         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12796                                         (uint8_t *)ptype, buff_size,
12797                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12798         if (ret) {
12799                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12800                 rte_free(ptype);
12801                 return ret;
12802         }
12803
12804         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12805         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12806         if (!ptype_mapping) {
12807                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12808                 rte_free(ptype);
12809                 return -1;
12810         }
12811
12812         /* Update ptype mapping table. */
12813         for (i = 0; i < ptype_num; i++) {
12814                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12815                 ptype_mapping[i].sw_ptype = 0;
12816                 in_tunnel = false;
12817                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12818                         proto_id = ptype[i].protocols[j];
12819                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12820                                 continue;
12821                         for (n = 0; n < proto_num; n++) {
12822                                 if (proto[n].proto_id != proto_id)
12823                                         continue;
12824                                 memset(name, 0, sizeof(name));
12825                                 strcpy(name, proto[n].name);
12826                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12827                                 if (!strncasecmp(name, "PPPOE", 5))
12828                                         ptype_mapping[i].sw_ptype |=
12829                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12830                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12831                                          !in_tunnel) {
12832                                         ptype_mapping[i].sw_ptype |=
12833                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12834                                         ptype_mapping[i].sw_ptype |=
12835                                                 RTE_PTYPE_L4_FRAG;
12836                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12837                                            in_tunnel) {
12838                                         ptype_mapping[i].sw_ptype |=
12839                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12840                                         ptype_mapping[i].sw_ptype |=
12841                                                 RTE_PTYPE_INNER_L4_FRAG;
12842                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12843                                         ptype_mapping[i].sw_ptype |=
12844                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12845                                         in_tunnel = true;
12846                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12847                                            !in_tunnel)
12848                                         ptype_mapping[i].sw_ptype |=
12849                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12850                                 else if (!strncasecmp(name, "IPV4", 4) &&
12851                                          in_tunnel)
12852                                         ptype_mapping[i].sw_ptype |=
12853                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12854                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12855                                          !in_tunnel) {
12856                                         ptype_mapping[i].sw_ptype |=
12857                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12858                                         ptype_mapping[i].sw_ptype |=
12859                                                 RTE_PTYPE_L4_FRAG;
12860                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12861                                            in_tunnel) {
12862                                         ptype_mapping[i].sw_ptype |=
12863                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12864                                         ptype_mapping[i].sw_ptype |=
12865                                                 RTE_PTYPE_INNER_L4_FRAG;
12866                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12867                                         ptype_mapping[i].sw_ptype |=
12868                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12869                                         in_tunnel = true;
12870                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12871                                            !in_tunnel)
12872                                         ptype_mapping[i].sw_ptype |=
12873                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12874                                 else if (!strncasecmp(name, "IPV6", 4) &&
12875                                          in_tunnel)
12876                                         ptype_mapping[i].sw_ptype |=
12877                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12878                                 else if (!strncasecmp(name, "UDP", 3) &&
12879                                          !in_tunnel)
12880                                         ptype_mapping[i].sw_ptype |=
12881                                                 RTE_PTYPE_L4_UDP;
12882                                 else if (!strncasecmp(name, "UDP", 3) &&
12883                                          in_tunnel)
12884                                         ptype_mapping[i].sw_ptype |=
12885                                                 RTE_PTYPE_INNER_L4_UDP;
12886                                 else if (!strncasecmp(name, "TCP", 3) &&
12887                                          !in_tunnel)
12888                                         ptype_mapping[i].sw_ptype |=
12889                                                 RTE_PTYPE_L4_TCP;
12890                                 else if (!strncasecmp(name, "TCP", 3) &&
12891                                          in_tunnel)
12892                                         ptype_mapping[i].sw_ptype |=
12893                                                 RTE_PTYPE_INNER_L4_TCP;
12894                                 else if (!strncasecmp(name, "SCTP", 4) &&
12895                                          !in_tunnel)
12896                                         ptype_mapping[i].sw_ptype |=
12897                                                 RTE_PTYPE_L4_SCTP;
12898                                 else if (!strncasecmp(name, "SCTP", 4) &&
12899                                          in_tunnel)
12900                                         ptype_mapping[i].sw_ptype |=
12901                                                 RTE_PTYPE_INNER_L4_SCTP;
12902                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12903                                           !strncasecmp(name, "ICMPV6", 6)) &&
12904                                          !in_tunnel)
12905                                         ptype_mapping[i].sw_ptype |=
12906                                                 RTE_PTYPE_L4_ICMP;
12907                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12908                                           !strncasecmp(name, "ICMPV6", 6)) &&
12909                                          in_tunnel)
12910                                         ptype_mapping[i].sw_ptype |=
12911                                                 RTE_PTYPE_INNER_L4_ICMP;
12912                                 else if (!strncasecmp(name, "GTPC", 4)) {
12913                                         ptype_mapping[i].sw_ptype |=
12914                                                 RTE_PTYPE_TUNNEL_GTPC;
12915                                         in_tunnel = true;
12916                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12917                                         ptype_mapping[i].sw_ptype |=
12918                                                 RTE_PTYPE_TUNNEL_GTPU;
12919                                         in_tunnel = true;
12920                                 } else if (!strncasecmp(name, "ESP", 3)) {
12921                                         ptype_mapping[i].sw_ptype |=
12922                                                 RTE_PTYPE_TUNNEL_ESP;
12923                                         in_tunnel = true;
12924                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12925                                         ptype_mapping[i].sw_ptype |=
12926                                                 RTE_PTYPE_TUNNEL_GRENAT;
12927                                         in_tunnel = true;
12928                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12929                                            !strncasecmp(name, "L2TPV2", 6) ||
12930                                            !strncasecmp(name, "L2TPV3", 6)) {
12931                                         ptype_mapping[i].sw_ptype |=
12932                                                 RTE_PTYPE_TUNNEL_L2TP;
12933                                         in_tunnel = true;
12934                                 }
12935
12936                                 break;
12937                         }
12938                 }
12939         }
12940
12941         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12942                                                 ptype_num, 0);
12943         if (ret)
12944                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12945
12946         rte_free(ptype_mapping);
12947         rte_free(ptype);
12948         return ret;
12949 }
12950
12951 void
12952 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12953                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12954 {
12955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12956         uint32_t proto_num;
12957         struct rte_pmd_i40e_proto_info *proto;
12958         uint32_t buff_size;
12959         uint32_t i;
12960         int ret;
12961
12962         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12963             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12964                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12965                 return;
12966         }
12967
12968         /* get information about protocol number */
12969         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12970                                        (uint8_t *)&proto_num, sizeof(proto_num),
12971                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12972         if (ret) {
12973                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12974                 return;
12975         }
12976         if (!proto_num) {
12977                 PMD_DRV_LOG(INFO, "No new protocol added");
12978                 return;
12979         }
12980
12981         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12982         proto = rte_zmalloc("new_proto", buff_size, 0);
12983         if (!proto) {
12984                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12985                 return;
12986         }
12987
12988         /* get information about protocol list */
12989         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12990                                         (uint8_t *)proto, buff_size,
12991                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12992         if (ret) {
12993                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12994                 rte_free(proto);
12995                 return;
12996         }
12997
12998         /* Check if GTP is supported. */
12999         for (i = 0; i < proto_num; i++) {
13000                 if (!strncmp(proto[i].name, "GTP", 3)) {
13001                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13002                                 pf->gtp_support = true;
13003                         else
13004                                 pf->gtp_support = false;
13005                         break;
13006                 }
13007         }
13008
13009         /* Check if ESP is supported. */
13010         for (i = 0; i < proto_num; i++) {
13011                 if (!strncmp(proto[i].name, "ESP", 3)) {
13012                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
13013                                 pf->esp_support = true;
13014                         else
13015                                 pf->esp_support = false;
13016                         break;
13017                 }
13018         }
13019
13020         /* Update customized pctype info */
13021         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
13022                                             proto_num, proto, op);
13023         if (ret)
13024                 PMD_DRV_LOG(INFO, "No pctype is updated.");
13025
13026         /* Update customized ptype info */
13027         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
13028                                            proto_num, proto, op);
13029         if (ret)
13030                 PMD_DRV_LOG(INFO, "No ptype is updated.");
13031
13032         rte_free(proto);
13033 }
13034
13035 /* Create a QinQ cloud filter
13036  *
13037  * The Fortville NIC has limited resources for tunnel filters,
13038  * so we can only reuse existing filters.
13039  *
13040  * In step 1 we define which Field Vector fields can be used for
13041  * filter types.
13042  * As we do not have the inner tag defined as a field,
13043  * we have to define it first, by reusing one of L1 entries.
13044  *
13045  * In step 2 we are replacing one of existing filter types with
13046  * a new one for QinQ.
13047  * As we reusing L1 and replacing L2, some of the default filter
13048  * types will disappear,which depends on L1 and L2 entries we reuse.
13049  *
13050  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
13051  *
13052  * 1.   Create L1 filter of outer vlan (12b) which will be in use
13053  *              later when we define the cloud filter.
13054  *      a.      Valid_flags.replace_cloud = 0
13055  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
13056  *      c.      New_filter = 0x10
13057  *      d.      TR bit = 0xff (optional, not used here)
13058  *      e.      Buffer – 2 entries:
13059  *              i.      Byte 0 = 8 (outer vlan FV index).
13060  *                      Byte 1 = 0 (rsv)
13061  *                      Byte 2-3 = 0x0fff
13062  *              ii.     Byte 0 = 37 (inner vlan FV index).
13063  *                      Byte 1 =0 (rsv)
13064  *                      Byte 2-3 = 0x0fff
13065  *
13066  * Step 2:
13067  * 2.   Create cloud filter using two L1 filters entries: stag and
13068  *              new filter(outer vlan+ inner vlan)
13069  *      a.      Valid_flags.replace_cloud = 1
13070  *      b.      Old_filter = 1 (instead of outer IP)
13071  *      c.      New_filter = 0x10
13072  *      d.      Buffer – 2 entries:
13073  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13074  *                      Byte 1-3 = 0 (rsv)
13075  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13076  *                      Byte 9-11 = 0 (rsv)
13077  */
13078 static int
13079 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13080 {
13081         int ret = -ENOTSUP;
13082         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13083         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13084         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13085         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13086
13087         if (pf->support_multi_driver) {
13088                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13089                 return ret;
13090         }
13091
13092         /* Init */
13093         memset(&filter_replace, 0,
13094                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13095         memset(&filter_replace_buf, 0,
13096                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13097
13098         /* create L1 filter */
13099         filter_replace.old_filter_type =
13100                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13101         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13102         filter_replace.tr_bit = 0;
13103
13104         /* Prepare the buffer, 2 entries */
13105         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13106         filter_replace_buf.data[0] |=
13107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13108         /* Field Vector 12b mask */
13109         filter_replace_buf.data[2] = 0xff;
13110         filter_replace_buf.data[3] = 0x0f;
13111         filter_replace_buf.data[4] =
13112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13113         filter_replace_buf.data[4] |=
13114                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13115         /* Field Vector 12b mask */
13116         filter_replace_buf.data[6] = 0xff;
13117         filter_replace_buf.data[7] = 0x0f;
13118         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13119                         &filter_replace_buf);
13120         if (ret != I40E_SUCCESS)
13121                 return ret;
13122
13123         if (filter_replace.old_filter_type !=
13124             filter_replace.new_filter_type)
13125                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13126                             " original: 0x%x, new: 0x%x",
13127                             dev->device->name,
13128                             filter_replace.old_filter_type,
13129                             filter_replace.new_filter_type);
13130
13131         /* Apply the second L2 cloud filter */
13132         memset(&filter_replace, 0,
13133                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13134         memset(&filter_replace_buf, 0,
13135                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13136
13137         /* create L2 filter, input for L2 filter will be L1 filter  */
13138         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13139         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13140         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13141
13142         /* Prepare the buffer, 2 entries */
13143         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13144         filter_replace_buf.data[0] |=
13145                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13146         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13147         filter_replace_buf.data[4] |=
13148                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13149         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13150                         &filter_replace_buf);
13151         if (!ret && (filter_replace.old_filter_type !=
13152                      filter_replace.new_filter_type))
13153                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13154                             " original: 0x%x, new: 0x%x",
13155                             dev->device->name,
13156                             filter_replace.old_filter_type,
13157                             filter_replace.new_filter_type);
13158
13159         return ret;
13160 }
13161
13162 int
13163 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13164                    const struct rte_flow_action_rss *in)
13165 {
13166         if (in->key_len > RTE_DIM(out->key) ||
13167             in->queue_num > RTE_DIM(out->queue))
13168                 return -EINVAL;
13169         if (!in->key && in->key_len)
13170                 return -EINVAL;
13171         out->conf = (struct rte_flow_action_rss){
13172                 .func = in->func,
13173                 .level = in->level,
13174                 .types = in->types,
13175                 .key_len = in->key_len,
13176                 .queue_num = in->queue_num,
13177                 .queue = memcpy(out->queue, in->queue,
13178                                 sizeof(*in->queue) * in->queue_num),
13179         };
13180         if (in->key)
13181                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13182         return 0;
13183 }
13184
13185 /* Write HENA register to enable hash */
13186 static int
13187 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13188 {
13189         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13190         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13191         uint64_t hena;
13192         int ret;
13193
13194         ret = i40e_set_rss_key(pf->main_vsi, key,
13195                                rss_conf->conf.key_len);
13196         if (ret)
13197                 return ret;
13198
13199         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13200         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13201         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13202         I40E_WRITE_FLUSH(hw);
13203
13204         return 0;
13205 }
13206
13207 /* Configure hash input set */
13208 static int
13209 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13210 {
13211         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13212         struct rte_eth_input_set_conf conf;
13213         uint64_t mask0;
13214         int ret = 0;
13215         uint32_t j;
13216         int i;
13217         static const struct {
13218                 uint64_t type;
13219                 enum rte_eth_input_set_field field;
13220         } inset_match_table[] = {
13221                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13222                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13223                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13224                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13225                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13226                         RTE_ETH_INPUT_SET_UNKNOWN},
13227                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13228                         RTE_ETH_INPUT_SET_UNKNOWN},
13229
13230                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13231                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13232                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13233                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13234                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13235                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13236                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13237                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13238
13239                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13240                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13241                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13242                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13243                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13244                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13245                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13246                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13247
13248                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13249                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13250                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13251                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13252                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13253                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13254                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13255                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13256
13257                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13258                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13259                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13260                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13261                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13262                         RTE_ETH_INPUT_SET_UNKNOWN},
13263                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13264                         RTE_ETH_INPUT_SET_UNKNOWN},
13265
13266                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13267                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13268                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13269                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13270                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13271                         RTE_ETH_INPUT_SET_UNKNOWN},
13272                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13273                         RTE_ETH_INPUT_SET_UNKNOWN},
13274
13275                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13276                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13277                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13278                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13279                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13280                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13281                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13282                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13283
13284                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13285                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13286                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13287                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13288                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13289                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13290                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13291                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13292
13293                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13294                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13295                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13296                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13297                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13298                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13299                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13300                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13301
13302                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13303                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13304                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13305                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13306                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13307                         RTE_ETH_INPUT_SET_UNKNOWN},
13308                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13309                         RTE_ETH_INPUT_SET_UNKNOWN},
13310         };
13311
13312         mask0 = types & pf->adapter->flow_types_mask;
13313         conf.op = RTE_ETH_INPUT_SET_SELECT;
13314         conf.inset_size = 0;
13315         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13316                 if (mask0 & (1ULL << i)) {
13317                         conf.flow_type = i;
13318                         break;
13319                 }
13320         }
13321
13322         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13323                 if ((types & inset_match_table[j].type) ==
13324                     inset_match_table[j].type) {
13325                         if (inset_match_table[j].field ==
13326                             RTE_ETH_INPUT_SET_UNKNOWN)
13327                                 return -EINVAL;
13328
13329                         conf.field[conf.inset_size] =
13330                                 inset_match_table[j].field;
13331                         conf.inset_size++;
13332                 }
13333         }
13334
13335         if (conf.inset_size) {
13336                 ret = i40e_hash_filter_inset_select(hw, &conf);
13337                 if (ret)
13338                         return ret;
13339         }
13340
13341         return ret;
13342 }
13343
13344 /* Look up the conflicted rule then mark it as invalid */
13345 static void
13346 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13347                 struct i40e_rte_flow_rss_conf *conf)
13348 {
13349         struct i40e_rss_filter *rss_item;
13350         uint64_t rss_inset;
13351
13352         /* Clear input set bits before comparing the pctype */
13353         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13354                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13355
13356         /* Look up the conflicted rule then mark it as invalid */
13357         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13358                 if (!rss_item->rss_filter_info.valid)
13359                         continue;
13360
13361                 if (conf->conf.queue_num &&
13362                     rss_item->rss_filter_info.conf.queue_num)
13363                         rss_item->rss_filter_info.valid = false;
13364
13365                 if (conf->conf.types &&
13366                     (rss_item->rss_filter_info.conf.types &
13367                     rss_inset) ==
13368                     (conf->conf.types & rss_inset))
13369                         rss_item->rss_filter_info.valid = false;
13370
13371                 if (conf->conf.func ==
13372                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13373                     rss_item->rss_filter_info.conf.func ==
13374                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13375                         rss_item->rss_filter_info.valid = false;
13376         }
13377 }
13378
13379 /* Configure RSS hash function */
13380 static int
13381 i40e_rss_config_hash_function(struct i40e_pf *pf,
13382                 struct i40e_rte_flow_rss_conf *conf)
13383 {
13384         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13385         uint32_t reg, i;
13386         uint64_t mask0;
13387         uint16_t j;
13388
13389         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13390                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13391                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13392                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13393                         I40E_WRITE_FLUSH(hw);
13394                         i40e_rss_mark_invalid_rule(pf, conf);
13395
13396                         return 0;
13397                 }
13398                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13399
13400                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13401                 I40E_WRITE_FLUSH(hw);
13402                 i40e_rss_mark_invalid_rule(pf, conf);
13403         } else if (conf->conf.func ==
13404                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13405                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13406
13407                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13408                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13409                         if (mask0 & (1UL << i))
13410                                 break;
13411                 }
13412
13413                 if (i == UINT64_BIT)
13414                         return -EINVAL;
13415
13416                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13417                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13418                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13419                                 i40e_write_global_rx_ctl(hw,
13420                                         I40E_GLQF_HSYM(j),
13421                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13422                 }
13423         }
13424
13425         return 0;
13426 }
13427
13428 /* Enable RSS according to the configuration */
13429 static int
13430 i40e_rss_enable_hash(struct i40e_pf *pf,
13431                 struct i40e_rte_flow_rss_conf *conf)
13432 {
13433         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13434         struct i40e_rte_flow_rss_conf rss_conf;
13435
13436         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13437                 return -ENOTSUP;
13438
13439         memset(&rss_conf, 0, sizeof(rss_conf));
13440         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13441
13442         /* Configure hash input set */
13443         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13444                 return -EINVAL;
13445
13446         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13447             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13448                 /* Random default keys */
13449                 static uint32_t rss_key_default[] = {0x6b793944,
13450                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13451                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13452                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13453
13454                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13455                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13456                                 sizeof(uint32_t);
13457                 PMD_DRV_LOG(INFO,
13458                         "No valid RSS key config for i40e, using default\n");
13459         }
13460
13461         rss_conf.conf.types |= rss_info->conf.types;
13462         i40e_rss_hash_set(pf, &rss_conf);
13463
13464         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13465                 i40e_rss_config_hash_function(pf, conf);
13466
13467         i40e_rss_mark_invalid_rule(pf, conf);
13468
13469         return 0;
13470 }
13471
13472 /* Configure RSS queue region */
13473 static int
13474 i40e_rss_config_queue_region(struct i40e_pf *pf,
13475                 struct i40e_rte_flow_rss_conf *conf)
13476 {
13477         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13478         uint32_t lut = 0;
13479         uint16_t j, num;
13480         uint32_t i;
13481
13482         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13483          * It's necessary to calculate the actual PF queues that are configured.
13484          */
13485         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13486                 num = i40e_pf_calc_configured_queues_num(pf);
13487         else
13488                 num = pf->dev_data->nb_rx_queues;
13489
13490         num = RTE_MIN(num, conf->conf.queue_num);
13491         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13492                         num);
13493
13494         if (num == 0) {
13495                 PMD_DRV_LOG(ERR,
13496                         "No PF queues are configured to enable RSS for port %u",
13497                         pf->dev_data->port_id);
13498                 return -ENOTSUP;
13499         }
13500
13501         /* Fill in redirection table */
13502         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13503                 if (j == num)
13504                         j = 0;
13505                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13506                         hw->func_caps.rss_table_entry_width) - 1));
13507                 if ((i & 3) == 3)
13508                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13509         }
13510
13511         i40e_rss_mark_invalid_rule(pf, conf);
13512
13513         return 0;
13514 }
13515
13516 /* Configure RSS hash function to default */
13517 static int
13518 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13519                 struct i40e_rte_flow_rss_conf *conf)
13520 {
13521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13522         uint32_t i, reg;
13523         uint64_t mask0;
13524         uint16_t j;
13525
13526         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13527                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13528                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13529                         PMD_DRV_LOG(DEBUG,
13530                                 "Hash function already set to Toeplitz");
13531                         I40E_WRITE_FLUSH(hw);
13532
13533                         return 0;
13534                 }
13535                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13536
13537                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13538                 I40E_WRITE_FLUSH(hw);
13539         } else if (conf->conf.func ==
13540                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13541                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13542
13543                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13544                         if (mask0 & (1UL << i))
13545                                 break;
13546                 }
13547
13548                 if (i == UINT64_BIT)
13549                         return -EINVAL;
13550
13551                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13552                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13553                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13554                                 i40e_write_global_rx_ctl(hw,
13555                                         I40E_GLQF_HSYM(j),
13556                                         0);
13557                 }
13558         }
13559
13560         return 0;
13561 }
13562
13563 /* Disable RSS hash and configure default input set */
13564 static int
13565 i40e_rss_disable_hash(struct i40e_pf *pf,
13566                 struct i40e_rte_flow_rss_conf *conf)
13567 {
13568         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13569         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13570         struct i40e_rte_flow_rss_conf rss_conf;
13571         uint32_t i;
13572
13573         memset(&rss_conf, 0, sizeof(rss_conf));
13574         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13575
13576         /* Disable RSS hash */
13577         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13578         i40e_rss_hash_set(pf, &rss_conf);
13579
13580         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13581                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13582                     !(conf->conf.types & (1ULL << i)))
13583                         continue;
13584
13585                 /* Configure default input set */
13586                 struct rte_eth_input_set_conf input_conf = {
13587                         .op = RTE_ETH_INPUT_SET_SELECT,
13588                         .flow_type = i,
13589                         .inset_size = 1,
13590                 };
13591                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13592                 i40e_hash_filter_inset_select(hw, &input_conf);
13593         }
13594
13595         rss_info->conf.types = rss_conf.conf.types;
13596
13597         i40e_rss_clear_hash_function(pf, conf);
13598
13599         return 0;
13600 }
13601
13602 /* Configure RSS queue region to default */
13603 static int
13604 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13605 {
13606         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13607         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13608         uint16_t queue[I40E_MAX_Q_PER_TC];
13609         uint32_t num_rxq, i;
13610         uint32_t lut = 0;
13611         uint16_t j, num;
13612
13613         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13614
13615         for (j = 0; j < num_rxq; j++)
13616                 queue[j] = j;
13617
13618         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13619          * It's necessary to calculate the actual PF queues that are configured.
13620          */
13621         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13622                 num = i40e_pf_calc_configured_queues_num(pf);
13623         else
13624                 num = pf->dev_data->nb_rx_queues;
13625
13626         num = RTE_MIN(num, num_rxq);
13627         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13628                         num);
13629
13630         if (num == 0) {
13631                 PMD_DRV_LOG(ERR,
13632                         "No PF queues are configured to enable RSS for port %u",
13633                         pf->dev_data->port_id);
13634                 return -ENOTSUP;
13635         }
13636
13637         /* Fill in redirection table */
13638         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13639                 if (j == num)
13640                         j = 0;
13641                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13642                         hw->func_caps.rss_table_entry_width) - 1));
13643                 if ((i & 3) == 3)
13644                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13645         }
13646
13647         rss_info->conf.queue_num = 0;
13648         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13649
13650         return 0;
13651 }
13652
13653 int
13654 i40e_config_rss_filter(struct i40e_pf *pf,
13655                 struct i40e_rte_flow_rss_conf *conf, bool add)
13656 {
13657         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13658         struct rte_flow_action_rss update_conf = rss_info->conf;
13659         int ret = 0;
13660
13661         if (add) {
13662                 if (conf->conf.queue_num) {
13663                         /* Configure RSS queue region */
13664                         ret = i40e_rss_config_queue_region(pf, conf);
13665                         if (ret)
13666                                 return ret;
13667
13668                         update_conf.queue_num = conf->conf.queue_num;
13669                         update_conf.queue = conf->conf.queue;
13670                 } else if (conf->conf.func ==
13671                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13672                         /* Configure hash function */
13673                         ret = i40e_rss_config_hash_function(pf, conf);
13674                         if (ret)
13675                                 return ret;
13676
13677                         update_conf.func = conf->conf.func;
13678                 } else {
13679                         /* Configure hash enable and input set */
13680                         ret = i40e_rss_enable_hash(pf, conf);
13681                         if (ret)
13682                                 return ret;
13683
13684                         update_conf.types |= conf->conf.types;
13685                         update_conf.key = conf->conf.key;
13686                         update_conf.key_len = conf->conf.key_len;
13687                 }
13688
13689                 /* Update RSS info in pf */
13690                 if (i40e_rss_conf_init(rss_info, &update_conf))
13691                         return -EINVAL;
13692         } else {
13693                 if (!conf->valid)
13694                         return 0;
13695
13696                 if (conf->conf.queue_num)
13697                         i40e_rss_clear_queue_region(pf);
13698                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13699                         i40e_rss_clear_hash_function(pf, conf);
13700                 else
13701                         i40e_rss_disable_hash(pf, conf);
13702         }
13703
13704         return 0;
13705 }
13706
13707 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13708 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13709 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13710 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13711 #endif
13712 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13713 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13714 #endif
13715 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13716 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13717 #endif
13718
13719 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13720                               ETH_I40E_FLOATING_VEB_ARG "=1"
13721                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13722                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13723                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13724                               ETH_I40E_USE_LATEST_VEC "=0|1");