drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control default high water */
  90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  91
  92 /* Flow control default low water */
  93 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  94
  95 /* Flow control enable fwd bit */
  96 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  97
  98 /* Receive Packet Buffer size */
  99 #define I40E_RXPBSIZE (968 * 1024)
 100
 101 /* Kilobytes shift */
 102 #define I40E_KILOSHIFT 10
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_stats *stats);
 262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 263                                struct rte_eth_xstat *xstats, unsigned n);
 264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 265                                      struct rte_eth_xstat_name *xstats_names,
 266                                      unsigned limit);
 267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id,
 270                                             uint8_t stat_idx,
 271                                             uint8_t is_rx);
 272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 273                                 char *fw_version, size_t fw_size);
 274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 275                               struct rte_eth_dev_info *dev_info);
 276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 277                                 uint16_t vlan_id,
 278                                 int on);
 279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 280                               enum rte_vlan_type vlan_type,
 281                               uint16_t tpid);
 282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 284                                       uint16_t queue,
 285                                       int on);
 286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 292                               struct rte_eth_fc_conf *fc_conf);
 293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 294                                        struct rte_eth_pfc_conf *pfc_conf);
 295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 296                             struct ether_addr *mac_addr,
 297                             uint32_t index,
 298                             uint32_t pool);
 299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 301                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                     uint16_t reta_size);
 303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 304                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 305                                    uint16_t reta_size);
 306
 307 static int i40e_get_cap(struct i40e_hw *hw);
 308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 309 static int i40e_pf_setup(struct i40e_pf *pf);
 310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 315                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 316 static void i40e_stat_update_48(struct i40e_hw *hw,
 317                                uint32_t hireg,
 318                                uint32_t loreg,
 319                                bool offset_loaded,
 320                                uint64_t *offset,
 321                                uint64_t *stat);
 322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 323 static void i40e_dev_interrupt_handler(void *param);
 324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 325                                 uint32_t base, uint32_t num);
 326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 328                         uint32_t base);
 329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 330                         uint16_t num);
 331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 332 static int i40e_veb_release(struct i40e_veb *veb);
 333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 334                                                 struct i40e_vsi *vsi);
 335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 338                                              struct i40e_macvlan_filter *mv_f,
 339                                              int num,
 340                                              uint16_t vlan);
 341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 343                                     struct rte_eth_rss_conf *rss_conf);
 344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 345                                       struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 347                                         struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 355                                 enum rte_filter_type filter_type,
 356                                 enum rte_filter_op filter_op,
 357                                 void *arg);
 358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 359                                   struct rte_eth_dcb_info *dcb_info);
 360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 361 static void i40e_configure_registers(struct i40e_hw *hw);
 362 static void i40e_hw_init(struct rte_eth_dev *dev);
 363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 364 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 365                         struct rte_eth_mirror_conf *mirror_conf,
 366                         uint8_t sw_id, uint8_t on);
 367 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 368
 369 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 371 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 372                                            struct timespec *timestamp,
 373                                            uint32_t flags);
 374 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp);
 376 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 377
 378 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 379
 380 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 381                                    struct timespec *timestamp);
 382 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 383                                     const struct timespec *timestamp);
 384
 385 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 386                                          uint16_t queue_id);
 387 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 388                                           uint16_t queue_id);
 389
 390 static int i40e_get_regs(struct rte_eth_dev *dev,
 391                          struct rte_dev_reg_info *regs);
 392
 393 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 394
 395 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 396                            struct rte_dev_eeprom_info *eeprom);
 397
 398 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 399                                       struct ether_addr *mac_addr);
 400
 401 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 402
 403 static int i40e_ethertype_filter_convert(
 404         const struct rte_eth_ethertype_filter *input,
 405         struct i40e_ethertype_filter *filter);
 406 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 407                                    struct i40e_ethertype_filter *filter);
 408
 409 static int i40e_tunnel_filter_convert(
 410         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 411         struct i40e_tunnel_filter *tunnel_filter);
 412 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 413                                 struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 415
 416 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 417 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 418 static void i40e_filter_restore(struct i40e_pf *pf);
 419 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 420
 421 int i40e_logtype_init;
 422 int i40e_logtype_driver;
 423
 424 static const struct rte_pci_id pci_id_i40e_map[] = {
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 445         { .vendor_id = 0, /* sentinel */ },
 446 };
 447
 448 static const struct eth_dev_ops i40e_eth_dev_ops = {
 449         .dev_configure                = i40e_dev_configure,
 450         .dev_start                    = i40e_dev_start,
 451         .dev_stop                     = i40e_dev_stop,
 452         .dev_close                    = i40e_dev_close,
 453         .dev_reset                    = i40e_dev_reset,
 454         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 455         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 456         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 457         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 458         .dev_set_link_up              = i40e_dev_set_link_up,
 459         .dev_set_link_down            = i40e_dev_set_link_down,
 460         .link_update                  = i40e_dev_link_update,
 461         .stats_get                    = i40e_dev_stats_get,
 462         .xstats_get                   = i40e_dev_xstats_get,
 463         .xstats_get_names             = i40e_dev_xstats_get_names,
 464         .stats_reset                  = i40e_dev_stats_reset,
 465         .xstats_reset                 = i40e_dev_stats_reset,
 466         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .mirror_rule_set              = i40e_mirror_rule_set,
 506         .mirror_rule_reset            = i40e_mirror_rule_reset,
 507         .timesync_enable              = i40e_timesync_enable,
 508         .timesync_disable             = i40e_timesync_disable,
 509         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 510         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 511         .get_dcb_info                 = i40e_dev_get_dcb_info,
 512         .timesync_adjust_time         = i40e_timesync_adjust_time,
 513         .timesync_read_time           = i40e_timesync_read_time,
 514         .timesync_write_time          = i40e_timesync_write_time,
 515         .get_reg                      = i40e_get_regs,
 516         .get_eeprom_length            = i40e_get_eeprom_length,
 517         .get_eeprom                   = i40e_get_eeprom,
 518         .mac_addr_set                 = i40e_set_default_mac_addr,
 519         .mtu_set                      = i40e_dev_mtu_set,
 520         .tm_ops_get                   = i40e_tm_ops_get,
 521 };
 522
 523 /* store statistics names and its offset in stats structure */
 524 struct rte_i40e_xstats_name_off {
 525         char name[RTE_ETH_XSTATS_NAME_SIZE];
 526         unsigned offset;
 527 };
 528
 529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 530         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 531         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 532         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 533         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 534         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 535                 rx_unknown_protocol)},
 536         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 537         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 538         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 539         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 540 };
 541
 542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 543                 sizeof(rte_i40e_stats_strings[0]))
 544
 545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 546         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 547                 tx_dropped_link_down)},
 548         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 549         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 550                 illegal_bytes)},
 551         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 552         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_local_faults)},
 554         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_remote_faults)},
 556         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_length_errors)},
 558         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 559         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 560         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 561         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 562         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 563         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_127)},
 565         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_255)},
 567         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_511)},
 569         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1023)},
 571         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1522)},
 573         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_big)},
 575         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_undersize)},
 577         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_oversize)},
 579         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 580                 mac_short_packet_dropped)},
 581         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_fragments)},
 583         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 584         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 585         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_127)},
 587         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_255)},
 589         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_511)},
 591         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1023)},
 593         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1522)},
 595         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_big)},
 597         {"rx_flow_director_atr_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 599         {"rx_flow_director_sb_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 601         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_status)},
 603         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_status)},
 605         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_count)},
 607         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_count)},
 609 };
 610
 611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 612                 sizeof(rte_i40e_hw_port_strings[0]))
 613
 614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 615         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xon_rx)},
 617         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xoff_rx)},
 619 };
 620
 621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 622                 sizeof(rte_i40e_rxq_prio_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_tx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_tx)},
 629         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_2_xoff)},
 631 };
 632
 633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 634                 sizeof(rte_i40e_txq_prio_strings[0]))
 635
 636 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 637         struct rte_pci_device *pci_dev)
 638 {
 639         return rte_eth_dev_pci_generic_probe(pci_dev,
 640                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 641 }
 642
 643 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 644 {
 645         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 646 }
 647
 648 static struct rte_pci_driver rte_i40e_pmd = {
 649         .id_table = pci_id_i40e_map,
 650         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 651         .probe = eth_i40e_pci_probe,
 652         .remove = eth_i40e_pci_remove,
 653 };
 654
 655 static inline int
 656 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 657                                      struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = link;
 660         struct rte_eth_link *src = &(dev->data->dev_link);
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 static inline int
 670 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 671                                       struct rte_eth_link *link)
 672 {
 673         struct rte_eth_link *dst = &(dev->data->dev_link);
 674         struct rte_eth_link *src = link;
 675
 676         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 677                                         *(uint64_t *)src) == 0)
 678                 return -1;
 679
 680         return 0;
 681 }
 682
 683 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 684 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 685 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 686
 687 #ifndef I40E_GLQF_ORT
 688 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_PIT
 691 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_L3_MAP
 694 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 695 #endif
 696
 697 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 698 {
 699         /*
 700          * Initialize registers for flexible payload, which should be set by NVM.
 701          * This should be removed from code once it is fixed in NVM.
 702          */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 713         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 714         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 715
 716         /* Initialize registers for parsing packet type of QinQ */
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 718         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 719 }
 720
 721 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 722
 723 /*
 724  * Add a ethertype filter to drop all flow control frames transmitted
 725  * from VSIs.
 726 */
 727 static void
 728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 729 {
 730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 731         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 732                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 733                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 734         int ret;
 735
 736         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 737                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 738                                 pf->main_vsi_seid, 0,
 739                                 TRUE, NULL, NULL);
 740         if (ret)
 741                 PMD_INIT_LOG(ERR,
 742                         "Failed to add filter to drop flow control frames from VSIs.");
 743 }
 744
 745 static int
 746 floating_veb_list_handler(__rte_unused const char *key,
 747                           const char *floating_veb_value,
 748                           void *opaque)
 749 {
 750         int idx = 0;
 751         unsigned int count = 0;
 752         char *end = NULL;
 753         int min, max;
 754         bool *vf_floating_veb = opaque;
 755
 756         while (isblank(*floating_veb_value))
 757                 floating_veb_value++;
 758
 759         /* Reset floating VEB configuration for VFs */
 760         for (idx = 0; idx < I40E_MAX_VF; idx++)
 761                 vf_floating_veb[idx] = false;
 762
 763         min = I40E_MAX_VF;
 764         do {
 765                 while (isblank(*floating_veb_value))
 766                         floating_veb_value++;
 767                 if (*floating_veb_value == '\0')
 768                         return -1;
 769                 errno = 0;
 770                 idx = strtoul(floating_veb_value, &end, 10);
 771                 if (errno || end == NULL)
 772                         return -1;
 773                 while (isblank(*end))
 774                         end++;
 775                 if (*end == '-') {
 776                         min = idx;
 777                 } else if ((*end == ';') || (*end == '\0')) {
 778                         max = idx;
 779                         if (min == I40E_MAX_VF)
 780                                 min = idx;
 781                         if (max >= I40E_MAX_VF)
 782                                 max = I40E_MAX_VF - 1;
 783                         for (idx = min; idx <= max; idx++) {
 784                                 vf_floating_veb[idx] = true;
 785                                 count++;
 786                         }
 787                         min = I40E_MAX_VF;
 788                 } else {
 789                         return -1;
 790                 }
 791                 floating_veb_value = end + 1;
 792         } while (*end != '\0');
 793
 794         if (count == 0)
 795                 return -1;
 796
 797         return 0;
 798 }
 799
 800 static void
 801 config_vf_floating_veb(struct rte_devargs *devargs,
 802                        uint16_t floating_veb,
 803                        bool *vf_floating_veb)
 804 {
 805         struct rte_kvargs *kvlist;
 806         int i;
 807         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 808
 809         if (!floating_veb)
 810                 return;
 811         /* All the VFs attach to the floating VEB by default
 812          * when the floating VEB is enabled.
 813          */
 814         for (i = 0; i < I40E_MAX_VF; i++)
 815                 vf_floating_veb[i] = true;
 816
 817         if (devargs == NULL)
 818                 return;
 819
 820         kvlist = rte_kvargs_parse(devargs->args, NULL);
 821         if (kvlist == NULL)
 822                 return;
 823
 824         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 825                 rte_kvargs_free(kvlist);
 826                 return;
 827         }
 828         /* When the floating_veb_list parameter exists, all the VFs
 829          * will attach to the legacy VEB firstly, then configure VFs
 830          * to the floating VEB according to the floating_veb_list.
 831          */
 832         if (rte_kvargs_process(kvlist, floating_veb_list,
 833                                floating_veb_list_handler,
 834                                vf_floating_veb) < 0) {
 835                 rte_kvargs_free(kvlist);
 836                 return;
 837         }
 838         rte_kvargs_free(kvlist);
 839 }
 840
 841 static int
 842 i40e_check_floating_handler(__rte_unused const char *key,
 843                             const char *value,
 844                             __rte_unused void *opaque)
 845 {
 846         if (strcmp(value, "1"))
 847                 return -1;
 848
 849         return 0;
 850 }
 851
 852 static int
 853 is_floating_veb_supported(struct rte_devargs *devargs)
 854 {
 855         struct rte_kvargs *kvlist;
 856         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 857
 858         if (devargs == NULL)
 859                 return 0;
 860
 861         kvlist = rte_kvargs_parse(devargs->args, NULL);
 862         if (kvlist == NULL)
 863                 return 0;
 864
 865         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 866                 rte_kvargs_free(kvlist);
 867                 return 0;
 868         }
 869         /* Floating VEB is enabled when there's key-value:
 870          * enable_floating_veb=1
 871          */
 872         if (rte_kvargs_process(kvlist, floating_veb_key,
 873                                i40e_check_floating_handler, NULL) < 0) {
 874                 rte_kvargs_free(kvlist);
 875                 return 0;
 876         }
 877         rte_kvargs_free(kvlist);
 878
 879         return 1;
 880 }
 881
 882 static void
 883 config_floating_veb(struct rte_eth_dev *dev)
 884 {
 885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 888
 889         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 890
 891         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 892                 pf->floating_veb =
 893                         is_floating_veb_supported(pci_dev->device.devargs);
 894                 config_vf_floating_veb(pci_dev->device.devargs,
 895                                        pf->floating_veb,
 896                                        pf->floating_veb_list);
 897         } else {
 898                 pf->floating_veb = false;
 899         }
 900 }
 901
 902 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 903 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 904
 905 static int
 906 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 907 {
 908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 909         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 910         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 911         int ret;
 912
 913         struct rte_hash_parameters ethertype_hash_params = {
 914                 .name = ethertype_hash_name,
 915                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 916                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 917                 .hash_func = rte_hash_crc,
 918                 .hash_func_init_val = 0,
 919                 .socket_id = rte_socket_id(),
 920         };
 921
 922         /* Initialize ethertype filter rule list and hash */
 923         TAILQ_INIT(&ethertype_rule->ethertype_list);
 924         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 925                  "ethertype_%s", dev->device->name);
 926         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 927         if (!ethertype_rule->hash_table) {
 928                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 929                 return -EINVAL;
 930         }
 931         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 932                                        sizeof(struct i40e_ethertype_filter *) *
 933                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 934                                        0);
 935         if (!ethertype_rule->hash_map) {
 936                 PMD_INIT_LOG(ERR,
 937                              "Failed to allocate memory for ethertype hash map!");
 938                 ret = -ENOMEM;
 939                 goto err_ethertype_hash_map_alloc;
 940         }
 941
 942         return 0;
 943
 944 err_ethertype_hash_map_alloc:
 945         rte_hash_free(ethertype_rule->hash_table);
 946
 947         return ret;
 948 }
 949
 950 static int
 951 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 955         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters tunnel_hash_params = {
 959                 .name = tunnel_hash_name,
 960                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize tunnel filter rule list and hash */
 968         TAILQ_INIT(&tunnel_rule->tunnel_list);
 969         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 970                  "tunnel_%s", dev->device->name);
 971         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 972         if (!tunnel_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 974                 return -EINVAL;
 975         }
 976         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 977                                     sizeof(struct i40e_tunnel_filter *) *
 978                                     I40E_MAX_TUNNEL_FILTER_NUM,
 979                                     0);
 980         if (!tunnel_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for tunnel hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_tunnel_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_tunnel_hash_map_alloc:
 990         rte_hash_free(tunnel_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_fdir_info *fdir_info = &pf->fdir;
1000         char fdir_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters fdir_hash_params = {
1004                 .name = fdir_hash_name,
1005                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1006                 .key_len = sizeof(struct rte_eth_fdir_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize flow director filter rule list and hash */
1013         TAILQ_INIT(&fdir_info->fdir_list);
1014         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1015                  "fdir_%s", dev->device->name);
1016         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1017         if (!fdir_info->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1019                 return -EINVAL;
1020         }
1021         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1022                                           sizeof(struct i40e_fdir_filter *) *
1023                                           I40E_MAX_FDIR_FILTER_NUM,
1024                                           0);
1025         if (!fdir_info->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for fdir hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_fdir_hash_map_alloc;
1030         }
1031         return 0;
1032
1033 err_fdir_hash_map_alloc:
1034         rte_hash_free(fdir_info->hash_table);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 eth_i40e_dev_init(struct rte_eth_dev *dev)
1041 {
1042         struct rte_pci_device *pci_dev;
1043         struct rte_intr_handle *intr_handle;
1044         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         struct i40e_vsi *vsi;
1047         int ret;
1048         uint32_t len;
1049         uint8_t aq_fail = 0;
1050
1051         PMD_INIT_FUNC_TRACE();
1052
1053         dev->dev_ops = &i40e_eth_dev_ops;
1054         dev->rx_pkt_burst = i40e_recv_pkts;
1055         dev->tx_pkt_burst = i40e_xmit_pkts;
1056         dev->tx_pkt_prepare = i40e_prep_pkts;
1057
1058         /* for secondary processes, we don't initialise any further as primary
1059          * has already done this work. Only check we don't need a different
1060          * RX function */
1061         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1062                 i40e_set_rx_function(dev);
1063                 i40e_set_tx_function(dev);
1064                 return 0;
1065         }
1066         i40e_set_default_ptype_table(dev);
1067         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1068         intr_handle = &pci_dev->intr_handle;
1069
1070         rte_eth_copy_pci_info(dev, pci_dev);
1071         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1072
1073         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074         pf->adapter->eth_dev = dev;
1075         pf->dev_data = dev->data;
1076
1077         hw->back = I40E_PF_TO_ADAPTER(pf);
1078         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1079         if (!hw->hw_addr) {
1080                 PMD_INIT_LOG(ERR,
1081                         "Hardware is not available, as address is NULL");
1082                 return -ENODEV;
1083         }
1084
1085         hw->vendor_id = pci_dev->id.vendor_id;
1086         hw->device_id = pci_dev->id.device_id;
1087         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1088         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1089         hw->bus.device = pci_dev->addr.devid;
1090         hw->bus.func = pci_dev->addr.function;
1091         hw->adapter_stopped = 0;
1092
1093         /* Make sure all is clean before doing PF reset */
1094         i40e_clear_hw(hw);
1095
1096         /* Initialize the hardware */
1097         i40e_hw_init(dev);
1098
1099         /* Reset here to make sure all is clean for each PF */
1100         ret = i40e_pf_reset(hw);
1101         if (ret) {
1102                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103                 return ret;
1104         }
1105
1106         /* Initialize the shared code (base driver) */
1107         ret = i40e_init_shared_code(hw);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1110                 return ret;
1111         }
1112
1113         /*
1114          * To work around the NVM issue, initialize registers
1115          * for flexible payload and packet type of QinQ by
1116          * software. It should be removed once issues are fixed
1117          * in NVM.
1118          */
1119         i40e_GLQF_reg_init(hw);
1120
1121         /* Initialize the input set for filters (hash and fd) to default value */
1122         i40e_filter_input_set_init(pf);
1123
1124         /* Initialize the parameters for adminq */
1125         i40e_init_adminq_parameter(hw);
1126         ret = i40e_init_adminq(hw);
1127         if (ret != I40E_SUCCESS) {
1128                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1129                 return -EIO;
1130         }
1131         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1132                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1133                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1134                      ((hw->nvm.version >> 12) & 0xf),
1135                      ((hw->nvm.version >> 4) & 0xff),
1136                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1137
1138         /* initialise the L3_MAP register */
1139         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1140                                    0x00000028,  NULL);
1141         if (ret)
1142                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1143
1144         /* Need the special FW version to support floating VEB */
1145         config_floating_veb(dev);
1146         /* Clear PXE mode */
1147         i40e_clear_pxe_mode(hw);
1148         i40e_dev_sync_phy_type(hw);
1149
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         /* initialize Traffic Manager configuration */
1302         i40e_tm_conf_init(dev);
1303
1304         ret = i40e_init_ethtype_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_ethtype_filter_list;
1307         ret = i40e_init_tunnel_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_tunnel_filter_list;
1310         ret = i40e_init_fdir_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_fdir_filter_list;
1313
1314         return 0;
1315
1316 err_init_fdir_filter_list:
1317         rte_free(pf->tunnel.hash_table);
1318         rte_free(pf->tunnel.hash_map);
1319 err_init_tunnel_filter_list:
1320         rte_free(pf->ethertype.hash_table);
1321         rte_free(pf->ethertype.hash_map);
1322 err_init_ethtype_filter_list:
1323         rte_free(dev->data->mac_addrs);
1324 err_mac_alloc:
1325         i40e_vsi_release(pf->main_vsi);
1326 err_setup_pf_switch:
1327 err_get_mac_addr:
1328 err_configure_lan_hmc:
1329         (void)i40e_shutdown_lan_hmc(hw);
1330 err_init_lan_hmc:
1331         i40e_res_pool_destroy(&pf->msix_pool);
1332 err_msix_pool_init:
1333         i40e_res_pool_destroy(&pf->qp_pool);
1334 err_qp_pool_init:
1335 err_parameter_init:
1336 err_get_capabilities:
1337         (void)i40e_shutdown_adminq(hw);
1338
1339         return ret;
1340 }
1341
1342 static void
1343 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1344 {
1345         struct i40e_ethertype_filter *p_ethertype;
1346         struct i40e_ethertype_rule *ethertype_rule;
1347
1348         ethertype_rule = &pf->ethertype;
1349         /* Remove all ethertype filter rules and hash */
1350         if (ethertype_rule->hash_map)
1351                 rte_free(ethertype_rule->hash_map);
1352         if (ethertype_rule->hash_table)
1353                 rte_hash_free(ethertype_rule->hash_table);
1354
1355         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1356                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1357                              p_ethertype, rules);
1358                 rte_free(p_ethertype);
1359         }
1360 }
1361
1362 static void
1363 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1364 {
1365         struct i40e_tunnel_filter *p_tunnel;
1366         struct i40e_tunnel_rule *tunnel_rule;
1367
1368         tunnel_rule = &pf->tunnel;
1369         /* Remove all tunnel director rules and hash */
1370         if (tunnel_rule->hash_map)
1371                 rte_free(tunnel_rule->hash_map);
1372         if (tunnel_rule->hash_table)
1373                 rte_hash_free(tunnel_rule->hash_table);
1374
1375         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1376                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1377                 rte_free(p_tunnel);
1378         }
1379 }
1380
1381 static void
1382 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1383 {
1384         struct i40e_fdir_filter *p_fdir;
1385         struct i40e_fdir_info *fdir_info;
1386
1387         fdir_info = &pf->fdir;
1388         /* Remove all flow director rules and hash */
1389         if (fdir_info->hash_map)
1390                 rte_free(fdir_info->hash_map);
1391         if (fdir_info->hash_table)
1392                 rte_hash_free(fdir_info->hash_table);
1393
1394         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1395                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1396                 rte_free(p_fdir);
1397         }
1398 }
1399
1400 static int
1401 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 {
1403         struct i40e_pf *pf;
1404         struct rte_pci_device *pci_dev;
1405         struct rte_intr_handle *intr_handle;
1406         struct i40e_hw *hw;
1407         struct i40e_filter_control_settings settings;
1408         struct rte_flow *p_flow;
1409         int ret;
1410         uint8_t aq_fail = 0;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415                 return 0;
1416
1417         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420         intr_handle = &pci_dev->intr_handle;
1421
1422         if (hw->adapter_stopped == 0)
1423                 i40e_dev_close(dev);
1424
1425         dev->dev_ops = NULL;
1426         dev->rx_pkt_burst = NULL;
1427         dev->tx_pkt_burst = NULL;
1428
1429         /* Clear PXE mode */
1430         i40e_clear_pxe_mode(hw);
1431
1432         /* Unconfigure filter control */
1433         memset(&settings, 0, sizeof(settings));
1434         ret = i40e_set_filter_control(hw, &settings);
1435         if (ret)
1436                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437                                         ret);
1438
1439         /* Disable flow control */
1440         hw->fc.requested_mode = I40E_FC_NONE;
1441         i40e_set_fc(hw, &aq_fail, TRUE);
1442
1443         /* uninitialize pf host driver */
1444         i40e_pf_host_uninit(dev);
1445
1446         rte_free(dev->data->mac_addrs);
1447         dev->data->mac_addrs = NULL;
1448
1449         /* disable uio intr before callback unregister */
1450         rte_intr_disable(intr_handle);
1451
1452         /* register callback func to eal lib */
1453         rte_intr_callback_unregister(intr_handle,
1454                                      i40e_dev_interrupt_handler, dev);
1455
1456         i40e_rm_ethtype_filter_list(pf);
1457         i40e_rm_tunnel_filter_list(pf);
1458         i40e_rm_fdir_filter_list(pf);
1459
1460         /* Remove all flows */
1461         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1462                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1463                 rte_free(p_flow);
1464         }
1465
1466         /* Remove all Traffic Manager configuration */
1467         i40e_tm_conf_uninit(dev);
1468
1469         return 0;
1470 }
1471
1472 static int
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1474 {
1475         struct i40e_adapter *ad =
1476                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1480         int i, ret;
1481
1482         ret = i40e_dev_sync_phy_type(hw);
1483         if (ret)
1484                 return ret;
1485
1486         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1487          * bulk allocation or vector Rx preconditions we will reset it.
1488          */
1489         ad->rx_bulk_alloc_allowed = true;
1490         ad->rx_vec_allowed = true;
1491         ad->tx_simple_allowed = true;
1492         ad->tx_vec_allowed = true;
1493
1494         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1495                 ret = i40e_fdir_setup(pf);
1496                 if (ret != I40E_SUCCESS) {
1497                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1498                         return -ENOTSUP;
1499                 }
1500                 ret = i40e_fdir_configure(dev);
1501                 if (ret < 0) {
1502                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1503                         goto err;
1504                 }
1505         } else
1506                 i40e_fdir_teardown(pf);
1507
1508         ret = i40e_dev_init_vlan(dev);
1509         if (ret < 0)
1510                 goto err;
1511
1512         /* VMDQ setup.
1513          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1514          *  RSS setting have different requirements.
1515          *  General PMD driver call sequence are NIC init, configure,
1516          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1517          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1518          *  applicable. So, VMDQ setting has to be done before
1519          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1520          *  For RSS setting, it will try to calculate actual configured RX queue
1521          *  number, which will be available after rx_queue_setup(). dev_start()
1522          *  function is good to place RSS setup.
1523          */
1524         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1525                 ret = i40e_vmdq_setup(dev);
1526                 if (ret)
1527                         goto err;
1528         }
1529
1530         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1531                 ret = i40e_dcb_setup(dev);
1532                 if (ret) {
1533                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1534                         goto err_dcb;
1535                 }
1536         }
1537
1538         TAILQ_INIT(&pf->flow_list);
1539
1540         return 0;
1541
1542 err_dcb:
1543         /* need to release vmdq resource if exists */
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_release(pf->vmdq[i].vsi);
1546                 pf->vmdq[i].vsi = NULL;
1547         }
1548         rte_free(pf->vmdq);
1549         pf->vmdq = NULL;
1550 err:
1551         /* need to release fdir resource if exists */
1552         i40e_fdir_teardown(pf);
1553         return ret;
1554 }
1555
1556 void
1557 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1558 {
1559         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1560         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563         uint16_t msix_vect = vsi->msix_intr;
1564         uint16_t i;
1565
1566         for (i = 0; i < vsi->nb_qps; i++) {
1567                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1568                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1569                 rte_wmb();
1570         }
1571
1572         if (vsi->type != I40E_VSI_SRIOV) {
1573                 if (!rte_intr_allow_others(intr_handle)) {
1574                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1575                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1576                         I40E_WRITE_REG(hw,
1577                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1578                                        0);
1579                 } else {
1580                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1581                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1582                         I40E_WRITE_REG(hw,
1583                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1584                                                        msix_vect - 1), 0);
1585                 }
1586         } else {
1587                 uint32_t reg;
1588                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1589                         vsi->user_param + (msix_vect - 1);
1590
1591                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1592                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1593         }
1594         I40E_WRITE_FLUSH(hw);
1595 }
1596
1597 static void
1598 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1599                        int base_queue, int nb_queue)
1600 {
1601         int i;
1602         uint32_t val;
1603         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1604
1605         /* Bind all RX queues to allocated MSIX interrupt */
1606         for (i = 0; i < nb_queue; i++) {
1607                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1608                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1609                         ((base_queue + i + 1) <<
1610                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1611                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1612                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1613
1614                 if (i == nb_queue - 1)
1615                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1616                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1617         }
1618
1619         /* Write first RX queue to Link list register as the head element */
1620         if (vsi->type != I40E_VSI_SRIOV) {
1621                 uint16_t interval =
1622                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1623
1624                 if (msix_vect == I40E_MISC_VEC_ID) {
1625                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1626                                        (base_queue <<
1627                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1628                                        (0x0 <<
1629                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1630                         I40E_WRITE_REG(hw,
1631                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1632                                        interval);
1633                 } else {
1634                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1635                                        (base_queue <<
1636                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1637                                        (0x0 <<
1638                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1639                         I40E_WRITE_REG(hw,
1640                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1641                                                        msix_vect - 1),
1642                                        interval);
1643                 }
1644         } else {
1645                 uint32_t reg;
1646
1647                 if (msix_vect == I40E_MISC_VEC_ID) {
1648                         I40E_WRITE_REG(hw,
1649                                        I40E_VPINT_LNKLST0(vsi->user_param),
1650                                        (base_queue <<
1651                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1652                                        (0x0 <<
1653                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1654                 } else {
1655                         /* num_msix_vectors_vf needs to minus irq0 */
1656                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1657                                 vsi->user_param + (msix_vect - 1);
1658
1659                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1660                                        (base_queue <<
1661                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1662                                        (0x0 <<
1663                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1664                 }
1665         }
1666
1667         I40E_WRITE_FLUSH(hw);
1668 }
1669
1670 void
1671 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1672 {
1673         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1674         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1675         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1676         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1677         uint16_t msix_vect = vsi->msix_intr;
1678         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1679         uint16_t queue_idx = 0;
1680         int record = 0;
1681         uint32_t val;
1682         int i;
1683
1684         for (i = 0; i < vsi->nb_qps; i++) {
1685                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1686                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1687         }
1688
1689         /* INTENA flag is not auto-cleared for interrupt */
1690         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1691         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1692                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1693                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1694         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1695
1696         /* VF bind interrupt */
1697         if (vsi->type == I40E_VSI_SRIOV) {
1698                 __vsi_queues_bind_intr(vsi, msix_vect,
1699                                        vsi->base_queue, vsi->nb_qps);
1700                 return;
1701         }
1702
1703         /* PF & VMDq bind interrupt */
1704         if (rte_intr_dp_is_en(intr_handle)) {
1705                 if (vsi->type == I40E_VSI_MAIN) {
1706                         queue_idx = 0;
1707                         record = 1;
1708                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1709                         struct i40e_vsi *main_vsi =
1710                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1711                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1712                         record = 1;
1713                 }
1714         }
1715
1716         for (i = 0; i < vsi->nb_used_qps; i++) {
1717                 if (nb_msix <= 1) {
1718                         if (!rte_intr_allow_others(intr_handle))
1719                                 /* allow to share MISC_VEC_ID */
1720                                 msix_vect = I40E_MISC_VEC_ID;
1721
1722                         /* no enough msix_vect, map all to one */
1723                         __vsi_queues_bind_intr(vsi, msix_vect,
1724                                                vsi->base_queue + i,
1725                                                vsi->nb_used_qps - i);
1726                         for (; !!record && i < vsi->nb_used_qps; i++)
1727                                 intr_handle->intr_vec[queue_idx + i] =
1728                                         msix_vect;
1729                         break;
1730                 }
1731                 /* 1:1 queue/msix_vect mapping */
1732                 __vsi_queues_bind_intr(vsi, msix_vect,
1733                                        vsi->base_queue + i, 1);
1734                 if (!!record)
1735                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1736
1737                 msix_vect++;
1738                 nb_msix--;
1739         }
1740 }
1741
1742 static void
1743 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1744 {
1745         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1746         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1747         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1748         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1749         uint16_t interval = i40e_calc_itr_interval(\
1750                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1751         uint16_t msix_intr, i;
1752
1753         if (rte_intr_allow_others(intr_handle))
1754                 for (i = 0; i < vsi->nb_msix; i++) {
1755                         msix_intr = vsi->msix_intr + i;
1756                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1757                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1758                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1759                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1760                                 (interval <<
1761                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1762                 }
1763         else
1764                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1765                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1766                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1767                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1768                                (interval <<
1769                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1770
1771         I40E_WRITE_FLUSH(hw);
1772 }
1773
1774 static void
1775 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1776 {
1777         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1778         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1779         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1781         uint16_t msix_intr, i;
1782
1783         if (rte_intr_allow_others(intr_handle))
1784                 for (i = 0; i < vsi->nb_msix; i++) {
1785                         msix_intr = vsi->msix_intr + i;
1786                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1787                                        0);
1788                 }
1789         else
1790                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1791
1792         I40E_WRITE_FLUSH(hw);
1793 }
1794
1795 static inline uint8_t
1796 i40e_parse_link_speeds(uint16_t link_speeds)
1797 {
1798         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1799
1800         if (link_speeds & ETH_LINK_SPEED_40G)
1801                 link_speed |= I40E_LINK_SPEED_40GB;
1802         if (link_speeds & ETH_LINK_SPEED_25G)
1803                 link_speed |= I40E_LINK_SPEED_25GB;
1804         if (link_speeds & ETH_LINK_SPEED_20G)
1805                 link_speed |= I40E_LINK_SPEED_20GB;
1806         if (link_speeds & ETH_LINK_SPEED_10G)
1807                 link_speed |= I40E_LINK_SPEED_10GB;
1808         if (link_speeds & ETH_LINK_SPEED_1G)
1809                 link_speed |= I40E_LINK_SPEED_1GB;
1810         if (link_speeds & ETH_LINK_SPEED_100M)
1811                 link_speed |= I40E_LINK_SPEED_100MB;
1812
1813         return link_speed;
1814 }
1815
1816 static int
1817 i40e_phy_conf_link(struct i40e_hw *hw,
1818                    uint8_t abilities,
1819                    uint8_t force_speed,
1820                    bool is_up)
1821 {
1822         enum i40e_status_code status;
1823         struct i40e_aq_get_phy_abilities_resp phy_ab;
1824         struct i40e_aq_set_phy_config phy_conf;
1825         enum i40e_aq_phy_type cnt;
1826         uint32_t phy_type_mask = 0;
1827
1828         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1829                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1830                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1831                         I40E_AQ_PHY_FLAG_LOW_POWER;
1832         const uint8_t advt = I40E_LINK_SPEED_40GB |
1833                         I40E_LINK_SPEED_25GB |
1834                         I40E_LINK_SPEED_10GB |
1835                         I40E_LINK_SPEED_1GB |
1836                         I40E_LINK_SPEED_100MB;
1837         int ret = -ENOTSUP;
1838
1839
1840         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1841                                               NULL);
1842         if (status)
1843                 return ret;
1844
1845         /* If link already up, no need to set up again */
1846         if (is_up && phy_ab.phy_type != 0)
1847                 return I40E_SUCCESS;
1848
1849         memset(&phy_conf, 0, sizeof(phy_conf));
1850
1851         /* bits 0-2 use the values from get_phy_abilities_resp */
1852         abilities &= ~mask;
1853         abilities |= phy_ab.abilities & mask;
1854
1855         /* update ablities and speed */
1856         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1857                 phy_conf.link_speed = advt;
1858         else
1859                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1860
1861         phy_conf.abilities = abilities;
1862
1863
1864
1865         /* To enable link, phy_type mask needs to include each type */
1866         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1867                 phy_type_mask |= 1 << cnt;
1868
1869         /* use get_phy_abilities_resp value for the rest */
1870         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1871         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1872                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1873                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1874         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1875         phy_conf.eee_capability = phy_ab.eee_capability;
1876         phy_conf.eeer = phy_ab.eeer_val;
1877         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1878
1879         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1880                     phy_ab.abilities, phy_ab.link_speed);
1881         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1882                     phy_conf.abilities, phy_conf.link_speed);
1883
1884         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1885         if (status)
1886                 return ret;
1887
1888         return I40E_SUCCESS;
1889 }
1890
1891 static int
1892 i40e_apply_link_speed(struct rte_eth_dev *dev)
1893 {
1894         uint8_t speed;
1895         uint8_t abilities = 0;
1896         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897         struct rte_eth_conf *conf = &dev->data->dev_conf;
1898
1899         speed = i40e_parse_link_speeds(conf->link_speeds);
1900         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1901         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1902                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1903         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1904
1905         return i40e_phy_conf_link(hw, abilities, speed, true);
1906 }
1907
1908 static int
1909 i40e_dev_start(struct rte_eth_dev *dev)
1910 {
1911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct i40e_vsi *main_vsi = pf->main_vsi;
1914         int ret, i;
1915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1916         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1917         uint32_t intr_vector = 0;
1918         struct i40e_vsi *vsi;
1919
1920         hw->adapter_stopped = 0;
1921
1922         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1923                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1924                              dev->data->port_id);
1925                 return -EINVAL;
1926         }
1927
1928         rte_intr_disable(intr_handle);
1929
1930         if ((rte_intr_cap_multiple(intr_handle) ||
1931              !RTE_ETH_DEV_SRIOV(dev).active) &&
1932             dev->data->dev_conf.intr_conf.rxq != 0) {
1933                 intr_vector = dev->data->nb_rx_queues;
1934                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1935                 if (ret)
1936                         return ret;
1937         }
1938
1939         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1940                 intr_handle->intr_vec =
1941                         rte_zmalloc("intr_vec",
1942                                     dev->data->nb_rx_queues * sizeof(int),
1943                                     0);
1944                 if (!intr_handle->intr_vec) {
1945                         PMD_INIT_LOG(ERR,
1946                                 "Failed to allocate %d rx_queues intr_vec",
1947                                 dev->data->nb_rx_queues);
1948                         return -ENOMEM;
1949                 }
1950         }
1951
1952         /* Initialize VSI */
1953         ret = i40e_dev_rxtx_init(pf);
1954         if (ret != I40E_SUCCESS) {
1955                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1956                 goto err_up;
1957         }
1958
1959         /* Map queues with MSIX interrupt */
1960         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1961                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1962         i40e_vsi_queues_bind_intr(main_vsi);
1963         i40e_vsi_enable_queues_intr(main_vsi);
1964
1965         /* Map VMDQ VSI queues with MSIX interrupt */
1966         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1967                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1968                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1969                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1970         }
1971
1972         /* enable FDIR MSIX interrupt */
1973         if (pf->fdir.fdir_vsi) {
1974                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1975                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1976         }
1977
1978         /* Enable all queues which have been configured */
1979         ret = i40e_dev_switch_queues(pf, TRUE);
1980         if (ret != I40E_SUCCESS) {
1981                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1982                 goto err_up;
1983         }
1984
1985         /* Enable receiving broadcast packets */
1986         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1987         if (ret != I40E_SUCCESS)
1988                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1989
1990         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1991                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1992                                                 true, NULL);
1993                 if (ret != I40E_SUCCESS)
1994                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1995         }
1996
1997         /* Enable the VLAN promiscuous mode. */
1998         if (pf->vfs) {
1999                 for (i = 0; i < pf->vf_num; i++) {
2000                         vsi = pf->vfs[i].vsi;
2001                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2002                                                      true, NULL);
2003                 }
2004         }
2005
2006         /* Apply link configure */
2007         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2008                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2009                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2010                                 ETH_LINK_SPEED_40G)) {
2011                 PMD_DRV_LOG(ERR, "Invalid link setting");
2012                 goto err_up;
2013         }
2014         ret = i40e_apply_link_speed(dev);
2015         if (I40E_SUCCESS != ret) {
2016                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2017                 goto err_up;
2018         }
2019
2020         if (!rte_intr_allow_others(intr_handle)) {
2021                 rte_intr_callback_unregister(intr_handle,
2022                                              i40e_dev_interrupt_handler,
2023                                              (void *)dev);
2024                 /* configure and enable device interrupt */
2025                 i40e_pf_config_irq0(hw, FALSE);
2026                 i40e_pf_enable_irq0(hw);
2027
2028                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2029                         PMD_INIT_LOG(INFO,
2030                                 "lsc won't enable because of no intr multiplex");
2031         } else {
2032                 ret = i40e_aq_set_phy_int_mask(hw,
2033                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2034                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2035                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2036                 if (ret != I40E_SUCCESS)
2037                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2038
2039                 /* Call get_link_info aq commond to enable/disable LSE */
2040                 i40e_dev_link_update(dev, 0);
2041         }
2042
2043         /* enable uio intr after callback register */
2044         rte_intr_enable(intr_handle);
2045
2046         i40e_filter_restore(pf);
2047
2048         if (pf->tm_conf.root && !pf->tm_conf.committed)
2049                 PMD_DRV_LOG(WARNING,
2050                             "please call hierarchy_commit() "
2051                             "before starting the port");
2052
2053         return I40E_SUCCESS;
2054
2055 err_up:
2056         i40e_dev_switch_queues(pf, FALSE);
2057         i40e_dev_clear_queues(dev);
2058
2059         return ret;
2060 }
2061
2062 static void
2063 i40e_dev_stop(struct rte_eth_dev *dev)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067         struct i40e_vsi *main_vsi = pf->main_vsi;
2068         struct i40e_mirror_rule *p_mirror;
2069         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2070         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2071         int i;
2072
2073         if (hw->adapter_stopped == 1)
2074                 return;
2075         /* Disable all queues */
2076         i40e_dev_switch_queues(pf, FALSE);
2077
2078         /* un-map queues with interrupt registers */
2079         i40e_vsi_disable_queues_intr(main_vsi);
2080         i40e_vsi_queues_unbind_intr(main_vsi);
2081
2082         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2083                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2084                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2085         }
2086
2087         if (pf->fdir.fdir_vsi) {
2088                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2089                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2090         }
2091         /* Clear all queues and release memory */
2092         i40e_dev_clear_queues(dev);
2093
2094         /* Set link down */
2095         i40e_dev_set_link_down(dev);
2096
2097         /* Remove all mirror rules */
2098         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2099                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2100                 rte_free(p_mirror);
2101         }
2102         pf->nb_mirror_rule = 0;
2103
2104         if (!rte_intr_allow_others(intr_handle))
2105                 /* resume to the default handler */
2106                 rte_intr_callback_register(intr_handle,
2107                                            i40e_dev_interrupt_handler,
2108                                            (void *)dev);
2109
2110         /* Clean datapath event and queue/vec mapping */
2111         rte_intr_efd_disable(intr_handle);
2112         if (intr_handle->intr_vec) {
2113                 rte_free(intr_handle->intr_vec);
2114                 intr_handle->intr_vec = NULL;
2115         }
2116
2117         /* reset hierarchy commit */
2118         pf->tm_conf.committed = false;
2119
2120         hw->adapter_stopped = 1;
2121 }
2122
2123 static void
2124 i40e_dev_close(struct rte_eth_dev *dev)
2125 {
2126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2127         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2129         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2130         uint32_t reg;
2131         int i;
2132
2133         PMD_INIT_FUNC_TRACE();
2134
2135         i40e_dev_stop(dev);
2136         i40e_dev_free_queues(dev);
2137
2138         /* Disable interrupt */
2139         i40e_pf_disable_irq0(hw);
2140         rte_intr_disable(intr_handle);
2141
2142         /* shutdown and destroy the HMC */
2143         i40e_shutdown_lan_hmc(hw);
2144
2145         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2146                 i40e_vsi_release(pf->vmdq[i].vsi);
2147                 pf->vmdq[i].vsi = NULL;
2148         }
2149         rte_free(pf->vmdq);
2150         pf->vmdq = NULL;
2151
2152         /* release all the existing VSIs and VEBs */
2153         i40e_fdir_teardown(pf);
2154         i40e_vsi_release(pf->main_vsi);
2155
2156         /* shutdown the adminq */
2157         i40e_aq_queue_shutdown(hw, true);
2158         i40e_shutdown_adminq(hw);
2159
2160         i40e_res_pool_destroy(&pf->qp_pool);
2161         i40e_res_pool_destroy(&pf->msix_pool);
2162
2163         /* force a PF reset to clean anything leftover */
2164         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2165         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2166                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2167         I40E_WRITE_FLUSH(hw);
2168 }
2169
2170 /*
2171  * Reset PF device only to re-initialize resources in PMD layer
2172  */
2173 static int
2174 i40e_dev_reset(struct rte_eth_dev *dev)
2175 {
2176         int ret;
2177
2178         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2179          * its VF to make them align with it. The detailed notification
2180          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2181          * To avoid unexpected behavior in VF, currently reset of PF with
2182          * SR-IOV activation is not supported. It might be supported later.
2183          */
2184         if (dev->data->sriov.active)
2185                 return -ENOTSUP;
2186
2187         ret = eth_i40e_dev_uninit(dev);
2188         if (ret)
2189                 return ret;
2190
2191         ret = eth_i40e_dev_init(dev);
2192
2193         return ret;
2194 }
2195
2196 static void
2197 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2198 {
2199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2200         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201         struct i40e_vsi *vsi = pf->main_vsi;
2202         int status;
2203
2204         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2205                                                      true, NULL, true);
2206         if (status != I40E_SUCCESS)
2207                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2208
2209         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2210                                                         TRUE, NULL);
2211         if (status != I40E_SUCCESS)
2212                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2213
2214 }
2215
2216 static void
2217 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2218 {
2219         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221         struct i40e_vsi *vsi = pf->main_vsi;
2222         int status;
2223
2224         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2225                                                      false, NULL, true);
2226         if (status != I40E_SUCCESS)
2227                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2228
2229         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2230                                                         false, NULL);
2231         if (status != I40E_SUCCESS)
2232                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2233 }
2234
2235 static void
2236 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *vsi = pf->main_vsi;
2241         int ret;
2242
2243         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2244         if (ret != I40E_SUCCESS)
2245                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2246 }
2247
2248 static void
2249 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2250 {
2251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct i40e_vsi *vsi = pf->main_vsi;
2254         int ret;
2255
2256         if (dev->data->promiscuous == 1)
2257                 return; /* must remain in all_multicast mode */
2258
2259         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2260                                 vsi->seid, FALSE, NULL);
2261         if (ret != I40E_SUCCESS)
2262                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2263 }
2264
2265 /*
2266  * Set device link up.
2267  */
2268 static int
2269 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2270 {
2271         /* re-apply link speed setting */
2272         return i40e_apply_link_speed(dev);
2273 }
2274
2275 /*
2276  * Set device link down.
2277  */
2278 static int
2279 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2280 {
2281         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2282         uint8_t abilities = 0;
2283         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284
2285         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2286         return i40e_phy_conf_link(hw, abilities, speed, false);
2287 }
2288
2289 int
2290 i40e_dev_link_update(struct rte_eth_dev *dev,
2291                      int wait_to_complete)
2292 {
2293 #define CHECK_INTERVAL 100  /* 100ms */
2294 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2295         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct i40e_link_status link_status;
2297         struct rte_eth_link link, old;
2298         int status;
2299         unsigned rep_cnt = MAX_REPEAT_TIME;
2300         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2301
2302         memset(&link, 0, sizeof(link));
2303         memset(&old, 0, sizeof(old));
2304         memset(&link_status, 0, sizeof(link_status));
2305         rte_i40e_dev_atomic_read_link_status(dev, &old);
2306
2307         do {
2308                 /* Get link status information from hardware */
2309                 status = i40e_aq_get_link_info(hw, enable_lse,
2310                                                 &link_status, NULL);
2311                 if (status != I40E_SUCCESS) {
2312                         link.link_speed = ETH_SPEED_NUM_100M;
2313                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2314                         PMD_DRV_LOG(ERR, "Failed to get link info");
2315                         goto out;
2316                 }
2317
2318                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2319                 if (!wait_to_complete || link.link_status)
2320                         break;
2321
2322                 rte_delay_ms(CHECK_INTERVAL);
2323         } while (--rep_cnt);
2324
2325         if (!link.link_status)
2326                 goto out;
2327
2328         /* i40e uses full duplex only */
2329         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2330
2331         /* Parse the link status */
2332         switch (link_status.link_speed) {
2333         case I40E_LINK_SPEED_100MB:
2334                 link.link_speed = ETH_SPEED_NUM_100M;
2335                 break;
2336         case I40E_LINK_SPEED_1GB:
2337                 link.link_speed = ETH_SPEED_NUM_1G;
2338                 break;
2339         case I40E_LINK_SPEED_10GB:
2340                 link.link_speed = ETH_SPEED_NUM_10G;
2341                 break;
2342         case I40E_LINK_SPEED_20GB:
2343                 link.link_speed = ETH_SPEED_NUM_20G;
2344                 break;
2345         case I40E_LINK_SPEED_25GB:
2346                 link.link_speed = ETH_SPEED_NUM_25G;
2347                 break;
2348         case I40E_LINK_SPEED_40GB:
2349                 link.link_speed = ETH_SPEED_NUM_40G;
2350                 break;
2351         default:
2352                 link.link_speed = ETH_SPEED_NUM_100M;
2353                 break;
2354         }
2355
2356         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2357                         ETH_LINK_SPEED_FIXED);
2358
2359 out:
2360         rte_i40e_dev_atomic_write_link_status(dev, &link);
2361         if (link.link_status == old.link_status)
2362                 return -1;
2363
2364         i40e_notify_all_vfs_link_status(dev);
2365
2366         return 0;
2367 }
2368
2369 /* Get all the statistics of a VSI */
2370 void
2371 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2372 {
2373         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2374         struct i40e_eth_stats *nes = &vsi->eth_stats;
2375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2376         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2377
2378         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2379                             vsi->offset_loaded, &oes->rx_bytes,
2380                             &nes->rx_bytes);
2381         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2382                             vsi->offset_loaded, &oes->rx_unicast,
2383                             &nes->rx_unicast);
2384         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2385                             vsi->offset_loaded, &oes->rx_multicast,
2386                             &nes->rx_multicast);
2387         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2388                             vsi->offset_loaded, &oes->rx_broadcast,
2389                             &nes->rx_broadcast);
2390         /* exclude CRC bytes */
2391         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2392                 nes->rx_broadcast) * ETHER_CRC_LEN;
2393
2394         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2395                             &oes->rx_discards, &nes->rx_discards);
2396         /* GLV_REPC not supported */
2397         /* GLV_RMPC not supported */
2398         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2399                             &oes->rx_unknown_protocol,
2400                             &nes->rx_unknown_protocol);
2401         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2402                             vsi->offset_loaded, &oes->tx_bytes,
2403                             &nes->tx_bytes);
2404         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2405                             vsi->offset_loaded, &oes->tx_unicast,
2406                             &nes->tx_unicast);
2407         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2408                             vsi->offset_loaded, &oes->tx_multicast,
2409                             &nes->tx_multicast);
2410         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2411                             vsi->offset_loaded,  &oes->tx_broadcast,
2412                             &nes->tx_broadcast);
2413         /* GLV_TDPC not supported */
2414         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2415                             &oes->tx_errors, &nes->tx_errors);
2416         vsi->offset_loaded = true;
2417
2418         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2419                     vsi->vsi_id);
2420         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2421         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2422         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2423         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2424         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2425         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2426                     nes->rx_unknown_protocol);
2427         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2428         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2429         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2430         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2431         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2432         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2433         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2434                     vsi->vsi_id);
2435 }
2436
2437 static void
2438 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2439 {
2440         unsigned int i;
2441         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2442         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2443
2444         /* Get rx/tx bytes of internal transfer packets */
2445         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2446                         I40E_GLV_GORCL(hw->port),
2447                         pf->offset_loaded,
2448                         &pf->internal_stats_offset.rx_bytes,
2449                         &pf->internal_stats.rx_bytes);
2450
2451         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2452                         I40E_GLV_GOTCL(hw->port),
2453                         pf->offset_loaded,
2454                         &pf->internal_stats_offset.tx_bytes,
2455                         &pf->internal_stats.tx_bytes);
2456         /* Get total internal rx packet count */
2457         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2458                             I40E_GLV_UPRCL(hw->port),
2459                             pf->offset_loaded,
2460                             &pf->internal_stats_offset.rx_unicast,
2461                             &pf->internal_stats.rx_unicast);
2462         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2463                             I40E_GLV_MPRCL(hw->port),
2464                             pf->offset_loaded,
2465                             &pf->internal_stats_offset.rx_multicast,
2466                             &pf->internal_stats.rx_multicast);
2467         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2468                             I40E_GLV_BPRCL(hw->port),
2469                             pf->offset_loaded,
2470                             &pf->internal_stats_offset.rx_broadcast,
2471                             &pf->internal_stats.rx_broadcast);
2472
2473         /* exclude CRC size */
2474         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2475                 pf->internal_stats.rx_multicast +
2476                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2477
2478         /* Get statistics of struct i40e_eth_stats */
2479         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2480                             I40E_GLPRT_GORCL(hw->port),
2481                             pf->offset_loaded, &os->eth.rx_bytes,
2482                             &ns->eth.rx_bytes);
2483         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2484                             I40E_GLPRT_UPRCL(hw->port),
2485                             pf->offset_loaded, &os->eth.rx_unicast,
2486                             &ns->eth.rx_unicast);
2487         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2488                             I40E_GLPRT_MPRCL(hw->port),
2489                             pf->offset_loaded, &os->eth.rx_multicast,
2490                             &ns->eth.rx_multicast);
2491         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2492                             I40E_GLPRT_BPRCL(hw->port),
2493                             pf->offset_loaded, &os->eth.rx_broadcast,
2494                             &ns->eth.rx_broadcast);
2495         /* Workaround: CRC size should not be included in byte statistics,
2496          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2497          */
2498         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2499                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2500
2501         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2502          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2503          * value.
2504          */
2505         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2506                 ns->eth.rx_bytes = 0;
2507         /* exlude internal rx bytes */
2508         else
2509                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2510
2511         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2512                             pf->offset_loaded, &os->eth.rx_discards,
2513                             &ns->eth.rx_discards);
2514         /* GLPRT_REPC not supported */
2515         /* GLPRT_RMPC not supported */
2516         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2517                             pf->offset_loaded,
2518                             &os->eth.rx_unknown_protocol,
2519                             &ns->eth.rx_unknown_protocol);
2520         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2521                             I40E_GLPRT_GOTCL(hw->port),
2522                             pf->offset_loaded, &os->eth.tx_bytes,
2523                             &ns->eth.tx_bytes);
2524         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2525                             I40E_GLPRT_UPTCL(hw->port),
2526                             pf->offset_loaded, &os->eth.tx_unicast,
2527                             &ns->eth.tx_unicast);
2528         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2529                             I40E_GLPRT_MPTCL(hw->port),
2530                             pf->offset_loaded, &os->eth.tx_multicast,
2531                             &ns->eth.tx_multicast);
2532         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2533                             I40E_GLPRT_BPTCL(hw->port),
2534                             pf->offset_loaded, &os->eth.tx_broadcast,
2535                             &ns->eth.tx_broadcast);
2536         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2537                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2538
2539         /* exclude internal tx bytes */
2540         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2541                 ns->eth.tx_bytes = 0;
2542         else
2543                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2544
2545         /* GLPRT_TEPC not supported */
2546
2547         /* additional port specific stats */
2548         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2549                             pf->offset_loaded, &os->tx_dropped_link_down,
2550                             &ns->tx_dropped_link_down);
2551         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2552                             pf->offset_loaded, &os->crc_errors,
2553                             &ns->crc_errors);
2554         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2555                             pf->offset_loaded, &os->illegal_bytes,
2556                             &ns->illegal_bytes);
2557         /* GLPRT_ERRBC not supported */
2558         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2559                             pf->offset_loaded, &os->mac_local_faults,
2560                             &ns->mac_local_faults);
2561         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2562                             pf->offset_loaded, &os->mac_remote_faults,
2563                             &ns->mac_remote_faults);
2564         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2565                             pf->offset_loaded, &os->rx_length_errors,
2566                             &ns->rx_length_errors);
2567         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2568                             pf->offset_loaded, &os->link_xon_rx,
2569                             &ns->link_xon_rx);
2570         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2571                             pf->offset_loaded, &os->link_xoff_rx,
2572                             &ns->link_xoff_rx);
2573         for (i = 0; i < 8; i++) {
2574                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2575                                     pf->offset_loaded,
2576                                     &os->priority_xon_rx[i],
2577                                     &ns->priority_xon_rx[i]);
2578                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2579                                     pf->offset_loaded,
2580                                     &os->priority_xoff_rx[i],
2581                                     &ns->priority_xoff_rx[i]);
2582         }
2583         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2584                             pf->offset_loaded, &os->link_xon_tx,
2585                             &ns->link_xon_tx);
2586         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2587                             pf->offset_loaded, &os->link_xoff_tx,
2588                             &ns->link_xoff_tx);
2589         for (i = 0; i < 8; i++) {
2590                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2591                                     pf->offset_loaded,
2592                                     &os->priority_xon_tx[i],
2593                                     &ns->priority_xon_tx[i]);
2594                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2595                                     pf->offset_loaded,
2596                                     &os->priority_xoff_tx[i],
2597                                     &ns->priority_xoff_tx[i]);
2598                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2599                                     pf->offset_loaded,
2600                                     &os->priority_xon_2_xoff[i],
2601                                     &ns->priority_xon_2_xoff[i]);
2602         }
2603         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2604                             I40E_GLPRT_PRC64L(hw->port),
2605                             pf->offset_loaded, &os->rx_size_64,
2606                             &ns->rx_size_64);
2607         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2608                             I40E_GLPRT_PRC127L(hw->port),
2609                             pf->offset_loaded, &os->rx_size_127,
2610                             &ns->rx_size_127);
2611         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2612                             I40E_GLPRT_PRC255L(hw->port),
2613                             pf->offset_loaded, &os->rx_size_255,
2614                             &ns->rx_size_255);
2615         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2616                             I40E_GLPRT_PRC511L(hw->port),
2617                             pf->offset_loaded, &os->rx_size_511,
2618                             &ns->rx_size_511);
2619         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2620                             I40E_GLPRT_PRC1023L(hw->port),
2621                             pf->offset_loaded, &os->rx_size_1023,
2622                             &ns->rx_size_1023);
2623         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2624                             I40E_GLPRT_PRC1522L(hw->port),
2625                             pf->offset_loaded, &os->rx_size_1522,
2626                             &ns->rx_size_1522);
2627         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2628                             I40E_GLPRT_PRC9522L(hw->port),
2629                             pf->offset_loaded, &os->rx_size_big,
2630                             &ns->rx_size_big);
2631         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2632                             pf->offset_loaded, &os->rx_undersize,
2633                             &ns->rx_undersize);
2634         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2635                             pf->offset_loaded, &os->rx_fragments,
2636                             &ns->rx_fragments);
2637         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2638                             pf->offset_loaded, &os->rx_oversize,
2639                             &ns->rx_oversize);
2640         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2641                             pf->offset_loaded, &os->rx_jabber,
2642                             &ns->rx_jabber);
2643         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2644                             I40E_GLPRT_PTC64L(hw->port),
2645                             pf->offset_loaded, &os->tx_size_64,
2646                             &ns->tx_size_64);
2647         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2648                             I40E_GLPRT_PTC127L(hw->port),
2649                             pf->offset_loaded, &os->tx_size_127,
2650                             &ns->tx_size_127);
2651         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2652                             I40E_GLPRT_PTC255L(hw->port),
2653                             pf->offset_loaded, &os->tx_size_255,
2654                             &ns->tx_size_255);
2655         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2656                             I40E_GLPRT_PTC511L(hw->port),
2657                             pf->offset_loaded, &os->tx_size_511,
2658                             &ns->tx_size_511);
2659         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2660                             I40E_GLPRT_PTC1023L(hw->port),
2661                             pf->offset_loaded, &os->tx_size_1023,
2662                             &ns->tx_size_1023);
2663         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2664                             I40E_GLPRT_PTC1522L(hw->port),
2665                             pf->offset_loaded, &os->tx_size_1522,
2666                             &ns->tx_size_1522);
2667         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2668                             I40E_GLPRT_PTC9522L(hw->port),
2669                             pf->offset_loaded, &os->tx_size_big,
2670                             &ns->tx_size_big);
2671         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2672                            pf->offset_loaded,
2673                            &os->fd_sb_match, &ns->fd_sb_match);
2674         /* GLPRT_MSPDC not supported */
2675         /* GLPRT_XEC not supported */
2676
2677         pf->offset_loaded = true;
2678
2679         if (pf->main_vsi)
2680                 i40e_update_vsi_stats(pf->main_vsi);
2681 }
2682
2683 /* Get all statistics of a port */
2684 static void
2685 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2690         unsigned i;
2691
2692         /* call read registers - updates values, now write them to struct */
2693         i40e_read_stats_registers(pf, hw);
2694
2695         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2696                         pf->main_vsi->eth_stats.rx_multicast +
2697                         pf->main_vsi->eth_stats.rx_broadcast -
2698                         pf->main_vsi->eth_stats.rx_discards;
2699         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2700                         pf->main_vsi->eth_stats.tx_multicast +
2701                         pf->main_vsi->eth_stats.tx_broadcast;
2702         stats->ibytes   = ns->eth.rx_bytes;
2703         stats->obytes   = ns->eth.tx_bytes;
2704         stats->oerrors  = ns->eth.tx_errors +
2705                         pf->main_vsi->eth_stats.tx_errors;
2706
2707         /* Rx Errors */
2708         stats->imissed  = ns->eth.rx_discards +
2709                         pf->main_vsi->eth_stats.rx_discards;
2710         stats->ierrors  = ns->crc_errors +
2711                         ns->rx_length_errors + ns->rx_undersize +
2712                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2713
2714         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2715         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2716         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2717         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2718         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2719         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2720         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2721                     ns->eth.rx_unknown_protocol);
2722         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2723         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2724         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2725         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2726         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2727         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2728
2729         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2730                     ns->tx_dropped_link_down);
2731         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2732         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2733                     ns->illegal_bytes);
2734         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2735         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2736                     ns->mac_local_faults);
2737         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2738                     ns->mac_remote_faults);
2739         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2740                     ns->rx_length_errors);
2741         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2742         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2743         for (i = 0; i < 8; i++) {
2744                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2745                                 i, ns->priority_xon_rx[i]);
2746                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2747                                 i, ns->priority_xoff_rx[i]);
2748         }
2749         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2750         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2751         for (i = 0; i < 8; i++) {
2752                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2753                                 i, ns->priority_xon_tx[i]);
2754                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2755                                 i, ns->priority_xoff_tx[i]);
2756                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2757                                 i, ns->priority_xon_2_xoff[i]);
2758         }
2759         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2760         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2761         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2762         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2763         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2764         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2765         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2766         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2767         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2768         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2769         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2770         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2771         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2772         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2773         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2774         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2775         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2776         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2777         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2778                         ns->mac_short_packet_dropped);
2779         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2780                     ns->checksum_error);
2781         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2782         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2783 }
2784
2785 /* Reset the statistics */
2786 static void
2787 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2788 {
2789         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791
2792         /* Mark PF and VSI stats to update the offset, aka "reset" */
2793         pf->offset_loaded = false;
2794         if (pf->main_vsi)
2795                 pf->main_vsi->offset_loaded = false;
2796
2797         /* read the stats, reading current register values into offset */
2798         i40e_read_stats_registers(pf, hw);
2799 }
2800
2801 static uint32_t
2802 i40e_xstats_calc_num(void)
2803 {
2804         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2805                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2806                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2807 }
2808
2809 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2810                                      struct rte_eth_xstat_name *xstats_names,
2811                                      __rte_unused unsigned limit)
2812 {
2813         unsigned count = 0;
2814         unsigned i, prio;
2815
2816         if (xstats_names == NULL)
2817                 return i40e_xstats_calc_num();
2818
2819         /* Note: limit checked in rte_eth_xstats_names() */
2820
2821         /* Get stats from i40e_eth_stats struct */
2822         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2823                 snprintf(xstats_names[count].name,
2824                          sizeof(xstats_names[count].name),
2825                          "%s", rte_i40e_stats_strings[i].name);
2826                 count++;
2827         }
2828
2829         /* Get individiual stats from i40e_hw_port struct */
2830         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2831                 snprintf(xstats_names[count].name,
2832                         sizeof(xstats_names[count].name),
2833                          "%s", rte_i40e_hw_port_strings[i].name);
2834                 count++;
2835         }
2836
2837         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2838                 for (prio = 0; prio < 8; prio++) {
2839                         snprintf(xstats_names[count].name,
2840                                  sizeof(xstats_names[count].name),
2841                                  "rx_priority%u_%s", prio,
2842                                  rte_i40e_rxq_prio_strings[i].name);
2843                         count++;
2844                 }
2845         }
2846
2847         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2848                 for (prio = 0; prio < 8; prio++) {
2849                         snprintf(xstats_names[count].name,
2850                                  sizeof(xstats_names[count].name),
2851                                  "tx_priority%u_%s", prio,
2852                                  rte_i40e_txq_prio_strings[i].name);
2853                         count++;
2854                 }
2855         }
2856         return count;
2857 }
2858
2859 static int
2860 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2861                     unsigned n)
2862 {
2863         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2864         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         unsigned i, count, prio;
2866         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2867
2868         count = i40e_xstats_calc_num();
2869         if (n < count)
2870                 return count;
2871
2872         i40e_read_stats_registers(pf, hw);
2873
2874         if (xstats == NULL)
2875                 return 0;
2876
2877         count = 0;
2878
2879         /* Get stats from i40e_eth_stats struct */
2880         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2881                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2882                         rte_i40e_stats_strings[i].offset);
2883                 xstats[count].id = count;
2884                 count++;
2885         }
2886
2887         /* Get individiual stats from i40e_hw_port struct */
2888         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2889                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2890                         rte_i40e_hw_port_strings[i].offset);
2891                 xstats[count].id = count;
2892                 count++;
2893         }
2894
2895         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2896                 for (prio = 0; prio < 8; prio++) {
2897                         xstats[count].value =
2898                                 *(uint64_t *)(((char *)hw_stats) +
2899                                 rte_i40e_rxq_prio_strings[i].offset +
2900                                 (sizeof(uint64_t) * prio));
2901                         xstats[count].id = count;
2902                         count++;
2903                 }
2904         }
2905
2906         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2907                 for (prio = 0; prio < 8; prio++) {
2908                         xstats[count].value =
2909                                 *(uint64_t *)(((char *)hw_stats) +
2910                                 rte_i40e_txq_prio_strings[i].offset +
2911                                 (sizeof(uint64_t) * prio));
2912                         xstats[count].id = count;
2913                         count++;
2914                 }
2915         }
2916
2917         return count;
2918 }
2919
2920 static int
2921 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2922                                  __rte_unused uint16_t queue_id,
2923                                  __rte_unused uint8_t stat_idx,
2924                                  __rte_unused uint8_t is_rx)
2925 {
2926         PMD_INIT_FUNC_TRACE();
2927
2928         return -ENOSYS;
2929 }
2930
2931 static int
2932 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2933 {
2934         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2935         u32 full_ver;
2936         u8 ver, patch;
2937         u16 build;
2938         int ret;
2939
2940         full_ver = hw->nvm.oem_ver;
2941         ver = (u8)(full_ver >> 24);
2942         build = (u16)((full_ver >> 8) & 0xffff);
2943         patch = (u8)(full_ver & 0xff);
2944
2945         ret = snprintf(fw_version, fw_size,
2946                  "%d.%d%d 0x%08x %d.%d.%d",
2947                  ((hw->nvm.version >> 12) & 0xf),
2948                  ((hw->nvm.version >> 4) & 0xff),
2949                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2950                  ver, build, patch);
2951
2952         ret += 1; /* add the size of '\0' */
2953         if (fw_size < (u32)ret)
2954                 return ret;
2955         else
2956                 return 0;
2957 }
2958
2959 static void
2960 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2961 {
2962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         struct i40e_vsi *vsi = pf->main_vsi;
2965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2966
2967         dev_info->pci_dev = pci_dev;
2968         dev_info->max_rx_queues = vsi->nb_qps;
2969         dev_info->max_tx_queues = vsi->nb_qps;
2970         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2971         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2972         dev_info->max_mac_addrs = vsi->max_macaddrs;
2973         dev_info->max_vfs = pci_dev->max_vfs;
2974         dev_info->rx_offload_capa =
2975                 DEV_RX_OFFLOAD_VLAN_STRIP |
2976                 DEV_RX_OFFLOAD_QINQ_STRIP |
2977                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2978                 DEV_RX_OFFLOAD_UDP_CKSUM |
2979                 DEV_RX_OFFLOAD_TCP_CKSUM;
2980         dev_info->tx_offload_capa =
2981                 DEV_TX_OFFLOAD_VLAN_INSERT |
2982                 DEV_TX_OFFLOAD_QINQ_INSERT |
2983                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2984                 DEV_TX_OFFLOAD_UDP_CKSUM |
2985                 DEV_TX_OFFLOAD_TCP_CKSUM |
2986                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2987                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2988                 DEV_TX_OFFLOAD_TCP_TSO |
2989                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2990                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2991                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2992                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2993         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2994                                                 sizeof(uint32_t);
2995         dev_info->reta_size = pf->hash_lut_size;
2996         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2997
2998         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2999                 .rx_thresh = {
3000                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3001                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3002                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3003                 },
3004                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3005                 .rx_drop_en = 0,
3006         };
3007
3008         dev_info->default_txconf = (struct rte_eth_txconf) {
3009                 .tx_thresh = {
3010                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3011                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3012                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3013                 },
3014                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3015                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3016                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3017                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3018         };
3019
3020         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3021                 .nb_max = I40E_MAX_RING_DESC,
3022                 .nb_min = I40E_MIN_RING_DESC,
3023                 .nb_align = I40E_ALIGN_RING_DESC,
3024         };
3025
3026         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3027                 .nb_max = I40E_MAX_RING_DESC,
3028                 .nb_min = I40E_MIN_RING_DESC,
3029                 .nb_align = I40E_ALIGN_RING_DESC,
3030                 .nb_seg_max = I40E_TX_MAX_SEG,
3031                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3032         };
3033
3034         if (pf->flags & I40E_FLAG_VMDQ) {
3035                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3036                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3037                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3038                                                 pf->max_nb_vmdq_vsi;
3039                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3040                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3041                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3042         }
3043
3044         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3045                 /* For XL710 */
3046                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3047         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3048                 /* For XXV710 */
3049                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3050         else
3051                 /* For X710 */
3052                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3053 }
3054
3055 static int
3056 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3057 {
3058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3059         struct i40e_vsi *vsi = pf->main_vsi;
3060         PMD_INIT_FUNC_TRACE();
3061
3062         if (on)
3063                 return i40e_vsi_add_vlan(vsi, vlan_id);
3064         else
3065                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3066 }
3067
3068 static int
3069 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3070                                 enum rte_vlan_type vlan_type,
3071                                 uint16_t tpid, int qinq)
3072 {
3073         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074         uint64_t reg_r = 0;
3075         uint64_t reg_w = 0;
3076         uint16_t reg_id = 3;
3077         int ret;
3078
3079         if (qinq) {
3080                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3081                         reg_id = 2;
3082         }
3083
3084         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3085                                           &reg_r, NULL);
3086         if (ret != I40E_SUCCESS) {
3087                 PMD_DRV_LOG(ERR,
3088                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3089                            reg_id);
3090                 return -EIO;
3091         }
3092         PMD_DRV_LOG(DEBUG,
3093                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3094                     reg_id, reg_r);
3095
3096         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3097         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3098         if (reg_r == reg_w) {
3099                 PMD_DRV_LOG(DEBUG, "No need to write");
3100                 return 0;
3101         }
3102
3103         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3104                                            reg_w, NULL);
3105         if (ret != I40E_SUCCESS) {
3106                 PMD_DRV_LOG(ERR,
3107                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3108                             reg_id);
3109                 return -EIO;
3110         }
3111         PMD_DRV_LOG(DEBUG,
3112                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3113                     reg_w, reg_id);
3114
3115         return 0;
3116 }
3117
3118 static int
3119 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3120                    enum rte_vlan_type vlan_type,
3121                    uint16_t tpid)
3122 {
3123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3125         int ret = 0;
3126
3127         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3128              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3129             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3130                 PMD_DRV_LOG(ERR,
3131                             "Unsupported vlan type.");
3132                 return -EINVAL;
3133         }
3134         /* 802.1ad frames ability is added in NVM API 1.7*/
3135         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3136                 if (qinq) {
3137                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3138                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3139                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3140                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3141                 } else {
3142                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3143                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3144                 }
3145                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3146                 if (ret != I40E_SUCCESS) {
3147                         PMD_DRV_LOG(ERR,
3148                                     "Set switch config failed aq_err: %d",
3149                                     hw->aq.asq_last_status);
3150                         ret = -EIO;
3151                 }
3152         } else
3153                 /* If NVM API < 1.7, keep the register setting */
3154                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3155                                                       tpid, qinq);
3156
3157         return ret;
3158 }
3159
3160 static void
3161 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3162 {
3163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3164         struct i40e_vsi *vsi = pf->main_vsi;
3165
3166         if (mask & ETH_VLAN_FILTER_MASK) {
3167                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3168                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3169                 else
3170                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3171         }
3172
3173         if (mask & ETH_VLAN_STRIP_MASK) {
3174                 /* Enable or disable VLAN stripping */
3175                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3176                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3177                 else
3178                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3179         }
3180
3181         if (mask & ETH_VLAN_EXTEND_MASK) {
3182                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3183                         i40e_vsi_config_double_vlan(vsi, TRUE);
3184                         /* Set global registers with default ethertype. */
3185                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3186                                            ETHER_TYPE_VLAN);
3187                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3188                                            ETHER_TYPE_VLAN);
3189                 }
3190                 else
3191                         i40e_vsi_config_double_vlan(vsi, FALSE);
3192         }
3193 }
3194
3195 static void
3196 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3197                           __rte_unused uint16_t queue,
3198                           __rte_unused int on)
3199 {
3200         PMD_INIT_FUNC_TRACE();
3201 }
3202
3203 static int
3204 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3205 {
3206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3207         struct i40e_vsi *vsi = pf->main_vsi;
3208         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3209         struct i40e_vsi_vlan_pvid_info info;
3210
3211         memset(&info, 0, sizeof(info));
3212         info.on = on;
3213         if (info.on)
3214                 info.config.pvid = pvid;
3215         else {
3216                 info.config.reject.tagged =
3217                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3218                 info.config.reject.untagged =
3219                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3220         }
3221
3222         return i40e_vsi_vlan_pvid_set(vsi, &info);
3223 }
3224
3225 static int
3226 i40e_dev_led_on(struct rte_eth_dev *dev)
3227 {
3228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         uint32_t mode = i40e_led_get(hw);
3230
3231         if (mode == 0)
3232                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3233
3234         return 0;
3235 }
3236
3237 static int
3238 i40e_dev_led_off(struct rte_eth_dev *dev)
3239 {
3240         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241         uint32_t mode = i40e_led_get(hw);
3242
3243         if (mode != 0)
3244                 i40e_led_set(hw, 0, false);
3245
3246         return 0;
3247 }
3248
3249 static int
3250 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3251 {
3252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254
3255         fc_conf->pause_time = pf->fc_conf.pause_time;
3256         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3257         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3258
3259          /* Return current mode according to actual setting*/
3260         switch (hw->fc.current_mode) {
3261         case I40E_FC_FULL:
3262                 fc_conf->mode = RTE_FC_FULL;
3263                 break;
3264         case I40E_FC_TX_PAUSE:
3265                 fc_conf->mode = RTE_FC_TX_PAUSE;
3266                 break;
3267         case I40E_FC_RX_PAUSE:
3268                 fc_conf->mode = RTE_FC_RX_PAUSE;
3269                 break;
3270         case I40E_FC_NONE:
3271         default:
3272                 fc_conf->mode = RTE_FC_NONE;
3273         };
3274
3275         return 0;
3276 }
3277
3278 static int
3279 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3280 {
3281         uint32_t mflcn_reg, fctrl_reg, reg;
3282         uint32_t max_high_water;
3283         uint8_t i, aq_failure;
3284         int err;
3285         struct i40e_hw *hw;
3286         struct i40e_pf *pf;
3287         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3288                 [RTE_FC_NONE] = I40E_FC_NONE,
3289                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3290                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3291                 [RTE_FC_FULL] = I40E_FC_FULL
3292         };
3293
3294         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3295
3296         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3297         if ((fc_conf->high_water > max_high_water) ||
3298                         (fc_conf->high_water < fc_conf->low_water)) {
3299                 PMD_INIT_LOG(ERR,
3300                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3301                         max_high_water);
3302                 return -EINVAL;
3303         }
3304
3305         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3307         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3308
3309         pf->fc_conf.pause_time = fc_conf->pause_time;
3310         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3311         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3312
3313         PMD_INIT_FUNC_TRACE();
3314
3315         /* All the link flow control related enable/disable register
3316          * configuration is handle by the F/W
3317          */
3318         err = i40e_set_fc(hw, &aq_failure, true);
3319         if (err < 0)
3320                 return -ENOSYS;
3321
3322         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3323                 /* Configure flow control refresh threshold,
3324                  * the value for stat_tx_pause_refresh_timer[8]
3325                  * is used for global pause operation.
3326                  */
3327
3328                 I40E_WRITE_REG(hw,
3329                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3330                                pf->fc_conf.pause_time);
3331
3332                 /* configure the timer value included in transmitted pause
3333                  * frame,
3334                  * the value for stat_tx_pause_quanta[8] is used for global
3335                  * pause operation
3336                  */
3337                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3338                                pf->fc_conf.pause_time);
3339
3340                 fctrl_reg = I40E_READ_REG(hw,
3341                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3342
3343                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3344                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3345                 else
3346                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3347
3348                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3349                                fctrl_reg);
3350         } else {
3351                 /* Configure pause time (2 TCs per register) */
3352                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3353                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3354                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3355
3356                 /* Configure flow control refresh threshold value */
3357                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3358                                pf->fc_conf.pause_time / 2);
3359
3360                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3361
3362                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3363                  *depending on configuration
3364                  */
3365                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3366                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3367                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3368                 } else {
3369                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3370                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3371                 }
3372
3373                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3374         }
3375
3376         /* config the water marker both based on the packets and bytes */
3377         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3378                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3379                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3380         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3381                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3382                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3383         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3384                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3385                        << I40E_KILOSHIFT);
3386         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3387                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3388                        << I40E_KILOSHIFT);
3389
3390         I40E_WRITE_FLUSH(hw);
3391
3392         return 0;
3393 }
3394
3395 static int
3396 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3397                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3398 {
3399         PMD_INIT_FUNC_TRACE();
3400
3401         return -ENOSYS;
3402 }
3403
3404 /* Add a MAC address, and update filters */
3405 static int
3406 i40e_macaddr_add(struct rte_eth_dev *dev,
3407                  struct ether_addr *mac_addr,
3408                  __rte_unused uint32_t index,
3409                  uint32_t pool)
3410 {
3411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3412         struct i40e_mac_filter_info mac_filter;
3413         struct i40e_vsi *vsi;
3414         int ret;
3415
3416         /* If VMDQ not enabled or configured, return */
3417         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3418                           !pf->nb_cfg_vmdq_vsi)) {
3419                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3420                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3421                         pool);
3422                 return -ENOTSUP;
3423         }
3424
3425         if (pool > pf->nb_cfg_vmdq_vsi) {
3426                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3427                                 pool, pf->nb_cfg_vmdq_vsi);
3428                 return -EINVAL;
3429         }
3430
3431         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3432         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3433                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3434         else
3435                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3436
3437         if (pool == 0)
3438                 vsi = pf->main_vsi;
3439         else
3440                 vsi = pf->vmdq[pool - 1].vsi;
3441
3442         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3443         if (ret != I40E_SUCCESS) {
3444                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3445                 return -ENODEV;
3446         }
3447         return 0;
3448 }
3449
3450 /* Remove a MAC address, and update filters */
3451 static void
3452 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3453 {
3454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3455         struct i40e_vsi *vsi;
3456         struct rte_eth_dev_data *data = dev->data;
3457         struct ether_addr *macaddr;
3458         int ret;
3459         uint32_t i;
3460         uint64_t pool_sel;
3461
3462         macaddr = &(data->mac_addrs[index]);
3463
3464         pool_sel = dev->data->mac_pool_sel[index];
3465
3466         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3467                 if (pool_sel & (1ULL << i)) {
3468                         if (i == 0)
3469                                 vsi = pf->main_vsi;
3470                         else {
3471                                 /* No VMDQ pool enabled or configured */
3472                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3473                                         (i > pf->nb_cfg_vmdq_vsi)) {
3474                                         PMD_DRV_LOG(ERR,
3475                                                 "No VMDQ pool enabled/configured");
3476                                         return;
3477                                 }
3478                                 vsi = pf->vmdq[i - 1].vsi;
3479                         }
3480                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3481
3482                         if (ret) {
3483                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3484                                 return;
3485                         }
3486                 }
3487         }
3488 }
3489
3490 /* Set perfect match or hash match of MAC and VLAN for a VF */
3491 static int
3492 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3493                  struct rte_eth_mac_filter *filter,
3494                  bool add)
3495 {
3496         struct i40e_hw *hw;
3497         struct i40e_mac_filter_info mac_filter;
3498         struct ether_addr old_mac;
3499         struct ether_addr *new_mac;
3500         struct i40e_pf_vf *vf = NULL;
3501         uint16_t vf_id;
3502         int ret;
3503
3504         if (pf == NULL) {
3505                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3506                 return -EINVAL;
3507         }
3508         hw = I40E_PF_TO_HW(pf);
3509
3510         if (filter == NULL) {
3511                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3512                 return -EINVAL;
3513         }
3514
3515         new_mac = &filter->mac_addr;
3516
3517         if (is_zero_ether_addr(new_mac)) {
3518                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3519                 return -EINVAL;
3520         }
3521
3522         vf_id = filter->dst_id;
3523
3524         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3525                 PMD_DRV_LOG(ERR, "Invalid argument.");
3526                 return -EINVAL;
3527         }
3528         vf = &pf->vfs[vf_id];
3529
3530         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3531                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3532                 return -EINVAL;
3533         }
3534
3535         if (add) {
3536                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3537                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3538                                 ETHER_ADDR_LEN);
3539                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3540                                  ETHER_ADDR_LEN);
3541
3542                 mac_filter.filter_type = filter->filter_type;
3543                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3544                 if (ret != I40E_SUCCESS) {
3545                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3546                         return -1;
3547                 }
3548                 ether_addr_copy(new_mac, &pf->dev_addr);
3549         } else {
3550                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3551                                 ETHER_ADDR_LEN);
3552                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3553                 if (ret != I40E_SUCCESS) {
3554                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3555                         return -1;
3556                 }
3557
3558                 /* Clear device address as it has been removed */
3559                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3560                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3561         }
3562
3563         return 0;
3564 }
3565
3566 /* MAC filter handle */
3567 static int
3568 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3569                 void *arg)
3570 {
3571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3572         struct rte_eth_mac_filter *filter;
3573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3574         int ret = I40E_NOT_SUPPORTED;
3575
3576         filter = (struct rte_eth_mac_filter *)(arg);
3577
3578         switch (filter_op) {
3579         case RTE_ETH_FILTER_NOP:
3580                 ret = I40E_SUCCESS;
3581                 break;
3582         case RTE_ETH_FILTER_ADD:
3583                 i40e_pf_disable_irq0(hw);
3584                 if (filter->is_vf)
3585                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3586                 i40e_pf_enable_irq0(hw);
3587                 break;
3588         case RTE_ETH_FILTER_DELETE:
3589                 i40e_pf_disable_irq0(hw);
3590                 if (filter->is_vf)
3591                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3592                 i40e_pf_enable_irq0(hw);
3593                 break;
3594         default:
3595                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3596                 ret = I40E_ERR_PARAM;
3597                 break;
3598         }
3599
3600         return ret;
3601 }
3602
3603 static int
3604 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3605 {
3606         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3607         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3608         int ret;
3609
3610         if (!lut)
3611                 return -EINVAL;
3612
3613         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3614                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3615                                           lut, lut_size);
3616                 if (ret) {
3617                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3618                         return ret;
3619                 }
3620         } else {
3621                 uint32_t *lut_dw = (uint32_t *)lut;
3622                 uint16_t i, lut_size_dw = lut_size / 4;
3623
3624                 for (i = 0; i < lut_size_dw; i++)
3625                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3626         }
3627
3628         return 0;
3629 }
3630
3631 static int
3632 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3633 {
3634         struct i40e_pf *pf;
3635         struct i40e_hw *hw;
3636         int ret;
3637
3638         if (!vsi || !lut)
3639                 return -EINVAL;
3640
3641         pf = I40E_VSI_TO_PF(vsi);
3642         hw = I40E_VSI_TO_HW(vsi);
3643
3644         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3645                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3646                                           lut, lut_size);
3647                 if (ret) {
3648                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3649                         return ret;
3650                 }
3651         } else {
3652                 uint32_t *lut_dw = (uint32_t *)lut;
3653                 uint16_t i, lut_size_dw = lut_size / 4;
3654
3655                 for (i = 0; i < lut_size_dw; i++)
3656                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3657                 I40E_WRITE_FLUSH(hw);
3658         }
3659
3660         return 0;
3661 }
3662
3663 static int
3664 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3665                          struct rte_eth_rss_reta_entry64 *reta_conf,
3666                          uint16_t reta_size)
3667 {
3668         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3669         uint16_t i, lut_size = pf->hash_lut_size;
3670         uint16_t idx, shift;
3671         uint8_t *lut;
3672         int ret;
3673
3674         if (reta_size != lut_size ||
3675                 reta_size > ETH_RSS_RETA_SIZE_512) {
3676                 PMD_DRV_LOG(ERR,
3677                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3678                         reta_size, lut_size);
3679                 return -EINVAL;
3680         }
3681
3682         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3683         if (!lut) {
3684                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3685                 return -ENOMEM;
3686         }
3687         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3688         if (ret)
3689                 goto out;
3690         for (i = 0; i < reta_size; i++) {
3691                 idx = i / RTE_RETA_GROUP_SIZE;
3692                 shift = i % RTE_RETA_GROUP_SIZE;
3693                 if (reta_conf[idx].mask & (1ULL << shift))
3694                         lut[i] = reta_conf[idx].reta[shift];
3695         }
3696         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3697
3698 out:
3699         rte_free(lut);
3700
3701         return ret;
3702 }
3703
3704 static int
3705 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3706                         struct rte_eth_rss_reta_entry64 *reta_conf,
3707                         uint16_t reta_size)
3708 {
3709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3710         uint16_t i, lut_size = pf->hash_lut_size;
3711         uint16_t idx, shift;
3712         uint8_t *lut;
3713         int ret;
3714
3715         if (reta_size != lut_size ||
3716                 reta_size > ETH_RSS_RETA_SIZE_512) {
3717                 PMD_DRV_LOG(ERR,
3718                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3719                         reta_size, lut_size);
3720                 return -EINVAL;
3721         }
3722
3723         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3724         if (!lut) {
3725                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3726                 return -ENOMEM;
3727         }
3728
3729         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3730         if (ret)
3731                 goto out;
3732         for (i = 0; i < reta_size; i++) {
3733                 idx = i / RTE_RETA_GROUP_SIZE;
3734                 shift = i % RTE_RETA_GROUP_SIZE;
3735                 if (reta_conf[idx].mask & (1ULL << shift))
3736                         reta_conf[idx].reta[shift] = lut[i];
3737         }
3738
3739 out:
3740         rte_free(lut);
3741
3742         return ret;
3743 }
3744
3745 /**
3746  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3747  * @hw:   pointer to the HW structure
3748  * @mem:  pointer to mem struct to fill out
3749  * @size: size of memory requested
3750  * @alignment: what to align the allocation to
3751  **/
3752 enum i40e_status_code
3753 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3754                         struct i40e_dma_mem *mem,
3755                         u64 size,
3756                         u32 alignment)
3757 {
3758         const struct rte_memzone *mz = NULL;
3759         char z_name[RTE_MEMZONE_NAMESIZE];
3760
3761         if (!mem)
3762                 return I40E_ERR_PARAM;
3763
3764         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3765         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3766                                          alignment, RTE_PGSIZE_2M);
3767         if (!mz)
3768                 return I40E_ERR_NO_MEMORY;
3769
3770         mem->size = size;
3771         mem->va = mz->addr;
3772         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3773         mem->zone = (const void *)mz;
3774         PMD_DRV_LOG(DEBUG,
3775                 "memzone %s allocated with physical address: %"PRIu64,
3776                 mz->name, mem->pa);
3777
3778         return I40E_SUCCESS;
3779 }
3780
3781 /**
3782  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3783  * @hw:   pointer to the HW structure
3784  * @mem:  ptr to mem struct to free
3785  **/
3786 enum i40e_status_code
3787 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3788                     struct i40e_dma_mem *mem)
3789 {
3790         if (!mem)
3791                 return I40E_ERR_PARAM;
3792
3793         PMD_DRV_LOG(DEBUG,
3794                 "memzone %s to be freed with physical address: %"PRIu64,
3795                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3796         rte_memzone_free((const struct rte_memzone *)mem->zone);
3797         mem->zone = NULL;
3798         mem->va = NULL;
3799         mem->pa = (u64)0;
3800
3801         return I40E_SUCCESS;
3802 }
3803
3804 /**
3805  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3806  * @hw:   pointer to the HW structure
3807  * @mem:  pointer to mem struct to fill out
3808  * @size: size of memory requested
3809  **/
3810 enum i40e_status_code
3811 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3812                          struct i40e_virt_mem *mem,
3813                          u32 size)
3814 {
3815         if (!mem)
3816                 return I40E_ERR_PARAM;
3817
3818         mem->size = size;
3819         mem->va = rte_zmalloc("i40e", size, 0);
3820
3821         if (mem->va)
3822                 return I40E_SUCCESS;
3823         else
3824                 return I40E_ERR_NO_MEMORY;
3825 }
3826
3827 /**
3828  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3829  * @hw:   pointer to the HW structure
3830  * @mem:  pointer to mem struct to free
3831  **/
3832 enum i40e_status_code
3833 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3834                      struct i40e_virt_mem *mem)
3835 {
3836         if (!mem)
3837                 return I40E_ERR_PARAM;
3838
3839         rte_free(mem->va);
3840         mem->va = NULL;
3841
3842         return I40E_SUCCESS;
3843 }
3844
3845 void
3846 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3847 {
3848         rte_spinlock_init(&sp->spinlock);
3849 }
3850
3851 void
3852 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3853 {
3854         rte_spinlock_lock(&sp->spinlock);
3855 }
3856
3857 void
3858 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3859 {
3860         rte_spinlock_unlock(&sp->spinlock);
3861 }
3862
3863 void
3864 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3865 {
3866         return;
3867 }
3868
3869 /**
3870  * Get the hardware capabilities, which will be parsed
3871  * and saved into struct i40e_hw.
3872  */
3873 static int
3874 i40e_get_cap(struct i40e_hw *hw)
3875 {
3876         struct i40e_aqc_list_capabilities_element_resp *buf;
3877         uint16_t len, size = 0;
3878         int ret;
3879
3880         /* Calculate a huge enough buff for saving response data temporarily */
3881         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3882                                                 I40E_MAX_CAP_ELE_NUM;
3883         buf = rte_zmalloc("i40e", len, 0);
3884         if (!buf) {
3885                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3886                 return I40E_ERR_NO_MEMORY;
3887         }
3888
3889         /* Get, parse the capabilities and save it to hw */
3890         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3891                         i40e_aqc_opc_list_func_capabilities, NULL);
3892         if (ret != I40E_SUCCESS)
3893                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3894
3895         /* Free the temporary buffer after being used */
3896         rte_free(buf);
3897
3898         return ret;
3899 }
3900
3901 static int
3902 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3903 {
3904         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3905         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3906         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3907         uint16_t qp_count = 0, vsi_count = 0;
3908
3909         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3910                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3911                 return -EINVAL;
3912         }
3913         /* Add the parameter init for LFC */
3914         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3915         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3916         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3917
3918         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3919         pf->max_num_vsi = hw->func_caps.num_vsis;
3920         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3921         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3922         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3923
3924         /* FDir queue/VSI allocation */
3925         pf->fdir_qp_offset = 0;
3926         if (hw->func_caps.fd) {
3927                 pf->flags |= I40E_FLAG_FDIR;
3928                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3929         } else {
3930                 pf->fdir_nb_qps = 0;
3931         }
3932         qp_count += pf->fdir_nb_qps;
3933         vsi_count += 1;
3934
3935         /* LAN queue/VSI allocation */
3936         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3937         if (!hw->func_caps.rss) {
3938                 pf->lan_nb_qps = 1;
3939         } else {
3940                 pf->flags |= I40E_FLAG_RSS;
3941                 if (hw->mac.type == I40E_MAC_X722)
3942                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3943                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3944         }
3945         qp_count += pf->lan_nb_qps;
3946         vsi_count += 1;
3947
3948         /* VF queue/VSI allocation */
3949         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3950         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3951                 pf->flags |= I40E_FLAG_SRIOV;
3952                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3953                 pf->vf_num = pci_dev->max_vfs;
3954                 PMD_DRV_LOG(DEBUG,
3955                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3956                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3957         } else {
3958                 pf->vf_nb_qps = 0;
3959                 pf->vf_num = 0;
3960         }
3961         qp_count += pf->vf_nb_qps * pf->vf_num;
3962         vsi_count += pf->vf_num;
3963
3964         /* VMDq queue/VSI allocation */
3965         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3966         pf->vmdq_nb_qps = 0;
3967         pf->max_nb_vmdq_vsi = 0;
3968         if (hw->func_caps.vmdq) {
3969                 if (qp_count < hw->func_caps.num_tx_qp &&
3970                         vsi_count < hw->func_caps.num_vsis) {
3971                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3972                                 qp_count) / pf->vmdq_nb_qp_max;
3973
3974                         /* Limit the maximum number of VMDq vsi to the maximum
3975                          * ethdev can support
3976                          */
3977                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3978                                 hw->func_caps.num_vsis - vsi_count);
3979                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3980                                 ETH_64_POOLS);
3981                         if (pf->max_nb_vmdq_vsi) {
3982                                 pf->flags |= I40E_FLAG_VMDQ;
3983                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3984                                 PMD_DRV_LOG(DEBUG,
3985                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3986                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3987                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3988                         } else {
3989                                 PMD_DRV_LOG(INFO,
3990                                         "No enough queues left for VMDq");
3991                         }
3992                 } else {
3993                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3994                 }
3995         }
3996         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3997         vsi_count += pf->max_nb_vmdq_vsi;
3998
3999         if (hw->func_caps.dcb)
4000                 pf->flags |= I40E_FLAG_DCB;
4001
4002         if (qp_count > hw->func_caps.num_tx_qp) {
4003                 PMD_DRV_LOG(ERR,
4004                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4005                         qp_count, hw->func_caps.num_tx_qp);
4006                 return -EINVAL;
4007         }
4008         if (vsi_count > hw->func_caps.num_vsis) {
4009                 PMD_DRV_LOG(ERR,
4010                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4011                         vsi_count, hw->func_caps.num_vsis);
4012                 return -EINVAL;
4013         }
4014
4015         return 0;
4016 }
4017
4018 static int
4019 i40e_pf_get_switch_config(struct i40e_pf *pf)
4020 {
4021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4022         struct i40e_aqc_get_switch_config_resp *switch_config;
4023         struct i40e_aqc_switch_config_element_resp *element;
4024         uint16_t start_seid = 0, num_reported;
4025         int ret;
4026
4027         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4028                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4029         if (!switch_config) {
4030                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4031                 return -ENOMEM;
4032         }
4033
4034         /* Get the switch configurations */
4035         ret = i40e_aq_get_switch_config(hw, switch_config,
4036                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4037         if (ret != I40E_SUCCESS) {
4038                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4039                 goto fail;
4040         }
4041         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4042         if (num_reported != 1) { /* The number should be 1 */
4043                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4044                 goto fail;
4045         }
4046
4047         /* Parse the switch configuration elements */
4048         element = &(switch_config->element[0]);
4049         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4050                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4051                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4052         } else
4053                 PMD_DRV_LOG(INFO, "Unknown element type");
4054
4055 fail:
4056         rte_free(switch_config);
4057
4058         return ret;
4059 }
4060
4061 static int
4062 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4063                         uint32_t num)
4064 {
4065         struct pool_entry *entry;
4066
4067         if (pool == NULL || num == 0)
4068                 return -EINVAL;
4069
4070         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4071         if (entry == NULL) {
4072                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4073                 return -ENOMEM;
4074         }
4075
4076         /* queue heap initialize */
4077         pool->num_free = num;
4078         pool->num_alloc = 0;
4079         pool->base = base;
4080         LIST_INIT(&pool->alloc_list);
4081         LIST_INIT(&pool->free_list);
4082
4083         /* Initialize element  */
4084         entry->base = 0;
4085         entry->len = num;
4086
4087         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4088         return 0;
4089 }
4090
4091 static void
4092 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4093 {
4094         struct pool_entry *entry, *next_entry;
4095
4096         if (pool == NULL)
4097                 return;
4098
4099         for (entry = LIST_FIRST(&pool->alloc_list);
4100                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4101                         entry = next_entry) {
4102                 LIST_REMOVE(entry, next);
4103                 rte_free(entry);
4104         }
4105
4106         for (entry = LIST_FIRST(&pool->free_list);
4107                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4108                         entry = next_entry) {
4109                 LIST_REMOVE(entry, next);
4110                 rte_free(entry);
4111         }
4112
4113         pool->num_free = 0;
4114         pool->num_alloc = 0;
4115         pool->base = 0;
4116         LIST_INIT(&pool->alloc_list);
4117         LIST_INIT(&pool->free_list);
4118 }
4119
4120 static int
4121 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4122                        uint32_t base)
4123 {
4124         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4125         uint32_t pool_offset;
4126         int insert;
4127
4128         if (pool == NULL) {
4129                 PMD_DRV_LOG(ERR, "Invalid parameter");
4130                 return -EINVAL;
4131         }
4132
4133         pool_offset = base - pool->base;
4134         /* Lookup in alloc list */
4135         LIST_FOREACH(entry, &pool->alloc_list, next) {
4136                 if (entry->base == pool_offset) {
4137                         valid_entry = entry;
4138                         LIST_REMOVE(entry, next);
4139                         break;
4140                 }
4141         }
4142
4143         /* Not find, return */
4144         if (valid_entry == NULL) {
4145                 PMD_DRV_LOG(ERR, "Failed to find entry");
4146                 return -EINVAL;
4147         }
4148
4149         /**
4150          * Found it, move it to free list  and try to merge.
4151          * In order to make merge easier, always sort it by qbase.
4152          * Find adjacent prev and last entries.
4153          */
4154         prev = next = NULL;
4155         LIST_FOREACH(entry, &pool->free_list, next) {
4156                 if (entry->base > valid_entry->base) {
4157                         next = entry;
4158                         break;
4159                 }
4160                 prev = entry;
4161         }
4162
4163         insert = 0;
4164         /* Try to merge with next one*/
4165         if (next != NULL) {
4166                 /* Merge with next one */
4167                 if (valid_entry->base + valid_entry->len == next->base) {
4168                         next->base = valid_entry->base;
4169                         next->len += valid_entry->len;
4170                         rte_free(valid_entry);
4171                         valid_entry = next;
4172                         insert = 1;
4173                 }
4174         }
4175
4176         if (prev != NULL) {
4177                 /* Merge with previous one */
4178                 if (prev->base + prev->len == valid_entry->base) {
4179                         prev->len += valid_entry->len;
4180                         /* If it merge with next one, remove next node */
4181                         if (insert == 1) {
4182                                 LIST_REMOVE(valid_entry, next);
4183                                 rte_free(valid_entry);
4184                         } else {
4185                                 rte_free(valid_entry);
4186                                 insert = 1;
4187                         }
4188                 }
4189         }
4190
4191         /* Not find any entry to merge, insert */
4192         if (insert == 0) {
4193                 if (prev != NULL)
4194                         LIST_INSERT_AFTER(prev, valid_entry, next);
4195                 else if (next != NULL)
4196                         LIST_INSERT_BEFORE(next, valid_entry, next);
4197                 else /* It's empty list, insert to head */
4198                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4199         }
4200
4201         pool->num_free += valid_entry->len;
4202         pool->num_alloc -= valid_entry->len;
4203
4204         return 0;
4205 }
4206
4207 static int
4208 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4209                        uint16_t num)
4210 {
4211         struct pool_entry *entry, *valid_entry;
4212
4213         if (pool == NULL || num == 0) {
4214                 PMD_DRV_LOG(ERR, "Invalid parameter");
4215                 return -EINVAL;
4216         }
4217
4218         if (pool->num_free < num) {
4219                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4220                             num, pool->num_free);
4221                 return -ENOMEM;
4222         }
4223
4224         valid_entry = NULL;
4225         /* Lookup  in free list and find most fit one */
4226         LIST_FOREACH(entry, &pool->free_list, next) {
4227                 if (entry->len >= num) {
4228                         /* Find best one */
4229                         if (entry->len == num) {
4230                                 valid_entry = entry;
4231                                 break;
4232                         }
4233                         if (valid_entry == NULL || valid_entry->len > entry->len)
4234                                 valid_entry = entry;
4235                 }
4236         }
4237
4238         /* Not find one to satisfy the request, return */
4239         if (valid_entry == NULL) {
4240                 PMD_DRV_LOG(ERR, "No valid entry found");
4241                 return -ENOMEM;
4242         }
4243         /**
4244          * The entry have equal queue number as requested,
4245          * remove it from alloc_list.
4246          */
4247         if (valid_entry->len == num) {
4248                 LIST_REMOVE(valid_entry, next);
4249         } else {
4250                 /**
4251                  * The entry have more numbers than requested,
4252                  * create a new entry for alloc_list and minus its
4253                  * queue base and number in free_list.
4254                  */
4255                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4256                 if (entry == NULL) {
4257                         PMD_DRV_LOG(ERR,
4258                                 "Failed to allocate memory for resource pool");
4259                         return -ENOMEM;
4260                 }
4261                 entry->base = valid_entry->base;
4262                 entry->len = num;
4263                 valid_entry->base += num;
4264                 valid_entry->len -= num;
4265                 valid_entry = entry;
4266         }
4267
4268         /* Insert it into alloc list, not sorted */
4269         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4270
4271         pool->num_free -= valid_entry->len;
4272         pool->num_alloc += valid_entry->len;
4273
4274         return valid_entry->base + pool->base;
4275 }
4276
4277 /**
4278  * bitmap_is_subset - Check whether src2 is subset of src1
4279  **/
4280 static inline int
4281 bitmap_is_subset(uint8_t src1, uint8_t src2)
4282 {
4283         return !((src1 ^ src2) & src2);
4284 }
4285
4286 static enum i40e_status_code
4287 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4288 {
4289         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4290
4291         /* If DCB is not supported, only default TC is supported */
4292         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4293                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4294                 return I40E_NOT_SUPPORTED;
4295         }
4296
4297         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4298                 PMD_DRV_LOG(ERR,
4299                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4300                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4301                 return I40E_NOT_SUPPORTED;
4302         }
4303         return I40E_SUCCESS;
4304 }
4305
4306 int
4307 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4308                                 struct i40e_vsi_vlan_pvid_info *info)
4309 {
4310         struct i40e_hw *hw;
4311         struct i40e_vsi_context ctxt;
4312         uint8_t vlan_flags = 0;
4313         int ret;
4314
4315         if (vsi == NULL || info == NULL) {
4316                 PMD_DRV_LOG(ERR, "invalid parameters");
4317                 return I40E_ERR_PARAM;
4318         }
4319
4320         if (info->on) {
4321                 vsi->info.pvid = info->config.pvid;
4322                 /**
4323                  * If insert pvid is enabled, only tagged pkts are
4324                  * allowed to be sent out.
4325                  */
4326                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4327                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4328         } else {
4329                 vsi->info.pvid = 0;
4330                 if (info->config.reject.tagged == 0)
4331                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4332
4333                 if (info->config.reject.untagged == 0)
4334                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4335         }
4336         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4337                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4338         vsi->info.port_vlan_flags |= vlan_flags;
4339         vsi->info.valid_sections =
4340                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4341         memset(&ctxt, 0, sizeof(ctxt));
4342         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4343         ctxt.seid = vsi->seid;
4344
4345         hw = I40E_VSI_TO_HW(vsi);
4346         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4347         if (ret != I40E_SUCCESS)
4348                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4349
4350         return ret;
4351 }
4352
4353 static int
4354 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4355 {
4356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4357         int i, ret;
4358         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4359
4360         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4361         if (ret != I40E_SUCCESS)
4362                 return ret;
4363
4364         if (!vsi->seid) {
4365                 PMD_DRV_LOG(ERR, "seid not valid");
4366                 return -EINVAL;
4367         }
4368
4369         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4370         tc_bw_data.tc_valid_bits = enabled_tcmap;
4371         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4372                 tc_bw_data.tc_bw_credits[i] =
4373                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4374
4375         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4376         if (ret != I40E_SUCCESS) {
4377                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4378                 return ret;
4379         }
4380
4381         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4382                                         sizeof(vsi->info.qs_handle));
4383         return I40E_SUCCESS;
4384 }
4385
4386 static enum i40e_status_code
4387 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4388                                  struct i40e_aqc_vsi_properties_data *info,
4389                                  uint8_t enabled_tcmap)
4390 {
4391         enum i40e_status_code ret;
4392         int i, total_tc = 0;
4393         uint16_t qpnum_per_tc, bsf, qp_idx;
4394
4395         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4396         if (ret != I40E_SUCCESS)
4397                 return ret;
4398
4399         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4400                 if (enabled_tcmap & (1 << i))
4401                         total_tc++;
4402         if (total_tc == 0)
4403                 total_tc = 1;
4404         vsi->enabled_tc = enabled_tcmap;
4405
4406         /* Number of queues per enabled TC */
4407         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4408         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4409         bsf = rte_bsf32(qpnum_per_tc);
4410
4411         /* Adjust the queue number to actual queues that can be applied */
4412         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4413                 vsi->nb_qps = qpnum_per_tc * total_tc;
4414
4415         /**
4416          * Configure TC and queue mapping parameters, for enabled TC,
4417          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4418          * default queue will serve it.
4419          */
4420         qp_idx = 0;
4421         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4422                 if (vsi->enabled_tc & (1 << i)) {
4423                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4424                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4425                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4426                         qp_idx += qpnum_per_tc;
4427                 } else
4428                         info->tc_mapping[i] = 0;
4429         }
4430
4431         /* Associate queue number with VSI */
4432         if (vsi->type == I40E_VSI_SRIOV) {
4433                 info->mapping_flags |=
4434                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4435                 for (i = 0; i < vsi->nb_qps; i++)
4436                         info->queue_mapping[i] =
4437                                 rte_cpu_to_le_16(vsi->base_queue + i);
4438         } else {
4439                 info->mapping_flags |=
4440                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4441                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4442         }
4443         info->valid_sections |=
4444                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4445
4446         return I40E_SUCCESS;
4447 }
4448
4449 static int
4450 i40e_veb_release(struct i40e_veb *veb)
4451 {
4452         struct i40e_vsi *vsi;
4453         struct i40e_hw *hw;
4454
4455         if (veb == NULL)
4456                 return -EINVAL;
4457
4458         if (!TAILQ_EMPTY(&veb->head)) {
4459                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4460                 return -EACCES;
4461         }
4462         /* associate_vsi field is NULL for floating VEB */
4463         if (veb->associate_vsi != NULL) {
4464                 vsi = veb->associate_vsi;
4465                 hw = I40E_VSI_TO_HW(vsi);
4466
4467                 vsi->uplink_seid = veb->uplink_seid;
4468                 vsi->veb = NULL;
4469         } else {
4470                 veb->associate_pf->main_vsi->floating_veb = NULL;
4471                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4472         }
4473
4474         i40e_aq_delete_element(hw, veb->seid, NULL);
4475         rte_free(veb);
4476         return I40E_SUCCESS;
4477 }
4478
4479 /* Setup a veb */
4480 static struct i40e_veb *
4481 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4482 {
4483         struct i40e_veb *veb;
4484         int ret;
4485         struct i40e_hw *hw;
4486
4487         if (pf == NULL) {
4488                 PMD_DRV_LOG(ERR,
4489                             "veb setup failed, associated PF shouldn't null");
4490                 return NULL;
4491         }
4492         hw = I40E_PF_TO_HW(pf);
4493
4494         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4495         if (!veb) {
4496                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4497                 goto fail;
4498         }
4499
4500         veb->associate_vsi = vsi;
4501         veb->associate_pf = pf;
4502         TAILQ_INIT(&veb->head);
4503         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4504
4505         /* create floating veb if vsi is NULL */
4506         if (vsi != NULL) {
4507                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4508                                       I40E_DEFAULT_TCMAP, false,
4509                                       &veb->seid, false, NULL);
4510         } else {
4511                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4512                                       true, &veb->seid, false, NULL);
4513         }
4514
4515         if (ret != I40E_SUCCESS) {
4516                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4517                             hw->aq.asq_last_status);
4518                 goto fail;
4519         }
4520         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4521
4522         /* get statistics index */
4523         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4524                                 &veb->stats_idx, NULL, NULL, NULL);
4525         if (ret != I40E_SUCCESS) {
4526                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4527                             hw->aq.asq_last_status);
4528                 goto fail;
4529         }
4530         /* Get VEB bandwidth, to be implemented */
4531         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4532         if (vsi)
4533                 vsi->uplink_seid = veb->seid;
4534
4535         return veb;
4536 fail:
4537         rte_free(veb);
4538         return NULL;
4539 }
4540
4541 int
4542 i40e_vsi_release(struct i40e_vsi *vsi)
4543 {
4544         struct i40e_pf *pf;
4545         struct i40e_hw *hw;
4546         struct i40e_vsi_list *vsi_list;
4547         void *temp;
4548         int ret;
4549         struct i40e_mac_filter *f;
4550         uint16_t user_param;
4551
4552         if (!vsi)
4553                 return I40E_SUCCESS;
4554
4555         if (!vsi->adapter)
4556                 return -EFAULT;
4557
4558         user_param = vsi->user_param;
4559
4560         pf = I40E_VSI_TO_PF(vsi);
4561         hw = I40E_VSI_TO_HW(vsi);
4562
4563         /* VSI has child to attach, release child first */
4564         if (vsi->veb) {
4565                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4566                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4567                                 return -1;
4568                 }
4569                 i40e_veb_release(vsi->veb);
4570         }
4571
4572         if (vsi->floating_veb) {
4573                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4574                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4575                                 return -1;
4576                 }
4577         }
4578
4579         /* Remove all macvlan filters of the VSI */
4580         i40e_vsi_remove_all_macvlan_filter(vsi);
4581         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4582                 rte_free(f);
4583
4584         if (vsi->type != I40E_VSI_MAIN &&
4585             ((vsi->type != I40E_VSI_SRIOV) ||
4586             !pf->floating_veb_list[user_param])) {
4587                 /* Remove vsi from parent's sibling list */
4588                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4589                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4590                         return I40E_ERR_PARAM;
4591                 }
4592                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4593                                 &vsi->sib_vsi_list, list);
4594
4595                 /* Remove all switch element of the VSI */
4596                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4597                 if (ret != I40E_SUCCESS)
4598                         PMD_DRV_LOG(ERR, "Failed to delete element");
4599         }
4600
4601         if ((vsi->type == I40E_VSI_SRIOV) &&
4602             pf->floating_veb_list[user_param]) {
4603                 /* Remove vsi from parent's sibling list */
4604                 if (vsi->parent_vsi == NULL ||
4605                     vsi->parent_vsi->floating_veb == NULL) {
4606                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4607                         return I40E_ERR_PARAM;
4608                 }
4609                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4610                              &vsi->sib_vsi_list, list);
4611
4612                 /* Remove all switch element of the VSI */
4613                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4614                 if (ret != I40E_SUCCESS)
4615                         PMD_DRV_LOG(ERR, "Failed to delete element");
4616         }
4617
4618         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4619
4620         if (vsi->type != I40E_VSI_SRIOV)
4621                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4622         rte_free(vsi);
4623
4624         return I40E_SUCCESS;
4625 }
4626
4627 static int
4628 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4629 {
4630         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4631         struct i40e_aqc_remove_macvlan_element_data def_filter;
4632         struct i40e_mac_filter_info filter;
4633         int ret;
4634
4635         if (vsi->type != I40E_VSI_MAIN)
4636                 return I40E_ERR_CONFIG;
4637         memset(&def_filter, 0, sizeof(def_filter));
4638         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4639                                         ETH_ADDR_LEN);
4640         def_filter.vlan_tag = 0;
4641         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4642                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4643         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4644         if (ret != I40E_SUCCESS) {
4645                 struct i40e_mac_filter *f;
4646                 struct ether_addr *mac;
4647
4648                 PMD_DRV_LOG(DEBUG,
4649                             "Cannot remove the default macvlan filter");
4650                 /* It needs to add the permanent mac into mac list */
4651                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4652                 if (f == NULL) {
4653                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4654                         return I40E_ERR_NO_MEMORY;
4655                 }
4656                 mac = &f->mac_info.mac_addr;
4657                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4658                                 ETH_ADDR_LEN);
4659                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4660                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4661                 vsi->mac_num++;
4662
4663                 return ret;
4664         }
4665         (void)rte_memcpy(&filter.mac_addr,
4666                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4667         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4668         return i40e_vsi_add_mac(vsi, &filter);
4669 }
4670
4671 /*
4672  * i40e_vsi_get_bw_config - Query VSI BW Information
4673  * @vsi: the VSI to be queried
4674  *
4675  * Returns 0 on success, negative value on failure
4676  */
4677 static enum i40e_status_code
4678 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4679 {
4680         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4681         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4682         struct i40e_hw *hw = &vsi->adapter->hw;
4683         i40e_status ret;
4684         int i;
4685         uint32_t bw_max;
4686
4687         memset(&bw_config, 0, sizeof(bw_config));
4688         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4689         if (ret != I40E_SUCCESS) {
4690                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4691                             hw->aq.asq_last_status);
4692                 return ret;
4693         }
4694
4695         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4696         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4697                                         &ets_sla_config, NULL);
4698         if (ret != I40E_SUCCESS) {
4699                 PMD_DRV_LOG(ERR,
4700                         "VSI failed to get TC bandwdith configuration %u",
4701                         hw->aq.asq_last_status);
4702                 return ret;
4703         }
4704
4705         /* store and print out BW info */
4706         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4707         vsi->bw_info.bw_max = bw_config.max_bw;
4708         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4709         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4710         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4711                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4712                      I40E_16_BIT_WIDTH);
4713         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4714                 vsi->bw_info.bw_ets_share_credits[i] =
4715                                 ets_sla_config.share_credits[i];
4716                 vsi->bw_info.bw_ets_credits[i] =
4717                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4718                 /* 4 bits per TC, 4th bit is reserved */
4719                 vsi->bw_info.bw_ets_max[i] =
4720                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4721                                   RTE_LEN2MASK(3, uint8_t));
4722                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4723                             vsi->bw_info.bw_ets_share_credits[i]);
4724                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4725                             vsi->bw_info.bw_ets_credits[i]);
4726                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4727                             vsi->bw_info.bw_ets_max[i]);
4728         }
4729
4730         return I40E_SUCCESS;
4731 }
4732
4733 /* i40e_enable_pf_lb
4734  * @pf: pointer to the pf structure
4735  *
4736  * allow loopback on pf
4737  */
4738 static inline void
4739 i40e_enable_pf_lb(struct i40e_pf *pf)
4740 {
4741         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4742         struct i40e_vsi_context ctxt;
4743         int ret;
4744
4745         /* Use the FW API if FW >= v5.0 */
4746         if (hw->aq.fw_maj_ver < 5) {
4747                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4748                 return;
4749         }
4750
4751         memset(&ctxt, 0, sizeof(ctxt));
4752         ctxt.seid = pf->main_vsi_seid;
4753         ctxt.pf_num = hw->pf_id;
4754         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4755         if (ret) {
4756                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4757                             ret, hw->aq.asq_last_status);
4758                 return;
4759         }
4760         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4761         ctxt.info.valid_sections =
4762                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4763         ctxt.info.switch_id |=
4764                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4765
4766         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4767         if (ret)
4768                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4769                             hw->aq.asq_last_status);
4770 }
4771
4772 /* Setup a VSI */
4773 struct i40e_vsi *
4774 i40e_vsi_setup(struct i40e_pf *pf,
4775                enum i40e_vsi_type type,
4776                struct i40e_vsi *uplink_vsi,
4777                uint16_t user_param)
4778 {
4779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4780         struct i40e_vsi *vsi;
4781         struct i40e_mac_filter_info filter;
4782         int ret;
4783         struct i40e_vsi_context ctxt;
4784         struct ether_addr broadcast =
4785                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4786
4787         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4788             uplink_vsi == NULL) {
4789                 PMD_DRV_LOG(ERR,
4790                         "VSI setup failed, VSI link shouldn't be NULL");
4791                 return NULL;
4792         }
4793
4794         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4795                 PMD_DRV_LOG(ERR,
4796                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4797                 return NULL;
4798         }
4799
4800         /* two situations
4801          * 1.type is not MAIN and uplink vsi is not NULL
4802          * If uplink vsi didn't setup VEB, create one first under veb field
4803          * 2.type is SRIOV and the uplink is NULL
4804          * If floating VEB is NULL, create one veb under floating veb field
4805          */
4806
4807         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4808             uplink_vsi->veb == NULL) {
4809                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4810
4811                 if (uplink_vsi->veb == NULL) {
4812                         PMD_DRV_LOG(ERR, "VEB setup failed");
4813                         return NULL;
4814                 }
4815                 /* set ALLOWLOOPBACk on pf, when veb is created */
4816                 i40e_enable_pf_lb(pf);
4817         }
4818
4819         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4820             pf->main_vsi->floating_veb == NULL) {
4821                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4822
4823                 if (pf->main_vsi->floating_veb == NULL) {
4824                         PMD_DRV_LOG(ERR, "VEB setup failed");
4825                         return NULL;
4826                 }
4827         }
4828
4829         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4830         if (!vsi) {
4831                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4832                 return NULL;
4833         }
4834         TAILQ_INIT(&vsi->mac_list);
4835         vsi->type = type;
4836         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4837         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4838         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4839         vsi->user_param = user_param;
4840         vsi->vlan_anti_spoof_on = 0;
4841         vsi->vlan_filter_on = 0;
4842         /* Allocate queues */
4843         switch (vsi->type) {
4844         case I40E_VSI_MAIN  :
4845                 vsi->nb_qps = pf->lan_nb_qps;
4846                 break;
4847         case I40E_VSI_SRIOV :
4848                 vsi->nb_qps = pf->vf_nb_qps;
4849                 break;
4850         case I40E_VSI_VMDQ2:
4851                 vsi->nb_qps = pf->vmdq_nb_qps;
4852                 break;
4853         case I40E_VSI_FDIR:
4854                 vsi->nb_qps = pf->fdir_nb_qps;
4855                 break;
4856         default:
4857                 goto fail_mem;
4858         }
4859         /*
4860          * The filter status descriptor is reported in rx queue 0,
4861          * while the tx queue for fdir filter programming has no
4862          * such constraints, can be non-zero queues.
4863          * To simplify it, choose FDIR vsi use queue 0 pair.
4864          * To make sure it will use queue 0 pair, queue allocation
4865          * need be done before this function is called
4866          */
4867         if (type != I40E_VSI_FDIR) {
4868                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4869                         if (ret < 0) {
4870                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4871                                                 vsi->seid, ret);
4872                                 goto fail_mem;
4873                         }
4874                         vsi->base_queue = ret;
4875         } else
4876                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4877
4878         /* VF has MSIX interrupt in VF range, don't allocate here */
4879         if (type == I40E_VSI_MAIN) {
4880                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4881                                           RTE_MIN(vsi->nb_qps,
4882                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4883                 if (ret < 0) {
4884                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4885                                     vsi->seid, ret);
4886                         goto fail_queue_alloc;
4887                 }
4888                 vsi->msix_intr = ret;
4889                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4890         } else if (type != I40E_VSI_SRIOV) {
4891                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4892                 if (ret < 0) {
4893                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4894                         goto fail_queue_alloc;
4895                 }
4896                 vsi->msix_intr = ret;
4897                 vsi->nb_msix = 1;
4898         } else {
4899                 vsi->msix_intr = 0;
4900                 vsi->nb_msix = 0;
4901         }
4902
4903         /* Add VSI */
4904         if (type == I40E_VSI_MAIN) {
4905                 /* For main VSI, no need to add since it's default one */
4906                 vsi->uplink_seid = pf->mac_seid;
4907                 vsi->seid = pf->main_vsi_seid;
4908                 /* Bind queues with specific MSIX interrupt */
4909                 /**
4910                  * Needs 2 interrupt at least, one for misc cause which will
4911                  * enabled from OS side, Another for queues binding the
4912                  * interrupt from device side only.
4913                  */
4914
4915                 /* Get default VSI parameters from hardware */
4916                 memset(&ctxt, 0, sizeof(ctxt));
4917                 ctxt.seid = vsi->seid;
4918                 ctxt.pf_num = hw->pf_id;
4919                 ctxt.uplink_seid = vsi->uplink_seid;
4920                 ctxt.vf_num = 0;
4921                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4922                 if (ret != I40E_SUCCESS) {
4923                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4924                         goto fail_msix_alloc;
4925                 }
4926                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4927                         sizeof(struct i40e_aqc_vsi_properties_data));
4928                 vsi->vsi_id = ctxt.vsi_number;
4929                 vsi->info.valid_sections = 0;
4930
4931                 /* Configure tc, enabled TC0 only */
4932                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4933                         I40E_SUCCESS) {
4934                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4935                         goto fail_msix_alloc;
4936                 }
4937
4938                 /* TC, queue mapping */
4939                 memset(&ctxt, 0, sizeof(ctxt));
4940                 vsi->info.valid_sections |=
4941                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4942                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4943                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4944                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4945                         sizeof(struct i40e_aqc_vsi_properties_data));
4946                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4947                                                 I40E_DEFAULT_TCMAP);
4948                 if (ret != I40E_SUCCESS) {
4949                         PMD_DRV_LOG(ERR,
4950                                 "Failed to configure TC queue mapping");
4951                         goto fail_msix_alloc;
4952                 }
4953                 ctxt.seid = vsi->seid;
4954                 ctxt.pf_num = hw->pf_id;
4955                 ctxt.uplink_seid = vsi->uplink_seid;
4956                 ctxt.vf_num = 0;
4957
4958                 /* Update VSI parameters */
4959                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4960                 if (ret != I40E_SUCCESS) {
4961                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4962                         goto fail_msix_alloc;
4963                 }
4964
4965                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4966                                                 sizeof(vsi->info.tc_mapping));
4967                 (void)rte_memcpy(&vsi->info.queue_mapping,
4968                                 &ctxt.info.queue_mapping,
4969                         sizeof(vsi->info.queue_mapping));
4970                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4971                 vsi->info.valid_sections = 0;
4972
4973                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4974                                 ETH_ADDR_LEN);
4975
4976                 /**
4977                  * Updating default filter settings are necessary to prevent
4978                  * reception of tagged packets.
4979                  * Some old firmware configurations load a default macvlan
4980                  * filter which accepts both tagged and untagged packets.
4981                  * The updating is to use a normal filter instead if needed.
4982                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4983                  * The firmware with correct configurations load the default
4984                  * macvlan filter which is expected and cannot be removed.
4985                  */
4986                 i40e_update_default_filter_setting(vsi);
4987                 i40e_config_qinq(hw, vsi);
4988         } else if (type == I40E_VSI_SRIOV) {
4989                 memset(&ctxt, 0, sizeof(ctxt));
4990                 /**
4991                  * For other VSI, the uplink_seid equals to uplink VSI's
4992                  * uplink_seid since they share same VEB
4993                  */
4994                 if (uplink_vsi == NULL)
4995                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4996                 else
4997                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4998                 ctxt.pf_num = hw->pf_id;
4999                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5000                 ctxt.uplink_seid = vsi->uplink_seid;
5001                 ctxt.connection_type = 0x1;
5002                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5003
5004                 /* Use the VEB configuration if FW >= v5.0 */
5005                 if (hw->aq.fw_maj_ver >= 5) {
5006                         /* Configure switch ID */
5007                         ctxt.info.valid_sections |=
5008                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5009                         ctxt.info.switch_id =
5010                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5011                 }
5012
5013                 /* Configure port/vlan */
5014                 ctxt.info.valid_sections |=
5015                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5016                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5017                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5018                                                 hw->func_caps.enabled_tcmap);
5019                 if (ret != I40E_SUCCESS) {
5020                         PMD_DRV_LOG(ERR,
5021                                 "Failed to configure TC queue mapping");
5022                         goto fail_msix_alloc;
5023                 }
5024
5025                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5026                 ctxt.info.valid_sections |=
5027                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5028                 /**
5029                  * Since VSI is not created yet, only configure parameter,
5030                  * will add vsi below.
5031                  */
5032
5033                 i40e_config_qinq(hw, vsi);
5034         } else if (type == I40E_VSI_VMDQ2) {
5035                 memset(&ctxt, 0, sizeof(ctxt));
5036                 /*
5037                  * For other VSI, the uplink_seid equals to uplink VSI's
5038                  * uplink_seid since they share same VEB
5039                  */
5040                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5041                 ctxt.pf_num = hw->pf_id;
5042                 ctxt.vf_num = 0;
5043                 ctxt.uplink_seid = vsi->uplink_seid;
5044                 ctxt.connection_type = 0x1;
5045                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5046
5047                 ctxt.info.valid_sections |=
5048                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5049                 /* user_param carries flag to enable loop back */
5050                 if (user_param) {
5051                         ctxt.info.switch_id =
5052                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5053                         ctxt.info.switch_id |=
5054                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5055                 }
5056
5057                 /* Configure port/vlan */
5058                 ctxt.info.valid_sections |=
5059                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5060                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5061                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5062                                                 I40E_DEFAULT_TCMAP);
5063                 if (ret != I40E_SUCCESS) {
5064                         PMD_DRV_LOG(ERR,
5065                                 "Failed to configure TC queue mapping");
5066                         goto fail_msix_alloc;
5067                 }
5068                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5069                 ctxt.info.valid_sections |=
5070                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5071         } else if (type == I40E_VSI_FDIR) {
5072                 memset(&ctxt, 0, sizeof(ctxt));
5073                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5074                 ctxt.pf_num = hw->pf_id;
5075                 ctxt.vf_num = 0;
5076                 ctxt.uplink_seid = vsi->uplink_seid;
5077                 ctxt.connection_type = 0x1;     /* regular data port */
5078                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5079                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5080                                                 I40E_DEFAULT_TCMAP);
5081                 if (ret != I40E_SUCCESS) {
5082                         PMD_DRV_LOG(ERR,
5083                                 "Failed to configure TC queue mapping.");
5084                         goto fail_msix_alloc;
5085                 }
5086                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5087                 ctxt.info.valid_sections |=
5088                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5089         } else {
5090                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5091                 goto fail_msix_alloc;
5092         }
5093
5094         if (vsi->type != I40E_VSI_MAIN) {
5095                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5096                 if (ret != I40E_SUCCESS) {
5097                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5098                                     hw->aq.asq_last_status);
5099                         goto fail_msix_alloc;
5100                 }
5101                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5102                 vsi->info.valid_sections = 0;
5103                 vsi->seid = ctxt.seid;
5104                 vsi->vsi_id = ctxt.vsi_number;
5105                 vsi->sib_vsi_list.vsi = vsi;
5106                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5107                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5108                                           &vsi->sib_vsi_list, list);
5109                 } else {
5110                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5111                                           &vsi->sib_vsi_list, list);
5112                 }
5113         }
5114
5115         /* MAC/VLAN configuration */
5116         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5117         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5118
5119         ret = i40e_vsi_add_mac(vsi, &filter);
5120         if (ret != I40E_SUCCESS) {
5121                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5122                 goto fail_msix_alloc;
5123         }
5124
5125         /* Get VSI BW information */
5126         i40e_vsi_get_bw_config(vsi);
5127         return vsi;
5128 fail_msix_alloc:
5129         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5130 fail_queue_alloc:
5131         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5132 fail_mem:
5133         rte_free(vsi);
5134         return NULL;
5135 }
5136
5137 /* Configure vlan filter on or off */
5138 int
5139 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5140 {
5141         int i, num;
5142         struct i40e_mac_filter *f;
5143         void *temp;
5144         struct i40e_mac_filter_info *mac_filter;
5145         enum rte_mac_filter_type desired_filter;
5146         int ret = I40E_SUCCESS;
5147
5148         if (on) {
5149                 /* Filter to match MAC and VLAN */
5150                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5151         } else {
5152                 /* Filter to match only MAC */
5153                 desired_filter = RTE_MAC_PERFECT_MATCH;
5154         }
5155
5156         num = vsi->mac_num;
5157
5158         mac_filter = rte_zmalloc("mac_filter_info_data",
5159                                  num * sizeof(*mac_filter), 0);
5160         if (mac_filter == NULL) {
5161                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5162                 return I40E_ERR_NO_MEMORY;
5163         }
5164
5165         i = 0;
5166
5167         /* Remove all existing mac */
5168         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5169                 mac_filter[i] = f->mac_info;
5170                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5171                 if (ret) {
5172                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5173                                     on ? "enable" : "disable");
5174                         goto DONE;
5175                 }
5176                 i++;
5177         }
5178
5179         /* Override with new filter */
5180         for (i = 0; i < num; i++) {
5181                 mac_filter[i].filter_type = desired_filter;
5182                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5183                 if (ret) {
5184                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5185                                     on ? "enable" : "disable");
5186                         goto DONE;
5187                 }
5188         }
5189
5190 DONE:
5191         rte_free(mac_filter);
5192         return ret;
5193 }
5194
5195 /* Configure vlan stripping on or off */
5196 int
5197 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5198 {
5199         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5200         struct i40e_vsi_context ctxt;
5201         uint8_t vlan_flags;
5202         int ret = I40E_SUCCESS;
5203
5204         /* Check if it has been already on or off */
5205         if (vsi->info.valid_sections &
5206                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5207                 if (on) {
5208                         if ((vsi->info.port_vlan_flags &
5209                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5210                                 return 0; /* already on */
5211                 } else {
5212                         if ((vsi->info.port_vlan_flags &
5213                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5214                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5215                                 return 0; /* already off */
5216                 }
5217         }
5218
5219         if (on)
5220                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5221         else
5222                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5223         vsi->info.valid_sections =
5224                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5225         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5226         vsi->info.port_vlan_flags |= vlan_flags;
5227         ctxt.seid = vsi->seid;
5228         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5229         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5230         if (ret)
5231                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5232                             on ? "enable" : "disable");
5233
5234         return ret;
5235 }
5236
5237 static int
5238 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5239 {
5240         struct rte_eth_dev_data *data = dev->data;
5241         int ret;
5242         int mask = 0;
5243
5244         /* Apply vlan offload setting */
5245         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5246         i40e_vlan_offload_set(dev, mask);
5247
5248         /* Apply double-vlan setting, not implemented yet */
5249
5250         /* Apply pvid setting */
5251         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5252                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5253         if (ret)
5254                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5255
5256         return ret;
5257 }
5258
5259 static int
5260 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5261 {
5262         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5263
5264         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5265 }
5266
5267 static int
5268 i40e_update_flow_control(struct i40e_hw *hw)
5269 {
5270 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5271         struct i40e_link_status link_status;
5272         uint32_t rxfc = 0, txfc = 0, reg;
5273         uint8_t an_info;
5274         int ret;
5275
5276         memset(&link_status, 0, sizeof(link_status));
5277         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5278         if (ret != I40E_SUCCESS) {
5279                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5280                 goto write_reg; /* Disable flow control */
5281         }
5282
5283         an_info = hw->phy.link_info.an_info;
5284         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5285                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5286                 ret = I40E_ERR_NOT_READY;
5287                 goto write_reg; /* Disable flow control */
5288         }
5289         /**
5290          * If link auto negotiation is enabled, flow control needs to
5291          * be configured according to it
5292          */
5293         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5294         case I40E_LINK_PAUSE_RXTX:
5295                 rxfc = 1;
5296                 txfc = 1;
5297                 hw->fc.current_mode = I40E_FC_FULL;
5298                 break;
5299         case I40E_AQ_LINK_PAUSE_RX:
5300                 rxfc = 1;
5301                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5302                 break;
5303         case I40E_AQ_LINK_PAUSE_TX:
5304                 txfc = 1;
5305                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5306                 break;
5307         default:
5308                 hw->fc.current_mode = I40E_FC_NONE;
5309                 break;
5310         }
5311
5312 write_reg:
5313         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5314                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5315         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5316         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5317         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5318         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5319
5320         return ret;
5321 }
5322
5323 /* PF setup */
5324 static int
5325 i40e_pf_setup(struct i40e_pf *pf)
5326 {
5327         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5328         struct i40e_filter_control_settings settings;
5329         struct i40e_vsi *vsi;
5330         int ret;
5331
5332         /* Clear all stats counters */
5333         pf->offset_loaded = FALSE;
5334         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5335         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5336         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5337         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5338
5339         ret = i40e_pf_get_switch_config(pf);
5340         if (ret != I40E_SUCCESS) {
5341                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5342                 return ret;
5343         }
5344         if (pf->flags & I40E_FLAG_FDIR) {
5345                 /* make queue allocated first, let FDIR use queue pair 0*/
5346                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5347                 if (ret != I40E_FDIR_QUEUE_ID) {
5348                         PMD_DRV_LOG(ERR,
5349                                 "queue allocation fails for FDIR: ret =%d",
5350                                 ret);
5351                         pf->flags &= ~I40E_FLAG_FDIR;
5352                 }
5353         }
5354         /*  main VSI setup */
5355         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5356         if (!vsi) {
5357                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5358                 return I40E_ERR_NOT_READY;
5359         }
5360         pf->main_vsi = vsi;
5361
5362         /* Configure filter control */
5363         memset(&settings, 0, sizeof(settings));
5364         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5365                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5366         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5367                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5368         else {
5369                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5370                         hw->func_caps.rss_table_size);
5371                 return I40E_ERR_PARAM;
5372         }
5373         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5374                 hw->func_caps.rss_table_size);
5375         pf->hash_lut_size = hw->func_caps.rss_table_size;
5376
5377         /* Enable ethtype and macvlan filters */
5378         settings.enable_ethtype = TRUE;
5379         settings.enable_macvlan = TRUE;
5380         ret = i40e_set_filter_control(hw, &settings);
5381         if (ret)
5382                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5383                                                                 ret);
5384
5385         /* Update flow control according to the auto negotiation */
5386         i40e_update_flow_control(hw);
5387
5388         return I40E_SUCCESS;
5389 }
5390
5391 int
5392 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5393 {
5394         uint32_t reg;
5395         uint16_t j;
5396
5397         /**
5398          * Set or clear TX Queue Disable flags,
5399          * which is required by hardware.
5400          */
5401         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5402         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5403
5404         /* Wait until the request is finished */
5405         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5406                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5407                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5408                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5409                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5410                                                         & 0x1))) {
5411                         break;
5412                 }
5413         }
5414         if (on) {
5415                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5416                         return I40E_SUCCESS; /* already on, skip next steps */
5417
5418                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5419                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5420         } else {
5421                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5422                         return I40E_SUCCESS; /* already off, skip next steps */
5423                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5424         }
5425         /* Write the register */
5426         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5427         /* Check the result */
5428         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5429                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5430                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5431                 if (on) {
5432                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5433                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5434                                 break;
5435                 } else {
5436                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5437                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5438                                 break;
5439                 }
5440         }
5441         /* Check if it is timeout */
5442         if (j >= I40E_CHK_Q_ENA_COUNT) {
5443                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5444                             (on ? "enable" : "disable"), q_idx);
5445                 return I40E_ERR_TIMEOUT;
5446         }
5447
5448         return I40E_SUCCESS;
5449 }
5450
5451 /* Swith on or off the tx queues */
5452 static int
5453 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5454 {
5455         struct rte_eth_dev_data *dev_data = pf->dev_data;
5456         struct i40e_tx_queue *txq;
5457         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5458         uint16_t i;
5459         int ret;
5460
5461         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5462                 txq = dev_data->tx_queues[i];
5463                 /* Don't operate the queue if not configured or
5464                  * if starting only per queue */
5465                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5466                         continue;
5467                 if (on)
5468                         ret = i40e_dev_tx_queue_start(dev, i);
5469                 else
5470                         ret = i40e_dev_tx_queue_stop(dev, i);
5471                 if ( ret != I40E_SUCCESS)
5472                         return ret;
5473         }
5474
5475         return I40E_SUCCESS;
5476 }
5477
5478 int
5479 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5480 {
5481         uint32_t reg;
5482         uint16_t j;
5483
5484         /* Wait until the request is finished */
5485         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5486                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5487                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5488                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5489                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5490                         break;
5491         }
5492
5493         if (on) {
5494                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5495                         return I40E_SUCCESS; /* Already on, skip next steps */
5496                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5497         } else {
5498                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5499                         return I40E_SUCCESS; /* Already off, skip next steps */
5500                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5501         }
5502
5503         /* Write the register */
5504         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5505         /* Check the result */
5506         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5507                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5508                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5509                 if (on) {
5510                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5511                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5512                                 break;
5513                 } else {
5514                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5515                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5516                                 break;
5517                 }
5518         }
5519
5520         /* Check if it is timeout */
5521         if (j >= I40E_CHK_Q_ENA_COUNT) {
5522                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5523                             (on ? "enable" : "disable"), q_idx);
5524                 return I40E_ERR_TIMEOUT;
5525         }
5526
5527         return I40E_SUCCESS;
5528 }
5529 /* Switch on or off the rx queues */
5530 static int
5531 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5532 {
5533         struct rte_eth_dev_data *dev_data = pf->dev_data;
5534         struct i40e_rx_queue *rxq;
5535         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5536         uint16_t i;
5537         int ret;
5538
5539         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5540                 rxq = dev_data->rx_queues[i];
5541                 /* Don't operate the queue if not configured or
5542                  * if starting only per queue */
5543                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5544                         continue;
5545                 if (on)
5546                         ret = i40e_dev_rx_queue_start(dev, i);
5547                 else
5548                         ret = i40e_dev_rx_queue_stop(dev, i);
5549                 if (ret != I40E_SUCCESS)
5550                         return ret;
5551         }
5552
5553         return I40E_SUCCESS;
5554 }
5555
5556 /* Switch on or off all the rx/tx queues */
5557 int
5558 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5559 {
5560         int ret;
5561
5562         if (on) {
5563                 /* enable rx queues before enabling tx queues */
5564                 ret = i40e_dev_switch_rx_queues(pf, on);
5565                 if (ret) {
5566                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5567                         return ret;
5568                 }
5569                 ret = i40e_dev_switch_tx_queues(pf, on);
5570         } else {
5571                 /* Stop tx queues before stopping rx queues */
5572                 ret = i40e_dev_switch_tx_queues(pf, on);
5573                 if (ret) {
5574                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5575                         return ret;
5576                 }
5577                 ret = i40e_dev_switch_rx_queues(pf, on);
5578         }
5579
5580         return ret;
5581 }
5582
5583 /* Initialize VSI for TX */
5584 static int
5585 i40e_dev_tx_init(struct i40e_pf *pf)
5586 {
5587         struct rte_eth_dev_data *data = pf->dev_data;
5588         uint16_t i;
5589         uint32_t ret = I40E_SUCCESS;
5590         struct i40e_tx_queue *txq;
5591
5592         for (i = 0; i < data->nb_tx_queues; i++) {
5593                 txq = data->tx_queues[i];
5594                 if (!txq || !txq->q_set)
5595                         continue;
5596                 ret = i40e_tx_queue_init(txq);
5597                 if (ret != I40E_SUCCESS)
5598                         break;
5599         }
5600         if (ret == I40E_SUCCESS)
5601                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5602                                      ->eth_dev);
5603
5604         return ret;
5605 }
5606
5607 /* Initialize VSI for RX */
5608 static int
5609 i40e_dev_rx_init(struct i40e_pf *pf)
5610 {
5611         struct rte_eth_dev_data *data = pf->dev_data;
5612         int ret = I40E_SUCCESS;
5613         uint16_t i;
5614         struct i40e_rx_queue *rxq;
5615
5616         i40e_pf_config_mq_rx(pf);
5617         for (i = 0; i < data->nb_rx_queues; i++) {
5618                 rxq = data->rx_queues[i];
5619                 if (!rxq || !rxq->q_set)
5620                         continue;
5621
5622                 ret = i40e_rx_queue_init(rxq);
5623                 if (ret != I40E_SUCCESS) {
5624                         PMD_DRV_LOG(ERR,
5625                                 "Failed to do RX queue initialization");
5626                         break;
5627                 }
5628         }
5629         if (ret == I40E_SUCCESS)
5630                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5631                                      ->eth_dev);
5632
5633         return ret;
5634 }
5635
5636 static int
5637 i40e_dev_rxtx_init(struct i40e_pf *pf)
5638 {
5639         int err;
5640
5641         err = i40e_dev_tx_init(pf);
5642         if (err) {
5643                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5644                 return err;
5645         }
5646         err = i40e_dev_rx_init(pf);
5647         if (err) {
5648                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5649                 return err;
5650         }
5651
5652         return err;
5653 }
5654
5655 static int
5656 i40e_vmdq_setup(struct rte_eth_dev *dev)
5657 {
5658         struct rte_eth_conf *conf = &dev->data->dev_conf;
5659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5660         int i, err, conf_vsis, j, loop;
5661         struct i40e_vsi *vsi;
5662         struct i40e_vmdq_info *vmdq_info;
5663         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5664         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5665
5666         /*
5667          * Disable interrupt to avoid message from VF. Furthermore, it will
5668          * avoid race condition in VSI creation/destroy.
5669          */
5670         i40e_pf_disable_irq0(hw);
5671
5672         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5673                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5674                 return -ENOTSUP;
5675         }
5676
5677         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5678         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5679                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5680                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5681                         pf->max_nb_vmdq_vsi);
5682                 return -ENOTSUP;
5683         }
5684
5685         if (pf->vmdq != NULL) {
5686                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5687                 return 0;
5688         }
5689
5690         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5691                                 sizeof(*vmdq_info) * conf_vsis, 0);
5692
5693         if (pf->vmdq == NULL) {
5694                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5695                 return -ENOMEM;
5696         }
5697
5698         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5699
5700         /* Create VMDQ VSI */
5701         for (i = 0; i < conf_vsis; i++) {
5702                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5703                                 vmdq_conf->enable_loop_back);
5704                 if (vsi == NULL) {
5705                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5706                         err = -1;
5707                         goto err_vsi_setup;
5708                 }
5709                 vmdq_info = &pf->vmdq[i];
5710                 vmdq_info->pf = pf;
5711                 vmdq_info->vsi = vsi;
5712         }
5713         pf->nb_cfg_vmdq_vsi = conf_vsis;
5714
5715         /* Configure Vlan */
5716         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5717         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5718                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5719                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5720                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5721                                         vmdq_conf->pool_map[i].vlan_id, j);
5722
5723                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5724                                                 vmdq_conf->pool_map[i].vlan_id);
5725                                 if (err) {
5726                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5727                                         err = -1;
5728                                         goto err_vsi_setup;
5729                                 }
5730                         }
5731                 }
5732         }
5733
5734         i40e_pf_enable_irq0(hw);
5735
5736         return 0;
5737
5738 err_vsi_setup:
5739         for (i = 0; i < conf_vsis; i++)
5740                 if (pf->vmdq[i].vsi == NULL)
5741                         break;
5742                 else
5743                         i40e_vsi_release(pf->vmdq[i].vsi);
5744
5745         rte_free(pf->vmdq);
5746         pf->vmdq = NULL;
5747         i40e_pf_enable_irq0(hw);
5748         return err;
5749 }
5750
5751 static void
5752 i40e_stat_update_32(struct i40e_hw *hw,
5753                    uint32_t reg,
5754                    bool offset_loaded,
5755                    uint64_t *offset,
5756                    uint64_t *stat)
5757 {
5758         uint64_t new_data;
5759
5760         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5761         if (!offset_loaded)
5762                 *offset = new_data;
5763
5764         if (new_data >= *offset)
5765                 *stat = (uint64_t)(new_data - *offset);
5766         else
5767                 *stat = (uint64_t)((new_data +
5768                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5769 }
5770
5771 static void
5772 i40e_stat_update_48(struct i40e_hw *hw,
5773                    uint32_t hireg,
5774                    uint32_t loreg,
5775                    bool offset_loaded,
5776                    uint64_t *offset,
5777                    uint64_t *stat)
5778 {
5779         uint64_t new_data;
5780
5781         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5782         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5783                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5784
5785         if (!offset_loaded)
5786                 *offset = new_data;
5787
5788         if (new_data >= *offset)
5789                 *stat = new_data - *offset;
5790         else
5791                 *stat = (uint64_t)((new_data +
5792                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5793
5794         *stat &= I40E_48_BIT_MASK;
5795 }
5796
5797 /* Disable IRQ0 */
5798 void
5799 i40e_pf_disable_irq0(struct i40e_hw *hw)
5800 {
5801         /* Disable all interrupt types */
5802         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5803         I40E_WRITE_FLUSH(hw);
5804 }
5805
5806 /* Enable IRQ0 */
5807 void
5808 i40e_pf_enable_irq0(struct i40e_hw *hw)
5809 {
5810         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5811                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5812                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5813                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5814         I40E_WRITE_FLUSH(hw);
5815 }
5816
5817 static void
5818 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5819 {
5820         /* read pending request and disable first */
5821         i40e_pf_disable_irq0(hw);
5822         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5823         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5824                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5825
5826         if (no_queue)
5827                 /* Link no queues with irq0 */
5828                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5829                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5830 }
5831
5832 static void
5833 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5834 {
5835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5836         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5837         int i;
5838         uint16_t abs_vf_id;
5839         uint32_t index, offset, val;
5840
5841         if (!pf->vfs)
5842                 return;
5843         /**
5844          * Try to find which VF trigger a reset, use absolute VF id to access
5845          * since the reg is global register.
5846          */
5847         for (i = 0; i < pf->vf_num; i++) {
5848                 abs_vf_id = hw->func_caps.vf_base_id + i;
5849                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5850                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5851                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5852                 /* VFR event occurred */
5853                 if (val & (0x1 << offset)) {
5854                         int ret;
5855
5856                         /* Clear the event first */
5857                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5858                                                         (0x1 << offset));
5859                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5860                         /**
5861                          * Only notify a VF reset event occurred,
5862                          * don't trigger another SW reset
5863                          */
5864                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5865                         if (ret != I40E_SUCCESS)
5866                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5867                 }
5868         }
5869 }
5870
5871 static void
5872 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5873 {
5874         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5875         int i;
5876
5877         for (i = 0; i < pf->vf_num; i++)
5878                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5879 }
5880
5881 static void
5882 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5883 {
5884         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885         struct i40e_arq_event_info info;
5886         uint16_t pending, opcode;
5887         int ret;
5888
5889         info.buf_len = I40E_AQ_BUF_SZ;
5890         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5891         if (!info.msg_buf) {
5892                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5893                 return;
5894         }
5895
5896         pending = 1;
5897         while (pending) {
5898                 ret = i40e_clean_arq_element(hw, &info, &pending);
5899
5900                 if (ret != I40E_SUCCESS) {
5901                         PMD_DRV_LOG(INFO,
5902                                 "Failed to read msg from AdminQ, aq_err: %u",
5903                                 hw->aq.asq_last_status);
5904                         break;
5905                 }
5906                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5907
5908                 switch (opcode) {
5909                 case i40e_aqc_opc_send_msg_to_pf:
5910                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5911                         i40e_pf_host_handle_vf_msg(dev,
5912                                         rte_le_to_cpu_16(info.desc.retval),
5913                                         rte_le_to_cpu_32(info.desc.cookie_high),
5914                                         rte_le_to_cpu_32(info.desc.cookie_low),
5915                                         info.msg_buf,
5916                                         info.msg_len);
5917                         break;
5918                 case i40e_aqc_opc_get_link_status:
5919                         ret = i40e_dev_link_update(dev, 0);
5920                         if (!ret)
5921                                 _rte_eth_dev_callback_process(dev,
5922                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5923                         break;
5924                 default:
5925                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5926                                     opcode);
5927                         break;
5928                 }
5929         }
5930         rte_free(info.msg_buf);
5931 }
5932
5933 /**
5934  * Interrupt handler triggered by NIC  for handling
5935  * specific interrupt.
5936  *
5937  * @param handle
5938  *  Pointer to interrupt handle.
5939  * @param param
5940  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5941  *
5942  * @return
5943  *  void
5944  */
5945 static void
5946 i40e_dev_interrupt_handler(void *param)
5947 {
5948         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5950         uint32_t icr0;
5951
5952         /* Disable interrupt */
5953         i40e_pf_disable_irq0(hw);
5954
5955         /* read out interrupt causes */
5956         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5957
5958         /* No interrupt event indicated */
5959         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5960                 PMD_DRV_LOG(INFO, "No interrupt event");
5961                 goto done;
5962         }
5963         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5964                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5965         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5966                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5967         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5968                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5969         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5970                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5971         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5972                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5973         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5974                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5975         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5976                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5977
5978         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5979                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5980                 i40e_dev_handle_vfr_event(dev);
5981         }
5982         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5983                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5984                 i40e_dev_handle_aq_msg(dev);
5985         }
5986
5987 done:
5988         /* Enable interrupt */
5989         i40e_pf_enable_irq0(hw);
5990         rte_intr_enable(dev->intr_handle);
5991 }
5992
5993 int
5994 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5995                          struct i40e_macvlan_filter *filter,
5996                          int total)
5997 {
5998         int ele_num, ele_buff_size;
5999         int num, actual_num, i;
6000         uint16_t flags;
6001         int ret = I40E_SUCCESS;
6002         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6003         struct i40e_aqc_add_macvlan_element_data *req_list;
6004
6005         if (filter == NULL  || total == 0)
6006                 return I40E_ERR_PARAM;
6007         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6008         ele_buff_size = hw->aq.asq_buf_size;
6009
6010         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6011         if (req_list == NULL) {
6012                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6013                 return I40E_ERR_NO_MEMORY;
6014         }
6015
6016         num = 0;
6017         do {
6018                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6019                 memset(req_list, 0, ele_buff_size);
6020
6021                 for (i = 0; i < actual_num; i++) {
6022                         (void)rte_memcpy(req_list[i].mac_addr,
6023                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6024                         req_list[i].vlan_tag =
6025                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6026
6027                         switch (filter[num + i].filter_type) {
6028                         case RTE_MAC_PERFECT_MATCH:
6029                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6030                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6031                                 break;
6032                         case RTE_MACVLAN_PERFECT_MATCH:
6033                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6034                                 break;
6035                         case RTE_MAC_HASH_MATCH:
6036                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6037                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6038                                 break;
6039                         case RTE_MACVLAN_HASH_MATCH:
6040                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6041                                 break;
6042                         default:
6043                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6044                                 ret = I40E_ERR_PARAM;
6045                                 goto DONE;
6046                         }
6047
6048                         req_list[i].queue_number = 0;
6049
6050                         req_list[i].flags = rte_cpu_to_le_16(flags);
6051                 }
6052
6053                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6054                                                 actual_num, NULL);
6055                 if (ret != I40E_SUCCESS) {
6056                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6057                         goto DONE;
6058                 }
6059                 num += actual_num;
6060         } while (num < total);
6061
6062 DONE:
6063         rte_free(req_list);
6064         return ret;
6065 }
6066
6067 int
6068 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6069                             struct i40e_macvlan_filter *filter,
6070                             int total)
6071 {
6072         int ele_num, ele_buff_size;
6073         int num, actual_num, i;
6074         uint16_t flags;
6075         int ret = I40E_SUCCESS;
6076         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6077         struct i40e_aqc_remove_macvlan_element_data *req_list;
6078
6079         if (filter == NULL  || total == 0)
6080                 return I40E_ERR_PARAM;
6081
6082         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6083         ele_buff_size = hw->aq.asq_buf_size;
6084
6085         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6086         if (req_list == NULL) {
6087                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6088                 return I40E_ERR_NO_MEMORY;
6089         }
6090
6091         num = 0;
6092         do {
6093                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6094                 memset(req_list, 0, ele_buff_size);
6095
6096                 for (i = 0; i < actual_num; i++) {
6097                         (void)rte_memcpy(req_list[i].mac_addr,
6098                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6099                         req_list[i].vlan_tag =
6100                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6101
6102                         switch (filter[num + i].filter_type) {
6103                         case RTE_MAC_PERFECT_MATCH:
6104                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6105                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6106                                 break;
6107                         case RTE_MACVLAN_PERFECT_MATCH:
6108                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6109                                 break;
6110                         case RTE_MAC_HASH_MATCH:
6111                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6112                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6113                                 break;
6114                         case RTE_MACVLAN_HASH_MATCH:
6115                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6116                                 break;
6117                         default:
6118                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6119                                 ret = I40E_ERR_PARAM;
6120                                 goto DONE;
6121                         }
6122                         req_list[i].flags = rte_cpu_to_le_16(flags);
6123                 }
6124
6125                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6126                                                 actual_num, NULL);
6127                 if (ret != I40E_SUCCESS) {
6128                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6129                         goto DONE;
6130                 }
6131                 num += actual_num;
6132         } while (num < total);
6133
6134 DONE:
6135         rte_free(req_list);
6136         return ret;
6137 }
6138
6139 /* Find out specific MAC filter */
6140 static struct i40e_mac_filter *
6141 i40e_find_mac_filter(struct i40e_vsi *vsi,
6142                          struct ether_addr *macaddr)
6143 {
6144         struct i40e_mac_filter *f;
6145
6146         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6147                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6148                         return f;
6149         }
6150
6151         return NULL;
6152 }
6153
6154 static bool
6155 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6156                          uint16_t vlan_id)
6157 {
6158         uint32_t vid_idx, vid_bit;
6159
6160         if (vlan_id > ETH_VLAN_ID_MAX)
6161                 return 0;
6162
6163         vid_idx = I40E_VFTA_IDX(vlan_id);
6164         vid_bit = I40E_VFTA_BIT(vlan_id);
6165
6166         if (vsi->vfta[vid_idx] & vid_bit)
6167                 return 1;
6168         else
6169                 return 0;
6170 }
6171
6172 static void
6173 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6174                        uint16_t vlan_id, bool on)
6175 {
6176         uint32_t vid_idx, vid_bit;
6177
6178         vid_idx = I40E_VFTA_IDX(vlan_id);
6179         vid_bit = I40E_VFTA_BIT(vlan_id);
6180
6181         if (on)
6182                 vsi->vfta[vid_idx] |= vid_bit;
6183         else
6184                 vsi->vfta[vid_idx] &= ~vid_bit;
6185 }
6186
6187 void
6188 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6189                      uint16_t vlan_id, bool on)
6190 {
6191         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6192         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6193         int ret;
6194
6195         if (vlan_id > ETH_VLAN_ID_MAX)
6196                 return;
6197
6198         i40e_store_vlan_filter(vsi, vlan_id, on);
6199
6200         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6201                 return;
6202
6203         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6204
6205         if (on) {
6206                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6207                                        &vlan_data, 1, NULL);
6208                 if (ret != I40E_SUCCESS)
6209                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6210         } else {
6211                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6212                                           &vlan_data, 1, NULL);
6213                 if (ret != I40E_SUCCESS)
6214                         PMD_DRV_LOG(ERR,
6215                                     "Failed to remove vlan filter");
6216         }
6217 }
6218
6219 /**
6220  * Find all vlan options for specific mac addr,
6221  * return with actual vlan found.
6222  */
6223 int
6224 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6225                            struct i40e_macvlan_filter *mv_f,
6226                            int num, struct ether_addr *addr)
6227 {
6228         int i;
6229         uint32_t j, k;
6230
6231         /**
6232          * Not to use i40e_find_vlan_filter to decrease the loop time,
6233          * although the code looks complex.
6234           */
6235         if (num < vsi->vlan_num)
6236                 return I40E_ERR_PARAM;
6237
6238         i = 0;
6239         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6240                 if (vsi->vfta[j]) {
6241                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6242                                 if (vsi->vfta[j] & (1 << k)) {
6243                                         if (i > num - 1) {
6244                                                 PMD_DRV_LOG(ERR,
6245                                                         "vlan number doesn't match");
6246                                                 return I40E_ERR_PARAM;
6247                                         }
6248                                         (void)rte_memcpy(&mv_f[i].macaddr,
6249                                                         addr, ETH_ADDR_LEN);
6250                                         mv_f[i].vlan_id =
6251                                                 j * I40E_UINT32_BIT_SIZE + k;
6252                                         i++;
6253                                 }
6254                         }
6255                 }
6256         }
6257         return I40E_SUCCESS;
6258 }
6259
6260 static inline int
6261 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6262                            struct i40e_macvlan_filter *mv_f,
6263                            int num,
6264                            uint16_t vlan)
6265 {
6266         int i = 0;
6267         struct i40e_mac_filter *f;
6268
6269         if (num < vsi->mac_num)
6270                 return I40E_ERR_PARAM;
6271
6272         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6273                 if (i > num - 1) {
6274                         PMD_DRV_LOG(ERR, "buffer number not match");
6275                         return I40E_ERR_PARAM;
6276                 }
6277                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6278                                 ETH_ADDR_LEN);
6279                 mv_f[i].vlan_id = vlan;
6280                 mv_f[i].filter_type = f->mac_info.filter_type;
6281                 i++;
6282         }
6283
6284         return I40E_SUCCESS;
6285 }
6286
6287 static int
6288 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6289 {
6290         int i, j, num;
6291         struct i40e_mac_filter *f;
6292         struct i40e_macvlan_filter *mv_f;
6293         int ret = I40E_SUCCESS;
6294
6295         if (vsi == NULL || vsi->mac_num == 0)
6296                 return I40E_ERR_PARAM;
6297
6298         /* Case that no vlan is set */
6299         if (vsi->vlan_num == 0)
6300                 num = vsi->mac_num;
6301         else
6302                 num = vsi->mac_num * vsi->vlan_num;
6303
6304         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6305         if (mv_f == NULL) {
6306                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6307                 return I40E_ERR_NO_MEMORY;
6308         }
6309
6310         i = 0;
6311         if (vsi->vlan_num == 0) {
6312                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6313                         (void)rte_memcpy(&mv_f[i].macaddr,
6314                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6315                         mv_f[i].filter_type = f->mac_info.filter_type;
6316                         mv_f[i].vlan_id = 0;
6317                         i++;
6318                 }
6319         } else {
6320                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6321                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6322                                         vsi->vlan_num, &f->mac_info.mac_addr);
6323                         if (ret != I40E_SUCCESS)
6324                                 goto DONE;
6325                         for (j = i; j < i + vsi->vlan_num; j++)
6326                                 mv_f[j].filter_type = f->mac_info.filter_type;
6327                         i += vsi->vlan_num;
6328                 }
6329         }
6330
6331         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6332 DONE:
6333         rte_free(mv_f);
6334
6335         return ret;
6336 }
6337
6338 int
6339 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6340 {
6341         struct i40e_macvlan_filter *mv_f;
6342         int mac_num;
6343         int ret = I40E_SUCCESS;
6344
6345         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6346                 return I40E_ERR_PARAM;
6347
6348         /* If it's already set, just return */
6349         if (i40e_find_vlan_filter(vsi,vlan))
6350                 return I40E_SUCCESS;
6351
6352         mac_num = vsi->mac_num;
6353
6354         if (mac_num == 0) {
6355                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6356                 return I40E_ERR_PARAM;
6357         }
6358
6359         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6360
6361         if (mv_f == NULL) {
6362                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6363                 return I40E_ERR_NO_MEMORY;
6364         }
6365
6366         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6367
6368         if (ret != I40E_SUCCESS)
6369                 goto DONE;
6370
6371         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6372
6373         if (ret != I40E_SUCCESS)
6374                 goto DONE;
6375
6376         i40e_set_vlan_filter(vsi, vlan, 1);
6377
6378         vsi->vlan_num++;
6379         ret = I40E_SUCCESS;
6380 DONE:
6381         rte_free(mv_f);
6382         return ret;
6383 }
6384
6385 int
6386 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6387 {
6388         struct i40e_macvlan_filter *mv_f;
6389         int mac_num;
6390         int ret = I40E_SUCCESS;
6391
6392         /**
6393          * Vlan 0 is the generic filter for untagged packets
6394          * and can't be removed.
6395          */
6396         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6397                 return I40E_ERR_PARAM;
6398
6399         /* If can't find it, just return */
6400         if (!i40e_find_vlan_filter(vsi, vlan))
6401                 return I40E_ERR_PARAM;
6402
6403         mac_num = vsi->mac_num;
6404
6405         if (mac_num == 0) {
6406                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6407                 return I40E_ERR_PARAM;
6408         }
6409
6410         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6411
6412         if (mv_f == NULL) {
6413                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6414                 return I40E_ERR_NO_MEMORY;
6415         }
6416
6417         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6418
6419         if (ret != I40E_SUCCESS)
6420                 goto DONE;
6421
6422         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6423
6424         if (ret != I40E_SUCCESS)
6425                 goto DONE;
6426
6427         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6428         if (vsi->vlan_num == 1) {
6429                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6430                 if (ret != I40E_SUCCESS)
6431                         goto DONE;
6432
6433                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6434                 if (ret != I40E_SUCCESS)
6435                         goto DONE;
6436         }
6437
6438         i40e_set_vlan_filter(vsi, vlan, 0);
6439
6440         vsi->vlan_num--;
6441         ret = I40E_SUCCESS;
6442 DONE:
6443         rte_free(mv_f);
6444         return ret;
6445 }
6446
6447 int
6448 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6449 {
6450         struct i40e_mac_filter *f;
6451         struct i40e_macvlan_filter *mv_f;
6452         int i, vlan_num = 0;
6453         int ret = I40E_SUCCESS;
6454
6455         /* If it's add and we've config it, return */
6456         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6457         if (f != NULL)
6458                 return I40E_SUCCESS;
6459         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6460                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6461
6462                 /**
6463                  * If vlan_num is 0, that's the first time to add mac,
6464                  * set mask for vlan_id 0.
6465                  */
6466                 if (vsi->vlan_num == 0) {
6467                         i40e_set_vlan_filter(vsi, 0, 1);
6468                         vsi->vlan_num = 1;
6469                 }
6470                 vlan_num = vsi->vlan_num;
6471         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6472                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6473                 vlan_num = 1;
6474
6475         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6476         if (mv_f == NULL) {
6477                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6478                 return I40E_ERR_NO_MEMORY;
6479         }
6480
6481         for (i = 0; i < vlan_num; i++) {
6482                 mv_f[i].filter_type = mac_filter->filter_type;
6483                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6484                                 ETH_ADDR_LEN);
6485         }
6486
6487         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6488                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6489                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6490                                         &mac_filter->mac_addr);
6491                 if (ret != I40E_SUCCESS)
6492                         goto DONE;
6493         }
6494
6495         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6496         if (ret != I40E_SUCCESS)
6497                 goto DONE;
6498
6499         /* Add the mac addr into mac list */
6500         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6501         if (f == NULL) {
6502                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6503                 ret = I40E_ERR_NO_MEMORY;
6504                 goto DONE;
6505         }
6506         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6507                         ETH_ADDR_LEN);
6508         f->mac_info.filter_type = mac_filter->filter_type;
6509         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6510         vsi->mac_num++;
6511
6512         ret = I40E_SUCCESS;
6513 DONE:
6514         rte_free(mv_f);
6515
6516         return ret;
6517 }
6518
6519 int
6520 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6521 {
6522         struct i40e_mac_filter *f;
6523         struct i40e_macvlan_filter *mv_f;
6524         int i, vlan_num;
6525         enum rte_mac_filter_type filter_type;
6526         int ret = I40E_SUCCESS;
6527
6528         /* Can't find it, return an error */
6529         f = i40e_find_mac_filter(vsi, addr);
6530         if (f == NULL)
6531                 return I40E_ERR_PARAM;
6532
6533         vlan_num = vsi->vlan_num;
6534         filter_type = f->mac_info.filter_type;
6535         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6536                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6537                 if (vlan_num == 0) {
6538                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6539                         return I40E_ERR_PARAM;
6540                 }
6541         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6542                         filter_type == RTE_MAC_HASH_MATCH)
6543                 vlan_num = 1;
6544
6545         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6546         if (mv_f == NULL) {
6547                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6548                 return I40E_ERR_NO_MEMORY;
6549         }
6550
6551         for (i = 0; i < vlan_num; i++) {
6552                 mv_f[i].filter_type = filter_type;
6553                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6554                                 ETH_ADDR_LEN);
6555         }
6556         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6557                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6558                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6559                 if (ret != I40E_SUCCESS)
6560                         goto DONE;
6561         }
6562
6563         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6564         if (ret != I40E_SUCCESS)
6565                 goto DONE;
6566
6567         /* Remove the mac addr into mac list */
6568         TAILQ_REMOVE(&vsi->mac_list, f, next);
6569         rte_free(f);
6570         vsi->mac_num--;
6571
6572         ret = I40E_SUCCESS;
6573 DONE:
6574         rte_free(mv_f);
6575         return ret;
6576 }
6577
6578 /* Configure hash enable flags for RSS */
6579 uint64_t
6580 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6581 {
6582         uint64_t hena = 0;
6583
6584         if (!flags)
6585                 return hena;
6586
6587         if (flags & ETH_RSS_FRAG_IPV4)
6588                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6589         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6590                 if (type == I40E_MAC_X722) {
6591                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6592                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6593                 } else
6594                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6595         }
6596         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6597                 if (type == I40E_MAC_X722) {
6598                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6599                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6600                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6601                 } else
6602                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6603         }
6604         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6605                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6606         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6607                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6608         if (flags & ETH_RSS_FRAG_IPV6)
6609                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6610         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6611                 if (type == I40E_MAC_X722) {
6612                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6613                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6614                 } else
6615                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6616         }
6617         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6618                 if (type == I40E_MAC_X722) {
6619                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6620                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6621                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6622                 } else
6623                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6624         }
6625         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6626                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6627         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6628                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6629         if (flags & ETH_RSS_L2_PAYLOAD)
6630                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6631
6632         return hena;
6633 }
6634
6635 /* Parse the hash enable flags */
6636 uint64_t
6637 i40e_parse_hena(uint64_t flags)
6638 {
6639         uint64_t rss_hf = 0;
6640
6641         if (!flags)
6642                 return rss_hf;
6643         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6644                 rss_hf |= ETH_RSS_FRAG_IPV4;
6645         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6646                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6647         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6648                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6649         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6650                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6651         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6652                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6653         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6654                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6655         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6656                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6657         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6658                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6659         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6660                 rss_hf |= ETH_RSS_FRAG_IPV6;
6661         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6662                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6663         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6664                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6665         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6666                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6667         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6668                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6669         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6670                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6671         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6672                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6673         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6674                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6675         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6676                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6677
6678         return rss_hf;
6679 }
6680
6681 /* Disable RSS */
6682 static void
6683 i40e_pf_disable_rss(struct i40e_pf *pf)
6684 {
6685         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6686         uint64_t hena;
6687
6688         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6689         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6690         if (hw->mac.type == I40E_MAC_X722)
6691                 hena &= ~I40E_RSS_HENA_ALL_X722;
6692         else
6693                 hena &= ~I40E_RSS_HENA_ALL;
6694         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6695         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6696         I40E_WRITE_FLUSH(hw);
6697 }
6698
6699 static int
6700 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6701 {
6702         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6703         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6704         int ret = 0;
6705
6706         if (!key || key_len == 0) {
6707                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6708                 return 0;
6709         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6710                 sizeof(uint32_t)) {
6711                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6712                 return -EINVAL;
6713         }
6714
6715         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6716                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6717                         (struct i40e_aqc_get_set_rss_key_data *)key;
6718
6719                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6720                 if (ret)
6721                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6722         } else {
6723                 uint32_t *hash_key = (uint32_t *)key;
6724                 uint16_t i;
6725
6726                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6727                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6728                 I40E_WRITE_FLUSH(hw);
6729         }
6730
6731         return ret;
6732 }
6733
6734 static int
6735 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6736 {
6737         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6738         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6739         int ret;
6740
6741         if (!key || !key_len)
6742                 return -EINVAL;
6743
6744         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6745                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6746                         (struct i40e_aqc_get_set_rss_key_data *)key);
6747                 if (ret) {
6748                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6749                         return ret;
6750                 }
6751         } else {
6752                 uint32_t *key_dw = (uint32_t *)key;
6753                 uint16_t i;
6754
6755                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6756                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6757         }
6758         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6759
6760         return 0;
6761 }
6762
6763 static int
6764 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6765 {
6766         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6767         uint64_t rss_hf;
6768         uint64_t hena;
6769         int ret;
6770
6771         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6772                                rss_conf->rss_key_len);
6773         if (ret)
6774                 return ret;
6775
6776         rss_hf = rss_conf->rss_hf;
6777         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6778         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6779         if (hw->mac.type == I40E_MAC_X722)
6780                 hena &= ~I40E_RSS_HENA_ALL_X722;
6781         else
6782                 hena &= ~I40E_RSS_HENA_ALL;
6783         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6784         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6785         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6786         I40E_WRITE_FLUSH(hw);
6787
6788         return 0;
6789 }
6790
6791 static int
6792 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6793                          struct rte_eth_rss_conf *rss_conf)
6794 {
6795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6797         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6798         uint64_t hena;
6799
6800         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6801         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6802         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6803                  ? I40E_RSS_HENA_ALL_X722
6804                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6805                 if (rss_hf != 0) /* Enable RSS */
6806                         return -EINVAL;
6807                 return 0; /* Nothing to do */
6808         }
6809         /* RSS enabled */
6810         if (rss_hf == 0) /* Disable RSS */
6811                 return -EINVAL;
6812
6813         return i40e_hw_rss_hash_set(pf, rss_conf);
6814 }
6815
6816 static int
6817 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6818                            struct rte_eth_rss_conf *rss_conf)
6819 {
6820         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6822         uint64_t hena;
6823
6824         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6825                          &rss_conf->rss_key_len);
6826
6827         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6828         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6829         rss_conf->rss_hf = i40e_parse_hena(hena);
6830
6831         return 0;
6832 }
6833
6834 static int
6835 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6836 {
6837         switch (filter_type) {
6838         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6839                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6840                 break;
6841         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6842                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6843                 break;
6844         case RTE_TUNNEL_FILTER_IMAC_TENID:
6845                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6846                 break;
6847         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6848                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6849                 break;
6850         case ETH_TUNNEL_FILTER_IMAC:
6851                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6852                 break;
6853         case ETH_TUNNEL_FILTER_OIP:
6854                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6855                 break;
6856         case ETH_TUNNEL_FILTER_IIP:
6857                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6858                 break;
6859         default:
6860                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6861                 return -EINVAL;
6862         }
6863
6864         return 0;
6865 }
6866
6867 /* Convert tunnel filter structure */
6868 static int
6869 i40e_tunnel_filter_convert(
6870         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6871         struct i40e_tunnel_filter *tunnel_filter)
6872 {
6873         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6874                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6875         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6876                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6877         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6878         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6879              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6880             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6881                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6882         else
6883                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6884         tunnel_filter->input.flags = cld_filter->element.flags;
6885         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6886         tunnel_filter->queue = cld_filter->element.queue_number;
6887         rte_memcpy(tunnel_filter->input.general_fields,
6888                    cld_filter->general_fields,
6889                    sizeof(cld_filter->general_fields));
6890
6891         return 0;
6892 }
6893
6894 /* Check if there exists the tunnel filter */
6895 struct i40e_tunnel_filter *
6896 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6897                              const struct i40e_tunnel_filter_input *input)
6898 {
6899         int ret;
6900
6901         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6902         if (ret < 0)
6903                 return NULL;
6904
6905         return tunnel_rule->hash_map[ret];
6906 }
6907
6908 /* Add a tunnel filter into the SW list */
6909 static int
6910 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6911                              struct i40e_tunnel_filter *tunnel_filter)
6912 {
6913         struct i40e_tunnel_rule *rule = &pf->tunnel;
6914         int ret;
6915
6916         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6917         if (ret < 0) {
6918                 PMD_DRV_LOG(ERR,
6919                             "Failed to insert tunnel filter to hash table %d!",
6920                             ret);
6921                 return ret;
6922         }
6923         rule->hash_map[ret] = tunnel_filter;
6924
6925         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6926
6927         return 0;
6928 }
6929
6930 /* Delete a tunnel filter from the SW list */
6931 int
6932 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6933                           struct i40e_tunnel_filter_input *input)
6934 {
6935         struct i40e_tunnel_rule *rule = &pf->tunnel;
6936         struct i40e_tunnel_filter *tunnel_filter;
6937         int ret;
6938
6939         ret = rte_hash_del_key(rule->hash_table, input);
6940         if (ret < 0) {
6941                 PMD_DRV_LOG(ERR,
6942                             "Failed to delete tunnel filter to hash table %d!",
6943                             ret);
6944                 return ret;
6945         }
6946         tunnel_filter = rule->hash_map[ret];
6947         rule->hash_map[ret] = NULL;
6948
6949         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6950         rte_free(tunnel_filter);
6951
6952         return 0;
6953 }
6954
6955 int
6956 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6957                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6958                         uint8_t add)
6959 {
6960         uint16_t ip_type;
6961         uint32_t ipv4_addr;
6962         uint8_t i, tun_type = 0;
6963         /* internal varialbe to convert ipv6 byte order */
6964         uint32_t convert_ipv6[4];
6965         int val, ret = 0;
6966         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6967         struct i40e_vsi *vsi = pf->main_vsi;
6968         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6969         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6970         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6971         struct i40e_tunnel_filter *tunnel, *node;
6972         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6973
6974         cld_filter = rte_zmalloc("tunnel_filter",
6975                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6976         0);
6977
6978         if (NULL == cld_filter) {
6979                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6980                 return -ENOMEM;
6981         }
6982         pfilter = cld_filter;
6983
6984         ether_addr_copy(&tunnel_filter->outer_mac,
6985                         (struct ether_addr *)&pfilter->element.outer_mac);
6986         ether_addr_copy(&tunnel_filter->inner_mac,
6987                         (struct ether_addr *)&pfilter->element.inner_mac);
6988
6989         pfilter->element.inner_vlan =
6990                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6991         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6992                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6993                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6994                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6995                                 &rte_cpu_to_le_32(ipv4_addr),
6996                                 sizeof(pfilter->element.ipaddr.v4.data));
6997         } else {
6998                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6999                 for (i = 0; i < 4; i++) {
7000                         convert_ipv6[i] =
7001                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7002                 }
7003                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7004                            &convert_ipv6,
7005                            sizeof(pfilter->element.ipaddr.v6.data));
7006         }
7007
7008         /* check tunneled type */
7009         switch (tunnel_filter->tunnel_type) {
7010         case RTE_TUNNEL_TYPE_VXLAN:
7011                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7012                 break;
7013         case RTE_TUNNEL_TYPE_NVGRE:
7014                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7015                 break;
7016         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7017                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7018                 break;
7019         default:
7020                 /* Other tunnel types is not supported. */
7021                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7022                 rte_free(cld_filter);
7023                 return -EINVAL;
7024         }
7025
7026         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7027                                        &pfilter->element.flags);
7028         if (val < 0) {
7029                 rte_free(cld_filter);
7030                 return -EINVAL;
7031         }
7032
7033         pfilter->element.flags |= rte_cpu_to_le_16(
7034                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7035                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7036         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7037         pfilter->element.queue_number =
7038                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7039
7040         /* Check if there is the filter in SW list */
7041         memset(&check_filter, 0, sizeof(check_filter));
7042         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7043         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7044         if (add && node) {
7045                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7046                 return -EINVAL;
7047         }
7048
7049         if (!add && !node) {
7050                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7051                 return -EINVAL;
7052         }
7053
7054         if (add) {
7055                 ret = i40e_aq_add_cloud_filters(hw,
7056                                         vsi->seid, &cld_filter->element, 1);
7057                 if (ret < 0) {
7058                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7059                         return -ENOTSUP;
7060                 }
7061                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7062                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7063                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7064         } else {
7065                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7066                                                    &cld_filter->element, 1);
7067                 if (ret < 0) {
7068                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7069                         return -ENOTSUP;
7070                 }
7071                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7072         }
7073
7074         rte_free(cld_filter);
7075         return ret;
7076 }
7077
7078 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7079 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7080 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7081 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7082 #define I40E_TR_GRE_KEY_MASK                    0x400
7083 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7084 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7085
7086 static enum
7087 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7088 {
7089         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7090         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7091         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7092         enum i40e_status_code status = I40E_SUCCESS;
7093
7094         memset(&filter_replace, 0,
7095                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7096         memset(&filter_replace_buf, 0,
7097                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7098
7099         /* create L1 filter */
7100         filter_replace.old_filter_type =
7101                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7102         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7103         filter_replace.tr_bit = 0;
7104
7105         /* Prepare the buffer, 3 entries */
7106         filter_replace_buf.data[0] =
7107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7108         filter_replace_buf.data[0] |=
7109                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7110         filter_replace_buf.data[2] = 0xFF;
7111         filter_replace_buf.data[3] = 0xFF;
7112         filter_replace_buf.data[4] =
7113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7114         filter_replace_buf.data[4] |=
7115                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7116         filter_replace_buf.data[7] = 0xF0;
7117         filter_replace_buf.data[8]
7118                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7119         filter_replace_buf.data[8] |=
7120                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7121         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7122                 I40E_TR_GENEVE_KEY_MASK |
7123                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7124         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7125                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7126                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7127
7128         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7129                                                &filter_replace_buf);
7130         return status;
7131 }
7132
7133 static enum
7134 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7135 {
7136         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7137         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7138         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7139         enum i40e_status_code status = I40E_SUCCESS;
7140
7141         /* For MPLSoUDP */
7142         memset(&filter_replace, 0,
7143                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7144         memset(&filter_replace_buf, 0,
7145                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7146         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7147                 I40E_AQC_MIRROR_CLOUD_FILTER;
7148         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7149         filter_replace.new_filter_type =
7150                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7151         /* Prepare the buffer, 2 entries */
7152         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7153         filter_replace_buf.data[0] |=
7154                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7155         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7156         filter_replace_buf.data[4] |=
7157                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7158         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7159                                                &filter_replace_buf);
7160         if (status < 0)
7161                 return status;
7162
7163         /* For MPLSoGRE */
7164         memset(&filter_replace, 0,
7165                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7166         memset(&filter_replace_buf, 0,
7167                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7168
7169         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7170                 I40E_AQC_MIRROR_CLOUD_FILTER;
7171         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7172         filter_replace.new_filter_type =
7173                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7174         /* Prepare the buffer, 2 entries */
7175         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7176         filter_replace_buf.data[0] |=
7177                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7178         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7179         filter_replace_buf.data[4] |=
7180                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7181
7182         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7183                                                &filter_replace_buf);
7184         return status;
7185 }
7186
7187 int
7188 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7189                       struct i40e_tunnel_filter_conf *tunnel_filter,
7190                       uint8_t add)
7191 {
7192         uint16_t ip_type;
7193         uint32_t ipv4_addr;
7194         uint8_t i, tun_type = 0;
7195         /* internal variable to convert ipv6 byte order */
7196         uint32_t convert_ipv6[4];
7197         int val, ret = 0;
7198         struct i40e_pf_vf *vf = NULL;
7199         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7200         struct i40e_vsi *vsi;
7201         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7202         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7203         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7204         struct i40e_tunnel_filter *tunnel, *node;
7205         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7206         uint32_t teid_le;
7207         bool big_buffer = 0;
7208
7209         cld_filter = rte_zmalloc("tunnel_filter",
7210                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7211                          0);
7212
7213         if (cld_filter == NULL) {
7214                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7215                 return -ENOMEM;
7216         }
7217         pfilter = cld_filter;
7218
7219         ether_addr_copy(&tunnel_filter->outer_mac,
7220                         (struct ether_addr *)&pfilter->element.outer_mac);
7221         ether_addr_copy(&tunnel_filter->inner_mac,
7222                         (struct ether_addr *)&pfilter->element.inner_mac);
7223
7224         pfilter->element.inner_vlan =
7225                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7226         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7227                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7228                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7229                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7230                                 &rte_cpu_to_le_32(ipv4_addr),
7231                                 sizeof(pfilter->element.ipaddr.v4.data));
7232         } else {
7233                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7234                 for (i = 0; i < 4; i++) {
7235                         convert_ipv6[i] =
7236                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7237                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7238                 }
7239                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7240                            &convert_ipv6,
7241                            sizeof(pfilter->element.ipaddr.v6.data));
7242         }
7243
7244         /* check tunneled type */
7245         switch (tunnel_filter->tunnel_type) {
7246         case I40E_TUNNEL_TYPE_VXLAN:
7247                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7248                 break;
7249         case I40E_TUNNEL_TYPE_NVGRE:
7250                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7251                 break;
7252         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7253                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7254                 break;
7255         case I40E_TUNNEL_TYPE_MPLSoUDP:
7256                 if (!pf->mpls_replace_flag) {
7257                         i40e_replace_mpls_l1_filter(pf);
7258                         i40e_replace_mpls_cloud_filter(pf);
7259                         pf->mpls_replace_flag = 1;
7260                 }
7261                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7262                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7263                         teid_le >> 4;
7264                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7265                         (teid_le & 0xF) << 12;
7266                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7267                         0x40;
7268                 big_buffer = 1;
7269                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7270                 break;
7271         case I40E_TUNNEL_TYPE_MPLSoGRE:
7272                 if (!pf->mpls_replace_flag) {
7273                         i40e_replace_mpls_l1_filter(pf);
7274                         i40e_replace_mpls_cloud_filter(pf);
7275                         pf->mpls_replace_flag = 1;
7276                 }
7277                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7278                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7279                         teid_le >> 4;
7280                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7281                         (teid_le & 0xF) << 12;
7282                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7283                         0x0;
7284                 big_buffer = 1;
7285                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7286                 break;
7287         case I40E_TUNNEL_TYPE_QINQ:
7288                 if (!pf->qinq_replace_flag) {
7289                         ret = i40e_cloud_filter_qinq_create(pf);
7290                         if (ret < 0)
7291                                 PMD_DRV_LOG(DEBUG,
7292                                             "QinQ tunnel filter already created.");
7293                         pf->qinq_replace_flag = 1;
7294                 }
7295                 /*      Add in the General fields the values of
7296                  *      the Outer and Inner VLAN
7297                  *      Big Buffer should be set, see changes in
7298                  *      i40e_aq_add_cloud_filters
7299                  */
7300                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7301                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7302                 big_buffer = 1;
7303                 break;
7304         default:
7305                 /* Other tunnel types is not supported. */
7306                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7307                 rte_free(cld_filter);
7308                 return -EINVAL;
7309         }
7310
7311         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7312                 pfilter->element.flags =
7313                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7314         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7315                 pfilter->element.flags =
7316                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7317         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7318                 pfilter->element.flags |=
7319                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7320         else {
7321                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7322                                                 &pfilter->element.flags);
7323                 if (val < 0) {
7324                         rte_free(cld_filter);
7325                         return -EINVAL;
7326                 }
7327         }
7328
7329         pfilter->element.flags |= rte_cpu_to_le_16(
7330                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7331                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7332         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7333         pfilter->element.queue_number =
7334                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7335
7336         if (!tunnel_filter->is_to_vf)
7337                 vsi = pf->main_vsi;
7338         else {
7339                 if (tunnel_filter->vf_id >= pf->vf_num) {
7340                         PMD_DRV_LOG(ERR, "Invalid argument.");
7341                         return -EINVAL;
7342                 }
7343                 vf = &pf->vfs[tunnel_filter->vf_id];
7344                 vsi = vf->vsi;
7345         }
7346
7347         /* Check if there is the filter in SW list */
7348         memset(&check_filter, 0, sizeof(check_filter));
7349         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7350         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7351         check_filter.vf_id = tunnel_filter->vf_id;
7352         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7353         if (add && node) {
7354                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7355                 return -EINVAL;
7356         }
7357
7358         if (!add && !node) {
7359                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7360                 return -EINVAL;
7361         }
7362
7363         if (add) {
7364                 if (big_buffer)
7365                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7366                                                    vsi->seid, cld_filter, 1);
7367                 else
7368                         ret = i40e_aq_add_cloud_filters(hw,
7369                                         vsi->seid, &cld_filter->element, 1);
7370                 if (ret < 0) {
7371                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7372                         return -ENOTSUP;
7373                 }
7374                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7375                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7376                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7377         } else {
7378                 if (big_buffer)
7379                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7380                                 hw, vsi->seid, cld_filter, 1);
7381                 else
7382                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7383                                                    &cld_filter->element, 1);
7384                 if (ret < 0) {
7385                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7386                         return -ENOTSUP;
7387                 }
7388                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7389         }
7390
7391         rte_free(cld_filter);
7392         return ret;
7393 }
7394
7395 static int
7396 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7397 {
7398         uint8_t i;
7399
7400         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7401                 if (pf->vxlan_ports[i] == port)
7402                         return i;
7403         }
7404
7405         return -1;
7406 }
7407
7408 static int
7409 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7410 {
7411         int  idx, ret;
7412         uint8_t filter_idx;
7413         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7414
7415         idx = i40e_get_vxlan_port_idx(pf, port);
7416
7417         /* Check if port already exists */
7418         if (idx >= 0) {
7419                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7420                 return -EINVAL;
7421         }
7422
7423         /* Now check if there is space to add the new port */
7424         idx = i40e_get_vxlan_port_idx(pf, 0);
7425         if (idx < 0) {
7426                 PMD_DRV_LOG(ERR,
7427                         "Maximum number of UDP ports reached, not adding port %d",
7428                         port);
7429                 return -ENOSPC;
7430         }
7431
7432         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7433                                         &filter_idx, NULL);
7434         if (ret < 0) {
7435                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7436                 return -1;
7437         }
7438
7439         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7440                          port,  filter_idx);
7441
7442         /* New port: add it and mark its index in the bitmap */
7443         pf->vxlan_ports[idx] = port;
7444         pf->vxlan_bitmap |= (1 << idx);
7445
7446         if (!(pf->flags & I40E_FLAG_VXLAN))
7447                 pf->flags |= I40E_FLAG_VXLAN;
7448
7449         return 0;
7450 }
7451
7452 static int
7453 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7454 {
7455         int idx;
7456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7457
7458         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7459                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7460                 return -EINVAL;
7461         }
7462
7463         idx = i40e_get_vxlan_port_idx(pf, port);
7464
7465         if (idx < 0) {
7466                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7467                 return -EINVAL;
7468         }
7469
7470         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7471                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7472                 return -1;
7473         }
7474
7475         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7476                         port, idx);
7477
7478         pf->vxlan_ports[idx] = 0;
7479         pf->vxlan_bitmap &= ~(1 << idx);
7480
7481         if (!pf->vxlan_bitmap)
7482                 pf->flags &= ~I40E_FLAG_VXLAN;
7483
7484         return 0;
7485 }
7486
7487 /* Add UDP tunneling port */
7488 static int
7489 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7490                              struct rte_eth_udp_tunnel *udp_tunnel)
7491 {
7492         int ret = 0;
7493         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7494
7495         if (udp_tunnel == NULL)
7496                 return -EINVAL;
7497
7498         switch (udp_tunnel->prot_type) {
7499         case RTE_TUNNEL_TYPE_VXLAN:
7500                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7501                 break;
7502
7503         case RTE_TUNNEL_TYPE_GENEVE:
7504         case RTE_TUNNEL_TYPE_TEREDO:
7505                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7506                 ret = -1;
7507                 break;
7508
7509         default:
7510                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7511                 ret = -1;
7512                 break;
7513         }
7514
7515         return ret;
7516 }
7517
7518 /* Remove UDP tunneling port */
7519 static int
7520 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7521                              struct rte_eth_udp_tunnel *udp_tunnel)
7522 {
7523         int ret = 0;
7524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7525
7526         if (udp_tunnel == NULL)
7527                 return -EINVAL;
7528
7529         switch (udp_tunnel->prot_type) {
7530         case RTE_TUNNEL_TYPE_VXLAN:
7531                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7532                 break;
7533         case RTE_TUNNEL_TYPE_GENEVE:
7534         case RTE_TUNNEL_TYPE_TEREDO:
7535                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7536                 ret = -1;
7537                 break;
7538         default:
7539                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7540                 ret = -1;
7541                 break;
7542         }
7543
7544         return ret;
7545 }
7546
7547 /* Calculate the maximum number of contiguous PF queues that are configured */
7548 static int
7549 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7550 {
7551         struct rte_eth_dev_data *data = pf->dev_data;
7552         int i, num;
7553         struct i40e_rx_queue *rxq;
7554
7555         num = 0;
7556         for (i = 0; i < pf->lan_nb_qps; i++) {
7557                 rxq = data->rx_queues[i];
7558                 if (rxq && rxq->q_set)
7559                         num++;
7560                 else
7561                         break;
7562         }
7563
7564         return num;
7565 }
7566
7567 /* Configure RSS */
7568 static int
7569 i40e_pf_config_rss(struct i40e_pf *pf)
7570 {
7571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7572         struct rte_eth_rss_conf rss_conf;
7573         uint32_t i, lut = 0;
7574         uint16_t j, num;
7575
7576         /*
7577          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7578          * It's necessary to calculate the actual PF queues that are configured.
7579          */
7580         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7581                 num = i40e_pf_calc_configured_queues_num(pf);
7582         else
7583                 num = pf->dev_data->nb_rx_queues;
7584
7585         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7586         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7587                         num);
7588
7589         if (num == 0) {
7590                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7591                 return -ENOTSUP;
7592         }
7593
7594         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7595                 if (j == num)
7596                         j = 0;
7597                 lut = (lut << 8) | (j & ((0x1 <<
7598                         hw->func_caps.rss_table_entry_width) - 1));
7599                 if ((i & 3) == 3)
7600                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7601         }
7602
7603         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7604         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7605                 i40e_pf_disable_rss(pf);
7606                 return 0;
7607         }
7608         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7609                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7610                 /* Random default keys */
7611                 static uint32_t rss_key_default[] = {0x6b793944,
7612                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7613                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7614                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7615
7616                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7617                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7618                                                         sizeof(uint32_t);
7619         }
7620
7621         return i40e_hw_rss_hash_set(pf, &rss_conf);
7622 }
7623
7624 static int
7625 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7626                                struct rte_eth_tunnel_filter_conf *filter)
7627 {
7628         if (pf == NULL || filter == NULL) {
7629                 PMD_DRV_LOG(ERR, "Invalid parameter");
7630                 return -EINVAL;
7631         }
7632
7633         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7634                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7635                 return -EINVAL;
7636         }
7637
7638         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7639                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7640                 return -EINVAL;
7641         }
7642
7643         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7644                 (is_zero_ether_addr(&filter->outer_mac))) {
7645                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7646                 return -EINVAL;
7647         }
7648
7649         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7650                 (is_zero_ether_addr(&filter->inner_mac))) {
7651                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7652                 return -EINVAL;
7653         }
7654
7655         return 0;
7656 }
7657
7658 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7659 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7660 static int
7661 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7662 {
7663         uint32_t val, reg;
7664         int ret = -EINVAL;
7665
7666         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7667         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7668
7669         if (len == 3) {
7670                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7671         } else if (len == 4) {
7672                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7673         } else {
7674                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7675                 return ret;
7676         }
7677
7678         if (reg != val) {
7679                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7680                                                    reg, NULL);
7681                 if (ret != 0)
7682                         return ret;
7683         } else {
7684                 ret = 0;
7685         }
7686         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7687                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7688
7689         return ret;
7690 }
7691
7692 static int
7693 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7694 {
7695         int ret = -EINVAL;
7696
7697         if (!hw || !cfg)
7698                 return -EINVAL;
7699
7700         switch (cfg->cfg_type) {
7701         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7702                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7703                 break;
7704         default:
7705                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7706                 break;
7707         }
7708
7709         return ret;
7710 }
7711
7712 static int
7713 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7714                                enum rte_filter_op filter_op,
7715                                void *arg)
7716 {
7717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7718         int ret = I40E_ERR_PARAM;
7719
7720         switch (filter_op) {
7721         case RTE_ETH_FILTER_SET:
7722                 ret = i40e_dev_global_config_set(hw,
7723                         (struct rte_eth_global_cfg *)arg);
7724                 break;
7725         default:
7726                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7727                 break;
7728         }
7729
7730         return ret;
7731 }
7732
7733 static int
7734 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7735                           enum rte_filter_op filter_op,
7736                           void *arg)
7737 {
7738         struct rte_eth_tunnel_filter_conf *filter;
7739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7740         int ret = I40E_SUCCESS;
7741
7742         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7743
7744         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7745                 return I40E_ERR_PARAM;
7746
7747         switch (filter_op) {
7748         case RTE_ETH_FILTER_NOP:
7749                 if (!(pf->flags & I40E_FLAG_VXLAN))
7750                         ret = I40E_NOT_SUPPORTED;
7751                 break;
7752         case RTE_ETH_FILTER_ADD:
7753                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7754                 break;
7755         case RTE_ETH_FILTER_DELETE:
7756                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7757                 break;
7758         default:
7759                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7760                 ret = I40E_ERR_PARAM;
7761                 break;
7762         }
7763
7764         return ret;
7765 }
7766
7767 static int
7768 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7769 {
7770         int ret = 0;
7771         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7772
7773         /* RSS setup */
7774         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7775                 ret = i40e_pf_config_rss(pf);
7776         else
7777                 i40e_pf_disable_rss(pf);
7778
7779         return ret;
7780 }
7781
7782 /* Get the symmetric hash enable configurations per port */
7783 static void
7784 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7785 {
7786         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7787
7788         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7789 }
7790
7791 /* Set the symmetric hash enable configurations per port */
7792 static void
7793 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7794 {
7795         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7796
7797         if (enable > 0) {
7798                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7799                         PMD_DRV_LOG(INFO,
7800                                 "Symmetric hash has already been enabled");
7801                         return;
7802                 }
7803                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7804         } else {
7805                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7806                         PMD_DRV_LOG(INFO,
7807                                 "Symmetric hash has already been disabled");
7808                         return;
7809                 }
7810                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7811         }
7812         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7813         I40E_WRITE_FLUSH(hw);
7814 }
7815
7816 /*
7817  * Get global configurations of hash function type and symmetric hash enable
7818  * per flow type (pctype). Note that global configuration means it affects all
7819  * the ports on the same NIC.
7820  */
7821 static int
7822 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7823                                    struct rte_eth_hash_global_conf *g_cfg)
7824 {
7825         uint32_t reg, mask = I40E_FLOW_TYPES;
7826         uint16_t i;
7827         enum i40e_filter_pctype pctype;
7828
7829         memset(g_cfg, 0, sizeof(*g_cfg));
7830         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7831         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7832                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7833         else
7834                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7835         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7836                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7837
7838         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7839                 if (!(mask & (1UL << i)))
7840                         continue;
7841                 mask &= ~(1UL << i);
7842                 /* Bit set indicats the coresponding flow type is supported */
7843                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7844                 /* if flowtype is invalid, continue */
7845                 if (!I40E_VALID_FLOW(i))
7846                         continue;
7847                 pctype = i40e_flowtype_to_pctype(i);
7848                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7849                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7850                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7851         }
7852
7853         return 0;
7854 }
7855
7856 static int
7857 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7858 {
7859         uint32_t i;
7860         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7861
7862         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7863                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7864                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7865                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7866                                                 g_cfg->hash_func);
7867                 return -EINVAL;
7868         }
7869
7870         /*
7871          * As i40e supports less than 32 flow types, only first 32 bits need to
7872          * be checked.
7873          */
7874         mask0 = g_cfg->valid_bit_mask[0];
7875         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7876                 if (i == 0) {
7877                         /* Check if any unsupported flow type configured */
7878                         if ((mask0 | i40e_mask) ^ i40e_mask)
7879                                 goto mask_err;
7880                 } else {
7881                         if (g_cfg->valid_bit_mask[i])
7882                                 goto mask_err;
7883                 }
7884         }
7885
7886         return 0;
7887
7888 mask_err:
7889         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7890
7891         return -EINVAL;
7892 }
7893
7894 /*
7895  * Set global configurations of hash function type and symmetric hash enable
7896  * per flow type (pctype). Note any modifying global configuration will affect
7897  * all the ports on the same NIC.
7898  */
7899 static int
7900 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7901                                    struct rte_eth_hash_global_conf *g_cfg)
7902 {
7903         int ret;
7904         uint16_t i;
7905         uint32_t reg;
7906         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7907         enum i40e_filter_pctype pctype;
7908
7909         /* Check the input parameters */
7910         ret = i40e_hash_global_config_check(g_cfg);
7911         if (ret < 0)
7912                 return ret;
7913
7914         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7915                 if (!(mask0 & (1UL << i)))
7916                         continue;
7917                 mask0 &= ~(1UL << i);
7918                 /* if flowtype is invalid, continue */
7919                 if (!I40E_VALID_FLOW(i))
7920                         continue;
7921                 pctype = i40e_flowtype_to_pctype(i);
7922                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7923                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7924                 if (hw->mac.type == I40E_MAC_X722) {
7925                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7926                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7927                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7928                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7929                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7930                                   reg);
7931                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7932                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7933                                   reg);
7934                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7935                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7936                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7937                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7938                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7939                                   reg);
7940                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7941                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7942                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7943                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7944                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7945                                   reg);
7946                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7947                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7948                                   reg);
7949                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7950                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7951                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7952                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7953                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7954                                   reg);
7955                         } else {
7956                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7957                                   reg);
7958                         }
7959                 } else {
7960                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7961                 }
7962         }
7963
7964         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7965         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7966                 /* Toeplitz */
7967                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7968                         PMD_DRV_LOG(DEBUG,
7969                                 "Hash function already set to Toeplitz");
7970                         goto out;
7971                 }
7972                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7973         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7974                 /* Simple XOR */
7975                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7976                         PMD_DRV_LOG(DEBUG,
7977                                 "Hash function already set to Simple XOR");
7978                         goto out;
7979                 }
7980                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7981         } else
7982                 /* Use the default, and keep it as it is */
7983                 goto out;
7984
7985         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7986
7987 out:
7988         I40E_WRITE_FLUSH(hw);
7989
7990         return 0;
7991 }
7992
7993 /**
7994  * Valid input sets for hash and flow director filters per PCTYPE
7995  */
7996 static uint64_t
7997 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7998                 enum rte_filter_type filter)
7999 {
8000         uint64_t valid;
8001
8002         static const uint64_t valid_hash_inset_table[] = {
8003                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8004                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8005                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8007                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8008                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8009                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8010                         I40E_INSET_FLEX_PAYLOAD,
8011                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8012                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8013                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8014                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8015                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8016                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8017                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8018                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8019                         I40E_INSET_FLEX_PAYLOAD,
8020                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8021                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8022                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8023                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8024                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8025                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8026                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8027                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8028                         I40E_INSET_FLEX_PAYLOAD,
8029                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8030                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8031                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8033                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8034                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8035                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8036                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8037                         I40E_INSET_FLEX_PAYLOAD,
8038                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8039                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8040                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8041                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8042                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8043                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8044                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8045                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8046                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8047                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8048                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8049                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8050                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8051                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8052                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8053                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8054                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8055                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8056                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8057                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8058                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8059                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8060                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8061                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8062                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8063                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8064                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8065                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8066                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8067                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8069                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8070                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8071                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8072                         I40E_INSET_FLEX_PAYLOAD,
8073                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8074                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8075                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8076                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8077                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8078                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8079                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8080                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8081                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8082                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8083                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8084                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8085                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8086                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8087                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8088                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8089                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8090                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8091                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8092                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8093                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8094                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8095                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8096                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8097                         I40E_INSET_FLEX_PAYLOAD,
8098                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8099                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8100                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8101                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8102                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8103                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8104                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8105                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8106                         I40E_INSET_FLEX_PAYLOAD,
8107                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8108                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8109                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8110                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8111                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8112                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8113                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8114                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8115                         I40E_INSET_FLEX_PAYLOAD,
8116                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8120                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8121                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8122                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8123                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8124                         I40E_INSET_FLEX_PAYLOAD,
8125                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8129                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8130                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8131                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8132                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8133                         I40E_INSET_FLEX_PAYLOAD,
8134                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8135                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8136                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8138                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8139                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8140                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8141                         I40E_INSET_FLEX_PAYLOAD,
8142                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8146                         I40E_INSET_FLEX_PAYLOAD,
8147         };
8148
8149         /**
8150          * Flow director supports only fields defined in
8151          * union rte_eth_fdir_flow.
8152          */
8153         static const uint64_t valid_fdir_inset_table[] = {
8154                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8155                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8156                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8157                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8158                 I40E_INSET_IPV4_TTL,
8159                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8161                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8162                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8163                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8164                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8166                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8167                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8168                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8169                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8170                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8171                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8172                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8173                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8174                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8175                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8176                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8177                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8178                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8179                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8180                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8181                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8182                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8183                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8184                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8185                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8186                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8187                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8188                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8189                 I40E_INSET_SCTP_VT,
8190                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8191                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8192                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8193                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8194                 I40E_INSET_IPV4_TTL,
8195                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8196                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8197                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8198                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8199                 I40E_INSET_IPV6_HOP_LIMIT,
8200                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8201                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8202                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8203                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8204                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8205                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8206                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8207                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8208                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8209                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8210                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8211                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8212                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8213                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8214                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8215                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8216                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8217                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8218                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8219                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8220                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8221                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8222                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8223                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8224                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8225                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8226                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8227                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8228                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8229                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8230                 I40E_INSET_SCTP_VT,
8231                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8232                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8233                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8234                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8235                 I40E_INSET_IPV6_HOP_LIMIT,
8236                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8237                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8238                 I40E_INSET_LAST_ETHER_TYPE,
8239         };
8240
8241         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8242                 return 0;
8243         if (filter == RTE_ETH_FILTER_HASH)
8244                 valid = valid_hash_inset_table[pctype];
8245         else
8246                 valid = valid_fdir_inset_table[pctype];
8247
8248         return valid;
8249 }
8250
8251 /**
8252  * Validate if the input set is allowed for a specific PCTYPE
8253  */
8254 int
8255 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8256                 enum rte_filter_type filter, uint64_t inset)
8257 {
8258         uint64_t valid;
8259
8260         valid = i40e_get_valid_input_set(pctype, filter);
8261         if (inset & (~valid))
8262                 return -EINVAL;
8263
8264         return 0;
8265 }
8266
8267 /* default input set fields combination per pctype */
8268 uint64_t
8269 i40e_get_default_input_set(uint16_t pctype)
8270 {
8271         static const uint64_t default_inset_table[] = {
8272                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8273                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8274                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8275                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8276                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8277                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8278                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8280                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8281                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8282                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8283                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8284                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8285                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8287                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8288                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8289                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8290                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8291                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8292                         I40E_INSET_SCTP_VT,
8293                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8294                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8295                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8296                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8297                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8298                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8299                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8300                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8301                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8302                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8303                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8304                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8305                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8306                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8307                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8308                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8309                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8310                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8311                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8312                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8313                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8314                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8315                         I40E_INSET_SCTP_VT,
8316                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8317                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8318                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8319                         I40E_INSET_LAST_ETHER_TYPE,
8320         };
8321
8322         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8323                 return 0;
8324
8325         return default_inset_table[pctype];
8326 }
8327
8328 /**
8329  * Parse the input set from index to logical bit masks
8330  */
8331 static int
8332 i40e_parse_input_set(uint64_t *inset,
8333                      enum i40e_filter_pctype pctype,
8334                      enum rte_eth_input_set_field *field,
8335                      uint16_t size)
8336 {
8337         uint16_t i, j;
8338         int ret = -EINVAL;
8339
8340         static const struct {
8341                 enum rte_eth_input_set_field field;
8342                 uint64_t inset;
8343         } inset_convert_table[] = {
8344                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8345                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8346                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8347                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8348                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8349                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8350                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8351                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8352                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8353                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8354                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8355                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8356                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8357                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8358                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8359                         I40E_INSET_IPV6_NEXT_HDR},
8360                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8361                         I40E_INSET_IPV6_HOP_LIMIT},
8362                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8363                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8364                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8365                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8366                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8367                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8368                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8369                         I40E_INSET_SCTP_VT},
8370                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8371                         I40E_INSET_TUNNEL_DMAC},
8372                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8373                         I40E_INSET_VLAN_TUNNEL},
8374                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8375                         I40E_INSET_TUNNEL_ID},
8376                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8377                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8378                         I40E_INSET_FLEX_PAYLOAD_W1},
8379                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8380                         I40E_INSET_FLEX_PAYLOAD_W2},
8381                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8382                         I40E_INSET_FLEX_PAYLOAD_W3},
8383                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8384                         I40E_INSET_FLEX_PAYLOAD_W4},
8385                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8386                         I40E_INSET_FLEX_PAYLOAD_W5},
8387                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8388                         I40E_INSET_FLEX_PAYLOAD_W6},
8389                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8390                         I40E_INSET_FLEX_PAYLOAD_W7},
8391                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8392                         I40E_INSET_FLEX_PAYLOAD_W8},
8393         };
8394
8395         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8396                 return ret;
8397
8398         /* Only one item allowed for default or all */
8399         if (size == 1) {
8400                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8401                         *inset = i40e_get_default_input_set(pctype);
8402                         return 0;
8403                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8404                         *inset = I40E_INSET_NONE;
8405                         return 0;
8406                 }
8407         }
8408
8409         for (i = 0, *inset = 0; i < size; i++) {
8410                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8411                         if (field[i] == inset_convert_table[j].field) {
8412                                 *inset |= inset_convert_table[j].inset;
8413                                 break;
8414                         }
8415                 }
8416
8417                 /* It contains unsupported input set, return immediately */
8418                 if (j == RTE_DIM(inset_convert_table))
8419                         return ret;
8420         }
8421
8422         return 0;
8423 }
8424
8425 /**
8426  * Translate the input set from bit masks to register aware bit masks
8427  * and vice versa
8428  */
8429 uint64_t
8430 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8431 {
8432         uint64_t val = 0;
8433         uint16_t i;
8434
8435         struct inset_map {
8436                 uint64_t inset;
8437                 uint64_t inset_reg;
8438         };
8439
8440         static const struct inset_map inset_map_common[] = {
8441                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8442                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8443                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8444                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8445                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8446                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8447                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8448                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8449                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8450                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8451                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8452                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8453                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8454                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8455                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8456                 {I40E_INSET_TUNNEL_DMAC,
8457                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8458                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8459                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8460                 {I40E_INSET_TUNNEL_SRC_PORT,
8461                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8462                 {I40E_INSET_TUNNEL_DST_PORT,
8463                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8464                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8465                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8466                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8467                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8468                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8469                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8470                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8471                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8472                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8473         };
8474
8475     /* some different registers map in x722*/
8476         static const struct inset_map inset_map_diff_x722[] = {
8477                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8478                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8479                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8480                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8481         };
8482
8483         static const struct inset_map inset_map_diff_not_x722[] = {
8484                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8485                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8486                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8487                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8488         };
8489
8490         if (input == 0)
8491                 return val;
8492
8493         /* Translate input set to register aware inset */
8494         if (type == I40E_MAC_X722) {
8495                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8496                         if (input & inset_map_diff_x722[i].inset)
8497                                 val |= inset_map_diff_x722[i].inset_reg;
8498                 }
8499         } else {
8500                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8501                         if (input & inset_map_diff_not_x722[i].inset)
8502                                 val |= inset_map_diff_not_x722[i].inset_reg;
8503                 }
8504         }
8505
8506         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8507                 if (input & inset_map_common[i].inset)
8508                         val |= inset_map_common[i].inset_reg;
8509         }
8510
8511         return val;
8512 }
8513
8514 int
8515 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8516 {
8517         uint8_t i, idx = 0;
8518         uint64_t inset_need_mask = inset;
8519
8520         static const struct {
8521                 uint64_t inset;
8522                 uint32_t mask;
8523         } inset_mask_map[] = {
8524                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8525                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8526                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8527                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8528                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8529                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8530                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8531                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8532         };
8533
8534         if (!inset || !mask || !nb_elem)
8535                 return 0;
8536
8537         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8538                 /* Clear the inset bit, if no MASK is required,
8539                  * for example proto + ttl
8540                  */
8541                 if ((inset & inset_mask_map[i].inset) ==
8542                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8543                         inset_need_mask &= ~inset_mask_map[i].inset;
8544                 if (!inset_need_mask)
8545                         return 0;
8546         }
8547         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8548                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8549                     inset_mask_map[i].inset) {
8550                         if (idx >= nb_elem) {
8551                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8552                                 return -EINVAL;
8553                         }
8554                         mask[idx] = inset_mask_map[i].mask;
8555                         idx++;
8556                 }
8557         }
8558
8559         return idx;
8560 }
8561
8562 void
8563 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8564 {
8565         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8566
8567         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8568         if (reg != val)
8569                 i40e_write_rx_ctl(hw, addr, val);
8570         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8571                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8572 }
8573
8574 static void
8575 i40e_filter_input_set_init(struct i40e_pf *pf)
8576 {
8577         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8578         enum i40e_filter_pctype pctype;
8579         uint64_t input_set, inset_reg;
8580         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8581         int num, i;
8582
8583         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8584              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8585                 if (hw->mac.type == I40E_MAC_X722) {
8586                         if (!I40E_VALID_PCTYPE_X722(pctype))
8587                                 continue;
8588                 } else {
8589                         if (!I40E_VALID_PCTYPE(pctype))
8590                                 continue;
8591                 }
8592
8593                 input_set = i40e_get_default_input_set(pctype);
8594
8595                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8596                                                    I40E_INSET_MASK_NUM_REG);
8597                 if (num < 0)
8598                         return;
8599                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8600                                         input_set);
8601
8602                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8603                                       (uint32_t)(inset_reg & UINT32_MAX));
8604                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8605                                      (uint32_t)((inset_reg >>
8606                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8607                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8608                                       (uint32_t)(inset_reg & UINT32_MAX));
8609                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8610                                      (uint32_t)((inset_reg >>
8611                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8612
8613                 for (i = 0; i < num; i++) {
8614                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8615                                              mask_reg[i]);
8616                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8617                                              mask_reg[i]);
8618                 }
8619                 /*clear unused mask registers of the pctype */
8620                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8621                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8622                                              0);
8623                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8624                                              0);
8625                 }
8626                 I40E_WRITE_FLUSH(hw);
8627
8628                 /* store the default input set */
8629                 pf->hash_input_set[pctype] = input_set;
8630                 pf->fdir.input_set[pctype] = input_set;
8631         }
8632 }
8633
8634 int
8635 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8636                          struct rte_eth_input_set_conf *conf)
8637 {
8638         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8639         enum i40e_filter_pctype pctype;
8640         uint64_t input_set, inset_reg = 0;
8641         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8642         int ret, i, num;
8643
8644         if (!conf) {
8645                 PMD_DRV_LOG(ERR, "Invalid pointer");
8646                 return -EFAULT;
8647         }
8648         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8649             conf->op != RTE_ETH_INPUT_SET_ADD) {
8650                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8651                 return -EINVAL;
8652         }
8653
8654         if (!I40E_VALID_FLOW(conf->flow_type)) {
8655                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8656                 return -EINVAL;
8657         }
8658
8659         if (hw->mac.type == I40E_MAC_X722) {
8660                 /* get translated pctype value in fd pctype register */
8661                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8662                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8663                         conf->flow_type)));
8664         } else
8665                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8666
8667         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8668                                    conf->inset_size);
8669         if (ret) {
8670                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8671                 return -EINVAL;
8672         }
8673         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8674                                     input_set) != 0) {
8675                 PMD_DRV_LOG(ERR, "Invalid input set");
8676                 return -EINVAL;
8677         }
8678         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8679                 /* get inset value in register */
8680                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8681                 inset_reg <<= I40E_32_BIT_WIDTH;
8682                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8683                 input_set |= pf->hash_input_set[pctype];
8684         }
8685         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8686                                            I40E_INSET_MASK_NUM_REG);
8687         if (num < 0)
8688                 return -EINVAL;
8689
8690         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8691
8692         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8693                               (uint32_t)(inset_reg & UINT32_MAX));
8694         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8695                              (uint32_t)((inset_reg >>
8696                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8697
8698         for (i = 0; i < num; i++)
8699                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8700                                      mask_reg[i]);
8701         /*clear unused mask registers of the pctype */
8702         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8703                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8704                                      0);
8705         I40E_WRITE_FLUSH(hw);
8706
8707         pf->hash_input_set[pctype] = input_set;
8708         return 0;
8709 }
8710
8711 int
8712 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8713                          struct rte_eth_input_set_conf *conf)
8714 {
8715         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8716         enum i40e_filter_pctype pctype;
8717         uint64_t input_set, inset_reg = 0;
8718         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8719         int ret, i, num;
8720
8721         if (!hw || !conf) {
8722                 PMD_DRV_LOG(ERR, "Invalid pointer");
8723                 return -EFAULT;
8724         }
8725         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8726             conf->op != RTE_ETH_INPUT_SET_ADD) {
8727                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8728                 return -EINVAL;
8729         }
8730
8731         if (!I40E_VALID_FLOW(conf->flow_type)) {
8732                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8733                 return -EINVAL;
8734         }
8735
8736         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8737
8738         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8739                                    conf->inset_size);
8740         if (ret) {
8741                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8742                 return -EINVAL;
8743         }
8744         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8745                                     input_set) != 0) {
8746                 PMD_DRV_LOG(ERR, "Invalid input set");
8747                 return -EINVAL;
8748         }
8749
8750         /* get inset value in register */
8751         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8752         inset_reg <<= I40E_32_BIT_WIDTH;
8753         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8754
8755         /* Can not change the inset reg for flex payload for fdir,
8756          * it is done by writing I40E_PRTQF_FD_FLXINSET
8757          * in i40e_set_flex_mask_on_pctype.
8758          */
8759         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8760                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8761         else
8762                 input_set |= pf->fdir.input_set[pctype];
8763         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8764                                            I40E_INSET_MASK_NUM_REG);
8765         if (num < 0)
8766                 return -EINVAL;
8767
8768         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8769
8770         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8771                               (uint32_t)(inset_reg & UINT32_MAX));
8772         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8773                              (uint32_t)((inset_reg >>
8774                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8775
8776         for (i = 0; i < num; i++)
8777                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8778                                      mask_reg[i]);
8779         /*clear unused mask registers of the pctype */
8780         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8781                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8782                                      0);
8783         I40E_WRITE_FLUSH(hw);
8784
8785         pf->fdir.input_set[pctype] = input_set;
8786         return 0;
8787 }
8788
8789 static int
8790 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8791 {
8792         int ret = 0;
8793
8794         if (!hw || !info) {
8795                 PMD_DRV_LOG(ERR, "Invalid pointer");
8796                 return -EFAULT;
8797         }
8798
8799         switch (info->info_type) {
8800         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8801                 i40e_get_symmetric_hash_enable_per_port(hw,
8802                                         &(info->info.enable));
8803                 break;
8804         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8805                 ret = i40e_get_hash_filter_global_config(hw,
8806                                 &(info->info.global_conf));
8807                 break;
8808         default:
8809                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8810                                                         info->info_type);
8811                 ret = -EINVAL;
8812                 break;
8813         }
8814
8815         return ret;
8816 }
8817
8818 static int
8819 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8820 {
8821         int ret = 0;
8822
8823         if (!hw || !info) {
8824                 PMD_DRV_LOG(ERR, "Invalid pointer");
8825                 return -EFAULT;
8826         }
8827
8828         switch (info->info_type) {
8829         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8830                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8831                 break;
8832         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8833                 ret = i40e_set_hash_filter_global_config(hw,
8834                                 &(info->info.global_conf));
8835                 break;
8836         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8837                 ret = i40e_hash_filter_inset_select(hw,
8838                                                &(info->info.input_set_conf));
8839                 break;
8840
8841         default:
8842                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8843                                                         info->info_type);
8844                 ret = -EINVAL;
8845                 break;
8846         }
8847
8848         return ret;
8849 }
8850
8851 /* Operations for hash function */
8852 static int
8853 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8854                       enum rte_filter_op filter_op,
8855                       void *arg)
8856 {
8857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8858         int ret = 0;
8859
8860         switch (filter_op) {
8861         case RTE_ETH_FILTER_NOP:
8862                 break;
8863         case RTE_ETH_FILTER_GET:
8864                 ret = i40e_hash_filter_get(hw,
8865                         (struct rte_eth_hash_filter_info *)arg);
8866                 break;
8867         case RTE_ETH_FILTER_SET:
8868                 ret = i40e_hash_filter_set(hw,
8869                         (struct rte_eth_hash_filter_info *)arg);
8870                 break;
8871         default:
8872                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8873                                                                 filter_op);
8874                 ret = -ENOTSUP;
8875                 break;
8876         }
8877
8878         return ret;
8879 }
8880
8881 /* Convert ethertype filter structure */
8882 static int
8883 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8884                               struct i40e_ethertype_filter *filter)
8885 {
8886         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8887         filter->input.ether_type = input->ether_type;
8888         filter->flags = input->flags;
8889         filter->queue = input->queue;
8890
8891         return 0;
8892 }
8893
8894 /* Check if there exists the ehtertype filter */
8895 struct i40e_ethertype_filter *
8896 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8897                                 const struct i40e_ethertype_filter_input *input)
8898 {
8899         int ret;
8900
8901         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8902         if (ret < 0)
8903                 return NULL;
8904
8905         return ethertype_rule->hash_map[ret];
8906 }
8907
8908 /* Add ethertype filter in SW list */
8909 static int
8910 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8911                                 struct i40e_ethertype_filter *filter)
8912 {
8913         struct i40e_ethertype_rule *rule = &pf->ethertype;
8914         int ret;
8915
8916         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8917         if (ret < 0) {
8918                 PMD_DRV_LOG(ERR,
8919                             "Failed to insert ethertype filter"
8920                             " to hash table %d!",
8921                             ret);
8922                 return ret;
8923         }
8924         rule->hash_map[ret] = filter;
8925
8926         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8927
8928         return 0;
8929 }
8930
8931 /* Delete ethertype filter in SW list */
8932 int
8933 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8934                              struct i40e_ethertype_filter_input *input)
8935 {
8936         struct i40e_ethertype_rule *rule = &pf->ethertype;
8937         struct i40e_ethertype_filter *filter;
8938         int ret;
8939
8940         ret = rte_hash_del_key(rule->hash_table, input);
8941         if (ret < 0) {
8942                 PMD_DRV_LOG(ERR,
8943                             "Failed to delete ethertype filter"
8944                             " to hash table %d!",
8945                             ret);
8946                 return ret;
8947         }
8948         filter = rule->hash_map[ret];
8949         rule->hash_map[ret] = NULL;
8950
8951         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8952         rte_free(filter);
8953
8954         return 0;
8955 }
8956
8957 /*
8958  * Configure ethertype filter, which can director packet by filtering
8959  * with mac address and ether_type or only ether_type
8960  */
8961 int
8962 i40e_ethertype_filter_set(struct i40e_pf *pf,
8963                         struct rte_eth_ethertype_filter *filter,
8964                         bool add)
8965 {
8966         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8967         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8968         struct i40e_ethertype_filter *ethertype_filter, *node;
8969         struct i40e_ethertype_filter check_filter;
8970         struct i40e_control_filter_stats stats;
8971         uint16_t flags = 0;
8972         int ret;
8973
8974         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8975                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8976                 return -EINVAL;
8977         }
8978         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8979                 filter->ether_type == ETHER_TYPE_IPv6) {
8980                 PMD_DRV_LOG(ERR,
8981                         "unsupported ether_type(0x%04x) in control packet filter.",
8982                         filter->ether_type);
8983                 return -EINVAL;
8984         }
8985         if (filter->ether_type == ETHER_TYPE_VLAN)
8986                 PMD_DRV_LOG(WARNING,
8987                         "filter vlan ether_type in first tag is not supported.");
8988
8989         /* Check if there is the filter in SW list */
8990         memset(&check_filter, 0, sizeof(check_filter));
8991         i40e_ethertype_filter_convert(filter, &check_filter);
8992         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8993                                                &check_filter.input);
8994         if (add && node) {
8995                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8996                 return -EINVAL;
8997         }
8998
8999         if (!add && !node) {
9000                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9001                 return -EINVAL;
9002         }
9003
9004         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9005                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9006         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9007                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9008         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9009
9010         memset(&stats, 0, sizeof(stats));
9011         ret = i40e_aq_add_rem_control_packet_filter(hw,
9012                         filter->mac_addr.addr_bytes,
9013                         filter->ether_type, flags,
9014                         pf->main_vsi->seid,
9015                         filter->queue, add, &stats, NULL);
9016
9017         PMD_DRV_LOG(INFO,
9018                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9019                 ret, stats.mac_etype_used, stats.etype_used,
9020                 stats.mac_etype_free, stats.etype_free);
9021         if (ret < 0)
9022                 return -ENOSYS;
9023
9024         /* Add or delete a filter in SW list */
9025         if (add) {
9026                 ethertype_filter = rte_zmalloc("ethertype_filter",
9027                                        sizeof(*ethertype_filter), 0);
9028                 rte_memcpy(ethertype_filter, &check_filter,
9029                            sizeof(check_filter));
9030                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9031         } else {
9032                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9033         }
9034
9035         return ret;
9036 }
9037
9038 /*
9039  * Handle operations for ethertype filter.
9040  */
9041 static int
9042 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9043                                 enum rte_filter_op filter_op,
9044                                 void *arg)
9045 {
9046         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9047         int ret = 0;
9048
9049         if (filter_op == RTE_ETH_FILTER_NOP)
9050                 return ret;
9051
9052         if (arg == NULL) {
9053                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9054                             filter_op);
9055                 return -EINVAL;
9056         }
9057
9058         switch (filter_op) {
9059         case RTE_ETH_FILTER_ADD:
9060                 ret = i40e_ethertype_filter_set(pf,
9061                         (struct rte_eth_ethertype_filter *)arg,
9062                         TRUE);
9063                 break;
9064         case RTE_ETH_FILTER_DELETE:
9065                 ret = i40e_ethertype_filter_set(pf,
9066                         (struct rte_eth_ethertype_filter *)arg,
9067                         FALSE);
9068                 break;
9069         default:
9070                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9071                 ret = -ENOSYS;
9072                 break;
9073         }
9074         return ret;
9075 }
9076
9077 static int
9078 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9079                      enum rte_filter_type filter_type,
9080                      enum rte_filter_op filter_op,
9081                      void *arg)
9082 {
9083         int ret = 0;
9084
9085         if (dev == NULL)
9086                 return -EINVAL;
9087
9088         switch (filter_type) {
9089         case RTE_ETH_FILTER_NONE:
9090                 /* For global configuration */
9091                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9092                 break;
9093         case RTE_ETH_FILTER_HASH:
9094                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9095                 break;
9096         case RTE_ETH_FILTER_MACVLAN:
9097                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9098                 break;
9099         case RTE_ETH_FILTER_ETHERTYPE:
9100                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9101                 break;
9102         case RTE_ETH_FILTER_TUNNEL:
9103                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9104                 break;
9105         case RTE_ETH_FILTER_FDIR:
9106                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9107                 break;
9108         case RTE_ETH_FILTER_GENERIC:
9109                 if (filter_op != RTE_ETH_FILTER_GET)
9110                         return -EINVAL;
9111                 *(const void **)arg = &i40e_flow_ops;
9112                 break;
9113         default:
9114                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9115                                                         filter_type);
9116                 ret = -EINVAL;
9117                 break;
9118         }
9119
9120         return ret;
9121 }
9122
9123 /*
9124  * Check and enable Extended Tag.
9125  * Enabling Extended Tag is important for 40G performance.
9126  */
9127 static void
9128 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9129 {
9130         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9131         uint32_t buf = 0;
9132         int ret;
9133
9134         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9135                                       PCI_DEV_CAP_REG);
9136         if (ret < 0) {
9137                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9138                             PCI_DEV_CAP_REG);
9139                 return;
9140         }
9141         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9142                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9143                 return;
9144         }
9145
9146         buf = 0;
9147         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9148                                       PCI_DEV_CTRL_REG);
9149         if (ret < 0) {
9150                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9151                             PCI_DEV_CTRL_REG);
9152                 return;
9153         }
9154         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9155                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9156                 return;
9157         }
9158         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9159         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9160                                        PCI_DEV_CTRL_REG);
9161         if (ret < 0) {
9162                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9163                             PCI_DEV_CTRL_REG);
9164                 return;
9165         }
9166 }
9167
9168 /*
9169  * As some registers wouldn't be reset unless a global hardware reset,
9170  * hardware initialization is needed to put those registers into an
9171  * expected initial state.
9172  */
9173 static void
9174 i40e_hw_init(struct rte_eth_dev *dev)
9175 {
9176         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9177
9178         i40e_enable_extended_tag(dev);
9179
9180         /* clear the PF Queue Filter control register */
9181         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9182
9183         /* Disable symmetric hash per port */
9184         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9185 }
9186
9187 enum i40e_filter_pctype
9188 i40e_flowtype_to_pctype(uint16_t flow_type)
9189 {
9190         static const enum i40e_filter_pctype pctype_table[] = {
9191                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9192                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9193                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9194                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9195                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9196                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9197                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9198                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9199                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9200                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9201                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9202                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9203                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9204                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9205                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9206                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9207                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9208                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9209                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9210         };
9211
9212         return pctype_table[flow_type];
9213 }
9214
9215 uint16_t
9216 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9217 {
9218         static const uint16_t flowtype_table[] = {
9219                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9220                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9221                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9222                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9223                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9224                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9225                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9226                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9227                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9228                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9229                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9230                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9231                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9232                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9233                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9234                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9235                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9236                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9237                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9238                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9239                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9240                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9241                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9242                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9243                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9244                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9245                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9246                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9247                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9248                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9249                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9250         };
9251
9252         return flowtype_table[pctype];
9253 }
9254
9255 /*
9256  * On X710, performance number is far from the expectation on recent firmware
9257  * versions; on XL710, performance number is also far from the expectation on
9258  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9259  * mode is enabled and port MAC address is equal to the packet destination MAC
9260  * address. The fix for this issue may not be integrated in the following
9261  * firmware version. So the workaround in software driver is needed. It needs
9262  * to modify the initial values of 3 internal only registers for both X710 and
9263  * XL710. Note that the values for X710 or XL710 could be different, and the
9264  * workaround can be removed when it is fixed in firmware in the future.
9265  */
9266
9267 /* For both X710 and XL710 */
9268 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9269 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9270 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9271
9272 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9273 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9274
9275 /* For X722 */
9276 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9277 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9278
9279 /* For X710 */
9280 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9281 /* For XL710 */
9282 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9283 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9284
9285 static int
9286 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9287 {
9288         enum i40e_status_code status;
9289         struct i40e_aq_get_phy_abilities_resp phy_ab;
9290         int ret = -ENOTSUP;
9291         int retries = 0;
9292
9293         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9294                                               NULL);
9295
9296         while (status) {
9297                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9298                         status);
9299                 retries++;
9300                 rte_delay_us(100000);
9301                 if  (retries < 5)
9302                         status = i40e_aq_get_phy_capabilities(hw, false,
9303                                         true, &phy_ab, NULL);
9304                 else
9305                         return ret;
9306         }
9307         return 0;
9308 }
9309
9310 static void
9311 i40e_configure_registers(struct i40e_hw *hw)
9312 {
9313         static struct {
9314                 uint32_t addr;
9315                 uint64_t val;
9316         } reg_table[] = {
9317                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9318                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9319                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9320         };
9321         uint64_t reg;
9322         uint32_t i;
9323         int ret;
9324
9325         for (i = 0; i < RTE_DIM(reg_table); i++) {
9326                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9327                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9328                                 reg_table[i].val =
9329                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9330                         else /* For X710/XL710/XXV710 */
9331                                 if (hw->aq.fw_maj_ver < 6)
9332                                         reg_table[i].val =
9333                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9334                                 else
9335                                         reg_table[i].val =
9336                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9337                 }
9338
9339                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9340                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9341                                 reg_table[i].val =
9342                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9343                         else /* For X710/XL710/XXV710 */
9344                                 reg_table[i].val =
9345                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9346                 }
9347
9348                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9349                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9350                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9351                                 reg_table[i].val =
9352                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9353                         else /* For X710 */
9354                                 reg_table[i].val =
9355                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9356                 }
9357
9358                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9359                                                         &reg, NULL);
9360                 if (ret < 0) {
9361                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9362                                                         reg_table[i].addr);
9363                         break;
9364                 }
9365                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9366                                                 reg_table[i].addr, reg);
9367                 if (reg == reg_table[i].val)
9368                         continue;
9369
9370                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9371                                                 reg_table[i].val, NULL);
9372                 if (ret < 0) {
9373                         PMD_DRV_LOG(ERR,
9374                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9375                                 reg_table[i].val, reg_table[i].addr);
9376                         break;
9377                 }
9378                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9379                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9380         }
9381 }
9382
9383 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9384 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9385 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9386 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9387 static int
9388 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9389 {
9390         uint32_t reg;
9391         int ret;
9392
9393         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9394                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9395                 return -EINVAL;
9396         }
9397
9398         /* Configure for double VLAN RX stripping */
9399         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9400         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9401                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9402                 ret = i40e_aq_debug_write_register(hw,
9403                                                    I40E_VSI_TSR(vsi->vsi_id),
9404                                                    reg, NULL);
9405                 if (ret < 0) {
9406                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9407                                     vsi->vsi_id);
9408                         return I40E_ERR_CONFIG;
9409                 }
9410         }
9411
9412         /* Configure for double VLAN TX insertion */
9413         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9414         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9415                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9416                 ret = i40e_aq_debug_write_register(hw,
9417                                                    I40E_VSI_L2TAGSTXVALID(
9418                                                    vsi->vsi_id), reg, NULL);
9419                 if (ret < 0) {
9420                         PMD_DRV_LOG(ERR,
9421                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9422                                 vsi->vsi_id);
9423                         return I40E_ERR_CONFIG;
9424                 }
9425         }
9426
9427         return 0;
9428 }
9429
9430 /**
9431  * i40e_aq_add_mirror_rule
9432  * @hw: pointer to the hardware structure
9433  * @seid: VEB seid to add mirror rule to
9434  * @dst_id: destination vsi seid
9435  * @entries: Buffer which contains the entities to be mirrored
9436  * @count: number of entities contained in the buffer
9437  * @rule_id:the rule_id of the rule to be added
9438  *
9439  * Add a mirror rule for a given veb.
9440  *
9441  **/
9442 static enum i40e_status_code
9443 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9444                         uint16_t seid, uint16_t dst_id,
9445                         uint16_t rule_type, uint16_t *entries,
9446                         uint16_t count, uint16_t *rule_id)
9447 {
9448         struct i40e_aq_desc desc;
9449         struct i40e_aqc_add_delete_mirror_rule cmd;
9450         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9451                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9452                 &desc.params.raw;
9453         uint16_t buff_len;
9454         enum i40e_status_code status;
9455
9456         i40e_fill_default_direct_cmd_desc(&desc,
9457                                           i40e_aqc_opc_add_mirror_rule);
9458         memset(&cmd, 0, sizeof(cmd));
9459
9460         buff_len = sizeof(uint16_t) * count;
9461         desc.datalen = rte_cpu_to_le_16(buff_len);
9462         if (buff_len > 0)
9463                 desc.flags |= rte_cpu_to_le_16(
9464                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9465         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9466                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9467         cmd.num_entries = rte_cpu_to_le_16(count);
9468         cmd.seid = rte_cpu_to_le_16(seid);
9469         cmd.destination = rte_cpu_to_le_16(dst_id);
9470
9471         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9472         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9473         PMD_DRV_LOG(INFO,
9474                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9475                 hw->aq.asq_last_status, resp->rule_id,
9476                 resp->mirror_rules_used, resp->mirror_rules_free);
9477         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9478
9479         return status;
9480 }
9481
9482 /**
9483  * i40e_aq_del_mirror_rule
9484  * @hw: pointer to the hardware structure
9485  * @seid: VEB seid to add mirror rule to
9486  * @entries: Buffer which contains the entities to be mirrored
9487  * @count: number of entities contained in the buffer
9488  * @rule_id:the rule_id of the rule to be delete
9489  *
9490  * Delete a mirror rule for a given veb.
9491  *
9492  **/
9493 static enum i40e_status_code
9494 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9495                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9496                 uint16_t count, uint16_t rule_id)
9497 {
9498         struct i40e_aq_desc desc;
9499         struct i40e_aqc_add_delete_mirror_rule cmd;
9500         uint16_t buff_len = 0;
9501         enum i40e_status_code status;
9502         void *buff = NULL;
9503
9504         i40e_fill_default_direct_cmd_desc(&desc,
9505                                           i40e_aqc_opc_delete_mirror_rule);
9506         memset(&cmd, 0, sizeof(cmd));
9507         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9508                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9509                                                           I40E_AQ_FLAG_RD));
9510                 cmd.num_entries = count;
9511                 buff_len = sizeof(uint16_t) * count;
9512                 desc.datalen = rte_cpu_to_le_16(buff_len);
9513                 buff = (void *)entries;
9514         } else
9515                 /* rule id is filled in destination field for deleting mirror rule */
9516                 cmd.destination = rte_cpu_to_le_16(rule_id);
9517
9518         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9519                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9520         cmd.seid = rte_cpu_to_le_16(seid);
9521
9522         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9523         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9524
9525         return status;
9526 }
9527
9528 /**
9529  * i40e_mirror_rule_set
9530  * @dev: pointer to the hardware structure
9531  * @mirror_conf: mirror rule info
9532  * @sw_id: mirror rule's sw_id
9533  * @on: enable/disable
9534  *
9535  * set a mirror rule.
9536  *
9537  **/
9538 static int
9539 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9540                         struct rte_eth_mirror_conf *mirror_conf,
9541                         uint8_t sw_id, uint8_t on)
9542 {
9543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9544         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9545         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9546         struct i40e_mirror_rule *parent = NULL;
9547         uint16_t seid, dst_seid, rule_id;
9548         uint16_t i, j = 0;
9549         int ret;
9550
9551         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9552
9553         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9554                 PMD_DRV_LOG(ERR,
9555                         "mirror rule can not be configured without veb or vfs.");
9556                 return -ENOSYS;
9557         }
9558         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9559                 PMD_DRV_LOG(ERR, "mirror table is full.");
9560                 return -ENOSPC;
9561         }
9562         if (mirror_conf->dst_pool > pf->vf_num) {
9563                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9564                                  mirror_conf->dst_pool);
9565                 return -EINVAL;
9566         }
9567
9568         seid = pf->main_vsi->veb->seid;
9569
9570         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9571                 if (sw_id <= it->index) {
9572                         mirr_rule = it;
9573                         break;
9574                 }
9575                 parent = it;
9576         }
9577         if (mirr_rule && sw_id == mirr_rule->index) {
9578                 if (on) {
9579                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9580                         return -EEXIST;
9581                 } else {
9582                         ret = i40e_aq_del_mirror_rule(hw, seid,
9583                                         mirr_rule->rule_type,
9584                                         mirr_rule->entries,
9585                                         mirr_rule->num_entries, mirr_rule->id);
9586                         if (ret < 0) {
9587                                 PMD_DRV_LOG(ERR,
9588                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9589                                         ret, hw->aq.asq_last_status);
9590                                 return -ENOSYS;
9591                         }
9592                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9593                         rte_free(mirr_rule);
9594                         pf->nb_mirror_rule--;
9595                         return 0;
9596                 }
9597         } else if (!on) {
9598                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9599                 return -ENOENT;
9600         }
9601
9602         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9603                                 sizeof(struct i40e_mirror_rule) , 0);
9604         if (!mirr_rule) {
9605                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9606                 return I40E_ERR_NO_MEMORY;
9607         }
9608         switch (mirror_conf->rule_type) {
9609         case ETH_MIRROR_VLAN:
9610                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9611                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9612                                 mirr_rule->entries[j] =
9613                                         mirror_conf->vlan.vlan_id[i];
9614                                 j++;
9615                         }
9616                 }
9617                 if (j == 0) {
9618                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9619                         rte_free(mirr_rule);
9620                         return -EINVAL;
9621                 }
9622                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9623                 break;
9624         case ETH_MIRROR_VIRTUAL_POOL_UP:
9625         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9626                 /* check if the specified pool bit is out of range */
9627                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9628                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9629                         rte_free(mirr_rule);
9630                         return -EINVAL;
9631                 }
9632                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9633                         if (mirror_conf->pool_mask & (1ULL << i)) {
9634                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9635                                 j++;
9636                         }
9637                 }
9638                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9639                         /* add pf vsi to entries */
9640                         mirr_rule->entries[j] = pf->main_vsi_seid;
9641                         j++;
9642                 }
9643                 if (j == 0) {
9644                         PMD_DRV_LOG(ERR, "pool is not specified.");
9645                         rte_free(mirr_rule);
9646                         return -EINVAL;
9647                 }
9648                 /* egress and ingress in aq commands means from switch but not port */
9649                 mirr_rule->rule_type =
9650                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9651                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9652                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9653                 break;
9654         case ETH_MIRROR_UPLINK_PORT:
9655                 /* egress and ingress in aq commands means from switch but not port*/
9656                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9657                 break;
9658         case ETH_MIRROR_DOWNLINK_PORT:
9659                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9660                 break;
9661         default:
9662                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9663                         mirror_conf->rule_type);
9664                 rte_free(mirr_rule);
9665                 return -EINVAL;
9666         }
9667
9668         /* If the dst_pool is equal to vf_num, consider it as PF */
9669         if (mirror_conf->dst_pool == pf->vf_num)
9670                 dst_seid = pf->main_vsi_seid;
9671         else
9672                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9673
9674         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9675                                       mirr_rule->rule_type, mirr_rule->entries,
9676                                       j, &rule_id);
9677         if (ret < 0) {
9678                 PMD_DRV_LOG(ERR,
9679                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9680                         ret, hw->aq.asq_last_status);
9681                 rte_free(mirr_rule);
9682                 return -ENOSYS;
9683         }
9684
9685         mirr_rule->index = sw_id;
9686         mirr_rule->num_entries = j;
9687         mirr_rule->id = rule_id;
9688         mirr_rule->dst_vsi_seid = dst_seid;
9689
9690         if (parent)
9691                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9692         else
9693                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9694
9695         pf->nb_mirror_rule++;
9696         return 0;
9697 }
9698
9699 /**
9700  * i40e_mirror_rule_reset
9701  * @dev: pointer to the device
9702  * @sw_id: mirror rule's sw_id
9703  *
9704  * reset a mirror rule.
9705  *
9706  **/
9707 static int
9708 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9709 {
9710         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9712         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9713         uint16_t seid;
9714         int ret;
9715
9716         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9717
9718         seid = pf->main_vsi->veb->seid;
9719
9720         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9721                 if (sw_id == it->index) {
9722                         mirr_rule = it;
9723                         break;
9724                 }
9725         }
9726         if (mirr_rule) {
9727                 ret = i40e_aq_del_mirror_rule(hw, seid,
9728                                 mirr_rule->rule_type,
9729                                 mirr_rule->entries,
9730                                 mirr_rule->num_entries, mirr_rule->id);
9731                 if (ret < 0) {
9732                         PMD_DRV_LOG(ERR,
9733                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9734                                 ret, hw->aq.asq_last_status);
9735                         return -ENOSYS;
9736                 }
9737                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9738                 rte_free(mirr_rule);
9739                 pf->nb_mirror_rule--;
9740         } else {
9741                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9742                 return -ENOENT;
9743         }
9744         return 0;
9745 }
9746
9747 static uint64_t
9748 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9749 {
9750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9751         uint64_t systim_cycles;
9752
9753         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9754         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9755                         << 32;
9756
9757         return systim_cycles;
9758 }
9759
9760 static uint64_t
9761 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9762 {
9763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9764         uint64_t rx_tstamp;
9765
9766         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9767         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9768                         << 32;
9769
9770         return rx_tstamp;
9771 }
9772
9773 static uint64_t
9774 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9775 {
9776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9777         uint64_t tx_tstamp;
9778
9779         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9780         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9781                         << 32;
9782
9783         return tx_tstamp;
9784 }
9785
9786 static void
9787 i40e_start_timecounters(struct rte_eth_dev *dev)
9788 {
9789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9790         struct i40e_adapter *adapter =
9791                         (struct i40e_adapter *)dev->data->dev_private;
9792         struct rte_eth_link link;
9793         uint32_t tsync_inc_l;
9794         uint32_t tsync_inc_h;
9795
9796         /* Get current link speed. */
9797         memset(&link, 0, sizeof(link));
9798         i40e_dev_link_update(dev, 1);
9799         rte_i40e_dev_atomic_read_link_status(dev, &link);
9800
9801         switch (link.link_speed) {
9802         case ETH_SPEED_NUM_40G:
9803                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9804                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9805                 break;
9806         case ETH_SPEED_NUM_10G:
9807                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9808                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9809                 break;
9810         case ETH_SPEED_NUM_1G:
9811                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9812                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9813                 break;
9814         default:
9815                 tsync_inc_l = 0x0;
9816                 tsync_inc_h = 0x0;
9817         }
9818
9819         /* Set the timesync increment value. */
9820         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9821         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9822
9823         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9824         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9825         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9826
9827         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9828         adapter->systime_tc.cc_shift = 0;
9829         adapter->systime_tc.nsec_mask = 0;
9830
9831         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9832         adapter->rx_tstamp_tc.cc_shift = 0;
9833         adapter->rx_tstamp_tc.nsec_mask = 0;
9834
9835         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9836         adapter->tx_tstamp_tc.cc_shift = 0;
9837         adapter->tx_tstamp_tc.nsec_mask = 0;
9838 }
9839
9840 static int
9841 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9842 {
9843         struct i40e_adapter *adapter =
9844                         (struct i40e_adapter *)dev->data->dev_private;
9845
9846         adapter->systime_tc.nsec += delta;
9847         adapter->rx_tstamp_tc.nsec += delta;
9848         adapter->tx_tstamp_tc.nsec += delta;
9849
9850         return 0;
9851 }
9852
9853 static int
9854 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9855 {
9856         uint64_t ns;
9857         struct i40e_adapter *adapter =
9858                         (struct i40e_adapter *)dev->data->dev_private;
9859
9860         ns = rte_timespec_to_ns(ts);
9861
9862         /* Set the timecounters to a new value. */
9863         adapter->systime_tc.nsec = ns;
9864         adapter->rx_tstamp_tc.nsec = ns;
9865         adapter->tx_tstamp_tc.nsec = ns;
9866
9867         return 0;
9868 }
9869
9870 static int
9871 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9872 {
9873         uint64_t ns, systime_cycles;
9874         struct i40e_adapter *adapter =
9875                         (struct i40e_adapter *)dev->data->dev_private;
9876
9877         systime_cycles = i40e_read_systime_cyclecounter(dev);
9878         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9879         *ts = rte_ns_to_timespec(ns);
9880
9881         return 0;
9882 }
9883
9884 static int
9885 i40e_timesync_enable(struct rte_eth_dev *dev)
9886 {
9887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9888         uint32_t tsync_ctl_l;
9889         uint32_t tsync_ctl_h;
9890
9891         /* Stop the timesync system time. */
9892         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9893         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9894         /* Reset the timesync system time value. */
9895         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9896         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9897
9898         i40e_start_timecounters(dev);
9899
9900         /* Clear timesync registers. */
9901         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9902         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9903         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9904         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9905         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9906         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9907
9908         /* Enable timestamping of PTP packets. */
9909         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9910         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9911
9912         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9913         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9914         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9915
9916         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9917         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9918
9919         return 0;
9920 }
9921
9922 static int
9923 i40e_timesync_disable(struct rte_eth_dev *dev)
9924 {
9925         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9926         uint32_t tsync_ctl_l;
9927         uint32_t tsync_ctl_h;
9928
9929         /* Disable timestamping of transmitted PTP packets. */
9930         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9931         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9932
9933         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9934         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9935
9936         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9937         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9938
9939         /* Reset the timesync increment value. */
9940         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9941         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9942
9943         return 0;
9944 }
9945
9946 static int
9947 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9948                                 struct timespec *timestamp, uint32_t flags)
9949 {
9950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9951         struct i40e_adapter *adapter =
9952                 (struct i40e_adapter *)dev->data->dev_private;
9953
9954         uint32_t sync_status;
9955         uint32_t index = flags & 0x03;
9956         uint64_t rx_tstamp_cycles;
9957         uint64_t ns;
9958
9959         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9960         if ((sync_status & (1 << index)) == 0)
9961                 return -EINVAL;
9962
9963         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9964         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9965         *timestamp = rte_ns_to_timespec(ns);
9966
9967         return 0;
9968 }
9969
9970 static int
9971 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9972                                 struct timespec *timestamp)
9973 {
9974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9975         struct i40e_adapter *adapter =
9976                 (struct i40e_adapter *)dev->data->dev_private;
9977
9978         uint32_t sync_status;
9979         uint64_t tx_tstamp_cycles;
9980         uint64_t ns;
9981
9982         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9983         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9984                 return -EINVAL;
9985
9986         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9987         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9988         *timestamp = rte_ns_to_timespec(ns);
9989
9990         return 0;
9991 }
9992
9993 /*
9994  * i40e_parse_dcb_configure - parse dcb configure from user
9995  * @dev: the device being configured
9996  * @dcb_cfg: pointer of the result of parse
9997  * @*tc_map: bit map of enabled traffic classes
9998  *
9999  * Returns 0 on success, negative value on failure
10000  */
10001 static int
10002 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10003                          struct i40e_dcbx_config *dcb_cfg,
10004                          uint8_t *tc_map)
10005 {
10006         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10007         uint8_t i, tc_bw, bw_lf;
10008
10009         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10010
10011         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10012         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10013                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10014                 return -EINVAL;
10015         }
10016
10017         /* assume each tc has the same bw */
10018         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10019         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10020                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10021         /* to ensure the sum of tcbw is equal to 100 */
10022         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10023         for (i = 0; i < bw_lf; i++)
10024                 dcb_cfg->etscfg.tcbwtable[i]++;
10025
10026         /* assume each tc has the same Transmission Selection Algorithm */
10027         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10028                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10029
10030         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10031                 dcb_cfg->etscfg.prioritytable[i] =
10032                                 dcb_rx_conf->dcb_tc[i];
10033
10034         /* FW needs one App to configure HW */
10035         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10036         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10037         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10038         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10039
10040         if (dcb_rx_conf->nb_tcs == 0)
10041                 *tc_map = 1; /* tc0 only */
10042         else
10043                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10044
10045         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10046                 dcb_cfg->pfc.willing = 0;
10047                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10048                 dcb_cfg->pfc.pfcenable = *tc_map;
10049         }
10050         return 0;
10051 }
10052
10053
10054 static enum i40e_status_code
10055 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10056                               struct i40e_aqc_vsi_properties_data *info,
10057                               uint8_t enabled_tcmap)
10058 {
10059         enum i40e_status_code ret;
10060         int i, total_tc = 0;
10061         uint16_t qpnum_per_tc, bsf, qp_idx;
10062         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10063         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10064         uint16_t used_queues;
10065
10066         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10067         if (ret != I40E_SUCCESS)
10068                 return ret;
10069
10070         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10071                 if (enabled_tcmap & (1 << i))
10072                         total_tc++;
10073         }
10074         if (total_tc == 0)
10075                 total_tc = 1;
10076         vsi->enabled_tc = enabled_tcmap;
10077
10078         /* different VSI has different queues assigned */
10079         if (vsi->type == I40E_VSI_MAIN)
10080                 used_queues = dev_data->nb_rx_queues -
10081                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10082         else if (vsi->type == I40E_VSI_VMDQ2)
10083                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10084         else {
10085                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10086                 return I40E_ERR_NO_AVAILABLE_VSI;
10087         }
10088
10089         qpnum_per_tc = used_queues / total_tc;
10090         /* Number of queues per enabled TC */
10091         if (qpnum_per_tc == 0) {
10092                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10093                 return I40E_ERR_INVALID_QP_ID;
10094         }
10095         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10096                                 I40E_MAX_Q_PER_TC);
10097         bsf = rte_bsf32(qpnum_per_tc);
10098
10099         /**
10100          * Configure TC and queue mapping parameters, for enabled TC,
10101          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10102          * default queue will serve it.
10103          */
10104         qp_idx = 0;
10105         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10106                 if (vsi->enabled_tc & (1 << i)) {
10107                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10108                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10109                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10110                         qp_idx += qpnum_per_tc;
10111                 } else
10112                         info->tc_mapping[i] = 0;
10113         }
10114
10115         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10116         if (vsi->type == I40E_VSI_SRIOV) {
10117                 info->mapping_flags |=
10118                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10119                 for (i = 0; i < vsi->nb_qps; i++)
10120                         info->queue_mapping[i] =
10121                                 rte_cpu_to_le_16(vsi->base_queue + i);
10122         } else {
10123                 info->mapping_flags |=
10124                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10125                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10126         }
10127         info->valid_sections |=
10128                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10129
10130         return I40E_SUCCESS;
10131 }
10132
10133 /*
10134  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10135  * @veb: VEB to be configured
10136  * @tc_map: enabled TC bitmap
10137  *
10138  * Returns 0 on success, negative value on failure
10139  */
10140 static enum i40e_status_code
10141 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10142 {
10143         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10144         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10145         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10146         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10147         enum i40e_status_code ret = I40E_SUCCESS;
10148         int i;
10149         uint32_t bw_max;
10150
10151         /* Check if enabled_tc is same as existing or new TCs */
10152         if (veb->enabled_tc == tc_map)
10153                 return ret;
10154
10155         /* configure tc bandwidth */
10156         memset(&veb_bw, 0, sizeof(veb_bw));
10157         veb_bw.tc_valid_bits = tc_map;
10158         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10159         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10160                 if (tc_map & BIT_ULL(i))
10161                         veb_bw.tc_bw_share_credits[i] = 1;
10162         }
10163         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10164                                                    &veb_bw, NULL);
10165         if (ret) {
10166                 PMD_INIT_LOG(ERR,
10167                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10168                         hw->aq.asq_last_status);
10169                 return ret;
10170         }
10171
10172         memset(&ets_query, 0, sizeof(ets_query));
10173         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10174                                                    &ets_query, NULL);
10175         if (ret != I40E_SUCCESS) {
10176                 PMD_DRV_LOG(ERR,
10177                         "Failed to get switch_comp ETS configuration %u",
10178                         hw->aq.asq_last_status);
10179                 return ret;
10180         }
10181         memset(&bw_query, 0, sizeof(bw_query));
10182         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10183                                                   &bw_query, NULL);
10184         if (ret != I40E_SUCCESS) {
10185                 PMD_DRV_LOG(ERR,
10186                         "Failed to get switch_comp bandwidth configuration %u",
10187                         hw->aq.asq_last_status);
10188                 return ret;
10189         }
10190
10191         /* store and print out BW info */
10192         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10193         veb->bw_info.bw_max = ets_query.tc_bw_max;
10194         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10195         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10196         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10197                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10198                      I40E_16_BIT_WIDTH);
10199         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10200                 veb->bw_info.bw_ets_share_credits[i] =
10201                                 bw_query.tc_bw_share_credits[i];
10202                 veb->bw_info.bw_ets_credits[i] =
10203                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10204                 /* 4 bits per TC, 4th bit is reserved */
10205                 veb->bw_info.bw_ets_max[i] =
10206                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10207                                   RTE_LEN2MASK(3, uint8_t));
10208                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10209                             veb->bw_info.bw_ets_share_credits[i]);
10210                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10211                             veb->bw_info.bw_ets_credits[i]);
10212                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10213                             veb->bw_info.bw_ets_max[i]);
10214         }
10215
10216         veb->enabled_tc = tc_map;
10217
10218         return ret;
10219 }
10220
10221
10222 /*
10223  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10224  * @vsi: VSI to be configured
10225  * @tc_map: enabled TC bitmap
10226  *
10227  * Returns 0 on success, negative value on failure
10228  */
10229 static enum i40e_status_code
10230 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10231 {
10232         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10233         struct i40e_vsi_context ctxt;
10234         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10235         enum i40e_status_code ret = I40E_SUCCESS;
10236         int i;
10237
10238         /* Check if enabled_tc is same as existing or new TCs */
10239         if (vsi->enabled_tc == tc_map)
10240                 return ret;
10241
10242         /* configure tc bandwidth */
10243         memset(&bw_data, 0, sizeof(bw_data));
10244         bw_data.tc_valid_bits = tc_map;
10245         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10246         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10247                 if (tc_map & BIT_ULL(i))
10248                         bw_data.tc_bw_credits[i] = 1;
10249         }
10250         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10251         if (ret) {
10252                 PMD_INIT_LOG(ERR,
10253                         "AQ command Config VSI BW allocation per TC failed = %d",
10254                         hw->aq.asq_last_status);
10255                 goto out;
10256         }
10257         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10258                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10259
10260         /* Update Queue Pairs Mapping for currently enabled UPs */
10261         ctxt.seid = vsi->seid;
10262         ctxt.pf_num = hw->pf_id;
10263         ctxt.vf_num = 0;
10264         ctxt.uplink_seid = vsi->uplink_seid;
10265         ctxt.info = vsi->info;
10266         i40e_get_cap(hw);
10267         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10268         if (ret)
10269                 goto out;
10270
10271         /* Update the VSI after updating the VSI queue-mapping information */
10272         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10273         if (ret) {
10274                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10275                         hw->aq.asq_last_status);
10276                 goto out;
10277         }
10278         /* update the local VSI info with updated queue map */
10279         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10280                                         sizeof(vsi->info.tc_mapping));
10281         (void)rte_memcpy(&vsi->info.queue_mapping,
10282                         &ctxt.info.queue_mapping,
10283                 sizeof(vsi->info.queue_mapping));
10284         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10285         vsi->info.valid_sections = 0;
10286
10287         /* query and update current VSI BW information */
10288         ret = i40e_vsi_get_bw_config(vsi);
10289         if (ret) {
10290                 PMD_INIT_LOG(ERR,
10291                          "Failed updating vsi bw info, err %s aq_err %s",
10292                          i40e_stat_str(hw, ret),
10293                          i40e_aq_str(hw, hw->aq.asq_last_status));
10294                 goto out;
10295         }
10296
10297         vsi->enabled_tc = tc_map;
10298
10299 out:
10300         return ret;
10301 }
10302
10303 /*
10304  * i40e_dcb_hw_configure - program the dcb setting to hw
10305  * @pf: pf the configuration is taken on
10306  * @new_cfg: new configuration
10307  * @tc_map: enabled TC bitmap
10308  *
10309  * Returns 0 on success, negative value on failure
10310  */
10311 static enum i40e_status_code
10312 i40e_dcb_hw_configure(struct i40e_pf *pf,
10313                       struct i40e_dcbx_config *new_cfg,
10314                       uint8_t tc_map)
10315 {
10316         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10317         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10318         struct i40e_vsi *main_vsi = pf->main_vsi;
10319         struct i40e_vsi_list *vsi_list;
10320         enum i40e_status_code ret;
10321         int i;
10322         uint32_t val;
10323
10324         /* Use the FW API if FW > v4.4*/
10325         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10326               (hw->aq.fw_maj_ver >= 5))) {
10327                 PMD_INIT_LOG(ERR,
10328                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10329                 return I40E_ERR_FIRMWARE_API_VERSION;
10330         }
10331
10332         /* Check if need reconfiguration */
10333         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10334                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10335                 return I40E_SUCCESS;
10336         }
10337
10338         /* Copy the new config to the current config */
10339         *old_cfg = *new_cfg;
10340         old_cfg->etsrec = old_cfg->etscfg;
10341         ret = i40e_set_dcb_config(hw);
10342         if (ret) {
10343                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10344                          i40e_stat_str(hw, ret),
10345                          i40e_aq_str(hw, hw->aq.asq_last_status));
10346                 return ret;
10347         }
10348         /* set receive Arbiter to RR mode and ETS scheme by default */
10349         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10350                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10351                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10352                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10353                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10354                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10355                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10356                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10357                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10358                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10359                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10360                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10361                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10362         }
10363         /* get local mib to check whether it is configured correctly */
10364         /* IEEE mode */
10365         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10366         /* Get Local DCB Config */
10367         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10368                                      &hw->local_dcbx_config);
10369
10370         /* if Veb is created, need to update TC of it at first */
10371         if (main_vsi->veb) {
10372                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10373                 if (ret)
10374                         PMD_INIT_LOG(WARNING,
10375                                  "Failed configuring TC for VEB seid=%d",
10376                                  main_vsi->veb->seid);
10377         }
10378         /* Update each VSI */
10379         i40e_vsi_config_tc(main_vsi, tc_map);
10380         if (main_vsi->veb) {
10381                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10382                         /* Beside main VSI and VMDQ VSIs, only enable default
10383                          * TC for other VSIs
10384                          */
10385                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10386                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10387                                                          tc_map);
10388                         else
10389                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10390                                                          I40E_DEFAULT_TCMAP);
10391                         if (ret)
10392                                 PMD_INIT_LOG(WARNING,
10393                                         "Failed configuring TC for VSI seid=%d",
10394                                         vsi_list->vsi->seid);
10395                         /* continue */
10396                 }
10397         }
10398         return I40E_SUCCESS;
10399 }
10400
10401 /*
10402  * i40e_dcb_init_configure - initial dcb config
10403  * @dev: device being configured
10404  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10405  *
10406  * Returns 0 on success, negative value on failure
10407  */
10408 static int
10409 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10410 {
10411         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10412         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10413         int i, ret = 0;
10414
10415         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10416                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10417                 return -ENOTSUP;
10418         }
10419
10420         /* DCB initialization:
10421          * Update DCB configuration from the Firmware and configure
10422          * LLDP MIB change event.
10423          */
10424         if (sw_dcb == TRUE) {
10425                 ret = i40e_init_dcb(hw);
10426                 /* If lldp agent is stopped, the return value from
10427                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10428                  * adminq status. Otherwise, it should return success.
10429                  */
10430                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10431                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10432                         memset(&hw->local_dcbx_config, 0,
10433                                 sizeof(struct i40e_dcbx_config));
10434                         /* set dcb default configuration */
10435                         hw->local_dcbx_config.etscfg.willing = 0;
10436                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10437                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10438                         hw->local_dcbx_config.etscfg.tsatable[0] =
10439                                                 I40E_IEEE_TSA_ETS;
10440                         /* all UPs mapping to TC0 */
10441                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10442                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10443                         hw->local_dcbx_config.etsrec =
10444                                 hw->local_dcbx_config.etscfg;
10445                         hw->local_dcbx_config.pfc.willing = 0;
10446                         hw->local_dcbx_config.pfc.pfccap =
10447                                                 I40E_MAX_TRAFFIC_CLASS;
10448                         /* FW needs one App to configure HW */
10449                         hw->local_dcbx_config.numapps = 1;
10450                         hw->local_dcbx_config.app[0].selector =
10451                                                 I40E_APP_SEL_ETHTYPE;
10452                         hw->local_dcbx_config.app[0].priority = 3;
10453                         hw->local_dcbx_config.app[0].protocolid =
10454                                                 I40E_APP_PROTOID_FCOE;
10455                         ret = i40e_set_dcb_config(hw);
10456                         if (ret) {
10457                                 PMD_INIT_LOG(ERR,
10458                                         "default dcb config fails. err = %d, aq_err = %d.",
10459                                         ret, hw->aq.asq_last_status);
10460                                 return -ENOSYS;
10461                         }
10462                 } else {
10463                         PMD_INIT_LOG(ERR,
10464                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10465                                 ret, hw->aq.asq_last_status);
10466                         return -ENOTSUP;
10467                 }
10468         } else {
10469                 ret = i40e_aq_start_lldp(hw, NULL);
10470                 if (ret != I40E_SUCCESS)
10471                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10472
10473                 ret = i40e_init_dcb(hw);
10474                 if (!ret) {
10475                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10476                                 PMD_INIT_LOG(ERR,
10477                                         "HW doesn't support DCBX offload.");
10478                                 return -ENOTSUP;
10479                         }
10480                 } else {
10481                         PMD_INIT_LOG(ERR,
10482                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10483                                 ret, hw->aq.asq_last_status);
10484                         return -ENOTSUP;
10485                 }
10486         }
10487         return 0;
10488 }
10489
10490 /*
10491  * i40e_dcb_setup - setup dcb related config
10492  * @dev: device being configured
10493  *
10494  * Returns 0 on success, negative value on failure
10495  */
10496 static int
10497 i40e_dcb_setup(struct rte_eth_dev *dev)
10498 {
10499         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10500         struct i40e_dcbx_config dcb_cfg;
10501         uint8_t tc_map = 0;
10502         int ret = 0;
10503
10504         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10505                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10506                 return -ENOTSUP;
10507         }
10508
10509         if (pf->vf_num != 0)
10510                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10511
10512         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10513         if (ret) {
10514                 PMD_INIT_LOG(ERR, "invalid dcb config");
10515                 return -EINVAL;
10516         }
10517         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10518         if (ret) {
10519                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10520                 return -ENOSYS;
10521         }
10522
10523         return 0;
10524 }
10525
10526 static int
10527 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10528                       struct rte_eth_dcb_info *dcb_info)
10529 {
10530         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10532         struct i40e_vsi *vsi = pf->main_vsi;
10533         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10534         uint16_t bsf, tc_mapping;
10535         int i, j = 0;
10536
10537         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10538                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10539         else
10540                 dcb_info->nb_tcs = 1;
10541         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10542                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10543         for (i = 0; i < dcb_info->nb_tcs; i++)
10544                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10545
10546         /* get queue mapping if vmdq is disabled */
10547         if (!pf->nb_cfg_vmdq_vsi) {
10548                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10549                         if (!(vsi->enabled_tc & (1 << i)))
10550                                 continue;
10551                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10552                         dcb_info->tc_queue.tc_rxq[j][i].base =
10553                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10554                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10555                         dcb_info->tc_queue.tc_txq[j][i].base =
10556                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10557                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10558                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10559                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10560                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10561                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10562                 }
10563                 return 0;
10564         }
10565
10566         /* get queue mapping if vmdq is enabled */
10567         do {
10568                 vsi = pf->vmdq[j].vsi;
10569                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10570                         if (!(vsi->enabled_tc & (1 << i)))
10571                                 continue;
10572                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10573                         dcb_info->tc_queue.tc_rxq[j][i].base =
10574                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10575                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10576                         dcb_info->tc_queue.tc_txq[j][i].base =
10577                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10578                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10579                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10580                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10581                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10582                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10583                 }
10584                 j++;
10585         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10586         return 0;
10587 }
10588
10589 static int
10590 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10591 {
10592         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10593         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10595         uint16_t interval =
10596                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10597         uint16_t msix_intr;
10598
10599         msix_intr = intr_handle->intr_vec[queue_id];
10600         if (msix_intr == I40E_MISC_VEC_ID)
10601                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10602                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10603                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10604                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10605                                (interval <<
10606                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10607         else
10608                 I40E_WRITE_REG(hw,
10609                                I40E_PFINT_DYN_CTLN(msix_intr -
10610                                                    I40E_RX_VEC_START),
10611                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10612                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10613                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10614                                (interval <<
10615                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10616
10617         I40E_WRITE_FLUSH(hw);
10618         rte_intr_enable(&pci_dev->intr_handle);
10619
10620         return 0;
10621 }
10622
10623 static int
10624 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10625 {
10626         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10627         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10629         uint16_t msix_intr;
10630
10631         msix_intr = intr_handle->intr_vec[queue_id];
10632         if (msix_intr == I40E_MISC_VEC_ID)
10633                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10634         else
10635                 I40E_WRITE_REG(hw,
10636                                I40E_PFINT_DYN_CTLN(msix_intr -
10637                                                    I40E_RX_VEC_START),
10638                                0);
10639         I40E_WRITE_FLUSH(hw);
10640
10641         return 0;
10642 }
10643
10644 static int i40e_get_regs(struct rte_eth_dev *dev,
10645                          struct rte_dev_reg_info *regs)
10646 {
10647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10648         uint32_t *ptr_data = regs->data;
10649         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10650         const struct i40e_reg_info *reg_info;
10651
10652         if (ptr_data == NULL) {
10653                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10654                 regs->width = sizeof(uint32_t);
10655                 return 0;
10656         }
10657
10658         /* The first few registers have to be read using AQ operations */
10659         reg_idx = 0;
10660         while (i40e_regs_adminq[reg_idx].name) {
10661                 reg_info = &i40e_regs_adminq[reg_idx++];
10662                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10663                         for (arr_idx2 = 0;
10664                                         arr_idx2 <= reg_info->count2;
10665                                         arr_idx2++) {
10666                                 reg_offset = arr_idx * reg_info->stride1 +
10667                                         arr_idx2 * reg_info->stride2;
10668                                 reg_offset += reg_info->base_addr;
10669                                 ptr_data[reg_offset >> 2] =
10670                                         i40e_read_rx_ctl(hw, reg_offset);
10671                         }
10672         }
10673
10674         /* The remaining registers can be read using primitives */
10675         reg_idx = 0;
10676         while (i40e_regs_others[reg_idx].name) {
10677                 reg_info = &i40e_regs_others[reg_idx++];
10678                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10679                         for (arr_idx2 = 0;
10680                                         arr_idx2 <= reg_info->count2;
10681                                         arr_idx2++) {
10682                                 reg_offset = arr_idx * reg_info->stride1 +
10683                                         arr_idx2 * reg_info->stride2;
10684                                 reg_offset += reg_info->base_addr;
10685                                 ptr_data[reg_offset >> 2] =
10686                                         I40E_READ_REG(hw, reg_offset);
10687                         }
10688         }
10689
10690         return 0;
10691 }
10692
10693 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10694 {
10695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10696
10697         /* Convert word count to byte count */
10698         return hw->nvm.sr_size << 1;
10699 }
10700
10701 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10702                            struct rte_dev_eeprom_info *eeprom)
10703 {
10704         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10705         uint16_t *data = eeprom->data;
10706         uint16_t offset, length, cnt_words;
10707         int ret_code;
10708
10709         offset = eeprom->offset >> 1;
10710         length = eeprom->length >> 1;
10711         cnt_words = length;
10712
10713         if (offset > hw->nvm.sr_size ||
10714                 offset + length > hw->nvm.sr_size) {
10715                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10716                 return -EINVAL;
10717         }
10718
10719         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10720
10721         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10722         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10723                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10724                 return -EIO;
10725         }
10726
10727         return 0;
10728 }
10729
10730 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10731                                       struct ether_addr *mac_addr)
10732 {
10733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10734
10735         if (!is_valid_assigned_ether_addr(mac_addr)) {
10736                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10737                 return;
10738         }
10739
10740         /* Flags: 0x3 updates port address */
10741         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10742 }
10743
10744 static int
10745 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10746 {
10747         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10748         struct rte_eth_dev_data *dev_data = pf->dev_data;
10749         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10750         int ret = 0;
10751
10752         /* check if mtu is within the allowed range */
10753         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10754                 return -EINVAL;
10755
10756         /* mtu setting is forbidden if port is start */
10757         if (dev_data->dev_started) {
10758                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10759                             dev_data->port_id);
10760                 return -EBUSY;
10761         }
10762
10763         if (frame_size > ETHER_MAX_LEN)
10764                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10765         else
10766                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10767
10768         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10769
10770         return ret;
10771 }
10772
10773 /* Restore ethertype filter */
10774 static void
10775 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10776 {
10777         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10778         struct i40e_ethertype_filter_list
10779                 *ethertype_list = &pf->ethertype.ethertype_list;
10780         struct i40e_ethertype_filter *f;
10781         struct i40e_control_filter_stats stats;
10782         uint16_t flags;
10783
10784         TAILQ_FOREACH(f, ethertype_list, rules) {
10785                 flags = 0;
10786                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10787                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10788                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10789                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10790                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10791
10792                 memset(&stats, 0, sizeof(stats));
10793                 i40e_aq_add_rem_control_packet_filter(hw,
10794                                             f->input.mac_addr.addr_bytes,
10795                                             f->input.ether_type,
10796                                             flags, pf->main_vsi->seid,
10797                                             f->queue, 1, &stats, NULL);
10798         }
10799         PMD_DRV_LOG(INFO, "Ethertype filter:"
10800                     " mac_etype_used = %u, etype_used = %u,"
10801                     " mac_etype_free = %u, etype_free = %u",
10802                     stats.mac_etype_used, stats.etype_used,
10803                     stats.mac_etype_free, stats.etype_free);
10804 }
10805
10806 /* Restore tunnel filter */
10807 static void
10808 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10809 {
10810         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10811         struct i40e_vsi *vsi;
10812         struct i40e_pf_vf *vf;
10813         struct i40e_tunnel_filter_list
10814                 *tunnel_list = &pf->tunnel.tunnel_list;
10815         struct i40e_tunnel_filter *f;
10816         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10817         bool big_buffer = 0;
10818
10819         TAILQ_FOREACH(f, tunnel_list, rules) {
10820                 if (!f->is_to_vf)
10821                         vsi = pf->main_vsi;
10822                 else {
10823                         vf = &pf->vfs[f->vf_id];
10824                         vsi = vf->vsi;
10825                 }
10826                 memset(&cld_filter, 0, sizeof(cld_filter));
10827                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10828                         (struct ether_addr *)&cld_filter.element.outer_mac);
10829                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10830                         (struct ether_addr *)&cld_filter.element.inner_mac);
10831                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10832                 cld_filter.element.flags = f->input.flags;
10833                 cld_filter.element.tenant_id = f->input.tenant_id;
10834                 cld_filter.element.queue_number = f->queue;
10835                 rte_memcpy(cld_filter.general_fields,
10836                            f->input.general_fields,
10837                            sizeof(f->input.general_fields));
10838
10839                 if (((f->input.flags &
10840                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10841                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10842                     ((f->input.flags &
10843                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10844                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10845                     ((f->input.flags &
10846                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10847                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10848                         big_buffer = 1;
10849
10850                 if (big_buffer)
10851                         i40e_aq_add_cloud_filters_big_buffer(hw,
10852                                              vsi->seid, &cld_filter, 1);
10853                 else
10854                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10855                                                   &cld_filter.element, 1);
10856         }
10857 }
10858
10859 static void
10860 i40e_filter_restore(struct i40e_pf *pf)
10861 {
10862         i40e_ethertype_filter_restore(pf);
10863         i40e_tunnel_filter_restore(pf);
10864         i40e_fdir_filter_restore(pf);
10865 }
10866
10867 static bool
10868 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10869 {
10870         if (strcmp(dev->device->driver->name, drv->driver.name))
10871                 return false;
10872
10873         return true;
10874 }
10875
10876 bool
10877 is_i40e_supported(struct rte_eth_dev *dev)
10878 {
10879         return is_device_supported(dev, &rte_i40e_pmd);
10880 }
10881
10882 /* Create a QinQ cloud filter
10883  *
10884  * The Fortville NIC has limited resources for tunnel filters,
10885  * so we can only reuse existing filters.
10886  *
10887  * In step 1 we define which Field Vector fields can be used for
10888  * filter types.
10889  * As we do not have the inner tag defined as a field,
10890  * we have to define it first, by reusing one of L1 entries.
10891  *
10892  * In step 2 we are replacing one of existing filter types with
10893  * a new one for QinQ.
10894  * As we reusing L1 and replacing L2, some of the default filter
10895  * types will disappear,which depends on L1 and L2 entries we reuse.
10896  *
10897  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10898  *
10899  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10900  *              later when we define the cloud filter.
10901  *      a.      Valid_flags.replace_cloud = 0
10902  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10903  *      c.      New_filter = 0x10
10904  *      d.      TR bit = 0xff (optional, not used here)
10905  *      e.      Buffer – 2 entries:
10906  *              i.      Byte 0 = 8 (outer vlan FV index).
10907  *                      Byte 1 = 0 (rsv)
10908  *                      Byte 2-3 = 0x0fff
10909  *              ii.     Byte 0 = 37 (inner vlan FV index).
10910  *                      Byte 1 =0 (rsv)
10911  *                      Byte 2-3 = 0x0fff
10912  *
10913  * Step 2:
10914  * 2.   Create cloud filter using two L1 filters entries: stag and
10915  *              new filter(outer vlan+ inner vlan)
10916  *      a.      Valid_flags.replace_cloud = 1
10917  *      b.      Old_filter = 1 (instead of outer IP)
10918  *      c.      New_filter = 0x10
10919  *      d.      Buffer – 2 entries:
10920  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10921  *                      Byte 1-3 = 0 (rsv)
10922  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10923  *                      Byte 9-11 = 0 (rsv)
10924  */
10925 static int
10926 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10927 {
10928         int ret = -ENOTSUP;
10929         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10930         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10931         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10932
10933         /* Init */
10934         memset(&filter_replace, 0,
10935                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10936         memset(&filter_replace_buf, 0,
10937                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10938
10939         /* create L1 filter */
10940         filter_replace.old_filter_type =
10941                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10942         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10943         filter_replace.tr_bit = 0;
10944
10945         /* Prepare the buffer, 2 entries */
10946         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10947         filter_replace_buf.data[0] |=
10948                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10949         /* Field Vector 12b mask */
10950         filter_replace_buf.data[2] = 0xff;
10951         filter_replace_buf.data[3] = 0x0f;
10952         filter_replace_buf.data[4] =
10953                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10954         filter_replace_buf.data[4] |=
10955                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10956         /* Field Vector 12b mask */
10957         filter_replace_buf.data[6] = 0xff;
10958         filter_replace_buf.data[7] = 0x0f;
10959         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10960                         &filter_replace_buf);
10961         if (ret != I40E_SUCCESS)
10962                 return ret;
10963
10964         /* Apply the second L2 cloud filter */
10965         memset(&filter_replace, 0,
10966                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10967         memset(&filter_replace_buf, 0,
10968                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10969
10970         /* create L2 filter, input for L2 filter will be L1 filter  */
10971         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10972         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10973         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10974
10975         /* Prepare the buffer, 2 entries */
10976         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10977         filter_replace_buf.data[0] |=
10978                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10979         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10980         filter_replace_buf.data[4] |=
10981                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10982         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10983                         &filter_replace_buf);
10984         return ret;
10985 }
10986
10987 RTE_INIT(i40e_init_log);
10988 static void
10989 i40e_init_log(void)
10990 {
10991         i40e_logtype_init = rte_log_register("pmd.i40e.init");
10992         if (i40e_logtype_init >= 0)
10993                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10994         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10995         if (i40e_logtype_driver >= 0)
10996                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
10997 }