drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "base/i40e_diag.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45
  46 #define I40E_CLEAR_PXE_WAIT_MS     200
  47
  48 /* Maximun number of capability elements */
  49 #define I40E_MAX_CAP_ELE_NUM       128
  50
  51 /* Wait count and interval */
  52 #define I40E_CHK_Q_ENA_COUNT       1000
  53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  54
  55 /* Maximun number of VSI */
  56 #define I40E_MAX_NUM_VSIS          (384UL)
  57
  58 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  59
  60 /* Flow control default timer */
  61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  62
  63 /* Flow control enable fwd bit */
  64 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  65
  66 /* Receive Packet Buffer size */
  67 #define I40E_RXPBSIZE (968 * 1024)
  68
  69 /* Kilobytes shift */
  70 #define I40E_KILOSHIFT 10
  71
  72 /* Flow control default high water */
  73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  74
  75 /* Flow control default low water */
  76 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Receive Average Packet Size in Byte*/
  79 #define I40E_PACKET_AVERAGE_SIZE 128
  80
  81 /* Mask of PF interrupt causes */
  82 #define I40E_PFINT_ICR0_ENA_MASK ( \
  83                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  84                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  85                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  86                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  87                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  92
  93 #define I40E_FLOW_TYPES ( \
  94         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  99         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 104         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 105
 106 /* Additional timesync values. */
 107 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 108 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 109 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 110 #define I40E_PRTTSYN_TSYNENA     0x80000000
 111 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 112 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 113
 114 /**
 115  * Below are values for writing un-exposed registers suggested
 116  * by silicon experts
 117  */
 118 /* Destination MAC address */
 119 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 120 /* Source MAC address */
 121 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 123 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 126 /* Single VLAN tag in the inner L2 header */
 127 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 128 /* Source IPv4 address */
 129 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 130 /* Destination IPv4 address */
 131 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 132 /* Source IPv4 address for X722 */
 133 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 134 /* Destination IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 136 /* IPv4 Protocol for X722 */
 137 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 138 /* IPv4 Time to Live for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 140 /* IPv4 Type of Service (TOS) */
 141 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 142 /* IPv4 Protocol */
 143 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 144 /* IPv4 Time to Live */
 145 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 146 /* Source IPv6 address */
 147 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 148 /* Destination IPv6 address */
 149 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 150 /* IPv6 Traffic Class (TC) */
 151 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 152 /* IPv6 Next Header */
 153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 154 /* IPv6 Hop Limit */
 155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 156 /* Source L4 port */
 157 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 158 /* Destination L4 port */
 159 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 160 /* SCTP verification tag */
 161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 164 /* Source port of tunneling UDP */
 165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 166 /* Destination port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 168 /* UDP Tunneling ID, NVGRE/GRE key */
 169 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 170 /* Last ether type */
 171 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 172 /* Tunneling outer destination IPv4 address */
 173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 174 /* Tunneling outer destination IPv6 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 176 /* 1st word of flex payload */
 177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 178 /* 2nd word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 180 /* 3rd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 182 /* 4th word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 184 /* 5th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 186 /* 6th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 188 /* 7th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 190 /* 8th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 192 /* all 8 words flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 194 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 195
 196 #define I40E_TRANSLATE_INSET 0
 197 #define I40E_TRANSLATE_REG   1
 198
 199 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 200 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 201 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 202 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 204 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 205
 206 /* PCI offset for querying capability */
 207 #define PCI_DEV_CAP_REG            0xA4
 208 /* PCI offset for enabling/disabling Extended Tag */
 209 #define PCI_DEV_CTRL_REG           0xA8
 210 /* Bit mask of Extended Tag capability */
 211 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 212 /* Bit shift of Extended Tag enable/disable */
 213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 214 /* Bit mask of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 216
 217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 219 static int i40e_dev_configure(struct rte_eth_dev *dev);
 220 static int i40e_dev_start(struct rte_eth_dev *dev);
 221 static void i40e_dev_stop(struct rte_eth_dev *dev);
 222 static void i40e_dev_close(struct rte_eth_dev *dev);
 223 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 231                                struct rte_eth_stats *stats);
 232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_xstat *xstats, unsigned n);
 234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 235                                      struct rte_eth_xstat_name *xstats_names,
 236                                      unsigned limit);
 237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 239                                             uint16_t queue_id,
 240                                             uint8_t stat_idx,
 241                                             uint8_t is_rx);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 245                               struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 374                                       struct ether_addr *mac_addr);
 375
 376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 377
 378 static int i40e_ethertype_filter_convert(
 379         const struct rte_eth_ethertype_filter *input,
 380         struct i40e_ethertype_filter *filter);
 381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 382                                    struct i40e_ethertype_filter *filter);
 383
 384 static int i40e_tunnel_filter_convert(
 385         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 386         struct i40e_tunnel_filter *tunnel_filter);
 387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 388                                 struct i40e_tunnel_filter *tunnel_filter);
 389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 390
 391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 393 static void i40e_filter_restore(struct i40e_pf *pf);
 394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 395
 396 int i40e_logtype_init;
 397 int i40e_logtype_driver;
 398
 399 static const struct rte_pci_id pci_id_i40e_map[] = {
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 420         { .vendor_id = 0, /* sentinel */ },
 421 };
 422
 423 static const struct eth_dev_ops i40e_eth_dev_ops = {
 424         .dev_configure                = i40e_dev_configure,
 425         .dev_start                    = i40e_dev_start,
 426         .dev_stop                     = i40e_dev_stop,
 427         .dev_close                    = i40e_dev_close,
 428         .dev_reset                    = i40e_dev_reset,
 429         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 430         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 431         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 432         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 433         .dev_set_link_up              = i40e_dev_set_link_up,
 434         .dev_set_link_down            = i40e_dev_set_link_down,
 435         .link_update                  = i40e_dev_link_update,
 436         .stats_get                    = i40e_dev_stats_get,
 437         .xstats_get                   = i40e_dev_xstats_get,
 438         .xstats_get_names             = i40e_dev_xstats_get_names,
 439         .stats_reset                  = i40e_dev_stats_reset,
 440         .xstats_reset                 = i40e_dev_stats_reset,
 441         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 442         .fw_version_get               = i40e_fw_version_get,
 443         .dev_infos_get                = i40e_dev_info_get,
 444         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 445         .vlan_filter_set              = i40e_vlan_filter_set,
 446         .vlan_tpid_set                = i40e_vlan_tpid_set,
 447         .vlan_offload_set             = i40e_vlan_offload_set,
 448         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 449         .vlan_pvid_set                = i40e_vlan_pvid_set,
 450         .rx_queue_start               = i40e_dev_rx_queue_start,
 451         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 452         .tx_queue_start               = i40e_dev_tx_queue_start,
 453         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 454         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 455         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 456         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 457         .rx_queue_release             = i40e_dev_rx_queue_release,
 458         .rx_queue_count               = i40e_dev_rx_queue_count,
 459         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 460         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 461         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 462         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 463         .tx_queue_release             = i40e_dev_tx_queue_release,
 464         .dev_led_on                   = i40e_dev_led_on,
 465         .dev_led_off                  = i40e_dev_led_off,
 466         .flow_ctrl_get                = i40e_flow_ctrl_get,
 467         .flow_ctrl_set                = i40e_flow_ctrl_set,
 468         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 469         .mac_addr_add                 = i40e_macaddr_add,
 470         .mac_addr_remove              = i40e_macaddr_remove,
 471         .reta_update                  = i40e_dev_rss_reta_update,
 472         .reta_query                   = i40e_dev_rss_reta_query,
 473         .rss_hash_update              = i40e_dev_rss_hash_update,
 474         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 475         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 476         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 477         .filter_ctrl                  = i40e_dev_filter_ctrl,
 478         .rxq_info_get                 = i40e_rxq_info_get,
 479         .txq_info_get                 = i40e_txq_info_get,
 480         .mirror_rule_set              = i40e_mirror_rule_set,
 481         .mirror_rule_reset            = i40e_mirror_rule_reset,
 482         .timesync_enable              = i40e_timesync_enable,
 483         .timesync_disable             = i40e_timesync_disable,
 484         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 485         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 486         .get_dcb_info                 = i40e_dev_get_dcb_info,
 487         .timesync_adjust_time         = i40e_timesync_adjust_time,
 488         .timesync_read_time           = i40e_timesync_read_time,
 489         .timesync_write_time          = i40e_timesync_write_time,
 490         .get_reg                      = i40e_get_regs,
 491         .get_eeprom_length            = i40e_get_eeprom_length,
 492         .get_eeprom                   = i40e_get_eeprom,
 493         .mac_addr_set                 = i40e_set_default_mac_addr,
 494         .mtu_set                      = i40e_dev_mtu_set,
 495         .tm_ops_get                   = i40e_tm_ops_get,
 496 };
 497
 498 /* store statistics names and its offset in stats structure */
 499 struct rte_i40e_xstats_name_off {
 500         char name[RTE_ETH_XSTATS_NAME_SIZE];
 501         unsigned offset;
 502 };
 503
 504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 505         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 506         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 507         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 508         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 509         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 510                 rx_unknown_protocol)},
 511         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 512         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 513         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 514         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 515 };
 516
 517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 518                 sizeof(rte_i40e_stats_strings[0]))
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 521         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 522                 tx_dropped_link_down)},
 523         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 524         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 525                 illegal_bytes)},
 526         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 527         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 528                 mac_local_faults)},
 529         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 530                 mac_remote_faults)},
 531         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 532                 rx_length_errors)},
 533         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 534         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 535         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 536         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 537         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 538         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 539                 rx_size_127)},
 540         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 541                 rx_size_255)},
 542         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 543                 rx_size_511)},
 544         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 545                 rx_size_1023)},
 546         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 547                 rx_size_1522)},
 548         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 549                 rx_size_big)},
 550         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 551                 rx_undersize)},
 552         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_oversize)},
 554         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 555                 mac_short_packet_dropped)},
 556         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_fragments)},
 558         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 559         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 560         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 tx_size_127)},
 562         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 tx_size_255)},
 564         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 tx_size_511)},
 566         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 tx_size_1023)},
 568         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 tx_size_1522)},
 570         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 tx_size_big)},
 572         {"rx_flow_director_atr_match_packets",
 573                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 574         {"rx_flow_director_sb_match_packets",
 575                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 576         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 577                 tx_lpi_status)},
 578         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 579                 rx_lpi_status)},
 580         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 581                 tx_lpi_count)},
 582         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 583                 rx_lpi_count)},
 584 };
 585
 586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 587                 sizeof(rte_i40e_hw_port_strings[0]))
 588
 589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 590         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 591                 priority_xon_rx)},
 592         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 593                 priority_xoff_rx)},
 594 };
 595
 596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 597                 sizeof(rte_i40e_rxq_prio_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 600         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 601                 priority_xon_tx)},
 602         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 603                 priority_xoff_tx)},
 604         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 605                 priority_xon_2_xoff)},
 606 };
 607
 608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 609                 sizeof(rte_i40e_txq_prio_strings[0]))
 610
 611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 612         struct rte_pci_device *pci_dev)
 613 {
 614         return rte_eth_dev_pci_generic_probe(pci_dev,
 615                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 616 }
 617
 618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 619 {
 620         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 621 }
 622
 623 static struct rte_pci_driver rte_i40e_pmd = {
 624         .id_table = pci_id_i40e_map,
 625         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 626                      RTE_PCI_DRV_IOVA_AS_VA,
 627         .probe = eth_i40e_pci_probe,
 628         .remove = eth_i40e_pci_remove,
 629 };
 630
 631 static inline int
 632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 633                                      struct rte_eth_link *link)
 634 {
 635         struct rte_eth_link *dst = link;
 636         struct rte_eth_link *src = &(dev->data->dev_link);
 637
 638         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 639                                         *(uint64_t *)src) == 0)
 640                 return -1;
 641
 642         return 0;
 643 }
 644
 645 static inline int
 646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 647                                       struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = &(dev->data->dev_link);
 650         struct rte_eth_link *src = link;
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 660 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 661 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 662
 663 #ifndef I40E_GLQF_ORT
 664 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 665 #endif
 666 #ifndef I40E_GLQF_PIT
 667 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 668 #endif
 669 #ifndef I40E_GLQF_L3_MAP
 670 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 671 #endif
 672
 673 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 674 {
 675         /*
 676          * Initialize registers for parsing packet type of QinQ
 677          * This should be removed from code once proper
 678          * configuration API is added to avoid configuration conflicts
 679          * between ports of the same device.
 680          */
 681         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 682         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 683 }
 684
 685 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 686
 687 /*
 688  * Add a ethertype filter to drop all flow control frames transmitted
 689  * from VSIs.
 690 */
 691 static void
 692 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 693 {
 694         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 695         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 696                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 697                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 698         int ret;
 699
 700         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 701                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 702                                 pf->main_vsi_seid, 0,
 703                                 TRUE, NULL, NULL);
 704         if (ret)
 705                 PMD_INIT_LOG(ERR,
 706                         "Failed to add filter to drop flow control frames from VSIs.");
 707 }
 708
 709 static int
 710 floating_veb_list_handler(__rte_unused const char *key,
 711                           const char *floating_veb_value,
 712                           void *opaque)
 713 {
 714         int idx = 0;
 715         unsigned int count = 0;
 716         char *end = NULL;
 717         int min, max;
 718         bool *vf_floating_veb = opaque;
 719
 720         while (isblank(*floating_veb_value))
 721                 floating_veb_value++;
 722
 723         /* Reset floating VEB configuration for VFs */
 724         for (idx = 0; idx < I40E_MAX_VF; idx++)
 725                 vf_floating_veb[idx] = false;
 726
 727         min = I40E_MAX_VF;
 728         do {
 729                 while (isblank(*floating_veb_value))
 730                         floating_veb_value++;
 731                 if (*floating_veb_value == '\0')
 732                         return -1;
 733                 errno = 0;
 734                 idx = strtoul(floating_veb_value, &end, 10);
 735                 if (errno || end == NULL)
 736                         return -1;
 737                 while (isblank(*end))
 738                         end++;
 739                 if (*end == '-') {
 740                         min = idx;
 741                 } else if ((*end == ';') || (*end == '\0')) {
 742                         max = idx;
 743                         if (min == I40E_MAX_VF)
 744                                 min = idx;
 745                         if (max >= I40E_MAX_VF)
 746                                 max = I40E_MAX_VF - 1;
 747                         for (idx = min; idx <= max; idx++) {
 748                                 vf_floating_veb[idx] = true;
 749                                 count++;
 750                         }
 751                         min = I40E_MAX_VF;
 752                 } else {
 753                         return -1;
 754                 }
 755                 floating_veb_value = end + 1;
 756         } while (*end != '\0');
 757
 758         if (count == 0)
 759                 return -1;
 760
 761         return 0;
 762 }
 763
 764 static void
 765 config_vf_floating_veb(struct rte_devargs *devargs,
 766                        uint16_t floating_veb,
 767                        bool *vf_floating_veb)
 768 {
 769         struct rte_kvargs *kvlist;
 770         int i;
 771         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 772
 773         if (!floating_veb)
 774                 return;
 775         /* All the VFs attach to the floating VEB by default
 776          * when the floating VEB is enabled.
 777          */
 778         for (i = 0; i < I40E_MAX_VF; i++)
 779                 vf_floating_veb[i] = true;
 780
 781         if (devargs == NULL)
 782                 return;
 783
 784         kvlist = rte_kvargs_parse(devargs->args, NULL);
 785         if (kvlist == NULL)
 786                 return;
 787
 788         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 789                 rte_kvargs_free(kvlist);
 790                 return;
 791         }
 792         /* When the floating_veb_list parameter exists, all the VFs
 793          * will attach to the legacy VEB firstly, then configure VFs
 794          * to the floating VEB according to the floating_veb_list.
 795          */
 796         if (rte_kvargs_process(kvlist, floating_veb_list,
 797                                floating_veb_list_handler,
 798                                vf_floating_veb) < 0) {
 799                 rte_kvargs_free(kvlist);
 800                 return;
 801         }
 802         rte_kvargs_free(kvlist);
 803 }
 804
 805 static int
 806 i40e_check_floating_handler(__rte_unused const char *key,
 807                             const char *value,
 808                             __rte_unused void *opaque)
 809 {
 810         if (strcmp(value, "1"))
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static int
 817 is_floating_veb_supported(struct rte_devargs *devargs)
 818 {
 819         struct rte_kvargs *kvlist;
 820         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 821
 822         if (devargs == NULL)
 823                 return 0;
 824
 825         kvlist = rte_kvargs_parse(devargs->args, NULL);
 826         if (kvlist == NULL)
 827                 return 0;
 828
 829         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 830                 rte_kvargs_free(kvlist);
 831                 return 0;
 832         }
 833         /* Floating VEB is enabled when there's key-value:
 834          * enable_floating_veb=1
 835          */
 836         if (rte_kvargs_process(kvlist, floating_veb_key,
 837                                i40e_check_floating_handler, NULL) < 0) {
 838                 rte_kvargs_free(kvlist);
 839                 return 0;
 840         }
 841         rte_kvargs_free(kvlist);
 842
 843         return 1;
 844 }
 845
 846 static void
 847 config_floating_veb(struct rte_eth_dev *dev)
 848 {
 849         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 851         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 852
 853         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 854
 855         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 856                 pf->floating_veb =
 857                         is_floating_veb_supported(pci_dev->device.devargs);
 858                 config_vf_floating_veb(pci_dev->device.devargs,
 859                                        pf->floating_veb,
 860                                        pf->floating_veb_list);
 861         } else {
 862                 pf->floating_veb = false;
 863         }
 864 }
 865
 866 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 867 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 868
 869 static int
 870 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 871 {
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 874         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 875         int ret;
 876
 877         struct rte_hash_parameters ethertype_hash_params = {
 878                 .name = ethertype_hash_name,
 879                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 880                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 881                 .hash_func = rte_hash_crc,
 882                 .hash_func_init_val = 0,
 883                 .socket_id = rte_socket_id(),
 884         };
 885
 886         /* Initialize ethertype filter rule list and hash */
 887         TAILQ_INIT(&ethertype_rule->ethertype_list);
 888         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 889                  "ethertype_%s", dev->device->name);
 890         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 891         if (!ethertype_rule->hash_table) {
 892                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 893                 return -EINVAL;
 894         }
 895         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 896                                        sizeof(struct i40e_ethertype_filter *) *
 897                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 898                                        0);
 899         if (!ethertype_rule->hash_map) {
 900                 PMD_INIT_LOG(ERR,
 901                              "Failed to allocate memory for ethertype hash map!");
 902                 ret = -ENOMEM;
 903                 goto err_ethertype_hash_map_alloc;
 904         }
 905
 906         return 0;
 907
 908 err_ethertype_hash_map_alloc:
 909         rte_hash_free(ethertype_rule->hash_table);
 910
 911         return ret;
 912 }
 913
 914 static int
 915 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 916 {
 917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 918         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 919         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 920         int ret;
 921
 922         struct rte_hash_parameters tunnel_hash_params = {
 923                 .name = tunnel_hash_name,
 924                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 925                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 926                 .hash_func = rte_hash_crc,
 927                 .hash_func_init_val = 0,
 928                 .socket_id = rte_socket_id(),
 929         };
 930
 931         /* Initialize tunnel filter rule list and hash */
 932         TAILQ_INIT(&tunnel_rule->tunnel_list);
 933         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 934                  "tunnel_%s", dev->device->name);
 935         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 936         if (!tunnel_rule->hash_table) {
 937                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 938                 return -EINVAL;
 939         }
 940         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 941                                     sizeof(struct i40e_tunnel_filter *) *
 942                                     I40E_MAX_TUNNEL_FILTER_NUM,
 943                                     0);
 944         if (!tunnel_rule->hash_map) {
 945                 PMD_INIT_LOG(ERR,
 946                              "Failed to allocate memory for tunnel hash map!");
 947                 ret = -ENOMEM;
 948                 goto err_tunnel_hash_map_alloc;
 949         }
 950
 951         return 0;
 952
 953 err_tunnel_hash_map_alloc:
 954         rte_hash_free(tunnel_rule->hash_table);
 955
 956         return ret;
 957 }
 958
 959 static int
 960 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 961 {
 962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 963         struct i40e_fdir_info *fdir_info = &pf->fdir;
 964         char fdir_hash_name[RTE_HASH_NAMESIZE];
 965         int ret;
 966
 967         struct rte_hash_parameters fdir_hash_params = {
 968                 .name = fdir_hash_name,
 969                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 970                 .key_len = sizeof(struct i40e_fdir_input),
 971                 .hash_func = rte_hash_crc,
 972                 .hash_func_init_val = 0,
 973                 .socket_id = rte_socket_id(),
 974         };
 975
 976         /* Initialize flow director filter rule list and hash */
 977         TAILQ_INIT(&fdir_info->fdir_list);
 978         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 979                  "fdir_%s", dev->device->name);
 980         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 981         if (!fdir_info->hash_table) {
 982                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 983                 return -EINVAL;
 984         }
 985         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 986                                           sizeof(struct i40e_fdir_filter *) *
 987                                           I40E_MAX_FDIR_FILTER_NUM,
 988                                           0);
 989         if (!fdir_info->hash_map) {
 990                 PMD_INIT_LOG(ERR,
 991                              "Failed to allocate memory for fdir hash map!");
 992                 ret = -ENOMEM;
 993                 goto err_fdir_hash_map_alloc;
 994         }
 995         return 0;
 996
 997 err_fdir_hash_map_alloc:
 998         rte_hash_free(fdir_info->hash_table);
 999
1000         return ret;
1001 }
1002
1003 static void
1004 i40e_init_customized_info(struct i40e_pf *pf)
1005 {
1006         int i;
1007
1008         /* Initialize customized pctype */
1009         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1010                 pf->customized_pctype[i].index = i;
1011                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1012                 pf->customized_pctype[i].valid = false;
1013         }
1014
1015         pf->gtp_support = false;
1016 }
1017
1018 void
1019 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1020 {
1021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023         struct i40e_queue_regions *info = &pf->queue_region;
1024         uint16_t i;
1025
1026         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1027                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1028
1029         memset(info, 0, sizeof(struct i40e_queue_regions));
1030 }
1031
1032 static int
1033 eth_i40e_dev_init(struct rte_eth_dev *dev)
1034 {
1035         struct rte_pci_device *pci_dev;
1036         struct rte_intr_handle *intr_handle;
1037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039         struct i40e_vsi *vsi;
1040         int ret;
1041         uint32_t len;
1042         uint8_t aq_fail = 0;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         dev->dev_ops = &i40e_eth_dev_ops;
1047         dev->rx_pkt_burst = i40e_recv_pkts;
1048         dev->tx_pkt_burst = i40e_xmit_pkts;
1049         dev->tx_pkt_prepare = i40e_prep_pkts;
1050
1051         /* for secondary processes, we don't initialise any further as primary
1052          * has already done this work. Only check we don't need a different
1053          * RX function */
1054         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1055                 i40e_set_rx_function(dev);
1056                 i40e_set_tx_function(dev);
1057                 return 0;
1058         }
1059         i40e_set_default_ptype_table(dev);
1060         i40e_set_default_pctype_table(dev);
1061         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1062         intr_handle = &pci_dev->intr_handle;
1063
1064         rte_eth_copy_pci_info(dev, pci_dev);
1065
1066         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1067         pf->adapter->eth_dev = dev;
1068         pf->dev_data = dev->data;
1069
1070         hw->back = I40E_PF_TO_ADAPTER(pf);
1071         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1072         if (!hw->hw_addr) {
1073                 PMD_INIT_LOG(ERR,
1074                         "Hardware is not available, as address is NULL");
1075                 return -ENODEV;
1076         }
1077
1078         hw->vendor_id = pci_dev->id.vendor_id;
1079         hw->device_id = pci_dev->id.device_id;
1080         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1081         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1082         hw->bus.device = pci_dev->addr.devid;
1083         hw->bus.func = pci_dev->addr.function;
1084         hw->adapter_stopped = 0;
1085
1086         /* Make sure all is clean before doing PF reset */
1087         i40e_clear_hw(hw);
1088
1089         /* Initialize the hardware */
1090         i40e_hw_init(dev);
1091
1092         /* Reset here to make sure all is clean for each PF */
1093         ret = i40e_pf_reset(hw);
1094         if (ret) {
1095                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1096                 return ret;
1097         }
1098
1099         /* Initialize the shared code (base driver) */
1100         ret = i40e_init_shared_code(hw);
1101         if (ret) {
1102                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1103                 return ret;
1104         }
1105
1106         /*
1107          * To work around the NVM issue, initialize registers
1108          * for packet type of QinQ by software.
1109          * It should be removed once issues are fixed in NVM.
1110          */
1111         i40e_GLQF_reg_init(hw);
1112
1113         /* Initialize the input set for filters (hash and fd) to default value */
1114         i40e_filter_input_set_init(pf);
1115
1116         /* Initialize the parameters for adminq */
1117         i40e_init_adminq_parameter(hw);
1118         ret = i40e_init_adminq(hw);
1119         if (ret != I40E_SUCCESS) {
1120                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1121                 return -EIO;
1122         }
1123         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1124                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1125                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1126                      ((hw->nvm.version >> 12) & 0xf),
1127                      ((hw->nvm.version >> 4) & 0xff),
1128                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1129
1130         /* initialise the L3_MAP register */
1131         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1132                                    0x00000028,  NULL);
1133         if (ret)
1134                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1135
1136         /* Need the special FW version to support floating VEB */
1137         config_floating_veb(dev);
1138         /* Clear PXE mode */
1139         i40e_clear_pxe_mode(hw);
1140         i40e_dev_sync_phy_type(hw);
1141
1142         /*
1143          * On X710, performance number is far from the expectation on recent
1144          * firmware versions. The fix for this issue may not be integrated in
1145          * the following firmware version. So the workaround in software driver
1146          * is needed. It needs to modify the initial values of 3 internal only
1147          * registers. Note that the workaround can be removed when it is fixed
1148          * in firmware in the future.
1149          */
1150         i40e_configure_registers(hw);
1151
1152         /* Get hw capabilities */
1153         ret = i40e_get_cap(hw);
1154         if (ret != I40E_SUCCESS) {
1155                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1156                 goto err_get_capabilities;
1157         }
1158
1159         /* Initialize parameters for PF */
1160         ret = i40e_pf_parameter_init(dev);
1161         if (ret != 0) {
1162                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1163                 goto err_parameter_init;
1164         }
1165
1166         /* Initialize the queue management */
1167         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1168         if (ret < 0) {
1169                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1170                 goto err_qp_pool_init;
1171         }
1172         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1173                                 hw->func_caps.num_msix_vectors - 1);
1174         if (ret < 0) {
1175                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1176                 goto err_msix_pool_init;
1177         }
1178
1179         /* Initialize lan hmc */
1180         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1181                                 hw->func_caps.num_rx_qp, 0, 0);
1182         if (ret != I40E_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1184                 goto err_init_lan_hmc;
1185         }
1186
1187         /* Configure lan hmc */
1188         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1189         if (ret != I40E_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1191                 goto err_configure_lan_hmc;
1192         }
1193
1194         /* Get and check the mac address */
1195         i40e_get_mac_addr(hw, hw->mac.addr);
1196         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "mac address is not valid");
1198                 ret = -EIO;
1199                 goto err_get_mac_addr;
1200         }
1201         /* Copy the permanent MAC address */
1202         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1203                         (struct ether_addr *) hw->mac.perm_addr);
1204
1205         /* Disable flow control */
1206         hw->fc.requested_mode = I40E_FC_NONE;
1207         i40e_set_fc(hw, &aq_fail, TRUE);
1208
1209         /* Set the global registers with default ether type value */
1210         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1211         if (ret != I40E_SUCCESS) {
1212                 PMD_INIT_LOG(ERR,
1213                         "Failed to set the default outer VLAN ether type");
1214                 goto err_setup_pf_switch;
1215         }
1216
1217         /* PF setup, which includes VSI setup */
1218         ret = i40e_pf_setup(pf);
1219         if (ret) {
1220                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1221                 goto err_setup_pf_switch;
1222         }
1223
1224         /* reset all stats of the device, including pf and main vsi */
1225         i40e_dev_stats_reset(dev);
1226
1227         vsi = pf->main_vsi;
1228
1229         /* Disable double vlan by default */
1230         i40e_vsi_config_double_vlan(vsi, FALSE);
1231
1232         /* Disable S-TAG identification when floating_veb is disabled */
1233         if (!pf->floating_veb) {
1234                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1235                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1236                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1237                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1238                 }
1239         }
1240
1241         if (!vsi->max_macaddrs)
1242                 len = ETHER_ADDR_LEN;
1243         else
1244                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1245
1246         /* Should be after VSI initialized */
1247         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1248         if (!dev->data->mac_addrs) {
1249                 PMD_INIT_LOG(ERR,
1250                         "Failed to allocated memory for storing mac address");
1251                 goto err_mac_alloc;
1252         }
1253         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1254                                         &dev->data->mac_addrs[0]);
1255
1256         /* Init dcb to sw mode by default */
1257         ret = i40e_dcb_init_configure(dev, TRUE);
1258         if (ret != I40E_SUCCESS) {
1259                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1260                 pf->flags &= ~I40E_FLAG_DCB;
1261         }
1262         /* Update HW struct after DCB configuration */
1263         i40e_get_cap(hw);
1264
1265         /* initialize pf host driver to setup SRIOV resource if applicable */
1266         i40e_pf_host_init(dev);
1267
1268         /* register callback func to eal lib */
1269         rte_intr_callback_register(intr_handle,
1270                                    i40e_dev_interrupt_handler, dev);
1271
1272         /* configure and enable device interrupt */
1273         i40e_pf_config_irq0(hw, TRUE);
1274         i40e_pf_enable_irq0(hw);
1275
1276         /* enable uio intr after callback register */
1277         rte_intr_enable(intr_handle);
1278
1279         /* By default disable flexible payload in global configuration */
1280         i40e_flex_payload_reg_set_default(hw);
1281
1282         /*
1283          * Add an ethertype filter to drop all flow control frames transmitted
1284          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1285          * frames to wire.
1286          */
1287         i40e_add_tx_flow_control_drop_filter(pf);
1288
1289         /* Set the max frame size to 0x2600 by default,
1290          * in case other drivers changed the default value.
1291          */
1292         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1293
1294         /* initialize mirror rule list */
1295         TAILQ_INIT(&pf->mirror_list);
1296
1297         /* initialize Traffic Manager configuration */
1298         i40e_tm_conf_init(dev);
1299
1300         /* Initialize customized information */
1301         i40e_init_customized_info(pf);
1302
1303         ret = i40e_init_ethtype_filter_list(dev);
1304         if (ret < 0)
1305                 goto err_init_ethtype_filter_list;
1306         ret = i40e_init_tunnel_filter_list(dev);
1307         if (ret < 0)
1308                 goto err_init_tunnel_filter_list;
1309         ret = i40e_init_fdir_filter_list(dev);
1310         if (ret < 0)
1311                 goto err_init_fdir_filter_list;
1312
1313         /* initialize queue region configuration */
1314         i40e_init_queue_region_conf(dev);
1315
1316         return 0;
1317
1318 err_init_fdir_filter_list:
1319         rte_free(pf->tunnel.hash_table);
1320         rte_free(pf->tunnel.hash_map);
1321 err_init_tunnel_filter_list:
1322         rte_free(pf->ethertype.hash_table);
1323         rte_free(pf->ethertype.hash_map);
1324 err_init_ethtype_filter_list:
1325         rte_free(dev->data->mac_addrs);
1326 err_mac_alloc:
1327         i40e_vsi_release(pf->main_vsi);
1328 err_setup_pf_switch:
1329 err_get_mac_addr:
1330 err_configure_lan_hmc:
1331         (void)i40e_shutdown_lan_hmc(hw);
1332 err_init_lan_hmc:
1333         i40e_res_pool_destroy(&pf->msix_pool);
1334 err_msix_pool_init:
1335         i40e_res_pool_destroy(&pf->qp_pool);
1336 err_qp_pool_init:
1337 err_parameter_init:
1338 err_get_capabilities:
1339         (void)i40e_shutdown_adminq(hw);
1340
1341         return ret;
1342 }
1343
1344 static void
1345 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1346 {
1347         struct i40e_ethertype_filter *p_ethertype;
1348         struct i40e_ethertype_rule *ethertype_rule;
1349
1350         ethertype_rule = &pf->ethertype;
1351         /* Remove all ethertype filter rules and hash */
1352         if (ethertype_rule->hash_map)
1353                 rte_free(ethertype_rule->hash_map);
1354         if (ethertype_rule->hash_table)
1355                 rte_hash_free(ethertype_rule->hash_table);
1356
1357         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1358                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1359                              p_ethertype, rules);
1360                 rte_free(p_ethertype);
1361         }
1362 }
1363
1364 static void
1365 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1366 {
1367         struct i40e_tunnel_filter *p_tunnel;
1368         struct i40e_tunnel_rule *tunnel_rule;
1369
1370         tunnel_rule = &pf->tunnel;
1371         /* Remove all tunnel director rules and hash */
1372         if (tunnel_rule->hash_map)
1373                 rte_free(tunnel_rule->hash_map);
1374         if (tunnel_rule->hash_table)
1375                 rte_hash_free(tunnel_rule->hash_table);
1376
1377         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1378                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1379                 rte_free(p_tunnel);
1380         }
1381 }
1382
1383 static void
1384 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1385 {
1386         struct i40e_fdir_filter *p_fdir;
1387         struct i40e_fdir_info *fdir_info;
1388
1389         fdir_info = &pf->fdir;
1390         /* Remove all flow director rules and hash */
1391         if (fdir_info->hash_map)
1392                 rte_free(fdir_info->hash_map);
1393         if (fdir_info->hash_table)
1394                 rte_hash_free(fdir_info->hash_table);
1395
1396         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1397                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1398                 rte_free(p_fdir);
1399         }
1400 }
1401
1402 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1403 {
1404         /*
1405          * Disable by default flexible payload
1406          * for corresponding L2/L3/L4 layers.
1407          */
1408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1410         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1411 }
1412
1413 static int
1414 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1415 {
1416         struct i40e_pf *pf;
1417         struct rte_pci_device *pci_dev;
1418         struct rte_intr_handle *intr_handle;
1419         struct i40e_hw *hw;
1420         struct i40e_filter_control_settings settings;
1421         struct rte_flow *p_flow;
1422         int ret;
1423         uint8_t aq_fail = 0;
1424
1425         PMD_INIT_FUNC_TRACE();
1426
1427         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1428                 return 0;
1429
1430         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1431         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1432         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1433         intr_handle = &pci_dev->intr_handle;
1434
1435         if (hw->adapter_stopped == 0)
1436                 i40e_dev_close(dev);
1437
1438         dev->dev_ops = NULL;
1439         dev->rx_pkt_burst = NULL;
1440         dev->tx_pkt_burst = NULL;
1441
1442         /* Clear PXE mode */
1443         i40e_clear_pxe_mode(hw);
1444
1445         /* Unconfigure filter control */
1446         memset(&settings, 0, sizeof(settings));
1447         ret = i40e_set_filter_control(hw, &settings);
1448         if (ret)
1449                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1450                                         ret);
1451
1452         /* Disable flow control */
1453         hw->fc.requested_mode = I40E_FC_NONE;
1454         i40e_set_fc(hw, &aq_fail, TRUE);
1455
1456         /* uninitialize pf host driver */
1457         i40e_pf_host_uninit(dev);
1458
1459         rte_free(dev->data->mac_addrs);
1460         dev->data->mac_addrs = NULL;
1461
1462         /* disable uio intr before callback unregister */
1463         rte_intr_disable(intr_handle);
1464
1465         /* register callback func to eal lib */
1466         rte_intr_callback_unregister(intr_handle,
1467                                      i40e_dev_interrupt_handler, dev);
1468
1469         i40e_rm_ethtype_filter_list(pf);
1470         i40e_rm_tunnel_filter_list(pf);
1471         i40e_rm_fdir_filter_list(pf);
1472
1473         /* Remove all flows */
1474         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1475                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1476                 rte_free(p_flow);
1477         }
1478
1479         /* Remove all Traffic Manager configuration */
1480         i40e_tm_conf_uninit(dev);
1481
1482         return 0;
1483 }
1484
1485 static int
1486 i40e_dev_configure(struct rte_eth_dev *dev)
1487 {
1488         struct i40e_adapter *ad =
1489                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1490         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1492         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1493         int i, ret;
1494
1495         ret = i40e_dev_sync_phy_type(hw);
1496         if (ret)
1497                 return ret;
1498
1499         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1500          * bulk allocation or vector Rx preconditions we will reset it.
1501          */
1502         ad->rx_bulk_alloc_allowed = true;
1503         ad->rx_vec_allowed = true;
1504         ad->tx_simple_allowed = true;
1505         ad->tx_vec_allowed = true;
1506
1507         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1508                 ret = i40e_fdir_setup(pf);
1509                 if (ret != I40E_SUCCESS) {
1510                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1511                         return -ENOTSUP;
1512                 }
1513                 ret = i40e_fdir_configure(dev);
1514                 if (ret < 0) {
1515                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1516                         goto err;
1517                 }
1518         } else
1519                 i40e_fdir_teardown(pf);
1520
1521         ret = i40e_dev_init_vlan(dev);
1522         if (ret < 0)
1523                 goto err;
1524
1525         /* VMDQ setup.
1526          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1527          *  RSS setting have different requirements.
1528          *  General PMD driver call sequence are NIC init, configure,
1529          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1530          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1531          *  applicable. So, VMDQ setting has to be done before
1532          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1533          *  For RSS setting, it will try to calculate actual configured RX queue
1534          *  number, which will be available after rx_queue_setup(). dev_start()
1535          *  function is good to place RSS setup.
1536          */
1537         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1538                 ret = i40e_vmdq_setup(dev);
1539                 if (ret)
1540                         goto err;
1541         }
1542
1543         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1544                 ret = i40e_dcb_setup(dev);
1545                 if (ret) {
1546                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1547                         goto err_dcb;
1548                 }
1549         }
1550
1551         TAILQ_INIT(&pf->flow_list);
1552
1553         return 0;
1554
1555 err_dcb:
1556         /* need to release vmdq resource if exists */
1557         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1558                 i40e_vsi_release(pf->vmdq[i].vsi);
1559                 pf->vmdq[i].vsi = NULL;
1560         }
1561         rte_free(pf->vmdq);
1562         pf->vmdq = NULL;
1563 err:
1564         /* need to release fdir resource if exists */
1565         i40e_fdir_teardown(pf);
1566         return ret;
1567 }
1568
1569 void
1570 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1571 {
1572         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1573         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1575         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1576         uint16_t msix_vect = vsi->msix_intr;
1577         uint16_t i;
1578
1579         for (i = 0; i < vsi->nb_qps; i++) {
1580                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1581                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1582                 rte_wmb();
1583         }
1584
1585         if (vsi->type != I40E_VSI_SRIOV) {
1586                 if (!rte_intr_allow_others(intr_handle)) {
1587                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1588                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1589                         I40E_WRITE_REG(hw,
1590                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1591                                        0);
1592                 } else {
1593                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1594                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1595                         I40E_WRITE_REG(hw,
1596                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1597                                                        msix_vect - 1), 0);
1598                 }
1599         } else {
1600                 uint32_t reg;
1601                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1602                         vsi->user_param + (msix_vect - 1);
1603
1604                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1605                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1606         }
1607         I40E_WRITE_FLUSH(hw);
1608 }
1609
1610 static void
1611 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1612                        int base_queue, int nb_queue,
1613                        uint16_t itr_idx)
1614 {
1615         int i;
1616         uint32_t val;
1617         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1618
1619         /* Bind all RX queues to allocated MSIX interrupt */
1620         for (i = 0; i < nb_queue; i++) {
1621                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1622                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1623                         ((base_queue + i + 1) <<
1624                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1625                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1626                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1627
1628                 if (i == nb_queue - 1)
1629                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1630                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1631         }
1632
1633         /* Write first RX queue to Link list register as the head element */
1634         if (vsi->type != I40E_VSI_SRIOV) {
1635                 uint16_t interval =
1636                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1637
1638                 if (msix_vect == I40E_MISC_VEC_ID) {
1639                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1640                                        (base_queue <<
1641                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642                                        (0x0 <<
1643                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644                         I40E_WRITE_REG(hw,
1645                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1646                                        interval);
1647                 } else {
1648                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1649                                        (base_queue <<
1650                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1651                                        (0x0 <<
1652                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1653                         I40E_WRITE_REG(hw,
1654                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1655                                                        msix_vect - 1),
1656                                        interval);
1657                 }
1658         } else {
1659                 uint32_t reg;
1660
1661                 if (msix_vect == I40E_MISC_VEC_ID) {
1662                         I40E_WRITE_REG(hw,
1663                                        I40E_VPINT_LNKLST0(vsi->user_param),
1664                                        (base_queue <<
1665                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1666                                        (0x0 <<
1667                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1668                 } else {
1669                         /* num_msix_vectors_vf needs to minus irq0 */
1670                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1671                                 vsi->user_param + (msix_vect - 1);
1672
1673                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1674                                        (base_queue <<
1675                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1676                                        (0x0 <<
1677                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1678                 }
1679         }
1680
1681         I40E_WRITE_FLUSH(hw);
1682 }
1683
1684 void
1685 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1686 {
1687         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1691         uint16_t msix_vect = vsi->msix_intr;
1692         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1693         uint16_t queue_idx = 0;
1694         int record = 0;
1695         uint32_t val;
1696         int i;
1697
1698         for (i = 0; i < vsi->nb_qps; i++) {
1699                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1700                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1701         }
1702
1703         /* INTENA flag is not auto-cleared for interrupt */
1704         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1705         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1706                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1707                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1708         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1709
1710         /* VF bind interrupt */
1711         if (vsi->type == I40E_VSI_SRIOV) {
1712                 __vsi_queues_bind_intr(vsi, msix_vect,
1713                                        vsi->base_queue, vsi->nb_qps,
1714                                        itr_idx);
1715                 return;
1716         }
1717
1718         /* PF & VMDq bind interrupt */
1719         if (rte_intr_dp_is_en(intr_handle)) {
1720                 if (vsi->type == I40E_VSI_MAIN) {
1721                         queue_idx = 0;
1722                         record = 1;
1723                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1724                         struct i40e_vsi *main_vsi =
1725                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1726                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1727                         record = 1;
1728                 }
1729         }
1730
1731         for (i = 0; i < vsi->nb_used_qps; i++) {
1732                 if (nb_msix <= 1) {
1733                         if (!rte_intr_allow_others(intr_handle))
1734                                 /* allow to share MISC_VEC_ID */
1735                                 msix_vect = I40E_MISC_VEC_ID;
1736
1737                         /* no enough msix_vect, map all to one */
1738                         __vsi_queues_bind_intr(vsi, msix_vect,
1739                                                vsi->base_queue + i,
1740                                                vsi->nb_used_qps - i,
1741                                                itr_idx);
1742                         for (; !!record && i < vsi->nb_used_qps; i++)
1743                                 intr_handle->intr_vec[queue_idx + i] =
1744                                         msix_vect;
1745                         break;
1746                 }
1747                 /* 1:1 queue/msix_vect mapping */
1748                 __vsi_queues_bind_intr(vsi, msix_vect,
1749                                        vsi->base_queue + i, 1,
1750                                        itr_idx);
1751                 if (!!record)
1752                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1753
1754                 msix_vect++;
1755                 nb_msix--;
1756         }
1757 }
1758
1759 static void
1760 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1761 {
1762         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1763         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1764         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1766         uint16_t interval = i40e_calc_itr_interval(\
1767                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1768         uint16_t msix_intr, i;
1769
1770         if (rte_intr_allow_others(intr_handle))
1771                 for (i = 0; i < vsi->nb_msix; i++) {
1772                         msix_intr = vsi->msix_intr + i;
1773                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1774                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1775                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1776                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1777                                 (interval <<
1778                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1779                 }
1780         else
1781                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1782                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1783                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1784                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1785                                (interval <<
1786                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1787
1788         I40E_WRITE_FLUSH(hw);
1789 }
1790
1791 static void
1792 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1793 {
1794         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1795         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1796         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1797         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1798         uint16_t msix_intr, i;
1799
1800         if (rte_intr_allow_others(intr_handle))
1801                 for (i = 0; i < vsi->nb_msix; i++) {
1802                         msix_intr = vsi->msix_intr + i;
1803                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1804                                        0);
1805                 }
1806         else
1807                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1808
1809         I40E_WRITE_FLUSH(hw);
1810 }
1811
1812 static inline uint8_t
1813 i40e_parse_link_speeds(uint16_t link_speeds)
1814 {
1815         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1816
1817         if (link_speeds & ETH_LINK_SPEED_40G)
1818                 link_speed |= I40E_LINK_SPEED_40GB;
1819         if (link_speeds & ETH_LINK_SPEED_25G)
1820                 link_speed |= I40E_LINK_SPEED_25GB;
1821         if (link_speeds & ETH_LINK_SPEED_20G)
1822                 link_speed |= I40E_LINK_SPEED_20GB;
1823         if (link_speeds & ETH_LINK_SPEED_10G)
1824                 link_speed |= I40E_LINK_SPEED_10GB;
1825         if (link_speeds & ETH_LINK_SPEED_1G)
1826                 link_speed |= I40E_LINK_SPEED_1GB;
1827         if (link_speeds & ETH_LINK_SPEED_100M)
1828                 link_speed |= I40E_LINK_SPEED_100MB;
1829
1830         return link_speed;
1831 }
1832
1833 static int
1834 i40e_phy_conf_link(struct i40e_hw *hw,
1835                    uint8_t abilities,
1836                    uint8_t force_speed,
1837                    bool is_up)
1838 {
1839         enum i40e_status_code status;
1840         struct i40e_aq_get_phy_abilities_resp phy_ab;
1841         struct i40e_aq_set_phy_config phy_conf;
1842         enum i40e_aq_phy_type cnt;
1843         uint32_t phy_type_mask = 0;
1844
1845         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1846                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1847                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1848                         I40E_AQ_PHY_FLAG_LOW_POWER;
1849         const uint8_t advt = I40E_LINK_SPEED_40GB |
1850                         I40E_LINK_SPEED_25GB |
1851                         I40E_LINK_SPEED_10GB |
1852                         I40E_LINK_SPEED_1GB |
1853                         I40E_LINK_SPEED_100MB;
1854         int ret = -ENOTSUP;
1855
1856
1857         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1858                                               NULL);
1859         if (status)
1860                 return ret;
1861
1862         /* If link already up, no need to set up again */
1863         if (is_up && phy_ab.phy_type != 0)
1864                 return I40E_SUCCESS;
1865
1866         memset(&phy_conf, 0, sizeof(phy_conf));
1867
1868         /* bits 0-2 use the values from get_phy_abilities_resp */
1869         abilities &= ~mask;
1870         abilities |= phy_ab.abilities & mask;
1871
1872         /* update ablities and speed */
1873         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1874                 phy_conf.link_speed = advt;
1875         else
1876                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1877
1878         phy_conf.abilities = abilities;
1879
1880
1881
1882         /* To enable link, phy_type mask needs to include each type */
1883         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1884                 phy_type_mask |= 1 << cnt;
1885
1886         /* use get_phy_abilities_resp value for the rest */
1887         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1888         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1889                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1890                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1891         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1892         phy_conf.eee_capability = phy_ab.eee_capability;
1893         phy_conf.eeer = phy_ab.eeer_val;
1894         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1895
1896         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1897                     phy_ab.abilities, phy_ab.link_speed);
1898         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1899                     phy_conf.abilities, phy_conf.link_speed);
1900
1901         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1902         if (status)
1903                 return ret;
1904
1905         return I40E_SUCCESS;
1906 }
1907
1908 static int
1909 i40e_apply_link_speed(struct rte_eth_dev *dev)
1910 {
1911         uint8_t speed;
1912         uint8_t abilities = 0;
1913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914         struct rte_eth_conf *conf = &dev->data->dev_conf;
1915
1916         speed = i40e_parse_link_speeds(conf->link_speeds);
1917         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1918         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1919                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1920         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1921
1922         return i40e_phy_conf_link(hw, abilities, speed, true);
1923 }
1924
1925 static int
1926 i40e_dev_start(struct rte_eth_dev *dev)
1927 {
1928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1930         struct i40e_vsi *main_vsi = pf->main_vsi;
1931         int ret, i;
1932         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1933         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1934         uint32_t intr_vector = 0;
1935         struct i40e_vsi *vsi;
1936
1937         hw->adapter_stopped = 0;
1938
1939         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1940                 PMD_INIT_LOG(ERR,
1941                 "Invalid link_speeds for port %u, autonegotiation disabled",
1942                               dev->data->port_id);
1943                 return -EINVAL;
1944         }
1945
1946         rte_intr_disable(intr_handle);
1947
1948         if ((rte_intr_cap_multiple(intr_handle) ||
1949              !RTE_ETH_DEV_SRIOV(dev).active) &&
1950             dev->data->dev_conf.intr_conf.rxq != 0) {
1951                 intr_vector = dev->data->nb_rx_queues;
1952                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1953                 if (ret)
1954                         return ret;
1955         }
1956
1957         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1958                 intr_handle->intr_vec =
1959                         rte_zmalloc("intr_vec",
1960                                     dev->data->nb_rx_queues * sizeof(int),
1961                                     0);
1962                 if (!intr_handle->intr_vec) {
1963                         PMD_INIT_LOG(ERR,
1964                                 "Failed to allocate %d rx_queues intr_vec",
1965                                 dev->data->nb_rx_queues);
1966                         return -ENOMEM;
1967                 }
1968         }
1969
1970         /* Initialize VSI */
1971         ret = i40e_dev_rxtx_init(pf);
1972         if (ret != I40E_SUCCESS) {
1973                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1974                 goto err_up;
1975         }
1976
1977         /* Map queues with MSIX interrupt */
1978         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1979                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1980         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1981         i40e_vsi_enable_queues_intr(main_vsi);
1982
1983         /* Map VMDQ VSI queues with MSIX interrupt */
1984         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1985                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1986                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1987                                           I40E_ITR_INDEX_DEFAULT);
1988                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1989         }
1990
1991         /* enable FDIR MSIX interrupt */
1992         if (pf->fdir.fdir_vsi) {
1993                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1994                                           I40E_ITR_INDEX_NONE);
1995                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1996         }
1997
1998         /* Enable all queues which have been configured */
1999         ret = i40e_dev_switch_queues(pf, TRUE);
2000
2001         if (ret != I40E_SUCCESS) {
2002                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2003                 goto err_up;
2004         }
2005
2006         /* Enable receiving broadcast packets */
2007         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2008         if (ret != I40E_SUCCESS)
2009                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2010
2011         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2012                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2013                                                 true, NULL);
2014                 if (ret != I40E_SUCCESS)
2015                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2016         }
2017
2018         /* Enable the VLAN promiscuous mode. */
2019         if (pf->vfs) {
2020                 for (i = 0; i < pf->vf_num; i++) {
2021                         vsi = pf->vfs[i].vsi;
2022                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2023                                                      true, NULL);
2024                 }
2025         }
2026
2027         /* Enable mac loopback mode */
2028         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2029             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2030                 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2031                 if (ret != I40E_SUCCESS) {
2032                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2033                         goto err_up;
2034                 }
2035         }
2036
2037         /* Apply link configure */
2038         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2039                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2040                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2041                                 ETH_LINK_SPEED_40G)) {
2042                 PMD_DRV_LOG(ERR, "Invalid link setting");
2043                 goto err_up;
2044         }
2045         ret = i40e_apply_link_speed(dev);
2046         if (I40E_SUCCESS != ret) {
2047                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2048                 goto err_up;
2049         }
2050
2051         if (!rte_intr_allow_others(intr_handle)) {
2052                 rte_intr_callback_unregister(intr_handle,
2053                                              i40e_dev_interrupt_handler,
2054                                              (void *)dev);
2055                 /* configure and enable device interrupt */
2056                 i40e_pf_config_irq0(hw, FALSE);
2057                 i40e_pf_enable_irq0(hw);
2058
2059                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2060                         PMD_INIT_LOG(INFO,
2061                                 "lsc won't enable because of no intr multiplex");
2062         } else {
2063                 ret = i40e_aq_set_phy_int_mask(hw,
2064                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2065                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2066                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2067                 if (ret != I40E_SUCCESS)
2068                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2069
2070                 /* Call get_link_info aq commond to enable/disable LSE */
2071                 i40e_dev_link_update(dev, 0);
2072         }
2073
2074         /* enable uio intr after callback register */
2075         rte_intr_enable(intr_handle);
2076
2077         i40e_filter_restore(pf);
2078
2079         if (pf->tm_conf.root && !pf->tm_conf.committed)
2080                 PMD_DRV_LOG(WARNING,
2081                             "please call hierarchy_commit() "
2082                             "before starting the port");
2083
2084         return I40E_SUCCESS;
2085
2086 err_up:
2087         i40e_dev_switch_queues(pf, FALSE);
2088         i40e_dev_clear_queues(dev);
2089
2090         return ret;
2091 }
2092
2093 static void
2094 i40e_dev_stop(struct rte_eth_dev *dev)
2095 {
2096         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2097         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098         struct i40e_vsi *main_vsi = pf->main_vsi;
2099         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2100         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2101         int i;
2102
2103         if (hw->adapter_stopped == 1)
2104                 return;
2105         /* Disable all queues */
2106         i40e_dev_switch_queues(pf, FALSE);
2107
2108         /* un-map queues with interrupt registers */
2109         i40e_vsi_disable_queues_intr(main_vsi);
2110         i40e_vsi_queues_unbind_intr(main_vsi);
2111
2112         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2113                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2114                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2115         }
2116
2117         if (pf->fdir.fdir_vsi) {
2118                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2119                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2120         }
2121         /* Clear all queues and release memory */
2122         i40e_dev_clear_queues(dev);
2123
2124         /* Set link down */
2125         i40e_dev_set_link_down(dev);
2126
2127         if (!rte_intr_allow_others(intr_handle))
2128                 /* resume to the default handler */
2129                 rte_intr_callback_register(intr_handle,
2130                                            i40e_dev_interrupt_handler,
2131                                            (void *)dev);
2132
2133         /* Clean datapath event and queue/vec mapping */
2134         rte_intr_efd_disable(intr_handle);
2135         if (intr_handle->intr_vec) {
2136                 rte_free(intr_handle->intr_vec);
2137                 intr_handle->intr_vec = NULL;
2138         }
2139
2140         /* reset hierarchy commit */
2141         pf->tm_conf.committed = false;
2142
2143         /* Remove all the queue region configuration */
2144         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2145
2146         hw->adapter_stopped = 1;
2147 }
2148
2149 static void
2150 i40e_dev_close(struct rte_eth_dev *dev)
2151 {
2152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2155         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2156         struct i40e_mirror_rule *p_mirror;
2157         uint32_t reg;
2158         int i;
2159         int ret;
2160
2161         PMD_INIT_FUNC_TRACE();
2162
2163         i40e_dev_stop(dev);
2164
2165         /* Remove all mirror rules */
2166         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2167                 ret = i40e_aq_del_mirror_rule(hw,
2168                                               pf->main_vsi->veb->seid,
2169                                               p_mirror->rule_type,
2170                                               p_mirror->entries,
2171                                               p_mirror->num_entries,
2172                                               p_mirror->id);
2173                 if (ret < 0)
2174                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2175                                     "status = %d, aq_err = %d.", ret,
2176                                     hw->aq.asq_last_status);
2177
2178                 /* remove mirror software resource anyway */
2179                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2180                 rte_free(p_mirror);
2181                 pf->nb_mirror_rule--;
2182         }
2183
2184         i40e_dev_free_queues(dev);
2185
2186         /* Disable interrupt */
2187         i40e_pf_disable_irq0(hw);
2188         rte_intr_disable(intr_handle);
2189
2190         /* shutdown and destroy the HMC */
2191         i40e_shutdown_lan_hmc(hw);
2192
2193         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2194                 i40e_vsi_release(pf->vmdq[i].vsi);
2195                 pf->vmdq[i].vsi = NULL;
2196         }
2197         rte_free(pf->vmdq);
2198         pf->vmdq = NULL;
2199
2200         /* release all the existing VSIs and VEBs */
2201         i40e_fdir_teardown(pf);
2202         i40e_vsi_release(pf->main_vsi);
2203
2204         /* shutdown the adminq */
2205         i40e_aq_queue_shutdown(hw, true);
2206         i40e_shutdown_adminq(hw);
2207
2208         i40e_res_pool_destroy(&pf->qp_pool);
2209         i40e_res_pool_destroy(&pf->msix_pool);
2210
2211         /* Disable flexible payload in global configuration */
2212         i40e_flex_payload_reg_set_default(hw);
2213
2214         /* force a PF reset to clean anything leftover */
2215         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2216         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2217                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2218         I40E_WRITE_FLUSH(hw);
2219 }
2220
2221 /*
2222  * Reset PF device only to re-initialize resources in PMD layer
2223  */
2224 static int
2225 i40e_dev_reset(struct rte_eth_dev *dev)
2226 {
2227         int ret;
2228
2229         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2230          * its VF to make them align with it. The detailed notification
2231          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2232          * To avoid unexpected behavior in VF, currently reset of PF with
2233          * SR-IOV activation is not supported. It might be supported later.
2234          */
2235         if (dev->data->sriov.active)
2236                 return -ENOTSUP;
2237
2238         ret = eth_i40e_dev_uninit(dev);
2239         if (ret)
2240                 return ret;
2241
2242         ret = eth_i40e_dev_init(dev);
2243
2244         return ret;
2245 }
2246
2247 static void
2248 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2249 {
2250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2252         struct i40e_vsi *vsi = pf->main_vsi;
2253         int status;
2254
2255         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2256                                                      true, NULL, true);
2257         if (status != I40E_SUCCESS)
2258                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2259
2260         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2261                                                         TRUE, NULL);
2262         if (status != I40E_SUCCESS)
2263                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2264
2265 }
2266
2267 static void
2268 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2269 {
2270         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2271         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2272         struct i40e_vsi *vsi = pf->main_vsi;
2273         int status;
2274
2275         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2276                                                      false, NULL, true);
2277         if (status != I40E_SUCCESS)
2278                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2279
2280         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2281                                                         false, NULL);
2282         if (status != I40E_SUCCESS)
2283                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2284 }
2285
2286 static void
2287 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2288 {
2289         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         struct i40e_vsi *vsi = pf->main_vsi;
2292         int ret;
2293
2294         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2295         if (ret != I40E_SUCCESS)
2296                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2297 }
2298
2299 static void
2300 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2301 {
2302         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2303         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2304         struct i40e_vsi *vsi = pf->main_vsi;
2305         int ret;
2306
2307         if (dev->data->promiscuous == 1)
2308                 return; /* must remain in all_multicast mode */
2309
2310         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2311                                 vsi->seid, FALSE, NULL);
2312         if (ret != I40E_SUCCESS)
2313                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2314 }
2315
2316 /*
2317  * Set device link up.
2318  */
2319 static int
2320 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2321 {
2322         /* re-apply link speed setting */
2323         return i40e_apply_link_speed(dev);
2324 }
2325
2326 /*
2327  * Set device link down.
2328  */
2329 static int
2330 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2331 {
2332         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2333         uint8_t abilities = 0;
2334         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2335
2336         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2337         return i40e_phy_conf_link(hw, abilities, speed, false);
2338 }
2339
2340 int
2341 i40e_dev_link_update(struct rte_eth_dev *dev,
2342                      int wait_to_complete)
2343 {
2344 #define CHECK_INTERVAL 100  /* 100ms */
2345 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct i40e_link_status link_status;
2348         struct rte_eth_link link, old;
2349         int status;
2350         unsigned rep_cnt = MAX_REPEAT_TIME;
2351         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2352
2353         memset(&link, 0, sizeof(link));
2354         memset(&old, 0, sizeof(old));
2355         memset(&link_status, 0, sizeof(link_status));
2356         rte_i40e_dev_atomic_read_link_status(dev, &old);
2357
2358         do {
2359                 /* Get link status information from hardware */
2360                 status = i40e_aq_get_link_info(hw, enable_lse,
2361                                                 &link_status, NULL);
2362                 if (status != I40E_SUCCESS) {
2363                         link.link_speed = ETH_SPEED_NUM_100M;
2364                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2365                         PMD_DRV_LOG(ERR, "Failed to get link info");
2366                         goto out;
2367                 }
2368
2369                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2370                 if (!wait_to_complete || link.link_status)
2371                         break;
2372
2373                 rte_delay_ms(CHECK_INTERVAL);
2374         } while (--rep_cnt);
2375
2376         if (!link.link_status)
2377                 goto out;
2378
2379         /* i40e uses full duplex only */
2380         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2381
2382         /* Parse the link status */
2383         switch (link_status.link_speed) {
2384         case I40E_LINK_SPEED_100MB:
2385                 link.link_speed = ETH_SPEED_NUM_100M;
2386                 break;
2387         case I40E_LINK_SPEED_1GB:
2388                 link.link_speed = ETH_SPEED_NUM_1G;
2389                 break;
2390         case I40E_LINK_SPEED_10GB:
2391                 link.link_speed = ETH_SPEED_NUM_10G;
2392                 break;
2393         case I40E_LINK_SPEED_20GB:
2394                 link.link_speed = ETH_SPEED_NUM_20G;
2395                 break;
2396         case I40E_LINK_SPEED_25GB:
2397                 link.link_speed = ETH_SPEED_NUM_25G;
2398                 break;
2399         case I40E_LINK_SPEED_40GB:
2400                 link.link_speed = ETH_SPEED_NUM_40G;
2401                 break;
2402         default:
2403                 link.link_speed = ETH_SPEED_NUM_100M;
2404                 break;
2405         }
2406
2407         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2408                         ETH_LINK_SPEED_FIXED);
2409
2410 out:
2411         rte_i40e_dev_atomic_write_link_status(dev, &link);
2412         if (link.link_status == old.link_status)
2413                 return -1;
2414
2415         i40e_notify_all_vfs_link_status(dev);
2416
2417         return 0;
2418 }
2419
2420 /* Get all the statistics of a VSI */
2421 void
2422 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2423 {
2424         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2425         struct i40e_eth_stats *nes = &vsi->eth_stats;
2426         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2427         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2428
2429         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2430                             vsi->offset_loaded, &oes->rx_bytes,
2431                             &nes->rx_bytes);
2432         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2433                             vsi->offset_loaded, &oes->rx_unicast,
2434                             &nes->rx_unicast);
2435         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2436                             vsi->offset_loaded, &oes->rx_multicast,
2437                             &nes->rx_multicast);
2438         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2439                             vsi->offset_loaded, &oes->rx_broadcast,
2440                             &nes->rx_broadcast);
2441         /* exclude CRC bytes */
2442         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2443                 nes->rx_broadcast) * ETHER_CRC_LEN;
2444
2445         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2446                             &oes->rx_discards, &nes->rx_discards);
2447         /* GLV_REPC not supported */
2448         /* GLV_RMPC not supported */
2449         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2450                             &oes->rx_unknown_protocol,
2451                             &nes->rx_unknown_protocol);
2452         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2453                             vsi->offset_loaded, &oes->tx_bytes,
2454                             &nes->tx_bytes);
2455         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2456                             vsi->offset_loaded, &oes->tx_unicast,
2457                             &nes->tx_unicast);
2458         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2459                             vsi->offset_loaded, &oes->tx_multicast,
2460                             &nes->tx_multicast);
2461         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2462                             vsi->offset_loaded,  &oes->tx_broadcast,
2463                             &nes->tx_broadcast);
2464         /* GLV_TDPC not supported */
2465         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2466                             &oes->tx_errors, &nes->tx_errors);
2467         vsi->offset_loaded = true;
2468
2469         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2470                     vsi->vsi_id);
2471         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2472         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2473         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2474         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2475         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2476         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2477                     nes->rx_unknown_protocol);
2478         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2479         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2480         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2481         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2482         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2483         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2484         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2485                     vsi->vsi_id);
2486 }
2487
2488 static void
2489 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2490 {
2491         unsigned int i;
2492         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2493         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2494
2495         /* Get rx/tx bytes of internal transfer packets */
2496         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2497                         I40E_GLV_GORCL(hw->port),
2498                         pf->offset_loaded,
2499                         &pf->internal_stats_offset.rx_bytes,
2500                         &pf->internal_stats.rx_bytes);
2501
2502         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2503                         I40E_GLV_GOTCL(hw->port),
2504                         pf->offset_loaded,
2505                         &pf->internal_stats_offset.tx_bytes,
2506                         &pf->internal_stats.tx_bytes);
2507         /* Get total internal rx packet count */
2508         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2509                             I40E_GLV_UPRCL(hw->port),
2510                             pf->offset_loaded,
2511                             &pf->internal_stats_offset.rx_unicast,
2512                             &pf->internal_stats.rx_unicast);
2513         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2514                             I40E_GLV_MPRCL(hw->port),
2515                             pf->offset_loaded,
2516                             &pf->internal_stats_offset.rx_multicast,
2517                             &pf->internal_stats.rx_multicast);
2518         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2519                             I40E_GLV_BPRCL(hw->port),
2520                             pf->offset_loaded,
2521                             &pf->internal_stats_offset.rx_broadcast,
2522                             &pf->internal_stats.rx_broadcast);
2523         /* Get total internal tx packet count */
2524         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2525                             I40E_GLV_UPTCL(hw->port),
2526                             pf->offset_loaded,
2527                             &pf->internal_stats_offset.tx_unicast,
2528                             &pf->internal_stats.tx_unicast);
2529         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2530                             I40E_GLV_MPTCL(hw->port),
2531                             pf->offset_loaded,
2532                             &pf->internal_stats_offset.tx_multicast,
2533                             &pf->internal_stats.tx_multicast);
2534         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2535                             I40E_GLV_BPTCL(hw->port),
2536                             pf->offset_loaded,
2537                             &pf->internal_stats_offset.tx_broadcast,
2538                             &pf->internal_stats.tx_broadcast);
2539
2540         /* exclude CRC size */
2541         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2542                 pf->internal_stats.rx_multicast +
2543                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2544
2545         /* Get statistics of struct i40e_eth_stats */
2546         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2547                             I40E_GLPRT_GORCL(hw->port),
2548                             pf->offset_loaded, &os->eth.rx_bytes,
2549                             &ns->eth.rx_bytes);
2550         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2551                             I40E_GLPRT_UPRCL(hw->port),
2552                             pf->offset_loaded, &os->eth.rx_unicast,
2553                             &ns->eth.rx_unicast);
2554         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2555                             I40E_GLPRT_MPRCL(hw->port),
2556                             pf->offset_loaded, &os->eth.rx_multicast,
2557                             &ns->eth.rx_multicast);
2558         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2559                             I40E_GLPRT_BPRCL(hw->port),
2560                             pf->offset_loaded, &os->eth.rx_broadcast,
2561                             &ns->eth.rx_broadcast);
2562         /* Workaround: CRC size should not be included in byte statistics,
2563          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2564          */
2565         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2566                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2567
2568         /* exclude internal rx bytes
2569          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2570          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2571          * value.
2572          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2573          */
2574         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2575                 ns->eth.rx_bytes = 0;
2576         else
2577                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2578
2579         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2580                 ns->eth.rx_unicast = 0;
2581         else
2582                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2583
2584         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2585                 ns->eth.rx_multicast = 0;
2586         else
2587                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2588
2589         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2590                 ns->eth.rx_broadcast = 0;
2591         else
2592                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2593
2594         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2595                             pf->offset_loaded, &os->eth.rx_discards,
2596                             &ns->eth.rx_discards);
2597         /* GLPRT_REPC not supported */
2598         /* GLPRT_RMPC not supported */
2599         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2600                             pf->offset_loaded,
2601                             &os->eth.rx_unknown_protocol,
2602                             &ns->eth.rx_unknown_protocol);
2603         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2604                             I40E_GLPRT_GOTCL(hw->port),
2605                             pf->offset_loaded, &os->eth.tx_bytes,
2606                             &ns->eth.tx_bytes);
2607         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2608                             I40E_GLPRT_UPTCL(hw->port),
2609                             pf->offset_loaded, &os->eth.tx_unicast,
2610                             &ns->eth.tx_unicast);
2611         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2612                             I40E_GLPRT_MPTCL(hw->port),
2613                             pf->offset_loaded, &os->eth.tx_multicast,
2614                             &ns->eth.tx_multicast);
2615         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2616                             I40E_GLPRT_BPTCL(hw->port),
2617                             pf->offset_loaded, &os->eth.tx_broadcast,
2618                             &ns->eth.tx_broadcast);
2619         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2620                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2621
2622         /* exclude internal tx bytes
2623          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2624          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2625          * value.
2626          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2627          */
2628         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2629                 ns->eth.tx_bytes = 0;
2630         else
2631                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2632
2633         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2634                 ns->eth.tx_unicast = 0;
2635         else
2636                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2637
2638         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2639                 ns->eth.tx_multicast = 0;
2640         else
2641                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2642
2643         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2644                 ns->eth.tx_broadcast = 0;
2645         else
2646                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2647
2648         /* GLPRT_TEPC not supported */
2649
2650         /* additional port specific stats */
2651         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2652                             pf->offset_loaded, &os->tx_dropped_link_down,
2653                             &ns->tx_dropped_link_down);
2654         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2655                             pf->offset_loaded, &os->crc_errors,
2656                             &ns->crc_errors);
2657         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2658                             pf->offset_loaded, &os->illegal_bytes,
2659                             &ns->illegal_bytes);
2660         /* GLPRT_ERRBC not supported */
2661         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2662                             pf->offset_loaded, &os->mac_local_faults,
2663                             &ns->mac_local_faults);
2664         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2665                             pf->offset_loaded, &os->mac_remote_faults,
2666                             &ns->mac_remote_faults);
2667         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2668                             pf->offset_loaded, &os->rx_length_errors,
2669                             &ns->rx_length_errors);
2670         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2671                             pf->offset_loaded, &os->link_xon_rx,
2672                             &ns->link_xon_rx);
2673         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2674                             pf->offset_loaded, &os->link_xoff_rx,
2675                             &ns->link_xoff_rx);
2676         for (i = 0; i < 8; i++) {
2677                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2678                                     pf->offset_loaded,
2679                                     &os->priority_xon_rx[i],
2680                                     &ns->priority_xon_rx[i]);
2681                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2682                                     pf->offset_loaded,
2683                                     &os->priority_xoff_rx[i],
2684                                     &ns->priority_xoff_rx[i]);
2685         }
2686         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2687                             pf->offset_loaded, &os->link_xon_tx,
2688                             &ns->link_xon_tx);
2689         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2690                             pf->offset_loaded, &os->link_xoff_tx,
2691                             &ns->link_xoff_tx);
2692         for (i = 0; i < 8; i++) {
2693                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2694                                     pf->offset_loaded,
2695                                     &os->priority_xon_tx[i],
2696                                     &ns->priority_xon_tx[i]);
2697                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2698                                     pf->offset_loaded,
2699                                     &os->priority_xoff_tx[i],
2700                                     &ns->priority_xoff_tx[i]);
2701                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2702                                     pf->offset_loaded,
2703                                     &os->priority_xon_2_xoff[i],
2704                                     &ns->priority_xon_2_xoff[i]);
2705         }
2706         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2707                             I40E_GLPRT_PRC64L(hw->port),
2708                             pf->offset_loaded, &os->rx_size_64,
2709                             &ns->rx_size_64);
2710         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2711                             I40E_GLPRT_PRC127L(hw->port),
2712                             pf->offset_loaded, &os->rx_size_127,
2713                             &ns->rx_size_127);
2714         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2715                             I40E_GLPRT_PRC255L(hw->port),
2716                             pf->offset_loaded, &os->rx_size_255,
2717                             &ns->rx_size_255);
2718         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2719                             I40E_GLPRT_PRC511L(hw->port),
2720                             pf->offset_loaded, &os->rx_size_511,
2721                             &ns->rx_size_511);
2722         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2723                             I40E_GLPRT_PRC1023L(hw->port),
2724                             pf->offset_loaded, &os->rx_size_1023,
2725                             &ns->rx_size_1023);
2726         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2727                             I40E_GLPRT_PRC1522L(hw->port),
2728                             pf->offset_loaded, &os->rx_size_1522,
2729                             &ns->rx_size_1522);
2730         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2731                             I40E_GLPRT_PRC9522L(hw->port),
2732                             pf->offset_loaded, &os->rx_size_big,
2733                             &ns->rx_size_big);
2734         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2735                             pf->offset_loaded, &os->rx_undersize,
2736                             &ns->rx_undersize);
2737         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2738                             pf->offset_loaded, &os->rx_fragments,
2739                             &ns->rx_fragments);
2740         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2741                             pf->offset_loaded, &os->rx_oversize,
2742                             &ns->rx_oversize);
2743         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2744                             pf->offset_loaded, &os->rx_jabber,
2745                             &ns->rx_jabber);
2746         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2747                             I40E_GLPRT_PTC64L(hw->port),
2748                             pf->offset_loaded, &os->tx_size_64,
2749                             &ns->tx_size_64);
2750         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2751                             I40E_GLPRT_PTC127L(hw->port),
2752                             pf->offset_loaded, &os->tx_size_127,
2753                             &ns->tx_size_127);
2754         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2755                             I40E_GLPRT_PTC255L(hw->port),
2756                             pf->offset_loaded, &os->tx_size_255,
2757                             &ns->tx_size_255);
2758         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2759                             I40E_GLPRT_PTC511L(hw->port),
2760                             pf->offset_loaded, &os->tx_size_511,
2761                             &ns->tx_size_511);
2762         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2763                             I40E_GLPRT_PTC1023L(hw->port),
2764                             pf->offset_loaded, &os->tx_size_1023,
2765                             &ns->tx_size_1023);
2766         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2767                             I40E_GLPRT_PTC1522L(hw->port),
2768                             pf->offset_loaded, &os->tx_size_1522,
2769                             &ns->tx_size_1522);
2770         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2771                             I40E_GLPRT_PTC9522L(hw->port),
2772                             pf->offset_loaded, &os->tx_size_big,
2773                             &ns->tx_size_big);
2774         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2775                            pf->offset_loaded,
2776                            &os->fd_sb_match, &ns->fd_sb_match);
2777         /* GLPRT_MSPDC not supported */
2778         /* GLPRT_XEC not supported */
2779
2780         pf->offset_loaded = true;
2781
2782         if (pf->main_vsi)
2783                 i40e_update_vsi_stats(pf->main_vsi);
2784 }
2785
2786 /* Get all statistics of a port */
2787 static int
2788 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2789 {
2790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2791         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2793         unsigned i;
2794
2795         /* call read registers - updates values, now write them to struct */
2796         i40e_read_stats_registers(pf, hw);
2797
2798         stats->ipackets = ns->eth.rx_unicast +
2799                         ns->eth.rx_multicast +
2800                         ns->eth.rx_broadcast -
2801                         ns->eth.rx_discards -
2802                         pf->main_vsi->eth_stats.rx_discards;
2803         stats->opackets = ns->eth.tx_unicast +
2804                         ns->eth.tx_multicast +
2805                         ns->eth.tx_broadcast;
2806         stats->ibytes   = ns->eth.rx_bytes;
2807         stats->obytes   = ns->eth.tx_bytes;
2808         stats->oerrors  = ns->eth.tx_errors +
2809                         pf->main_vsi->eth_stats.tx_errors;
2810
2811         /* Rx Errors */
2812         stats->imissed  = ns->eth.rx_discards +
2813                         pf->main_vsi->eth_stats.rx_discards;
2814         stats->ierrors  = ns->crc_errors +
2815                         ns->rx_length_errors + ns->rx_undersize +
2816                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2817
2818         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2819         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2820         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2821         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2822         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2823         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2824         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2825                     ns->eth.rx_unknown_protocol);
2826         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2827         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2828         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2829         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2830         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2831         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2832
2833         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2834                     ns->tx_dropped_link_down);
2835         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2836         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2837                     ns->illegal_bytes);
2838         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2839         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2840                     ns->mac_local_faults);
2841         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2842                     ns->mac_remote_faults);
2843         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2844                     ns->rx_length_errors);
2845         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2846         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2847         for (i = 0; i < 8; i++) {
2848                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2849                                 i, ns->priority_xon_rx[i]);
2850                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2851                                 i, ns->priority_xoff_rx[i]);
2852         }
2853         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2854         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2855         for (i = 0; i < 8; i++) {
2856                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2857                                 i, ns->priority_xon_tx[i]);
2858                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2859                                 i, ns->priority_xoff_tx[i]);
2860                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2861                                 i, ns->priority_xon_2_xoff[i]);
2862         }
2863         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2864         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2865         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2866         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2867         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2868         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2869         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2870         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2871         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2872         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2873         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2874         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2875         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2876         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2877         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2878         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2879         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2880         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2881         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2882                         ns->mac_short_packet_dropped);
2883         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2884                     ns->checksum_error);
2885         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2886         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2887         return 0;
2888 }
2889
2890 /* Reset the statistics */
2891 static void
2892 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2893 {
2894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896
2897         /* Mark PF and VSI stats to update the offset, aka "reset" */
2898         pf->offset_loaded = false;
2899         if (pf->main_vsi)
2900                 pf->main_vsi->offset_loaded = false;
2901
2902         /* read the stats, reading current register values into offset */
2903         i40e_read_stats_registers(pf, hw);
2904 }
2905
2906 static uint32_t
2907 i40e_xstats_calc_num(void)
2908 {
2909         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2910                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2911                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2912 }
2913
2914 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2915                                      struct rte_eth_xstat_name *xstats_names,
2916                                      __rte_unused unsigned limit)
2917 {
2918         unsigned count = 0;
2919         unsigned i, prio;
2920
2921         if (xstats_names == NULL)
2922                 return i40e_xstats_calc_num();
2923
2924         /* Note: limit checked in rte_eth_xstats_names() */
2925
2926         /* Get stats from i40e_eth_stats struct */
2927         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2928                 snprintf(xstats_names[count].name,
2929                          sizeof(xstats_names[count].name),
2930                          "%s", rte_i40e_stats_strings[i].name);
2931                 count++;
2932         }
2933
2934         /* Get individiual stats from i40e_hw_port struct */
2935         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2936                 snprintf(xstats_names[count].name,
2937                         sizeof(xstats_names[count].name),
2938                          "%s", rte_i40e_hw_port_strings[i].name);
2939                 count++;
2940         }
2941
2942         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2943                 for (prio = 0; prio < 8; prio++) {
2944                         snprintf(xstats_names[count].name,
2945                                  sizeof(xstats_names[count].name),
2946                                  "rx_priority%u_%s", prio,
2947                                  rte_i40e_rxq_prio_strings[i].name);
2948                         count++;
2949                 }
2950         }
2951
2952         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2953                 for (prio = 0; prio < 8; prio++) {
2954                         snprintf(xstats_names[count].name,
2955                                  sizeof(xstats_names[count].name),
2956                                  "tx_priority%u_%s", prio,
2957                                  rte_i40e_txq_prio_strings[i].name);
2958                         count++;
2959                 }
2960         }
2961         return count;
2962 }
2963
2964 static int
2965 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2966                     unsigned n)
2967 {
2968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         unsigned i, count, prio;
2971         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2972
2973         count = i40e_xstats_calc_num();
2974         if (n < count)
2975                 return count;
2976
2977         i40e_read_stats_registers(pf, hw);
2978
2979         if (xstats == NULL)
2980                 return 0;
2981
2982         count = 0;
2983
2984         /* Get stats from i40e_eth_stats struct */
2985         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2986                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2987                         rte_i40e_stats_strings[i].offset);
2988                 xstats[count].id = count;
2989                 count++;
2990         }
2991
2992         /* Get individiual stats from i40e_hw_port struct */
2993         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2994                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2995                         rte_i40e_hw_port_strings[i].offset);
2996                 xstats[count].id = count;
2997                 count++;
2998         }
2999
3000         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3001                 for (prio = 0; prio < 8; prio++) {
3002                         xstats[count].value =
3003                                 *(uint64_t *)(((char *)hw_stats) +
3004                                 rte_i40e_rxq_prio_strings[i].offset +
3005                                 (sizeof(uint64_t) * prio));
3006                         xstats[count].id = count;
3007                         count++;
3008                 }
3009         }
3010
3011         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3012                 for (prio = 0; prio < 8; prio++) {
3013                         xstats[count].value =
3014                                 *(uint64_t *)(((char *)hw_stats) +
3015                                 rte_i40e_txq_prio_strings[i].offset +
3016                                 (sizeof(uint64_t) * prio));
3017                         xstats[count].id = count;
3018                         count++;
3019                 }
3020         }
3021
3022         return count;
3023 }
3024
3025 static int
3026 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3027                                  __rte_unused uint16_t queue_id,
3028                                  __rte_unused uint8_t stat_idx,
3029                                  __rte_unused uint8_t is_rx)
3030 {
3031         PMD_INIT_FUNC_TRACE();
3032
3033         return -ENOSYS;
3034 }
3035
3036 static int
3037 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3038 {
3039         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3040         u32 full_ver;
3041         u8 ver, patch;
3042         u16 build;
3043         int ret;
3044
3045         full_ver = hw->nvm.oem_ver;
3046         ver = (u8)(full_ver >> 24);
3047         build = (u16)((full_ver >> 8) & 0xffff);
3048         patch = (u8)(full_ver & 0xff);
3049
3050         ret = snprintf(fw_version, fw_size,
3051                  "%d.%d%d 0x%08x %d.%d.%d",
3052                  ((hw->nvm.version >> 12) & 0xf),
3053                  ((hw->nvm.version >> 4) & 0xff),
3054                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3055                  ver, build, patch);
3056
3057         ret += 1; /* add the size of '\0' */
3058         if (fw_size < (u32)ret)
3059                 return ret;
3060         else
3061                 return 0;
3062 }
3063
3064 static void
3065 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3066 {
3067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct i40e_vsi *vsi = pf->main_vsi;
3070         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3071
3072         dev_info->pci_dev = pci_dev;
3073         dev_info->max_rx_queues = vsi->nb_qps;
3074         dev_info->max_tx_queues = vsi->nb_qps;
3075         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3076         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3077         dev_info->max_mac_addrs = vsi->max_macaddrs;
3078         dev_info->max_vfs = pci_dev->max_vfs;
3079         dev_info->rx_offload_capa =
3080                 DEV_RX_OFFLOAD_VLAN_STRIP |
3081                 DEV_RX_OFFLOAD_QINQ_STRIP |
3082                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3083                 DEV_RX_OFFLOAD_UDP_CKSUM |
3084                 DEV_RX_OFFLOAD_TCP_CKSUM;
3085         dev_info->tx_offload_capa =
3086                 DEV_TX_OFFLOAD_VLAN_INSERT |
3087                 DEV_TX_OFFLOAD_QINQ_INSERT |
3088                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3089                 DEV_TX_OFFLOAD_UDP_CKSUM |
3090                 DEV_TX_OFFLOAD_TCP_CKSUM |
3091                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3092                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3093                 DEV_TX_OFFLOAD_TCP_TSO |
3094                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3095                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3096                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3097                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3098         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3099                                                 sizeof(uint32_t);
3100         dev_info->reta_size = pf->hash_lut_size;
3101         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3102
3103         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3104                 .rx_thresh = {
3105                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3106                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3107                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3108                 },
3109                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3110                 .rx_drop_en = 0,
3111         };
3112
3113         dev_info->default_txconf = (struct rte_eth_txconf) {
3114                 .tx_thresh = {
3115                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3116                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3117                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3118                 },
3119                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3120                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3121                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3122                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3123         };
3124
3125         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3126                 .nb_max = I40E_MAX_RING_DESC,
3127                 .nb_min = I40E_MIN_RING_DESC,
3128                 .nb_align = I40E_ALIGN_RING_DESC,
3129         };
3130
3131         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3132                 .nb_max = I40E_MAX_RING_DESC,
3133                 .nb_min = I40E_MIN_RING_DESC,
3134                 .nb_align = I40E_ALIGN_RING_DESC,
3135                 .nb_seg_max = I40E_TX_MAX_SEG,
3136                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3137         };
3138
3139         if (pf->flags & I40E_FLAG_VMDQ) {
3140                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3141                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3142                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3143                                                 pf->max_nb_vmdq_vsi;
3144                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3145                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3146                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3147         }
3148
3149         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3150                 /* For XL710 */
3151                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3152         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3153                 /* For XXV710 */
3154                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3155         else
3156                 /* For X710 */
3157                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3158 }
3159
3160 static int
3161 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3162 {
3163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3164         struct i40e_vsi *vsi = pf->main_vsi;
3165         PMD_INIT_FUNC_TRACE();
3166
3167         if (on)
3168                 return i40e_vsi_add_vlan(vsi, vlan_id);
3169         else
3170                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3171 }
3172
3173 static int
3174 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3175                                 enum rte_vlan_type vlan_type,
3176                                 uint16_t tpid, int qinq)
3177 {
3178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3179         uint64_t reg_r = 0;
3180         uint64_t reg_w = 0;
3181         uint16_t reg_id = 3;
3182         int ret;
3183
3184         if (qinq) {
3185                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3186                         reg_id = 2;
3187         }
3188
3189         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3190                                           &reg_r, NULL);
3191         if (ret != I40E_SUCCESS) {
3192                 PMD_DRV_LOG(ERR,
3193                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3194                            reg_id);
3195                 return -EIO;
3196         }
3197         PMD_DRV_LOG(DEBUG,
3198                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3199                     reg_id, reg_r);
3200
3201         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3202         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3203         if (reg_r == reg_w) {
3204                 PMD_DRV_LOG(DEBUG, "No need to write");
3205                 return 0;
3206         }
3207
3208         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3209                                            reg_w, NULL);
3210         if (ret != I40E_SUCCESS) {
3211                 PMD_DRV_LOG(ERR,
3212                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3213                             reg_id);
3214                 return -EIO;
3215         }
3216         PMD_DRV_LOG(DEBUG,
3217                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3218                     reg_w, reg_id);
3219
3220         return 0;
3221 }
3222
3223 static int
3224 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3225                    enum rte_vlan_type vlan_type,
3226                    uint16_t tpid)
3227 {
3228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3230         int ret = 0;
3231
3232         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3233              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3234             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3235                 PMD_DRV_LOG(ERR,
3236                             "Unsupported vlan type.");
3237                 return -EINVAL;
3238         }
3239         /* 802.1ad frames ability is added in NVM API 1.7*/
3240         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3241                 if (qinq) {
3242                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3243                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3244                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3245                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3246                 } else {
3247                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3248                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3249                 }
3250                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3251                 if (ret != I40E_SUCCESS) {
3252                         PMD_DRV_LOG(ERR,
3253                                     "Set switch config failed aq_err: %d",
3254                                     hw->aq.asq_last_status);
3255                         ret = -EIO;
3256                 }
3257         } else
3258                 /* If NVM API < 1.7, keep the register setting */
3259                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3260                                                       tpid, qinq);
3261
3262         return ret;
3263 }
3264
3265 static int
3266 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3267 {
3268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3269         struct i40e_vsi *vsi = pf->main_vsi;
3270
3271         if (mask & ETH_VLAN_FILTER_MASK) {
3272                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3273                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3274                 else
3275                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3276         }
3277
3278         if (mask & ETH_VLAN_STRIP_MASK) {
3279                 /* Enable or disable VLAN stripping */
3280                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3281                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3282                 else
3283                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3284         }
3285
3286         if (mask & ETH_VLAN_EXTEND_MASK) {
3287                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3288                         i40e_vsi_config_double_vlan(vsi, TRUE);
3289                         /* Set global registers with default ethertype. */
3290                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3291                                            ETHER_TYPE_VLAN);
3292                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3293                                            ETHER_TYPE_VLAN);
3294                 }
3295                 else
3296                         i40e_vsi_config_double_vlan(vsi, FALSE);
3297         }
3298
3299         return 0;
3300 }
3301
3302 static void
3303 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3304                           __rte_unused uint16_t queue,
3305                           __rte_unused int on)
3306 {
3307         PMD_INIT_FUNC_TRACE();
3308 }
3309
3310 static int
3311 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3312 {
3313         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3314         struct i40e_vsi *vsi = pf->main_vsi;
3315         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3316         struct i40e_vsi_vlan_pvid_info info;
3317
3318         memset(&info, 0, sizeof(info));
3319         info.on = on;
3320         if (info.on)
3321                 info.config.pvid = pvid;
3322         else {
3323                 info.config.reject.tagged =
3324                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3325                 info.config.reject.untagged =
3326                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3327         }
3328
3329         return i40e_vsi_vlan_pvid_set(vsi, &info);
3330 }
3331
3332 static int
3333 i40e_dev_led_on(struct rte_eth_dev *dev)
3334 {
3335         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3336         uint32_t mode = i40e_led_get(hw);
3337
3338         if (mode == 0)
3339                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3340
3341         return 0;
3342 }
3343
3344 static int
3345 i40e_dev_led_off(struct rte_eth_dev *dev)
3346 {
3347         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3348         uint32_t mode = i40e_led_get(hw);
3349
3350         if (mode != 0)
3351                 i40e_led_set(hw, 0, false);
3352
3353         return 0;
3354 }
3355
3356 static int
3357 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3358 {
3359         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361
3362         fc_conf->pause_time = pf->fc_conf.pause_time;
3363
3364         /* read out from register, in case they are modified by other port */
3365         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3366                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3367         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3368                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3369
3370         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3371         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3372
3373          /* Return current mode according to actual setting*/
3374         switch (hw->fc.current_mode) {
3375         case I40E_FC_FULL:
3376                 fc_conf->mode = RTE_FC_FULL;
3377                 break;
3378         case I40E_FC_TX_PAUSE:
3379                 fc_conf->mode = RTE_FC_TX_PAUSE;
3380                 break;
3381         case I40E_FC_RX_PAUSE:
3382                 fc_conf->mode = RTE_FC_RX_PAUSE;
3383                 break;
3384         case I40E_FC_NONE:
3385         default:
3386                 fc_conf->mode = RTE_FC_NONE;
3387         };
3388
3389         return 0;
3390 }
3391
3392 static int
3393 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3394 {
3395         uint32_t mflcn_reg, fctrl_reg, reg;
3396         uint32_t max_high_water;
3397         uint8_t i, aq_failure;
3398         int err;
3399         struct i40e_hw *hw;
3400         struct i40e_pf *pf;
3401         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3402                 [RTE_FC_NONE] = I40E_FC_NONE,
3403                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3404                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3405                 [RTE_FC_FULL] = I40E_FC_FULL
3406         };
3407
3408         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3409
3410         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3411         if ((fc_conf->high_water > max_high_water) ||
3412                         (fc_conf->high_water < fc_conf->low_water)) {
3413                 PMD_INIT_LOG(ERR,
3414                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3415                         max_high_water);
3416                 return -EINVAL;
3417         }
3418
3419         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3420         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3421         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3422
3423         pf->fc_conf.pause_time = fc_conf->pause_time;
3424         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3425         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3426
3427         PMD_INIT_FUNC_TRACE();
3428
3429         /* All the link flow control related enable/disable register
3430          * configuration is handle by the F/W
3431          */
3432         err = i40e_set_fc(hw, &aq_failure, true);
3433         if (err < 0)
3434                 return -ENOSYS;
3435
3436         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3437                 /* Configure flow control refresh threshold,
3438                  * the value for stat_tx_pause_refresh_timer[8]
3439                  * is used for global pause operation.
3440                  */
3441
3442                 I40E_WRITE_REG(hw,
3443                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3444                                pf->fc_conf.pause_time);
3445
3446                 /* configure the timer value included in transmitted pause
3447                  * frame,
3448                  * the value for stat_tx_pause_quanta[8] is used for global
3449                  * pause operation
3450                  */
3451                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3452                                pf->fc_conf.pause_time);
3453
3454                 fctrl_reg = I40E_READ_REG(hw,
3455                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3456
3457                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3458                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3459                 else
3460                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3461
3462                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3463                                fctrl_reg);
3464         } else {
3465                 /* Configure pause time (2 TCs per register) */
3466                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3467                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3468                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3469
3470                 /* Configure flow control refresh threshold value */
3471                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3472                                pf->fc_conf.pause_time / 2);
3473
3474                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3475
3476                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3477                  *depending on configuration
3478                  */
3479                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3480                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3481                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3482                 } else {
3483                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3484                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3485                 }
3486
3487                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3488         }
3489
3490         /* config the water marker both based on the packets and bytes */
3491         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3492                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3493                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3494         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3495                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3496                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3497         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3498                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3499                        << I40E_KILOSHIFT);
3500         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3501                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3502                        << I40E_KILOSHIFT);
3503
3504         I40E_WRITE_FLUSH(hw);
3505
3506         return 0;
3507 }
3508
3509 static int
3510 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3511                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3512 {
3513         PMD_INIT_FUNC_TRACE();
3514
3515         return -ENOSYS;
3516 }
3517
3518 /* Add a MAC address, and update filters */
3519 static int
3520 i40e_macaddr_add(struct rte_eth_dev *dev,
3521                  struct ether_addr *mac_addr,
3522                  __rte_unused uint32_t index,
3523                  uint32_t pool)
3524 {
3525         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3526         struct i40e_mac_filter_info mac_filter;
3527         struct i40e_vsi *vsi;
3528         int ret;
3529
3530         /* If VMDQ not enabled or configured, return */
3531         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3532                           !pf->nb_cfg_vmdq_vsi)) {
3533                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3534                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3535                         pool);
3536                 return -ENOTSUP;
3537         }
3538
3539         if (pool > pf->nb_cfg_vmdq_vsi) {
3540                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3541                                 pool, pf->nb_cfg_vmdq_vsi);
3542                 return -EINVAL;
3543         }
3544
3545         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3546         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3547                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3548         else
3549                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3550
3551         if (pool == 0)
3552                 vsi = pf->main_vsi;
3553         else
3554                 vsi = pf->vmdq[pool - 1].vsi;
3555
3556         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3557         if (ret != I40E_SUCCESS) {
3558                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3559                 return -ENODEV;
3560         }
3561         return 0;
3562 }
3563
3564 /* Remove a MAC address, and update filters */
3565 static void
3566 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3567 {
3568         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3569         struct i40e_vsi *vsi;
3570         struct rte_eth_dev_data *data = dev->data;
3571         struct ether_addr *macaddr;
3572         int ret;
3573         uint32_t i;
3574         uint64_t pool_sel;
3575
3576         macaddr = &(data->mac_addrs[index]);
3577
3578         pool_sel = dev->data->mac_pool_sel[index];
3579
3580         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3581                 if (pool_sel & (1ULL << i)) {
3582                         if (i == 0)
3583                                 vsi = pf->main_vsi;
3584                         else {
3585                                 /* No VMDQ pool enabled or configured */
3586                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3587                                         (i > pf->nb_cfg_vmdq_vsi)) {
3588                                         PMD_DRV_LOG(ERR,
3589                                                 "No VMDQ pool enabled/configured");
3590                                         return;
3591                                 }
3592                                 vsi = pf->vmdq[i - 1].vsi;
3593                         }
3594                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3595
3596                         if (ret) {
3597                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3598                                 return;
3599                         }
3600                 }
3601         }
3602 }
3603
3604 /* Set perfect match or hash match of MAC and VLAN for a VF */
3605 static int
3606 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3607                  struct rte_eth_mac_filter *filter,
3608                  bool add)
3609 {
3610         struct i40e_hw *hw;
3611         struct i40e_mac_filter_info mac_filter;
3612         struct ether_addr old_mac;
3613         struct ether_addr *new_mac;
3614         struct i40e_pf_vf *vf = NULL;
3615         uint16_t vf_id;
3616         int ret;
3617
3618         if (pf == NULL) {
3619                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3620                 return -EINVAL;
3621         }
3622         hw = I40E_PF_TO_HW(pf);
3623
3624         if (filter == NULL) {
3625                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3626                 return -EINVAL;
3627         }
3628
3629         new_mac = &filter->mac_addr;
3630
3631         if (is_zero_ether_addr(new_mac)) {
3632                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3633                 return -EINVAL;
3634         }
3635
3636         vf_id = filter->dst_id;
3637
3638         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3639                 PMD_DRV_LOG(ERR, "Invalid argument.");
3640                 return -EINVAL;
3641         }
3642         vf = &pf->vfs[vf_id];
3643
3644         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3645                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3646                 return -EINVAL;
3647         }
3648
3649         if (add) {
3650                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3651                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3652                                 ETHER_ADDR_LEN);
3653                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3654                                  ETHER_ADDR_LEN);
3655
3656                 mac_filter.filter_type = filter->filter_type;
3657                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3658                 if (ret != I40E_SUCCESS) {
3659                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3660                         return -1;
3661                 }
3662                 ether_addr_copy(new_mac, &pf->dev_addr);
3663         } else {
3664                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3665                                 ETHER_ADDR_LEN);
3666                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3667                 if (ret != I40E_SUCCESS) {
3668                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3669                         return -1;
3670                 }
3671
3672                 /* Clear device address as it has been removed */
3673                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3674                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3675         }
3676
3677         return 0;
3678 }
3679
3680 /* MAC filter handle */
3681 static int
3682 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3683                 void *arg)
3684 {
3685         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3686         struct rte_eth_mac_filter *filter;
3687         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3688         int ret = I40E_NOT_SUPPORTED;
3689
3690         filter = (struct rte_eth_mac_filter *)(arg);
3691
3692         switch (filter_op) {
3693         case RTE_ETH_FILTER_NOP:
3694                 ret = I40E_SUCCESS;
3695                 break;
3696         case RTE_ETH_FILTER_ADD:
3697                 i40e_pf_disable_irq0(hw);
3698                 if (filter->is_vf)
3699                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3700                 i40e_pf_enable_irq0(hw);
3701                 break;
3702         case RTE_ETH_FILTER_DELETE:
3703                 i40e_pf_disable_irq0(hw);
3704                 if (filter->is_vf)
3705                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3706                 i40e_pf_enable_irq0(hw);
3707                 break;
3708         default:
3709                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3710                 ret = I40E_ERR_PARAM;
3711                 break;
3712         }
3713
3714         return ret;
3715 }
3716
3717 static int
3718 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3719 {
3720         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3721         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3722         uint32_t reg;
3723         int ret;
3724
3725         if (!lut)
3726                 return -EINVAL;
3727
3728         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3729                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3730                                           lut, lut_size);
3731                 if (ret) {
3732                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3733                         return ret;
3734                 }
3735         } else {
3736                 uint32_t *lut_dw = (uint32_t *)lut;
3737                 uint16_t i, lut_size_dw = lut_size / 4;
3738
3739                 if (vsi->type == I40E_VSI_SRIOV) {
3740                         for (i = 0; i <= lut_size_dw; i++) {
3741                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3742                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3743                         }
3744                 } else {
3745                         for (i = 0; i < lut_size_dw; i++)
3746                                 lut_dw[i] = I40E_READ_REG(hw,
3747                                                           I40E_PFQF_HLUT(i));
3748                 }
3749         }
3750
3751         return 0;
3752 }
3753
3754 int
3755 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3756 {
3757         struct i40e_pf *pf;
3758         struct i40e_hw *hw;
3759         int ret;
3760
3761         if (!vsi || !lut)
3762                 return -EINVAL;
3763
3764         pf = I40E_VSI_TO_PF(vsi);
3765         hw = I40E_VSI_TO_HW(vsi);
3766
3767         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3768                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3769                                           lut, lut_size);
3770                 if (ret) {
3771                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3772                         return ret;
3773                 }
3774         } else {
3775                 uint32_t *lut_dw = (uint32_t *)lut;
3776                 uint16_t i, lut_size_dw = lut_size / 4;
3777
3778                 if (vsi->type == I40E_VSI_SRIOV) {
3779                         for (i = 0; i < lut_size_dw; i++)
3780                                 I40E_WRITE_REG(
3781                                         hw,
3782                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3783                                         lut_dw[i]);
3784                 } else {
3785                         for (i = 0; i < lut_size_dw; i++)
3786                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3787                                                lut_dw[i]);
3788                 }
3789                 I40E_WRITE_FLUSH(hw);
3790         }
3791
3792         return 0;
3793 }
3794
3795 static int
3796 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3797                          struct rte_eth_rss_reta_entry64 *reta_conf,
3798                          uint16_t reta_size)
3799 {
3800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3801         uint16_t i, lut_size = pf->hash_lut_size;
3802         uint16_t idx, shift;
3803         uint8_t *lut;
3804         int ret;
3805
3806         if (reta_size != lut_size ||
3807                 reta_size > ETH_RSS_RETA_SIZE_512) {
3808                 PMD_DRV_LOG(ERR,
3809                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3810                         reta_size, lut_size);
3811                 return -EINVAL;
3812         }
3813
3814         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3815         if (!lut) {
3816                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3817                 return -ENOMEM;
3818         }
3819         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3820         if (ret)
3821                 goto out;
3822         for (i = 0; i < reta_size; i++) {
3823                 idx = i / RTE_RETA_GROUP_SIZE;
3824                 shift = i % RTE_RETA_GROUP_SIZE;
3825                 if (reta_conf[idx].mask & (1ULL << shift))
3826                         lut[i] = reta_conf[idx].reta[shift];
3827         }
3828         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3829
3830 out:
3831         rte_free(lut);
3832
3833         return ret;
3834 }
3835
3836 static int
3837 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3838                         struct rte_eth_rss_reta_entry64 *reta_conf,
3839                         uint16_t reta_size)
3840 {
3841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3842         uint16_t i, lut_size = pf->hash_lut_size;
3843         uint16_t idx, shift;
3844         uint8_t *lut;
3845         int ret;
3846
3847         if (reta_size != lut_size ||
3848                 reta_size > ETH_RSS_RETA_SIZE_512) {
3849                 PMD_DRV_LOG(ERR,
3850                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3851                         reta_size, lut_size);
3852                 return -EINVAL;
3853         }
3854
3855         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3856         if (!lut) {
3857                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3858                 return -ENOMEM;
3859         }
3860
3861         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3862         if (ret)
3863                 goto out;
3864         for (i = 0; i < reta_size; i++) {
3865                 idx = i / RTE_RETA_GROUP_SIZE;
3866                 shift = i % RTE_RETA_GROUP_SIZE;
3867                 if (reta_conf[idx].mask & (1ULL << shift))
3868                         reta_conf[idx].reta[shift] = lut[i];
3869         }
3870
3871 out:
3872         rte_free(lut);
3873
3874         return ret;
3875 }
3876
3877 /**
3878  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3879  * @hw:   pointer to the HW structure
3880  * @mem:  pointer to mem struct to fill out
3881  * @size: size of memory requested
3882  * @alignment: what to align the allocation to
3883  **/
3884 enum i40e_status_code
3885 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3886                         struct i40e_dma_mem *mem,
3887                         u64 size,
3888                         u32 alignment)
3889 {
3890         const struct rte_memzone *mz = NULL;
3891         char z_name[RTE_MEMZONE_NAMESIZE];
3892
3893         if (!mem)
3894                 return I40E_ERR_PARAM;
3895
3896         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3897         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3898                                          alignment, RTE_PGSIZE_2M);
3899         if (!mz)
3900                 return I40E_ERR_NO_MEMORY;
3901
3902         mem->size = size;
3903         mem->va = mz->addr;
3904         mem->pa = mz->iova;
3905         mem->zone = (const void *)mz;
3906         PMD_DRV_LOG(DEBUG,
3907                 "memzone %s allocated with physical address: %"PRIu64,
3908                 mz->name, mem->pa);
3909
3910         return I40E_SUCCESS;
3911 }
3912
3913 /**
3914  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3915  * @hw:   pointer to the HW structure
3916  * @mem:  ptr to mem struct to free
3917  **/
3918 enum i40e_status_code
3919 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3920                     struct i40e_dma_mem *mem)
3921 {
3922         if (!mem)
3923                 return I40E_ERR_PARAM;
3924
3925         PMD_DRV_LOG(DEBUG,
3926                 "memzone %s to be freed with physical address: %"PRIu64,
3927                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3928         rte_memzone_free((const struct rte_memzone *)mem->zone);
3929         mem->zone = NULL;
3930         mem->va = NULL;
3931         mem->pa = (u64)0;
3932
3933         return I40E_SUCCESS;
3934 }
3935
3936 /**
3937  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3938  * @hw:   pointer to the HW structure
3939  * @mem:  pointer to mem struct to fill out
3940  * @size: size of memory requested
3941  **/
3942 enum i40e_status_code
3943 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3944                          struct i40e_virt_mem *mem,
3945                          u32 size)
3946 {
3947         if (!mem)
3948                 return I40E_ERR_PARAM;
3949
3950         mem->size = size;
3951         mem->va = rte_zmalloc("i40e", size, 0);
3952
3953         if (mem->va)
3954                 return I40E_SUCCESS;
3955         else
3956                 return I40E_ERR_NO_MEMORY;
3957 }
3958
3959 /**
3960  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3961  * @hw:   pointer to the HW structure
3962  * @mem:  pointer to mem struct to free
3963  **/
3964 enum i40e_status_code
3965 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3966                      struct i40e_virt_mem *mem)
3967 {
3968         if (!mem)
3969                 return I40E_ERR_PARAM;
3970
3971         rte_free(mem->va);
3972         mem->va = NULL;
3973
3974         return I40E_SUCCESS;
3975 }
3976
3977 void
3978 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3979 {
3980         rte_spinlock_init(&sp->spinlock);
3981 }
3982
3983 void
3984 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3985 {
3986         rte_spinlock_lock(&sp->spinlock);
3987 }
3988
3989 void
3990 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3991 {
3992         rte_spinlock_unlock(&sp->spinlock);
3993 }
3994
3995 void
3996 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3997 {
3998         return;
3999 }
4000
4001 /**
4002  * Get the hardware capabilities, which will be parsed
4003  * and saved into struct i40e_hw.
4004  */
4005 static int
4006 i40e_get_cap(struct i40e_hw *hw)
4007 {
4008         struct i40e_aqc_list_capabilities_element_resp *buf;
4009         uint16_t len, size = 0;
4010         int ret;
4011
4012         /* Calculate a huge enough buff for saving response data temporarily */
4013         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4014                                                 I40E_MAX_CAP_ELE_NUM;
4015         buf = rte_zmalloc("i40e", len, 0);
4016         if (!buf) {
4017                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4018                 return I40E_ERR_NO_MEMORY;
4019         }
4020
4021         /* Get, parse the capabilities and save it to hw */
4022         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4023                         i40e_aqc_opc_list_func_capabilities, NULL);
4024         if (ret != I40E_SUCCESS)
4025                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4026
4027         /* Free the temporary buffer after being used */
4028         rte_free(buf);
4029
4030         return ret;
4031 }
4032
4033 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4034 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4035 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4036
4037 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4038                 const char *value,
4039                 void *opaque)
4040 {
4041         struct i40e_pf *pf;
4042         unsigned long num;
4043         char *end;
4044
4045         pf = (struct i40e_pf *)opaque;
4046         RTE_SET_USED(key);
4047
4048         errno = 0;
4049         num = strtoul(value, &end, 0);
4050         if (errno != 0 || end == value || *end != 0) {
4051                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4052                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4053                 return -(EINVAL);
4054         }
4055
4056         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4057                 pf->vf_nb_qp_max = (uint16_t)num;
4058         else
4059                 /* here return 0 to make next valid same argument work */
4060                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4061                             "power of 2 and equal or less than 16 !, Now it is "
4062                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4063
4064         return 0;
4065 }
4066
4067 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4068 {
4069         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4071         struct rte_kvargs *kvlist;
4072
4073         /* set default queue number per VF as 4 */
4074         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4075
4076         if (dev->device->devargs == NULL)
4077                 return 0;
4078
4079         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4080         if (kvlist == NULL)
4081                 return -(EINVAL);
4082
4083         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4084                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4085                             "the first invalid or last valid one is used !",
4086                             QUEUE_NUM_PER_VF_ARG);
4087
4088         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4089                            i40e_pf_parse_vf_queue_number_handler, pf);
4090
4091         rte_kvargs_free(kvlist);
4092
4093         return 0;
4094 }
4095
4096 static int
4097 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4098 {
4099         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4100         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4102         uint16_t qp_count = 0, vsi_count = 0;
4103
4104         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4105                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4106                 return -EINVAL;
4107         }
4108
4109         i40e_pf_config_vf_rxq_number(dev);
4110
4111         /* Add the parameter init for LFC */
4112         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4113         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4114         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4115
4116         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4117         pf->max_num_vsi = hw->func_caps.num_vsis;
4118         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4119         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4120
4121         /* FDir queue/VSI allocation */
4122         pf->fdir_qp_offset = 0;
4123         if (hw->func_caps.fd) {
4124                 pf->flags |= I40E_FLAG_FDIR;
4125                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4126         } else {
4127                 pf->fdir_nb_qps = 0;
4128         }
4129         qp_count += pf->fdir_nb_qps;
4130         vsi_count += 1;
4131
4132         /* LAN queue/VSI allocation */
4133         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4134         if (!hw->func_caps.rss) {
4135                 pf->lan_nb_qps = 1;
4136         } else {
4137                 pf->flags |= I40E_FLAG_RSS;
4138                 if (hw->mac.type == I40E_MAC_X722)
4139                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4140                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4141         }
4142         qp_count += pf->lan_nb_qps;
4143         vsi_count += 1;
4144
4145         /* VF queue/VSI allocation */
4146         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4147         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4148                 pf->flags |= I40E_FLAG_SRIOV;
4149                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4150                 pf->vf_num = pci_dev->max_vfs;
4151                 PMD_DRV_LOG(DEBUG,
4152                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4153                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4154         } else {
4155                 pf->vf_nb_qps = 0;
4156                 pf->vf_num = 0;
4157         }
4158         qp_count += pf->vf_nb_qps * pf->vf_num;
4159         vsi_count += pf->vf_num;
4160
4161         /* VMDq queue/VSI allocation */
4162         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4163         pf->vmdq_nb_qps = 0;
4164         pf->max_nb_vmdq_vsi = 0;
4165         if (hw->func_caps.vmdq) {
4166                 if (qp_count < hw->func_caps.num_tx_qp &&
4167                         vsi_count < hw->func_caps.num_vsis) {
4168                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4169                                 qp_count) / pf->vmdq_nb_qp_max;
4170
4171                         /* Limit the maximum number of VMDq vsi to the maximum
4172                          * ethdev can support
4173                          */
4174                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4175                                 hw->func_caps.num_vsis - vsi_count);
4176                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4177                                 ETH_64_POOLS);
4178                         if (pf->max_nb_vmdq_vsi) {
4179                                 pf->flags |= I40E_FLAG_VMDQ;
4180                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4181                                 PMD_DRV_LOG(DEBUG,
4182                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4183                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4184                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4185                         } else {
4186                                 PMD_DRV_LOG(INFO,
4187                                         "No enough queues left for VMDq");
4188                         }
4189                 } else {
4190                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4191                 }
4192         }
4193         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4194         vsi_count += pf->max_nb_vmdq_vsi;
4195
4196         if (hw->func_caps.dcb)
4197                 pf->flags |= I40E_FLAG_DCB;
4198
4199         if (qp_count > hw->func_caps.num_tx_qp) {
4200                 PMD_DRV_LOG(ERR,
4201                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4202                         qp_count, hw->func_caps.num_tx_qp);
4203                 return -EINVAL;
4204         }
4205         if (vsi_count > hw->func_caps.num_vsis) {
4206                 PMD_DRV_LOG(ERR,
4207                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4208                         vsi_count, hw->func_caps.num_vsis);
4209                 return -EINVAL;
4210         }
4211
4212         return 0;
4213 }
4214
4215 static int
4216 i40e_pf_get_switch_config(struct i40e_pf *pf)
4217 {
4218         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4219         struct i40e_aqc_get_switch_config_resp *switch_config;
4220         struct i40e_aqc_switch_config_element_resp *element;
4221         uint16_t start_seid = 0, num_reported;
4222         int ret;
4223
4224         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4225                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4226         if (!switch_config) {
4227                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4228                 return -ENOMEM;
4229         }
4230
4231         /* Get the switch configurations */
4232         ret = i40e_aq_get_switch_config(hw, switch_config,
4233                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4234         if (ret != I40E_SUCCESS) {
4235                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4236                 goto fail;
4237         }
4238         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4239         if (num_reported != 1) { /* The number should be 1 */
4240                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4241                 goto fail;
4242         }
4243
4244         /* Parse the switch configuration elements */
4245         element = &(switch_config->element[0]);
4246         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4247                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4248                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4249         } else
4250                 PMD_DRV_LOG(INFO, "Unknown element type");
4251
4252 fail:
4253         rte_free(switch_config);
4254
4255         return ret;
4256 }
4257
4258 static int
4259 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4260                         uint32_t num)
4261 {
4262         struct pool_entry *entry;
4263
4264         if (pool == NULL || num == 0)
4265                 return -EINVAL;
4266
4267         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4268         if (entry == NULL) {
4269                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4270                 return -ENOMEM;
4271         }
4272
4273         /* queue heap initialize */
4274         pool->num_free = num;
4275         pool->num_alloc = 0;
4276         pool->base = base;
4277         LIST_INIT(&pool->alloc_list);
4278         LIST_INIT(&pool->free_list);
4279
4280         /* Initialize element  */
4281         entry->base = 0;
4282         entry->len = num;
4283
4284         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4285         return 0;
4286 }
4287
4288 static void
4289 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4290 {
4291         struct pool_entry *entry, *next_entry;
4292
4293         if (pool == NULL)
4294                 return;
4295
4296         for (entry = LIST_FIRST(&pool->alloc_list);
4297                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4298                         entry = next_entry) {
4299                 LIST_REMOVE(entry, next);
4300                 rte_free(entry);
4301         }
4302
4303         for (entry = LIST_FIRST(&pool->free_list);
4304                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4305                         entry = next_entry) {
4306                 LIST_REMOVE(entry, next);
4307                 rte_free(entry);
4308         }
4309
4310         pool->num_free = 0;
4311         pool->num_alloc = 0;
4312         pool->base = 0;
4313         LIST_INIT(&pool->alloc_list);
4314         LIST_INIT(&pool->free_list);
4315 }
4316
4317 static int
4318 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4319                        uint32_t base)
4320 {
4321         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4322         uint32_t pool_offset;
4323         int insert;
4324
4325         if (pool == NULL) {
4326                 PMD_DRV_LOG(ERR, "Invalid parameter");
4327                 return -EINVAL;
4328         }
4329
4330         pool_offset = base - pool->base;
4331         /* Lookup in alloc list */
4332         LIST_FOREACH(entry, &pool->alloc_list, next) {
4333                 if (entry->base == pool_offset) {
4334                         valid_entry = entry;
4335                         LIST_REMOVE(entry, next);
4336                         break;
4337                 }
4338         }
4339
4340         /* Not find, return */
4341         if (valid_entry == NULL) {
4342                 PMD_DRV_LOG(ERR, "Failed to find entry");
4343                 return -EINVAL;
4344         }
4345
4346         /**
4347          * Found it, move it to free list  and try to merge.
4348          * In order to make merge easier, always sort it by qbase.
4349          * Find adjacent prev and last entries.
4350          */
4351         prev = next = NULL;
4352         LIST_FOREACH(entry, &pool->free_list, next) {
4353                 if (entry->base > valid_entry->base) {
4354                         next = entry;
4355                         break;
4356                 }
4357                 prev = entry;
4358         }
4359
4360         insert = 0;
4361         /* Try to merge with next one*/
4362         if (next != NULL) {
4363                 /* Merge with next one */
4364                 if (valid_entry->base + valid_entry->len == next->base) {
4365                         next->base = valid_entry->base;
4366                         next->len += valid_entry->len;
4367                         rte_free(valid_entry);
4368                         valid_entry = next;
4369                         insert = 1;
4370                 }
4371         }
4372
4373         if (prev != NULL) {
4374                 /* Merge with previous one */
4375                 if (prev->base + prev->len == valid_entry->base) {
4376                         prev->len += valid_entry->len;
4377                         /* If it merge with next one, remove next node */
4378                         if (insert == 1) {
4379                                 LIST_REMOVE(valid_entry, next);
4380                                 rte_free(valid_entry);
4381                         } else {
4382                                 rte_free(valid_entry);
4383                                 insert = 1;
4384                         }
4385                 }
4386         }
4387
4388         /* Not find any entry to merge, insert */
4389         if (insert == 0) {
4390                 if (prev != NULL)
4391                         LIST_INSERT_AFTER(prev, valid_entry, next);
4392                 else if (next != NULL)
4393                         LIST_INSERT_BEFORE(next, valid_entry, next);
4394                 else /* It's empty list, insert to head */
4395                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4396         }
4397
4398         pool->num_free += valid_entry->len;
4399         pool->num_alloc -= valid_entry->len;
4400
4401         return 0;
4402 }
4403
4404 static int
4405 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4406                        uint16_t num)
4407 {
4408         struct pool_entry *entry, *valid_entry;
4409
4410         if (pool == NULL || num == 0) {
4411                 PMD_DRV_LOG(ERR, "Invalid parameter");
4412                 return -EINVAL;
4413         }
4414
4415         if (pool->num_free < num) {
4416                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4417                             num, pool->num_free);
4418                 return -ENOMEM;
4419         }
4420
4421         valid_entry = NULL;
4422         /* Lookup  in free list and find most fit one */
4423         LIST_FOREACH(entry, &pool->free_list, next) {
4424                 if (entry->len >= num) {
4425                         /* Find best one */
4426                         if (entry->len == num) {
4427                                 valid_entry = entry;
4428                                 break;
4429                         }
4430                         if (valid_entry == NULL || valid_entry->len > entry->len)
4431                                 valid_entry = entry;
4432                 }
4433         }
4434
4435         /* Not find one to satisfy the request, return */
4436         if (valid_entry == NULL) {
4437                 PMD_DRV_LOG(ERR, "No valid entry found");
4438                 return -ENOMEM;
4439         }
4440         /**
4441          * The entry have equal queue number as requested,
4442          * remove it from alloc_list.
4443          */
4444         if (valid_entry->len == num) {
4445                 LIST_REMOVE(valid_entry, next);
4446         } else {
4447                 /**
4448                  * The entry have more numbers than requested,
4449                  * create a new entry for alloc_list and minus its
4450                  * queue base and number in free_list.
4451                  */
4452                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4453                 if (entry == NULL) {
4454                         PMD_DRV_LOG(ERR,
4455                                 "Failed to allocate memory for resource pool");
4456                         return -ENOMEM;
4457                 }
4458                 entry->base = valid_entry->base;
4459                 entry->len = num;
4460                 valid_entry->base += num;
4461                 valid_entry->len -= num;
4462                 valid_entry = entry;
4463         }
4464
4465         /* Insert it into alloc list, not sorted */
4466         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4467
4468         pool->num_free -= valid_entry->len;
4469         pool->num_alloc += valid_entry->len;
4470
4471         return valid_entry->base + pool->base;
4472 }
4473
4474 /**
4475  * bitmap_is_subset - Check whether src2 is subset of src1
4476  **/
4477 static inline int
4478 bitmap_is_subset(uint8_t src1, uint8_t src2)
4479 {
4480         return !((src1 ^ src2) & src2);
4481 }
4482
4483 static enum i40e_status_code
4484 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4485 {
4486         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4487
4488         /* If DCB is not supported, only default TC is supported */
4489         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4490                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4491                 return I40E_NOT_SUPPORTED;
4492         }
4493
4494         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4495                 PMD_DRV_LOG(ERR,
4496                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4497                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4498                 return I40E_NOT_SUPPORTED;
4499         }
4500         return I40E_SUCCESS;
4501 }
4502
4503 int
4504 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4505                                 struct i40e_vsi_vlan_pvid_info *info)
4506 {
4507         struct i40e_hw *hw;
4508         struct i40e_vsi_context ctxt;
4509         uint8_t vlan_flags = 0;
4510         int ret;
4511
4512         if (vsi == NULL || info == NULL) {
4513                 PMD_DRV_LOG(ERR, "invalid parameters");
4514                 return I40E_ERR_PARAM;
4515         }
4516
4517         if (info->on) {
4518                 vsi->info.pvid = info->config.pvid;
4519                 /**
4520                  * If insert pvid is enabled, only tagged pkts are
4521                  * allowed to be sent out.
4522                  */
4523                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4524                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4525         } else {
4526                 vsi->info.pvid = 0;
4527                 if (info->config.reject.tagged == 0)
4528                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4529
4530                 if (info->config.reject.untagged == 0)
4531                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4532         }
4533         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4534                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4535         vsi->info.port_vlan_flags |= vlan_flags;
4536         vsi->info.valid_sections =
4537                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4538         memset(&ctxt, 0, sizeof(ctxt));
4539         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4540         ctxt.seid = vsi->seid;
4541
4542         hw = I40E_VSI_TO_HW(vsi);
4543         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4544         if (ret != I40E_SUCCESS)
4545                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4546
4547         return ret;
4548 }
4549
4550 static int
4551 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4552 {
4553         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4554         int i, ret;
4555         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4556
4557         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4558         if (ret != I40E_SUCCESS)
4559                 return ret;
4560
4561         if (!vsi->seid) {
4562                 PMD_DRV_LOG(ERR, "seid not valid");
4563                 return -EINVAL;
4564         }
4565
4566         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4567         tc_bw_data.tc_valid_bits = enabled_tcmap;
4568         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4569                 tc_bw_data.tc_bw_credits[i] =
4570                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4571
4572         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4573         if (ret != I40E_SUCCESS) {
4574                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4575                 return ret;
4576         }
4577
4578         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4579                                         sizeof(vsi->info.qs_handle));
4580         return I40E_SUCCESS;
4581 }
4582
4583 static enum i40e_status_code
4584 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4585                                  struct i40e_aqc_vsi_properties_data *info,
4586                                  uint8_t enabled_tcmap)
4587 {
4588         enum i40e_status_code ret;
4589         int i, total_tc = 0;
4590         uint16_t qpnum_per_tc, bsf, qp_idx;
4591
4592         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4593         if (ret != I40E_SUCCESS)
4594                 return ret;
4595
4596         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4597                 if (enabled_tcmap & (1 << i))
4598                         total_tc++;
4599         if (total_tc == 0)
4600                 total_tc = 1;
4601         vsi->enabled_tc = enabled_tcmap;
4602
4603         /* Number of queues per enabled TC */
4604         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4605         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4606         bsf = rte_bsf32(qpnum_per_tc);
4607
4608         /* Adjust the queue number to actual queues that can be applied */
4609         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4610                 vsi->nb_qps = qpnum_per_tc * total_tc;
4611
4612         /**
4613          * Configure TC and queue mapping parameters, for enabled TC,
4614          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4615          * default queue will serve it.
4616          */
4617         qp_idx = 0;
4618         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4619                 if (vsi->enabled_tc & (1 << i)) {
4620                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4621                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4622                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4623                         qp_idx += qpnum_per_tc;
4624                 } else
4625                         info->tc_mapping[i] = 0;
4626         }
4627
4628         /* Associate queue number with VSI */
4629         if (vsi->type == I40E_VSI_SRIOV) {
4630                 info->mapping_flags |=
4631                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4632                 for (i = 0; i < vsi->nb_qps; i++)
4633                         info->queue_mapping[i] =
4634                                 rte_cpu_to_le_16(vsi->base_queue + i);
4635         } else {
4636                 info->mapping_flags |=
4637                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4638                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4639         }
4640         info->valid_sections |=
4641                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4642
4643         return I40E_SUCCESS;
4644 }
4645
4646 static int
4647 i40e_veb_release(struct i40e_veb *veb)
4648 {
4649         struct i40e_vsi *vsi;
4650         struct i40e_hw *hw;
4651
4652         if (veb == NULL)
4653                 return -EINVAL;
4654
4655         if (!TAILQ_EMPTY(&veb->head)) {
4656                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4657                 return -EACCES;
4658         }
4659         /* associate_vsi field is NULL for floating VEB */
4660         if (veb->associate_vsi != NULL) {
4661                 vsi = veb->associate_vsi;
4662                 hw = I40E_VSI_TO_HW(vsi);
4663
4664                 vsi->uplink_seid = veb->uplink_seid;
4665                 vsi->veb = NULL;
4666         } else {
4667                 veb->associate_pf->main_vsi->floating_veb = NULL;
4668                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4669         }
4670
4671         i40e_aq_delete_element(hw, veb->seid, NULL);
4672         rte_free(veb);
4673         return I40E_SUCCESS;
4674 }
4675
4676 /* Setup a veb */
4677 static struct i40e_veb *
4678 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4679 {
4680         struct i40e_veb *veb;
4681         int ret;
4682         struct i40e_hw *hw;
4683
4684         if (pf == NULL) {
4685                 PMD_DRV_LOG(ERR,
4686                             "veb setup failed, associated PF shouldn't null");
4687                 return NULL;
4688         }
4689         hw = I40E_PF_TO_HW(pf);
4690
4691         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4692         if (!veb) {
4693                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4694                 goto fail;
4695         }
4696
4697         veb->associate_vsi = vsi;
4698         veb->associate_pf = pf;
4699         TAILQ_INIT(&veb->head);
4700         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4701
4702         /* create floating veb if vsi is NULL */
4703         if (vsi != NULL) {
4704                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4705                                       I40E_DEFAULT_TCMAP, false,
4706                                       &veb->seid, false, NULL);
4707         } else {
4708                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4709                                       true, &veb->seid, false, NULL);
4710         }
4711
4712         if (ret != I40E_SUCCESS) {
4713                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4714                             hw->aq.asq_last_status);
4715                 goto fail;
4716         }
4717         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4718
4719         /* get statistics index */
4720         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4721                                 &veb->stats_idx, NULL, NULL, NULL);
4722         if (ret != I40E_SUCCESS) {
4723                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4724                             hw->aq.asq_last_status);
4725                 goto fail;
4726         }
4727         /* Get VEB bandwidth, to be implemented */
4728         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4729         if (vsi)
4730                 vsi->uplink_seid = veb->seid;
4731
4732         return veb;
4733 fail:
4734         rte_free(veb);
4735         return NULL;
4736 }
4737
4738 int
4739 i40e_vsi_release(struct i40e_vsi *vsi)
4740 {
4741         struct i40e_pf *pf;
4742         struct i40e_hw *hw;
4743         struct i40e_vsi_list *vsi_list;
4744         void *temp;
4745         int ret;
4746         struct i40e_mac_filter *f;
4747         uint16_t user_param;
4748
4749         if (!vsi)
4750                 return I40E_SUCCESS;
4751
4752         if (!vsi->adapter)
4753                 return -EFAULT;
4754
4755         user_param = vsi->user_param;
4756
4757         pf = I40E_VSI_TO_PF(vsi);
4758         hw = I40E_VSI_TO_HW(vsi);
4759
4760         /* VSI has child to attach, release child first */
4761         if (vsi->veb) {
4762                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4763                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4764                                 return -1;
4765                 }
4766                 i40e_veb_release(vsi->veb);
4767         }
4768
4769         if (vsi->floating_veb) {
4770                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4771                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4772                                 return -1;
4773                 }
4774         }
4775
4776         /* Remove all macvlan filters of the VSI */
4777         i40e_vsi_remove_all_macvlan_filter(vsi);
4778         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4779                 rte_free(f);
4780
4781         if (vsi->type != I40E_VSI_MAIN &&
4782             ((vsi->type != I40E_VSI_SRIOV) ||
4783             !pf->floating_veb_list[user_param])) {
4784                 /* Remove vsi from parent's sibling list */
4785                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4786                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4787                         return I40E_ERR_PARAM;
4788                 }
4789                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4790                                 &vsi->sib_vsi_list, list);
4791
4792                 /* Remove all switch element of the VSI */
4793                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4794                 if (ret != I40E_SUCCESS)
4795                         PMD_DRV_LOG(ERR, "Failed to delete element");
4796         }
4797
4798         if ((vsi->type == I40E_VSI_SRIOV) &&
4799             pf->floating_veb_list[user_param]) {
4800                 /* Remove vsi from parent's sibling list */
4801                 if (vsi->parent_vsi == NULL ||
4802                     vsi->parent_vsi->floating_veb == NULL) {
4803                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4804                         return I40E_ERR_PARAM;
4805                 }
4806                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4807                              &vsi->sib_vsi_list, list);
4808
4809                 /* Remove all switch element of the VSI */
4810                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4811                 if (ret != I40E_SUCCESS)
4812                         PMD_DRV_LOG(ERR, "Failed to delete element");
4813         }
4814
4815         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4816
4817         if (vsi->type != I40E_VSI_SRIOV)
4818                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4819         rte_free(vsi);
4820
4821         return I40E_SUCCESS;
4822 }
4823
4824 static int
4825 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4826 {
4827         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4828         struct i40e_aqc_remove_macvlan_element_data def_filter;
4829         struct i40e_mac_filter_info filter;
4830         int ret;
4831
4832         if (vsi->type != I40E_VSI_MAIN)
4833                 return I40E_ERR_CONFIG;
4834         memset(&def_filter, 0, sizeof(def_filter));
4835         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4836                                         ETH_ADDR_LEN);
4837         def_filter.vlan_tag = 0;
4838         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4839                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4840         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4841         if (ret != I40E_SUCCESS) {
4842                 struct i40e_mac_filter *f;
4843                 struct ether_addr *mac;
4844
4845                 PMD_DRV_LOG(DEBUG,
4846                             "Cannot remove the default macvlan filter");
4847                 /* It needs to add the permanent mac into mac list */
4848                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4849                 if (f == NULL) {
4850                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4851                         return I40E_ERR_NO_MEMORY;
4852                 }
4853                 mac = &f->mac_info.mac_addr;
4854                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4855                                 ETH_ADDR_LEN);
4856                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4857                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4858                 vsi->mac_num++;
4859
4860                 return ret;
4861         }
4862         rte_memcpy(&filter.mac_addr,
4863                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4864         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4865         return i40e_vsi_add_mac(vsi, &filter);
4866 }
4867
4868 /*
4869  * i40e_vsi_get_bw_config - Query VSI BW Information
4870  * @vsi: the VSI to be queried
4871  *
4872  * Returns 0 on success, negative value on failure
4873  */
4874 static enum i40e_status_code
4875 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4876 {
4877         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4878         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4879         struct i40e_hw *hw = &vsi->adapter->hw;
4880         i40e_status ret;
4881         int i;
4882         uint32_t bw_max;
4883
4884         memset(&bw_config, 0, sizeof(bw_config));
4885         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4886         if (ret != I40E_SUCCESS) {
4887                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4888                             hw->aq.asq_last_status);
4889                 return ret;
4890         }
4891
4892         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4893         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4894                                         &ets_sla_config, NULL);
4895         if (ret != I40E_SUCCESS) {
4896                 PMD_DRV_LOG(ERR,
4897                         "VSI failed to get TC bandwdith configuration %u",
4898                         hw->aq.asq_last_status);
4899                 return ret;
4900         }
4901
4902         /* store and print out BW info */
4903         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4904         vsi->bw_info.bw_max = bw_config.max_bw;
4905         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4906         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4907         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4908                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4909                      I40E_16_BIT_WIDTH);
4910         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4911                 vsi->bw_info.bw_ets_share_credits[i] =
4912                                 ets_sla_config.share_credits[i];
4913                 vsi->bw_info.bw_ets_credits[i] =
4914                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4915                 /* 4 bits per TC, 4th bit is reserved */
4916                 vsi->bw_info.bw_ets_max[i] =
4917                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4918                                   RTE_LEN2MASK(3, uint8_t));
4919                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4920                             vsi->bw_info.bw_ets_share_credits[i]);
4921                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4922                             vsi->bw_info.bw_ets_credits[i]);
4923                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4924                             vsi->bw_info.bw_ets_max[i]);
4925         }
4926
4927         return I40E_SUCCESS;
4928 }
4929
4930 /* i40e_enable_pf_lb
4931  * @pf: pointer to the pf structure
4932  *
4933  * allow loopback on pf
4934  */
4935 static inline void
4936 i40e_enable_pf_lb(struct i40e_pf *pf)
4937 {
4938         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4939         struct i40e_vsi_context ctxt;
4940         int ret;
4941
4942         /* Use the FW API if FW >= v5.0 */
4943         if (hw->aq.fw_maj_ver < 5) {
4944                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4945                 return;
4946         }
4947
4948         memset(&ctxt, 0, sizeof(ctxt));
4949         ctxt.seid = pf->main_vsi_seid;
4950         ctxt.pf_num = hw->pf_id;
4951         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4952         if (ret) {
4953                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4954                             ret, hw->aq.asq_last_status);
4955                 return;
4956         }
4957         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4958         ctxt.info.valid_sections =
4959                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4960         ctxt.info.switch_id |=
4961                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4962
4963         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4964         if (ret)
4965                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4966                             hw->aq.asq_last_status);
4967 }
4968
4969 /* Setup a VSI */
4970 struct i40e_vsi *
4971 i40e_vsi_setup(struct i40e_pf *pf,
4972                enum i40e_vsi_type type,
4973                struct i40e_vsi *uplink_vsi,
4974                uint16_t user_param)
4975 {
4976         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4977         struct i40e_vsi *vsi;
4978         struct i40e_mac_filter_info filter;
4979         int ret;
4980         struct i40e_vsi_context ctxt;
4981         struct ether_addr broadcast =
4982                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4983
4984         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4985             uplink_vsi == NULL) {
4986                 PMD_DRV_LOG(ERR,
4987                         "VSI setup failed, VSI link shouldn't be NULL");
4988                 return NULL;
4989         }
4990
4991         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4992                 PMD_DRV_LOG(ERR,
4993                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4994                 return NULL;
4995         }
4996
4997         /* two situations
4998          * 1.type is not MAIN and uplink vsi is not NULL
4999          * If uplink vsi didn't setup VEB, create one first under veb field
5000          * 2.type is SRIOV and the uplink is NULL
5001          * If floating VEB is NULL, create one veb under floating veb field
5002          */
5003
5004         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5005             uplink_vsi->veb == NULL) {
5006                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5007
5008                 if (uplink_vsi->veb == NULL) {
5009                         PMD_DRV_LOG(ERR, "VEB setup failed");
5010                         return NULL;
5011                 }
5012                 /* set ALLOWLOOPBACk on pf, when veb is created */
5013                 i40e_enable_pf_lb(pf);
5014         }
5015
5016         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5017             pf->main_vsi->floating_veb == NULL) {
5018                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5019
5020                 if (pf->main_vsi->floating_veb == NULL) {
5021                         PMD_DRV_LOG(ERR, "VEB setup failed");
5022                         return NULL;
5023                 }
5024         }
5025
5026         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5027         if (!vsi) {
5028                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5029                 return NULL;
5030         }
5031         TAILQ_INIT(&vsi->mac_list);
5032         vsi->type = type;
5033         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5034         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5035         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5036         vsi->user_param = user_param;
5037         vsi->vlan_anti_spoof_on = 0;
5038         vsi->vlan_filter_on = 0;
5039         /* Allocate queues */
5040         switch (vsi->type) {
5041         case I40E_VSI_MAIN  :
5042                 vsi->nb_qps = pf->lan_nb_qps;
5043                 break;
5044         case I40E_VSI_SRIOV :
5045                 vsi->nb_qps = pf->vf_nb_qps;
5046                 break;
5047         case I40E_VSI_VMDQ2:
5048                 vsi->nb_qps = pf->vmdq_nb_qps;
5049                 break;
5050         case I40E_VSI_FDIR:
5051                 vsi->nb_qps = pf->fdir_nb_qps;
5052                 break;
5053         default:
5054                 goto fail_mem;
5055         }
5056         /*
5057          * The filter status descriptor is reported in rx queue 0,
5058          * while the tx queue for fdir filter programming has no
5059          * such constraints, can be non-zero queues.
5060          * To simplify it, choose FDIR vsi use queue 0 pair.
5061          * To make sure it will use queue 0 pair, queue allocation
5062          * need be done before this function is called
5063          */
5064         if (type != I40E_VSI_FDIR) {
5065                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5066                         if (ret < 0) {
5067                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5068                                                 vsi->seid, ret);
5069                                 goto fail_mem;
5070                         }
5071                         vsi->base_queue = ret;
5072         } else
5073                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5074
5075         /* VF has MSIX interrupt in VF range, don't allocate here */
5076         if (type == I40E_VSI_MAIN) {
5077                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5078                                           RTE_MIN(vsi->nb_qps,
5079                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5080                 if (ret < 0) {
5081                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5082                                     vsi->seid, ret);
5083                         goto fail_queue_alloc;
5084                 }
5085                 vsi->msix_intr = ret;
5086                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5087         } else if (type != I40E_VSI_SRIOV) {
5088                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5089                 if (ret < 0) {
5090                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5091                         goto fail_queue_alloc;
5092                 }
5093                 vsi->msix_intr = ret;
5094                 vsi->nb_msix = 1;
5095         } else {
5096                 vsi->msix_intr = 0;
5097                 vsi->nb_msix = 0;
5098         }
5099
5100         /* Add VSI */
5101         if (type == I40E_VSI_MAIN) {
5102                 /* For main VSI, no need to add since it's default one */
5103                 vsi->uplink_seid = pf->mac_seid;
5104                 vsi->seid = pf->main_vsi_seid;
5105                 /* Bind queues with specific MSIX interrupt */
5106                 /**
5107                  * Needs 2 interrupt at least, one for misc cause which will
5108                  * enabled from OS side, Another for queues binding the
5109                  * interrupt from device side only.
5110                  */
5111
5112                 /* Get default VSI parameters from hardware */
5113                 memset(&ctxt, 0, sizeof(ctxt));
5114                 ctxt.seid = vsi->seid;
5115                 ctxt.pf_num = hw->pf_id;
5116                 ctxt.uplink_seid = vsi->uplink_seid;
5117                 ctxt.vf_num = 0;
5118                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5119                 if (ret != I40E_SUCCESS) {
5120                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5121                         goto fail_msix_alloc;
5122                 }
5123                 rte_memcpy(&vsi->info, &ctxt.info,
5124                         sizeof(struct i40e_aqc_vsi_properties_data));
5125                 vsi->vsi_id = ctxt.vsi_number;
5126                 vsi->info.valid_sections = 0;
5127
5128                 /* Configure tc, enabled TC0 only */
5129                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5130                         I40E_SUCCESS) {
5131                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5132                         goto fail_msix_alloc;
5133                 }
5134
5135                 /* TC, queue mapping */
5136                 memset(&ctxt, 0, sizeof(ctxt));
5137                 vsi->info.valid_sections |=
5138                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5139                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5140                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5141                 rte_memcpy(&ctxt.info, &vsi->info,
5142                         sizeof(struct i40e_aqc_vsi_properties_data));
5143                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5144                                                 I40E_DEFAULT_TCMAP);
5145                 if (ret != I40E_SUCCESS) {
5146                         PMD_DRV_LOG(ERR,
5147                                 "Failed to configure TC queue mapping");
5148                         goto fail_msix_alloc;
5149                 }
5150                 ctxt.seid = vsi->seid;
5151                 ctxt.pf_num = hw->pf_id;
5152                 ctxt.uplink_seid = vsi->uplink_seid;
5153                 ctxt.vf_num = 0;
5154
5155                 /* Update VSI parameters */
5156                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5157                 if (ret != I40E_SUCCESS) {
5158                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5159                         goto fail_msix_alloc;
5160                 }
5161
5162                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5163                                                 sizeof(vsi->info.tc_mapping));
5164                 rte_memcpy(&vsi->info.queue_mapping,
5165                                 &ctxt.info.queue_mapping,
5166                         sizeof(vsi->info.queue_mapping));
5167                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5168                 vsi->info.valid_sections = 0;
5169
5170                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5171                                 ETH_ADDR_LEN);
5172
5173                 /**
5174                  * Updating default filter settings are necessary to prevent
5175                  * reception of tagged packets.
5176                  * Some old firmware configurations load a default macvlan
5177                  * filter which accepts both tagged and untagged packets.
5178                  * The updating is to use a normal filter instead if needed.
5179                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5180                  * The firmware with correct configurations load the default
5181                  * macvlan filter which is expected and cannot be removed.
5182                  */
5183                 i40e_update_default_filter_setting(vsi);
5184                 i40e_config_qinq(hw, vsi);
5185         } else if (type == I40E_VSI_SRIOV) {
5186                 memset(&ctxt, 0, sizeof(ctxt));
5187                 /**
5188                  * For other VSI, the uplink_seid equals to uplink VSI's
5189                  * uplink_seid since they share same VEB
5190                  */
5191                 if (uplink_vsi == NULL)
5192                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5193                 else
5194                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5195                 ctxt.pf_num = hw->pf_id;
5196                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5197                 ctxt.uplink_seid = vsi->uplink_seid;
5198                 ctxt.connection_type = 0x1;
5199                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5200
5201                 /* Use the VEB configuration if FW >= v5.0 */
5202                 if (hw->aq.fw_maj_ver >= 5) {
5203                         /* Configure switch ID */
5204                         ctxt.info.valid_sections |=
5205                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5206                         ctxt.info.switch_id =
5207                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5208                 }
5209
5210                 /* Configure port/vlan */
5211                 ctxt.info.valid_sections |=
5212                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5213                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5214                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5215                                                 hw->func_caps.enabled_tcmap);
5216                 if (ret != I40E_SUCCESS) {
5217                         PMD_DRV_LOG(ERR,
5218                                 "Failed to configure TC queue mapping");
5219                         goto fail_msix_alloc;
5220                 }
5221
5222                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5223                 ctxt.info.valid_sections |=
5224                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5225                 /**
5226                  * Since VSI is not created yet, only configure parameter,
5227                  * will add vsi below.
5228                  */
5229
5230                 i40e_config_qinq(hw, vsi);
5231         } else if (type == I40E_VSI_VMDQ2) {
5232                 memset(&ctxt, 0, sizeof(ctxt));
5233                 /*
5234                  * For other VSI, the uplink_seid equals to uplink VSI's
5235                  * uplink_seid since they share same VEB
5236                  */
5237                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5238                 ctxt.pf_num = hw->pf_id;
5239                 ctxt.vf_num = 0;
5240                 ctxt.uplink_seid = vsi->uplink_seid;
5241                 ctxt.connection_type = 0x1;
5242                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5243
5244                 ctxt.info.valid_sections |=
5245                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5246                 /* user_param carries flag to enable loop back */
5247                 if (user_param) {
5248                         ctxt.info.switch_id =
5249                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5250                         ctxt.info.switch_id |=
5251                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5252                 }
5253
5254                 /* Configure port/vlan */
5255                 ctxt.info.valid_sections |=
5256                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5257                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5258                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5259                                                 I40E_DEFAULT_TCMAP);
5260                 if (ret != I40E_SUCCESS) {
5261                         PMD_DRV_LOG(ERR,
5262                                 "Failed to configure TC queue mapping");
5263                         goto fail_msix_alloc;
5264                 }
5265                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5266                 ctxt.info.valid_sections |=
5267                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5268         } else if (type == I40E_VSI_FDIR) {
5269                 memset(&ctxt, 0, sizeof(ctxt));
5270                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5271                 ctxt.pf_num = hw->pf_id;
5272                 ctxt.vf_num = 0;
5273                 ctxt.uplink_seid = vsi->uplink_seid;
5274                 ctxt.connection_type = 0x1;     /* regular data port */
5275                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5276                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5277                                                 I40E_DEFAULT_TCMAP);
5278                 if (ret != I40E_SUCCESS) {
5279                         PMD_DRV_LOG(ERR,
5280                                 "Failed to configure TC queue mapping.");
5281                         goto fail_msix_alloc;
5282                 }
5283                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5284                 ctxt.info.valid_sections |=
5285                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5286         } else {
5287                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5288                 goto fail_msix_alloc;
5289         }
5290
5291         if (vsi->type != I40E_VSI_MAIN) {
5292                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5293                 if (ret != I40E_SUCCESS) {
5294                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5295                                     hw->aq.asq_last_status);
5296                         goto fail_msix_alloc;
5297                 }
5298                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5299                 vsi->info.valid_sections = 0;
5300                 vsi->seid = ctxt.seid;
5301                 vsi->vsi_id = ctxt.vsi_number;
5302                 vsi->sib_vsi_list.vsi = vsi;
5303                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5304                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5305                                           &vsi->sib_vsi_list, list);
5306                 } else {
5307                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5308                                           &vsi->sib_vsi_list, list);
5309                 }
5310         }
5311
5312         /* MAC/VLAN configuration */
5313         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5314         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5315
5316         ret = i40e_vsi_add_mac(vsi, &filter);
5317         if (ret != I40E_SUCCESS) {
5318                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5319                 goto fail_msix_alloc;
5320         }
5321
5322         /* Get VSI BW information */
5323         i40e_vsi_get_bw_config(vsi);
5324         return vsi;
5325 fail_msix_alloc:
5326         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5327 fail_queue_alloc:
5328         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5329 fail_mem:
5330         rte_free(vsi);
5331         return NULL;
5332 }
5333
5334 /* Configure vlan filter on or off */
5335 int
5336 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5337 {
5338         int i, num;
5339         struct i40e_mac_filter *f;
5340         void *temp;
5341         struct i40e_mac_filter_info *mac_filter;
5342         enum rte_mac_filter_type desired_filter;
5343         int ret = I40E_SUCCESS;
5344
5345         if (on) {
5346                 /* Filter to match MAC and VLAN */
5347                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5348         } else {
5349                 /* Filter to match only MAC */
5350                 desired_filter = RTE_MAC_PERFECT_MATCH;
5351         }
5352
5353         num = vsi->mac_num;
5354
5355         mac_filter = rte_zmalloc("mac_filter_info_data",
5356                                  num * sizeof(*mac_filter), 0);
5357         if (mac_filter == NULL) {
5358                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5359                 return I40E_ERR_NO_MEMORY;
5360         }
5361
5362         i = 0;
5363
5364         /* Remove all existing mac */
5365         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5366                 mac_filter[i] = f->mac_info;
5367                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5368                 if (ret) {
5369                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5370                                     on ? "enable" : "disable");
5371                         goto DONE;
5372                 }
5373                 i++;
5374         }
5375
5376         /* Override with new filter */
5377         for (i = 0; i < num; i++) {
5378                 mac_filter[i].filter_type = desired_filter;
5379                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5380                 if (ret) {
5381                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5382                                     on ? "enable" : "disable");
5383                         goto DONE;
5384                 }
5385         }
5386
5387 DONE:
5388         rte_free(mac_filter);
5389         return ret;
5390 }
5391
5392 /* Configure vlan stripping on or off */
5393 int
5394 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5395 {
5396         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5397         struct i40e_vsi_context ctxt;
5398         uint8_t vlan_flags;
5399         int ret = I40E_SUCCESS;
5400
5401         /* Check if it has been already on or off */
5402         if (vsi->info.valid_sections &
5403                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5404                 if (on) {
5405                         if ((vsi->info.port_vlan_flags &
5406                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5407                                 return 0; /* already on */
5408                 } else {
5409                         if ((vsi->info.port_vlan_flags &
5410                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5411                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5412                                 return 0; /* already off */
5413                 }
5414         }
5415
5416         if (on)
5417                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5418         else
5419                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5420         vsi->info.valid_sections =
5421                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5422         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5423         vsi->info.port_vlan_flags |= vlan_flags;
5424         ctxt.seid = vsi->seid;
5425         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5426         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5427         if (ret)
5428                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5429                             on ? "enable" : "disable");
5430
5431         return ret;
5432 }
5433
5434 static int
5435 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5436 {
5437         struct rte_eth_dev_data *data = dev->data;
5438         int ret;
5439         int mask = 0;
5440
5441         /* Apply vlan offload setting */
5442         mask = ETH_VLAN_STRIP_MASK |
5443                ETH_VLAN_FILTER_MASK |
5444                ETH_VLAN_EXTEND_MASK;
5445         ret = i40e_vlan_offload_set(dev, mask);
5446         if (ret) {
5447                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5448                 return ret;
5449         }
5450
5451         /* Apply pvid setting */
5452         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5453                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5454         if (ret)
5455                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5456
5457         return ret;
5458 }
5459
5460 static int
5461 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5462 {
5463         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5464
5465         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5466 }
5467
5468 static int
5469 i40e_update_flow_control(struct i40e_hw *hw)
5470 {
5471 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5472         struct i40e_link_status link_status;
5473         uint32_t rxfc = 0, txfc = 0, reg;
5474         uint8_t an_info;
5475         int ret;
5476
5477         memset(&link_status, 0, sizeof(link_status));
5478         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5479         if (ret != I40E_SUCCESS) {
5480                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5481                 goto write_reg; /* Disable flow control */
5482         }
5483
5484         an_info = hw->phy.link_info.an_info;
5485         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5486                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5487                 ret = I40E_ERR_NOT_READY;
5488                 goto write_reg; /* Disable flow control */
5489         }
5490         /**
5491          * If link auto negotiation is enabled, flow control needs to
5492          * be configured according to it
5493          */
5494         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5495         case I40E_LINK_PAUSE_RXTX:
5496                 rxfc = 1;
5497                 txfc = 1;
5498                 hw->fc.current_mode = I40E_FC_FULL;
5499                 break;
5500         case I40E_AQ_LINK_PAUSE_RX:
5501                 rxfc = 1;
5502                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5503                 break;
5504         case I40E_AQ_LINK_PAUSE_TX:
5505                 txfc = 1;
5506                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5507                 break;
5508         default:
5509                 hw->fc.current_mode = I40E_FC_NONE;
5510                 break;
5511         }
5512
5513 write_reg:
5514         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5515                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5516         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5517         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5518         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5519         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5520
5521         return ret;
5522 }
5523
5524 /* PF setup */
5525 static int
5526 i40e_pf_setup(struct i40e_pf *pf)
5527 {
5528         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5529         struct i40e_filter_control_settings settings;
5530         struct i40e_vsi *vsi;
5531         int ret;
5532
5533         /* Clear all stats counters */
5534         pf->offset_loaded = FALSE;
5535         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5536         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5537         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5538         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5539
5540         ret = i40e_pf_get_switch_config(pf);
5541         if (ret != I40E_SUCCESS) {
5542                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5543                 return ret;
5544         }
5545         if (pf->flags & I40E_FLAG_FDIR) {
5546                 /* make queue allocated first, let FDIR use queue pair 0*/
5547                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5548                 if (ret != I40E_FDIR_QUEUE_ID) {
5549                         PMD_DRV_LOG(ERR,
5550                                 "queue allocation fails for FDIR: ret =%d",
5551                                 ret);
5552                         pf->flags &= ~I40E_FLAG_FDIR;
5553                 }
5554         }
5555         /*  main VSI setup */
5556         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5557         if (!vsi) {
5558                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5559                 return I40E_ERR_NOT_READY;
5560         }
5561         pf->main_vsi = vsi;
5562
5563         /* Configure filter control */
5564         memset(&settings, 0, sizeof(settings));
5565         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5566                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5567         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5568                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5569         else {
5570                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5571                         hw->func_caps.rss_table_size);
5572                 return I40E_ERR_PARAM;
5573         }
5574         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5575                 hw->func_caps.rss_table_size);
5576         pf->hash_lut_size = hw->func_caps.rss_table_size;
5577
5578         /* Enable ethtype and macvlan filters */
5579         settings.enable_ethtype = TRUE;
5580         settings.enable_macvlan = TRUE;
5581         ret = i40e_set_filter_control(hw, &settings);
5582         if (ret)
5583                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5584                                                                 ret);
5585
5586         /* Update flow control according to the auto negotiation */
5587         i40e_update_flow_control(hw);
5588
5589         return I40E_SUCCESS;
5590 }
5591
5592 int
5593 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5594 {
5595         uint32_t reg;
5596         uint16_t j;
5597
5598         /**
5599          * Set or clear TX Queue Disable flags,
5600          * which is required by hardware.
5601          */
5602         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5603         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5604
5605         /* Wait until the request is finished */
5606         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5607                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5608                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5609                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5610                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5611                                                         & 0x1))) {
5612                         break;
5613                 }
5614         }
5615         if (on) {
5616                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5617                         return I40E_SUCCESS; /* already on, skip next steps */
5618
5619                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5620                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5621         } else {
5622                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5623                         return I40E_SUCCESS; /* already off, skip next steps */
5624                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5625         }
5626         /* Write the register */
5627         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5628         /* Check the result */
5629         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5630                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5631                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5632                 if (on) {
5633                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5634                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5635                                 break;
5636                 } else {
5637                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5638                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5639                                 break;
5640                 }
5641         }
5642         /* Check if it is timeout */
5643         if (j >= I40E_CHK_Q_ENA_COUNT) {
5644                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5645                             (on ? "enable" : "disable"), q_idx);
5646                 return I40E_ERR_TIMEOUT;
5647         }
5648
5649         return I40E_SUCCESS;
5650 }
5651
5652 /* Swith on or off the tx queues */
5653 static int
5654 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5655 {
5656         struct rte_eth_dev_data *dev_data = pf->dev_data;
5657         struct i40e_tx_queue *txq;
5658         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5659         uint16_t i;
5660         int ret;
5661
5662         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5663                 txq = dev_data->tx_queues[i];
5664                 /* Don't operate the queue if not configured or
5665                  * if starting only per queue */
5666                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5667                         continue;
5668                 if (on)
5669                         ret = i40e_dev_tx_queue_start(dev, i);
5670                 else
5671                         ret = i40e_dev_tx_queue_stop(dev, i);
5672                 if ( ret != I40E_SUCCESS)
5673                         return ret;
5674         }
5675
5676         return I40E_SUCCESS;
5677 }
5678
5679 int
5680 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5681 {
5682         uint32_t reg;
5683         uint16_t j;
5684
5685         /* Wait until the request is finished */
5686         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5687                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5688                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5689                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5690                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5691                         break;
5692         }
5693
5694         if (on) {
5695                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5696                         return I40E_SUCCESS; /* Already on, skip next steps */
5697                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5698         } else {
5699                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5700                         return I40E_SUCCESS; /* Already off, skip next steps */
5701                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5702         }
5703
5704         /* Write the register */
5705         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5706         /* Check the result */
5707         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5708                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5709                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5710                 if (on) {
5711                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5712                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5713                                 break;
5714                 } else {
5715                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5716                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5717                                 break;
5718                 }
5719         }
5720
5721         /* Check if it is timeout */
5722         if (j >= I40E_CHK_Q_ENA_COUNT) {
5723                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5724                             (on ? "enable" : "disable"), q_idx);
5725                 return I40E_ERR_TIMEOUT;
5726         }
5727
5728         return I40E_SUCCESS;
5729 }
5730 /* Switch on or off the rx queues */
5731 static int
5732 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5733 {
5734         struct rte_eth_dev_data *dev_data = pf->dev_data;
5735         struct i40e_rx_queue *rxq;
5736         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5737         uint16_t i;
5738         int ret;
5739
5740         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5741                 rxq = dev_data->rx_queues[i];
5742                 /* Don't operate the queue if not configured or
5743                  * if starting only per queue */
5744                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5745                         continue;
5746                 if (on)
5747                         ret = i40e_dev_rx_queue_start(dev, i);
5748                 else
5749                         ret = i40e_dev_rx_queue_stop(dev, i);
5750                 if (ret != I40E_SUCCESS)
5751                         return ret;
5752         }
5753
5754         return I40E_SUCCESS;
5755 }
5756
5757 /* Switch on or off all the rx/tx queues */
5758 int
5759 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5760 {
5761         int ret;
5762
5763         if (on) {
5764                 /* enable rx queues before enabling tx queues */
5765                 ret = i40e_dev_switch_rx_queues(pf, on);
5766                 if (ret) {
5767                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5768                         return ret;
5769                 }
5770                 ret = i40e_dev_switch_tx_queues(pf, on);
5771         } else {
5772                 /* Stop tx queues before stopping rx queues */
5773                 ret = i40e_dev_switch_tx_queues(pf, on);
5774                 if (ret) {
5775                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5776                         return ret;
5777                 }
5778                 ret = i40e_dev_switch_rx_queues(pf, on);
5779         }
5780
5781         return ret;
5782 }
5783
5784 /* Initialize VSI for TX */
5785 static int
5786 i40e_dev_tx_init(struct i40e_pf *pf)
5787 {
5788         struct rte_eth_dev_data *data = pf->dev_data;
5789         uint16_t i;
5790         uint32_t ret = I40E_SUCCESS;
5791         struct i40e_tx_queue *txq;
5792
5793         for (i = 0; i < data->nb_tx_queues; i++) {
5794                 txq = data->tx_queues[i];
5795                 if (!txq || !txq->q_set)
5796                         continue;
5797                 ret = i40e_tx_queue_init(txq);
5798                 if (ret != I40E_SUCCESS)
5799                         break;
5800         }
5801         if (ret == I40E_SUCCESS)
5802                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5803                                      ->eth_dev);
5804
5805         return ret;
5806 }
5807
5808 /* Initialize VSI for RX */
5809 static int
5810 i40e_dev_rx_init(struct i40e_pf *pf)
5811 {
5812         struct rte_eth_dev_data *data = pf->dev_data;
5813         int ret = I40E_SUCCESS;
5814         uint16_t i;
5815         struct i40e_rx_queue *rxq;
5816
5817         i40e_pf_config_mq_rx(pf);
5818         for (i = 0; i < data->nb_rx_queues; i++) {
5819                 rxq = data->rx_queues[i];
5820                 if (!rxq || !rxq->q_set)
5821                         continue;
5822
5823                 ret = i40e_rx_queue_init(rxq);
5824                 if (ret != I40E_SUCCESS) {
5825                         PMD_DRV_LOG(ERR,
5826                                 "Failed to do RX queue initialization");
5827                         break;
5828                 }
5829         }
5830         if (ret == I40E_SUCCESS)
5831                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5832                                      ->eth_dev);
5833
5834         return ret;
5835 }
5836
5837 static int
5838 i40e_dev_rxtx_init(struct i40e_pf *pf)
5839 {
5840         int err;
5841
5842         err = i40e_dev_tx_init(pf);
5843         if (err) {
5844                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5845                 return err;
5846         }
5847         err = i40e_dev_rx_init(pf);
5848         if (err) {
5849                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5850                 return err;
5851         }
5852
5853         return err;
5854 }
5855
5856 static int
5857 i40e_vmdq_setup(struct rte_eth_dev *dev)
5858 {
5859         struct rte_eth_conf *conf = &dev->data->dev_conf;
5860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5861         int i, err, conf_vsis, j, loop;
5862         struct i40e_vsi *vsi;
5863         struct i40e_vmdq_info *vmdq_info;
5864         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5866
5867         /*
5868          * Disable interrupt to avoid message from VF. Furthermore, it will
5869          * avoid race condition in VSI creation/destroy.
5870          */
5871         i40e_pf_disable_irq0(hw);
5872
5873         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5874                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5875                 return -ENOTSUP;
5876         }
5877
5878         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5879         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5880                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5881                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5882                         pf->max_nb_vmdq_vsi);
5883                 return -ENOTSUP;
5884         }
5885
5886         if (pf->vmdq != NULL) {
5887                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5888                 return 0;
5889         }
5890
5891         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5892                                 sizeof(*vmdq_info) * conf_vsis, 0);
5893
5894         if (pf->vmdq == NULL) {
5895                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5896                 return -ENOMEM;
5897         }
5898
5899         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5900
5901         /* Create VMDQ VSI */
5902         for (i = 0; i < conf_vsis; i++) {
5903                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5904                                 vmdq_conf->enable_loop_back);
5905                 if (vsi == NULL) {
5906                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5907                         err = -1;
5908                         goto err_vsi_setup;
5909                 }
5910                 vmdq_info = &pf->vmdq[i];
5911                 vmdq_info->pf = pf;
5912                 vmdq_info->vsi = vsi;
5913         }
5914         pf->nb_cfg_vmdq_vsi = conf_vsis;
5915
5916         /* Configure Vlan */
5917         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5918         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5919                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5920                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5921                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5922                                         vmdq_conf->pool_map[i].vlan_id, j);
5923
5924                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5925                                                 vmdq_conf->pool_map[i].vlan_id);
5926                                 if (err) {
5927                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5928                                         err = -1;
5929                                         goto err_vsi_setup;
5930                                 }
5931                         }
5932                 }
5933         }
5934
5935         i40e_pf_enable_irq0(hw);
5936
5937         return 0;
5938
5939 err_vsi_setup:
5940         for (i = 0; i < conf_vsis; i++)
5941                 if (pf->vmdq[i].vsi == NULL)
5942                         break;
5943                 else
5944                         i40e_vsi_release(pf->vmdq[i].vsi);
5945
5946         rte_free(pf->vmdq);
5947         pf->vmdq = NULL;
5948         i40e_pf_enable_irq0(hw);
5949         return err;
5950 }
5951
5952 static void
5953 i40e_stat_update_32(struct i40e_hw *hw,
5954                    uint32_t reg,
5955                    bool offset_loaded,
5956                    uint64_t *offset,
5957                    uint64_t *stat)
5958 {
5959         uint64_t new_data;
5960
5961         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5962         if (!offset_loaded)
5963                 *offset = new_data;
5964
5965         if (new_data >= *offset)
5966                 *stat = (uint64_t)(new_data - *offset);
5967         else
5968                 *stat = (uint64_t)((new_data +
5969                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5970 }
5971
5972 static void
5973 i40e_stat_update_48(struct i40e_hw *hw,
5974                    uint32_t hireg,
5975                    uint32_t loreg,
5976                    bool offset_loaded,
5977                    uint64_t *offset,
5978                    uint64_t *stat)
5979 {
5980         uint64_t new_data;
5981
5982         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5983         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5984                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5985
5986         if (!offset_loaded)
5987                 *offset = new_data;
5988
5989         if (new_data >= *offset)
5990                 *stat = new_data - *offset;
5991         else
5992                 *stat = (uint64_t)((new_data +
5993                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5994
5995         *stat &= I40E_48_BIT_MASK;
5996 }
5997
5998 /* Disable IRQ0 */
5999 void
6000 i40e_pf_disable_irq0(struct i40e_hw *hw)
6001 {
6002         /* Disable all interrupt types */
6003         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6004         I40E_WRITE_FLUSH(hw);
6005 }
6006
6007 /* Enable IRQ0 */
6008 void
6009 i40e_pf_enable_irq0(struct i40e_hw *hw)
6010 {
6011         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6012                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6013                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6014                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6015         I40E_WRITE_FLUSH(hw);
6016 }
6017
6018 static void
6019 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6020 {
6021         /* read pending request and disable first */
6022         i40e_pf_disable_irq0(hw);
6023         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6024         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6025                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6026
6027         if (no_queue)
6028                 /* Link no queues with irq0 */
6029                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6030                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6031 }
6032
6033 static void
6034 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6035 {
6036         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6038         int i;
6039         uint16_t abs_vf_id;
6040         uint32_t index, offset, val;
6041
6042         if (!pf->vfs)
6043                 return;
6044         /**
6045          * Try to find which VF trigger a reset, use absolute VF id to access
6046          * since the reg is global register.
6047          */
6048         for (i = 0; i < pf->vf_num; i++) {
6049                 abs_vf_id = hw->func_caps.vf_base_id + i;
6050                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6051                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6052                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6053                 /* VFR event occurred */
6054                 if (val & (0x1 << offset)) {
6055                         int ret;
6056
6057                         /* Clear the event first */
6058                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6059                                                         (0x1 << offset));
6060                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6061                         /**
6062                          * Only notify a VF reset event occurred,
6063                          * don't trigger another SW reset
6064                          */
6065                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6066                         if (ret != I40E_SUCCESS)
6067                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6068                 }
6069         }
6070 }
6071
6072 static void
6073 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6074 {
6075         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6076         int i;
6077
6078         for (i = 0; i < pf->vf_num; i++)
6079                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6080 }
6081
6082 static void
6083 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6084 {
6085         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6086         struct i40e_arq_event_info info;
6087         uint16_t pending, opcode;
6088         int ret;
6089
6090         info.buf_len = I40E_AQ_BUF_SZ;
6091         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6092         if (!info.msg_buf) {
6093                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6094                 return;
6095         }
6096
6097         pending = 1;
6098         while (pending) {
6099                 ret = i40e_clean_arq_element(hw, &info, &pending);
6100
6101                 if (ret != I40E_SUCCESS) {
6102                         PMD_DRV_LOG(INFO,
6103                                 "Failed to read msg from AdminQ, aq_err: %u",
6104                                 hw->aq.asq_last_status);
6105                         break;
6106                 }
6107                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6108
6109                 switch (opcode) {
6110                 case i40e_aqc_opc_send_msg_to_pf:
6111                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6112                         i40e_pf_host_handle_vf_msg(dev,
6113                                         rte_le_to_cpu_16(info.desc.retval),
6114                                         rte_le_to_cpu_32(info.desc.cookie_high),
6115                                         rte_le_to_cpu_32(info.desc.cookie_low),
6116                                         info.msg_buf,
6117                                         info.msg_len);
6118                         break;
6119                 case i40e_aqc_opc_get_link_status:
6120                         ret = i40e_dev_link_update(dev, 0);
6121                         if (!ret)
6122                                 _rte_eth_dev_callback_process(dev,
6123                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6124                         break;
6125                 default:
6126                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6127                                     opcode);
6128                         break;
6129                 }
6130         }
6131         rte_free(info.msg_buf);
6132 }
6133
6134 /**
6135  * Interrupt handler triggered by NIC  for handling
6136  * specific interrupt.
6137  *
6138  * @param handle
6139  *  Pointer to interrupt handle.
6140  * @param param
6141  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6142  *
6143  * @return
6144  *  void
6145  */
6146 static void
6147 i40e_dev_interrupt_handler(void *param)
6148 {
6149         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6151         uint32_t icr0;
6152
6153         /* Disable interrupt */
6154         i40e_pf_disable_irq0(hw);
6155
6156         /* read out interrupt causes */
6157         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6158
6159         /* No interrupt event indicated */
6160         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6161                 PMD_DRV_LOG(INFO, "No interrupt event");
6162                 goto done;
6163         }
6164         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6165                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6166         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6167                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6168         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6169                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6170         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6171                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6172         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6173                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6174         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6175                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6176         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6177                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6178
6179         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6180                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6181                 i40e_dev_handle_vfr_event(dev);
6182         }
6183         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6184                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6185                 i40e_dev_handle_aq_msg(dev);
6186         }
6187
6188 done:
6189         /* Enable interrupt */
6190         i40e_pf_enable_irq0(hw);
6191         rte_intr_enable(dev->intr_handle);
6192 }
6193
6194 int
6195 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6196                          struct i40e_macvlan_filter *filter,
6197                          int total)
6198 {
6199         int ele_num, ele_buff_size;
6200         int num, actual_num, i;
6201         uint16_t flags;
6202         int ret = I40E_SUCCESS;
6203         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6204         struct i40e_aqc_add_macvlan_element_data *req_list;
6205
6206         if (filter == NULL  || total == 0)
6207                 return I40E_ERR_PARAM;
6208         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6209         ele_buff_size = hw->aq.asq_buf_size;
6210
6211         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6212         if (req_list == NULL) {
6213                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6214                 return I40E_ERR_NO_MEMORY;
6215         }
6216
6217         num = 0;
6218         do {
6219                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6220                 memset(req_list, 0, ele_buff_size);
6221
6222                 for (i = 0; i < actual_num; i++) {
6223                         rte_memcpy(req_list[i].mac_addr,
6224                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6225                         req_list[i].vlan_tag =
6226                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6227
6228                         switch (filter[num + i].filter_type) {
6229                         case RTE_MAC_PERFECT_MATCH:
6230                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6231                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6232                                 break;
6233                         case RTE_MACVLAN_PERFECT_MATCH:
6234                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6235                                 break;
6236                         case RTE_MAC_HASH_MATCH:
6237                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6238                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6239                                 break;
6240                         case RTE_MACVLAN_HASH_MATCH:
6241                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6242                                 break;
6243                         default:
6244                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6245                                 ret = I40E_ERR_PARAM;
6246                                 goto DONE;
6247                         }
6248
6249                         req_list[i].queue_number = 0;
6250
6251                         req_list[i].flags = rte_cpu_to_le_16(flags);
6252                 }
6253
6254                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6255                                                 actual_num, NULL);
6256                 if (ret != I40E_SUCCESS) {
6257                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6258                         goto DONE;
6259                 }
6260                 num += actual_num;
6261         } while (num < total);
6262
6263 DONE:
6264         rte_free(req_list);
6265         return ret;
6266 }
6267
6268 int
6269 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6270                             struct i40e_macvlan_filter *filter,
6271                             int total)
6272 {
6273         int ele_num, ele_buff_size;
6274         int num, actual_num, i;
6275         uint16_t flags;
6276         int ret = I40E_SUCCESS;
6277         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6278         struct i40e_aqc_remove_macvlan_element_data *req_list;
6279
6280         if (filter == NULL  || total == 0)
6281                 return I40E_ERR_PARAM;
6282
6283         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6284         ele_buff_size = hw->aq.asq_buf_size;
6285
6286         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6287         if (req_list == NULL) {
6288                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6289                 return I40E_ERR_NO_MEMORY;
6290         }
6291
6292         num = 0;
6293         do {
6294                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6295                 memset(req_list, 0, ele_buff_size);
6296
6297                 for (i = 0; i < actual_num; i++) {
6298                         rte_memcpy(req_list[i].mac_addr,
6299                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6300                         req_list[i].vlan_tag =
6301                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6302
6303                         switch (filter[num + i].filter_type) {
6304                         case RTE_MAC_PERFECT_MATCH:
6305                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6306                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6307                                 break;
6308                         case RTE_MACVLAN_PERFECT_MATCH:
6309                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6310                                 break;
6311                         case RTE_MAC_HASH_MATCH:
6312                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6313                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6314                                 break;
6315                         case RTE_MACVLAN_HASH_MATCH:
6316                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6317                                 break;
6318                         default:
6319                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6320                                 ret = I40E_ERR_PARAM;
6321                                 goto DONE;
6322                         }
6323                         req_list[i].flags = rte_cpu_to_le_16(flags);
6324                 }
6325
6326                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6327                                                 actual_num, NULL);
6328                 if (ret != I40E_SUCCESS) {
6329                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6330                         goto DONE;
6331                 }
6332                 num += actual_num;
6333         } while (num < total);
6334
6335 DONE:
6336         rte_free(req_list);
6337         return ret;
6338 }
6339
6340 /* Find out specific MAC filter */
6341 static struct i40e_mac_filter *
6342 i40e_find_mac_filter(struct i40e_vsi *vsi,
6343                          struct ether_addr *macaddr)
6344 {
6345         struct i40e_mac_filter *f;
6346
6347         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6348                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6349                         return f;
6350         }
6351
6352         return NULL;
6353 }
6354
6355 static bool
6356 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6357                          uint16_t vlan_id)
6358 {
6359         uint32_t vid_idx, vid_bit;
6360
6361         if (vlan_id > ETH_VLAN_ID_MAX)
6362                 return 0;
6363
6364         vid_idx = I40E_VFTA_IDX(vlan_id);
6365         vid_bit = I40E_VFTA_BIT(vlan_id);
6366
6367         if (vsi->vfta[vid_idx] & vid_bit)
6368                 return 1;
6369         else
6370                 return 0;
6371 }
6372
6373 static void
6374 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6375                        uint16_t vlan_id, bool on)
6376 {
6377         uint32_t vid_idx, vid_bit;
6378
6379         vid_idx = I40E_VFTA_IDX(vlan_id);
6380         vid_bit = I40E_VFTA_BIT(vlan_id);
6381
6382         if (on)
6383                 vsi->vfta[vid_idx] |= vid_bit;
6384         else
6385                 vsi->vfta[vid_idx] &= ~vid_bit;
6386 }
6387
6388 void
6389 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6390                      uint16_t vlan_id, bool on)
6391 {
6392         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6393         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6394         int ret;
6395
6396         if (vlan_id > ETH_VLAN_ID_MAX)
6397                 return;
6398
6399         i40e_store_vlan_filter(vsi, vlan_id, on);
6400
6401         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6402                 return;
6403
6404         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6405
6406         if (on) {
6407                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6408                                        &vlan_data, 1, NULL);
6409                 if (ret != I40E_SUCCESS)
6410                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6411         } else {
6412                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6413                                           &vlan_data, 1, NULL);
6414                 if (ret != I40E_SUCCESS)
6415                         PMD_DRV_LOG(ERR,
6416                                     "Failed to remove vlan filter");
6417         }
6418 }
6419
6420 /**
6421  * Find all vlan options for specific mac addr,
6422  * return with actual vlan found.
6423  */
6424 int
6425 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6426                            struct i40e_macvlan_filter *mv_f,
6427                            int num, struct ether_addr *addr)
6428 {
6429         int i;
6430         uint32_t j, k;
6431
6432         /**
6433          * Not to use i40e_find_vlan_filter to decrease the loop time,
6434          * although the code looks complex.
6435           */
6436         if (num < vsi->vlan_num)
6437                 return I40E_ERR_PARAM;
6438
6439         i = 0;
6440         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6441                 if (vsi->vfta[j]) {
6442                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6443                                 if (vsi->vfta[j] & (1 << k)) {
6444                                         if (i > num - 1) {
6445                                                 PMD_DRV_LOG(ERR,
6446                                                         "vlan number doesn't match");
6447                                                 return I40E_ERR_PARAM;
6448                                         }
6449                                         rte_memcpy(&mv_f[i].macaddr,
6450                                                         addr, ETH_ADDR_LEN);
6451                                         mv_f[i].vlan_id =
6452                                                 j * I40E_UINT32_BIT_SIZE + k;
6453                                         i++;
6454                                 }
6455                         }
6456                 }
6457         }
6458         return I40E_SUCCESS;
6459 }
6460
6461 static inline int
6462 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6463                            struct i40e_macvlan_filter *mv_f,
6464                            int num,
6465                            uint16_t vlan)
6466 {
6467         int i = 0;
6468         struct i40e_mac_filter *f;
6469
6470         if (num < vsi->mac_num)
6471                 return I40E_ERR_PARAM;
6472
6473         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6474                 if (i > num - 1) {
6475                         PMD_DRV_LOG(ERR, "buffer number not match");
6476                         return I40E_ERR_PARAM;
6477                 }
6478                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6479                                 ETH_ADDR_LEN);
6480                 mv_f[i].vlan_id = vlan;
6481                 mv_f[i].filter_type = f->mac_info.filter_type;
6482                 i++;
6483         }
6484
6485         return I40E_SUCCESS;
6486 }
6487
6488 static int
6489 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6490 {
6491         int i, j, num;
6492         struct i40e_mac_filter *f;
6493         struct i40e_macvlan_filter *mv_f;
6494         int ret = I40E_SUCCESS;
6495
6496         if (vsi == NULL || vsi->mac_num == 0)
6497                 return I40E_ERR_PARAM;
6498
6499         /* Case that no vlan is set */
6500         if (vsi->vlan_num == 0)
6501                 num = vsi->mac_num;
6502         else
6503                 num = vsi->mac_num * vsi->vlan_num;
6504
6505         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6506         if (mv_f == NULL) {
6507                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6508                 return I40E_ERR_NO_MEMORY;
6509         }
6510
6511         i = 0;
6512         if (vsi->vlan_num == 0) {
6513                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6514                         rte_memcpy(&mv_f[i].macaddr,
6515                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6516                         mv_f[i].filter_type = f->mac_info.filter_type;
6517                         mv_f[i].vlan_id = 0;
6518                         i++;
6519                 }
6520         } else {
6521                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6522                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6523                                         vsi->vlan_num, &f->mac_info.mac_addr);
6524                         if (ret != I40E_SUCCESS)
6525                                 goto DONE;
6526                         for (j = i; j < i + vsi->vlan_num; j++)
6527                                 mv_f[j].filter_type = f->mac_info.filter_type;
6528                         i += vsi->vlan_num;
6529                 }
6530         }
6531
6532         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6533 DONE:
6534         rte_free(mv_f);
6535
6536         return ret;
6537 }
6538
6539 int
6540 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6541 {
6542         struct i40e_macvlan_filter *mv_f;
6543         int mac_num;
6544         int ret = I40E_SUCCESS;
6545
6546         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6547                 return I40E_ERR_PARAM;
6548
6549         /* If it's already set, just return */
6550         if (i40e_find_vlan_filter(vsi,vlan))
6551                 return I40E_SUCCESS;
6552
6553         mac_num = vsi->mac_num;
6554
6555         if (mac_num == 0) {
6556                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6557                 return I40E_ERR_PARAM;
6558         }
6559
6560         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6561
6562         if (mv_f == NULL) {
6563                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6564                 return I40E_ERR_NO_MEMORY;
6565         }
6566
6567         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6568
6569         if (ret != I40E_SUCCESS)
6570                 goto DONE;
6571
6572         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6573
6574         if (ret != I40E_SUCCESS)
6575                 goto DONE;
6576
6577         i40e_set_vlan_filter(vsi, vlan, 1);
6578
6579         vsi->vlan_num++;
6580         ret = I40E_SUCCESS;
6581 DONE:
6582         rte_free(mv_f);
6583         return ret;
6584 }
6585
6586 int
6587 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6588 {
6589         struct i40e_macvlan_filter *mv_f;
6590         int mac_num;
6591         int ret = I40E_SUCCESS;
6592
6593         /**
6594          * Vlan 0 is the generic filter for untagged packets
6595          * and can't be removed.
6596          */
6597         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6598                 return I40E_ERR_PARAM;
6599
6600         /* If can't find it, just return */
6601         if (!i40e_find_vlan_filter(vsi, vlan))
6602                 return I40E_ERR_PARAM;
6603
6604         mac_num = vsi->mac_num;
6605
6606         if (mac_num == 0) {
6607                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6608                 return I40E_ERR_PARAM;
6609         }
6610
6611         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6612
6613         if (mv_f == NULL) {
6614                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6615                 return I40E_ERR_NO_MEMORY;
6616         }
6617
6618         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6619
6620         if (ret != I40E_SUCCESS)
6621                 goto DONE;
6622
6623         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6624
6625         if (ret != I40E_SUCCESS)
6626                 goto DONE;
6627
6628         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6629         if (vsi->vlan_num == 1) {
6630                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6631                 if (ret != I40E_SUCCESS)
6632                         goto DONE;
6633
6634                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6635                 if (ret != I40E_SUCCESS)
6636                         goto DONE;
6637         }
6638
6639         i40e_set_vlan_filter(vsi, vlan, 0);
6640
6641         vsi->vlan_num--;
6642         ret = I40E_SUCCESS;
6643 DONE:
6644         rte_free(mv_f);
6645         return ret;
6646 }
6647
6648 int
6649 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6650 {
6651         struct i40e_mac_filter *f;
6652         struct i40e_macvlan_filter *mv_f;
6653         int i, vlan_num = 0;
6654         int ret = I40E_SUCCESS;
6655
6656         /* If it's add and we've config it, return */
6657         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6658         if (f != NULL)
6659                 return I40E_SUCCESS;
6660         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6661                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6662
6663                 /**
6664                  * If vlan_num is 0, that's the first time to add mac,
6665                  * set mask for vlan_id 0.
6666                  */
6667                 if (vsi->vlan_num == 0) {
6668                         i40e_set_vlan_filter(vsi, 0, 1);
6669                         vsi->vlan_num = 1;
6670                 }
6671                 vlan_num = vsi->vlan_num;
6672         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6673                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6674                 vlan_num = 1;
6675
6676         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6677         if (mv_f == NULL) {
6678                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6679                 return I40E_ERR_NO_MEMORY;
6680         }
6681
6682         for (i = 0; i < vlan_num; i++) {
6683                 mv_f[i].filter_type = mac_filter->filter_type;
6684                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6685                                 ETH_ADDR_LEN);
6686         }
6687
6688         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6689                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6690                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6691                                         &mac_filter->mac_addr);
6692                 if (ret != I40E_SUCCESS)
6693                         goto DONE;
6694         }
6695
6696         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6697         if (ret != I40E_SUCCESS)
6698                 goto DONE;
6699
6700         /* Add the mac addr into mac list */
6701         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6702         if (f == NULL) {
6703                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6704                 ret = I40E_ERR_NO_MEMORY;
6705                 goto DONE;
6706         }
6707         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6708                         ETH_ADDR_LEN);
6709         f->mac_info.filter_type = mac_filter->filter_type;
6710         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6711         vsi->mac_num++;
6712
6713         ret = I40E_SUCCESS;
6714 DONE:
6715         rte_free(mv_f);
6716
6717         return ret;
6718 }
6719
6720 int
6721 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6722 {
6723         struct i40e_mac_filter *f;
6724         struct i40e_macvlan_filter *mv_f;
6725         int i, vlan_num;
6726         enum rte_mac_filter_type filter_type;
6727         int ret = I40E_SUCCESS;
6728
6729         /* Can't find it, return an error */
6730         f = i40e_find_mac_filter(vsi, addr);
6731         if (f == NULL)
6732                 return I40E_ERR_PARAM;
6733
6734         vlan_num = vsi->vlan_num;
6735         filter_type = f->mac_info.filter_type;
6736         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6737                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6738                 if (vlan_num == 0) {
6739                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6740                         return I40E_ERR_PARAM;
6741                 }
6742         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6743                         filter_type == RTE_MAC_HASH_MATCH)
6744                 vlan_num = 1;
6745
6746         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6747         if (mv_f == NULL) {
6748                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6749                 return I40E_ERR_NO_MEMORY;
6750         }
6751
6752         for (i = 0; i < vlan_num; i++) {
6753                 mv_f[i].filter_type = filter_type;
6754                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6755                                 ETH_ADDR_LEN);
6756         }
6757         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6758                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6759                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6760                 if (ret != I40E_SUCCESS)
6761                         goto DONE;
6762         }
6763
6764         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6765         if (ret != I40E_SUCCESS)
6766                 goto DONE;
6767
6768         /* Remove the mac addr into mac list */
6769         TAILQ_REMOVE(&vsi->mac_list, f, next);
6770         rte_free(f);
6771         vsi->mac_num--;
6772
6773         ret = I40E_SUCCESS;
6774 DONE:
6775         rte_free(mv_f);
6776         return ret;
6777 }
6778
6779 /* Configure hash enable flags for RSS */
6780 uint64_t
6781 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6782 {
6783         uint64_t hena = 0;
6784         int i;
6785
6786         if (!flags)
6787                 return hena;
6788
6789         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6790                 if (flags & (1ULL << i))
6791                         hena |= adapter->pctypes_tbl[i];
6792         }
6793
6794         return hena;
6795 }
6796
6797 /* Parse the hash enable flags */
6798 uint64_t
6799 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6800 {
6801         uint64_t rss_hf = 0;
6802
6803         if (!flags)
6804                 return rss_hf;
6805         int i;
6806
6807         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6808                 if (flags & adapter->pctypes_tbl[i])
6809                         rss_hf |= (1ULL << i);
6810         }
6811         return rss_hf;
6812 }
6813
6814 /* Disable RSS */
6815 static void
6816 i40e_pf_disable_rss(struct i40e_pf *pf)
6817 {
6818         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6819
6820         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6821         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6822         I40E_WRITE_FLUSH(hw);
6823 }
6824
6825 int
6826 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6827 {
6828         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6829         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6830         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6831                            I40E_VFQF_HKEY_MAX_INDEX :
6832                            I40E_PFQF_HKEY_MAX_INDEX;
6833         int ret = 0;
6834
6835         if (!key || key_len == 0) {
6836                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6837                 return 0;
6838         } else if (key_len != (key_idx + 1) *
6839                 sizeof(uint32_t)) {
6840                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6841                 return -EINVAL;
6842         }
6843
6844         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6845                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6846                         (struct i40e_aqc_get_set_rss_key_data *)key;
6847
6848                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6849                 if (ret)
6850                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6851         } else {
6852                 uint32_t *hash_key = (uint32_t *)key;
6853                 uint16_t i;
6854
6855                 if (vsi->type == I40E_VSI_SRIOV) {
6856                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6857                                 I40E_WRITE_REG(
6858                                         hw,
6859                                         I40E_VFQF_HKEY1(i, vsi->user_param),
6860                                         hash_key[i]);
6861
6862                 } else {
6863                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6864                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6865                                                hash_key[i]);
6866                 }
6867                 I40E_WRITE_FLUSH(hw);
6868         }
6869
6870         return ret;
6871 }
6872
6873 static int
6874 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6875 {
6876         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6877         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6878         uint32_t reg;
6879         int ret;
6880
6881         if (!key || !key_len)
6882                 return -EINVAL;
6883
6884         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6885                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6886                         (struct i40e_aqc_get_set_rss_key_data *)key);
6887                 if (ret) {
6888                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6889                         return ret;
6890                 }
6891         } else {
6892                 uint32_t *key_dw = (uint32_t *)key;
6893                 uint16_t i;
6894
6895                 if (vsi->type == I40E_VSI_SRIOV) {
6896                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6897                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6898                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6899                         }
6900                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6901                                    sizeof(uint32_t);
6902                 } else {
6903                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6904                                 reg = I40E_PFQF_HKEY(i);
6905                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6906                         }
6907                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6908                                    sizeof(uint32_t);
6909                 }
6910         }
6911         return 0;
6912 }
6913
6914 static int
6915 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6916 {
6917         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6918         uint64_t hena;
6919         int ret;
6920
6921         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6922                                rss_conf->rss_key_len);
6923         if (ret)
6924                 return ret;
6925
6926         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6927         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6928         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6929         I40E_WRITE_FLUSH(hw);
6930
6931         return 0;
6932 }
6933
6934 static int
6935 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6936                          struct rte_eth_rss_conf *rss_conf)
6937 {
6938         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6940         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6941         uint64_t hena;
6942
6943         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6944         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6945
6946         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6947                 if (rss_hf != 0) /* Enable RSS */
6948                         return -EINVAL;
6949                 return 0; /* Nothing to do */
6950         }
6951         /* RSS enabled */
6952         if (rss_hf == 0) /* Disable RSS */
6953                 return -EINVAL;
6954
6955         return i40e_hw_rss_hash_set(pf, rss_conf);
6956 }
6957
6958 static int
6959 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6960                            struct rte_eth_rss_conf *rss_conf)
6961 {
6962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6964         uint64_t hena;
6965
6966         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6967                          &rss_conf->rss_key_len);
6968
6969         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6970         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6971         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6972
6973         return 0;
6974 }
6975
6976 static int
6977 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6978 {
6979         switch (filter_type) {
6980         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6981                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6982                 break;
6983         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6984                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6985                 break;
6986         case RTE_TUNNEL_FILTER_IMAC_TENID:
6987                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6988                 break;
6989         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6990                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6991                 break;
6992         case ETH_TUNNEL_FILTER_IMAC:
6993                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6994                 break;
6995         case ETH_TUNNEL_FILTER_OIP:
6996                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6997                 break;
6998         case ETH_TUNNEL_FILTER_IIP:
6999                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7000                 break;
7001         default:
7002                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7003                 return -EINVAL;
7004         }
7005
7006         return 0;
7007 }
7008
7009 /* Convert tunnel filter structure */
7010 static int
7011 i40e_tunnel_filter_convert(
7012         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7013         struct i40e_tunnel_filter *tunnel_filter)
7014 {
7015         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7016                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7017         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7018                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7019         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7020         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7021              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7022             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7023                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7024         else
7025                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7026         tunnel_filter->input.flags = cld_filter->element.flags;
7027         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7028         tunnel_filter->queue = cld_filter->element.queue_number;
7029         rte_memcpy(tunnel_filter->input.general_fields,
7030                    cld_filter->general_fields,
7031                    sizeof(cld_filter->general_fields));
7032
7033         return 0;
7034 }
7035
7036 /* Check if there exists the tunnel filter */
7037 struct i40e_tunnel_filter *
7038 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7039                              const struct i40e_tunnel_filter_input *input)
7040 {
7041         int ret;
7042
7043         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7044         if (ret < 0)
7045                 return NULL;
7046
7047         return tunnel_rule->hash_map[ret];
7048 }
7049
7050 /* Add a tunnel filter into the SW list */
7051 static int
7052 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7053                              struct i40e_tunnel_filter *tunnel_filter)
7054 {
7055         struct i40e_tunnel_rule *rule = &pf->tunnel;
7056         int ret;
7057
7058         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7059         if (ret < 0) {
7060                 PMD_DRV_LOG(ERR,
7061                             "Failed to insert tunnel filter to hash table %d!",
7062                             ret);
7063                 return ret;
7064         }
7065         rule->hash_map[ret] = tunnel_filter;
7066
7067         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7068
7069         return 0;
7070 }
7071
7072 /* Delete a tunnel filter from the SW list */
7073 int
7074 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7075                           struct i40e_tunnel_filter_input *input)
7076 {
7077         struct i40e_tunnel_rule *rule = &pf->tunnel;
7078         struct i40e_tunnel_filter *tunnel_filter;
7079         int ret;
7080
7081         ret = rte_hash_del_key(rule->hash_table, input);
7082         if (ret < 0) {
7083                 PMD_DRV_LOG(ERR,
7084                             "Failed to delete tunnel filter to hash table %d!",
7085                             ret);
7086                 return ret;
7087         }
7088         tunnel_filter = rule->hash_map[ret];
7089         rule->hash_map[ret] = NULL;
7090
7091         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7092         rte_free(tunnel_filter);
7093
7094         return 0;
7095 }
7096
7097 int
7098 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7099                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7100                         uint8_t add)
7101 {
7102         uint16_t ip_type;
7103         uint32_t ipv4_addr, ipv4_addr_le;
7104         uint8_t i, tun_type = 0;
7105         /* internal varialbe to convert ipv6 byte order */
7106         uint32_t convert_ipv6[4];
7107         int val, ret = 0;
7108         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7109         struct i40e_vsi *vsi = pf->main_vsi;
7110         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7111         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7112         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7113         struct i40e_tunnel_filter *tunnel, *node;
7114         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7115
7116         cld_filter = rte_zmalloc("tunnel_filter",
7117                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7118         0);
7119
7120         if (NULL == cld_filter) {
7121                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7122                 return -ENOMEM;
7123         }
7124         pfilter = cld_filter;
7125
7126         ether_addr_copy(&tunnel_filter->outer_mac,
7127                         (struct ether_addr *)&pfilter->element.outer_mac);
7128         ether_addr_copy(&tunnel_filter->inner_mac,
7129                         (struct ether_addr *)&pfilter->element.inner_mac);
7130
7131         pfilter->element.inner_vlan =
7132                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7133         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7134                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7135                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7136                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7137                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7138                                 &ipv4_addr_le,
7139                                 sizeof(pfilter->element.ipaddr.v4.data));
7140         } else {
7141                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7142                 for (i = 0; i < 4; i++) {
7143                         convert_ipv6[i] =
7144                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7145                 }
7146                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7147                            &convert_ipv6,
7148                            sizeof(pfilter->element.ipaddr.v6.data));
7149         }
7150
7151         /* check tunneled type */
7152         switch (tunnel_filter->tunnel_type) {
7153         case RTE_TUNNEL_TYPE_VXLAN:
7154                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7155                 break;
7156         case RTE_TUNNEL_TYPE_NVGRE:
7157                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7158                 break;
7159         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7160                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7161                 break;
7162         default:
7163                 /* Other tunnel types is not supported. */
7164                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7165                 rte_free(cld_filter);
7166                 return -EINVAL;
7167         }
7168
7169         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7170                                        &pfilter->element.flags);
7171         if (val < 0) {
7172                 rte_free(cld_filter);
7173                 return -EINVAL;
7174         }
7175
7176         pfilter->element.flags |= rte_cpu_to_le_16(
7177                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7178                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7179         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7180         pfilter->element.queue_number =
7181                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7182
7183         /* Check if there is the filter in SW list */
7184         memset(&check_filter, 0, sizeof(check_filter));
7185         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7186         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7187         if (add && node) {
7188                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7189                 return -EINVAL;
7190         }
7191
7192         if (!add && !node) {
7193                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7194                 return -EINVAL;
7195         }
7196
7197         if (add) {
7198                 ret = i40e_aq_add_cloud_filters(hw,
7199                                         vsi->seid, &cld_filter->element, 1);
7200                 if (ret < 0) {
7201                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7202                         return -ENOTSUP;
7203                 }
7204                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7205                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7206                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7207         } else {
7208                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7209                                                    &cld_filter->element, 1);
7210                 if (ret < 0) {
7211                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7212                         return -ENOTSUP;
7213                 }
7214                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7215         }
7216
7217         rte_free(cld_filter);
7218         return ret;
7219 }
7220
7221 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7222 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7223 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7224 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7225 #define I40E_TR_GRE_KEY_MASK                    0x400
7226 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7227 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7228
7229 static enum
7230 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7231 {
7232         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7233         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7235         enum i40e_status_code status = I40E_SUCCESS;
7236
7237         memset(&filter_replace, 0,
7238                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7239         memset(&filter_replace_buf, 0,
7240                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7241
7242         /* create L1 filter */
7243         filter_replace.old_filter_type =
7244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7245         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7246         filter_replace.tr_bit = 0;
7247
7248         /* Prepare the buffer, 3 entries */
7249         filter_replace_buf.data[0] =
7250                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7251         filter_replace_buf.data[0] |=
7252                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7253         filter_replace_buf.data[2] = 0xFF;
7254         filter_replace_buf.data[3] = 0xFF;
7255         filter_replace_buf.data[4] =
7256                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7257         filter_replace_buf.data[4] |=
7258                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7259         filter_replace_buf.data[7] = 0xF0;
7260         filter_replace_buf.data[8]
7261                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7262         filter_replace_buf.data[8] |=
7263                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7264         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7265                 I40E_TR_GENEVE_KEY_MASK |
7266                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7267         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7268                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7269                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7270
7271         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7272                                                &filter_replace_buf);
7273         return status;
7274 }
7275
7276 static enum
7277 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7278 {
7279         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7280         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7281         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7282         enum i40e_status_code status = I40E_SUCCESS;
7283
7284         /* For MPLSoUDP */
7285         memset(&filter_replace, 0,
7286                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7287         memset(&filter_replace_buf, 0,
7288                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7289         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7290                 I40E_AQC_MIRROR_CLOUD_FILTER;
7291         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7292         filter_replace.new_filter_type =
7293                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7294         /* Prepare the buffer, 2 entries */
7295         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7296         filter_replace_buf.data[0] |=
7297                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7298         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7299         filter_replace_buf.data[4] |=
7300                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7301         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7302                                                &filter_replace_buf);
7303         if (status < 0)
7304                 return status;
7305
7306         /* For MPLSoGRE */
7307         memset(&filter_replace, 0,
7308                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7309         memset(&filter_replace_buf, 0,
7310                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7311
7312         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7313                 I40E_AQC_MIRROR_CLOUD_FILTER;
7314         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7315         filter_replace.new_filter_type =
7316                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7317         /* Prepare the buffer, 2 entries */
7318         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7319         filter_replace_buf.data[0] |=
7320                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7321         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7322         filter_replace_buf.data[4] |=
7323                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7324
7325         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7326                                                &filter_replace_buf);
7327         return status;
7328 }
7329
7330 static enum i40e_status_code
7331 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7332 {
7333         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7334         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7335         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7336         enum i40e_status_code status = I40E_SUCCESS;
7337
7338         /* For GTP-C */
7339         memset(&filter_replace, 0,
7340                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7341         memset(&filter_replace_buf, 0,
7342                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7343         /* create L1 filter */
7344         filter_replace.old_filter_type =
7345                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7346         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7347         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7348                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7349         /* Prepare the buffer, 2 entries */
7350         filter_replace_buf.data[0] =
7351                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7352         filter_replace_buf.data[0] |=
7353                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7354         filter_replace_buf.data[2] = 0xFF;
7355         filter_replace_buf.data[3] = 0xFF;
7356         filter_replace_buf.data[4] =
7357                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7358         filter_replace_buf.data[4] |=
7359                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7360         filter_replace_buf.data[6] = 0xFF;
7361         filter_replace_buf.data[7] = 0xFF;
7362         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7363                                                &filter_replace_buf);
7364         if (status < 0)
7365                 return status;
7366
7367         /* for GTP-U */
7368         memset(&filter_replace, 0,
7369                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7370         memset(&filter_replace_buf, 0,
7371                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7372         /* create L1 filter */
7373         filter_replace.old_filter_type =
7374                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7375         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7376         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7377                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7378         /* Prepare the buffer, 2 entries */
7379         filter_replace_buf.data[0] =
7380                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7381         filter_replace_buf.data[0] |=
7382                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7383         filter_replace_buf.data[2] = 0xFF;
7384         filter_replace_buf.data[3] = 0xFF;
7385         filter_replace_buf.data[4] =
7386                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7387         filter_replace_buf.data[4] |=
7388                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7389         filter_replace_buf.data[6] = 0xFF;
7390         filter_replace_buf.data[7] = 0xFF;
7391
7392         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7393                                                &filter_replace_buf);
7394         return status;
7395 }
7396
7397 static enum
7398 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7399 {
7400         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7401         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7402         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7403         enum i40e_status_code status = I40E_SUCCESS;
7404
7405         /* for GTP-C */
7406         memset(&filter_replace, 0,
7407                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7408         memset(&filter_replace_buf, 0,
7409                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7410         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7411         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7412         filter_replace.new_filter_type =
7413                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7414         /* Prepare the buffer, 2 entries */
7415         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7416         filter_replace_buf.data[0] |=
7417                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7418         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7419         filter_replace_buf.data[4] |=
7420                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7421         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7422                                                &filter_replace_buf);
7423         if (status < 0)
7424                 return status;
7425
7426         /* for GTP-U */
7427         memset(&filter_replace, 0,
7428                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7429         memset(&filter_replace_buf, 0,
7430                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7431         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7432         filter_replace.old_filter_type =
7433                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7434         filter_replace.new_filter_type =
7435                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7436         /* Prepare the buffer, 2 entries */
7437         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7438         filter_replace_buf.data[0] |=
7439                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7440         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7441         filter_replace_buf.data[4] |=
7442                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7443
7444         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7445                                                &filter_replace_buf);
7446         return status;
7447 }
7448
7449 int
7450 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7451                       struct i40e_tunnel_filter_conf *tunnel_filter,
7452                       uint8_t add)
7453 {
7454         uint16_t ip_type;
7455         uint32_t ipv4_addr, ipv4_addr_le;
7456         uint8_t i, tun_type = 0;
7457         /* internal variable to convert ipv6 byte order */
7458         uint32_t convert_ipv6[4];
7459         int val, ret = 0;
7460         struct i40e_pf_vf *vf = NULL;
7461         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7462         struct i40e_vsi *vsi;
7463         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7464         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7465         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7466         struct i40e_tunnel_filter *tunnel, *node;
7467         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7468         uint32_t teid_le;
7469         bool big_buffer = 0;
7470
7471         cld_filter = rte_zmalloc("tunnel_filter",
7472                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7473                          0);
7474
7475         if (cld_filter == NULL) {
7476                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7477                 return -ENOMEM;
7478         }
7479         pfilter = cld_filter;
7480
7481         ether_addr_copy(&tunnel_filter->outer_mac,
7482                         (struct ether_addr *)&pfilter->element.outer_mac);
7483         ether_addr_copy(&tunnel_filter->inner_mac,
7484                         (struct ether_addr *)&pfilter->element.inner_mac);
7485
7486         pfilter->element.inner_vlan =
7487                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7488         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7489                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7490                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7491                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7492                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7493                                 &ipv4_addr_le,
7494                                 sizeof(pfilter->element.ipaddr.v4.data));
7495         } else {
7496                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7497                 for (i = 0; i < 4; i++) {
7498                         convert_ipv6[i] =
7499                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7500                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7501                 }
7502                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7503                            &convert_ipv6,
7504                            sizeof(pfilter->element.ipaddr.v6.data));
7505         }
7506
7507         /* check tunneled type */
7508         switch (tunnel_filter->tunnel_type) {
7509         case I40E_TUNNEL_TYPE_VXLAN:
7510                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7511                 break;
7512         case I40E_TUNNEL_TYPE_NVGRE:
7513                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7514                 break;
7515         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7516                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7517                 break;
7518         case I40E_TUNNEL_TYPE_MPLSoUDP:
7519                 if (!pf->mpls_replace_flag) {
7520                         i40e_replace_mpls_l1_filter(pf);
7521                         i40e_replace_mpls_cloud_filter(pf);
7522                         pf->mpls_replace_flag = 1;
7523                 }
7524                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7525                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7526                         teid_le >> 4;
7527                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7528                         (teid_le & 0xF) << 12;
7529                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7530                         0x40;
7531                 big_buffer = 1;
7532                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7533                 break;
7534         case I40E_TUNNEL_TYPE_MPLSoGRE:
7535                 if (!pf->mpls_replace_flag) {
7536                         i40e_replace_mpls_l1_filter(pf);
7537                         i40e_replace_mpls_cloud_filter(pf);
7538                         pf->mpls_replace_flag = 1;
7539                 }
7540                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7541                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7542                         teid_le >> 4;
7543                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7544                         (teid_le & 0xF) << 12;
7545                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7546                         0x0;
7547                 big_buffer = 1;
7548                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7549                 break;
7550         case I40E_TUNNEL_TYPE_GTPC:
7551                 if (!pf->gtp_replace_flag) {
7552                         i40e_replace_gtp_l1_filter(pf);
7553                         i40e_replace_gtp_cloud_filter(pf);
7554                         pf->gtp_replace_flag = 1;
7555                 }
7556                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7557                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7558                         (teid_le >> 16) & 0xFFFF;
7559                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7560                         teid_le & 0xFFFF;
7561                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7562                         0x0;
7563                 big_buffer = 1;
7564                 break;
7565         case I40E_TUNNEL_TYPE_GTPU:
7566                 if (!pf->gtp_replace_flag) {
7567                         i40e_replace_gtp_l1_filter(pf);
7568                         i40e_replace_gtp_cloud_filter(pf);
7569                         pf->gtp_replace_flag = 1;
7570                 }
7571                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7572                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7573                         (teid_le >> 16) & 0xFFFF;
7574                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7575                         teid_le & 0xFFFF;
7576                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7577                         0x0;
7578                 big_buffer = 1;
7579                 break;
7580         case I40E_TUNNEL_TYPE_QINQ:
7581                 if (!pf->qinq_replace_flag) {
7582                         ret = i40e_cloud_filter_qinq_create(pf);
7583                         if (ret < 0)
7584                                 PMD_DRV_LOG(DEBUG,
7585                                             "QinQ tunnel filter already created.");
7586                         pf->qinq_replace_flag = 1;
7587                 }
7588                 /*      Add in the General fields the values of
7589                  *      the Outer and Inner VLAN
7590                  *      Big Buffer should be set, see changes in
7591                  *      i40e_aq_add_cloud_filters
7592                  */
7593                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7594                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7595                 big_buffer = 1;
7596                 break;
7597         default:
7598                 /* Other tunnel types is not supported. */
7599                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7600                 rte_free(cld_filter);
7601                 return -EINVAL;
7602         }
7603
7604         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7605                 pfilter->element.flags =
7606                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7607         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7608                 pfilter->element.flags =
7609                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7610         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7611                 pfilter->element.flags =
7612                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7613         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7614                 pfilter->element.flags =
7615                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7616         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7617                 pfilter->element.flags |=
7618                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7619         else {
7620                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7621                                                 &pfilter->element.flags);
7622                 if (val < 0) {
7623                         rte_free(cld_filter);
7624                         return -EINVAL;
7625                 }
7626         }
7627
7628         pfilter->element.flags |= rte_cpu_to_le_16(
7629                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7630                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7631         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7632         pfilter->element.queue_number =
7633                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7634
7635         if (!tunnel_filter->is_to_vf)
7636                 vsi = pf->main_vsi;
7637         else {
7638                 if (tunnel_filter->vf_id >= pf->vf_num) {
7639                         PMD_DRV_LOG(ERR, "Invalid argument.");
7640                         return -EINVAL;
7641                 }
7642                 vf = &pf->vfs[tunnel_filter->vf_id];
7643                 vsi = vf->vsi;
7644         }
7645
7646         /* Check if there is the filter in SW list */
7647         memset(&check_filter, 0, sizeof(check_filter));
7648         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7649         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7650         check_filter.vf_id = tunnel_filter->vf_id;
7651         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7652         if (add && node) {
7653                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7654                 return -EINVAL;
7655         }
7656
7657         if (!add && !node) {
7658                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7659                 return -EINVAL;
7660         }
7661
7662         if (add) {
7663                 if (big_buffer)
7664                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7665                                                    vsi->seid, cld_filter, 1);
7666                 else
7667                         ret = i40e_aq_add_cloud_filters(hw,
7668                                         vsi->seid, &cld_filter->element, 1);
7669                 if (ret < 0) {
7670                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7671                         return -ENOTSUP;
7672                 }
7673                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7674                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7675                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7676         } else {
7677                 if (big_buffer)
7678                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7679                                 hw, vsi->seid, cld_filter, 1);
7680                 else
7681                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7682                                                    &cld_filter->element, 1);
7683                 if (ret < 0) {
7684                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7685                         return -ENOTSUP;
7686                 }
7687                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7688         }
7689
7690         rte_free(cld_filter);
7691         return ret;
7692 }
7693
7694 static int
7695 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7696 {
7697         uint8_t i;
7698
7699         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7700                 if (pf->vxlan_ports[i] == port)
7701                         return i;
7702         }
7703
7704         return -1;
7705 }
7706
7707 static int
7708 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7709 {
7710         int  idx, ret;
7711         uint8_t filter_idx;
7712         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7713
7714         idx = i40e_get_vxlan_port_idx(pf, port);
7715
7716         /* Check if port already exists */
7717         if (idx >= 0) {
7718                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7719                 return -EINVAL;
7720         }
7721
7722         /* Now check if there is space to add the new port */
7723         idx = i40e_get_vxlan_port_idx(pf, 0);
7724         if (idx < 0) {
7725                 PMD_DRV_LOG(ERR,
7726                         "Maximum number of UDP ports reached, not adding port %d",
7727                         port);
7728                 return -ENOSPC;
7729         }
7730
7731         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7732                                         &filter_idx, NULL);
7733         if (ret < 0) {
7734                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7735                 return -1;
7736         }
7737
7738         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7739                          port,  filter_idx);
7740
7741         /* New port: add it and mark its index in the bitmap */
7742         pf->vxlan_ports[idx] = port;
7743         pf->vxlan_bitmap |= (1 << idx);
7744
7745         if (!(pf->flags & I40E_FLAG_VXLAN))
7746                 pf->flags |= I40E_FLAG_VXLAN;
7747
7748         return 0;
7749 }
7750
7751 static int
7752 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7753 {
7754         int idx;
7755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7756
7757         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7758                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7759                 return -EINVAL;
7760         }
7761
7762         idx = i40e_get_vxlan_port_idx(pf, port);
7763
7764         if (idx < 0) {
7765                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7766                 return -EINVAL;
7767         }
7768
7769         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7770                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7771                 return -1;
7772         }
7773
7774         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7775                         port, idx);
7776
7777         pf->vxlan_ports[idx] = 0;
7778         pf->vxlan_bitmap &= ~(1 << idx);
7779
7780         if (!pf->vxlan_bitmap)
7781                 pf->flags &= ~I40E_FLAG_VXLAN;
7782
7783         return 0;
7784 }
7785
7786 /* Add UDP tunneling port */
7787 static int
7788 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7789                              struct rte_eth_udp_tunnel *udp_tunnel)
7790 {
7791         int ret = 0;
7792         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7793
7794         if (udp_tunnel == NULL)
7795                 return -EINVAL;
7796
7797         switch (udp_tunnel->prot_type) {
7798         case RTE_TUNNEL_TYPE_VXLAN:
7799                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7800                 break;
7801
7802         case RTE_TUNNEL_TYPE_GENEVE:
7803         case RTE_TUNNEL_TYPE_TEREDO:
7804                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7805                 ret = -1;
7806                 break;
7807
7808         default:
7809                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7810                 ret = -1;
7811                 break;
7812         }
7813
7814         return ret;
7815 }
7816
7817 /* Remove UDP tunneling port */
7818 static int
7819 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7820                              struct rte_eth_udp_tunnel *udp_tunnel)
7821 {
7822         int ret = 0;
7823         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7824
7825         if (udp_tunnel == NULL)
7826                 return -EINVAL;
7827
7828         switch (udp_tunnel->prot_type) {
7829         case RTE_TUNNEL_TYPE_VXLAN:
7830                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7831                 break;
7832         case RTE_TUNNEL_TYPE_GENEVE:
7833         case RTE_TUNNEL_TYPE_TEREDO:
7834                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7835                 ret = -1;
7836                 break;
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -1;
7840                 break;
7841         }
7842
7843         return ret;
7844 }
7845
7846 /* Calculate the maximum number of contiguous PF queues that are configured */
7847 static int
7848 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7849 {
7850         struct rte_eth_dev_data *data = pf->dev_data;
7851         int i, num;
7852         struct i40e_rx_queue *rxq;
7853
7854         num = 0;
7855         for (i = 0; i < pf->lan_nb_qps; i++) {
7856                 rxq = data->rx_queues[i];
7857                 if (rxq && rxq->q_set)
7858                         num++;
7859                 else
7860                         break;
7861         }
7862
7863         return num;
7864 }
7865
7866 /* Configure RSS */
7867 static int
7868 i40e_pf_config_rss(struct i40e_pf *pf)
7869 {
7870         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7871         struct rte_eth_rss_conf rss_conf;
7872         uint32_t i, lut = 0;
7873         uint16_t j, num;
7874
7875         /*
7876          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7877          * It's necessary to calculate the actual PF queues that are configured.
7878          */
7879         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7880                 num = i40e_pf_calc_configured_queues_num(pf);
7881         else
7882                 num = pf->dev_data->nb_rx_queues;
7883
7884         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7885         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7886                         num);
7887
7888         if (num == 0) {
7889                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7890                 return -ENOTSUP;
7891         }
7892
7893         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7894                 if (j == num)
7895                         j = 0;
7896                 lut = (lut << 8) | (j & ((0x1 <<
7897                         hw->func_caps.rss_table_entry_width) - 1));
7898                 if ((i & 3) == 3)
7899                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7900         }
7901
7902         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7903         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7904                 i40e_pf_disable_rss(pf);
7905                 return 0;
7906         }
7907         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7908                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7909                 /* Random default keys */
7910                 static uint32_t rss_key_default[] = {0x6b793944,
7911                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7912                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7913                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7914
7915                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7916                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7917                                                         sizeof(uint32_t);
7918         }
7919
7920         return i40e_hw_rss_hash_set(pf, &rss_conf);
7921 }
7922
7923 static int
7924 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7925                                struct rte_eth_tunnel_filter_conf *filter)
7926 {
7927         if (pf == NULL || filter == NULL) {
7928                 PMD_DRV_LOG(ERR, "Invalid parameter");
7929                 return -EINVAL;
7930         }
7931
7932         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7933                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7934                 return -EINVAL;
7935         }
7936
7937         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7938                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7939                 return -EINVAL;
7940         }
7941
7942         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7943                 (is_zero_ether_addr(&filter->outer_mac))) {
7944                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7945                 return -EINVAL;
7946         }
7947
7948         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7949                 (is_zero_ether_addr(&filter->inner_mac))) {
7950                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7951                 return -EINVAL;
7952         }
7953
7954         return 0;
7955 }
7956
7957 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7958 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7959 static int
7960 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7961 {
7962         uint32_t val, reg;
7963         int ret = -EINVAL;
7964
7965         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7966         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7967
7968         if (len == 3) {
7969                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7970         } else if (len == 4) {
7971                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7972         } else {
7973                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7974                 return ret;
7975         }
7976
7977         if (reg != val) {
7978                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7979                                                    reg, NULL);
7980                 if (ret != 0)
7981                         return ret;
7982         } else {
7983                 ret = 0;
7984         }
7985         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7986                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7987
7988         return ret;
7989 }
7990
7991 static int
7992 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7993 {
7994         int ret = -EINVAL;
7995
7996         if (!hw || !cfg)
7997                 return -EINVAL;
7998
7999         switch (cfg->cfg_type) {
8000         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8001                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8002                 break;
8003         default:
8004                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8005                 break;
8006         }
8007
8008         return ret;
8009 }
8010
8011 static int
8012 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8013                                enum rte_filter_op filter_op,
8014                                void *arg)
8015 {
8016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8017         int ret = I40E_ERR_PARAM;
8018
8019         switch (filter_op) {
8020         case RTE_ETH_FILTER_SET:
8021                 ret = i40e_dev_global_config_set(hw,
8022                         (struct rte_eth_global_cfg *)arg);
8023                 break;
8024         default:
8025                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8026                 break;
8027         }
8028
8029         return ret;
8030 }
8031
8032 static int
8033 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8034                           enum rte_filter_op filter_op,
8035                           void *arg)
8036 {
8037         struct rte_eth_tunnel_filter_conf *filter;
8038         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8039         int ret = I40E_SUCCESS;
8040
8041         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8042
8043         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8044                 return I40E_ERR_PARAM;
8045
8046         switch (filter_op) {
8047         case RTE_ETH_FILTER_NOP:
8048                 if (!(pf->flags & I40E_FLAG_VXLAN))
8049                         ret = I40E_NOT_SUPPORTED;
8050                 break;
8051         case RTE_ETH_FILTER_ADD:
8052                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8053                 break;
8054         case RTE_ETH_FILTER_DELETE:
8055                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8056                 break;
8057         default:
8058                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8059                 ret = I40E_ERR_PARAM;
8060                 break;
8061         }
8062
8063         return ret;
8064 }
8065
8066 static int
8067 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8068 {
8069         int ret = 0;
8070         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8071
8072         /* RSS setup */
8073         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8074                 ret = i40e_pf_config_rss(pf);
8075         else
8076                 i40e_pf_disable_rss(pf);
8077
8078         return ret;
8079 }
8080
8081 /* Get the symmetric hash enable configurations per port */
8082 static void
8083 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8084 {
8085         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8086
8087         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8088 }
8089
8090 /* Set the symmetric hash enable configurations per port */
8091 static void
8092 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8093 {
8094         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8095
8096         if (enable > 0) {
8097                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8098                         PMD_DRV_LOG(INFO,
8099                                 "Symmetric hash has already been enabled");
8100                         return;
8101                 }
8102                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8103         } else {
8104                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8105                         PMD_DRV_LOG(INFO,
8106                                 "Symmetric hash has already been disabled");
8107                         return;
8108                 }
8109                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8110         }
8111         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8112         I40E_WRITE_FLUSH(hw);
8113 }
8114
8115 /*
8116  * Get global configurations of hash function type and symmetric hash enable
8117  * per flow type (pctype). Note that global configuration means it affects all
8118  * the ports on the same NIC.
8119  */
8120 static int
8121 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8122                                    struct rte_eth_hash_global_conf *g_cfg)
8123 {
8124         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8125         uint32_t reg;
8126         uint16_t i, j;
8127
8128         memset(g_cfg, 0, sizeof(*g_cfg));
8129         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8130         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8131                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8132         else
8133                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8134         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8135                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8136
8137         /*
8138          * We work only with lowest 32 bits which is not correct, but to work
8139          * properly the valid_bit_mask size should be increased up to 64 bits
8140          * and this will brake ABI. This modification will be done in next
8141          * release
8142          */
8143         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8144
8145         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8146                 if (!adapter->pctypes_tbl[i])
8147                         continue;
8148                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8149                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8150                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8151                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8152                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8153                                         g_cfg->sym_hash_enable_mask[0] |=
8154                                                                 (1UL << i);
8155                                 }
8156                         }
8157                 }
8158         }
8159
8160         return 0;
8161 }
8162
8163 static int
8164 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8165                               const struct rte_eth_hash_global_conf *g_cfg)
8166 {
8167         uint32_t i;
8168         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8169
8170         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8171                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8172                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8173                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8174                                                 g_cfg->hash_func);
8175                 return -EINVAL;
8176         }
8177
8178         /*
8179          * As i40e supports less than 32 flow types, only first 32 bits need to
8180          * be checked.
8181          */
8182         mask0 = g_cfg->valid_bit_mask[0];
8183         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8184                 if (i == 0) {
8185                         /* Check if any unsupported flow type configured */
8186                         if ((mask0 | i40e_mask) ^ i40e_mask)
8187                                 goto mask_err;
8188                 } else {
8189                         if (g_cfg->valid_bit_mask[i])
8190                                 goto mask_err;
8191                 }
8192         }
8193
8194         return 0;
8195
8196 mask_err:
8197         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8198
8199         return -EINVAL;
8200 }
8201
8202 /*
8203  * Set global configurations of hash function type and symmetric hash enable
8204  * per flow type (pctype). Note any modifying global configuration will affect
8205  * all the ports on the same NIC.
8206  */
8207 static int
8208 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8209                                    struct rte_eth_hash_global_conf *g_cfg)
8210 {
8211         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8212         int ret;
8213         uint16_t i, j;
8214         uint32_t reg;
8215         /*
8216          * We work only with lowest 32 bits which is not correct, but to work
8217          * properly the valid_bit_mask size should be increased up to 64 bits
8218          * and this will brake ABI. This modification will be done in next
8219          * release
8220          */
8221         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8222                                         (uint32_t)adapter->flow_types_mask;
8223
8224         /* Check the input parameters */
8225         ret = i40e_hash_global_config_check(adapter, g_cfg);
8226         if (ret < 0)
8227                 return ret;
8228
8229         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8230                 if (mask0 & (1UL << i)) {
8231                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8232                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8233
8234                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8235                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8236                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8237                                         i40e_write_rx_ctl(hw,
8238                                                           I40E_GLQF_HSYM(j),
8239                                                           reg);
8240                         }
8241                 }
8242         }
8243
8244         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8245         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8246                 /* Toeplitz */
8247                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8248                         PMD_DRV_LOG(DEBUG,
8249                                 "Hash function already set to Toeplitz");
8250                         goto out;
8251                 }
8252                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8253         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8254                 /* Simple XOR */
8255                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8256                         PMD_DRV_LOG(DEBUG,
8257                                 "Hash function already set to Simple XOR");
8258                         goto out;
8259                 }
8260                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8261         } else
8262                 /* Use the default, and keep it as it is */
8263                 goto out;
8264
8265         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8266
8267 out:
8268         I40E_WRITE_FLUSH(hw);
8269
8270         return 0;
8271 }
8272
8273 /**
8274  * Valid input sets for hash and flow director filters per PCTYPE
8275  */
8276 static uint64_t
8277 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8278                 enum rte_filter_type filter)
8279 {
8280         uint64_t valid;
8281
8282         static const uint64_t valid_hash_inset_table[] = {
8283                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8284                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8285                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8286                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8287                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8288                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8289                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8290                         I40E_INSET_FLEX_PAYLOAD,
8291                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8292                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8293                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8295                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8296                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8299                         I40E_INSET_FLEX_PAYLOAD,
8300                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8301                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8302                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8303                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8304                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8305                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8306                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8307                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8308                         I40E_INSET_FLEX_PAYLOAD,
8309                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8310                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8311                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8312                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8313                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8314                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8315                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8316                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8317                         I40E_INSET_FLEX_PAYLOAD,
8318                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8319                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8320                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8321                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8322                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8323                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8324                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8325                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8326                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8327                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8328                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8329                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8330                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8331                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8332                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8333                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8334                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8335                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8336                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8337                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8338                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8340                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8341                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8342                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8343                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8344                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8345                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8346                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8347                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8348                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8349                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8350                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8351                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8352                         I40E_INSET_FLEX_PAYLOAD,
8353                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8354                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8355                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8356                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8357                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8358                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8359                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8360                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8361                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8362                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8363                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8364                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8365                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8366                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8367                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8368                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8369                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8370                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8371                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8372                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8373                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8374                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8375                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8376                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8377                         I40E_INSET_FLEX_PAYLOAD,
8378                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8379                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8380                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8381                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8382                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8383                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8384                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8385                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8386                         I40E_INSET_FLEX_PAYLOAD,
8387                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8388                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8389                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8390                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8391                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8392                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8393                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8394                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8395                         I40E_INSET_FLEX_PAYLOAD,
8396                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8397                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8398                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8399                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8400                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8401                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8402                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8403                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8404                         I40E_INSET_FLEX_PAYLOAD,
8405                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8406                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8407                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8408                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8409                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8410                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8411                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8412                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8413                         I40E_INSET_FLEX_PAYLOAD,
8414                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8415                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8416                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8417                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8418                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8419                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8420                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8421                         I40E_INSET_FLEX_PAYLOAD,
8422                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8423                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8424                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8425                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8426                         I40E_INSET_FLEX_PAYLOAD,
8427         };
8428
8429         /**
8430          * Flow director supports only fields defined in
8431          * union rte_eth_fdir_flow.
8432          */
8433         static const uint64_t valid_fdir_inset_table[] = {
8434                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8435                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8436                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8437                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8438                 I40E_INSET_IPV4_TTL,
8439                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8440                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8441                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8442                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8443                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8444                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8445                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8446                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8447                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8448                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8449                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8450                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8451                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8452                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8453                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8454                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8455                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8456                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8457                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8458                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8459                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8460                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8461                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8462                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8463                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8464                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8465                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8466                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8467                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8468                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8469                 I40E_INSET_SCTP_VT,
8470                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8471                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8472                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8473                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8474                 I40E_INSET_IPV4_TTL,
8475                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8476                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8477                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8478                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8479                 I40E_INSET_IPV6_HOP_LIMIT,
8480                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8481                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8482                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8483                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8484                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8485                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8486                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8487                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8488                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8489                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8490                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8491                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8492                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8493                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8494                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8495                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8496                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8497                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8498                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8499                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8500                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8501                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8502                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8503                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8504                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8505                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8506                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8507                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8508                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8509                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8510                 I40E_INSET_SCTP_VT,
8511                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8512                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8513                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8514                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8515                 I40E_INSET_IPV6_HOP_LIMIT,
8516                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8517                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8518                 I40E_INSET_LAST_ETHER_TYPE,
8519         };
8520
8521         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8522                 return 0;
8523         if (filter == RTE_ETH_FILTER_HASH)
8524                 valid = valid_hash_inset_table[pctype];
8525         else
8526                 valid = valid_fdir_inset_table[pctype];
8527
8528         return valid;
8529 }
8530
8531 /**
8532  * Validate if the input set is allowed for a specific PCTYPE
8533  */
8534 int
8535 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8536                 enum rte_filter_type filter, uint64_t inset)
8537 {
8538         uint64_t valid;
8539
8540         valid = i40e_get_valid_input_set(pctype, filter);
8541         if (inset & (~valid))
8542                 return -EINVAL;
8543
8544         return 0;
8545 }
8546
8547 /* default input set fields combination per pctype */
8548 uint64_t
8549 i40e_get_default_input_set(uint16_t pctype)
8550 {
8551         static const uint64_t default_inset_table[] = {
8552                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8553                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8554                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8555                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8556                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8557                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8558                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8559                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8560                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8561                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8562                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8563                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8564                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8565                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8566                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8567                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8568                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8569                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8570                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8571                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8572                         I40E_INSET_SCTP_VT,
8573                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8574                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8575                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8576                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8577                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8578                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8579                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8580                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8581                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8582                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8583                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8584                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8585                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8586                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8587                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8588                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8589                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8590                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8591                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8592                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8593                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8594                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8595                         I40E_INSET_SCTP_VT,
8596                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8597                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8598                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8599                         I40E_INSET_LAST_ETHER_TYPE,
8600         };
8601
8602         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8603                 return 0;
8604
8605         return default_inset_table[pctype];
8606 }
8607
8608 /**
8609  * Parse the input set from index to logical bit masks
8610  */
8611 static int
8612 i40e_parse_input_set(uint64_t *inset,
8613                      enum i40e_filter_pctype pctype,
8614                      enum rte_eth_input_set_field *field,
8615                      uint16_t size)
8616 {
8617         uint16_t i, j;
8618         int ret = -EINVAL;
8619
8620         static const struct {
8621                 enum rte_eth_input_set_field field;
8622                 uint64_t inset;
8623         } inset_convert_table[] = {
8624                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8625                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8626                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8627                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8628                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8629                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8630                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8631                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8632                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8633                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8634                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8635                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8636                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8637                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8638                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8639                         I40E_INSET_IPV6_NEXT_HDR},
8640                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8641                         I40E_INSET_IPV6_HOP_LIMIT},
8642                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8643                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8644                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8645                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8646                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8647                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8648                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8649                         I40E_INSET_SCTP_VT},
8650                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8651                         I40E_INSET_TUNNEL_DMAC},
8652                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8653                         I40E_INSET_VLAN_TUNNEL},
8654                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8655                         I40E_INSET_TUNNEL_ID},
8656                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8657                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8658                         I40E_INSET_FLEX_PAYLOAD_W1},
8659                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8660                         I40E_INSET_FLEX_PAYLOAD_W2},
8661                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8662                         I40E_INSET_FLEX_PAYLOAD_W3},
8663                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8664                         I40E_INSET_FLEX_PAYLOAD_W4},
8665                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8666                         I40E_INSET_FLEX_PAYLOAD_W5},
8667                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8668                         I40E_INSET_FLEX_PAYLOAD_W6},
8669                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8670                         I40E_INSET_FLEX_PAYLOAD_W7},
8671                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8672                         I40E_INSET_FLEX_PAYLOAD_W8},
8673         };
8674
8675         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8676                 return ret;
8677
8678         /* Only one item allowed for default or all */
8679         if (size == 1) {
8680                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8681                         *inset = i40e_get_default_input_set(pctype);
8682                         return 0;
8683                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8684                         *inset = I40E_INSET_NONE;
8685                         return 0;
8686                 }
8687         }
8688
8689         for (i = 0, *inset = 0; i < size; i++) {
8690                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8691                         if (field[i] == inset_convert_table[j].field) {
8692                                 *inset |= inset_convert_table[j].inset;
8693                                 break;
8694                         }
8695                 }
8696
8697                 /* It contains unsupported input set, return immediately */
8698                 if (j == RTE_DIM(inset_convert_table))
8699                         return ret;
8700         }
8701
8702         return 0;
8703 }
8704
8705 /**
8706  * Translate the input set from bit masks to register aware bit masks
8707  * and vice versa
8708  */
8709 uint64_t
8710 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8711 {
8712         uint64_t val = 0;
8713         uint16_t i;
8714
8715         struct inset_map {
8716                 uint64_t inset;
8717                 uint64_t inset_reg;
8718         };
8719
8720         static const struct inset_map inset_map_common[] = {
8721                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8722                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8723                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8724                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8725                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8726                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8727                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8728                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8729                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8730                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8731                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8732                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8733                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8734                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8735                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8736                 {I40E_INSET_TUNNEL_DMAC,
8737                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8738                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8739                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8740                 {I40E_INSET_TUNNEL_SRC_PORT,
8741                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8742                 {I40E_INSET_TUNNEL_DST_PORT,
8743                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8744                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8745                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8746                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8747                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8748                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8749                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8750                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8751                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8752                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8753         };
8754
8755     /* some different registers map in x722*/
8756         static const struct inset_map inset_map_diff_x722[] = {
8757                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8758                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8759                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8760                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8761         };
8762
8763         static const struct inset_map inset_map_diff_not_x722[] = {
8764                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8765                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8766                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8767                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8768         };
8769
8770         if (input == 0)
8771                 return val;
8772
8773         /* Translate input set to register aware inset */
8774         if (type == I40E_MAC_X722) {
8775                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8776                         if (input & inset_map_diff_x722[i].inset)
8777                                 val |= inset_map_diff_x722[i].inset_reg;
8778                 }
8779         } else {
8780                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8781                         if (input & inset_map_diff_not_x722[i].inset)
8782                                 val |= inset_map_diff_not_x722[i].inset_reg;
8783                 }
8784         }
8785
8786         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8787                 if (input & inset_map_common[i].inset)
8788                         val |= inset_map_common[i].inset_reg;
8789         }
8790
8791         return val;
8792 }
8793
8794 int
8795 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8796 {
8797         uint8_t i, idx = 0;
8798         uint64_t inset_need_mask = inset;
8799
8800         static const struct {
8801                 uint64_t inset;
8802                 uint32_t mask;
8803         } inset_mask_map[] = {
8804                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8805                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8806                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8807                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8808                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8809                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8810                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8811                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8812         };
8813
8814         if (!inset || !mask || !nb_elem)
8815                 return 0;
8816
8817         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8818                 /* Clear the inset bit, if no MASK is required,
8819                  * for example proto + ttl
8820                  */
8821                 if ((inset & inset_mask_map[i].inset) ==
8822                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8823                         inset_need_mask &= ~inset_mask_map[i].inset;
8824                 if (!inset_need_mask)
8825                         return 0;
8826         }
8827         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8828                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8829                     inset_mask_map[i].inset) {
8830                         if (idx >= nb_elem) {
8831                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8832                                 return -EINVAL;
8833                         }
8834                         mask[idx] = inset_mask_map[i].mask;
8835                         idx++;
8836                 }
8837         }
8838
8839         return idx;
8840 }
8841
8842 void
8843 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8844 {
8845         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8846
8847         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8848         if (reg != val)
8849                 i40e_write_rx_ctl(hw, addr, val);
8850         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8851                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8852 }
8853
8854 static void
8855 i40e_filter_input_set_init(struct i40e_pf *pf)
8856 {
8857         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8858         enum i40e_filter_pctype pctype;
8859         uint64_t input_set, inset_reg;
8860         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8861         int num, i;
8862         uint16_t flow_type;
8863
8864         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8865              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8866                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8867
8868                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8869                         continue;
8870
8871                 input_set = i40e_get_default_input_set(pctype);
8872
8873                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8874                                                    I40E_INSET_MASK_NUM_REG);
8875                 if (num < 0)
8876                         return;
8877                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8878                                         input_set);
8879
8880                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8881                                       (uint32_t)(inset_reg & UINT32_MAX));
8882                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8883                                      (uint32_t)((inset_reg >>
8884                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8885                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8886                                       (uint32_t)(inset_reg & UINT32_MAX));
8887                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8888                                      (uint32_t)((inset_reg >>
8889                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8890
8891                 for (i = 0; i < num; i++) {
8892                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8893                                              mask_reg[i]);
8894                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8895                                              mask_reg[i]);
8896                 }
8897                 /*clear unused mask registers of the pctype */
8898                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8899                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8900                                              0);
8901                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8902                                              0);
8903                 }
8904                 I40E_WRITE_FLUSH(hw);
8905
8906                 /* store the default input set */
8907                 pf->hash_input_set[pctype] = input_set;
8908                 pf->fdir.input_set[pctype] = input_set;
8909         }
8910 }
8911
8912 int
8913 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8914                          struct rte_eth_input_set_conf *conf)
8915 {
8916         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8917         enum i40e_filter_pctype pctype;
8918         uint64_t input_set, inset_reg = 0;
8919         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8920         int ret, i, num;
8921
8922         if (!conf) {
8923                 PMD_DRV_LOG(ERR, "Invalid pointer");
8924                 return -EFAULT;
8925         }
8926         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8927             conf->op != RTE_ETH_INPUT_SET_ADD) {
8928                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8929                 return -EINVAL;
8930         }
8931
8932         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8933         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8934                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8935                 return -EINVAL;
8936         }
8937
8938         if (hw->mac.type == I40E_MAC_X722) {
8939                 /* get translated pctype value in fd pctype register */
8940                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8941                         I40E_GLQF_FD_PCTYPES((int)pctype));
8942         }
8943
8944         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8945                                    conf->inset_size);
8946         if (ret) {
8947                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8948                 return -EINVAL;
8949         }
8950
8951         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8952                 /* get inset value in register */
8953                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8954                 inset_reg <<= I40E_32_BIT_WIDTH;
8955                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8956                 input_set |= pf->hash_input_set[pctype];
8957         }
8958         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8959                                            I40E_INSET_MASK_NUM_REG);
8960         if (num < 0)
8961                 return -EINVAL;
8962
8963         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8964
8965         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8966                               (uint32_t)(inset_reg & UINT32_MAX));
8967         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8968                              (uint32_t)((inset_reg >>
8969                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8970
8971         for (i = 0; i < num; i++)
8972                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8973                                      mask_reg[i]);
8974         /*clear unused mask registers of the pctype */
8975         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8976                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8977                                      0);
8978         I40E_WRITE_FLUSH(hw);
8979
8980         pf->hash_input_set[pctype] = input_set;
8981         return 0;
8982 }
8983
8984 int
8985 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8986                          struct rte_eth_input_set_conf *conf)
8987 {
8988         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8989         enum i40e_filter_pctype pctype;
8990         uint64_t input_set, inset_reg = 0;
8991         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8992         int ret, i, num;
8993
8994         if (!hw || !conf) {
8995                 PMD_DRV_LOG(ERR, "Invalid pointer");
8996                 return -EFAULT;
8997         }
8998         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8999             conf->op != RTE_ETH_INPUT_SET_ADD) {
9000                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9001                 return -EINVAL;
9002         }
9003
9004         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9005
9006         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9007                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9008                 return -EINVAL;
9009         }
9010
9011         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9012                                    conf->inset_size);
9013         if (ret) {
9014                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9015                 return -EINVAL;
9016         }
9017
9018         /* get inset value in register */
9019         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9020         inset_reg <<= I40E_32_BIT_WIDTH;
9021         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9022
9023         /* Can not change the inset reg for flex payload for fdir,
9024          * it is done by writing I40E_PRTQF_FD_FLXINSET
9025          * in i40e_set_flex_mask_on_pctype.
9026          */
9027         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9028                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9029         else
9030                 input_set |= pf->fdir.input_set[pctype];
9031         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9032                                            I40E_INSET_MASK_NUM_REG);
9033         if (num < 0)
9034                 return -EINVAL;
9035
9036         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9037
9038         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9039                               (uint32_t)(inset_reg & UINT32_MAX));
9040         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9041                              (uint32_t)((inset_reg >>
9042                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9043
9044         for (i = 0; i < num; i++)
9045                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9046                                      mask_reg[i]);
9047         /*clear unused mask registers of the pctype */
9048         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9049                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9050                                      0);
9051         I40E_WRITE_FLUSH(hw);
9052
9053         pf->fdir.input_set[pctype] = input_set;
9054         return 0;
9055 }
9056
9057 static int
9058 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9059 {
9060         int ret = 0;
9061
9062         if (!hw || !info) {
9063                 PMD_DRV_LOG(ERR, "Invalid pointer");
9064                 return -EFAULT;
9065         }
9066
9067         switch (info->info_type) {
9068         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9069                 i40e_get_symmetric_hash_enable_per_port(hw,
9070                                         &(info->info.enable));
9071                 break;
9072         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9073                 ret = i40e_get_hash_filter_global_config(hw,
9074                                 &(info->info.global_conf));
9075                 break;
9076         default:
9077                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9078                                                         info->info_type);
9079                 ret = -EINVAL;
9080                 break;
9081         }
9082
9083         return ret;
9084 }
9085
9086 static int
9087 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9088 {
9089         int ret = 0;
9090
9091         if (!hw || !info) {
9092                 PMD_DRV_LOG(ERR, "Invalid pointer");
9093                 return -EFAULT;
9094         }
9095
9096         switch (info->info_type) {
9097         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9098                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9099                 break;
9100         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9101                 ret = i40e_set_hash_filter_global_config(hw,
9102                                 &(info->info.global_conf));
9103                 break;
9104         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9105                 ret = i40e_hash_filter_inset_select(hw,
9106                                                &(info->info.input_set_conf));
9107                 break;
9108
9109         default:
9110                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9111                                                         info->info_type);
9112                 ret = -EINVAL;
9113                 break;
9114         }
9115
9116         return ret;
9117 }
9118
9119 /* Operations for hash function */
9120 static int
9121 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9122                       enum rte_filter_op filter_op,
9123                       void *arg)
9124 {
9125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9126         int ret = 0;
9127
9128         switch (filter_op) {
9129         case RTE_ETH_FILTER_NOP:
9130                 break;
9131         case RTE_ETH_FILTER_GET:
9132                 ret = i40e_hash_filter_get(hw,
9133                         (struct rte_eth_hash_filter_info *)arg);
9134                 break;
9135         case RTE_ETH_FILTER_SET:
9136                 ret = i40e_hash_filter_set(hw,
9137                         (struct rte_eth_hash_filter_info *)arg);
9138                 break;
9139         default:
9140                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9141                                                                 filter_op);
9142                 ret = -ENOTSUP;
9143                 break;
9144         }
9145
9146         return ret;
9147 }
9148
9149 /* Convert ethertype filter structure */
9150 static int
9151 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9152                               struct i40e_ethertype_filter *filter)
9153 {
9154         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9155         filter->input.ether_type = input->ether_type;
9156         filter->flags = input->flags;
9157         filter->queue = input->queue;
9158
9159         return 0;
9160 }
9161
9162 /* Check if there exists the ehtertype filter */
9163 struct i40e_ethertype_filter *
9164 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9165                                 const struct i40e_ethertype_filter_input *input)
9166 {
9167         int ret;
9168
9169         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9170         if (ret < 0)
9171                 return NULL;
9172
9173         return ethertype_rule->hash_map[ret];
9174 }
9175
9176 /* Add ethertype filter in SW list */
9177 static int
9178 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9179                                 struct i40e_ethertype_filter *filter)
9180 {
9181         struct i40e_ethertype_rule *rule = &pf->ethertype;
9182         int ret;
9183
9184         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9185         if (ret < 0) {
9186                 PMD_DRV_LOG(ERR,
9187                             "Failed to insert ethertype filter"
9188                             " to hash table %d!",
9189                             ret);
9190                 return ret;
9191         }
9192         rule->hash_map[ret] = filter;
9193
9194         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9195
9196         return 0;
9197 }
9198
9199 /* Delete ethertype filter in SW list */
9200 int
9201 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9202                              struct i40e_ethertype_filter_input *input)
9203 {
9204         struct i40e_ethertype_rule *rule = &pf->ethertype;
9205         struct i40e_ethertype_filter *filter;
9206         int ret;
9207
9208         ret = rte_hash_del_key(rule->hash_table, input);
9209         if (ret < 0) {
9210                 PMD_DRV_LOG(ERR,
9211                             "Failed to delete ethertype filter"
9212                             " to hash table %d!",
9213                             ret);
9214                 return ret;
9215         }
9216         filter = rule->hash_map[ret];
9217         rule->hash_map[ret] = NULL;
9218
9219         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9220         rte_free(filter);
9221
9222         return 0;
9223 }
9224
9225 /*
9226  * Configure ethertype filter, which can director packet by filtering
9227  * with mac address and ether_type or only ether_type
9228  */
9229 int
9230 i40e_ethertype_filter_set(struct i40e_pf *pf,
9231                         struct rte_eth_ethertype_filter *filter,
9232                         bool add)
9233 {
9234         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9235         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9236         struct i40e_ethertype_filter *ethertype_filter, *node;
9237         struct i40e_ethertype_filter check_filter;
9238         struct i40e_control_filter_stats stats;
9239         uint16_t flags = 0;
9240         int ret;
9241
9242         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9243                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9244                 return -EINVAL;
9245         }
9246         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9247                 filter->ether_type == ETHER_TYPE_IPv6) {
9248                 PMD_DRV_LOG(ERR,
9249                         "unsupported ether_type(0x%04x) in control packet filter.",
9250                         filter->ether_type);
9251                 return -EINVAL;
9252         }
9253         if (filter->ether_type == ETHER_TYPE_VLAN)
9254                 PMD_DRV_LOG(WARNING,
9255                         "filter vlan ether_type in first tag is not supported.");
9256
9257         /* Check if there is the filter in SW list */
9258         memset(&check_filter, 0, sizeof(check_filter));
9259         i40e_ethertype_filter_convert(filter, &check_filter);
9260         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9261                                                &check_filter.input);
9262         if (add && node) {
9263                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9264                 return -EINVAL;
9265         }
9266
9267         if (!add && !node) {
9268                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9269                 return -EINVAL;
9270         }
9271
9272         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9273                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9274         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9275                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9276         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9277
9278         memset(&stats, 0, sizeof(stats));
9279         ret = i40e_aq_add_rem_control_packet_filter(hw,
9280                         filter->mac_addr.addr_bytes,
9281                         filter->ether_type, flags,
9282                         pf->main_vsi->seid,
9283                         filter->queue, add, &stats, NULL);
9284
9285         PMD_DRV_LOG(INFO,
9286                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9287                 ret, stats.mac_etype_used, stats.etype_used,
9288                 stats.mac_etype_free, stats.etype_free);
9289         if (ret < 0)
9290                 return -ENOSYS;
9291
9292         /* Add or delete a filter in SW list */
9293         if (add) {
9294                 ethertype_filter = rte_zmalloc("ethertype_filter",
9295                                        sizeof(*ethertype_filter), 0);
9296                 rte_memcpy(ethertype_filter, &check_filter,
9297                            sizeof(check_filter));
9298                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9299         } else {
9300                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9301         }
9302
9303         return ret;
9304 }
9305
9306 /*
9307  * Handle operations for ethertype filter.
9308  */
9309 static int
9310 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9311                                 enum rte_filter_op filter_op,
9312                                 void *arg)
9313 {
9314         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9315         int ret = 0;
9316
9317         if (filter_op == RTE_ETH_FILTER_NOP)
9318                 return ret;
9319
9320         if (arg == NULL) {
9321                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9322                             filter_op);
9323                 return -EINVAL;
9324         }
9325
9326         switch (filter_op) {
9327         case RTE_ETH_FILTER_ADD:
9328                 ret = i40e_ethertype_filter_set(pf,
9329                         (struct rte_eth_ethertype_filter *)arg,
9330                         TRUE);
9331                 break;
9332         case RTE_ETH_FILTER_DELETE:
9333                 ret = i40e_ethertype_filter_set(pf,
9334                         (struct rte_eth_ethertype_filter *)arg,
9335                         FALSE);
9336                 break;
9337         default:
9338                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9339                 ret = -ENOSYS;
9340                 break;
9341         }
9342         return ret;
9343 }
9344
9345 static int
9346 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9347                      enum rte_filter_type filter_type,
9348                      enum rte_filter_op filter_op,
9349                      void *arg)
9350 {
9351         int ret = 0;
9352
9353         if (dev == NULL)
9354                 return -EINVAL;
9355
9356         switch (filter_type) {
9357         case RTE_ETH_FILTER_NONE:
9358                 /* For global configuration */
9359                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9360                 break;
9361         case RTE_ETH_FILTER_HASH:
9362                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9363                 break;
9364         case RTE_ETH_FILTER_MACVLAN:
9365                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9366                 break;
9367         case RTE_ETH_FILTER_ETHERTYPE:
9368                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9369                 break;
9370         case RTE_ETH_FILTER_TUNNEL:
9371                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9372                 break;
9373         case RTE_ETH_FILTER_FDIR:
9374                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9375                 break;
9376         case RTE_ETH_FILTER_GENERIC:
9377                 if (filter_op != RTE_ETH_FILTER_GET)
9378                         return -EINVAL;
9379                 *(const void **)arg = &i40e_flow_ops;
9380                 break;
9381         default:
9382                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9383                                                         filter_type);
9384                 ret = -EINVAL;
9385                 break;
9386         }
9387
9388         return ret;
9389 }
9390
9391 /*
9392  * Check and enable Extended Tag.
9393  * Enabling Extended Tag is important for 40G performance.
9394  */
9395 static void
9396 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9397 {
9398         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9399         uint32_t buf = 0;
9400         int ret;
9401
9402         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9403                                       PCI_DEV_CAP_REG);
9404         if (ret < 0) {
9405                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9406                             PCI_DEV_CAP_REG);
9407                 return;
9408         }
9409         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9410                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9411                 return;
9412         }
9413
9414         buf = 0;
9415         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9416                                       PCI_DEV_CTRL_REG);
9417         if (ret < 0) {
9418                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9419                             PCI_DEV_CTRL_REG);
9420                 return;
9421         }
9422         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9423                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9424                 return;
9425         }
9426         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9427         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9428                                        PCI_DEV_CTRL_REG);
9429         if (ret < 0) {
9430                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9431                             PCI_DEV_CTRL_REG);
9432                 return;
9433         }
9434 }
9435
9436 /*
9437  * As some registers wouldn't be reset unless a global hardware reset,
9438  * hardware initialization is needed to put those registers into an
9439  * expected initial state.
9440  */
9441 static void
9442 i40e_hw_init(struct rte_eth_dev *dev)
9443 {
9444         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9445
9446         i40e_enable_extended_tag(dev);
9447
9448         /* clear the PF Queue Filter control register */
9449         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9450
9451         /* Disable symmetric hash per port */
9452         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9453 }
9454
9455 /*
9456  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9457  * however this function will return only one highest pctype index,
9458  * which is not quite correct. This is known problem of i40e driver
9459  * and needs to be fixed later.
9460  */
9461 enum i40e_filter_pctype
9462 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9463 {
9464         int i;
9465         uint64_t pctype_mask;
9466
9467         if (flow_type < I40E_FLOW_TYPE_MAX) {
9468                 pctype_mask = adapter->pctypes_tbl[flow_type];
9469                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9470                         if (pctype_mask & (1ULL << i))
9471                                 return (enum i40e_filter_pctype)i;
9472                 }
9473         }
9474         return I40E_FILTER_PCTYPE_INVALID;
9475 }
9476
9477 uint16_t
9478 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9479                         enum i40e_filter_pctype pctype)
9480 {
9481         uint16_t flowtype;
9482         uint64_t pctype_mask = 1ULL << pctype;
9483
9484         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9485              flowtype++) {
9486                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9487                         return flowtype;
9488         }
9489
9490         return RTE_ETH_FLOW_UNKNOWN;
9491 }
9492
9493 /*
9494  * On X710, performance number is far from the expectation on recent firmware
9495  * versions; on XL710, performance number is also far from the expectation on
9496  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9497  * mode is enabled and port MAC address is equal to the packet destination MAC
9498  * address. The fix for this issue may not be integrated in the following
9499  * firmware version. So the workaround in software driver is needed. It needs
9500  * to modify the initial values of 3 internal only registers for both X710 and
9501  * XL710. Note that the values for X710 or XL710 could be different, and the
9502  * workaround can be removed when it is fixed in firmware in the future.
9503  */
9504
9505 /* For both X710 and XL710 */
9506 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9507 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9508 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9509
9510 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9511 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9512
9513 /* For X722 */
9514 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9515 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9516
9517 /* For X710 */
9518 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9519 /* For XL710 */
9520 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9521 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9522
9523 static int
9524 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9525 {
9526         enum i40e_status_code status;
9527         struct i40e_aq_get_phy_abilities_resp phy_ab;
9528         int ret = -ENOTSUP;
9529         int retries = 0;
9530
9531         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9532                                               NULL);
9533
9534         while (status) {
9535                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9536                         status);
9537                 retries++;
9538                 rte_delay_us(100000);
9539                 if  (retries < 5)
9540                         status = i40e_aq_get_phy_capabilities(hw, false,
9541                                         true, &phy_ab, NULL);
9542                 else
9543                         return ret;
9544         }
9545         return 0;
9546 }
9547
9548 static void
9549 i40e_configure_registers(struct i40e_hw *hw)
9550 {
9551         static struct {
9552                 uint32_t addr;
9553                 uint64_t val;
9554         } reg_table[] = {
9555                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9556                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9557                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9558         };
9559         uint64_t reg;
9560         uint32_t i;
9561         int ret;
9562
9563         for (i = 0; i < RTE_DIM(reg_table); i++) {
9564                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9565                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9566                                 reg_table[i].val =
9567                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9568                         else /* For X710/XL710/XXV710 */
9569                                 if (hw->aq.fw_maj_ver < 6)
9570                                         reg_table[i].val =
9571                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9572                                 else
9573                                         reg_table[i].val =
9574                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9575                 }
9576
9577                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9578                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9579                                 reg_table[i].val =
9580                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9581                         else /* For X710/XL710/XXV710 */
9582                                 reg_table[i].val =
9583                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9584                 }
9585
9586                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9587                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9588                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9589                                 reg_table[i].val =
9590                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9591                         else /* For X710 */
9592                                 reg_table[i].val =
9593                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9594                 }
9595
9596                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9597                                                         &reg, NULL);
9598                 if (ret < 0) {
9599                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9600                                                         reg_table[i].addr);
9601                         break;
9602                 }
9603                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9604                                                 reg_table[i].addr, reg);
9605                 if (reg == reg_table[i].val)
9606                         continue;
9607
9608                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9609                                                 reg_table[i].val, NULL);
9610                 if (ret < 0) {
9611                         PMD_DRV_LOG(ERR,
9612                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9613                                 reg_table[i].val, reg_table[i].addr);
9614                         break;
9615                 }
9616                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9617                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9618         }
9619 }
9620
9621 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9622 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9623 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9624 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9625 static int
9626 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9627 {
9628         uint32_t reg;
9629         int ret;
9630
9631         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9632                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9633                 return -EINVAL;
9634         }
9635
9636         /* Configure for double VLAN RX stripping */
9637         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9638         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9639                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9640                 ret = i40e_aq_debug_write_register(hw,
9641                                                    I40E_VSI_TSR(vsi->vsi_id),
9642                                                    reg, NULL);
9643                 if (ret < 0) {
9644                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9645                                     vsi->vsi_id);
9646                         return I40E_ERR_CONFIG;
9647                 }
9648         }
9649
9650         /* Configure for double VLAN TX insertion */
9651         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9652         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9653                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9654                 ret = i40e_aq_debug_write_register(hw,
9655                                                    I40E_VSI_L2TAGSTXVALID(
9656                                                    vsi->vsi_id), reg, NULL);
9657                 if (ret < 0) {
9658                         PMD_DRV_LOG(ERR,
9659                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9660                                 vsi->vsi_id);
9661                         return I40E_ERR_CONFIG;
9662                 }
9663         }
9664
9665         return 0;
9666 }
9667
9668 /**
9669  * i40e_aq_add_mirror_rule
9670  * @hw: pointer to the hardware structure
9671  * @seid: VEB seid to add mirror rule to
9672  * @dst_id: destination vsi seid
9673  * @entries: Buffer which contains the entities to be mirrored
9674  * @count: number of entities contained in the buffer
9675  * @rule_id:the rule_id of the rule to be added
9676  *
9677  * Add a mirror rule for a given veb.
9678  *
9679  **/
9680 static enum i40e_status_code
9681 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9682                         uint16_t seid, uint16_t dst_id,
9683                         uint16_t rule_type, uint16_t *entries,
9684                         uint16_t count, uint16_t *rule_id)
9685 {
9686         struct i40e_aq_desc desc;
9687         struct i40e_aqc_add_delete_mirror_rule cmd;
9688         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9689                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9690                 &desc.params.raw;
9691         uint16_t buff_len;
9692         enum i40e_status_code status;
9693
9694         i40e_fill_default_direct_cmd_desc(&desc,
9695                                           i40e_aqc_opc_add_mirror_rule);
9696         memset(&cmd, 0, sizeof(cmd));
9697
9698         buff_len = sizeof(uint16_t) * count;
9699         desc.datalen = rte_cpu_to_le_16(buff_len);
9700         if (buff_len > 0)
9701                 desc.flags |= rte_cpu_to_le_16(
9702                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9703         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9704                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9705         cmd.num_entries = rte_cpu_to_le_16(count);
9706         cmd.seid = rte_cpu_to_le_16(seid);
9707         cmd.destination = rte_cpu_to_le_16(dst_id);
9708
9709         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9710         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9711         PMD_DRV_LOG(INFO,
9712                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9713                 hw->aq.asq_last_status, resp->rule_id,
9714                 resp->mirror_rules_used, resp->mirror_rules_free);
9715         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9716
9717         return status;
9718 }
9719
9720 /**
9721  * i40e_aq_del_mirror_rule
9722  * @hw: pointer to the hardware structure
9723  * @seid: VEB seid to add mirror rule to
9724  * @entries: Buffer which contains the entities to be mirrored
9725  * @count: number of entities contained in the buffer
9726  * @rule_id:the rule_id of the rule to be delete
9727  *
9728  * Delete a mirror rule for a given veb.
9729  *
9730  **/
9731 static enum i40e_status_code
9732 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9733                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9734                 uint16_t count, uint16_t rule_id)
9735 {
9736         struct i40e_aq_desc desc;
9737         struct i40e_aqc_add_delete_mirror_rule cmd;
9738         uint16_t buff_len = 0;
9739         enum i40e_status_code status;
9740         void *buff = NULL;
9741
9742         i40e_fill_default_direct_cmd_desc(&desc,
9743                                           i40e_aqc_opc_delete_mirror_rule);
9744         memset(&cmd, 0, sizeof(cmd));
9745         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9746                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9747                                                           I40E_AQ_FLAG_RD));
9748                 cmd.num_entries = count;
9749                 buff_len = sizeof(uint16_t) * count;
9750                 desc.datalen = rte_cpu_to_le_16(buff_len);
9751                 buff = (void *)entries;
9752         } else
9753                 /* rule id is filled in destination field for deleting mirror rule */
9754                 cmd.destination = rte_cpu_to_le_16(rule_id);
9755
9756         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9757                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9758         cmd.seid = rte_cpu_to_le_16(seid);
9759
9760         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9761         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9762
9763         return status;
9764 }
9765
9766 /**
9767  * i40e_mirror_rule_set
9768  * @dev: pointer to the hardware structure
9769  * @mirror_conf: mirror rule info
9770  * @sw_id: mirror rule's sw_id
9771  * @on: enable/disable
9772  *
9773  * set a mirror rule.
9774  *
9775  **/
9776 static int
9777 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9778                         struct rte_eth_mirror_conf *mirror_conf,
9779                         uint8_t sw_id, uint8_t on)
9780 {
9781         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9782         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9783         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9784         struct i40e_mirror_rule *parent = NULL;
9785         uint16_t seid, dst_seid, rule_id;
9786         uint16_t i, j = 0;
9787         int ret;
9788
9789         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9790
9791         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9792                 PMD_DRV_LOG(ERR,
9793                         "mirror rule can not be configured without veb or vfs.");
9794                 return -ENOSYS;
9795         }
9796         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9797                 PMD_DRV_LOG(ERR, "mirror table is full.");
9798                 return -ENOSPC;
9799         }
9800         if (mirror_conf->dst_pool > pf->vf_num) {
9801                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9802                                  mirror_conf->dst_pool);
9803                 return -EINVAL;
9804         }
9805
9806         seid = pf->main_vsi->veb->seid;
9807
9808         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9809                 if (sw_id <= it->index) {
9810                         mirr_rule = it;
9811                         break;
9812                 }
9813                 parent = it;
9814         }
9815         if (mirr_rule && sw_id == mirr_rule->index) {
9816                 if (on) {
9817                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9818                         return -EEXIST;
9819                 } else {
9820                         ret = i40e_aq_del_mirror_rule(hw, seid,
9821                                         mirr_rule->rule_type,
9822                                         mirr_rule->entries,
9823                                         mirr_rule->num_entries, mirr_rule->id);
9824                         if (ret < 0) {
9825                                 PMD_DRV_LOG(ERR,
9826                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9827                                         ret, hw->aq.asq_last_status);
9828                                 return -ENOSYS;
9829                         }
9830                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9831                         rte_free(mirr_rule);
9832                         pf->nb_mirror_rule--;
9833                         return 0;
9834                 }
9835         } else if (!on) {
9836                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9837                 return -ENOENT;
9838         }
9839
9840         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9841                                 sizeof(struct i40e_mirror_rule) , 0);
9842         if (!mirr_rule) {
9843                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9844                 return I40E_ERR_NO_MEMORY;
9845         }
9846         switch (mirror_conf->rule_type) {
9847         case ETH_MIRROR_VLAN:
9848                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9849                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9850                                 mirr_rule->entries[j] =
9851                                         mirror_conf->vlan.vlan_id[i];
9852                                 j++;
9853                         }
9854                 }
9855                 if (j == 0) {
9856                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9857                         rte_free(mirr_rule);
9858                         return -EINVAL;
9859                 }
9860                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9861                 break;
9862         case ETH_MIRROR_VIRTUAL_POOL_UP:
9863         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9864                 /* check if the specified pool bit is out of range */
9865                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9866                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9867                         rte_free(mirr_rule);
9868                         return -EINVAL;
9869                 }
9870                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9871                         if (mirror_conf->pool_mask & (1ULL << i)) {
9872                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9873                                 j++;
9874                         }
9875                 }
9876                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9877                         /* add pf vsi to entries */
9878                         mirr_rule->entries[j] = pf->main_vsi_seid;
9879                         j++;
9880                 }
9881                 if (j == 0) {
9882                         PMD_DRV_LOG(ERR, "pool is not specified.");
9883                         rte_free(mirr_rule);
9884                         return -EINVAL;
9885                 }
9886                 /* egress and ingress in aq commands means from switch but not port */
9887                 mirr_rule->rule_type =
9888                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9889                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9890                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9891                 break;
9892         case ETH_MIRROR_UPLINK_PORT:
9893                 /* egress and ingress in aq commands means from switch but not port*/
9894                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9895                 break;
9896         case ETH_MIRROR_DOWNLINK_PORT:
9897                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9898                 break;
9899         default:
9900                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9901                         mirror_conf->rule_type);
9902                 rte_free(mirr_rule);
9903                 return -EINVAL;
9904         }
9905
9906         /* If the dst_pool is equal to vf_num, consider it as PF */
9907         if (mirror_conf->dst_pool == pf->vf_num)
9908                 dst_seid = pf->main_vsi_seid;
9909         else
9910                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9911
9912         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9913                                       mirr_rule->rule_type, mirr_rule->entries,
9914                                       j, &rule_id);
9915         if (ret < 0) {
9916                 PMD_DRV_LOG(ERR,
9917                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9918                         ret, hw->aq.asq_last_status);
9919                 rte_free(mirr_rule);
9920                 return -ENOSYS;
9921         }
9922
9923         mirr_rule->index = sw_id;
9924         mirr_rule->num_entries = j;
9925         mirr_rule->id = rule_id;
9926         mirr_rule->dst_vsi_seid = dst_seid;
9927
9928         if (parent)
9929                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9930         else
9931                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9932
9933         pf->nb_mirror_rule++;
9934         return 0;
9935 }
9936
9937 /**
9938  * i40e_mirror_rule_reset
9939  * @dev: pointer to the device
9940  * @sw_id: mirror rule's sw_id
9941  *
9942  * reset a mirror rule.
9943  *
9944  **/
9945 static int
9946 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9947 {
9948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9950         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9951         uint16_t seid;
9952         int ret;
9953
9954         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9955
9956         seid = pf->main_vsi->veb->seid;
9957
9958         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9959                 if (sw_id == it->index) {
9960                         mirr_rule = it;
9961                         break;
9962                 }
9963         }
9964         if (mirr_rule) {
9965                 ret = i40e_aq_del_mirror_rule(hw, seid,
9966                                 mirr_rule->rule_type,
9967                                 mirr_rule->entries,
9968                                 mirr_rule->num_entries, mirr_rule->id);
9969                 if (ret < 0) {
9970                         PMD_DRV_LOG(ERR,
9971                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9972                                 ret, hw->aq.asq_last_status);
9973                         return -ENOSYS;
9974                 }
9975                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9976                 rte_free(mirr_rule);
9977                 pf->nb_mirror_rule--;
9978         } else {
9979                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9980                 return -ENOENT;
9981         }
9982         return 0;
9983 }
9984
9985 static uint64_t
9986 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9987 {
9988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9989         uint64_t systim_cycles;
9990
9991         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9992         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9993                         << 32;
9994
9995         return systim_cycles;
9996 }
9997
9998 static uint64_t
9999 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10000 {
10001         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10002         uint64_t rx_tstamp;
10003
10004         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10005         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10006                         << 32;
10007
10008         return rx_tstamp;
10009 }
10010
10011 static uint64_t
10012 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10013 {
10014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10015         uint64_t tx_tstamp;
10016
10017         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10018         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10019                         << 32;
10020
10021         return tx_tstamp;
10022 }
10023
10024 static void
10025 i40e_start_timecounters(struct rte_eth_dev *dev)
10026 {
10027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10028         struct i40e_adapter *adapter =
10029                         (struct i40e_adapter *)dev->data->dev_private;
10030         struct rte_eth_link link;
10031         uint32_t tsync_inc_l;
10032         uint32_t tsync_inc_h;
10033
10034         /* Get current link speed. */
10035         memset(&link, 0, sizeof(link));
10036         i40e_dev_link_update(dev, 1);
10037         rte_i40e_dev_atomic_read_link_status(dev, &link);
10038
10039         switch (link.link_speed) {
10040         case ETH_SPEED_NUM_40G:
10041                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10042                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10043                 break;
10044         case ETH_SPEED_NUM_10G:
10045                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10046                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10047                 break;
10048         case ETH_SPEED_NUM_1G:
10049                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10050                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10051                 break;
10052         default:
10053                 tsync_inc_l = 0x0;
10054                 tsync_inc_h = 0x0;
10055         }
10056
10057         /* Set the timesync increment value. */
10058         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10059         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10060
10061         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10062         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10063         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10064
10065         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10066         adapter->systime_tc.cc_shift = 0;
10067         adapter->systime_tc.nsec_mask = 0;
10068
10069         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10070         adapter->rx_tstamp_tc.cc_shift = 0;
10071         adapter->rx_tstamp_tc.nsec_mask = 0;
10072
10073         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10074         adapter->tx_tstamp_tc.cc_shift = 0;
10075         adapter->tx_tstamp_tc.nsec_mask = 0;
10076 }
10077
10078 static int
10079 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10080 {
10081         struct i40e_adapter *adapter =
10082                         (struct i40e_adapter *)dev->data->dev_private;
10083
10084         adapter->systime_tc.nsec += delta;
10085         adapter->rx_tstamp_tc.nsec += delta;
10086         adapter->tx_tstamp_tc.nsec += delta;
10087
10088         return 0;
10089 }
10090
10091 static int
10092 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10093 {
10094         uint64_t ns;
10095         struct i40e_adapter *adapter =
10096                         (struct i40e_adapter *)dev->data->dev_private;
10097
10098         ns = rte_timespec_to_ns(ts);
10099
10100         /* Set the timecounters to a new value. */
10101         adapter->systime_tc.nsec = ns;
10102         adapter->rx_tstamp_tc.nsec = ns;
10103         adapter->tx_tstamp_tc.nsec = ns;
10104
10105         return 0;
10106 }
10107
10108 static int
10109 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10110 {
10111         uint64_t ns, systime_cycles;
10112         struct i40e_adapter *adapter =
10113                         (struct i40e_adapter *)dev->data->dev_private;
10114
10115         systime_cycles = i40e_read_systime_cyclecounter(dev);
10116         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10117         *ts = rte_ns_to_timespec(ns);
10118
10119         return 0;
10120 }
10121
10122 static int
10123 i40e_timesync_enable(struct rte_eth_dev *dev)
10124 {
10125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10126         uint32_t tsync_ctl_l;
10127         uint32_t tsync_ctl_h;
10128
10129         /* Stop the timesync system time. */
10130         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10131         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10132         /* Reset the timesync system time value. */
10133         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10134         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10135
10136         i40e_start_timecounters(dev);
10137
10138         /* Clear timesync registers. */
10139         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10140         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10141         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10142         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10143         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10144         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10145
10146         /* Enable timestamping of PTP packets. */
10147         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10148         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10149
10150         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10151         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10152         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10153
10154         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10155         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10156
10157         return 0;
10158 }
10159
10160 static int
10161 i40e_timesync_disable(struct rte_eth_dev *dev)
10162 {
10163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10164         uint32_t tsync_ctl_l;
10165         uint32_t tsync_ctl_h;
10166
10167         /* Disable timestamping of transmitted PTP packets. */
10168         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10169         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10170
10171         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10172         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10173
10174         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10175         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10176
10177         /* Reset the timesync increment value. */
10178         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10179         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10180
10181         return 0;
10182 }
10183
10184 static int
10185 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10186                                 struct timespec *timestamp, uint32_t flags)
10187 {
10188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10189         struct i40e_adapter *adapter =
10190                 (struct i40e_adapter *)dev->data->dev_private;
10191
10192         uint32_t sync_status;
10193         uint32_t index = flags & 0x03;
10194         uint64_t rx_tstamp_cycles;
10195         uint64_t ns;
10196
10197         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10198         if ((sync_status & (1 << index)) == 0)
10199                 return -EINVAL;
10200
10201         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10202         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10203         *timestamp = rte_ns_to_timespec(ns);
10204
10205         return 0;
10206 }
10207
10208 static int
10209 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10210                                 struct timespec *timestamp)
10211 {
10212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10213         struct i40e_adapter *adapter =
10214                 (struct i40e_adapter *)dev->data->dev_private;
10215
10216         uint32_t sync_status;
10217         uint64_t tx_tstamp_cycles;
10218         uint64_t ns;
10219
10220         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10221         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10222                 return -EINVAL;
10223
10224         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10225         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10226         *timestamp = rte_ns_to_timespec(ns);
10227
10228         return 0;
10229 }
10230
10231 /*
10232  * i40e_parse_dcb_configure - parse dcb configure from user
10233  * @dev: the device being configured
10234  * @dcb_cfg: pointer of the result of parse
10235  * @*tc_map: bit map of enabled traffic classes
10236  *
10237  * Returns 0 on success, negative value on failure
10238  */
10239 static int
10240 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10241                          struct i40e_dcbx_config *dcb_cfg,
10242                          uint8_t *tc_map)
10243 {
10244         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10245         uint8_t i, tc_bw, bw_lf;
10246
10247         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10248
10249         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10250         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10251                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10252                 return -EINVAL;
10253         }
10254
10255         /* assume each tc has the same bw */
10256         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10257         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10258                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10259         /* to ensure the sum of tcbw is equal to 100 */
10260         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10261         for (i = 0; i < bw_lf; i++)
10262                 dcb_cfg->etscfg.tcbwtable[i]++;
10263
10264         /* assume each tc has the same Transmission Selection Algorithm */
10265         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10266                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10267
10268         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10269                 dcb_cfg->etscfg.prioritytable[i] =
10270                                 dcb_rx_conf->dcb_tc[i];
10271
10272         /* FW needs one App to configure HW */
10273         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10274         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10275         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10276         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10277
10278         if (dcb_rx_conf->nb_tcs == 0)
10279                 *tc_map = 1; /* tc0 only */
10280         else
10281                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10282
10283         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10284                 dcb_cfg->pfc.willing = 0;
10285                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10286                 dcb_cfg->pfc.pfcenable = *tc_map;
10287         }
10288         return 0;
10289 }
10290
10291
10292 static enum i40e_status_code
10293 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10294                               struct i40e_aqc_vsi_properties_data *info,
10295                               uint8_t enabled_tcmap)
10296 {
10297         enum i40e_status_code ret;
10298         int i, total_tc = 0;
10299         uint16_t qpnum_per_tc, bsf, qp_idx;
10300         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10301         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10302         uint16_t used_queues;
10303
10304         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10305         if (ret != I40E_SUCCESS)
10306                 return ret;
10307
10308         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10309                 if (enabled_tcmap & (1 << i))
10310                         total_tc++;
10311         }
10312         if (total_tc == 0)
10313                 total_tc = 1;
10314         vsi->enabled_tc = enabled_tcmap;
10315
10316         /* different VSI has different queues assigned */
10317         if (vsi->type == I40E_VSI_MAIN)
10318                 used_queues = dev_data->nb_rx_queues -
10319                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10320         else if (vsi->type == I40E_VSI_VMDQ2)
10321                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10322         else {
10323                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10324                 return I40E_ERR_NO_AVAILABLE_VSI;
10325         }
10326
10327         qpnum_per_tc = used_queues / total_tc;
10328         /* Number of queues per enabled TC */
10329         if (qpnum_per_tc == 0) {
10330                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10331                 return I40E_ERR_INVALID_QP_ID;
10332         }
10333         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10334                                 I40E_MAX_Q_PER_TC);
10335         bsf = rte_bsf32(qpnum_per_tc);
10336
10337         /**
10338          * Configure TC and queue mapping parameters, for enabled TC,
10339          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10340          * default queue will serve it.
10341          */
10342         qp_idx = 0;
10343         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10344                 if (vsi->enabled_tc & (1 << i)) {
10345                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10346                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10347                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10348                         qp_idx += qpnum_per_tc;
10349                 } else
10350                         info->tc_mapping[i] = 0;
10351         }
10352
10353         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10354         if (vsi->type == I40E_VSI_SRIOV) {
10355                 info->mapping_flags |=
10356                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10357                 for (i = 0; i < vsi->nb_qps; i++)
10358                         info->queue_mapping[i] =
10359                                 rte_cpu_to_le_16(vsi->base_queue + i);
10360         } else {
10361                 info->mapping_flags |=
10362                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10363                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10364         }
10365         info->valid_sections |=
10366                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10367
10368         return I40E_SUCCESS;
10369 }
10370
10371 /*
10372  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10373  * @veb: VEB to be configured
10374  * @tc_map: enabled TC bitmap
10375  *
10376  * Returns 0 on success, negative value on failure
10377  */
10378 static enum i40e_status_code
10379 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10380 {
10381         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10382         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10383         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10384         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10385         enum i40e_status_code ret = I40E_SUCCESS;
10386         int i;
10387         uint32_t bw_max;
10388
10389         /* Check if enabled_tc is same as existing or new TCs */
10390         if (veb->enabled_tc == tc_map)
10391                 return ret;
10392
10393         /* configure tc bandwidth */
10394         memset(&veb_bw, 0, sizeof(veb_bw));
10395         veb_bw.tc_valid_bits = tc_map;
10396         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10397         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10398                 if (tc_map & BIT_ULL(i))
10399                         veb_bw.tc_bw_share_credits[i] = 1;
10400         }
10401         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10402                                                    &veb_bw, NULL);
10403         if (ret) {
10404                 PMD_INIT_LOG(ERR,
10405                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10406                         hw->aq.asq_last_status);
10407                 return ret;
10408         }
10409
10410         memset(&ets_query, 0, sizeof(ets_query));
10411         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10412                                                    &ets_query, NULL);
10413         if (ret != I40E_SUCCESS) {
10414                 PMD_DRV_LOG(ERR,
10415                         "Failed to get switch_comp ETS configuration %u",
10416                         hw->aq.asq_last_status);
10417                 return ret;
10418         }
10419         memset(&bw_query, 0, sizeof(bw_query));
10420         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10421                                                   &bw_query, NULL);
10422         if (ret != I40E_SUCCESS) {
10423                 PMD_DRV_LOG(ERR,
10424                         "Failed to get switch_comp bandwidth configuration %u",
10425                         hw->aq.asq_last_status);
10426                 return ret;
10427         }
10428
10429         /* store and print out BW info */
10430         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10431         veb->bw_info.bw_max = ets_query.tc_bw_max;
10432         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10433         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10434         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10435                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10436                      I40E_16_BIT_WIDTH);
10437         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10438                 veb->bw_info.bw_ets_share_credits[i] =
10439                                 bw_query.tc_bw_share_credits[i];
10440                 veb->bw_info.bw_ets_credits[i] =
10441                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10442                 /* 4 bits per TC, 4th bit is reserved */
10443                 veb->bw_info.bw_ets_max[i] =
10444                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10445                                   RTE_LEN2MASK(3, uint8_t));
10446                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10447                             veb->bw_info.bw_ets_share_credits[i]);
10448                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10449                             veb->bw_info.bw_ets_credits[i]);
10450                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10451                             veb->bw_info.bw_ets_max[i]);
10452         }
10453
10454         veb->enabled_tc = tc_map;
10455
10456         return ret;
10457 }
10458
10459
10460 /*
10461  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10462  * @vsi: VSI to be configured
10463  * @tc_map: enabled TC bitmap
10464  *
10465  * Returns 0 on success, negative value on failure
10466  */
10467 static enum i40e_status_code
10468 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10469 {
10470         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10471         struct i40e_vsi_context ctxt;
10472         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10473         enum i40e_status_code ret = I40E_SUCCESS;
10474         int i;
10475
10476         /* Check if enabled_tc is same as existing or new TCs */
10477         if (vsi->enabled_tc == tc_map)
10478                 return ret;
10479
10480         /* configure tc bandwidth */
10481         memset(&bw_data, 0, sizeof(bw_data));
10482         bw_data.tc_valid_bits = tc_map;
10483         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10484         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10485                 if (tc_map & BIT_ULL(i))
10486                         bw_data.tc_bw_credits[i] = 1;
10487         }
10488         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10489         if (ret) {
10490                 PMD_INIT_LOG(ERR,
10491                         "AQ command Config VSI BW allocation per TC failed = %d",
10492                         hw->aq.asq_last_status);
10493                 goto out;
10494         }
10495         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10496                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10497
10498         /* Update Queue Pairs Mapping for currently enabled UPs */
10499         ctxt.seid = vsi->seid;
10500         ctxt.pf_num = hw->pf_id;
10501         ctxt.vf_num = 0;
10502         ctxt.uplink_seid = vsi->uplink_seid;
10503         ctxt.info = vsi->info;
10504         i40e_get_cap(hw);
10505         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10506         if (ret)
10507                 goto out;
10508
10509         /* Update the VSI after updating the VSI queue-mapping information */
10510         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10511         if (ret) {
10512                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10513                         hw->aq.asq_last_status);
10514                 goto out;
10515         }
10516         /* update the local VSI info with updated queue map */
10517         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10518                                         sizeof(vsi->info.tc_mapping));
10519         rte_memcpy(&vsi->info.queue_mapping,
10520                         &ctxt.info.queue_mapping,
10521                 sizeof(vsi->info.queue_mapping));
10522         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10523         vsi->info.valid_sections = 0;
10524
10525         /* query and update current VSI BW information */
10526         ret = i40e_vsi_get_bw_config(vsi);
10527         if (ret) {
10528                 PMD_INIT_LOG(ERR,
10529                          "Failed updating vsi bw info, err %s aq_err %s",
10530                          i40e_stat_str(hw, ret),
10531                          i40e_aq_str(hw, hw->aq.asq_last_status));
10532                 goto out;
10533         }
10534
10535         vsi->enabled_tc = tc_map;
10536
10537 out:
10538         return ret;
10539 }
10540
10541 /*
10542  * i40e_dcb_hw_configure - program the dcb setting to hw
10543  * @pf: pf the configuration is taken on
10544  * @new_cfg: new configuration
10545  * @tc_map: enabled TC bitmap
10546  *
10547  * Returns 0 on success, negative value on failure
10548  */
10549 static enum i40e_status_code
10550 i40e_dcb_hw_configure(struct i40e_pf *pf,
10551                       struct i40e_dcbx_config *new_cfg,
10552                       uint8_t tc_map)
10553 {
10554         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10555         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10556         struct i40e_vsi *main_vsi = pf->main_vsi;
10557         struct i40e_vsi_list *vsi_list;
10558         enum i40e_status_code ret;
10559         int i;
10560         uint32_t val;
10561
10562         /* Use the FW API if FW > v4.4*/
10563         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10564               (hw->aq.fw_maj_ver >= 5))) {
10565                 PMD_INIT_LOG(ERR,
10566                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10567                 return I40E_ERR_FIRMWARE_API_VERSION;
10568         }
10569
10570         /* Check if need reconfiguration */
10571         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10572                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10573                 return I40E_SUCCESS;
10574         }
10575
10576         /* Copy the new config to the current config */
10577         *old_cfg = *new_cfg;
10578         old_cfg->etsrec = old_cfg->etscfg;
10579         ret = i40e_set_dcb_config(hw);
10580         if (ret) {
10581                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10582                          i40e_stat_str(hw, ret),
10583                          i40e_aq_str(hw, hw->aq.asq_last_status));
10584                 return ret;
10585         }
10586         /* set receive Arbiter to RR mode and ETS scheme by default */
10587         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10588                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10589                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10590                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10591                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10592                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10593                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10594                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10595                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10596                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10597                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10598                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10599                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10600         }
10601         /* get local mib to check whether it is configured correctly */
10602         /* IEEE mode */
10603         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10604         /* Get Local DCB Config */
10605         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10606                                      &hw->local_dcbx_config);
10607
10608         /* if Veb is created, need to update TC of it at first */
10609         if (main_vsi->veb) {
10610                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10611                 if (ret)
10612                         PMD_INIT_LOG(WARNING,
10613                                  "Failed configuring TC for VEB seid=%d",
10614                                  main_vsi->veb->seid);
10615         }
10616         /* Update each VSI */
10617         i40e_vsi_config_tc(main_vsi, tc_map);
10618         if (main_vsi->veb) {
10619                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10620                         /* Beside main VSI and VMDQ VSIs, only enable default
10621                          * TC for other VSIs
10622                          */
10623                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10624                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10625                                                          tc_map);
10626                         else
10627                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10628                                                          I40E_DEFAULT_TCMAP);
10629                         if (ret)
10630                                 PMD_INIT_LOG(WARNING,
10631                                         "Failed configuring TC for VSI seid=%d",
10632                                         vsi_list->vsi->seid);
10633                         /* continue */
10634                 }
10635         }
10636         return I40E_SUCCESS;
10637 }
10638
10639 /*
10640  * i40e_dcb_init_configure - initial dcb config
10641  * @dev: device being configured
10642  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10643  *
10644  * Returns 0 on success, negative value on failure
10645  */
10646 int
10647 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10648 {
10649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10651         int i, ret = 0;
10652
10653         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10654                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10655                 return -ENOTSUP;
10656         }
10657
10658         /* DCB initialization:
10659          * Update DCB configuration from the Firmware and configure
10660          * LLDP MIB change event.
10661          */
10662         if (sw_dcb == TRUE) {
10663                 ret = i40e_init_dcb(hw);
10664                 /* If lldp agent is stopped, the return value from
10665                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10666                  * adminq status. Otherwise, it should return success.
10667                  */
10668                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10669                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10670                         memset(&hw->local_dcbx_config, 0,
10671                                 sizeof(struct i40e_dcbx_config));
10672                         /* set dcb default configuration */
10673                         hw->local_dcbx_config.etscfg.willing = 0;
10674                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10675                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10676                         hw->local_dcbx_config.etscfg.tsatable[0] =
10677                                                 I40E_IEEE_TSA_ETS;
10678                         /* all UPs mapping to TC0 */
10679                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10680                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10681                         hw->local_dcbx_config.etsrec =
10682                                 hw->local_dcbx_config.etscfg;
10683                         hw->local_dcbx_config.pfc.willing = 0;
10684                         hw->local_dcbx_config.pfc.pfccap =
10685                                                 I40E_MAX_TRAFFIC_CLASS;
10686                         /* FW needs one App to configure HW */
10687                         hw->local_dcbx_config.numapps = 1;
10688                         hw->local_dcbx_config.app[0].selector =
10689                                                 I40E_APP_SEL_ETHTYPE;
10690                         hw->local_dcbx_config.app[0].priority = 3;
10691                         hw->local_dcbx_config.app[0].protocolid =
10692                                                 I40E_APP_PROTOID_FCOE;
10693                         ret = i40e_set_dcb_config(hw);
10694                         if (ret) {
10695                                 PMD_INIT_LOG(ERR,
10696                                         "default dcb config fails. err = %d, aq_err = %d.",
10697                                         ret, hw->aq.asq_last_status);
10698                                 return -ENOSYS;
10699                         }
10700                 } else {
10701                         PMD_INIT_LOG(ERR,
10702                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10703                                 ret, hw->aq.asq_last_status);
10704                         return -ENOTSUP;
10705                 }
10706         } else {
10707                 ret = i40e_aq_start_lldp(hw, NULL);
10708                 if (ret != I40E_SUCCESS)
10709                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10710
10711                 ret = i40e_init_dcb(hw);
10712                 if (!ret) {
10713                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10714                                 PMD_INIT_LOG(ERR,
10715                                         "HW doesn't support DCBX offload.");
10716                                 return -ENOTSUP;
10717                         }
10718                 } else {
10719                         PMD_INIT_LOG(ERR,
10720                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10721                                 ret, hw->aq.asq_last_status);
10722                         return -ENOTSUP;
10723                 }
10724         }
10725         return 0;
10726 }
10727
10728 /*
10729  * i40e_dcb_setup - setup dcb related config
10730  * @dev: device being configured
10731  *
10732  * Returns 0 on success, negative value on failure
10733  */
10734 static int
10735 i40e_dcb_setup(struct rte_eth_dev *dev)
10736 {
10737         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10738         struct i40e_dcbx_config dcb_cfg;
10739         uint8_t tc_map = 0;
10740         int ret = 0;
10741
10742         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10743                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10744                 return -ENOTSUP;
10745         }
10746
10747         if (pf->vf_num != 0)
10748                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10749
10750         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10751         if (ret) {
10752                 PMD_INIT_LOG(ERR, "invalid dcb config");
10753                 return -EINVAL;
10754         }
10755         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10756         if (ret) {
10757                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10758                 return -ENOSYS;
10759         }
10760
10761         return 0;
10762 }
10763
10764 static int
10765 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10766                       struct rte_eth_dcb_info *dcb_info)
10767 {
10768         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770         struct i40e_vsi *vsi = pf->main_vsi;
10771         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10772         uint16_t bsf, tc_mapping;
10773         int i, j = 0;
10774
10775         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10776                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10777         else
10778                 dcb_info->nb_tcs = 1;
10779         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10780                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10781         for (i = 0; i < dcb_info->nb_tcs; i++)
10782                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10783
10784         /* get queue mapping if vmdq is disabled */
10785         if (!pf->nb_cfg_vmdq_vsi) {
10786                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10787                         if (!(vsi->enabled_tc & (1 << i)))
10788                                 continue;
10789                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10790                         dcb_info->tc_queue.tc_rxq[j][i].base =
10791                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10792                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10793                         dcb_info->tc_queue.tc_txq[j][i].base =
10794                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10795                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10796                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10797                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10798                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10799                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10800                 }
10801                 return 0;
10802         }
10803
10804         /* get queue mapping if vmdq is enabled */
10805         do {
10806                 vsi = pf->vmdq[j].vsi;
10807                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10808                         if (!(vsi->enabled_tc & (1 << i)))
10809                                 continue;
10810                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10811                         dcb_info->tc_queue.tc_rxq[j][i].base =
10812                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10813                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10814                         dcb_info->tc_queue.tc_txq[j][i].base =
10815                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10816                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10817                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10818                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10819                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10820                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10821                 }
10822                 j++;
10823         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10824         return 0;
10825 }
10826
10827 static int
10828 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10829 {
10830         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10831         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10833         uint16_t interval =
10834                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10835         uint16_t msix_intr;
10836
10837         msix_intr = intr_handle->intr_vec[queue_id];
10838         if (msix_intr == I40E_MISC_VEC_ID)
10839                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10840                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10841                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10842                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10843                                (interval <<
10844                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10845         else
10846                 I40E_WRITE_REG(hw,
10847                                I40E_PFINT_DYN_CTLN(msix_intr -
10848                                                    I40E_RX_VEC_START),
10849                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10850                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10851                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10852                                (interval <<
10853                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10854
10855         I40E_WRITE_FLUSH(hw);
10856         rte_intr_enable(&pci_dev->intr_handle);
10857
10858         return 0;
10859 }
10860
10861 static int
10862 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10863 {
10864         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10865         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10867         uint16_t msix_intr;
10868
10869         msix_intr = intr_handle->intr_vec[queue_id];
10870         if (msix_intr == I40E_MISC_VEC_ID)
10871                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10872         else
10873                 I40E_WRITE_REG(hw,
10874                                I40E_PFINT_DYN_CTLN(msix_intr -
10875                                                    I40E_RX_VEC_START),
10876                                0);
10877         I40E_WRITE_FLUSH(hw);
10878
10879         return 0;
10880 }
10881
10882 static int i40e_get_regs(struct rte_eth_dev *dev,
10883                          struct rte_dev_reg_info *regs)
10884 {
10885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10886         uint32_t *ptr_data = regs->data;
10887         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10888         const struct i40e_reg_info *reg_info;
10889
10890         if (ptr_data == NULL) {
10891                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10892                 regs->width = sizeof(uint32_t);
10893                 return 0;
10894         }
10895
10896         /* The first few registers have to be read using AQ operations */
10897         reg_idx = 0;
10898         while (i40e_regs_adminq[reg_idx].name) {
10899                 reg_info = &i40e_regs_adminq[reg_idx++];
10900                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10901                         for (arr_idx2 = 0;
10902                                         arr_idx2 <= reg_info->count2;
10903                                         arr_idx2++) {
10904                                 reg_offset = arr_idx * reg_info->stride1 +
10905                                         arr_idx2 * reg_info->stride2;
10906                                 reg_offset += reg_info->base_addr;
10907                                 ptr_data[reg_offset >> 2] =
10908                                         i40e_read_rx_ctl(hw, reg_offset);
10909                         }
10910         }
10911
10912         /* The remaining registers can be read using primitives */
10913         reg_idx = 0;
10914         while (i40e_regs_others[reg_idx].name) {
10915                 reg_info = &i40e_regs_others[reg_idx++];
10916                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10917                         for (arr_idx2 = 0;
10918                                         arr_idx2 <= reg_info->count2;
10919                                         arr_idx2++) {
10920                                 reg_offset = arr_idx * reg_info->stride1 +
10921                                         arr_idx2 * reg_info->stride2;
10922                                 reg_offset += reg_info->base_addr;
10923                                 ptr_data[reg_offset >> 2] =
10924                                         I40E_READ_REG(hw, reg_offset);
10925                         }
10926         }
10927
10928         return 0;
10929 }
10930
10931 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10932 {
10933         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10934
10935         /* Convert word count to byte count */
10936         return hw->nvm.sr_size << 1;
10937 }
10938
10939 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10940                            struct rte_dev_eeprom_info *eeprom)
10941 {
10942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10943         uint16_t *data = eeprom->data;
10944         uint16_t offset, length, cnt_words;
10945         int ret_code;
10946
10947         offset = eeprom->offset >> 1;
10948         length = eeprom->length >> 1;
10949         cnt_words = length;
10950
10951         if (offset > hw->nvm.sr_size ||
10952                 offset + length > hw->nvm.sr_size) {
10953                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10954                 return -EINVAL;
10955         }
10956
10957         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10958
10959         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10960         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10961                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10962                 return -EIO;
10963         }
10964
10965         return 0;
10966 }
10967
10968 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10969                                       struct ether_addr *mac_addr)
10970 {
10971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10973         struct i40e_vsi *vsi = pf->main_vsi;
10974         struct i40e_mac_filter_info mac_filter;
10975         struct i40e_mac_filter *f;
10976         int ret;
10977
10978         if (!is_valid_assigned_ether_addr(mac_addr)) {
10979                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10980                 return;
10981         }
10982
10983         TAILQ_FOREACH(f, &vsi->mac_list, next) {
10984                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10985                         break;
10986         }
10987
10988         if (f == NULL) {
10989                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10990                 return;
10991         }
10992
10993         mac_filter = f->mac_info;
10994         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10995         if (ret != I40E_SUCCESS) {
10996                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
10997                 return;
10998         }
10999         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11000         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11001         if (ret != I40E_SUCCESS) {
11002                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11003                 return;
11004         }
11005         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11006
11007         /* Flags: 0x3 updates port address */
11008         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
11009 }
11010
11011 static int
11012 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11013 {
11014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11015         struct rte_eth_dev_data *dev_data = pf->dev_data;
11016         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11017         int ret = 0;
11018
11019         /* check if mtu is within the allowed range */
11020         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11021                 return -EINVAL;
11022
11023         /* mtu setting is forbidden if port is start */
11024         if (dev_data->dev_started) {
11025                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11026                             dev_data->port_id);
11027                 return -EBUSY;
11028         }
11029
11030         if (frame_size > ETHER_MAX_LEN)
11031                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11032         else
11033                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11034
11035         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11036
11037         return ret;
11038 }
11039
11040 /* Restore ethertype filter */
11041 static void
11042 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11043 {
11044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11045         struct i40e_ethertype_filter_list
11046                 *ethertype_list = &pf->ethertype.ethertype_list;
11047         struct i40e_ethertype_filter *f;
11048         struct i40e_control_filter_stats stats;
11049         uint16_t flags;
11050
11051         TAILQ_FOREACH(f, ethertype_list, rules) {
11052                 flags = 0;
11053                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11054                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11055                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11056                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11057                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11058
11059                 memset(&stats, 0, sizeof(stats));
11060                 i40e_aq_add_rem_control_packet_filter(hw,
11061                                             f->input.mac_addr.addr_bytes,
11062                                             f->input.ether_type,
11063                                             flags, pf->main_vsi->seid,
11064                                             f->queue, 1, &stats, NULL);
11065         }
11066         PMD_DRV_LOG(INFO, "Ethertype filter:"
11067                     " mac_etype_used = %u, etype_used = %u,"
11068                     " mac_etype_free = %u, etype_free = %u",
11069                     stats.mac_etype_used, stats.etype_used,
11070                     stats.mac_etype_free, stats.etype_free);
11071 }
11072
11073 /* Restore tunnel filter */
11074 static void
11075 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11076 {
11077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11078         struct i40e_vsi *vsi;
11079         struct i40e_pf_vf *vf;
11080         struct i40e_tunnel_filter_list
11081                 *tunnel_list = &pf->tunnel.tunnel_list;
11082         struct i40e_tunnel_filter *f;
11083         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11084         bool big_buffer = 0;
11085
11086         TAILQ_FOREACH(f, tunnel_list, rules) {
11087                 if (!f->is_to_vf)
11088                         vsi = pf->main_vsi;
11089                 else {
11090                         vf = &pf->vfs[f->vf_id];
11091                         vsi = vf->vsi;
11092                 }
11093                 memset(&cld_filter, 0, sizeof(cld_filter));
11094                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11095                         (struct ether_addr *)&cld_filter.element.outer_mac);
11096                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11097                         (struct ether_addr *)&cld_filter.element.inner_mac);
11098                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11099                 cld_filter.element.flags = f->input.flags;
11100                 cld_filter.element.tenant_id = f->input.tenant_id;
11101                 cld_filter.element.queue_number = f->queue;
11102                 rte_memcpy(cld_filter.general_fields,
11103                            f->input.general_fields,
11104                            sizeof(f->input.general_fields));
11105
11106                 if (((f->input.flags &
11107                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11108                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11109                     ((f->input.flags &
11110                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11111                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11112                     ((f->input.flags &
11113                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11114                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11115                         big_buffer = 1;
11116
11117                 if (big_buffer)
11118                         i40e_aq_add_cloud_filters_big_buffer(hw,
11119                                              vsi->seid, &cld_filter, 1);
11120                 else
11121                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11122                                                   &cld_filter.element, 1);
11123         }
11124 }
11125
11126 static void
11127 i40e_filter_restore(struct i40e_pf *pf)
11128 {
11129         i40e_ethertype_filter_restore(pf);
11130         i40e_tunnel_filter_restore(pf);
11131         i40e_fdir_filter_restore(pf);
11132 }
11133
11134 static bool
11135 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11136 {
11137         if (strcmp(dev->device->driver->name, drv->driver.name))
11138                 return false;
11139
11140         return true;
11141 }
11142
11143 bool
11144 is_i40e_supported(struct rte_eth_dev *dev)
11145 {
11146         return is_device_supported(dev, &rte_i40e_pmd);
11147 }
11148
11149 struct i40e_customized_pctype*
11150 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11151 {
11152         int i;
11153
11154         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11155                 if (pf->customized_pctype[i].index == index)
11156                         return &pf->customized_pctype[i];
11157         }
11158         return NULL;
11159 }
11160
11161 static int
11162 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11163                               uint32_t pkg_size, uint32_t proto_num,
11164                               struct rte_pmd_i40e_proto_info *proto)
11165 {
11166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11167         uint32_t pctype_num;
11168         struct rte_pmd_i40e_ptype_info *pctype;
11169         uint32_t buff_size;
11170         struct i40e_customized_pctype *new_pctype = NULL;
11171         uint8_t proto_id;
11172         uint8_t pctype_value;
11173         char name[64];
11174         uint32_t i, j, n;
11175         int ret;
11176
11177         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11178                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11179                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11180         if (ret) {
11181                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11182                 return -1;
11183         }
11184         if (!pctype_num) {
11185                 PMD_DRV_LOG(INFO, "No new pctype added");
11186                 return -1;
11187         }
11188
11189         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11190         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11191         if (!pctype) {
11192                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11193                 return -1;
11194         }
11195         /* get information about new pctype list */
11196         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11197                                         (uint8_t *)pctype, buff_size,
11198                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11199         if (ret) {
11200                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11201                 rte_free(pctype);
11202                 return -1;
11203         }
11204
11205         /* Update customized pctype. */
11206         for (i = 0; i < pctype_num; i++) {
11207                 pctype_value = pctype[i].ptype_id;
11208                 memset(name, 0, sizeof(name));
11209                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11210                         proto_id = pctype[i].protocols[j];
11211                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11212                                 continue;
11213                         for (n = 0; n < proto_num; n++) {
11214                                 if (proto[n].proto_id != proto_id)
11215                                         continue;
11216                                 strcat(name, proto[n].name);
11217                                 strcat(name, "_");
11218                                 break;
11219                         }
11220                 }
11221                 name[strlen(name) - 1] = '\0';
11222                 if (!strcmp(name, "GTPC"))
11223                         new_pctype =
11224                                 i40e_find_customized_pctype(pf,
11225                                                       I40E_CUSTOMIZED_GTPC);
11226                 else if (!strcmp(name, "GTPU_IPV4"))
11227                         new_pctype =
11228                                 i40e_find_customized_pctype(pf,
11229                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11230                 else if (!strcmp(name, "GTPU_IPV6"))
11231                         new_pctype =
11232                                 i40e_find_customized_pctype(pf,
11233                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11234                 else if (!strcmp(name, "GTPU"))
11235                         new_pctype =
11236                                 i40e_find_customized_pctype(pf,
11237                                                       I40E_CUSTOMIZED_GTPU);
11238                 if (new_pctype) {
11239                         new_pctype->pctype = pctype_value;
11240                         new_pctype->valid = true;
11241                 }
11242         }
11243
11244         rte_free(pctype);
11245         return 0;
11246 }
11247
11248 static int
11249 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11250                                uint32_t pkg_size, uint32_t proto_num,
11251                                struct rte_pmd_i40e_proto_info *proto)
11252 {
11253         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11254         uint16_t port_id = dev->data->port_id;
11255         uint32_t ptype_num;
11256         struct rte_pmd_i40e_ptype_info *ptype;
11257         uint32_t buff_size;
11258         uint8_t proto_id;
11259         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11260         uint32_t i, j, n;
11261         bool in_tunnel;
11262         int ret;
11263
11264         /* get information about new ptype num */
11265         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11266                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11267                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11268         if (ret) {
11269                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11270                 return ret;
11271         }
11272         if (!ptype_num) {
11273                 PMD_DRV_LOG(INFO, "No new ptype added");
11274                 return -1;
11275         }
11276
11277         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11278         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11279         if (!ptype) {
11280                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11281                 return -1;
11282         }
11283
11284         /* get information about new ptype list */
11285         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11286                                         (uint8_t *)ptype, buff_size,
11287                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11288         if (ret) {
11289                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11290                 rte_free(ptype);
11291                 return ret;
11292         }
11293
11294         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11295         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11296         if (!ptype_mapping) {
11297                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11298                 rte_free(ptype);
11299                 return -1;
11300         }
11301
11302         /* Update ptype mapping table. */
11303         for (i = 0; i < ptype_num; i++) {
11304                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11305                 ptype_mapping[i].sw_ptype = 0;
11306                 in_tunnel = false;
11307                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11308                         proto_id = ptype[i].protocols[j];
11309                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11310                                 continue;
11311                         for (n = 0; n < proto_num; n++) {
11312                                 if (proto[n].proto_id != proto_id)
11313                                         continue;
11314                                 memset(name, 0, sizeof(name));
11315                                 strcpy(name, proto[n].name);
11316                                 if (!strncmp(name, "PPPOE", 5))
11317                                         ptype_mapping[i].sw_ptype |=
11318                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11319                                 else if (!strncmp(name, "OIPV4", 5)) {
11320                                         ptype_mapping[i].sw_ptype |=
11321                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11322                                         in_tunnel = true;
11323                                 } else if (!strncmp(name, "IPV4", 4) &&
11324                                            !in_tunnel)
11325                                         ptype_mapping[i].sw_ptype |=
11326                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11327                                 else if (!strncmp(name, "IPV4FRAG", 8) &&
11328                                          in_tunnel) {
11329                                         ptype_mapping[i].sw_ptype |=
11330                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11331                                         ptype_mapping[i].sw_ptype |=
11332                                                 RTE_PTYPE_INNER_L4_FRAG;
11333                                 } else if (!strncmp(name, "IPV4", 4) &&
11334                                            in_tunnel)
11335                                         ptype_mapping[i].sw_ptype |=
11336                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11337                                 else if (!strncmp(name, "OIPV6", 5)) {
11338                                         ptype_mapping[i].sw_ptype |=
11339                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11340                                         in_tunnel = true;
11341                                 } else if (!strncmp(name, "IPV6", 4) &&
11342                                            !in_tunnel)
11343                                         ptype_mapping[i].sw_ptype |=
11344                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11345                                 else if (!strncmp(name, "IPV6FRAG", 8) &&
11346                                          in_tunnel) {
11347                                         ptype_mapping[i].sw_ptype |=
11348                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11349                                         ptype_mapping[i].sw_ptype |=
11350                                                 RTE_PTYPE_INNER_L4_FRAG;
11351                                 } else if (!strncmp(name, "IPV6", 4) &&
11352                                            in_tunnel)
11353                                         ptype_mapping[i].sw_ptype |=
11354                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11355                                 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11356                                         ptype_mapping[i].sw_ptype |=
11357                                                 RTE_PTYPE_L4_UDP;
11358                                 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11359                                         ptype_mapping[i].sw_ptype |=
11360                                                 RTE_PTYPE_INNER_L4_UDP;
11361                                 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11362                                         ptype_mapping[i].sw_ptype |=
11363                                                 RTE_PTYPE_L4_TCP;
11364                                 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11365                                         ptype_mapping[i].sw_ptype |=
11366                                                 RTE_PTYPE_INNER_L4_TCP;
11367                                 else if (!strncmp(name, "SCTP", 4) &&
11368                                          !in_tunnel)
11369                                         ptype_mapping[i].sw_ptype |=
11370                                                 RTE_PTYPE_L4_SCTP;
11371                                 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11372                                         ptype_mapping[i].sw_ptype |=
11373                                                 RTE_PTYPE_INNER_L4_SCTP;
11374                                 else if ((!strncmp(name, "ICMP", 4) ||
11375                                           !strncmp(name, "ICMPV6", 6)) &&
11376                                          !in_tunnel)
11377                                         ptype_mapping[i].sw_ptype |=
11378                                                 RTE_PTYPE_L4_ICMP;
11379                                 else if ((!strncmp(name, "ICMP", 4) ||
11380                                           !strncmp(name, "ICMPV6", 6)) &&
11381                                          in_tunnel)
11382                                         ptype_mapping[i].sw_ptype |=
11383                                                 RTE_PTYPE_INNER_L4_ICMP;
11384                                 else if (!strncmp(name, "GTPC", 4)) {
11385                                         ptype_mapping[i].sw_ptype |=
11386                                                 RTE_PTYPE_TUNNEL_GTPC;
11387                                         in_tunnel = true;
11388                                 } else if (!strncmp(name, "GTPU", 4)) {
11389                                         ptype_mapping[i].sw_ptype |=
11390                                                 RTE_PTYPE_TUNNEL_GTPU;
11391                                         in_tunnel = true;
11392                                 } else if (!strncmp(name, "GRENAT", 6)) {
11393                                         ptype_mapping[i].sw_ptype |=
11394                                                 RTE_PTYPE_TUNNEL_GRENAT;
11395                                         in_tunnel = true;
11396                                 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11397                                         ptype_mapping[i].sw_ptype |=
11398                                                 RTE_PTYPE_TUNNEL_L2TP;
11399                                         in_tunnel = true;
11400                                 }
11401
11402                                 break;
11403                         }
11404                 }
11405         }
11406
11407         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11408                                                 ptype_num, 0);
11409         if (ret)
11410                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11411
11412         rte_free(ptype_mapping);
11413         rte_free(ptype);
11414         return ret;
11415 }
11416
11417 void
11418 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11419                               uint32_t pkg_size)
11420 {
11421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11422         uint32_t proto_num;
11423         struct rte_pmd_i40e_proto_info *proto;
11424         uint32_t buff_size;
11425         uint32_t i;
11426         int ret;
11427
11428         /* get information about protocol number */
11429         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11430                                        (uint8_t *)&proto_num, sizeof(proto_num),
11431                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11432         if (ret) {
11433                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11434                 return;
11435         }
11436         if (!proto_num) {
11437                 PMD_DRV_LOG(INFO, "No new protocol added");
11438                 return;
11439         }
11440
11441         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11442         proto = rte_zmalloc("new_proto", buff_size, 0);
11443         if (!proto) {
11444                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11445                 return;
11446         }
11447
11448         /* get information about protocol list */
11449         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11450                                         (uint8_t *)proto, buff_size,
11451                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11452         if (ret) {
11453                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11454                 rte_free(proto);
11455                 return;
11456         }
11457
11458         /* Check if GTP is supported. */
11459         for (i = 0; i < proto_num; i++) {
11460                 if (!strncmp(proto[i].name, "GTP", 3)) {
11461                         pf->gtp_support = true;
11462                         break;
11463                 }
11464         }
11465
11466         /* Update customized pctype info */
11467         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11468                                             proto_num, proto);
11469         if (ret)
11470                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11471
11472         /* Update customized ptype info */
11473         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11474                                            proto_num, proto);
11475         if (ret)
11476                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11477
11478         rte_free(proto);
11479 }
11480
11481 /* Create a QinQ cloud filter
11482  *
11483  * The Fortville NIC has limited resources for tunnel filters,
11484  * so we can only reuse existing filters.
11485  *
11486  * In step 1 we define which Field Vector fields can be used for
11487  * filter types.
11488  * As we do not have the inner tag defined as a field,
11489  * we have to define it first, by reusing one of L1 entries.
11490  *
11491  * In step 2 we are replacing one of existing filter types with
11492  * a new one for QinQ.
11493  * As we reusing L1 and replacing L2, some of the default filter
11494  * types will disappear,which depends on L1 and L2 entries we reuse.
11495  *
11496  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11497  *
11498  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11499  *              later when we define the cloud filter.
11500  *      a.      Valid_flags.replace_cloud = 0
11501  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11502  *      c.      New_filter = 0x10
11503  *      d.      TR bit = 0xff (optional, not used here)
11504  *      e.      Buffer – 2 entries:
11505  *              i.      Byte 0 = 8 (outer vlan FV index).
11506  *                      Byte 1 = 0 (rsv)
11507  *                      Byte 2-3 = 0x0fff
11508  *              ii.     Byte 0 = 37 (inner vlan FV index).
11509  *                      Byte 1 =0 (rsv)
11510  *                      Byte 2-3 = 0x0fff
11511  *
11512  * Step 2:
11513  * 2.   Create cloud filter using two L1 filters entries: stag and
11514  *              new filter(outer vlan+ inner vlan)
11515  *      a.      Valid_flags.replace_cloud = 1
11516  *      b.      Old_filter = 1 (instead of outer IP)
11517  *      c.      New_filter = 0x10
11518  *      d.      Buffer – 2 entries:
11519  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11520  *                      Byte 1-3 = 0 (rsv)
11521  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11522  *                      Byte 9-11 = 0 (rsv)
11523  */
11524 static int
11525 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11526 {
11527         int ret = -ENOTSUP;
11528         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11529         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11530         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11531
11532         /* Init */
11533         memset(&filter_replace, 0,
11534                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11535         memset(&filter_replace_buf, 0,
11536                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11537
11538         /* create L1 filter */
11539         filter_replace.old_filter_type =
11540                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11541         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11542         filter_replace.tr_bit = 0;
11543
11544         /* Prepare the buffer, 2 entries */
11545         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11546         filter_replace_buf.data[0] |=
11547                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11548         /* Field Vector 12b mask */
11549         filter_replace_buf.data[2] = 0xff;
11550         filter_replace_buf.data[3] = 0x0f;
11551         filter_replace_buf.data[4] =
11552                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11553         filter_replace_buf.data[4] |=
11554                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11555         /* Field Vector 12b mask */
11556         filter_replace_buf.data[6] = 0xff;
11557         filter_replace_buf.data[7] = 0x0f;
11558         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11559                         &filter_replace_buf);
11560         if (ret != I40E_SUCCESS)
11561                 return ret;
11562
11563         /* Apply the second L2 cloud filter */
11564         memset(&filter_replace, 0,
11565                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11566         memset(&filter_replace_buf, 0,
11567                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11568
11569         /* create L2 filter, input for L2 filter will be L1 filter  */
11570         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11571         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11572         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11573
11574         /* Prepare the buffer, 2 entries */
11575         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11576         filter_replace_buf.data[0] |=
11577                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11578         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11579         filter_replace_buf.data[4] |=
11580                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11581         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11582                         &filter_replace_buf);
11583         return ret;
11584 }
11585
11586 RTE_INIT(i40e_init_log);
11587 static void
11588 i40e_init_log(void)
11589 {
11590         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11591         if (i40e_logtype_init >= 0)
11592                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11593         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11594         if (i40e_logtype_driver >= 0)
11595                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11596 }