drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_eal.h>
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_ethdev_pci.h>
  49 #include <rte_memzone.h>
  50 #include <rte_malloc.h>
  51 #include <rte_memcpy.h>
  52 #include <rte_alarm.h>
  53 #include <rte_dev.h>
  54 #include <rte_eth_ctrl.h>
  55 #include <rte_tailq.h>
  56 #include <rte_hash_crc.h>
  57
  58 #include "i40e_logs.h"
  59 #include "base/i40e_prototype.h"
  60 #include "base/i40e_adminq_cmd.h"
  61 #include "base/i40e_type.h"
  62 #include "base/i40e_register.h"
  63 #include "base/i40e_dcb.h"
  64 #include "i40e_ethdev.h"
  65 #include "i40e_rxtx.h"
  66 #include "i40e_pf.h"
  67 #include "i40e_regs.h"
  68
  69 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  70 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  71
  72 #define I40E_CLEAR_PXE_WAIT_MS     200
  73
  74 /* Maximun number of capability elements */
  75 #define I40E_MAX_CAP_ELE_NUM       128
  76
  77 /* Wait count and interval */
  78 #define I40E_CHK_Q_ENA_COUNT       1000
  79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  80
  81 /* Maximun number of VSI */
  82 #define I40E_MAX_NUM_VSIS          (384UL)
  83
  84 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  85
  86 /* Flow control default timer */
  87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  88
  89 /* Flow control enable fwd bit */
  90 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  91
  92 /* Receive Packet Buffer size */
  93 #define I40E_RXPBSIZE (968 * 1024)
  94
  95 /* Kilobytes shift */
  96 #define I40E_KILOSHIFT 10
  97
  98 /* Flow control default high water */
  99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
 100
 101 /* Flow control default low water */
 102 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
 103
 104 /* Receive Average Packet Size in Byte*/
 105 #define I40E_PACKET_AVERAGE_SIZE 128
 106
 107 /* Mask of PF interrupt causes */
 108 #define I40E_PFINT_ICR0_ENA_MASK ( \
 109                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 110                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 112                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 113                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 114                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 117                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 118
 119 #define I40E_FLOW_TYPES ( \
 120         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 125         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 129         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 130         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 131
 132 /* Additional timesync values. */
 133 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 134 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 135 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 136 #define I40E_PRTTSYN_TSYNENA     0x80000000
 137 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 138 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 139
 140 #define I40E_MAX_PERCENT            100
 141 #define I40E_DEFAULT_DCB_APP_NUM    1
 142 #define I40E_DEFAULT_DCB_APP_PRIO   3
 143
 144 /**
 145  * Below are values for writing un-exposed registers suggested
 146  * by silicon experts
 147  */
 148 /* Destination MAC address */
 149 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 150 /* Source MAC address */
 151 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 153 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 155 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 156 /* Single VLAN tag in the inner L2 header */
 157 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 158 /* Source IPv4 address */
 159 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 160 /* Destination IPv4 address */
 161 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 162 /* Source IPv4 address for X722 */
 163 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 164 /* Destination IPv4 address for X722 */
 165 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 166 /* IPv4 Protocol for X722 */
 167 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 168 /* IPv4 Time to Live for X722 */
 169 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 170 /* IPv4 Type of Service (TOS) */
 171 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 172 /* IPv4 Protocol */
 173 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 174 /* IPv4 Time to Live */
 175 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 176 /* Source IPv6 address */
 177 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 178 /* Destination IPv6 address */
 179 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 180 /* IPv6 Traffic Class (TC) */
 181 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 182 /* IPv6 Next Header */
 183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 184 /* IPv6 Hop Limit */
 185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 186 /* Source L4 port */
 187 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 188 /* Destination L4 port */
 189 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 190 /* SCTP verification tag */
 191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 194 /* Source port of tunneling UDP */
 195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 196 /* Destination port of tunneling UDP */
 197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 198 /* UDP Tunneling ID, NVGRE/GRE key */
 199 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 200 /* Last ether type */
 201 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 202 /* Tunneling outer destination IPv4 address */
 203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 204 /* Tunneling outer destination IPv6 address */
 205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 206 /* 1st word of flex payload */
 207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 208 /* 2nd word of flex payload */
 209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 210 /* 3rd word of flex payload */
 211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 212 /* 4th word of flex payload */
 213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 214 /* 5th word of flex payload */
 215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 216 /* 6th word of flex payload */
 217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 218 /* 7th word of flex payload */
 219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 220 /* 8th word of flex payload */
 221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 222 /* all 8 words flex payload */
 223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 224 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 225
 226 #define I40E_TRANSLATE_INSET 0
 227 #define I40E_TRANSLATE_REG   1
 228
 229 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 230 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 231 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 232 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 234 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 235
 236 /* PCI offset for querying capability */
 237 #define PCI_DEV_CAP_REG            0xA4
 238 /* PCI offset for enabling/disabling Extended Tag */
 239 #define PCI_DEV_CTRL_REG           0xA8
 240 /* Bit mask of Extended Tag capability */
 241 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 242 /* Bit shift of Extended Tag enable/disable */
 243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 244 /* Bit mask of Extended Tag enable/disable */
 245 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 246
 247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int i40e_dev_configure(struct rte_eth_dev *dev);
 250 static int i40e_dev_start(struct rte_eth_dev *dev);
 251 static void i40e_dev_stop(struct rte_eth_dev *dev);
 252 static void i40e_dev_close(struct rte_eth_dev *dev);
 253 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_stats *stats);
 262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 263                                struct rte_eth_xstat *xstats, unsigned n);
 264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 265                                      struct rte_eth_xstat_name *xstats_names,
 266                                      unsigned limit);
 267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id,
 270                                             uint8_t stat_idx,
 271                                             uint8_t is_rx);
 272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 273                                 char *fw_version, size_t fw_size);
 274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 275                               struct rte_eth_dev_info *dev_info);
 276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 277                                 uint16_t vlan_id,
 278                                 int on);
 279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 280                               enum rte_vlan_type vlan_type,
 281                               uint16_t tpid);
 282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 284                                       uint16_t queue,
 285                                       int on);
 286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 292                               struct rte_eth_fc_conf *fc_conf);
 293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 294                                        struct rte_eth_pfc_conf *pfc_conf);
 295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 296                             struct ether_addr *mac_addr,
 297                             uint32_t index,
 298                             uint32_t pool);
 299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 301                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 302                                     uint16_t reta_size);
 303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 304                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 305                                    uint16_t reta_size);
 306
 307 static int i40e_get_cap(struct i40e_hw *hw);
 308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 309 static int i40e_pf_setup(struct i40e_pf *pf);
 310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 315                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 316 static void i40e_stat_update_48(struct i40e_hw *hw,
 317                                uint32_t hireg,
 318                                uint32_t loreg,
 319                                bool offset_loaded,
 320                                uint64_t *offset,
 321                                uint64_t *stat);
 322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 323 static void i40e_dev_interrupt_handler(void *param);
 324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 325                                 uint32_t base, uint32_t num);
 326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 328                         uint32_t base);
 329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 330                         uint16_t num);
 331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 332 static int i40e_veb_release(struct i40e_veb *veb);
 333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 334                                                 struct i40e_vsi *vsi);
 335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 338                                              struct i40e_macvlan_filter *mv_f,
 339                                              int num,
 340                                              uint16_t vlan);
 341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 343                                     struct rte_eth_rss_conf *rss_conf);
 344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 345                                       struct rte_eth_rss_conf *rss_conf);
 346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 347                                         struct rte_eth_udp_tunnel *udp_tunnel);
 348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 349                                         struct rte_eth_udp_tunnel *udp_tunnel);
 350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 352                                 enum rte_filter_op filter_op,
 353                                 void *arg);
 354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 355                                 enum rte_filter_type filter_type,
 356                                 enum rte_filter_op filter_op,
 357                                 void *arg);
 358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 359                                   struct rte_eth_dcb_info *dcb_info);
 360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 361 static void i40e_configure_registers(struct i40e_hw *hw);
 362 static void i40e_hw_init(struct rte_eth_dev *dev);
 363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 364 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 365                         struct rte_eth_mirror_conf *mirror_conf,
 366                         uint8_t sw_id, uint8_t on);
 367 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 368
 369 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 370 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 371 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 372                                            struct timespec *timestamp,
 373                                            uint32_t flags);
 374 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp);
 376 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 377
 378 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 379
 380 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 381                                    struct timespec *timestamp);
 382 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 383                                     const struct timespec *timestamp);
 384
 385 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 386                                          uint16_t queue_id);
 387 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 388                                           uint16_t queue_id);
 389
 390 static int i40e_get_regs(struct rte_eth_dev *dev,
 391                          struct rte_dev_reg_info *regs);
 392
 393 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 394
 395 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 396                            struct rte_dev_eeprom_info *eeprom);
 397
 398 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 399                                       struct ether_addr *mac_addr);
 400
 401 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 402
 403 static int i40e_ethertype_filter_convert(
 404         const struct rte_eth_ethertype_filter *input,
 405         struct i40e_ethertype_filter *filter);
 406 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 407                                    struct i40e_ethertype_filter *filter);
 408
 409 static int i40e_tunnel_filter_convert(
 410         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 411         struct i40e_tunnel_filter *tunnel_filter);
 412 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 413                                 struct i40e_tunnel_filter *tunnel_filter);
 414 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 415
 416 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 417 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 418 static void i40e_filter_restore(struct i40e_pf *pf);
 419 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 420
 421 int i40e_logtype_init;
 422 int i40e_logtype_driver;
 423
 424 static const struct rte_pci_id pci_id_i40e_map[] = {
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 445         { .vendor_id = 0, /* sentinel */ },
 446 };
 447
 448 static const struct eth_dev_ops i40e_eth_dev_ops = {
 449         .dev_configure                = i40e_dev_configure,
 450         .dev_start                    = i40e_dev_start,
 451         .dev_stop                     = i40e_dev_stop,
 452         .dev_close                    = i40e_dev_close,
 453         .dev_reset                    = i40e_dev_reset,
 454         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 455         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 456         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 457         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 458         .dev_set_link_up              = i40e_dev_set_link_up,
 459         .dev_set_link_down            = i40e_dev_set_link_down,
 460         .link_update                  = i40e_dev_link_update,
 461         .stats_get                    = i40e_dev_stats_get,
 462         .xstats_get                   = i40e_dev_xstats_get,
 463         .xstats_get_names             = i40e_dev_xstats_get_names,
 464         .stats_reset                  = i40e_dev_stats_reset,
 465         .xstats_reset                 = i40e_dev_stats_reset,
 466         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .mirror_rule_set              = i40e_mirror_rule_set,
 506         .mirror_rule_reset            = i40e_mirror_rule_reset,
 507         .timesync_enable              = i40e_timesync_enable,
 508         .timesync_disable             = i40e_timesync_disable,
 509         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 510         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 511         .get_dcb_info                 = i40e_dev_get_dcb_info,
 512         .timesync_adjust_time         = i40e_timesync_adjust_time,
 513         .timesync_read_time           = i40e_timesync_read_time,
 514         .timesync_write_time          = i40e_timesync_write_time,
 515         .get_reg                      = i40e_get_regs,
 516         .get_eeprom_length            = i40e_get_eeprom_length,
 517         .get_eeprom                   = i40e_get_eeprom,
 518         .mac_addr_set                 = i40e_set_default_mac_addr,
 519         .mtu_set                      = i40e_dev_mtu_set,
 520         .tm_ops_get                   = i40e_tm_ops_get,
 521 };
 522
 523 /* store statistics names and its offset in stats structure */
 524 struct rte_i40e_xstats_name_off {
 525         char name[RTE_ETH_XSTATS_NAME_SIZE];
 526         unsigned offset;
 527 };
 528
 529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 530         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 531         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 532         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 533         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 534         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 535                 rx_unknown_protocol)},
 536         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 537         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 538         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 539         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 540 };
 541
 542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 543                 sizeof(rte_i40e_stats_strings[0]))
 544
 545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 546         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 547                 tx_dropped_link_down)},
 548         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 549         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 550                 illegal_bytes)},
 551         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 552         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_local_faults)},
 554         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_remote_faults)},
 556         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_length_errors)},
 558         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 559         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 560         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 561         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 562         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 563         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_127)},
 565         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_255)},
 567         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_511)},
 569         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1023)},
 571         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1522)},
 573         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_big)},
 575         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_undersize)},
 577         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_oversize)},
 579         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 580                 mac_short_packet_dropped)},
 581         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_fragments)},
 583         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 584         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 585         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_127)},
 587         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_255)},
 589         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_511)},
 591         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1023)},
 593         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1522)},
 595         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_big)},
 597         {"rx_flow_director_atr_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 599         {"rx_flow_director_sb_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 601         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_status)},
 603         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_status)},
 605         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_count)},
 607         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_count)},
 609 };
 610
 611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 612                 sizeof(rte_i40e_hw_port_strings[0]))
 613
 614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 615         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xon_rx)},
 617         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xoff_rx)},
 619 };
 620
 621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 622                 sizeof(rte_i40e_rxq_prio_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_tx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_tx)},
 629         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_2_xoff)},
 631 };
 632
 633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 634                 sizeof(rte_i40e_txq_prio_strings[0]))
 635
 636 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 637         struct rte_pci_device *pci_dev)
 638 {
 639         return rte_eth_dev_pci_generic_probe(pci_dev,
 640                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 641 }
 642
 643 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 644 {
 645         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 646 }
 647
 648 static struct rte_pci_driver rte_i40e_pmd = {
 649         .id_table = pci_id_i40e_map,
 650         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 651         .probe = eth_i40e_pci_probe,
 652         .remove = eth_i40e_pci_remove,
 653 };
 654
 655 static inline int
 656 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 657                                      struct rte_eth_link *link)
 658 {
 659         struct rte_eth_link *dst = link;
 660         struct rte_eth_link *src = &(dev->data->dev_link);
 661
 662         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 663                                         *(uint64_t *)src) == 0)
 664                 return -1;
 665
 666         return 0;
 667 }
 668
 669 static inline int
 670 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 671                                       struct rte_eth_link *link)
 672 {
 673         struct rte_eth_link *dst = &(dev->data->dev_link);
 674         struct rte_eth_link *src = link;
 675
 676         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 677                                         *(uint64_t *)src) == 0)
 678                 return -1;
 679
 680         return 0;
 681 }
 682
 683 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 684 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 685 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 686
 687 #ifndef I40E_GLQF_ORT
 688 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 689 #endif
 690 #ifndef I40E_GLQF_PIT
 691 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 692 #endif
 693 #ifndef I40E_GLQF_L3_MAP
 694 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 695 #endif
 696
 697 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 698 {
 699         /*
 700          * Initialize registers for flexible payload, which should be set by NVM.
 701          * This should be removed from code once it is fixed in NVM.
 702          */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 704         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 705         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 706         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 707         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 708         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 709         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 710         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 711         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 712         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 713         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 714         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 715
 716         /* Initialize registers for parsing packet type of QinQ */
 717         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 718         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 719 }
 720
 721 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 722
 723 /*
 724  * Add a ethertype filter to drop all flow control frames transmitted
 725  * from VSIs.
 726 */
 727 static void
 728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 729 {
 730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 731         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 732                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 733                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 734         int ret;
 735
 736         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 737                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 738                                 pf->main_vsi_seid, 0,
 739                                 TRUE, NULL, NULL);
 740         if (ret)
 741                 PMD_INIT_LOG(ERR,
 742                         "Failed to add filter to drop flow control frames from VSIs.");
 743 }
 744
 745 static int
 746 floating_veb_list_handler(__rte_unused const char *key,
 747                           const char *floating_veb_value,
 748                           void *opaque)
 749 {
 750         int idx = 0;
 751         unsigned int count = 0;
 752         char *end = NULL;
 753         int min, max;
 754         bool *vf_floating_veb = opaque;
 755
 756         while (isblank(*floating_veb_value))
 757                 floating_veb_value++;
 758
 759         /* Reset floating VEB configuration for VFs */
 760         for (idx = 0; idx < I40E_MAX_VF; idx++)
 761                 vf_floating_veb[idx] = false;
 762
 763         min = I40E_MAX_VF;
 764         do {
 765                 while (isblank(*floating_veb_value))
 766                         floating_veb_value++;
 767                 if (*floating_veb_value == '\0')
 768                         return -1;
 769                 errno = 0;
 770                 idx = strtoul(floating_veb_value, &end, 10);
 771                 if (errno || end == NULL)
 772                         return -1;
 773                 while (isblank(*end))
 774                         end++;
 775                 if (*end == '-') {
 776                         min = idx;
 777                 } else if ((*end == ';') || (*end == '\0')) {
 778                         max = idx;
 779                         if (min == I40E_MAX_VF)
 780                                 min = idx;
 781                         if (max >= I40E_MAX_VF)
 782                                 max = I40E_MAX_VF - 1;
 783                         for (idx = min; idx <= max; idx++) {
 784                                 vf_floating_veb[idx] = true;
 785                                 count++;
 786                         }
 787                         min = I40E_MAX_VF;
 788                 } else {
 789                         return -1;
 790                 }
 791                 floating_veb_value = end + 1;
 792         } while (*end != '\0');
 793
 794         if (count == 0)
 795                 return -1;
 796
 797         return 0;
 798 }
 799
 800 static void
 801 config_vf_floating_veb(struct rte_devargs *devargs,
 802                        uint16_t floating_veb,
 803                        bool *vf_floating_veb)
 804 {
 805         struct rte_kvargs *kvlist;
 806         int i;
 807         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 808
 809         if (!floating_veb)
 810                 return;
 811         /* All the VFs attach to the floating VEB by default
 812          * when the floating VEB is enabled.
 813          */
 814         for (i = 0; i < I40E_MAX_VF; i++)
 815                 vf_floating_veb[i] = true;
 816
 817         if (devargs == NULL)
 818                 return;
 819
 820         kvlist = rte_kvargs_parse(devargs->args, NULL);
 821         if (kvlist == NULL)
 822                 return;
 823
 824         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 825                 rte_kvargs_free(kvlist);
 826                 return;
 827         }
 828         /* When the floating_veb_list parameter exists, all the VFs
 829          * will attach to the legacy VEB firstly, then configure VFs
 830          * to the floating VEB according to the floating_veb_list.
 831          */
 832         if (rte_kvargs_process(kvlist, floating_veb_list,
 833                                floating_veb_list_handler,
 834                                vf_floating_veb) < 0) {
 835                 rte_kvargs_free(kvlist);
 836                 return;
 837         }
 838         rte_kvargs_free(kvlist);
 839 }
 840
 841 static int
 842 i40e_check_floating_handler(__rte_unused const char *key,
 843                             const char *value,
 844                             __rte_unused void *opaque)
 845 {
 846         if (strcmp(value, "1"))
 847                 return -1;
 848
 849         return 0;
 850 }
 851
 852 static int
 853 is_floating_veb_supported(struct rte_devargs *devargs)
 854 {
 855         struct rte_kvargs *kvlist;
 856         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 857
 858         if (devargs == NULL)
 859                 return 0;
 860
 861         kvlist = rte_kvargs_parse(devargs->args, NULL);
 862         if (kvlist == NULL)
 863                 return 0;
 864
 865         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 866                 rte_kvargs_free(kvlist);
 867                 return 0;
 868         }
 869         /* Floating VEB is enabled when there's key-value:
 870          * enable_floating_veb=1
 871          */
 872         if (rte_kvargs_process(kvlist, floating_veb_key,
 873                                i40e_check_floating_handler, NULL) < 0) {
 874                 rte_kvargs_free(kvlist);
 875                 return 0;
 876         }
 877         rte_kvargs_free(kvlist);
 878
 879         return 1;
 880 }
 881
 882 static void
 883 config_floating_veb(struct rte_eth_dev *dev)
 884 {
 885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 886         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 887         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 888
 889         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 890
 891         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 892                 pf->floating_veb =
 893                         is_floating_veb_supported(pci_dev->device.devargs);
 894                 config_vf_floating_veb(pci_dev->device.devargs,
 895                                        pf->floating_veb,
 896                                        pf->floating_veb_list);
 897         } else {
 898                 pf->floating_veb = false;
 899         }
 900 }
 901
 902 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 903 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 904
 905 static int
 906 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 907 {
 908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 909         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 910         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 911         int ret;
 912
 913         struct rte_hash_parameters ethertype_hash_params = {
 914                 .name = ethertype_hash_name,
 915                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 916                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 917                 .hash_func = rte_hash_crc,
 918                 .hash_func_init_val = 0,
 919                 .socket_id = rte_socket_id(),
 920         };
 921
 922         /* Initialize ethertype filter rule list and hash */
 923         TAILQ_INIT(&ethertype_rule->ethertype_list);
 924         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 925                  "ethertype_%s", dev->device->name);
 926         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 927         if (!ethertype_rule->hash_table) {
 928                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 929                 return -EINVAL;
 930         }
 931         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 932                                        sizeof(struct i40e_ethertype_filter *) *
 933                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 934                                        0);
 935         if (!ethertype_rule->hash_map) {
 936                 PMD_INIT_LOG(ERR,
 937                              "Failed to allocate memory for ethertype hash map!");
 938                 ret = -ENOMEM;
 939                 goto err_ethertype_hash_map_alloc;
 940         }
 941
 942         return 0;
 943
 944 err_ethertype_hash_map_alloc:
 945         rte_hash_free(ethertype_rule->hash_table);
 946
 947         return ret;
 948 }
 949
 950 static int
 951 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 955         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters tunnel_hash_params = {
 959                 .name = tunnel_hash_name,
 960                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 962                 .hash_func = rte_hash_crc,
 963                 .hash_func_init_val = 0,
 964                 .socket_id = rte_socket_id(),
 965         };
 966
 967         /* Initialize tunnel filter rule list and hash */
 968         TAILQ_INIT(&tunnel_rule->tunnel_list);
 969         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 970                  "tunnel_%s", dev->device->name);
 971         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 972         if (!tunnel_rule->hash_table) {
 973                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 974                 return -EINVAL;
 975         }
 976         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 977                                     sizeof(struct i40e_tunnel_filter *) *
 978                                     I40E_MAX_TUNNEL_FILTER_NUM,
 979                                     0);
 980         if (!tunnel_rule->hash_map) {
 981                 PMD_INIT_LOG(ERR,
 982                              "Failed to allocate memory for tunnel hash map!");
 983                 ret = -ENOMEM;
 984                 goto err_tunnel_hash_map_alloc;
 985         }
 986
 987         return 0;
 988
 989 err_tunnel_hash_map_alloc:
 990         rte_hash_free(tunnel_rule->hash_table);
 991
 992         return ret;
 993 }
 994
 995 static int
 996 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 997 {
 998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 999         struct i40e_fdir_info *fdir_info = &pf->fdir;
1000         char fdir_hash_name[RTE_HASH_NAMESIZE];
1001         int ret;
1002
1003         struct rte_hash_parameters fdir_hash_params = {
1004                 .name = fdir_hash_name,
1005                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1006                 .key_len = sizeof(struct rte_eth_fdir_input),
1007                 .hash_func = rte_hash_crc,
1008                 .hash_func_init_val = 0,
1009                 .socket_id = rte_socket_id(),
1010         };
1011
1012         /* Initialize flow director filter rule list and hash */
1013         TAILQ_INIT(&fdir_info->fdir_list);
1014         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1015                  "fdir_%s", dev->device->name);
1016         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1017         if (!fdir_info->hash_table) {
1018                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1019                 return -EINVAL;
1020         }
1021         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1022                                           sizeof(struct i40e_fdir_filter *) *
1023                                           I40E_MAX_FDIR_FILTER_NUM,
1024                                           0);
1025         if (!fdir_info->hash_map) {
1026                 PMD_INIT_LOG(ERR,
1027                              "Failed to allocate memory for fdir hash map!");
1028                 ret = -ENOMEM;
1029                 goto err_fdir_hash_map_alloc;
1030         }
1031         return 0;
1032
1033 err_fdir_hash_map_alloc:
1034         rte_hash_free(fdir_info->hash_table);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 eth_i40e_dev_init(struct rte_eth_dev *dev)
1041 {
1042         struct rte_pci_device *pci_dev;
1043         struct rte_intr_handle *intr_handle;
1044         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046         struct i40e_vsi *vsi;
1047         int ret;
1048         uint32_t len;
1049         uint8_t aq_fail = 0;
1050
1051         PMD_INIT_FUNC_TRACE();
1052
1053         dev->dev_ops = &i40e_eth_dev_ops;
1054         dev->rx_pkt_burst = i40e_recv_pkts;
1055         dev->tx_pkt_burst = i40e_xmit_pkts;
1056         dev->tx_pkt_prepare = i40e_prep_pkts;
1057
1058         /* for secondary processes, we don't initialise any further as primary
1059          * has already done this work. Only check we don't need a different
1060          * RX function */
1061         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1062                 i40e_set_rx_function(dev);
1063                 i40e_set_tx_function(dev);
1064                 return 0;
1065         }
1066         i40e_set_default_ptype_table(dev);
1067         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1068         intr_handle = &pci_dev->intr_handle;
1069
1070         rte_eth_copy_pci_info(dev, pci_dev);
1071         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1072
1073         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074         pf->adapter->eth_dev = dev;
1075         pf->dev_data = dev->data;
1076
1077         hw->back = I40E_PF_TO_ADAPTER(pf);
1078         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1079         if (!hw->hw_addr) {
1080                 PMD_INIT_LOG(ERR,
1081                         "Hardware is not available, as address is NULL");
1082                 return -ENODEV;
1083         }
1084
1085         hw->vendor_id = pci_dev->id.vendor_id;
1086         hw->device_id = pci_dev->id.device_id;
1087         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1088         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1089         hw->bus.device = pci_dev->addr.devid;
1090         hw->bus.func = pci_dev->addr.function;
1091         hw->adapter_stopped = 0;
1092
1093         /* Make sure all is clean before doing PF reset */
1094         i40e_clear_hw(hw);
1095
1096         /* Initialize the hardware */
1097         i40e_hw_init(dev);
1098
1099         /* Reset here to make sure all is clean for each PF */
1100         ret = i40e_pf_reset(hw);
1101         if (ret) {
1102                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103                 return ret;
1104         }
1105
1106         /* Initialize the shared code (base driver) */
1107         ret = i40e_init_shared_code(hw);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1110                 return ret;
1111         }
1112
1113         /*
1114          * To work around the NVM issue, initialize registers
1115          * for flexible payload and packet type of QinQ by
1116          * software. It should be removed once issues are fixed
1117          * in NVM.
1118          */
1119         i40e_GLQF_reg_init(hw);
1120
1121         /* Initialize the input set for filters (hash and fd) to default value */
1122         i40e_filter_input_set_init(pf);
1123
1124         /* Initialize the parameters for adminq */
1125         i40e_init_adminq_parameter(hw);
1126         ret = i40e_init_adminq(hw);
1127         if (ret != I40E_SUCCESS) {
1128                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1129                 return -EIO;
1130         }
1131         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1132                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1133                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1134                      ((hw->nvm.version >> 12) & 0xf),
1135                      ((hw->nvm.version >> 4) & 0xff),
1136                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1137
1138         /* initialise the L3_MAP register */
1139         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1140                                    0x00000028,  NULL);
1141         if (ret)
1142                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1143
1144         /* Need the special FW version to support floating VEB */
1145         config_floating_veb(dev);
1146         /* Clear PXE mode */
1147         i40e_clear_pxe_mode(hw);
1148         i40e_dev_sync_phy_type(hw);
1149
1150         /*
1151          * On X710, performance number is far from the expectation on recent
1152          * firmware versions. The fix for this issue may not be integrated in
1153          * the following firmware version. So the workaround in software driver
1154          * is needed. It needs to modify the initial values of 3 internal only
1155          * registers. Note that the workaround can be removed when it is fixed
1156          * in firmware in the future.
1157          */
1158         i40e_configure_registers(hw);
1159
1160         /* Get hw capabilities */
1161         ret = i40e_get_cap(hw);
1162         if (ret != I40E_SUCCESS) {
1163                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164                 goto err_get_capabilities;
1165         }
1166
1167         /* Initialize parameters for PF */
1168         ret = i40e_pf_parameter_init(dev);
1169         if (ret != 0) {
1170                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171                 goto err_parameter_init;
1172         }
1173
1174         /* Initialize the queue management */
1175         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1176         if (ret < 0) {
1177                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178                 goto err_qp_pool_init;
1179         }
1180         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181                                 hw->func_caps.num_msix_vectors - 1);
1182         if (ret < 0) {
1183                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184                 goto err_msix_pool_init;
1185         }
1186
1187         /* Initialize lan hmc */
1188         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189                                 hw->func_caps.num_rx_qp, 0, 0);
1190         if (ret != I40E_SUCCESS) {
1191                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192                 goto err_init_lan_hmc;
1193         }
1194
1195         /* Configure lan hmc */
1196         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199                 goto err_configure_lan_hmc;
1200         }
1201
1202         /* Get and check the mac address */
1203         i40e_get_mac_addr(hw, hw->mac.addr);
1204         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205                 PMD_INIT_LOG(ERR, "mac address is not valid");
1206                 ret = -EIO;
1207                 goto err_get_mac_addr;
1208         }
1209         /* Copy the permanent MAC address */
1210         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211                         (struct ether_addr *) hw->mac.perm_addr);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* Set the global registers with default ether type value */
1218         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219         if (ret != I40E_SUCCESS) {
1220                 PMD_INIT_LOG(ERR,
1221                         "Failed to set the default outer VLAN ether type");
1222                 goto err_setup_pf_switch;
1223         }
1224
1225         /* PF setup, which includes VSI setup */
1226         ret = i40e_pf_setup(pf);
1227         if (ret) {
1228                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229                 goto err_setup_pf_switch;
1230         }
1231
1232         /* reset all stats of the device, including pf and main vsi */
1233         i40e_dev_stats_reset(dev);
1234
1235         vsi = pf->main_vsi;
1236
1237         /* Disable double vlan by default */
1238         i40e_vsi_config_double_vlan(vsi, FALSE);
1239
1240         /* Disable S-TAG identification when floating_veb is disabled */
1241         if (!pf->floating_veb) {
1242                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1246                 }
1247         }
1248
1249         if (!vsi->max_macaddrs)
1250                 len = ETHER_ADDR_LEN;
1251         else
1252                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1253
1254         /* Should be after VSI initialized */
1255         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256         if (!dev->data->mac_addrs) {
1257                 PMD_INIT_LOG(ERR,
1258                         "Failed to allocated memory for storing mac address");
1259                 goto err_mac_alloc;
1260         }
1261         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262                                         &dev->data->mac_addrs[0]);
1263
1264         /* Init dcb to sw mode by default */
1265         ret = i40e_dcb_init_configure(dev, TRUE);
1266         if (ret != I40E_SUCCESS) {
1267                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268                 pf->flags &= ~I40E_FLAG_DCB;
1269         }
1270         /* Update HW struct after DCB configuration */
1271         i40e_get_cap(hw);
1272
1273         /* initialize pf host driver to setup SRIOV resource if applicable */
1274         i40e_pf_host_init(dev);
1275
1276         /* register callback func to eal lib */
1277         rte_intr_callback_register(intr_handle,
1278                                    i40e_dev_interrupt_handler, dev);
1279
1280         /* configure and enable device interrupt */
1281         i40e_pf_config_irq0(hw, TRUE);
1282         i40e_pf_enable_irq0(hw);
1283
1284         /* enable uio intr after callback register */
1285         rte_intr_enable(intr_handle);
1286         /*
1287          * Add an ethertype filter to drop all flow control frames transmitted
1288          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1289          * frames to wire.
1290          */
1291         i40e_add_tx_flow_control_drop_filter(pf);
1292
1293         /* Set the max frame size to 0x2600 by default,
1294          * in case other drivers changed the default value.
1295          */
1296         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297
1298         /* initialize mirror rule list */
1299         TAILQ_INIT(&pf->mirror_list);
1300
1301         /* initialize Traffic Manager configuration */
1302         i40e_tm_conf_init(dev);
1303
1304         ret = i40e_init_ethtype_filter_list(dev);
1305         if (ret < 0)
1306                 goto err_init_ethtype_filter_list;
1307         ret = i40e_init_tunnel_filter_list(dev);
1308         if (ret < 0)
1309                 goto err_init_tunnel_filter_list;
1310         ret = i40e_init_fdir_filter_list(dev);
1311         if (ret < 0)
1312                 goto err_init_fdir_filter_list;
1313
1314         return 0;
1315
1316 err_init_fdir_filter_list:
1317         rte_free(pf->tunnel.hash_table);
1318         rte_free(pf->tunnel.hash_map);
1319 err_init_tunnel_filter_list:
1320         rte_free(pf->ethertype.hash_table);
1321         rte_free(pf->ethertype.hash_map);
1322 err_init_ethtype_filter_list:
1323         rte_free(dev->data->mac_addrs);
1324 err_mac_alloc:
1325         i40e_vsi_release(pf->main_vsi);
1326 err_setup_pf_switch:
1327 err_get_mac_addr:
1328 err_configure_lan_hmc:
1329         (void)i40e_shutdown_lan_hmc(hw);
1330 err_init_lan_hmc:
1331         i40e_res_pool_destroy(&pf->msix_pool);
1332 err_msix_pool_init:
1333         i40e_res_pool_destroy(&pf->qp_pool);
1334 err_qp_pool_init:
1335 err_parameter_init:
1336 err_get_capabilities:
1337         (void)i40e_shutdown_adminq(hw);
1338
1339         return ret;
1340 }
1341
1342 static void
1343 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1344 {
1345         struct i40e_ethertype_filter *p_ethertype;
1346         struct i40e_ethertype_rule *ethertype_rule;
1347
1348         ethertype_rule = &pf->ethertype;
1349         /* Remove all ethertype filter rules and hash */
1350         if (ethertype_rule->hash_map)
1351                 rte_free(ethertype_rule->hash_map);
1352         if (ethertype_rule->hash_table)
1353                 rte_hash_free(ethertype_rule->hash_table);
1354
1355         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1356                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1357                              p_ethertype, rules);
1358                 rte_free(p_ethertype);
1359         }
1360 }
1361
1362 static void
1363 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1364 {
1365         struct i40e_tunnel_filter *p_tunnel;
1366         struct i40e_tunnel_rule *tunnel_rule;
1367
1368         tunnel_rule = &pf->tunnel;
1369         /* Remove all tunnel director rules and hash */
1370         if (tunnel_rule->hash_map)
1371                 rte_free(tunnel_rule->hash_map);
1372         if (tunnel_rule->hash_table)
1373                 rte_hash_free(tunnel_rule->hash_table);
1374
1375         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1376                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1377                 rte_free(p_tunnel);
1378         }
1379 }
1380
1381 static void
1382 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1383 {
1384         struct i40e_fdir_filter *p_fdir;
1385         struct i40e_fdir_info *fdir_info;
1386
1387         fdir_info = &pf->fdir;
1388         /* Remove all flow director rules and hash */
1389         if (fdir_info->hash_map)
1390                 rte_free(fdir_info->hash_map);
1391         if (fdir_info->hash_table)
1392                 rte_hash_free(fdir_info->hash_table);
1393
1394         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1395                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1396                 rte_free(p_fdir);
1397         }
1398 }
1399
1400 static int
1401 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 {
1403         struct i40e_pf *pf;
1404         struct rte_pci_device *pci_dev;
1405         struct rte_intr_handle *intr_handle;
1406         struct i40e_hw *hw;
1407         struct i40e_filter_control_settings settings;
1408         struct rte_flow *p_flow;
1409         int ret;
1410         uint8_t aq_fail = 0;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415                 return 0;
1416
1417         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420         intr_handle = &pci_dev->intr_handle;
1421
1422         if (hw->adapter_stopped == 0)
1423                 i40e_dev_close(dev);
1424
1425         dev->dev_ops = NULL;
1426         dev->rx_pkt_burst = NULL;
1427         dev->tx_pkt_burst = NULL;
1428
1429         /* Clear PXE mode */
1430         i40e_clear_pxe_mode(hw);
1431
1432         /* Unconfigure filter control */
1433         memset(&settings, 0, sizeof(settings));
1434         ret = i40e_set_filter_control(hw, &settings);
1435         if (ret)
1436                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437                                         ret);
1438
1439         /* Disable flow control */
1440         hw->fc.requested_mode = I40E_FC_NONE;
1441         i40e_set_fc(hw, &aq_fail, TRUE);
1442
1443         /* uninitialize pf host driver */
1444         i40e_pf_host_uninit(dev);
1445
1446         rte_free(dev->data->mac_addrs);
1447         dev->data->mac_addrs = NULL;
1448
1449         /* disable uio intr before callback unregister */
1450         rte_intr_disable(intr_handle);
1451
1452         /* register callback func to eal lib */
1453         rte_intr_callback_unregister(intr_handle,
1454                                      i40e_dev_interrupt_handler, dev);
1455
1456         i40e_rm_ethtype_filter_list(pf);
1457         i40e_rm_tunnel_filter_list(pf);
1458         i40e_rm_fdir_filter_list(pf);
1459
1460         /* Remove all flows */
1461         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1462                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1463                 rte_free(p_flow);
1464         }
1465
1466         /* Remove all Traffic Manager configuration */
1467         i40e_tm_conf_uninit(dev);
1468
1469         return 0;
1470 }
1471
1472 static int
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1474 {
1475         struct i40e_adapter *ad =
1476                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1480         int i, ret;
1481
1482         ret = i40e_dev_sync_phy_type(hw);
1483         if (ret)
1484                 return ret;
1485
1486         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1487          * bulk allocation or vector Rx preconditions we will reset it.
1488          */
1489         ad->rx_bulk_alloc_allowed = true;
1490         ad->rx_vec_allowed = true;
1491         ad->tx_simple_allowed = true;
1492         ad->tx_vec_allowed = true;
1493
1494         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1495                 ret = i40e_fdir_setup(pf);
1496                 if (ret != I40E_SUCCESS) {
1497                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1498                         return -ENOTSUP;
1499                 }
1500                 ret = i40e_fdir_configure(dev);
1501                 if (ret < 0) {
1502                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1503                         goto err;
1504                 }
1505         } else
1506                 i40e_fdir_teardown(pf);
1507
1508         ret = i40e_dev_init_vlan(dev);
1509         if (ret < 0)
1510                 goto err;
1511
1512         /* VMDQ setup.
1513          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1514          *  RSS setting have different requirements.
1515          *  General PMD driver call sequence are NIC init, configure,
1516          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1517          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1518          *  applicable. So, VMDQ setting has to be done before
1519          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1520          *  For RSS setting, it will try to calculate actual configured RX queue
1521          *  number, which will be available after rx_queue_setup(). dev_start()
1522          *  function is good to place RSS setup.
1523          */
1524         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1525                 ret = i40e_vmdq_setup(dev);
1526                 if (ret)
1527                         goto err;
1528         }
1529
1530         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1531                 ret = i40e_dcb_setup(dev);
1532                 if (ret) {
1533                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1534                         goto err_dcb;
1535                 }
1536         }
1537
1538         TAILQ_INIT(&pf->flow_list);
1539
1540         return 0;
1541
1542 err_dcb:
1543         /* need to release vmdq resource if exists */
1544         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545                 i40e_vsi_release(pf->vmdq[i].vsi);
1546                 pf->vmdq[i].vsi = NULL;
1547         }
1548         rte_free(pf->vmdq);
1549         pf->vmdq = NULL;
1550 err:
1551         /* need to release fdir resource if exists */
1552         i40e_fdir_teardown(pf);
1553         return ret;
1554 }
1555
1556 void
1557 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1558 {
1559         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1560         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1561         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563         uint16_t msix_vect = vsi->msix_intr;
1564         uint16_t i;
1565
1566         for (i = 0; i < vsi->nb_qps; i++) {
1567                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1568                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1569                 rte_wmb();
1570         }
1571
1572         if (vsi->type != I40E_VSI_SRIOV) {
1573                 if (!rte_intr_allow_others(intr_handle)) {
1574                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1575                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1576                         I40E_WRITE_REG(hw,
1577                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1578                                        0);
1579                 } else {
1580                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1581                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1582                         I40E_WRITE_REG(hw,
1583                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1584                                                        msix_vect - 1), 0);
1585                 }
1586         } else {
1587                 uint32_t reg;
1588                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1589                         vsi->user_param + (msix_vect - 1);
1590
1591                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1592                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1593         }
1594         I40E_WRITE_FLUSH(hw);
1595 }
1596
1597 static void
1598 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1599                        int base_queue, int nb_queue,
1600                        uint16_t itr_idx)
1601 {
1602         int i;
1603         uint32_t val;
1604         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1605
1606         /* Bind all RX queues to allocated MSIX interrupt */
1607         for (i = 0; i < nb_queue; i++) {
1608                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1609                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1610                         ((base_queue + i + 1) <<
1611                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1612                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1613                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1614
1615                 if (i == nb_queue - 1)
1616                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1617                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1618         }
1619
1620         /* Write first RX queue to Link list register as the head element */
1621         if (vsi->type != I40E_VSI_SRIOV) {
1622                 uint16_t interval =
1623                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1624
1625                 if (msix_vect == I40E_MISC_VEC_ID) {
1626                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1627                                        (base_queue <<
1628                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1629                                        (0x0 <<
1630                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1631                         I40E_WRITE_REG(hw,
1632                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1633                                        interval);
1634                 } else {
1635                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1636                                        (base_queue <<
1637                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1638                                        (0x0 <<
1639                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1640                         I40E_WRITE_REG(hw,
1641                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1642                                                        msix_vect - 1),
1643                                        interval);
1644                 }
1645         } else {
1646                 uint32_t reg;
1647
1648                 if (msix_vect == I40E_MISC_VEC_ID) {
1649                         I40E_WRITE_REG(hw,
1650                                        I40E_VPINT_LNKLST0(vsi->user_param),
1651                                        (base_queue <<
1652                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1653                                        (0x0 <<
1654                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1655                 } else {
1656                         /* num_msix_vectors_vf needs to minus irq0 */
1657                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1658                                 vsi->user_param + (msix_vect - 1);
1659
1660                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1661                                        (base_queue <<
1662                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1663                                        (0x0 <<
1664                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1665                 }
1666         }
1667
1668         I40E_WRITE_FLUSH(hw);
1669 }
1670
1671 void
1672 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1673 {
1674         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1675         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1676         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1677         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1678         uint16_t msix_vect = vsi->msix_intr;
1679         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1680         uint16_t queue_idx = 0;
1681         int record = 0;
1682         uint32_t val;
1683         int i;
1684
1685         for (i = 0; i < vsi->nb_qps; i++) {
1686                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1687                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1688         }
1689
1690         /* INTENA flag is not auto-cleared for interrupt */
1691         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1692         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1693                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1694                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1695         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1696
1697         /* VF bind interrupt */
1698         if (vsi->type == I40E_VSI_SRIOV) {
1699                 __vsi_queues_bind_intr(vsi, msix_vect,
1700                                        vsi->base_queue, vsi->nb_qps,
1701                                        itr_idx);
1702                 return;
1703         }
1704
1705         /* PF & VMDq bind interrupt */
1706         if (rte_intr_dp_is_en(intr_handle)) {
1707                 if (vsi->type == I40E_VSI_MAIN) {
1708                         queue_idx = 0;
1709                         record = 1;
1710                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1711                         struct i40e_vsi *main_vsi =
1712                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1713                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1714                         record = 1;
1715                 }
1716         }
1717
1718         for (i = 0; i < vsi->nb_used_qps; i++) {
1719                 if (nb_msix <= 1) {
1720                         if (!rte_intr_allow_others(intr_handle))
1721                                 /* allow to share MISC_VEC_ID */
1722                                 msix_vect = I40E_MISC_VEC_ID;
1723
1724                         /* no enough msix_vect, map all to one */
1725                         __vsi_queues_bind_intr(vsi, msix_vect,
1726                                                vsi->base_queue + i,
1727                                                vsi->nb_used_qps - i,
1728                                                itr_idx);
1729                         for (; !!record && i < vsi->nb_used_qps; i++)
1730                                 intr_handle->intr_vec[queue_idx + i] =
1731                                         msix_vect;
1732                         break;
1733                 }
1734                 /* 1:1 queue/msix_vect mapping */
1735                 __vsi_queues_bind_intr(vsi, msix_vect,
1736                                        vsi->base_queue + i, 1,
1737                                        itr_idx);
1738                 if (!!record)
1739                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1740
1741                 msix_vect++;
1742                 nb_msix--;
1743         }
1744 }
1745
1746 static void
1747 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1748 {
1749         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1750         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1751         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1752         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1753         uint16_t interval = i40e_calc_itr_interval(\
1754                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1755         uint16_t msix_intr, i;
1756
1757         if (rte_intr_allow_others(intr_handle))
1758                 for (i = 0; i < vsi->nb_msix; i++) {
1759                         msix_intr = vsi->msix_intr + i;
1760                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1761                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1762                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1763                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1764                                 (interval <<
1765                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1766                 }
1767         else
1768                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1769                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1770                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1771                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1772                                (interval <<
1773                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1774
1775         I40E_WRITE_FLUSH(hw);
1776 }
1777
1778 static void
1779 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1780 {
1781         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1782         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1783         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1784         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1785         uint16_t msix_intr, i;
1786
1787         if (rte_intr_allow_others(intr_handle))
1788                 for (i = 0; i < vsi->nb_msix; i++) {
1789                         msix_intr = vsi->msix_intr + i;
1790                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1791                                        0);
1792                 }
1793         else
1794                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1795
1796         I40E_WRITE_FLUSH(hw);
1797 }
1798
1799 static inline uint8_t
1800 i40e_parse_link_speeds(uint16_t link_speeds)
1801 {
1802         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1803
1804         if (link_speeds & ETH_LINK_SPEED_40G)
1805                 link_speed |= I40E_LINK_SPEED_40GB;
1806         if (link_speeds & ETH_LINK_SPEED_25G)
1807                 link_speed |= I40E_LINK_SPEED_25GB;
1808         if (link_speeds & ETH_LINK_SPEED_20G)
1809                 link_speed |= I40E_LINK_SPEED_20GB;
1810         if (link_speeds & ETH_LINK_SPEED_10G)
1811                 link_speed |= I40E_LINK_SPEED_10GB;
1812         if (link_speeds & ETH_LINK_SPEED_1G)
1813                 link_speed |= I40E_LINK_SPEED_1GB;
1814         if (link_speeds & ETH_LINK_SPEED_100M)
1815                 link_speed |= I40E_LINK_SPEED_100MB;
1816
1817         return link_speed;
1818 }
1819
1820 static int
1821 i40e_phy_conf_link(struct i40e_hw *hw,
1822                    uint8_t abilities,
1823                    uint8_t force_speed,
1824                    bool is_up)
1825 {
1826         enum i40e_status_code status;
1827         struct i40e_aq_get_phy_abilities_resp phy_ab;
1828         struct i40e_aq_set_phy_config phy_conf;
1829         enum i40e_aq_phy_type cnt;
1830         uint32_t phy_type_mask = 0;
1831
1832         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1833                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1834                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1835                         I40E_AQ_PHY_FLAG_LOW_POWER;
1836         const uint8_t advt = I40E_LINK_SPEED_40GB |
1837                         I40E_LINK_SPEED_25GB |
1838                         I40E_LINK_SPEED_10GB |
1839                         I40E_LINK_SPEED_1GB |
1840                         I40E_LINK_SPEED_100MB;
1841         int ret = -ENOTSUP;
1842
1843
1844         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1845                                               NULL);
1846         if (status)
1847                 return ret;
1848
1849         /* If link already up, no need to set up again */
1850         if (is_up && phy_ab.phy_type != 0)
1851                 return I40E_SUCCESS;
1852
1853         memset(&phy_conf, 0, sizeof(phy_conf));
1854
1855         /* bits 0-2 use the values from get_phy_abilities_resp */
1856         abilities &= ~mask;
1857         abilities |= phy_ab.abilities & mask;
1858
1859         /* update ablities and speed */
1860         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1861                 phy_conf.link_speed = advt;
1862         else
1863                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1864
1865         phy_conf.abilities = abilities;
1866
1867
1868
1869         /* To enable link, phy_type mask needs to include each type */
1870         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1871                 phy_type_mask |= 1 << cnt;
1872
1873         /* use get_phy_abilities_resp value for the rest */
1874         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1875         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1876                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1877                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1878         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1879         phy_conf.eee_capability = phy_ab.eee_capability;
1880         phy_conf.eeer = phy_ab.eeer_val;
1881         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1882
1883         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1884                     phy_ab.abilities, phy_ab.link_speed);
1885         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1886                     phy_conf.abilities, phy_conf.link_speed);
1887
1888         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1889         if (status)
1890                 return ret;
1891
1892         return I40E_SUCCESS;
1893 }
1894
1895 static int
1896 i40e_apply_link_speed(struct rte_eth_dev *dev)
1897 {
1898         uint8_t speed;
1899         uint8_t abilities = 0;
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         struct rte_eth_conf *conf = &dev->data->dev_conf;
1902
1903         speed = i40e_parse_link_speeds(conf->link_speeds);
1904         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1905         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1906                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1907         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1908
1909         return i40e_phy_conf_link(hw, abilities, speed, true);
1910 }
1911
1912 static int
1913 i40e_dev_start(struct rte_eth_dev *dev)
1914 {
1915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         struct i40e_vsi *main_vsi = pf->main_vsi;
1918         int ret, i;
1919         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1920         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921         uint32_t intr_vector = 0;
1922         struct i40e_vsi *vsi;
1923
1924         hw->adapter_stopped = 0;
1925
1926         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1927                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1928                              dev->data->port_id);
1929                 return -EINVAL;
1930         }
1931
1932         rte_intr_disable(intr_handle);
1933
1934         if ((rte_intr_cap_multiple(intr_handle) ||
1935              !RTE_ETH_DEV_SRIOV(dev).active) &&
1936             dev->data->dev_conf.intr_conf.rxq != 0) {
1937                 intr_vector = dev->data->nb_rx_queues;
1938                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1939                 if (ret)
1940                         return ret;
1941         }
1942
1943         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1944                 intr_handle->intr_vec =
1945                         rte_zmalloc("intr_vec",
1946                                     dev->data->nb_rx_queues * sizeof(int),
1947                                     0);
1948                 if (!intr_handle->intr_vec) {
1949                         PMD_INIT_LOG(ERR,
1950                                 "Failed to allocate %d rx_queues intr_vec",
1951                                 dev->data->nb_rx_queues);
1952                         return -ENOMEM;
1953                 }
1954         }
1955
1956         /* Initialize VSI */
1957         ret = i40e_dev_rxtx_init(pf);
1958         if (ret != I40E_SUCCESS) {
1959                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1960                 goto err_up;
1961         }
1962
1963         /* Map queues with MSIX interrupt */
1964         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1965                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1966         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1967         i40e_vsi_enable_queues_intr(main_vsi);
1968
1969         /* Map VMDQ VSI queues with MSIX interrupt */
1970         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1972                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1973                                           I40E_ITR_INDEX_DEFAULT);
1974                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1975         }
1976
1977         /* enable FDIR MSIX interrupt */
1978         if (pf->fdir.fdir_vsi) {
1979                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1980                                           I40E_ITR_INDEX_NONE);
1981                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1982         }
1983
1984         /* Enable all queues which have been configured */
1985         ret = i40e_dev_switch_queues(pf, TRUE);
1986         if (ret != I40E_SUCCESS) {
1987                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1988                 goto err_up;
1989         }
1990
1991         /* Enable receiving broadcast packets */
1992         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1993         if (ret != I40E_SUCCESS)
1994                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1995
1996         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1997                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1998                                                 true, NULL);
1999                 if (ret != I40E_SUCCESS)
2000                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2001         }
2002
2003         /* Enable the VLAN promiscuous mode. */
2004         if (pf->vfs) {
2005                 for (i = 0; i < pf->vf_num; i++) {
2006                         vsi = pf->vfs[i].vsi;
2007                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2008                                                      true, NULL);
2009                 }
2010         }
2011
2012         /* Apply link configure */
2013         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2014                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2015                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2016                                 ETH_LINK_SPEED_40G)) {
2017                 PMD_DRV_LOG(ERR, "Invalid link setting");
2018                 goto err_up;
2019         }
2020         ret = i40e_apply_link_speed(dev);
2021         if (I40E_SUCCESS != ret) {
2022                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2023                 goto err_up;
2024         }
2025
2026         if (!rte_intr_allow_others(intr_handle)) {
2027                 rte_intr_callback_unregister(intr_handle,
2028                                              i40e_dev_interrupt_handler,
2029                                              (void *)dev);
2030                 /* configure and enable device interrupt */
2031                 i40e_pf_config_irq0(hw, FALSE);
2032                 i40e_pf_enable_irq0(hw);
2033
2034                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2035                         PMD_INIT_LOG(INFO,
2036                                 "lsc won't enable because of no intr multiplex");
2037         } else {
2038                 ret = i40e_aq_set_phy_int_mask(hw,
2039                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2040                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2041                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2042                 if (ret != I40E_SUCCESS)
2043                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2044
2045                 /* Call get_link_info aq commond to enable/disable LSE */
2046                 i40e_dev_link_update(dev, 0);
2047         }
2048
2049         /* enable uio intr after callback register */
2050         rte_intr_enable(intr_handle);
2051
2052         i40e_filter_restore(pf);
2053
2054         if (pf->tm_conf.root && !pf->tm_conf.committed)
2055                 PMD_DRV_LOG(WARNING,
2056                             "please call hierarchy_commit() "
2057                             "before starting the port");
2058
2059         return I40E_SUCCESS;
2060
2061 err_up:
2062         i40e_dev_switch_queues(pf, FALSE);
2063         i40e_dev_clear_queues(dev);
2064
2065         return ret;
2066 }
2067
2068 static void
2069 i40e_dev_stop(struct rte_eth_dev *dev)
2070 {
2071         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         struct i40e_vsi *main_vsi = pf->main_vsi;
2074         struct i40e_mirror_rule *p_mirror;
2075         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2077         int i;
2078
2079         if (hw->adapter_stopped == 1)
2080                 return;
2081         /* Disable all queues */
2082         i40e_dev_switch_queues(pf, FALSE);
2083
2084         /* un-map queues with interrupt registers */
2085         i40e_vsi_disable_queues_intr(main_vsi);
2086         i40e_vsi_queues_unbind_intr(main_vsi);
2087
2088         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2089                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2090                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2091         }
2092
2093         if (pf->fdir.fdir_vsi) {
2094                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2095                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2096         }
2097         /* Clear all queues and release memory */
2098         i40e_dev_clear_queues(dev);
2099
2100         /* Set link down */
2101         i40e_dev_set_link_down(dev);
2102
2103         /* Remove all mirror rules */
2104         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2105                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2106                 rte_free(p_mirror);
2107         }
2108         pf->nb_mirror_rule = 0;
2109
2110         if (!rte_intr_allow_others(intr_handle))
2111                 /* resume to the default handler */
2112                 rte_intr_callback_register(intr_handle,
2113                                            i40e_dev_interrupt_handler,
2114                                            (void *)dev);
2115
2116         /* Clean datapath event and queue/vec mapping */
2117         rte_intr_efd_disable(intr_handle);
2118         if (intr_handle->intr_vec) {
2119                 rte_free(intr_handle->intr_vec);
2120                 intr_handle->intr_vec = NULL;
2121         }
2122
2123         /* reset hierarchy commit */
2124         pf->tm_conf.committed = false;
2125
2126         hw->adapter_stopped = 1;
2127 }
2128
2129 static void
2130 i40e_dev_close(struct rte_eth_dev *dev)
2131 {
2132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2135         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2136         uint32_t reg;
2137         int i;
2138
2139         PMD_INIT_FUNC_TRACE();
2140
2141         i40e_dev_stop(dev);
2142         i40e_dev_free_queues(dev);
2143
2144         /* Disable interrupt */
2145         i40e_pf_disable_irq0(hw);
2146         rte_intr_disable(intr_handle);
2147
2148         /* shutdown and destroy the HMC */
2149         i40e_shutdown_lan_hmc(hw);
2150
2151         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2152                 i40e_vsi_release(pf->vmdq[i].vsi);
2153                 pf->vmdq[i].vsi = NULL;
2154         }
2155         rte_free(pf->vmdq);
2156         pf->vmdq = NULL;
2157
2158         /* release all the existing VSIs and VEBs */
2159         i40e_fdir_teardown(pf);
2160         i40e_vsi_release(pf->main_vsi);
2161
2162         /* shutdown the adminq */
2163         i40e_aq_queue_shutdown(hw, true);
2164         i40e_shutdown_adminq(hw);
2165
2166         i40e_res_pool_destroy(&pf->qp_pool);
2167         i40e_res_pool_destroy(&pf->msix_pool);
2168
2169         /* force a PF reset to clean anything leftover */
2170         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2171         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2172                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2173         I40E_WRITE_FLUSH(hw);
2174 }
2175
2176 /*
2177  * Reset PF device only to re-initialize resources in PMD layer
2178  */
2179 static int
2180 i40e_dev_reset(struct rte_eth_dev *dev)
2181 {
2182         int ret;
2183
2184         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2185          * its VF to make them align with it. The detailed notification
2186          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2187          * To avoid unexpected behavior in VF, currently reset of PF with
2188          * SR-IOV activation is not supported. It might be supported later.
2189          */
2190         if (dev->data->sriov.active)
2191                 return -ENOTSUP;
2192
2193         ret = eth_i40e_dev_uninit(dev);
2194         if (ret)
2195                 return ret;
2196
2197         ret = eth_i40e_dev_init(dev);
2198
2199         return ret;
2200 }
2201
2202 static void
2203 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2204 {
2205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         struct i40e_vsi *vsi = pf->main_vsi;
2208         int status;
2209
2210         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2211                                                      true, NULL, true);
2212         if (status != I40E_SUCCESS)
2213                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2214
2215         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2216                                                         TRUE, NULL);
2217         if (status != I40E_SUCCESS)
2218                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2219
2220 }
2221
2222 static void
2223 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2224 {
2225         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227         struct i40e_vsi *vsi = pf->main_vsi;
2228         int status;
2229
2230         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2231                                                      false, NULL, true);
2232         if (status != I40E_SUCCESS)
2233                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2234
2235         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2236                                                         false, NULL);
2237         if (status != I40E_SUCCESS)
2238                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2239 }
2240
2241 static void
2242 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2243 {
2244         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2245         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         struct i40e_vsi *vsi = pf->main_vsi;
2247         int ret;
2248
2249         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2250         if (ret != I40E_SUCCESS)
2251                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2252 }
2253
2254 static void
2255 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2256 {
2257         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2259         struct i40e_vsi *vsi = pf->main_vsi;
2260         int ret;
2261
2262         if (dev->data->promiscuous == 1)
2263                 return; /* must remain in all_multicast mode */
2264
2265         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2266                                 vsi->seid, FALSE, NULL);
2267         if (ret != I40E_SUCCESS)
2268                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2269 }
2270
2271 /*
2272  * Set device link up.
2273  */
2274 static int
2275 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2276 {
2277         /* re-apply link speed setting */
2278         return i40e_apply_link_speed(dev);
2279 }
2280
2281 /*
2282  * Set device link down.
2283  */
2284 static int
2285 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2286 {
2287         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2288         uint8_t abilities = 0;
2289         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2290
2291         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2292         return i40e_phy_conf_link(hw, abilities, speed, false);
2293 }
2294
2295 int
2296 i40e_dev_link_update(struct rte_eth_dev *dev,
2297                      int wait_to_complete)
2298 {
2299 #define CHECK_INTERVAL 100  /* 100ms */
2300 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         struct i40e_link_status link_status;
2303         struct rte_eth_link link, old;
2304         int status;
2305         unsigned rep_cnt = MAX_REPEAT_TIME;
2306         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2307
2308         memset(&link, 0, sizeof(link));
2309         memset(&old, 0, sizeof(old));
2310         memset(&link_status, 0, sizeof(link_status));
2311         rte_i40e_dev_atomic_read_link_status(dev, &old);
2312
2313         do {
2314                 /* Get link status information from hardware */
2315                 status = i40e_aq_get_link_info(hw, enable_lse,
2316                                                 &link_status, NULL);
2317                 if (status != I40E_SUCCESS) {
2318                         link.link_speed = ETH_SPEED_NUM_100M;
2319                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2320                         PMD_DRV_LOG(ERR, "Failed to get link info");
2321                         goto out;
2322                 }
2323
2324                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2325                 if (!wait_to_complete || link.link_status)
2326                         break;
2327
2328                 rte_delay_ms(CHECK_INTERVAL);
2329         } while (--rep_cnt);
2330
2331         if (!link.link_status)
2332                 goto out;
2333
2334         /* i40e uses full duplex only */
2335         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2336
2337         /* Parse the link status */
2338         switch (link_status.link_speed) {
2339         case I40E_LINK_SPEED_100MB:
2340                 link.link_speed = ETH_SPEED_NUM_100M;
2341                 break;
2342         case I40E_LINK_SPEED_1GB:
2343                 link.link_speed = ETH_SPEED_NUM_1G;
2344                 break;
2345         case I40E_LINK_SPEED_10GB:
2346                 link.link_speed = ETH_SPEED_NUM_10G;
2347                 break;
2348         case I40E_LINK_SPEED_20GB:
2349                 link.link_speed = ETH_SPEED_NUM_20G;
2350                 break;
2351         case I40E_LINK_SPEED_25GB:
2352                 link.link_speed = ETH_SPEED_NUM_25G;
2353                 break;
2354         case I40E_LINK_SPEED_40GB:
2355                 link.link_speed = ETH_SPEED_NUM_40G;
2356                 break;
2357         default:
2358                 link.link_speed = ETH_SPEED_NUM_100M;
2359                 break;
2360         }
2361
2362         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2363                         ETH_LINK_SPEED_FIXED);
2364
2365 out:
2366         rte_i40e_dev_atomic_write_link_status(dev, &link);
2367         if (link.link_status == old.link_status)
2368                 return -1;
2369
2370         i40e_notify_all_vfs_link_status(dev);
2371
2372         return 0;
2373 }
2374
2375 /* Get all the statistics of a VSI */
2376 void
2377 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2378 {
2379         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2380         struct i40e_eth_stats *nes = &vsi->eth_stats;
2381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2382         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2383
2384         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2385                             vsi->offset_loaded, &oes->rx_bytes,
2386                             &nes->rx_bytes);
2387         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2388                             vsi->offset_loaded, &oes->rx_unicast,
2389                             &nes->rx_unicast);
2390         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2391                             vsi->offset_loaded, &oes->rx_multicast,
2392                             &nes->rx_multicast);
2393         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2394                             vsi->offset_loaded, &oes->rx_broadcast,
2395                             &nes->rx_broadcast);
2396         /* exclude CRC bytes */
2397         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2398                 nes->rx_broadcast) * ETHER_CRC_LEN;
2399
2400         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2401                             &oes->rx_discards, &nes->rx_discards);
2402         /* GLV_REPC not supported */
2403         /* GLV_RMPC not supported */
2404         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2405                             &oes->rx_unknown_protocol,
2406                             &nes->rx_unknown_protocol);
2407         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2408                             vsi->offset_loaded, &oes->tx_bytes,
2409                             &nes->tx_bytes);
2410         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2411                             vsi->offset_loaded, &oes->tx_unicast,
2412                             &nes->tx_unicast);
2413         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2414                             vsi->offset_loaded, &oes->tx_multicast,
2415                             &nes->tx_multicast);
2416         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2417                             vsi->offset_loaded,  &oes->tx_broadcast,
2418                             &nes->tx_broadcast);
2419         /* GLV_TDPC not supported */
2420         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2421                             &oes->tx_errors, &nes->tx_errors);
2422         vsi->offset_loaded = true;
2423
2424         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2425                     vsi->vsi_id);
2426         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2427         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2428         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2429         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2430         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2431         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2432                     nes->rx_unknown_protocol);
2433         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2434         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2435         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2436         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2437         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2438         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2439         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2440                     vsi->vsi_id);
2441 }
2442
2443 static void
2444 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2445 {
2446         unsigned int i;
2447         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2448         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2449
2450         /* Get rx/tx bytes of internal transfer packets */
2451         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2452                         I40E_GLV_GORCL(hw->port),
2453                         pf->offset_loaded,
2454                         &pf->internal_stats_offset.rx_bytes,
2455                         &pf->internal_stats.rx_bytes);
2456
2457         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2458                         I40E_GLV_GOTCL(hw->port),
2459                         pf->offset_loaded,
2460                         &pf->internal_stats_offset.tx_bytes,
2461                         &pf->internal_stats.tx_bytes);
2462         /* Get total internal rx packet count */
2463         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2464                             I40E_GLV_UPRCL(hw->port),
2465                             pf->offset_loaded,
2466                             &pf->internal_stats_offset.rx_unicast,
2467                             &pf->internal_stats.rx_unicast);
2468         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2469                             I40E_GLV_MPRCL(hw->port),
2470                             pf->offset_loaded,
2471                             &pf->internal_stats_offset.rx_multicast,
2472                             &pf->internal_stats.rx_multicast);
2473         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2474                             I40E_GLV_BPRCL(hw->port),
2475                             pf->offset_loaded,
2476                             &pf->internal_stats_offset.rx_broadcast,
2477                             &pf->internal_stats.rx_broadcast);
2478
2479         /* exclude CRC size */
2480         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2481                 pf->internal_stats.rx_multicast +
2482                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2483
2484         /* Get statistics of struct i40e_eth_stats */
2485         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2486                             I40E_GLPRT_GORCL(hw->port),
2487                             pf->offset_loaded, &os->eth.rx_bytes,
2488                             &ns->eth.rx_bytes);
2489         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2490                             I40E_GLPRT_UPRCL(hw->port),
2491                             pf->offset_loaded, &os->eth.rx_unicast,
2492                             &ns->eth.rx_unicast);
2493         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2494                             I40E_GLPRT_MPRCL(hw->port),
2495                             pf->offset_loaded, &os->eth.rx_multicast,
2496                             &ns->eth.rx_multicast);
2497         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2498                             I40E_GLPRT_BPRCL(hw->port),
2499                             pf->offset_loaded, &os->eth.rx_broadcast,
2500                             &ns->eth.rx_broadcast);
2501         /* Workaround: CRC size should not be included in byte statistics,
2502          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2503          */
2504         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2505                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2506
2507         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2508          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2509          * value.
2510          */
2511         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2512                 ns->eth.rx_bytes = 0;
2513         /* exlude internal rx bytes */
2514         else
2515                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2516
2517         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2518                             pf->offset_loaded, &os->eth.rx_discards,
2519                             &ns->eth.rx_discards);
2520         /* GLPRT_REPC not supported */
2521         /* GLPRT_RMPC not supported */
2522         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2523                             pf->offset_loaded,
2524                             &os->eth.rx_unknown_protocol,
2525                             &ns->eth.rx_unknown_protocol);
2526         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2527                             I40E_GLPRT_GOTCL(hw->port),
2528                             pf->offset_loaded, &os->eth.tx_bytes,
2529                             &ns->eth.tx_bytes);
2530         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2531                             I40E_GLPRT_UPTCL(hw->port),
2532                             pf->offset_loaded, &os->eth.tx_unicast,
2533                             &ns->eth.tx_unicast);
2534         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2535                             I40E_GLPRT_MPTCL(hw->port),
2536                             pf->offset_loaded, &os->eth.tx_multicast,
2537                             &ns->eth.tx_multicast);
2538         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2539                             I40E_GLPRT_BPTCL(hw->port),
2540                             pf->offset_loaded, &os->eth.tx_broadcast,
2541                             &ns->eth.tx_broadcast);
2542         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2543                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2544
2545         /* exclude internal tx bytes */
2546         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2547                 ns->eth.tx_bytes = 0;
2548         else
2549                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2550
2551         /* GLPRT_TEPC not supported */
2552
2553         /* additional port specific stats */
2554         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2555                             pf->offset_loaded, &os->tx_dropped_link_down,
2556                             &ns->tx_dropped_link_down);
2557         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2558                             pf->offset_loaded, &os->crc_errors,
2559                             &ns->crc_errors);
2560         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2561                             pf->offset_loaded, &os->illegal_bytes,
2562                             &ns->illegal_bytes);
2563         /* GLPRT_ERRBC not supported */
2564         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2565                             pf->offset_loaded, &os->mac_local_faults,
2566                             &ns->mac_local_faults);
2567         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2568                             pf->offset_loaded, &os->mac_remote_faults,
2569                             &ns->mac_remote_faults);
2570         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2571                             pf->offset_loaded, &os->rx_length_errors,
2572                             &ns->rx_length_errors);
2573         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2574                             pf->offset_loaded, &os->link_xon_rx,
2575                             &ns->link_xon_rx);
2576         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2577                             pf->offset_loaded, &os->link_xoff_rx,
2578                             &ns->link_xoff_rx);
2579         for (i = 0; i < 8; i++) {
2580                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2581                                     pf->offset_loaded,
2582                                     &os->priority_xon_rx[i],
2583                                     &ns->priority_xon_rx[i]);
2584                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2585                                     pf->offset_loaded,
2586                                     &os->priority_xoff_rx[i],
2587                                     &ns->priority_xoff_rx[i]);
2588         }
2589         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2590                             pf->offset_loaded, &os->link_xon_tx,
2591                             &ns->link_xon_tx);
2592         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2593                             pf->offset_loaded, &os->link_xoff_tx,
2594                             &ns->link_xoff_tx);
2595         for (i = 0; i < 8; i++) {
2596                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2597                                     pf->offset_loaded,
2598                                     &os->priority_xon_tx[i],
2599                                     &ns->priority_xon_tx[i]);
2600                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2601                                     pf->offset_loaded,
2602                                     &os->priority_xoff_tx[i],
2603                                     &ns->priority_xoff_tx[i]);
2604                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2605                                     pf->offset_loaded,
2606                                     &os->priority_xon_2_xoff[i],
2607                                     &ns->priority_xon_2_xoff[i]);
2608         }
2609         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2610                             I40E_GLPRT_PRC64L(hw->port),
2611                             pf->offset_loaded, &os->rx_size_64,
2612                             &ns->rx_size_64);
2613         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2614                             I40E_GLPRT_PRC127L(hw->port),
2615                             pf->offset_loaded, &os->rx_size_127,
2616                             &ns->rx_size_127);
2617         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2618                             I40E_GLPRT_PRC255L(hw->port),
2619                             pf->offset_loaded, &os->rx_size_255,
2620                             &ns->rx_size_255);
2621         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2622                             I40E_GLPRT_PRC511L(hw->port),
2623                             pf->offset_loaded, &os->rx_size_511,
2624                             &ns->rx_size_511);
2625         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2626                             I40E_GLPRT_PRC1023L(hw->port),
2627                             pf->offset_loaded, &os->rx_size_1023,
2628                             &ns->rx_size_1023);
2629         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2630                             I40E_GLPRT_PRC1522L(hw->port),
2631                             pf->offset_loaded, &os->rx_size_1522,
2632                             &ns->rx_size_1522);
2633         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2634                             I40E_GLPRT_PRC9522L(hw->port),
2635                             pf->offset_loaded, &os->rx_size_big,
2636                             &ns->rx_size_big);
2637         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2638                             pf->offset_loaded, &os->rx_undersize,
2639                             &ns->rx_undersize);
2640         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2641                             pf->offset_loaded, &os->rx_fragments,
2642                             &ns->rx_fragments);
2643         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2644                             pf->offset_loaded, &os->rx_oversize,
2645                             &ns->rx_oversize);
2646         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2647                             pf->offset_loaded, &os->rx_jabber,
2648                             &ns->rx_jabber);
2649         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2650                             I40E_GLPRT_PTC64L(hw->port),
2651                             pf->offset_loaded, &os->tx_size_64,
2652                             &ns->tx_size_64);
2653         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2654                             I40E_GLPRT_PTC127L(hw->port),
2655                             pf->offset_loaded, &os->tx_size_127,
2656                             &ns->tx_size_127);
2657         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2658                             I40E_GLPRT_PTC255L(hw->port),
2659                             pf->offset_loaded, &os->tx_size_255,
2660                             &ns->tx_size_255);
2661         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2662                             I40E_GLPRT_PTC511L(hw->port),
2663                             pf->offset_loaded, &os->tx_size_511,
2664                             &ns->tx_size_511);
2665         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2666                             I40E_GLPRT_PTC1023L(hw->port),
2667                             pf->offset_loaded, &os->tx_size_1023,
2668                             &ns->tx_size_1023);
2669         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2670                             I40E_GLPRT_PTC1522L(hw->port),
2671                             pf->offset_loaded, &os->tx_size_1522,
2672                             &ns->tx_size_1522);
2673         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2674                             I40E_GLPRT_PTC9522L(hw->port),
2675                             pf->offset_loaded, &os->tx_size_big,
2676                             &ns->tx_size_big);
2677         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2678                            pf->offset_loaded,
2679                            &os->fd_sb_match, &ns->fd_sb_match);
2680         /* GLPRT_MSPDC not supported */
2681         /* GLPRT_XEC not supported */
2682
2683         pf->offset_loaded = true;
2684
2685         if (pf->main_vsi)
2686                 i40e_update_vsi_stats(pf->main_vsi);
2687 }
2688
2689 /* Get all statistics of a port */
2690 static void
2691 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2692 {
2693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2694         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2695         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2696         unsigned i;
2697
2698         /* call read registers - updates values, now write them to struct */
2699         i40e_read_stats_registers(pf, hw);
2700
2701         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2702                         pf->main_vsi->eth_stats.rx_multicast +
2703                         pf->main_vsi->eth_stats.rx_broadcast -
2704                         pf->main_vsi->eth_stats.rx_discards;
2705         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2706                         pf->main_vsi->eth_stats.tx_multicast +
2707                         pf->main_vsi->eth_stats.tx_broadcast;
2708         stats->ibytes   = ns->eth.rx_bytes;
2709         stats->obytes   = ns->eth.tx_bytes;
2710         stats->oerrors  = ns->eth.tx_errors +
2711                         pf->main_vsi->eth_stats.tx_errors;
2712
2713         /* Rx Errors */
2714         stats->imissed  = ns->eth.rx_discards +
2715                         pf->main_vsi->eth_stats.rx_discards;
2716         stats->ierrors  = ns->crc_errors +
2717                         ns->rx_length_errors + ns->rx_undersize +
2718                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2719
2720         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2721         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2722         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2723         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2724         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2725         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2726         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2727                     ns->eth.rx_unknown_protocol);
2728         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2729         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2730         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2731         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2732         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2733         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2734
2735         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2736                     ns->tx_dropped_link_down);
2737         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2738         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2739                     ns->illegal_bytes);
2740         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2741         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2742                     ns->mac_local_faults);
2743         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2744                     ns->mac_remote_faults);
2745         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2746                     ns->rx_length_errors);
2747         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2748         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2749         for (i = 0; i < 8; i++) {
2750                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2751                                 i, ns->priority_xon_rx[i]);
2752                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2753                                 i, ns->priority_xoff_rx[i]);
2754         }
2755         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2756         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2757         for (i = 0; i < 8; i++) {
2758                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2759                                 i, ns->priority_xon_tx[i]);
2760                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2761                                 i, ns->priority_xoff_tx[i]);
2762                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2763                                 i, ns->priority_xon_2_xoff[i]);
2764         }
2765         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2766         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2767         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2768         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2769         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2770         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2771         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2772         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2773         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2774         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2775         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2776         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2777         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2778         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2779         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2780         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2781         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2782         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2783         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2784                         ns->mac_short_packet_dropped);
2785         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2786                     ns->checksum_error);
2787         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2788         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2789 }
2790
2791 /* Reset the statistics */
2792 static void
2793 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2794 {
2795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797
2798         /* Mark PF and VSI stats to update the offset, aka "reset" */
2799         pf->offset_loaded = false;
2800         if (pf->main_vsi)
2801                 pf->main_vsi->offset_loaded = false;
2802
2803         /* read the stats, reading current register values into offset */
2804         i40e_read_stats_registers(pf, hw);
2805 }
2806
2807 static uint32_t
2808 i40e_xstats_calc_num(void)
2809 {
2810         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2811                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2812                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2813 }
2814
2815 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2816                                      struct rte_eth_xstat_name *xstats_names,
2817                                      __rte_unused unsigned limit)
2818 {
2819         unsigned count = 0;
2820         unsigned i, prio;
2821
2822         if (xstats_names == NULL)
2823                 return i40e_xstats_calc_num();
2824
2825         /* Note: limit checked in rte_eth_xstats_names() */
2826
2827         /* Get stats from i40e_eth_stats struct */
2828         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2829                 snprintf(xstats_names[count].name,
2830                          sizeof(xstats_names[count].name),
2831                          "%s", rte_i40e_stats_strings[i].name);
2832                 count++;
2833         }
2834
2835         /* Get individiual stats from i40e_hw_port struct */
2836         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2837                 snprintf(xstats_names[count].name,
2838                         sizeof(xstats_names[count].name),
2839                          "%s", rte_i40e_hw_port_strings[i].name);
2840                 count++;
2841         }
2842
2843         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2844                 for (prio = 0; prio < 8; prio++) {
2845                         snprintf(xstats_names[count].name,
2846                                  sizeof(xstats_names[count].name),
2847                                  "rx_priority%u_%s", prio,
2848                                  rte_i40e_rxq_prio_strings[i].name);
2849                         count++;
2850                 }
2851         }
2852
2853         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2854                 for (prio = 0; prio < 8; prio++) {
2855                         snprintf(xstats_names[count].name,
2856                                  sizeof(xstats_names[count].name),
2857                                  "tx_priority%u_%s", prio,
2858                                  rte_i40e_txq_prio_strings[i].name);
2859                         count++;
2860                 }
2861         }
2862         return count;
2863 }
2864
2865 static int
2866 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2867                     unsigned n)
2868 {
2869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2871         unsigned i, count, prio;
2872         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2873
2874         count = i40e_xstats_calc_num();
2875         if (n < count)
2876                 return count;
2877
2878         i40e_read_stats_registers(pf, hw);
2879
2880         if (xstats == NULL)
2881                 return 0;
2882
2883         count = 0;
2884
2885         /* Get stats from i40e_eth_stats struct */
2886         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2887                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2888                         rte_i40e_stats_strings[i].offset);
2889                 xstats[count].id = count;
2890                 count++;
2891         }
2892
2893         /* Get individiual stats from i40e_hw_port struct */
2894         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2895                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2896                         rte_i40e_hw_port_strings[i].offset);
2897                 xstats[count].id = count;
2898                 count++;
2899         }
2900
2901         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2902                 for (prio = 0; prio < 8; prio++) {
2903                         xstats[count].value =
2904                                 *(uint64_t *)(((char *)hw_stats) +
2905                                 rte_i40e_rxq_prio_strings[i].offset +
2906                                 (sizeof(uint64_t) * prio));
2907                         xstats[count].id = count;
2908                         count++;
2909                 }
2910         }
2911
2912         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2913                 for (prio = 0; prio < 8; prio++) {
2914                         xstats[count].value =
2915                                 *(uint64_t *)(((char *)hw_stats) +
2916                                 rte_i40e_txq_prio_strings[i].offset +
2917                                 (sizeof(uint64_t) * prio));
2918                         xstats[count].id = count;
2919                         count++;
2920                 }
2921         }
2922
2923         return count;
2924 }
2925
2926 static int
2927 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2928                                  __rte_unused uint16_t queue_id,
2929                                  __rte_unused uint8_t stat_idx,
2930                                  __rte_unused uint8_t is_rx)
2931 {
2932         PMD_INIT_FUNC_TRACE();
2933
2934         return -ENOSYS;
2935 }
2936
2937 static int
2938 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2939 {
2940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         u32 full_ver;
2942         u8 ver, patch;
2943         u16 build;
2944         int ret;
2945
2946         full_ver = hw->nvm.oem_ver;
2947         ver = (u8)(full_ver >> 24);
2948         build = (u16)((full_ver >> 8) & 0xffff);
2949         patch = (u8)(full_ver & 0xff);
2950
2951         ret = snprintf(fw_version, fw_size,
2952                  "%d.%d%d 0x%08x %d.%d.%d",
2953                  ((hw->nvm.version >> 12) & 0xf),
2954                  ((hw->nvm.version >> 4) & 0xff),
2955                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2956                  ver, build, patch);
2957
2958         ret += 1; /* add the size of '\0' */
2959         if (fw_size < (u32)ret)
2960                 return ret;
2961         else
2962                 return 0;
2963 }
2964
2965 static void
2966 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2967 {
2968         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         struct i40e_vsi *vsi = pf->main_vsi;
2971         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2972
2973         dev_info->pci_dev = pci_dev;
2974         dev_info->max_rx_queues = vsi->nb_qps;
2975         dev_info->max_tx_queues = vsi->nb_qps;
2976         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2977         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2978         dev_info->max_mac_addrs = vsi->max_macaddrs;
2979         dev_info->max_vfs = pci_dev->max_vfs;
2980         dev_info->rx_offload_capa =
2981                 DEV_RX_OFFLOAD_VLAN_STRIP |
2982                 DEV_RX_OFFLOAD_QINQ_STRIP |
2983                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2984                 DEV_RX_OFFLOAD_UDP_CKSUM |
2985                 DEV_RX_OFFLOAD_TCP_CKSUM;
2986         dev_info->tx_offload_capa =
2987                 DEV_TX_OFFLOAD_VLAN_INSERT |
2988                 DEV_TX_OFFLOAD_QINQ_INSERT |
2989                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2990                 DEV_TX_OFFLOAD_UDP_CKSUM |
2991                 DEV_TX_OFFLOAD_TCP_CKSUM |
2992                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2993                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2994                 DEV_TX_OFFLOAD_TCP_TSO |
2995                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2996                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2997                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2998                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2999         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3000                                                 sizeof(uint32_t);
3001         dev_info->reta_size = pf->hash_lut_size;
3002         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
3003
3004         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3005                 .rx_thresh = {
3006                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3007                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3008                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3009                 },
3010                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3011                 .rx_drop_en = 0,
3012         };
3013
3014         dev_info->default_txconf = (struct rte_eth_txconf) {
3015                 .tx_thresh = {
3016                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3017                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3018                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3019                 },
3020                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3021                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3022                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3023                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3024         };
3025
3026         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3027                 .nb_max = I40E_MAX_RING_DESC,
3028                 .nb_min = I40E_MIN_RING_DESC,
3029                 .nb_align = I40E_ALIGN_RING_DESC,
3030         };
3031
3032         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3033                 .nb_max = I40E_MAX_RING_DESC,
3034                 .nb_min = I40E_MIN_RING_DESC,
3035                 .nb_align = I40E_ALIGN_RING_DESC,
3036                 .nb_seg_max = I40E_TX_MAX_SEG,
3037                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3038         };
3039
3040         if (pf->flags & I40E_FLAG_VMDQ) {
3041                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3042                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3043                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3044                                                 pf->max_nb_vmdq_vsi;
3045                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3046                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3047                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3048         }
3049
3050         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3051                 /* For XL710 */
3052                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3053         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3054                 /* For XXV710 */
3055                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3056         else
3057                 /* For X710 */
3058                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3059 }
3060
3061 static int
3062 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3063 {
3064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3065         struct i40e_vsi *vsi = pf->main_vsi;
3066         PMD_INIT_FUNC_TRACE();
3067
3068         if (on)
3069                 return i40e_vsi_add_vlan(vsi, vlan_id);
3070         else
3071                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3072 }
3073
3074 static int
3075 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3076                                 enum rte_vlan_type vlan_type,
3077                                 uint16_t tpid, int qinq)
3078 {
3079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         uint64_t reg_r = 0;
3081         uint64_t reg_w = 0;
3082         uint16_t reg_id = 3;
3083         int ret;
3084
3085         if (qinq) {
3086                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3087                         reg_id = 2;
3088         }
3089
3090         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3091                                           &reg_r, NULL);
3092         if (ret != I40E_SUCCESS) {
3093                 PMD_DRV_LOG(ERR,
3094                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3095                            reg_id);
3096                 return -EIO;
3097         }
3098         PMD_DRV_LOG(DEBUG,
3099                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3100                     reg_id, reg_r);
3101
3102         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3103         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3104         if (reg_r == reg_w) {
3105                 PMD_DRV_LOG(DEBUG, "No need to write");
3106                 return 0;
3107         }
3108
3109         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3110                                            reg_w, NULL);
3111         if (ret != I40E_SUCCESS) {
3112                 PMD_DRV_LOG(ERR,
3113                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3114                             reg_id);
3115                 return -EIO;
3116         }
3117         PMD_DRV_LOG(DEBUG,
3118                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3119                     reg_w, reg_id);
3120
3121         return 0;
3122 }
3123
3124 static int
3125 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3126                    enum rte_vlan_type vlan_type,
3127                    uint16_t tpid)
3128 {
3129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3130         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3131         int ret = 0;
3132
3133         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3134              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3135             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3136                 PMD_DRV_LOG(ERR,
3137                             "Unsupported vlan type.");
3138                 return -EINVAL;
3139         }
3140         /* 802.1ad frames ability is added in NVM API 1.7*/
3141         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3142                 if (qinq) {
3143                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3144                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3145                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3146                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3147                 } else {
3148                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3149                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3150                 }
3151                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3152                 if (ret != I40E_SUCCESS) {
3153                         PMD_DRV_LOG(ERR,
3154                                     "Set switch config failed aq_err: %d",
3155                                     hw->aq.asq_last_status);
3156                         ret = -EIO;
3157                 }
3158         } else
3159                 /* If NVM API < 1.7, keep the register setting */
3160                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3161                                                       tpid, qinq);
3162
3163         return ret;
3164 }
3165
3166 static void
3167 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3168 {
3169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3170         struct i40e_vsi *vsi = pf->main_vsi;
3171
3172         if (mask & ETH_VLAN_FILTER_MASK) {
3173                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3174                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3175                 else
3176                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3177         }
3178
3179         if (mask & ETH_VLAN_STRIP_MASK) {
3180                 /* Enable or disable VLAN stripping */
3181                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3182                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3183                 else
3184                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3185         }
3186
3187         if (mask & ETH_VLAN_EXTEND_MASK) {
3188                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3189                         i40e_vsi_config_double_vlan(vsi, TRUE);
3190                         /* Set global registers with default ethertype. */
3191                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3192                                            ETHER_TYPE_VLAN);
3193                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3194                                            ETHER_TYPE_VLAN);
3195                 }
3196                 else
3197                         i40e_vsi_config_double_vlan(vsi, FALSE);
3198         }
3199 }
3200
3201 static void
3202 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3203                           __rte_unused uint16_t queue,
3204                           __rte_unused int on)
3205 {
3206         PMD_INIT_FUNC_TRACE();
3207 }
3208
3209 static int
3210 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3211 {
3212         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3213         struct i40e_vsi *vsi = pf->main_vsi;
3214         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3215         struct i40e_vsi_vlan_pvid_info info;
3216
3217         memset(&info, 0, sizeof(info));
3218         info.on = on;
3219         if (info.on)
3220                 info.config.pvid = pvid;
3221         else {
3222                 info.config.reject.tagged =
3223                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3224                 info.config.reject.untagged =
3225                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3226         }
3227
3228         return i40e_vsi_vlan_pvid_set(vsi, &info);
3229 }
3230
3231 static int
3232 i40e_dev_led_on(struct rte_eth_dev *dev)
3233 {
3234         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3235         uint32_t mode = i40e_led_get(hw);
3236
3237         if (mode == 0)
3238                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3239
3240         return 0;
3241 }
3242
3243 static int
3244 i40e_dev_led_off(struct rte_eth_dev *dev)
3245 {
3246         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3247         uint32_t mode = i40e_led_get(hw);
3248
3249         if (mode != 0)
3250                 i40e_led_set(hw, 0, false);
3251
3252         return 0;
3253 }
3254
3255 static int
3256 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3257 {
3258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260
3261         fc_conf->pause_time = pf->fc_conf.pause_time;
3262
3263         /* read out from register, in case they are modified by other port */
3264         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3265                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3266         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3267                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3268
3269         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3270         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3271
3272          /* Return current mode according to actual setting*/
3273         switch (hw->fc.current_mode) {
3274         case I40E_FC_FULL:
3275                 fc_conf->mode = RTE_FC_FULL;
3276                 break;
3277         case I40E_FC_TX_PAUSE:
3278                 fc_conf->mode = RTE_FC_TX_PAUSE;
3279                 break;
3280         case I40E_FC_RX_PAUSE:
3281                 fc_conf->mode = RTE_FC_RX_PAUSE;
3282                 break;
3283         case I40E_FC_NONE:
3284         default:
3285                 fc_conf->mode = RTE_FC_NONE;
3286         };
3287
3288         return 0;
3289 }
3290
3291 static int
3292 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3293 {
3294         uint32_t mflcn_reg, fctrl_reg, reg;
3295         uint32_t max_high_water;
3296         uint8_t i, aq_failure;
3297         int err;
3298         struct i40e_hw *hw;
3299         struct i40e_pf *pf;
3300         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3301                 [RTE_FC_NONE] = I40E_FC_NONE,
3302                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3303                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3304                 [RTE_FC_FULL] = I40E_FC_FULL
3305         };
3306
3307         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3308
3309         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3310         if ((fc_conf->high_water > max_high_water) ||
3311                         (fc_conf->high_water < fc_conf->low_water)) {
3312                 PMD_INIT_LOG(ERR,
3313                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3314                         max_high_water);
3315                 return -EINVAL;
3316         }
3317
3318         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3321
3322         pf->fc_conf.pause_time = fc_conf->pause_time;
3323         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3324         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3325
3326         PMD_INIT_FUNC_TRACE();
3327
3328         /* All the link flow control related enable/disable register
3329          * configuration is handle by the F/W
3330          */
3331         err = i40e_set_fc(hw, &aq_failure, true);
3332         if (err < 0)
3333                 return -ENOSYS;
3334
3335         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3336                 /* Configure flow control refresh threshold,
3337                  * the value for stat_tx_pause_refresh_timer[8]
3338                  * is used for global pause operation.
3339                  */
3340
3341                 I40E_WRITE_REG(hw,
3342                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3343                                pf->fc_conf.pause_time);
3344
3345                 /* configure the timer value included in transmitted pause
3346                  * frame,
3347                  * the value for stat_tx_pause_quanta[8] is used for global
3348                  * pause operation
3349                  */
3350                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3351                                pf->fc_conf.pause_time);
3352
3353                 fctrl_reg = I40E_READ_REG(hw,
3354                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3355
3356                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3357                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3358                 else
3359                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3360
3361                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3362                                fctrl_reg);
3363         } else {
3364                 /* Configure pause time (2 TCs per register) */
3365                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3366                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3367                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3368
3369                 /* Configure flow control refresh threshold value */
3370                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3371                                pf->fc_conf.pause_time / 2);
3372
3373                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3374
3375                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3376                  *depending on configuration
3377                  */
3378                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3379                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3380                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3381                 } else {
3382                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3383                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3384                 }
3385
3386                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3387         }
3388
3389         /* config the water marker both based on the packets and bytes */
3390         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3391                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3392                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3393         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3394                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3395                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3396         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3397                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3398                        << I40E_KILOSHIFT);
3399         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3400                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3401                        << I40E_KILOSHIFT);
3402
3403         I40E_WRITE_FLUSH(hw);
3404
3405         return 0;
3406 }
3407
3408 static int
3409 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3410                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3411 {
3412         PMD_INIT_FUNC_TRACE();
3413
3414         return -ENOSYS;
3415 }
3416
3417 /* Add a MAC address, and update filters */
3418 static int
3419 i40e_macaddr_add(struct rte_eth_dev *dev,
3420                  struct ether_addr *mac_addr,
3421                  __rte_unused uint32_t index,
3422                  uint32_t pool)
3423 {
3424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3425         struct i40e_mac_filter_info mac_filter;
3426         struct i40e_vsi *vsi;
3427         int ret;
3428
3429         /* If VMDQ not enabled or configured, return */
3430         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3431                           !pf->nb_cfg_vmdq_vsi)) {
3432                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3433                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3434                         pool);
3435                 return -ENOTSUP;
3436         }
3437
3438         if (pool > pf->nb_cfg_vmdq_vsi) {
3439                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3440                                 pool, pf->nb_cfg_vmdq_vsi);
3441                 return -EINVAL;
3442         }
3443
3444         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3445         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3446                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3447         else
3448                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3449
3450         if (pool == 0)
3451                 vsi = pf->main_vsi;
3452         else
3453                 vsi = pf->vmdq[pool - 1].vsi;
3454
3455         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3456         if (ret != I40E_SUCCESS) {
3457                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3458                 return -ENODEV;
3459         }
3460         return 0;
3461 }
3462
3463 /* Remove a MAC address, and update filters */
3464 static void
3465 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3466 {
3467         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3468         struct i40e_vsi *vsi;
3469         struct rte_eth_dev_data *data = dev->data;
3470         struct ether_addr *macaddr;
3471         int ret;
3472         uint32_t i;
3473         uint64_t pool_sel;
3474
3475         macaddr = &(data->mac_addrs[index]);
3476
3477         pool_sel = dev->data->mac_pool_sel[index];
3478
3479         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3480                 if (pool_sel & (1ULL << i)) {
3481                         if (i == 0)
3482                                 vsi = pf->main_vsi;
3483                         else {
3484                                 /* No VMDQ pool enabled or configured */
3485                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3486                                         (i > pf->nb_cfg_vmdq_vsi)) {
3487                                         PMD_DRV_LOG(ERR,
3488                                                 "No VMDQ pool enabled/configured");
3489                                         return;
3490                                 }
3491                                 vsi = pf->vmdq[i - 1].vsi;
3492                         }
3493                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3494
3495                         if (ret) {
3496                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3497                                 return;
3498                         }
3499                 }
3500         }
3501 }
3502
3503 /* Set perfect match or hash match of MAC and VLAN for a VF */
3504 static int
3505 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3506                  struct rte_eth_mac_filter *filter,
3507                  bool add)
3508 {
3509         struct i40e_hw *hw;
3510         struct i40e_mac_filter_info mac_filter;
3511         struct ether_addr old_mac;
3512         struct ether_addr *new_mac;
3513         struct i40e_pf_vf *vf = NULL;
3514         uint16_t vf_id;
3515         int ret;
3516
3517         if (pf == NULL) {
3518                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3519                 return -EINVAL;
3520         }
3521         hw = I40E_PF_TO_HW(pf);
3522
3523         if (filter == NULL) {
3524                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3525                 return -EINVAL;
3526         }
3527
3528         new_mac = &filter->mac_addr;
3529
3530         if (is_zero_ether_addr(new_mac)) {
3531                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3532                 return -EINVAL;
3533         }
3534
3535         vf_id = filter->dst_id;
3536
3537         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3538                 PMD_DRV_LOG(ERR, "Invalid argument.");
3539                 return -EINVAL;
3540         }
3541         vf = &pf->vfs[vf_id];
3542
3543         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3544                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3545                 return -EINVAL;
3546         }
3547
3548         if (add) {
3549                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3550                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3551                                 ETHER_ADDR_LEN);
3552                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3553                                  ETHER_ADDR_LEN);
3554
3555                 mac_filter.filter_type = filter->filter_type;
3556                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3557                 if (ret != I40E_SUCCESS) {
3558                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3559                         return -1;
3560                 }
3561                 ether_addr_copy(new_mac, &pf->dev_addr);
3562         } else {
3563                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3564                                 ETHER_ADDR_LEN);
3565                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3566                 if (ret != I40E_SUCCESS) {
3567                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3568                         return -1;
3569                 }
3570
3571                 /* Clear device address as it has been removed */
3572                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3573                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3574         }
3575
3576         return 0;
3577 }
3578
3579 /* MAC filter handle */
3580 static int
3581 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3582                 void *arg)
3583 {
3584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3585         struct rte_eth_mac_filter *filter;
3586         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3587         int ret = I40E_NOT_SUPPORTED;
3588
3589         filter = (struct rte_eth_mac_filter *)(arg);
3590
3591         switch (filter_op) {
3592         case RTE_ETH_FILTER_NOP:
3593                 ret = I40E_SUCCESS;
3594                 break;
3595         case RTE_ETH_FILTER_ADD:
3596                 i40e_pf_disable_irq0(hw);
3597                 if (filter->is_vf)
3598                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3599                 i40e_pf_enable_irq0(hw);
3600                 break;
3601         case RTE_ETH_FILTER_DELETE:
3602                 i40e_pf_disable_irq0(hw);
3603                 if (filter->is_vf)
3604                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3605                 i40e_pf_enable_irq0(hw);
3606                 break;
3607         default:
3608                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3609                 ret = I40E_ERR_PARAM;
3610                 break;
3611         }
3612
3613         return ret;
3614 }
3615
3616 static int
3617 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3618 {
3619         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3620         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3621         int ret;
3622
3623         if (!lut)
3624                 return -EINVAL;
3625
3626         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3627                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3628                                           lut, lut_size);
3629                 if (ret) {
3630                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3631                         return ret;
3632                 }
3633         } else {
3634                 uint32_t *lut_dw = (uint32_t *)lut;
3635                 uint16_t i, lut_size_dw = lut_size / 4;
3636
3637                 for (i = 0; i < lut_size_dw; i++)
3638                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3639         }
3640
3641         return 0;
3642 }
3643
3644 static int
3645 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3646 {
3647         struct i40e_pf *pf;
3648         struct i40e_hw *hw;
3649         int ret;
3650
3651         if (!vsi || !lut)
3652                 return -EINVAL;
3653
3654         pf = I40E_VSI_TO_PF(vsi);
3655         hw = I40E_VSI_TO_HW(vsi);
3656
3657         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3658                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3659                                           lut, lut_size);
3660                 if (ret) {
3661                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3662                         return ret;
3663                 }
3664         } else {
3665                 uint32_t *lut_dw = (uint32_t *)lut;
3666                 uint16_t i, lut_size_dw = lut_size / 4;
3667
3668                 for (i = 0; i < lut_size_dw; i++)
3669                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3670                 I40E_WRITE_FLUSH(hw);
3671         }
3672
3673         return 0;
3674 }
3675
3676 static int
3677 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3678                          struct rte_eth_rss_reta_entry64 *reta_conf,
3679                          uint16_t reta_size)
3680 {
3681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3682         uint16_t i, lut_size = pf->hash_lut_size;
3683         uint16_t idx, shift;
3684         uint8_t *lut;
3685         int ret;
3686
3687         if (reta_size != lut_size ||
3688                 reta_size > ETH_RSS_RETA_SIZE_512) {
3689                 PMD_DRV_LOG(ERR,
3690                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3691                         reta_size, lut_size);
3692                 return -EINVAL;
3693         }
3694
3695         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3696         if (!lut) {
3697                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3698                 return -ENOMEM;
3699         }
3700         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3701         if (ret)
3702                 goto out;
3703         for (i = 0; i < reta_size; i++) {
3704                 idx = i / RTE_RETA_GROUP_SIZE;
3705                 shift = i % RTE_RETA_GROUP_SIZE;
3706                 if (reta_conf[idx].mask & (1ULL << shift))
3707                         lut[i] = reta_conf[idx].reta[shift];
3708         }
3709         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3710
3711 out:
3712         rte_free(lut);
3713
3714         return ret;
3715 }
3716
3717 static int
3718 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3719                         struct rte_eth_rss_reta_entry64 *reta_conf,
3720                         uint16_t reta_size)
3721 {
3722         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723         uint16_t i, lut_size = pf->hash_lut_size;
3724         uint16_t idx, shift;
3725         uint8_t *lut;
3726         int ret;
3727
3728         if (reta_size != lut_size ||
3729                 reta_size > ETH_RSS_RETA_SIZE_512) {
3730                 PMD_DRV_LOG(ERR,
3731                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732                         reta_size, lut_size);
3733                 return -EINVAL;
3734         }
3735
3736         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3737         if (!lut) {
3738                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3739                 return -ENOMEM;
3740         }
3741
3742         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3743         if (ret)
3744                 goto out;
3745         for (i = 0; i < reta_size; i++) {
3746                 idx = i / RTE_RETA_GROUP_SIZE;
3747                 shift = i % RTE_RETA_GROUP_SIZE;
3748                 if (reta_conf[idx].mask & (1ULL << shift))
3749                         reta_conf[idx].reta[shift] = lut[i];
3750         }
3751
3752 out:
3753         rte_free(lut);
3754
3755         return ret;
3756 }
3757
3758 /**
3759  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3760  * @hw:   pointer to the HW structure
3761  * @mem:  pointer to mem struct to fill out
3762  * @size: size of memory requested
3763  * @alignment: what to align the allocation to
3764  **/
3765 enum i40e_status_code
3766 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3767                         struct i40e_dma_mem *mem,
3768                         u64 size,
3769                         u32 alignment)
3770 {
3771         const struct rte_memzone *mz = NULL;
3772         char z_name[RTE_MEMZONE_NAMESIZE];
3773
3774         if (!mem)
3775                 return I40E_ERR_PARAM;
3776
3777         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3778         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3779                                          alignment, RTE_PGSIZE_2M);
3780         if (!mz)
3781                 return I40E_ERR_NO_MEMORY;
3782
3783         mem->size = size;
3784         mem->va = mz->addr;
3785         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3786         mem->zone = (const void *)mz;
3787         PMD_DRV_LOG(DEBUG,
3788                 "memzone %s allocated with physical address: %"PRIu64,
3789                 mz->name, mem->pa);
3790
3791         return I40E_SUCCESS;
3792 }
3793
3794 /**
3795  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3796  * @hw:   pointer to the HW structure
3797  * @mem:  ptr to mem struct to free
3798  **/
3799 enum i40e_status_code
3800 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3801                     struct i40e_dma_mem *mem)
3802 {
3803         if (!mem)
3804                 return I40E_ERR_PARAM;
3805
3806         PMD_DRV_LOG(DEBUG,
3807                 "memzone %s to be freed with physical address: %"PRIu64,
3808                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3809         rte_memzone_free((const struct rte_memzone *)mem->zone);
3810         mem->zone = NULL;
3811         mem->va = NULL;
3812         mem->pa = (u64)0;
3813
3814         return I40E_SUCCESS;
3815 }
3816
3817 /**
3818  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3819  * @hw:   pointer to the HW structure
3820  * @mem:  pointer to mem struct to fill out
3821  * @size: size of memory requested
3822  **/
3823 enum i40e_status_code
3824 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3825                          struct i40e_virt_mem *mem,
3826                          u32 size)
3827 {
3828         if (!mem)
3829                 return I40E_ERR_PARAM;
3830
3831         mem->size = size;
3832         mem->va = rte_zmalloc("i40e", size, 0);
3833
3834         if (mem->va)
3835                 return I40E_SUCCESS;
3836         else
3837                 return I40E_ERR_NO_MEMORY;
3838 }
3839
3840 /**
3841  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3842  * @hw:   pointer to the HW structure
3843  * @mem:  pointer to mem struct to free
3844  **/
3845 enum i40e_status_code
3846 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3847                      struct i40e_virt_mem *mem)
3848 {
3849         if (!mem)
3850                 return I40E_ERR_PARAM;
3851
3852         rte_free(mem->va);
3853         mem->va = NULL;
3854
3855         return I40E_SUCCESS;
3856 }
3857
3858 void
3859 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3860 {
3861         rte_spinlock_init(&sp->spinlock);
3862 }
3863
3864 void
3865 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3866 {
3867         rte_spinlock_lock(&sp->spinlock);
3868 }
3869
3870 void
3871 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3872 {
3873         rte_spinlock_unlock(&sp->spinlock);
3874 }
3875
3876 void
3877 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3878 {
3879         return;
3880 }
3881
3882 /**
3883  * Get the hardware capabilities, which will be parsed
3884  * and saved into struct i40e_hw.
3885  */
3886 static int
3887 i40e_get_cap(struct i40e_hw *hw)
3888 {
3889         struct i40e_aqc_list_capabilities_element_resp *buf;
3890         uint16_t len, size = 0;
3891         int ret;
3892
3893         /* Calculate a huge enough buff for saving response data temporarily */
3894         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3895                                                 I40E_MAX_CAP_ELE_NUM;
3896         buf = rte_zmalloc("i40e", len, 0);
3897         if (!buf) {
3898                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3899                 return I40E_ERR_NO_MEMORY;
3900         }
3901
3902         /* Get, parse the capabilities and save it to hw */
3903         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3904                         i40e_aqc_opc_list_func_capabilities, NULL);
3905         if (ret != I40E_SUCCESS)
3906                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3907
3908         /* Free the temporary buffer after being used */
3909         rte_free(buf);
3910
3911         return ret;
3912 }
3913
3914 static int
3915 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3916 {
3917         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3919         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3920         uint16_t qp_count = 0, vsi_count = 0;
3921
3922         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3923                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3924                 return -EINVAL;
3925         }
3926         /* Add the parameter init for LFC */
3927         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3928         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3929         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3930
3931         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3932         pf->max_num_vsi = hw->func_caps.num_vsis;
3933         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3934         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3935         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3936
3937         /* FDir queue/VSI allocation */
3938         pf->fdir_qp_offset = 0;
3939         if (hw->func_caps.fd) {
3940                 pf->flags |= I40E_FLAG_FDIR;
3941                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3942         } else {
3943                 pf->fdir_nb_qps = 0;
3944         }
3945         qp_count += pf->fdir_nb_qps;
3946         vsi_count += 1;
3947
3948         /* LAN queue/VSI allocation */
3949         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3950         if (!hw->func_caps.rss) {
3951                 pf->lan_nb_qps = 1;
3952         } else {
3953                 pf->flags |= I40E_FLAG_RSS;
3954                 if (hw->mac.type == I40E_MAC_X722)
3955                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3956                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3957         }
3958         qp_count += pf->lan_nb_qps;
3959         vsi_count += 1;
3960
3961         /* VF queue/VSI allocation */
3962         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3963         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3964                 pf->flags |= I40E_FLAG_SRIOV;
3965                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3966                 pf->vf_num = pci_dev->max_vfs;
3967                 PMD_DRV_LOG(DEBUG,
3968                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3969                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3970         } else {
3971                 pf->vf_nb_qps = 0;
3972                 pf->vf_num = 0;
3973         }
3974         qp_count += pf->vf_nb_qps * pf->vf_num;
3975         vsi_count += pf->vf_num;
3976
3977         /* VMDq queue/VSI allocation */
3978         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3979         pf->vmdq_nb_qps = 0;
3980         pf->max_nb_vmdq_vsi = 0;
3981         if (hw->func_caps.vmdq) {
3982                 if (qp_count < hw->func_caps.num_tx_qp &&
3983                         vsi_count < hw->func_caps.num_vsis) {
3984                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3985                                 qp_count) / pf->vmdq_nb_qp_max;
3986
3987                         /* Limit the maximum number of VMDq vsi to the maximum
3988                          * ethdev can support
3989                          */
3990                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3991                                 hw->func_caps.num_vsis - vsi_count);
3992                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3993                                 ETH_64_POOLS);
3994                         if (pf->max_nb_vmdq_vsi) {
3995                                 pf->flags |= I40E_FLAG_VMDQ;
3996                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3997                                 PMD_DRV_LOG(DEBUG,
3998                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3999                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4000                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4001                         } else {
4002                                 PMD_DRV_LOG(INFO,
4003                                         "No enough queues left for VMDq");
4004                         }
4005                 } else {
4006                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4007                 }
4008         }
4009         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4010         vsi_count += pf->max_nb_vmdq_vsi;
4011
4012         if (hw->func_caps.dcb)
4013                 pf->flags |= I40E_FLAG_DCB;
4014
4015         if (qp_count > hw->func_caps.num_tx_qp) {
4016                 PMD_DRV_LOG(ERR,
4017                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4018                         qp_count, hw->func_caps.num_tx_qp);
4019                 return -EINVAL;
4020         }
4021         if (vsi_count > hw->func_caps.num_vsis) {
4022                 PMD_DRV_LOG(ERR,
4023                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4024                         vsi_count, hw->func_caps.num_vsis);
4025                 return -EINVAL;
4026         }
4027
4028         return 0;
4029 }
4030
4031 static int
4032 i40e_pf_get_switch_config(struct i40e_pf *pf)
4033 {
4034         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4035         struct i40e_aqc_get_switch_config_resp *switch_config;
4036         struct i40e_aqc_switch_config_element_resp *element;
4037         uint16_t start_seid = 0, num_reported;
4038         int ret;
4039
4040         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4041                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4042         if (!switch_config) {
4043                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4044                 return -ENOMEM;
4045         }
4046
4047         /* Get the switch configurations */
4048         ret = i40e_aq_get_switch_config(hw, switch_config,
4049                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4050         if (ret != I40E_SUCCESS) {
4051                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4052                 goto fail;
4053         }
4054         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4055         if (num_reported != 1) { /* The number should be 1 */
4056                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4057                 goto fail;
4058         }
4059
4060         /* Parse the switch configuration elements */
4061         element = &(switch_config->element[0]);
4062         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4063                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4064                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4065         } else
4066                 PMD_DRV_LOG(INFO, "Unknown element type");
4067
4068 fail:
4069         rte_free(switch_config);
4070
4071         return ret;
4072 }
4073
4074 static int
4075 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4076                         uint32_t num)
4077 {
4078         struct pool_entry *entry;
4079
4080         if (pool == NULL || num == 0)
4081                 return -EINVAL;
4082
4083         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4084         if (entry == NULL) {
4085                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4086                 return -ENOMEM;
4087         }
4088
4089         /* queue heap initialize */
4090         pool->num_free = num;
4091         pool->num_alloc = 0;
4092         pool->base = base;
4093         LIST_INIT(&pool->alloc_list);
4094         LIST_INIT(&pool->free_list);
4095
4096         /* Initialize element  */
4097         entry->base = 0;
4098         entry->len = num;
4099
4100         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4101         return 0;
4102 }
4103
4104 static void
4105 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4106 {
4107         struct pool_entry *entry, *next_entry;
4108
4109         if (pool == NULL)
4110                 return;
4111
4112         for (entry = LIST_FIRST(&pool->alloc_list);
4113                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4114                         entry = next_entry) {
4115                 LIST_REMOVE(entry, next);
4116                 rte_free(entry);
4117         }
4118
4119         for (entry = LIST_FIRST(&pool->free_list);
4120                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4121                         entry = next_entry) {
4122                 LIST_REMOVE(entry, next);
4123                 rte_free(entry);
4124         }
4125
4126         pool->num_free = 0;
4127         pool->num_alloc = 0;
4128         pool->base = 0;
4129         LIST_INIT(&pool->alloc_list);
4130         LIST_INIT(&pool->free_list);
4131 }
4132
4133 static int
4134 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4135                        uint32_t base)
4136 {
4137         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4138         uint32_t pool_offset;
4139         int insert;
4140
4141         if (pool == NULL) {
4142                 PMD_DRV_LOG(ERR, "Invalid parameter");
4143                 return -EINVAL;
4144         }
4145
4146         pool_offset = base - pool->base;
4147         /* Lookup in alloc list */
4148         LIST_FOREACH(entry, &pool->alloc_list, next) {
4149                 if (entry->base == pool_offset) {
4150                         valid_entry = entry;
4151                         LIST_REMOVE(entry, next);
4152                         break;
4153                 }
4154         }
4155
4156         /* Not find, return */
4157         if (valid_entry == NULL) {
4158                 PMD_DRV_LOG(ERR, "Failed to find entry");
4159                 return -EINVAL;
4160         }
4161
4162         /**
4163          * Found it, move it to free list  and try to merge.
4164          * In order to make merge easier, always sort it by qbase.
4165          * Find adjacent prev and last entries.
4166          */
4167         prev = next = NULL;
4168         LIST_FOREACH(entry, &pool->free_list, next) {
4169                 if (entry->base > valid_entry->base) {
4170                         next = entry;
4171                         break;
4172                 }
4173                 prev = entry;
4174         }
4175
4176         insert = 0;
4177         /* Try to merge with next one*/
4178         if (next != NULL) {
4179                 /* Merge with next one */
4180                 if (valid_entry->base + valid_entry->len == next->base) {
4181                         next->base = valid_entry->base;
4182                         next->len += valid_entry->len;
4183                         rte_free(valid_entry);
4184                         valid_entry = next;
4185                         insert = 1;
4186                 }
4187         }
4188
4189         if (prev != NULL) {
4190                 /* Merge with previous one */
4191                 if (prev->base + prev->len == valid_entry->base) {
4192                         prev->len += valid_entry->len;
4193                         /* If it merge with next one, remove next node */
4194                         if (insert == 1) {
4195                                 LIST_REMOVE(valid_entry, next);
4196                                 rte_free(valid_entry);
4197                         } else {
4198                                 rte_free(valid_entry);
4199                                 insert = 1;
4200                         }
4201                 }
4202         }
4203
4204         /* Not find any entry to merge, insert */
4205         if (insert == 0) {
4206                 if (prev != NULL)
4207                         LIST_INSERT_AFTER(prev, valid_entry, next);
4208                 else if (next != NULL)
4209                         LIST_INSERT_BEFORE(next, valid_entry, next);
4210                 else /* It's empty list, insert to head */
4211                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4212         }
4213
4214         pool->num_free += valid_entry->len;
4215         pool->num_alloc -= valid_entry->len;
4216
4217         return 0;
4218 }
4219
4220 static int
4221 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4222                        uint16_t num)
4223 {
4224         struct pool_entry *entry, *valid_entry;
4225
4226         if (pool == NULL || num == 0) {
4227                 PMD_DRV_LOG(ERR, "Invalid parameter");
4228                 return -EINVAL;
4229         }
4230
4231         if (pool->num_free < num) {
4232                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4233                             num, pool->num_free);
4234                 return -ENOMEM;
4235         }
4236
4237         valid_entry = NULL;
4238         /* Lookup  in free list and find most fit one */
4239         LIST_FOREACH(entry, &pool->free_list, next) {
4240                 if (entry->len >= num) {
4241                         /* Find best one */
4242                         if (entry->len == num) {
4243                                 valid_entry = entry;
4244                                 break;
4245                         }
4246                         if (valid_entry == NULL || valid_entry->len > entry->len)
4247                                 valid_entry = entry;
4248                 }
4249         }
4250
4251         /* Not find one to satisfy the request, return */
4252         if (valid_entry == NULL) {
4253                 PMD_DRV_LOG(ERR, "No valid entry found");
4254                 return -ENOMEM;
4255         }
4256         /**
4257          * The entry have equal queue number as requested,
4258          * remove it from alloc_list.
4259          */
4260         if (valid_entry->len == num) {
4261                 LIST_REMOVE(valid_entry, next);
4262         } else {
4263                 /**
4264                  * The entry have more numbers than requested,
4265                  * create a new entry for alloc_list and minus its
4266                  * queue base and number in free_list.
4267                  */
4268                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4269                 if (entry == NULL) {
4270                         PMD_DRV_LOG(ERR,
4271                                 "Failed to allocate memory for resource pool");
4272                         return -ENOMEM;
4273                 }
4274                 entry->base = valid_entry->base;
4275                 entry->len = num;
4276                 valid_entry->base += num;
4277                 valid_entry->len -= num;
4278                 valid_entry = entry;
4279         }
4280
4281         /* Insert it into alloc list, not sorted */
4282         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4283
4284         pool->num_free -= valid_entry->len;
4285         pool->num_alloc += valid_entry->len;
4286
4287         return valid_entry->base + pool->base;
4288 }
4289
4290 /**
4291  * bitmap_is_subset - Check whether src2 is subset of src1
4292  **/
4293 static inline int
4294 bitmap_is_subset(uint8_t src1, uint8_t src2)
4295 {
4296         return !((src1 ^ src2) & src2);
4297 }
4298
4299 static enum i40e_status_code
4300 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4301 {
4302         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4303
4304         /* If DCB is not supported, only default TC is supported */
4305         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4306                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4307                 return I40E_NOT_SUPPORTED;
4308         }
4309
4310         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4311                 PMD_DRV_LOG(ERR,
4312                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4313                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4314                 return I40E_NOT_SUPPORTED;
4315         }
4316         return I40E_SUCCESS;
4317 }
4318
4319 int
4320 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4321                                 struct i40e_vsi_vlan_pvid_info *info)
4322 {
4323         struct i40e_hw *hw;
4324         struct i40e_vsi_context ctxt;
4325         uint8_t vlan_flags = 0;
4326         int ret;
4327
4328         if (vsi == NULL || info == NULL) {
4329                 PMD_DRV_LOG(ERR, "invalid parameters");
4330                 return I40E_ERR_PARAM;
4331         }
4332
4333         if (info->on) {
4334                 vsi->info.pvid = info->config.pvid;
4335                 /**
4336                  * If insert pvid is enabled, only tagged pkts are
4337                  * allowed to be sent out.
4338                  */
4339                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4340                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4341         } else {
4342                 vsi->info.pvid = 0;
4343                 if (info->config.reject.tagged == 0)
4344                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4345
4346                 if (info->config.reject.untagged == 0)
4347                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4348         }
4349         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4350                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4351         vsi->info.port_vlan_flags |= vlan_flags;
4352         vsi->info.valid_sections =
4353                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4354         memset(&ctxt, 0, sizeof(ctxt));
4355         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4356         ctxt.seid = vsi->seid;
4357
4358         hw = I40E_VSI_TO_HW(vsi);
4359         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4360         if (ret != I40E_SUCCESS)
4361                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4362
4363         return ret;
4364 }
4365
4366 static int
4367 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4368 {
4369         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4370         int i, ret;
4371         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4372
4373         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4374         if (ret != I40E_SUCCESS)
4375                 return ret;
4376
4377         if (!vsi->seid) {
4378                 PMD_DRV_LOG(ERR, "seid not valid");
4379                 return -EINVAL;
4380         }
4381
4382         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4383         tc_bw_data.tc_valid_bits = enabled_tcmap;
4384         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4385                 tc_bw_data.tc_bw_credits[i] =
4386                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4387
4388         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4389         if (ret != I40E_SUCCESS) {
4390                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4391                 return ret;
4392         }
4393
4394         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4395                                         sizeof(vsi->info.qs_handle));
4396         return I40E_SUCCESS;
4397 }
4398
4399 static enum i40e_status_code
4400 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4401                                  struct i40e_aqc_vsi_properties_data *info,
4402                                  uint8_t enabled_tcmap)
4403 {
4404         enum i40e_status_code ret;
4405         int i, total_tc = 0;
4406         uint16_t qpnum_per_tc, bsf, qp_idx;
4407
4408         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4409         if (ret != I40E_SUCCESS)
4410                 return ret;
4411
4412         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4413                 if (enabled_tcmap & (1 << i))
4414                         total_tc++;
4415         if (total_tc == 0)
4416                 total_tc = 1;
4417         vsi->enabled_tc = enabled_tcmap;
4418
4419         /* Number of queues per enabled TC */
4420         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4421         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4422         bsf = rte_bsf32(qpnum_per_tc);
4423
4424         /* Adjust the queue number to actual queues that can be applied */
4425         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4426                 vsi->nb_qps = qpnum_per_tc * total_tc;
4427
4428         /**
4429          * Configure TC and queue mapping parameters, for enabled TC,
4430          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4431          * default queue will serve it.
4432          */
4433         qp_idx = 0;
4434         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4435                 if (vsi->enabled_tc & (1 << i)) {
4436                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4437                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4438                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4439                         qp_idx += qpnum_per_tc;
4440                 } else
4441                         info->tc_mapping[i] = 0;
4442         }
4443
4444         /* Associate queue number with VSI */
4445         if (vsi->type == I40E_VSI_SRIOV) {
4446                 info->mapping_flags |=
4447                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4448                 for (i = 0; i < vsi->nb_qps; i++)
4449                         info->queue_mapping[i] =
4450                                 rte_cpu_to_le_16(vsi->base_queue + i);
4451         } else {
4452                 info->mapping_flags |=
4453                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4454                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4455         }
4456         info->valid_sections |=
4457                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4458
4459         return I40E_SUCCESS;
4460 }
4461
4462 static int
4463 i40e_veb_release(struct i40e_veb *veb)
4464 {
4465         struct i40e_vsi *vsi;
4466         struct i40e_hw *hw;
4467
4468         if (veb == NULL)
4469                 return -EINVAL;
4470
4471         if (!TAILQ_EMPTY(&veb->head)) {
4472                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4473                 return -EACCES;
4474         }
4475         /* associate_vsi field is NULL for floating VEB */
4476         if (veb->associate_vsi != NULL) {
4477                 vsi = veb->associate_vsi;
4478                 hw = I40E_VSI_TO_HW(vsi);
4479
4480                 vsi->uplink_seid = veb->uplink_seid;
4481                 vsi->veb = NULL;
4482         } else {
4483                 veb->associate_pf->main_vsi->floating_veb = NULL;
4484                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4485         }
4486
4487         i40e_aq_delete_element(hw, veb->seid, NULL);
4488         rte_free(veb);
4489         return I40E_SUCCESS;
4490 }
4491
4492 /* Setup a veb */
4493 static struct i40e_veb *
4494 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4495 {
4496         struct i40e_veb *veb;
4497         int ret;
4498         struct i40e_hw *hw;
4499
4500         if (pf == NULL) {
4501                 PMD_DRV_LOG(ERR,
4502                             "veb setup failed, associated PF shouldn't null");
4503                 return NULL;
4504         }
4505         hw = I40E_PF_TO_HW(pf);
4506
4507         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4508         if (!veb) {
4509                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4510                 goto fail;
4511         }
4512
4513         veb->associate_vsi = vsi;
4514         veb->associate_pf = pf;
4515         TAILQ_INIT(&veb->head);
4516         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4517
4518         /* create floating veb if vsi is NULL */
4519         if (vsi != NULL) {
4520                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4521                                       I40E_DEFAULT_TCMAP, false,
4522                                       &veb->seid, false, NULL);
4523         } else {
4524                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4525                                       true, &veb->seid, false, NULL);
4526         }
4527
4528         if (ret != I40E_SUCCESS) {
4529                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4530                             hw->aq.asq_last_status);
4531                 goto fail;
4532         }
4533         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4534
4535         /* get statistics index */
4536         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4537                                 &veb->stats_idx, NULL, NULL, NULL);
4538         if (ret != I40E_SUCCESS) {
4539                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4540                             hw->aq.asq_last_status);
4541                 goto fail;
4542         }
4543         /* Get VEB bandwidth, to be implemented */
4544         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4545         if (vsi)
4546                 vsi->uplink_seid = veb->seid;
4547
4548         return veb;
4549 fail:
4550         rte_free(veb);
4551         return NULL;
4552 }
4553
4554 int
4555 i40e_vsi_release(struct i40e_vsi *vsi)
4556 {
4557         struct i40e_pf *pf;
4558         struct i40e_hw *hw;
4559         struct i40e_vsi_list *vsi_list;
4560         void *temp;
4561         int ret;
4562         struct i40e_mac_filter *f;
4563         uint16_t user_param;
4564
4565         if (!vsi)
4566                 return I40E_SUCCESS;
4567
4568         if (!vsi->adapter)
4569                 return -EFAULT;
4570
4571         user_param = vsi->user_param;
4572
4573         pf = I40E_VSI_TO_PF(vsi);
4574         hw = I40E_VSI_TO_HW(vsi);
4575
4576         /* VSI has child to attach, release child first */
4577         if (vsi->veb) {
4578                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4579                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4580                                 return -1;
4581                 }
4582                 i40e_veb_release(vsi->veb);
4583         }
4584
4585         if (vsi->floating_veb) {
4586                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4587                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4588                                 return -1;
4589                 }
4590         }
4591
4592         /* Remove all macvlan filters of the VSI */
4593         i40e_vsi_remove_all_macvlan_filter(vsi);
4594         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4595                 rte_free(f);
4596
4597         if (vsi->type != I40E_VSI_MAIN &&
4598             ((vsi->type != I40E_VSI_SRIOV) ||
4599             !pf->floating_veb_list[user_param])) {
4600                 /* Remove vsi from parent's sibling list */
4601                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4602                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4603                         return I40E_ERR_PARAM;
4604                 }
4605                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4606                                 &vsi->sib_vsi_list, list);
4607
4608                 /* Remove all switch element of the VSI */
4609                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4610                 if (ret != I40E_SUCCESS)
4611                         PMD_DRV_LOG(ERR, "Failed to delete element");
4612         }
4613
4614         if ((vsi->type == I40E_VSI_SRIOV) &&
4615             pf->floating_veb_list[user_param]) {
4616                 /* Remove vsi from parent's sibling list */
4617                 if (vsi->parent_vsi == NULL ||
4618                     vsi->parent_vsi->floating_veb == NULL) {
4619                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4620                         return I40E_ERR_PARAM;
4621                 }
4622                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4623                              &vsi->sib_vsi_list, list);
4624
4625                 /* Remove all switch element of the VSI */
4626                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4627                 if (ret != I40E_SUCCESS)
4628                         PMD_DRV_LOG(ERR, "Failed to delete element");
4629         }
4630
4631         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4632
4633         if (vsi->type != I40E_VSI_SRIOV)
4634                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4635         rte_free(vsi);
4636
4637         return I40E_SUCCESS;
4638 }
4639
4640 static int
4641 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4642 {
4643         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4644         struct i40e_aqc_remove_macvlan_element_data def_filter;
4645         struct i40e_mac_filter_info filter;
4646         int ret;
4647
4648         if (vsi->type != I40E_VSI_MAIN)
4649                 return I40E_ERR_CONFIG;
4650         memset(&def_filter, 0, sizeof(def_filter));
4651         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4652                                         ETH_ADDR_LEN);
4653         def_filter.vlan_tag = 0;
4654         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4655                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4656         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4657         if (ret != I40E_SUCCESS) {
4658                 struct i40e_mac_filter *f;
4659                 struct ether_addr *mac;
4660
4661                 PMD_DRV_LOG(DEBUG,
4662                             "Cannot remove the default macvlan filter");
4663                 /* It needs to add the permanent mac into mac list */
4664                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4665                 if (f == NULL) {
4666                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4667                         return I40E_ERR_NO_MEMORY;
4668                 }
4669                 mac = &f->mac_info.mac_addr;
4670                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4671                                 ETH_ADDR_LEN);
4672                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4673                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4674                 vsi->mac_num++;
4675
4676                 return ret;
4677         }
4678         (void)rte_memcpy(&filter.mac_addr,
4679                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4680         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4681         return i40e_vsi_add_mac(vsi, &filter);
4682 }
4683
4684 /*
4685  * i40e_vsi_get_bw_config - Query VSI BW Information
4686  * @vsi: the VSI to be queried
4687  *
4688  * Returns 0 on success, negative value on failure
4689  */
4690 static enum i40e_status_code
4691 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4692 {
4693         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4694         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4695         struct i40e_hw *hw = &vsi->adapter->hw;
4696         i40e_status ret;
4697         int i;
4698         uint32_t bw_max;
4699
4700         memset(&bw_config, 0, sizeof(bw_config));
4701         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4702         if (ret != I40E_SUCCESS) {
4703                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4704                             hw->aq.asq_last_status);
4705                 return ret;
4706         }
4707
4708         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4709         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4710                                         &ets_sla_config, NULL);
4711         if (ret != I40E_SUCCESS) {
4712                 PMD_DRV_LOG(ERR,
4713                         "VSI failed to get TC bandwdith configuration %u",
4714                         hw->aq.asq_last_status);
4715                 return ret;
4716         }
4717
4718         /* store and print out BW info */
4719         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4720         vsi->bw_info.bw_max = bw_config.max_bw;
4721         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4722         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4723         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4724                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4725                      I40E_16_BIT_WIDTH);
4726         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4727                 vsi->bw_info.bw_ets_share_credits[i] =
4728                                 ets_sla_config.share_credits[i];
4729                 vsi->bw_info.bw_ets_credits[i] =
4730                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4731                 /* 4 bits per TC, 4th bit is reserved */
4732                 vsi->bw_info.bw_ets_max[i] =
4733                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4734                                   RTE_LEN2MASK(3, uint8_t));
4735                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4736                             vsi->bw_info.bw_ets_share_credits[i]);
4737                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4738                             vsi->bw_info.bw_ets_credits[i]);
4739                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4740                             vsi->bw_info.bw_ets_max[i]);
4741         }
4742
4743         return I40E_SUCCESS;
4744 }
4745
4746 /* i40e_enable_pf_lb
4747  * @pf: pointer to the pf structure
4748  *
4749  * allow loopback on pf
4750  */
4751 static inline void
4752 i40e_enable_pf_lb(struct i40e_pf *pf)
4753 {
4754         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4755         struct i40e_vsi_context ctxt;
4756         int ret;
4757
4758         /* Use the FW API if FW >= v5.0 */
4759         if (hw->aq.fw_maj_ver < 5) {
4760                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4761                 return;
4762         }
4763
4764         memset(&ctxt, 0, sizeof(ctxt));
4765         ctxt.seid = pf->main_vsi_seid;
4766         ctxt.pf_num = hw->pf_id;
4767         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4768         if (ret) {
4769                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4770                             ret, hw->aq.asq_last_status);
4771                 return;
4772         }
4773         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4774         ctxt.info.valid_sections =
4775                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4776         ctxt.info.switch_id |=
4777                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4778
4779         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4780         if (ret)
4781                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4782                             hw->aq.asq_last_status);
4783 }
4784
4785 /* Setup a VSI */
4786 struct i40e_vsi *
4787 i40e_vsi_setup(struct i40e_pf *pf,
4788                enum i40e_vsi_type type,
4789                struct i40e_vsi *uplink_vsi,
4790                uint16_t user_param)
4791 {
4792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4793         struct i40e_vsi *vsi;
4794         struct i40e_mac_filter_info filter;
4795         int ret;
4796         struct i40e_vsi_context ctxt;
4797         struct ether_addr broadcast =
4798                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4799
4800         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4801             uplink_vsi == NULL) {
4802                 PMD_DRV_LOG(ERR,
4803                         "VSI setup failed, VSI link shouldn't be NULL");
4804                 return NULL;
4805         }
4806
4807         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4808                 PMD_DRV_LOG(ERR,
4809                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4810                 return NULL;
4811         }
4812
4813         /* two situations
4814          * 1.type is not MAIN and uplink vsi is not NULL
4815          * If uplink vsi didn't setup VEB, create one first under veb field
4816          * 2.type is SRIOV and the uplink is NULL
4817          * If floating VEB is NULL, create one veb under floating veb field
4818          */
4819
4820         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4821             uplink_vsi->veb == NULL) {
4822                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4823
4824                 if (uplink_vsi->veb == NULL) {
4825                         PMD_DRV_LOG(ERR, "VEB setup failed");
4826                         return NULL;
4827                 }
4828                 /* set ALLOWLOOPBACk on pf, when veb is created */
4829                 i40e_enable_pf_lb(pf);
4830         }
4831
4832         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4833             pf->main_vsi->floating_veb == NULL) {
4834                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4835
4836                 if (pf->main_vsi->floating_veb == NULL) {
4837                         PMD_DRV_LOG(ERR, "VEB setup failed");
4838                         return NULL;
4839                 }
4840         }
4841
4842         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4843         if (!vsi) {
4844                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4845                 return NULL;
4846         }
4847         TAILQ_INIT(&vsi->mac_list);
4848         vsi->type = type;
4849         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4850         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4851         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4852         vsi->user_param = user_param;
4853         vsi->vlan_anti_spoof_on = 0;
4854         vsi->vlan_filter_on = 0;
4855         /* Allocate queues */
4856         switch (vsi->type) {
4857         case I40E_VSI_MAIN  :
4858                 vsi->nb_qps = pf->lan_nb_qps;
4859                 break;
4860         case I40E_VSI_SRIOV :
4861                 vsi->nb_qps = pf->vf_nb_qps;
4862                 break;
4863         case I40E_VSI_VMDQ2:
4864                 vsi->nb_qps = pf->vmdq_nb_qps;
4865                 break;
4866         case I40E_VSI_FDIR:
4867                 vsi->nb_qps = pf->fdir_nb_qps;
4868                 break;
4869         default:
4870                 goto fail_mem;
4871         }
4872         /*
4873          * The filter status descriptor is reported in rx queue 0,
4874          * while the tx queue for fdir filter programming has no
4875          * such constraints, can be non-zero queues.
4876          * To simplify it, choose FDIR vsi use queue 0 pair.
4877          * To make sure it will use queue 0 pair, queue allocation
4878          * need be done before this function is called
4879          */
4880         if (type != I40E_VSI_FDIR) {
4881                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4882                         if (ret < 0) {
4883                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4884                                                 vsi->seid, ret);
4885                                 goto fail_mem;
4886                         }
4887                         vsi->base_queue = ret;
4888         } else
4889                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4890
4891         /* VF has MSIX interrupt in VF range, don't allocate here */
4892         if (type == I40E_VSI_MAIN) {
4893                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4894                                           RTE_MIN(vsi->nb_qps,
4895                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4896                 if (ret < 0) {
4897                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4898                                     vsi->seid, ret);
4899                         goto fail_queue_alloc;
4900                 }
4901                 vsi->msix_intr = ret;
4902                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4903         } else if (type != I40E_VSI_SRIOV) {
4904                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4905                 if (ret < 0) {
4906                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4907                         goto fail_queue_alloc;
4908                 }
4909                 vsi->msix_intr = ret;
4910                 vsi->nb_msix = 1;
4911         } else {
4912                 vsi->msix_intr = 0;
4913                 vsi->nb_msix = 0;
4914         }
4915
4916         /* Add VSI */
4917         if (type == I40E_VSI_MAIN) {
4918                 /* For main VSI, no need to add since it's default one */
4919                 vsi->uplink_seid = pf->mac_seid;
4920                 vsi->seid = pf->main_vsi_seid;
4921                 /* Bind queues with specific MSIX interrupt */
4922                 /**
4923                  * Needs 2 interrupt at least, one for misc cause which will
4924                  * enabled from OS side, Another for queues binding the
4925                  * interrupt from device side only.
4926                  */
4927
4928                 /* Get default VSI parameters from hardware */
4929                 memset(&ctxt, 0, sizeof(ctxt));
4930                 ctxt.seid = vsi->seid;
4931                 ctxt.pf_num = hw->pf_id;
4932                 ctxt.uplink_seid = vsi->uplink_seid;
4933                 ctxt.vf_num = 0;
4934                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4935                 if (ret != I40E_SUCCESS) {
4936                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4937                         goto fail_msix_alloc;
4938                 }
4939                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4940                         sizeof(struct i40e_aqc_vsi_properties_data));
4941                 vsi->vsi_id = ctxt.vsi_number;
4942                 vsi->info.valid_sections = 0;
4943
4944                 /* Configure tc, enabled TC0 only */
4945                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4946                         I40E_SUCCESS) {
4947                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4948                         goto fail_msix_alloc;
4949                 }
4950
4951                 /* TC, queue mapping */
4952                 memset(&ctxt, 0, sizeof(ctxt));
4953                 vsi->info.valid_sections |=
4954                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4955                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4956                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4957                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4958                         sizeof(struct i40e_aqc_vsi_properties_data));
4959                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4960                                                 I40E_DEFAULT_TCMAP);
4961                 if (ret != I40E_SUCCESS) {
4962                         PMD_DRV_LOG(ERR,
4963                                 "Failed to configure TC queue mapping");
4964                         goto fail_msix_alloc;
4965                 }
4966                 ctxt.seid = vsi->seid;
4967                 ctxt.pf_num = hw->pf_id;
4968                 ctxt.uplink_seid = vsi->uplink_seid;
4969                 ctxt.vf_num = 0;
4970
4971                 /* Update VSI parameters */
4972                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4973                 if (ret != I40E_SUCCESS) {
4974                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4975                         goto fail_msix_alloc;
4976                 }
4977
4978                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4979                                                 sizeof(vsi->info.tc_mapping));
4980                 (void)rte_memcpy(&vsi->info.queue_mapping,
4981                                 &ctxt.info.queue_mapping,
4982                         sizeof(vsi->info.queue_mapping));
4983                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4984                 vsi->info.valid_sections = 0;
4985
4986                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4987                                 ETH_ADDR_LEN);
4988
4989                 /**
4990                  * Updating default filter settings are necessary to prevent
4991                  * reception of tagged packets.
4992                  * Some old firmware configurations load a default macvlan
4993                  * filter which accepts both tagged and untagged packets.
4994                  * The updating is to use a normal filter instead if needed.
4995                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4996                  * The firmware with correct configurations load the default
4997                  * macvlan filter which is expected and cannot be removed.
4998                  */
4999                 i40e_update_default_filter_setting(vsi);
5000                 i40e_config_qinq(hw, vsi);
5001         } else if (type == I40E_VSI_SRIOV) {
5002                 memset(&ctxt, 0, sizeof(ctxt));
5003                 /**
5004                  * For other VSI, the uplink_seid equals to uplink VSI's
5005                  * uplink_seid since they share same VEB
5006                  */
5007                 if (uplink_vsi == NULL)
5008                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5009                 else
5010                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5011                 ctxt.pf_num = hw->pf_id;
5012                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5013                 ctxt.uplink_seid = vsi->uplink_seid;
5014                 ctxt.connection_type = 0x1;
5015                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5016
5017                 /* Use the VEB configuration if FW >= v5.0 */
5018                 if (hw->aq.fw_maj_ver >= 5) {
5019                         /* Configure switch ID */
5020                         ctxt.info.valid_sections |=
5021                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5022                         ctxt.info.switch_id =
5023                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5024                 }
5025
5026                 /* Configure port/vlan */
5027                 ctxt.info.valid_sections |=
5028                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5029                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5030                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5031                                                 hw->func_caps.enabled_tcmap);
5032                 if (ret != I40E_SUCCESS) {
5033                         PMD_DRV_LOG(ERR,
5034                                 "Failed to configure TC queue mapping");
5035                         goto fail_msix_alloc;
5036                 }
5037
5038                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5039                 ctxt.info.valid_sections |=
5040                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5041                 /**
5042                  * Since VSI is not created yet, only configure parameter,
5043                  * will add vsi below.
5044                  */
5045
5046                 i40e_config_qinq(hw, vsi);
5047         } else if (type == I40E_VSI_VMDQ2) {
5048                 memset(&ctxt, 0, sizeof(ctxt));
5049                 /*
5050                  * For other VSI, the uplink_seid equals to uplink VSI's
5051                  * uplink_seid since they share same VEB
5052                  */
5053                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5054                 ctxt.pf_num = hw->pf_id;
5055                 ctxt.vf_num = 0;
5056                 ctxt.uplink_seid = vsi->uplink_seid;
5057                 ctxt.connection_type = 0x1;
5058                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5059
5060                 ctxt.info.valid_sections |=
5061                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5062                 /* user_param carries flag to enable loop back */
5063                 if (user_param) {
5064                         ctxt.info.switch_id =
5065                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5066                         ctxt.info.switch_id |=
5067                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5068                 }
5069
5070                 /* Configure port/vlan */
5071                 ctxt.info.valid_sections |=
5072                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5073                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5074                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5075                                                 I40E_DEFAULT_TCMAP);
5076                 if (ret != I40E_SUCCESS) {
5077                         PMD_DRV_LOG(ERR,
5078                                 "Failed to configure TC queue mapping");
5079                         goto fail_msix_alloc;
5080                 }
5081                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5082                 ctxt.info.valid_sections |=
5083                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5084         } else if (type == I40E_VSI_FDIR) {
5085                 memset(&ctxt, 0, sizeof(ctxt));
5086                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5087                 ctxt.pf_num = hw->pf_id;
5088                 ctxt.vf_num = 0;
5089                 ctxt.uplink_seid = vsi->uplink_seid;
5090                 ctxt.connection_type = 0x1;     /* regular data port */
5091                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5092                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5093                                                 I40E_DEFAULT_TCMAP);
5094                 if (ret != I40E_SUCCESS) {
5095                         PMD_DRV_LOG(ERR,
5096                                 "Failed to configure TC queue mapping.");
5097                         goto fail_msix_alloc;
5098                 }
5099                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5100                 ctxt.info.valid_sections |=
5101                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5102         } else {
5103                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5104                 goto fail_msix_alloc;
5105         }
5106
5107         if (vsi->type != I40E_VSI_MAIN) {
5108                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5109                 if (ret != I40E_SUCCESS) {
5110                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5111                                     hw->aq.asq_last_status);
5112                         goto fail_msix_alloc;
5113                 }
5114                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5115                 vsi->info.valid_sections = 0;
5116                 vsi->seid = ctxt.seid;
5117                 vsi->vsi_id = ctxt.vsi_number;
5118                 vsi->sib_vsi_list.vsi = vsi;
5119                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5120                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5121                                           &vsi->sib_vsi_list, list);
5122                 } else {
5123                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5124                                           &vsi->sib_vsi_list, list);
5125                 }
5126         }
5127
5128         /* MAC/VLAN configuration */
5129         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5130         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5131
5132         ret = i40e_vsi_add_mac(vsi, &filter);
5133         if (ret != I40E_SUCCESS) {
5134                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5135                 goto fail_msix_alloc;
5136         }
5137
5138         /* Get VSI BW information */
5139         i40e_vsi_get_bw_config(vsi);
5140         return vsi;
5141 fail_msix_alloc:
5142         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5143 fail_queue_alloc:
5144         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5145 fail_mem:
5146         rte_free(vsi);
5147         return NULL;
5148 }
5149
5150 /* Configure vlan filter on or off */
5151 int
5152 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5153 {
5154         int i, num;
5155         struct i40e_mac_filter *f;
5156         void *temp;
5157         struct i40e_mac_filter_info *mac_filter;
5158         enum rte_mac_filter_type desired_filter;
5159         int ret = I40E_SUCCESS;
5160
5161         if (on) {
5162                 /* Filter to match MAC and VLAN */
5163                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5164         } else {
5165                 /* Filter to match only MAC */
5166                 desired_filter = RTE_MAC_PERFECT_MATCH;
5167         }
5168
5169         num = vsi->mac_num;
5170
5171         mac_filter = rte_zmalloc("mac_filter_info_data",
5172                                  num * sizeof(*mac_filter), 0);
5173         if (mac_filter == NULL) {
5174                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5175                 return I40E_ERR_NO_MEMORY;
5176         }
5177
5178         i = 0;
5179
5180         /* Remove all existing mac */
5181         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5182                 mac_filter[i] = f->mac_info;
5183                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5184                 if (ret) {
5185                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5186                                     on ? "enable" : "disable");
5187                         goto DONE;
5188                 }
5189                 i++;
5190         }
5191
5192         /* Override with new filter */
5193         for (i = 0; i < num; i++) {
5194                 mac_filter[i].filter_type = desired_filter;
5195                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5196                 if (ret) {
5197                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5198                                     on ? "enable" : "disable");
5199                         goto DONE;
5200                 }
5201         }
5202
5203 DONE:
5204         rte_free(mac_filter);
5205         return ret;
5206 }
5207
5208 /* Configure vlan stripping on or off */
5209 int
5210 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5211 {
5212         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5213         struct i40e_vsi_context ctxt;
5214         uint8_t vlan_flags;
5215         int ret = I40E_SUCCESS;
5216
5217         /* Check if it has been already on or off */
5218         if (vsi->info.valid_sections &
5219                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5220                 if (on) {
5221                         if ((vsi->info.port_vlan_flags &
5222                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5223                                 return 0; /* already on */
5224                 } else {
5225                         if ((vsi->info.port_vlan_flags &
5226                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5227                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5228                                 return 0; /* already off */
5229                 }
5230         }
5231
5232         if (on)
5233                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5234         else
5235                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5236         vsi->info.valid_sections =
5237                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5238         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5239         vsi->info.port_vlan_flags |= vlan_flags;
5240         ctxt.seid = vsi->seid;
5241         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5242         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5243         if (ret)
5244                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5245                             on ? "enable" : "disable");
5246
5247         return ret;
5248 }
5249
5250 static int
5251 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5252 {
5253         struct rte_eth_dev_data *data = dev->data;
5254         int ret;
5255         int mask = 0;
5256
5257         /* Apply vlan offload setting */
5258         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5259         i40e_vlan_offload_set(dev, mask);
5260
5261         /* Apply double-vlan setting, not implemented yet */
5262
5263         /* Apply pvid setting */
5264         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5265                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5266         if (ret)
5267                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5268
5269         return ret;
5270 }
5271
5272 static int
5273 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5274 {
5275         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5276
5277         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5278 }
5279
5280 static int
5281 i40e_update_flow_control(struct i40e_hw *hw)
5282 {
5283 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5284         struct i40e_link_status link_status;
5285         uint32_t rxfc = 0, txfc = 0, reg;
5286         uint8_t an_info;
5287         int ret;
5288
5289         memset(&link_status, 0, sizeof(link_status));
5290         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5291         if (ret != I40E_SUCCESS) {
5292                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5293                 goto write_reg; /* Disable flow control */
5294         }
5295
5296         an_info = hw->phy.link_info.an_info;
5297         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5298                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5299                 ret = I40E_ERR_NOT_READY;
5300                 goto write_reg; /* Disable flow control */
5301         }
5302         /**
5303          * If link auto negotiation is enabled, flow control needs to
5304          * be configured according to it
5305          */
5306         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5307         case I40E_LINK_PAUSE_RXTX:
5308                 rxfc = 1;
5309                 txfc = 1;
5310                 hw->fc.current_mode = I40E_FC_FULL;
5311                 break;
5312         case I40E_AQ_LINK_PAUSE_RX:
5313                 rxfc = 1;
5314                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5315                 break;
5316         case I40E_AQ_LINK_PAUSE_TX:
5317                 txfc = 1;
5318                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5319                 break;
5320         default:
5321                 hw->fc.current_mode = I40E_FC_NONE;
5322                 break;
5323         }
5324
5325 write_reg:
5326         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5327                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5328         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5329         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5330         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5331         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5332
5333         return ret;
5334 }
5335
5336 /* PF setup */
5337 static int
5338 i40e_pf_setup(struct i40e_pf *pf)
5339 {
5340         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5341         struct i40e_filter_control_settings settings;
5342         struct i40e_vsi *vsi;
5343         int ret;
5344
5345         /* Clear all stats counters */
5346         pf->offset_loaded = FALSE;
5347         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5348         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5349         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5350         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5351
5352         ret = i40e_pf_get_switch_config(pf);
5353         if (ret != I40E_SUCCESS) {
5354                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5355                 return ret;
5356         }
5357         if (pf->flags & I40E_FLAG_FDIR) {
5358                 /* make queue allocated first, let FDIR use queue pair 0*/
5359                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5360                 if (ret != I40E_FDIR_QUEUE_ID) {
5361                         PMD_DRV_LOG(ERR,
5362                                 "queue allocation fails for FDIR: ret =%d",
5363                                 ret);
5364                         pf->flags &= ~I40E_FLAG_FDIR;
5365                 }
5366         }
5367         /*  main VSI setup */
5368         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5369         if (!vsi) {
5370                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5371                 return I40E_ERR_NOT_READY;
5372         }
5373         pf->main_vsi = vsi;
5374
5375         /* Configure filter control */
5376         memset(&settings, 0, sizeof(settings));
5377         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5378                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5379         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5380                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5381         else {
5382                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5383                         hw->func_caps.rss_table_size);
5384                 return I40E_ERR_PARAM;
5385         }
5386         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5387                 hw->func_caps.rss_table_size);
5388         pf->hash_lut_size = hw->func_caps.rss_table_size;
5389
5390         /* Enable ethtype and macvlan filters */
5391         settings.enable_ethtype = TRUE;
5392         settings.enable_macvlan = TRUE;
5393         ret = i40e_set_filter_control(hw, &settings);
5394         if (ret)
5395                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5396                                                                 ret);
5397
5398         /* Update flow control according to the auto negotiation */
5399         i40e_update_flow_control(hw);
5400
5401         return I40E_SUCCESS;
5402 }
5403
5404 int
5405 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5406 {
5407         uint32_t reg;
5408         uint16_t j;
5409
5410         /**
5411          * Set or clear TX Queue Disable flags,
5412          * which is required by hardware.
5413          */
5414         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5415         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5416
5417         /* Wait until the request is finished */
5418         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5419                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5420                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5421                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5422                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5423                                                         & 0x1))) {
5424                         break;
5425                 }
5426         }
5427         if (on) {
5428                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5429                         return I40E_SUCCESS; /* already on, skip next steps */
5430
5431                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5432                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5433         } else {
5434                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5435                         return I40E_SUCCESS; /* already off, skip next steps */
5436                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5437         }
5438         /* Write the register */
5439         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5440         /* Check the result */
5441         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5442                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5443                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5444                 if (on) {
5445                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5446                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5447                                 break;
5448                 } else {
5449                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5450                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5451                                 break;
5452                 }
5453         }
5454         /* Check if it is timeout */
5455         if (j >= I40E_CHK_Q_ENA_COUNT) {
5456                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5457                             (on ? "enable" : "disable"), q_idx);
5458                 return I40E_ERR_TIMEOUT;
5459         }
5460
5461         return I40E_SUCCESS;
5462 }
5463
5464 /* Swith on or off the tx queues */
5465 static int
5466 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5467 {
5468         struct rte_eth_dev_data *dev_data = pf->dev_data;
5469         struct i40e_tx_queue *txq;
5470         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5471         uint16_t i;
5472         int ret;
5473
5474         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5475                 txq = dev_data->tx_queues[i];
5476                 /* Don't operate the queue if not configured or
5477                  * if starting only per queue */
5478                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5479                         continue;
5480                 if (on)
5481                         ret = i40e_dev_tx_queue_start(dev, i);
5482                 else
5483                         ret = i40e_dev_tx_queue_stop(dev, i);
5484                 if ( ret != I40E_SUCCESS)
5485                         return ret;
5486         }
5487
5488         return I40E_SUCCESS;
5489 }
5490
5491 int
5492 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5493 {
5494         uint32_t reg;
5495         uint16_t j;
5496
5497         /* Wait until the request is finished */
5498         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5499                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5500                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5501                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5502                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5503                         break;
5504         }
5505
5506         if (on) {
5507                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5508                         return I40E_SUCCESS; /* Already on, skip next steps */
5509                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5510         } else {
5511                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5512                         return I40E_SUCCESS; /* Already off, skip next steps */
5513                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5514         }
5515
5516         /* Write the register */
5517         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5518         /* Check the result */
5519         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5520                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5521                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5522                 if (on) {
5523                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5524                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5525                                 break;
5526                 } else {
5527                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5528                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5529                                 break;
5530                 }
5531         }
5532
5533         /* Check if it is timeout */
5534         if (j >= I40E_CHK_Q_ENA_COUNT) {
5535                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5536                             (on ? "enable" : "disable"), q_idx);
5537                 return I40E_ERR_TIMEOUT;
5538         }
5539
5540         return I40E_SUCCESS;
5541 }
5542 /* Switch on or off the rx queues */
5543 static int
5544 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5545 {
5546         struct rte_eth_dev_data *dev_data = pf->dev_data;
5547         struct i40e_rx_queue *rxq;
5548         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5549         uint16_t i;
5550         int ret;
5551
5552         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5553                 rxq = dev_data->rx_queues[i];
5554                 /* Don't operate the queue if not configured or
5555                  * if starting only per queue */
5556                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5557                         continue;
5558                 if (on)
5559                         ret = i40e_dev_rx_queue_start(dev, i);
5560                 else
5561                         ret = i40e_dev_rx_queue_stop(dev, i);
5562                 if (ret != I40E_SUCCESS)
5563                         return ret;
5564         }
5565
5566         return I40E_SUCCESS;
5567 }
5568
5569 /* Switch on or off all the rx/tx queues */
5570 int
5571 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5572 {
5573         int ret;
5574
5575         if (on) {
5576                 /* enable rx queues before enabling tx queues */
5577                 ret = i40e_dev_switch_rx_queues(pf, on);
5578                 if (ret) {
5579                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5580                         return ret;
5581                 }
5582                 ret = i40e_dev_switch_tx_queues(pf, on);
5583         } else {
5584                 /* Stop tx queues before stopping rx queues */
5585                 ret = i40e_dev_switch_tx_queues(pf, on);
5586                 if (ret) {
5587                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5588                         return ret;
5589                 }
5590                 ret = i40e_dev_switch_rx_queues(pf, on);
5591         }
5592
5593         return ret;
5594 }
5595
5596 /* Initialize VSI for TX */
5597 static int
5598 i40e_dev_tx_init(struct i40e_pf *pf)
5599 {
5600         struct rte_eth_dev_data *data = pf->dev_data;
5601         uint16_t i;
5602         uint32_t ret = I40E_SUCCESS;
5603         struct i40e_tx_queue *txq;
5604
5605         for (i = 0; i < data->nb_tx_queues; i++) {
5606                 txq = data->tx_queues[i];
5607                 if (!txq || !txq->q_set)
5608                         continue;
5609                 ret = i40e_tx_queue_init(txq);
5610                 if (ret != I40E_SUCCESS)
5611                         break;
5612         }
5613         if (ret == I40E_SUCCESS)
5614                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5615                                      ->eth_dev);
5616
5617         return ret;
5618 }
5619
5620 /* Initialize VSI for RX */
5621 static int
5622 i40e_dev_rx_init(struct i40e_pf *pf)
5623 {
5624         struct rte_eth_dev_data *data = pf->dev_data;
5625         int ret = I40E_SUCCESS;
5626         uint16_t i;
5627         struct i40e_rx_queue *rxq;
5628
5629         i40e_pf_config_mq_rx(pf);
5630         for (i = 0; i < data->nb_rx_queues; i++) {
5631                 rxq = data->rx_queues[i];
5632                 if (!rxq || !rxq->q_set)
5633                         continue;
5634
5635                 ret = i40e_rx_queue_init(rxq);
5636                 if (ret != I40E_SUCCESS) {
5637                         PMD_DRV_LOG(ERR,
5638                                 "Failed to do RX queue initialization");
5639                         break;
5640                 }
5641         }
5642         if (ret == I40E_SUCCESS)
5643                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5644                                      ->eth_dev);
5645
5646         return ret;
5647 }
5648
5649 static int
5650 i40e_dev_rxtx_init(struct i40e_pf *pf)
5651 {
5652         int err;
5653
5654         err = i40e_dev_tx_init(pf);
5655         if (err) {
5656                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5657                 return err;
5658         }
5659         err = i40e_dev_rx_init(pf);
5660         if (err) {
5661                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5662                 return err;
5663         }
5664
5665         return err;
5666 }
5667
5668 static int
5669 i40e_vmdq_setup(struct rte_eth_dev *dev)
5670 {
5671         struct rte_eth_conf *conf = &dev->data->dev_conf;
5672         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5673         int i, err, conf_vsis, j, loop;
5674         struct i40e_vsi *vsi;
5675         struct i40e_vmdq_info *vmdq_info;
5676         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5677         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5678
5679         /*
5680          * Disable interrupt to avoid message from VF. Furthermore, it will
5681          * avoid race condition in VSI creation/destroy.
5682          */
5683         i40e_pf_disable_irq0(hw);
5684
5685         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5686                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5687                 return -ENOTSUP;
5688         }
5689
5690         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5691         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5692                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5693                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5694                         pf->max_nb_vmdq_vsi);
5695                 return -ENOTSUP;
5696         }
5697
5698         if (pf->vmdq != NULL) {
5699                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5700                 return 0;
5701         }
5702
5703         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5704                                 sizeof(*vmdq_info) * conf_vsis, 0);
5705
5706         if (pf->vmdq == NULL) {
5707                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5708                 return -ENOMEM;
5709         }
5710
5711         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5712
5713         /* Create VMDQ VSI */
5714         for (i = 0; i < conf_vsis; i++) {
5715                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5716                                 vmdq_conf->enable_loop_back);
5717                 if (vsi == NULL) {
5718                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5719                         err = -1;
5720                         goto err_vsi_setup;
5721                 }
5722                 vmdq_info = &pf->vmdq[i];
5723                 vmdq_info->pf = pf;
5724                 vmdq_info->vsi = vsi;
5725         }
5726         pf->nb_cfg_vmdq_vsi = conf_vsis;
5727
5728         /* Configure Vlan */
5729         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5730         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5731                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5732                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5733                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5734                                         vmdq_conf->pool_map[i].vlan_id, j);
5735
5736                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5737                                                 vmdq_conf->pool_map[i].vlan_id);
5738                                 if (err) {
5739                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5740                                         err = -1;
5741                                         goto err_vsi_setup;
5742                                 }
5743                         }
5744                 }
5745         }
5746
5747         i40e_pf_enable_irq0(hw);
5748
5749         return 0;
5750
5751 err_vsi_setup:
5752         for (i = 0; i < conf_vsis; i++)
5753                 if (pf->vmdq[i].vsi == NULL)
5754                         break;
5755                 else
5756                         i40e_vsi_release(pf->vmdq[i].vsi);
5757
5758         rte_free(pf->vmdq);
5759         pf->vmdq = NULL;
5760         i40e_pf_enable_irq0(hw);
5761         return err;
5762 }
5763
5764 static void
5765 i40e_stat_update_32(struct i40e_hw *hw,
5766                    uint32_t reg,
5767                    bool offset_loaded,
5768                    uint64_t *offset,
5769                    uint64_t *stat)
5770 {
5771         uint64_t new_data;
5772
5773         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5774         if (!offset_loaded)
5775                 *offset = new_data;
5776
5777         if (new_data >= *offset)
5778                 *stat = (uint64_t)(new_data - *offset);
5779         else
5780                 *stat = (uint64_t)((new_data +
5781                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5782 }
5783
5784 static void
5785 i40e_stat_update_48(struct i40e_hw *hw,
5786                    uint32_t hireg,
5787                    uint32_t loreg,
5788                    bool offset_loaded,
5789                    uint64_t *offset,
5790                    uint64_t *stat)
5791 {
5792         uint64_t new_data;
5793
5794         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5795         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5796                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5797
5798         if (!offset_loaded)
5799                 *offset = new_data;
5800
5801         if (new_data >= *offset)
5802                 *stat = new_data - *offset;
5803         else
5804                 *stat = (uint64_t)((new_data +
5805                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5806
5807         *stat &= I40E_48_BIT_MASK;
5808 }
5809
5810 /* Disable IRQ0 */
5811 void
5812 i40e_pf_disable_irq0(struct i40e_hw *hw)
5813 {
5814         /* Disable all interrupt types */
5815         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5816         I40E_WRITE_FLUSH(hw);
5817 }
5818
5819 /* Enable IRQ0 */
5820 void
5821 i40e_pf_enable_irq0(struct i40e_hw *hw)
5822 {
5823         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5824                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5825                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5826                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5827         I40E_WRITE_FLUSH(hw);
5828 }
5829
5830 static void
5831 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5832 {
5833         /* read pending request and disable first */
5834         i40e_pf_disable_irq0(hw);
5835         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5836         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5837                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5838
5839         if (no_queue)
5840                 /* Link no queues with irq0 */
5841                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5842                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5843 }
5844
5845 static void
5846 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5847 {
5848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5850         int i;
5851         uint16_t abs_vf_id;
5852         uint32_t index, offset, val;
5853
5854         if (!pf->vfs)
5855                 return;
5856         /**
5857          * Try to find which VF trigger a reset, use absolute VF id to access
5858          * since the reg is global register.
5859          */
5860         for (i = 0; i < pf->vf_num; i++) {
5861                 abs_vf_id = hw->func_caps.vf_base_id + i;
5862                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5863                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5864                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5865                 /* VFR event occurred */
5866                 if (val & (0x1 << offset)) {
5867                         int ret;
5868
5869                         /* Clear the event first */
5870                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5871                                                         (0x1 << offset));
5872                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5873                         /**
5874                          * Only notify a VF reset event occurred,
5875                          * don't trigger another SW reset
5876                          */
5877                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5878                         if (ret != I40E_SUCCESS)
5879                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5880                 }
5881         }
5882 }
5883
5884 static void
5885 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5886 {
5887         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5888         int i;
5889
5890         for (i = 0; i < pf->vf_num; i++)
5891                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5892 }
5893
5894 static void
5895 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5896 {
5897         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5898         struct i40e_arq_event_info info;
5899         uint16_t pending, opcode;
5900         int ret;
5901
5902         info.buf_len = I40E_AQ_BUF_SZ;
5903         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5904         if (!info.msg_buf) {
5905                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5906                 return;
5907         }
5908
5909         pending = 1;
5910         while (pending) {
5911                 ret = i40e_clean_arq_element(hw, &info, &pending);
5912
5913                 if (ret != I40E_SUCCESS) {
5914                         PMD_DRV_LOG(INFO,
5915                                 "Failed to read msg from AdminQ, aq_err: %u",
5916                                 hw->aq.asq_last_status);
5917                         break;
5918                 }
5919                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5920
5921                 switch (opcode) {
5922                 case i40e_aqc_opc_send_msg_to_pf:
5923                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5924                         i40e_pf_host_handle_vf_msg(dev,
5925                                         rte_le_to_cpu_16(info.desc.retval),
5926                                         rte_le_to_cpu_32(info.desc.cookie_high),
5927                                         rte_le_to_cpu_32(info.desc.cookie_low),
5928                                         info.msg_buf,
5929                                         info.msg_len);
5930                         break;
5931                 case i40e_aqc_opc_get_link_status:
5932                         ret = i40e_dev_link_update(dev, 0);
5933                         if (!ret)
5934                                 _rte_eth_dev_callback_process(dev,
5935                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5936                         break;
5937                 default:
5938                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5939                                     opcode);
5940                         break;
5941                 }
5942         }
5943         rte_free(info.msg_buf);
5944 }
5945
5946 /**
5947  * Interrupt handler triggered by NIC  for handling
5948  * specific interrupt.
5949  *
5950  * @param handle
5951  *  Pointer to interrupt handle.
5952  * @param param
5953  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5954  *
5955  * @return
5956  *  void
5957  */
5958 static void
5959 i40e_dev_interrupt_handler(void *param)
5960 {
5961         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5962         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5963         uint32_t icr0;
5964
5965         /* Disable interrupt */
5966         i40e_pf_disable_irq0(hw);
5967
5968         /* read out interrupt causes */
5969         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5970
5971         /* No interrupt event indicated */
5972         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5973                 PMD_DRV_LOG(INFO, "No interrupt event");
5974                 goto done;
5975         }
5976         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5977                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5978         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5979                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5980         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5981                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5982         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5983                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5984         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5985                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5986         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5987                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5988         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5989                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5990
5991         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5992                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5993                 i40e_dev_handle_vfr_event(dev);
5994         }
5995         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5996                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5997                 i40e_dev_handle_aq_msg(dev);
5998         }
5999
6000 done:
6001         /* Enable interrupt */
6002         i40e_pf_enable_irq0(hw);
6003         rte_intr_enable(dev->intr_handle);
6004 }
6005
6006 int
6007 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6008                          struct i40e_macvlan_filter *filter,
6009                          int total)
6010 {
6011         int ele_num, ele_buff_size;
6012         int num, actual_num, i;
6013         uint16_t flags;
6014         int ret = I40E_SUCCESS;
6015         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6016         struct i40e_aqc_add_macvlan_element_data *req_list;
6017
6018         if (filter == NULL  || total == 0)
6019                 return I40E_ERR_PARAM;
6020         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6021         ele_buff_size = hw->aq.asq_buf_size;
6022
6023         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6024         if (req_list == NULL) {
6025                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6026                 return I40E_ERR_NO_MEMORY;
6027         }
6028
6029         num = 0;
6030         do {
6031                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6032                 memset(req_list, 0, ele_buff_size);
6033
6034                 for (i = 0; i < actual_num; i++) {
6035                         (void)rte_memcpy(req_list[i].mac_addr,
6036                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6037                         req_list[i].vlan_tag =
6038                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6039
6040                         switch (filter[num + i].filter_type) {
6041                         case RTE_MAC_PERFECT_MATCH:
6042                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6043                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6044                                 break;
6045                         case RTE_MACVLAN_PERFECT_MATCH:
6046                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6047                                 break;
6048                         case RTE_MAC_HASH_MATCH:
6049                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6050                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6051                                 break;
6052                         case RTE_MACVLAN_HASH_MATCH:
6053                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6054                                 break;
6055                         default:
6056                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6057                                 ret = I40E_ERR_PARAM;
6058                                 goto DONE;
6059                         }
6060
6061                         req_list[i].queue_number = 0;
6062
6063                         req_list[i].flags = rte_cpu_to_le_16(flags);
6064                 }
6065
6066                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6067                                                 actual_num, NULL);
6068                 if (ret != I40E_SUCCESS) {
6069                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6070                         goto DONE;
6071                 }
6072                 num += actual_num;
6073         } while (num < total);
6074
6075 DONE:
6076         rte_free(req_list);
6077         return ret;
6078 }
6079
6080 int
6081 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6082                             struct i40e_macvlan_filter *filter,
6083                             int total)
6084 {
6085         int ele_num, ele_buff_size;
6086         int num, actual_num, i;
6087         uint16_t flags;
6088         int ret = I40E_SUCCESS;
6089         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6090         struct i40e_aqc_remove_macvlan_element_data *req_list;
6091
6092         if (filter == NULL  || total == 0)
6093                 return I40E_ERR_PARAM;
6094
6095         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6096         ele_buff_size = hw->aq.asq_buf_size;
6097
6098         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6099         if (req_list == NULL) {
6100                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6101                 return I40E_ERR_NO_MEMORY;
6102         }
6103
6104         num = 0;
6105         do {
6106                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6107                 memset(req_list, 0, ele_buff_size);
6108
6109                 for (i = 0; i < actual_num; i++) {
6110                         (void)rte_memcpy(req_list[i].mac_addr,
6111                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6112                         req_list[i].vlan_tag =
6113                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6114
6115                         switch (filter[num + i].filter_type) {
6116                         case RTE_MAC_PERFECT_MATCH:
6117                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6118                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6119                                 break;
6120                         case RTE_MACVLAN_PERFECT_MATCH:
6121                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6122                                 break;
6123                         case RTE_MAC_HASH_MATCH:
6124                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6125                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6126                                 break;
6127                         case RTE_MACVLAN_HASH_MATCH:
6128                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6129                                 break;
6130                         default:
6131                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6132                                 ret = I40E_ERR_PARAM;
6133                                 goto DONE;
6134                         }
6135                         req_list[i].flags = rte_cpu_to_le_16(flags);
6136                 }
6137
6138                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6139                                                 actual_num, NULL);
6140                 if (ret != I40E_SUCCESS) {
6141                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6142                         goto DONE;
6143                 }
6144                 num += actual_num;
6145         } while (num < total);
6146
6147 DONE:
6148         rte_free(req_list);
6149         return ret;
6150 }
6151
6152 /* Find out specific MAC filter */
6153 static struct i40e_mac_filter *
6154 i40e_find_mac_filter(struct i40e_vsi *vsi,
6155                          struct ether_addr *macaddr)
6156 {
6157         struct i40e_mac_filter *f;
6158
6159         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6160                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6161                         return f;
6162         }
6163
6164         return NULL;
6165 }
6166
6167 static bool
6168 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6169                          uint16_t vlan_id)
6170 {
6171         uint32_t vid_idx, vid_bit;
6172
6173         if (vlan_id > ETH_VLAN_ID_MAX)
6174                 return 0;
6175
6176         vid_idx = I40E_VFTA_IDX(vlan_id);
6177         vid_bit = I40E_VFTA_BIT(vlan_id);
6178
6179         if (vsi->vfta[vid_idx] & vid_bit)
6180                 return 1;
6181         else
6182                 return 0;
6183 }
6184
6185 static void
6186 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6187                        uint16_t vlan_id, bool on)
6188 {
6189         uint32_t vid_idx, vid_bit;
6190
6191         vid_idx = I40E_VFTA_IDX(vlan_id);
6192         vid_bit = I40E_VFTA_BIT(vlan_id);
6193
6194         if (on)
6195                 vsi->vfta[vid_idx] |= vid_bit;
6196         else
6197                 vsi->vfta[vid_idx] &= ~vid_bit;
6198 }
6199
6200 void
6201 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6202                      uint16_t vlan_id, bool on)
6203 {
6204         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6205         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6206         int ret;
6207
6208         if (vlan_id > ETH_VLAN_ID_MAX)
6209                 return;
6210
6211         i40e_store_vlan_filter(vsi, vlan_id, on);
6212
6213         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6214                 return;
6215
6216         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6217
6218         if (on) {
6219                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6220                                        &vlan_data, 1, NULL);
6221                 if (ret != I40E_SUCCESS)
6222                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6223         } else {
6224                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6225                                           &vlan_data, 1, NULL);
6226                 if (ret != I40E_SUCCESS)
6227                         PMD_DRV_LOG(ERR,
6228                                     "Failed to remove vlan filter");
6229         }
6230 }
6231
6232 /**
6233  * Find all vlan options for specific mac addr,
6234  * return with actual vlan found.
6235  */
6236 int
6237 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6238                            struct i40e_macvlan_filter *mv_f,
6239                            int num, struct ether_addr *addr)
6240 {
6241         int i;
6242         uint32_t j, k;
6243
6244         /**
6245          * Not to use i40e_find_vlan_filter to decrease the loop time,
6246          * although the code looks complex.
6247           */
6248         if (num < vsi->vlan_num)
6249                 return I40E_ERR_PARAM;
6250
6251         i = 0;
6252         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6253                 if (vsi->vfta[j]) {
6254                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6255                                 if (vsi->vfta[j] & (1 << k)) {
6256                                         if (i > num - 1) {
6257                                                 PMD_DRV_LOG(ERR,
6258                                                         "vlan number doesn't match");
6259                                                 return I40E_ERR_PARAM;
6260                                         }
6261                                         (void)rte_memcpy(&mv_f[i].macaddr,
6262                                                         addr, ETH_ADDR_LEN);
6263                                         mv_f[i].vlan_id =
6264                                                 j * I40E_UINT32_BIT_SIZE + k;
6265                                         i++;
6266                                 }
6267                         }
6268                 }
6269         }
6270         return I40E_SUCCESS;
6271 }
6272
6273 static inline int
6274 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6275                            struct i40e_macvlan_filter *mv_f,
6276                            int num,
6277                            uint16_t vlan)
6278 {
6279         int i = 0;
6280         struct i40e_mac_filter *f;
6281
6282         if (num < vsi->mac_num)
6283                 return I40E_ERR_PARAM;
6284
6285         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6286                 if (i > num - 1) {
6287                         PMD_DRV_LOG(ERR, "buffer number not match");
6288                         return I40E_ERR_PARAM;
6289                 }
6290                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6291                                 ETH_ADDR_LEN);
6292                 mv_f[i].vlan_id = vlan;
6293                 mv_f[i].filter_type = f->mac_info.filter_type;
6294                 i++;
6295         }
6296
6297         return I40E_SUCCESS;
6298 }
6299
6300 static int
6301 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6302 {
6303         int i, j, num;
6304         struct i40e_mac_filter *f;
6305         struct i40e_macvlan_filter *mv_f;
6306         int ret = I40E_SUCCESS;
6307
6308         if (vsi == NULL || vsi->mac_num == 0)
6309                 return I40E_ERR_PARAM;
6310
6311         /* Case that no vlan is set */
6312         if (vsi->vlan_num == 0)
6313                 num = vsi->mac_num;
6314         else
6315                 num = vsi->mac_num * vsi->vlan_num;
6316
6317         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6318         if (mv_f == NULL) {
6319                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6320                 return I40E_ERR_NO_MEMORY;
6321         }
6322
6323         i = 0;
6324         if (vsi->vlan_num == 0) {
6325                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6326                         (void)rte_memcpy(&mv_f[i].macaddr,
6327                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6328                         mv_f[i].filter_type = f->mac_info.filter_type;
6329                         mv_f[i].vlan_id = 0;
6330                         i++;
6331                 }
6332         } else {
6333                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6334                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6335                                         vsi->vlan_num, &f->mac_info.mac_addr);
6336                         if (ret != I40E_SUCCESS)
6337                                 goto DONE;
6338                         for (j = i; j < i + vsi->vlan_num; j++)
6339                                 mv_f[j].filter_type = f->mac_info.filter_type;
6340                         i += vsi->vlan_num;
6341                 }
6342         }
6343
6344         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6345 DONE:
6346         rte_free(mv_f);
6347
6348         return ret;
6349 }
6350
6351 int
6352 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6353 {
6354         struct i40e_macvlan_filter *mv_f;
6355         int mac_num;
6356         int ret = I40E_SUCCESS;
6357
6358         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6359                 return I40E_ERR_PARAM;
6360
6361         /* If it's already set, just return */
6362         if (i40e_find_vlan_filter(vsi,vlan))
6363                 return I40E_SUCCESS;
6364
6365         mac_num = vsi->mac_num;
6366
6367         if (mac_num == 0) {
6368                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6369                 return I40E_ERR_PARAM;
6370         }
6371
6372         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6373
6374         if (mv_f == NULL) {
6375                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6376                 return I40E_ERR_NO_MEMORY;
6377         }
6378
6379         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6380
6381         if (ret != I40E_SUCCESS)
6382                 goto DONE;
6383
6384         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6385
6386         if (ret != I40E_SUCCESS)
6387                 goto DONE;
6388
6389         i40e_set_vlan_filter(vsi, vlan, 1);
6390
6391         vsi->vlan_num++;
6392         ret = I40E_SUCCESS;
6393 DONE:
6394         rte_free(mv_f);
6395         return ret;
6396 }
6397
6398 int
6399 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6400 {
6401         struct i40e_macvlan_filter *mv_f;
6402         int mac_num;
6403         int ret = I40E_SUCCESS;
6404
6405         /**
6406          * Vlan 0 is the generic filter for untagged packets
6407          * and can't be removed.
6408          */
6409         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6410                 return I40E_ERR_PARAM;
6411
6412         /* If can't find it, just return */
6413         if (!i40e_find_vlan_filter(vsi, vlan))
6414                 return I40E_ERR_PARAM;
6415
6416         mac_num = vsi->mac_num;
6417
6418         if (mac_num == 0) {
6419                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6420                 return I40E_ERR_PARAM;
6421         }
6422
6423         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6424
6425         if (mv_f == NULL) {
6426                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6427                 return I40E_ERR_NO_MEMORY;
6428         }
6429
6430         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6431
6432         if (ret != I40E_SUCCESS)
6433                 goto DONE;
6434
6435         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6436
6437         if (ret != I40E_SUCCESS)
6438                 goto DONE;
6439
6440         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6441         if (vsi->vlan_num == 1) {
6442                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6443                 if (ret != I40E_SUCCESS)
6444                         goto DONE;
6445
6446                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6447                 if (ret != I40E_SUCCESS)
6448                         goto DONE;
6449         }
6450
6451         i40e_set_vlan_filter(vsi, vlan, 0);
6452
6453         vsi->vlan_num--;
6454         ret = I40E_SUCCESS;
6455 DONE:
6456         rte_free(mv_f);
6457         return ret;
6458 }
6459
6460 int
6461 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6462 {
6463         struct i40e_mac_filter *f;
6464         struct i40e_macvlan_filter *mv_f;
6465         int i, vlan_num = 0;
6466         int ret = I40E_SUCCESS;
6467
6468         /* If it's add and we've config it, return */
6469         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6470         if (f != NULL)
6471                 return I40E_SUCCESS;
6472         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6473                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6474
6475                 /**
6476                  * If vlan_num is 0, that's the first time to add mac,
6477                  * set mask for vlan_id 0.
6478                  */
6479                 if (vsi->vlan_num == 0) {
6480                         i40e_set_vlan_filter(vsi, 0, 1);
6481                         vsi->vlan_num = 1;
6482                 }
6483                 vlan_num = vsi->vlan_num;
6484         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6485                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6486                 vlan_num = 1;
6487
6488         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6489         if (mv_f == NULL) {
6490                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6491                 return I40E_ERR_NO_MEMORY;
6492         }
6493
6494         for (i = 0; i < vlan_num; i++) {
6495                 mv_f[i].filter_type = mac_filter->filter_type;
6496                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6497                                 ETH_ADDR_LEN);
6498         }
6499
6500         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6501                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6502                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6503                                         &mac_filter->mac_addr);
6504                 if (ret != I40E_SUCCESS)
6505                         goto DONE;
6506         }
6507
6508         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6509         if (ret != I40E_SUCCESS)
6510                 goto DONE;
6511
6512         /* Add the mac addr into mac list */
6513         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6514         if (f == NULL) {
6515                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6516                 ret = I40E_ERR_NO_MEMORY;
6517                 goto DONE;
6518         }
6519         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6520                         ETH_ADDR_LEN);
6521         f->mac_info.filter_type = mac_filter->filter_type;
6522         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6523         vsi->mac_num++;
6524
6525         ret = I40E_SUCCESS;
6526 DONE:
6527         rte_free(mv_f);
6528
6529         return ret;
6530 }
6531
6532 int
6533 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6534 {
6535         struct i40e_mac_filter *f;
6536         struct i40e_macvlan_filter *mv_f;
6537         int i, vlan_num;
6538         enum rte_mac_filter_type filter_type;
6539         int ret = I40E_SUCCESS;
6540
6541         /* Can't find it, return an error */
6542         f = i40e_find_mac_filter(vsi, addr);
6543         if (f == NULL)
6544                 return I40E_ERR_PARAM;
6545
6546         vlan_num = vsi->vlan_num;
6547         filter_type = f->mac_info.filter_type;
6548         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6549                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6550                 if (vlan_num == 0) {
6551                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6552                         return I40E_ERR_PARAM;
6553                 }
6554         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6555                         filter_type == RTE_MAC_HASH_MATCH)
6556                 vlan_num = 1;
6557
6558         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6559         if (mv_f == NULL) {
6560                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6561                 return I40E_ERR_NO_MEMORY;
6562         }
6563
6564         for (i = 0; i < vlan_num; i++) {
6565                 mv_f[i].filter_type = filter_type;
6566                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6567                                 ETH_ADDR_LEN);
6568         }
6569         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6570                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6571                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6572                 if (ret != I40E_SUCCESS)
6573                         goto DONE;
6574         }
6575
6576         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6577         if (ret != I40E_SUCCESS)
6578                 goto DONE;
6579
6580         /* Remove the mac addr into mac list */
6581         TAILQ_REMOVE(&vsi->mac_list, f, next);
6582         rte_free(f);
6583         vsi->mac_num--;
6584
6585         ret = I40E_SUCCESS;
6586 DONE:
6587         rte_free(mv_f);
6588         return ret;
6589 }
6590
6591 /* Configure hash enable flags for RSS */
6592 uint64_t
6593 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6594 {
6595         uint64_t hena = 0;
6596
6597         if (!flags)
6598                 return hena;
6599
6600         if (flags & ETH_RSS_FRAG_IPV4)
6601                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6602         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6603                 if (type == I40E_MAC_X722) {
6604                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6605                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6606                 } else
6607                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6608         }
6609         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6610                 if (type == I40E_MAC_X722) {
6611                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6612                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6613                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6614                 } else
6615                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6616         }
6617         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6618                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6619         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6620                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6621         if (flags & ETH_RSS_FRAG_IPV6)
6622                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6623         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6624                 if (type == I40E_MAC_X722) {
6625                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6626                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6627                 } else
6628                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6629         }
6630         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6631                 if (type == I40E_MAC_X722) {
6632                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6633                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6634                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6635                 } else
6636                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6637         }
6638         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6639                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6640         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6641                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6642         if (flags & ETH_RSS_L2_PAYLOAD)
6643                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6644
6645         return hena;
6646 }
6647
6648 /* Parse the hash enable flags */
6649 uint64_t
6650 i40e_parse_hena(uint64_t flags)
6651 {
6652         uint64_t rss_hf = 0;
6653
6654         if (!flags)
6655                 return rss_hf;
6656         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6657                 rss_hf |= ETH_RSS_FRAG_IPV4;
6658         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6659                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6660         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6661                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6662         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6663                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6664         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6665                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6666         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6667                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6668         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6669                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6670         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6671                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6672         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6673                 rss_hf |= ETH_RSS_FRAG_IPV6;
6674         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6675                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6676         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6677                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6678         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6679                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6680         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6681                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6682         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6683                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6684         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6685                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6686         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6687                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6688         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6689                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6690
6691         return rss_hf;
6692 }
6693
6694 /* Disable RSS */
6695 static void
6696 i40e_pf_disable_rss(struct i40e_pf *pf)
6697 {
6698         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6699         uint64_t hena;
6700
6701         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6702         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6703         if (hw->mac.type == I40E_MAC_X722)
6704                 hena &= ~I40E_RSS_HENA_ALL_X722;
6705         else
6706                 hena &= ~I40E_RSS_HENA_ALL;
6707         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6708         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6709         I40E_WRITE_FLUSH(hw);
6710 }
6711
6712 static int
6713 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6714 {
6715         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6716         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6717         int ret = 0;
6718
6719         if (!key || key_len == 0) {
6720                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6721                 return 0;
6722         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6723                 sizeof(uint32_t)) {
6724                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6725                 return -EINVAL;
6726         }
6727
6728         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6729                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6730                         (struct i40e_aqc_get_set_rss_key_data *)key;
6731
6732                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6733                 if (ret)
6734                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6735         } else {
6736                 uint32_t *hash_key = (uint32_t *)key;
6737                 uint16_t i;
6738
6739                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6740                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6741                 I40E_WRITE_FLUSH(hw);
6742         }
6743
6744         return ret;
6745 }
6746
6747 static int
6748 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6749 {
6750         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6751         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6752         int ret;
6753
6754         if (!key || !key_len)
6755                 return -EINVAL;
6756
6757         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6758                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6759                         (struct i40e_aqc_get_set_rss_key_data *)key);
6760                 if (ret) {
6761                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6762                         return ret;
6763                 }
6764         } else {
6765                 uint32_t *key_dw = (uint32_t *)key;
6766                 uint16_t i;
6767
6768                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6769                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6770         }
6771         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6772
6773         return 0;
6774 }
6775
6776 static int
6777 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6778 {
6779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6780         uint64_t rss_hf;
6781         uint64_t hena;
6782         int ret;
6783
6784         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6785                                rss_conf->rss_key_len);
6786         if (ret)
6787                 return ret;
6788
6789         rss_hf = rss_conf->rss_hf;
6790         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6791         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6792         if (hw->mac.type == I40E_MAC_X722)
6793                 hena &= ~I40E_RSS_HENA_ALL_X722;
6794         else
6795                 hena &= ~I40E_RSS_HENA_ALL;
6796         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6797         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6798         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6799         I40E_WRITE_FLUSH(hw);
6800
6801         return 0;
6802 }
6803
6804 static int
6805 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6806                          struct rte_eth_rss_conf *rss_conf)
6807 {
6808         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6810         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6811         uint64_t hena;
6812
6813         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6814         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6815         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6816                  ? I40E_RSS_HENA_ALL_X722
6817                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6818                 if (rss_hf != 0) /* Enable RSS */
6819                         return -EINVAL;
6820                 return 0; /* Nothing to do */
6821         }
6822         /* RSS enabled */
6823         if (rss_hf == 0) /* Disable RSS */
6824                 return -EINVAL;
6825
6826         return i40e_hw_rss_hash_set(pf, rss_conf);
6827 }
6828
6829 static int
6830 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6831                            struct rte_eth_rss_conf *rss_conf)
6832 {
6833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6834         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6835         uint64_t hena;
6836
6837         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6838                          &rss_conf->rss_key_len);
6839
6840         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6841         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6842         rss_conf->rss_hf = i40e_parse_hena(hena);
6843
6844         return 0;
6845 }
6846
6847 static int
6848 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6849 {
6850         switch (filter_type) {
6851         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6852                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6853                 break;
6854         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6855                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6856                 break;
6857         case RTE_TUNNEL_FILTER_IMAC_TENID:
6858                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6859                 break;
6860         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6861                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6862                 break;
6863         case ETH_TUNNEL_FILTER_IMAC:
6864                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6865                 break;
6866         case ETH_TUNNEL_FILTER_OIP:
6867                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6868                 break;
6869         case ETH_TUNNEL_FILTER_IIP:
6870                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6871                 break;
6872         default:
6873                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6874                 return -EINVAL;
6875         }
6876
6877         return 0;
6878 }
6879
6880 /* Convert tunnel filter structure */
6881 static int
6882 i40e_tunnel_filter_convert(
6883         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6884         struct i40e_tunnel_filter *tunnel_filter)
6885 {
6886         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6887                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6888         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6889                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6890         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6891         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6892              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6893             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6894                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6895         else
6896                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6897         tunnel_filter->input.flags = cld_filter->element.flags;
6898         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6899         tunnel_filter->queue = cld_filter->element.queue_number;
6900         rte_memcpy(tunnel_filter->input.general_fields,
6901                    cld_filter->general_fields,
6902                    sizeof(cld_filter->general_fields));
6903
6904         return 0;
6905 }
6906
6907 /* Check if there exists the tunnel filter */
6908 struct i40e_tunnel_filter *
6909 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6910                              const struct i40e_tunnel_filter_input *input)
6911 {
6912         int ret;
6913
6914         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6915         if (ret < 0)
6916                 return NULL;
6917
6918         return tunnel_rule->hash_map[ret];
6919 }
6920
6921 /* Add a tunnel filter into the SW list */
6922 static int
6923 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6924                              struct i40e_tunnel_filter *tunnel_filter)
6925 {
6926         struct i40e_tunnel_rule *rule = &pf->tunnel;
6927         int ret;
6928
6929         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6930         if (ret < 0) {
6931                 PMD_DRV_LOG(ERR,
6932                             "Failed to insert tunnel filter to hash table %d!",
6933                             ret);
6934                 return ret;
6935         }
6936         rule->hash_map[ret] = tunnel_filter;
6937
6938         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6939
6940         return 0;
6941 }
6942
6943 /* Delete a tunnel filter from the SW list */
6944 int
6945 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6946                           struct i40e_tunnel_filter_input *input)
6947 {
6948         struct i40e_tunnel_rule *rule = &pf->tunnel;
6949         struct i40e_tunnel_filter *tunnel_filter;
6950         int ret;
6951
6952         ret = rte_hash_del_key(rule->hash_table, input);
6953         if (ret < 0) {
6954                 PMD_DRV_LOG(ERR,
6955                             "Failed to delete tunnel filter to hash table %d!",
6956                             ret);
6957                 return ret;
6958         }
6959         tunnel_filter = rule->hash_map[ret];
6960         rule->hash_map[ret] = NULL;
6961
6962         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6963         rte_free(tunnel_filter);
6964
6965         return 0;
6966 }
6967
6968 int
6969 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6970                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6971                         uint8_t add)
6972 {
6973         uint16_t ip_type;
6974         uint32_t ipv4_addr;
6975         uint8_t i, tun_type = 0;
6976         /* internal varialbe to convert ipv6 byte order */
6977         uint32_t convert_ipv6[4];
6978         int val, ret = 0;
6979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6980         struct i40e_vsi *vsi = pf->main_vsi;
6981         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6982         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6983         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6984         struct i40e_tunnel_filter *tunnel, *node;
6985         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6986
6987         cld_filter = rte_zmalloc("tunnel_filter",
6988                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6989         0);
6990
6991         if (NULL == cld_filter) {
6992                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6993                 return -ENOMEM;
6994         }
6995         pfilter = cld_filter;
6996
6997         ether_addr_copy(&tunnel_filter->outer_mac,
6998                         (struct ether_addr *)&pfilter->element.outer_mac);
6999         ether_addr_copy(&tunnel_filter->inner_mac,
7000                         (struct ether_addr *)&pfilter->element.inner_mac);
7001
7002         pfilter->element.inner_vlan =
7003                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7004         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7005                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7006                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7007                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7008                                 &rte_cpu_to_le_32(ipv4_addr),
7009                                 sizeof(pfilter->element.ipaddr.v4.data));
7010         } else {
7011                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7012                 for (i = 0; i < 4; i++) {
7013                         convert_ipv6[i] =
7014                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7015                 }
7016                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7017                            &convert_ipv6,
7018                            sizeof(pfilter->element.ipaddr.v6.data));
7019         }
7020
7021         /* check tunneled type */
7022         switch (tunnel_filter->tunnel_type) {
7023         case RTE_TUNNEL_TYPE_VXLAN:
7024                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7025                 break;
7026         case RTE_TUNNEL_TYPE_NVGRE:
7027                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7028                 break;
7029         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7030                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7031                 break;
7032         default:
7033                 /* Other tunnel types is not supported. */
7034                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7035                 rte_free(cld_filter);
7036                 return -EINVAL;
7037         }
7038
7039         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7040                                        &pfilter->element.flags);
7041         if (val < 0) {
7042                 rte_free(cld_filter);
7043                 return -EINVAL;
7044         }
7045
7046         pfilter->element.flags |= rte_cpu_to_le_16(
7047                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7048                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7049         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7050         pfilter->element.queue_number =
7051                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7052
7053         /* Check if there is the filter in SW list */
7054         memset(&check_filter, 0, sizeof(check_filter));
7055         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7056         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7057         if (add && node) {
7058                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7059                 return -EINVAL;
7060         }
7061
7062         if (!add && !node) {
7063                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7064                 return -EINVAL;
7065         }
7066
7067         if (add) {
7068                 ret = i40e_aq_add_cloud_filters(hw,
7069                                         vsi->seid, &cld_filter->element, 1);
7070                 if (ret < 0) {
7071                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7072                         return -ENOTSUP;
7073                 }
7074                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7075                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7076                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7077         } else {
7078                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7079                                                    &cld_filter->element, 1);
7080                 if (ret < 0) {
7081                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7082                         return -ENOTSUP;
7083                 }
7084                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7085         }
7086
7087         rte_free(cld_filter);
7088         return ret;
7089 }
7090
7091 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7092 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7093 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7094 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7095 #define I40E_TR_GRE_KEY_MASK                    0x400
7096 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7097 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7098
7099 static enum
7100 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7101 {
7102         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7103         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7104         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7105         enum i40e_status_code status = I40E_SUCCESS;
7106
7107         memset(&filter_replace, 0,
7108                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7109         memset(&filter_replace_buf, 0,
7110                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7111
7112         /* create L1 filter */
7113         filter_replace.old_filter_type =
7114                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7115         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7116         filter_replace.tr_bit = 0;
7117
7118         /* Prepare the buffer, 3 entries */
7119         filter_replace_buf.data[0] =
7120                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7121         filter_replace_buf.data[0] |=
7122                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7123         filter_replace_buf.data[2] = 0xFF;
7124         filter_replace_buf.data[3] = 0xFF;
7125         filter_replace_buf.data[4] =
7126                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7127         filter_replace_buf.data[4] |=
7128                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7129         filter_replace_buf.data[7] = 0xF0;
7130         filter_replace_buf.data[8]
7131                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7132         filter_replace_buf.data[8] |=
7133                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7134         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7135                 I40E_TR_GENEVE_KEY_MASK |
7136                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7137         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7138                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7139                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7140
7141         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7142                                                &filter_replace_buf);
7143         return status;
7144 }
7145
7146 static enum
7147 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7148 {
7149         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7150         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7151         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7152         enum i40e_status_code status = I40E_SUCCESS;
7153
7154         /* For MPLSoUDP */
7155         memset(&filter_replace, 0,
7156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7157         memset(&filter_replace_buf, 0,
7158                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7159         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7160                 I40E_AQC_MIRROR_CLOUD_FILTER;
7161         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7162         filter_replace.new_filter_type =
7163                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7164         /* Prepare the buffer, 2 entries */
7165         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7166         filter_replace_buf.data[0] |=
7167                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7168         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7169         filter_replace_buf.data[4] |=
7170                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7171         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7172                                                &filter_replace_buf);
7173         if (status < 0)
7174                 return status;
7175
7176         /* For MPLSoGRE */
7177         memset(&filter_replace, 0,
7178                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7179         memset(&filter_replace_buf, 0,
7180                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7181
7182         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7183                 I40E_AQC_MIRROR_CLOUD_FILTER;
7184         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7185         filter_replace.new_filter_type =
7186                 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7187         /* Prepare the buffer, 2 entries */
7188         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7189         filter_replace_buf.data[0] |=
7190                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7191         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7192         filter_replace_buf.data[4] |=
7193                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7194
7195         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7196                                                &filter_replace_buf);
7197         return status;
7198 }
7199
7200 int
7201 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7202                       struct i40e_tunnel_filter_conf *tunnel_filter,
7203                       uint8_t add)
7204 {
7205         uint16_t ip_type;
7206         uint32_t ipv4_addr;
7207         uint8_t i, tun_type = 0;
7208         /* internal variable to convert ipv6 byte order */
7209         uint32_t convert_ipv6[4];
7210         int val, ret = 0;
7211         struct i40e_pf_vf *vf = NULL;
7212         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7213         struct i40e_vsi *vsi;
7214         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7215         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7216         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7217         struct i40e_tunnel_filter *tunnel, *node;
7218         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7219         uint32_t teid_le;
7220         bool big_buffer = 0;
7221
7222         cld_filter = rte_zmalloc("tunnel_filter",
7223                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7224                          0);
7225
7226         if (cld_filter == NULL) {
7227                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7228                 return -ENOMEM;
7229         }
7230         pfilter = cld_filter;
7231
7232         ether_addr_copy(&tunnel_filter->outer_mac,
7233                         (struct ether_addr *)&pfilter->element.outer_mac);
7234         ether_addr_copy(&tunnel_filter->inner_mac,
7235                         (struct ether_addr *)&pfilter->element.inner_mac);
7236
7237         pfilter->element.inner_vlan =
7238                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7239         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7240                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7241                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7242                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7243                                 &rte_cpu_to_le_32(ipv4_addr),
7244                                 sizeof(pfilter->element.ipaddr.v4.data));
7245         } else {
7246                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7247                 for (i = 0; i < 4; i++) {
7248                         convert_ipv6[i] =
7249                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7250                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7251                 }
7252                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7253                            &convert_ipv6,
7254                            sizeof(pfilter->element.ipaddr.v6.data));
7255         }
7256
7257         /* check tunneled type */
7258         switch (tunnel_filter->tunnel_type) {
7259         case I40E_TUNNEL_TYPE_VXLAN:
7260                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7261                 break;
7262         case I40E_TUNNEL_TYPE_NVGRE:
7263                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7264                 break;
7265         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7266                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7267                 break;
7268         case I40E_TUNNEL_TYPE_MPLSoUDP:
7269                 if (!pf->mpls_replace_flag) {
7270                         i40e_replace_mpls_l1_filter(pf);
7271                         i40e_replace_mpls_cloud_filter(pf);
7272                         pf->mpls_replace_flag = 1;
7273                 }
7274                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7275                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7276                         teid_le >> 4;
7277                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7278                         (teid_le & 0xF) << 12;
7279                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7280                         0x40;
7281                 big_buffer = 1;
7282                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7283                 break;
7284         case I40E_TUNNEL_TYPE_MPLSoGRE:
7285                 if (!pf->mpls_replace_flag) {
7286                         i40e_replace_mpls_l1_filter(pf);
7287                         i40e_replace_mpls_cloud_filter(pf);
7288                         pf->mpls_replace_flag = 1;
7289                 }
7290                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7291                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7292                         teid_le >> 4;
7293                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7294                         (teid_le & 0xF) << 12;
7295                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7296                         0x0;
7297                 big_buffer = 1;
7298                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7299                 break;
7300         case I40E_TUNNEL_TYPE_QINQ:
7301                 if (!pf->qinq_replace_flag) {
7302                         ret = i40e_cloud_filter_qinq_create(pf);
7303                         if (ret < 0)
7304                                 PMD_DRV_LOG(DEBUG,
7305                                             "QinQ tunnel filter already created.");
7306                         pf->qinq_replace_flag = 1;
7307                 }
7308                 /*      Add in the General fields the values of
7309                  *      the Outer and Inner VLAN
7310                  *      Big Buffer should be set, see changes in
7311                  *      i40e_aq_add_cloud_filters
7312                  */
7313                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7314                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7315                 big_buffer = 1;
7316                 break;
7317         default:
7318                 /* Other tunnel types is not supported. */
7319                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7320                 rte_free(cld_filter);
7321                 return -EINVAL;
7322         }
7323
7324         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7325                 pfilter->element.flags =
7326                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7327         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7328                 pfilter->element.flags =
7329                         I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7330         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7331                 pfilter->element.flags |=
7332                         I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7333         else {
7334                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7335                                                 &pfilter->element.flags);
7336                 if (val < 0) {
7337                         rte_free(cld_filter);
7338                         return -EINVAL;
7339                 }
7340         }
7341
7342         pfilter->element.flags |= rte_cpu_to_le_16(
7343                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7344                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7345         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7346         pfilter->element.queue_number =
7347                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7348
7349         if (!tunnel_filter->is_to_vf)
7350                 vsi = pf->main_vsi;
7351         else {
7352                 if (tunnel_filter->vf_id >= pf->vf_num) {
7353                         PMD_DRV_LOG(ERR, "Invalid argument.");
7354                         return -EINVAL;
7355                 }
7356                 vf = &pf->vfs[tunnel_filter->vf_id];
7357                 vsi = vf->vsi;
7358         }
7359
7360         /* Check if there is the filter in SW list */
7361         memset(&check_filter, 0, sizeof(check_filter));
7362         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7363         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7364         check_filter.vf_id = tunnel_filter->vf_id;
7365         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7366         if (add && node) {
7367                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7368                 return -EINVAL;
7369         }
7370
7371         if (!add && !node) {
7372                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7373                 return -EINVAL;
7374         }
7375
7376         if (add) {
7377                 if (big_buffer)
7378                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7379                                                    vsi->seid, cld_filter, 1);
7380                 else
7381                         ret = i40e_aq_add_cloud_filters(hw,
7382                                         vsi->seid, &cld_filter->element, 1);
7383                 if (ret < 0) {
7384                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7385                         return -ENOTSUP;
7386                 }
7387                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7388                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7389                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7390         } else {
7391                 if (big_buffer)
7392                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7393                                 hw, vsi->seid, cld_filter, 1);
7394                 else
7395                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7396                                                    &cld_filter->element, 1);
7397                 if (ret < 0) {
7398                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7399                         return -ENOTSUP;
7400                 }
7401                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7402         }
7403
7404         rte_free(cld_filter);
7405         return ret;
7406 }
7407
7408 static int
7409 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7410 {
7411         uint8_t i;
7412
7413         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7414                 if (pf->vxlan_ports[i] == port)
7415                         return i;
7416         }
7417
7418         return -1;
7419 }
7420
7421 static int
7422 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7423 {
7424         int  idx, ret;
7425         uint8_t filter_idx;
7426         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7427
7428         idx = i40e_get_vxlan_port_idx(pf, port);
7429
7430         /* Check if port already exists */
7431         if (idx >= 0) {
7432                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7433                 return -EINVAL;
7434         }
7435
7436         /* Now check if there is space to add the new port */
7437         idx = i40e_get_vxlan_port_idx(pf, 0);
7438         if (idx < 0) {
7439                 PMD_DRV_LOG(ERR,
7440                         "Maximum number of UDP ports reached, not adding port %d",
7441                         port);
7442                 return -ENOSPC;
7443         }
7444
7445         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7446                                         &filter_idx, NULL);
7447         if (ret < 0) {
7448                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7449                 return -1;
7450         }
7451
7452         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7453                          port,  filter_idx);
7454
7455         /* New port: add it and mark its index in the bitmap */
7456         pf->vxlan_ports[idx] = port;
7457         pf->vxlan_bitmap |= (1 << idx);
7458
7459         if (!(pf->flags & I40E_FLAG_VXLAN))
7460                 pf->flags |= I40E_FLAG_VXLAN;
7461
7462         return 0;
7463 }
7464
7465 static int
7466 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7467 {
7468         int idx;
7469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7470
7471         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7472                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7473                 return -EINVAL;
7474         }
7475
7476         idx = i40e_get_vxlan_port_idx(pf, port);
7477
7478         if (idx < 0) {
7479                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7480                 return -EINVAL;
7481         }
7482
7483         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7484                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7485                 return -1;
7486         }
7487
7488         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7489                         port, idx);
7490
7491         pf->vxlan_ports[idx] = 0;
7492         pf->vxlan_bitmap &= ~(1 << idx);
7493
7494         if (!pf->vxlan_bitmap)
7495                 pf->flags &= ~I40E_FLAG_VXLAN;
7496
7497         return 0;
7498 }
7499
7500 /* Add UDP tunneling port */
7501 static int
7502 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7503                              struct rte_eth_udp_tunnel *udp_tunnel)
7504 {
7505         int ret = 0;
7506         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7507
7508         if (udp_tunnel == NULL)
7509                 return -EINVAL;
7510
7511         switch (udp_tunnel->prot_type) {
7512         case RTE_TUNNEL_TYPE_VXLAN:
7513                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7514                 break;
7515
7516         case RTE_TUNNEL_TYPE_GENEVE:
7517         case RTE_TUNNEL_TYPE_TEREDO:
7518                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7519                 ret = -1;
7520                 break;
7521
7522         default:
7523                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7524                 ret = -1;
7525                 break;
7526         }
7527
7528         return ret;
7529 }
7530
7531 /* Remove UDP tunneling port */
7532 static int
7533 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7534                              struct rte_eth_udp_tunnel *udp_tunnel)
7535 {
7536         int ret = 0;
7537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7538
7539         if (udp_tunnel == NULL)
7540                 return -EINVAL;
7541
7542         switch (udp_tunnel->prot_type) {
7543         case RTE_TUNNEL_TYPE_VXLAN:
7544                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7545                 break;
7546         case RTE_TUNNEL_TYPE_GENEVE:
7547         case RTE_TUNNEL_TYPE_TEREDO:
7548                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7549                 ret = -1;
7550                 break;
7551         default:
7552                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7553                 ret = -1;
7554                 break;
7555         }
7556
7557         return ret;
7558 }
7559
7560 /* Calculate the maximum number of contiguous PF queues that are configured */
7561 static int
7562 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7563 {
7564         struct rte_eth_dev_data *data = pf->dev_data;
7565         int i, num;
7566         struct i40e_rx_queue *rxq;
7567
7568         num = 0;
7569         for (i = 0; i < pf->lan_nb_qps; i++) {
7570                 rxq = data->rx_queues[i];
7571                 if (rxq && rxq->q_set)
7572                         num++;
7573                 else
7574                         break;
7575         }
7576
7577         return num;
7578 }
7579
7580 /* Configure RSS */
7581 static int
7582 i40e_pf_config_rss(struct i40e_pf *pf)
7583 {
7584         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7585         struct rte_eth_rss_conf rss_conf;
7586         uint32_t i, lut = 0;
7587         uint16_t j, num;
7588
7589         /*
7590          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7591          * It's necessary to calculate the actual PF queues that are configured.
7592          */
7593         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7594                 num = i40e_pf_calc_configured_queues_num(pf);
7595         else
7596                 num = pf->dev_data->nb_rx_queues;
7597
7598         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7599         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7600                         num);
7601
7602         if (num == 0) {
7603                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7604                 return -ENOTSUP;
7605         }
7606
7607         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7608                 if (j == num)
7609                         j = 0;
7610                 lut = (lut << 8) | (j & ((0x1 <<
7611                         hw->func_caps.rss_table_entry_width) - 1));
7612                 if ((i & 3) == 3)
7613                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7614         }
7615
7616         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7617         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7618                 i40e_pf_disable_rss(pf);
7619                 return 0;
7620         }
7621         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7622                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7623                 /* Random default keys */
7624                 static uint32_t rss_key_default[] = {0x6b793944,
7625                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7626                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7627                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7628
7629                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7630                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7631                                                         sizeof(uint32_t);
7632         }
7633
7634         return i40e_hw_rss_hash_set(pf, &rss_conf);
7635 }
7636
7637 static int
7638 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7639                                struct rte_eth_tunnel_filter_conf *filter)
7640 {
7641         if (pf == NULL || filter == NULL) {
7642                 PMD_DRV_LOG(ERR, "Invalid parameter");
7643                 return -EINVAL;
7644         }
7645
7646         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7647                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7648                 return -EINVAL;
7649         }
7650
7651         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7652                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7653                 return -EINVAL;
7654         }
7655
7656         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7657                 (is_zero_ether_addr(&filter->outer_mac))) {
7658                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7659                 return -EINVAL;
7660         }
7661
7662         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7663                 (is_zero_ether_addr(&filter->inner_mac))) {
7664                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7665                 return -EINVAL;
7666         }
7667
7668         return 0;
7669 }
7670
7671 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7672 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7673 static int
7674 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7675 {
7676         uint32_t val, reg;
7677         int ret = -EINVAL;
7678
7679         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7680         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7681
7682         if (len == 3) {
7683                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7684         } else if (len == 4) {
7685                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7686         } else {
7687                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7688                 return ret;
7689         }
7690
7691         if (reg != val) {
7692                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7693                                                    reg, NULL);
7694                 if (ret != 0)
7695                         return ret;
7696         } else {
7697                 ret = 0;
7698         }
7699         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7700                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7701
7702         return ret;
7703 }
7704
7705 static int
7706 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7707 {
7708         int ret = -EINVAL;
7709
7710         if (!hw || !cfg)
7711                 return -EINVAL;
7712
7713         switch (cfg->cfg_type) {
7714         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7715                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7716                 break;
7717         default:
7718                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7719                 break;
7720         }
7721
7722         return ret;
7723 }
7724
7725 static int
7726 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7727                                enum rte_filter_op filter_op,
7728                                void *arg)
7729 {
7730         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7731         int ret = I40E_ERR_PARAM;
7732
7733         switch (filter_op) {
7734         case RTE_ETH_FILTER_SET:
7735                 ret = i40e_dev_global_config_set(hw,
7736                         (struct rte_eth_global_cfg *)arg);
7737                 break;
7738         default:
7739                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7740                 break;
7741         }
7742
7743         return ret;
7744 }
7745
7746 static int
7747 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7748                           enum rte_filter_op filter_op,
7749                           void *arg)
7750 {
7751         struct rte_eth_tunnel_filter_conf *filter;
7752         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7753         int ret = I40E_SUCCESS;
7754
7755         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7756
7757         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7758                 return I40E_ERR_PARAM;
7759
7760         switch (filter_op) {
7761         case RTE_ETH_FILTER_NOP:
7762                 if (!(pf->flags & I40E_FLAG_VXLAN))
7763                         ret = I40E_NOT_SUPPORTED;
7764                 break;
7765         case RTE_ETH_FILTER_ADD:
7766                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7767                 break;
7768         case RTE_ETH_FILTER_DELETE:
7769                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7770                 break;
7771         default:
7772                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7773                 ret = I40E_ERR_PARAM;
7774                 break;
7775         }
7776
7777         return ret;
7778 }
7779
7780 static int
7781 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7782 {
7783         int ret = 0;
7784         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7785
7786         /* RSS setup */
7787         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7788                 ret = i40e_pf_config_rss(pf);
7789         else
7790                 i40e_pf_disable_rss(pf);
7791
7792         return ret;
7793 }
7794
7795 /* Get the symmetric hash enable configurations per port */
7796 static void
7797 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7798 {
7799         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7800
7801         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7802 }
7803
7804 /* Set the symmetric hash enable configurations per port */
7805 static void
7806 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7807 {
7808         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7809
7810         if (enable > 0) {
7811                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7812                         PMD_DRV_LOG(INFO,
7813                                 "Symmetric hash has already been enabled");
7814                         return;
7815                 }
7816                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7817         } else {
7818                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7819                         PMD_DRV_LOG(INFO,
7820                                 "Symmetric hash has already been disabled");
7821                         return;
7822                 }
7823                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7824         }
7825         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7826         I40E_WRITE_FLUSH(hw);
7827 }
7828
7829 /*
7830  * Get global configurations of hash function type and symmetric hash enable
7831  * per flow type (pctype). Note that global configuration means it affects all
7832  * the ports on the same NIC.
7833  */
7834 static int
7835 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7836                                    struct rte_eth_hash_global_conf *g_cfg)
7837 {
7838         uint32_t reg, mask = I40E_FLOW_TYPES;
7839         uint16_t i;
7840         enum i40e_filter_pctype pctype;
7841
7842         memset(g_cfg, 0, sizeof(*g_cfg));
7843         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7844         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7845                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7846         else
7847                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7848         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7849                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7850
7851         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7852                 if (!(mask & (1UL << i)))
7853                         continue;
7854                 mask &= ~(1UL << i);
7855                 /* Bit set indicats the coresponding flow type is supported */
7856                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7857                 /* if flowtype is invalid, continue */
7858                 if (!I40E_VALID_FLOW(i))
7859                         continue;
7860                 pctype = i40e_flowtype_to_pctype(i);
7861                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7862                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7863                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7864         }
7865
7866         return 0;
7867 }
7868
7869 static int
7870 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7871 {
7872         uint32_t i;
7873         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7874
7875         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7876                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7877                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7878                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7879                                                 g_cfg->hash_func);
7880                 return -EINVAL;
7881         }
7882
7883         /*
7884          * As i40e supports less than 32 flow types, only first 32 bits need to
7885          * be checked.
7886          */
7887         mask0 = g_cfg->valid_bit_mask[0];
7888         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7889                 if (i == 0) {
7890                         /* Check if any unsupported flow type configured */
7891                         if ((mask0 | i40e_mask) ^ i40e_mask)
7892                                 goto mask_err;
7893                 } else {
7894                         if (g_cfg->valid_bit_mask[i])
7895                                 goto mask_err;
7896                 }
7897         }
7898
7899         return 0;
7900
7901 mask_err:
7902         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7903
7904         return -EINVAL;
7905 }
7906
7907 /*
7908  * Set global configurations of hash function type and symmetric hash enable
7909  * per flow type (pctype). Note any modifying global configuration will affect
7910  * all the ports on the same NIC.
7911  */
7912 static int
7913 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7914                                    struct rte_eth_hash_global_conf *g_cfg)
7915 {
7916         int ret;
7917         uint16_t i;
7918         uint32_t reg;
7919         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7920         enum i40e_filter_pctype pctype;
7921
7922         /* Check the input parameters */
7923         ret = i40e_hash_global_config_check(g_cfg);
7924         if (ret < 0)
7925                 return ret;
7926
7927         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7928                 if (!(mask0 & (1UL << i)))
7929                         continue;
7930                 mask0 &= ~(1UL << i);
7931                 /* if flowtype is invalid, continue */
7932                 if (!I40E_VALID_FLOW(i))
7933                         continue;
7934                 pctype = i40e_flowtype_to_pctype(i);
7935                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7936                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7937                 if (hw->mac.type == I40E_MAC_X722) {
7938                         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7939                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7940                                   I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7941                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7942                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7943                                   reg);
7944                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7945                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7946                                   reg);
7947                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7948                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7949                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7950                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7951                                   I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7952                                   reg);
7953                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7954                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7955                                   I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7956                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7957                                   I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7958                                   reg);
7959                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7960                                   I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7961                                   reg);
7962                         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7963                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7964                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7965                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7966                                   I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7967                                   reg);
7968                         } else {
7969                                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7970                                   reg);
7971                         }
7972                 } else {
7973                         i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7974                 }
7975         }
7976
7977         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7978         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7979                 /* Toeplitz */
7980                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7981                         PMD_DRV_LOG(DEBUG,
7982                                 "Hash function already set to Toeplitz");
7983                         goto out;
7984                 }
7985                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7986         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7987                 /* Simple XOR */
7988                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7989                         PMD_DRV_LOG(DEBUG,
7990                                 "Hash function already set to Simple XOR");
7991                         goto out;
7992                 }
7993                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7994         } else
7995                 /* Use the default, and keep it as it is */
7996                 goto out;
7997
7998         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7999
8000 out:
8001         I40E_WRITE_FLUSH(hw);
8002
8003         return 0;
8004 }
8005
8006 /**
8007  * Valid input sets for hash and flow director filters per PCTYPE
8008  */
8009 static uint64_t
8010 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8011                 enum rte_filter_type filter)
8012 {
8013         uint64_t valid;
8014
8015         static const uint64_t valid_hash_inset_table[] = {
8016                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8017                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8018                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8019                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8020                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8021                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8022                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8023                         I40E_INSET_FLEX_PAYLOAD,
8024                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8025                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8026                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8028                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8029                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8030                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8031                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8032                         I40E_INSET_FLEX_PAYLOAD,
8033                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8034                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8035                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8036                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8037                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8038                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8039                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8040                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8041                         I40E_INSET_FLEX_PAYLOAD,
8042                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8046                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8047                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8048                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8049                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8050                         I40E_INSET_FLEX_PAYLOAD,
8051                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8052                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8053                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8054                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8055                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8056                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8057                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8058                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8059                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8060                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8061                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8062                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8064                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8065                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8066                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8067                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8068                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8069                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8070                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8071                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8072                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8073                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8074                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8075                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8076                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8077                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8078                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8079                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8080                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8081                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8082                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8083                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8084                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8085                         I40E_INSET_FLEX_PAYLOAD,
8086                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8087                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8088                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8089                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8090                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8091                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8092                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8093                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8094                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8095                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8096                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8097                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8098                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8099                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8100                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8101                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8102                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8103                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8104                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8105                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8106                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8107                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8108                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8109                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8110                         I40E_INSET_FLEX_PAYLOAD,
8111                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8115                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8116                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8117                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8118                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8119                         I40E_INSET_FLEX_PAYLOAD,
8120                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8121                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8122                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8123                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8124                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8125                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8126                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8127                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8128                         I40E_INSET_FLEX_PAYLOAD,
8129                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8130                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8131                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8132                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8133                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8134                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8135                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8136                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8137                         I40E_INSET_FLEX_PAYLOAD,
8138                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8139                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8140                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8141                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8142                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8143                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8144                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8145                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8146                         I40E_INSET_FLEX_PAYLOAD,
8147                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8148                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8149                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8150                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8151                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8152                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8153                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8154                         I40E_INSET_FLEX_PAYLOAD,
8155                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8156                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8157                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8158                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8159                         I40E_INSET_FLEX_PAYLOAD,
8160         };
8161
8162         /**
8163          * Flow director supports only fields defined in
8164          * union rte_eth_fdir_flow.
8165          */
8166         static const uint64_t valid_fdir_inset_table[] = {
8167                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8168                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8169                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8170                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8171                 I40E_INSET_IPV4_TTL,
8172                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8173                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8174                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8175                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8176                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8177                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8178                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8180                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8181                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8182                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8183                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8184                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8185                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8186                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8187                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8188                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8190                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8191                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8192                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8193                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8194                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8195                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8196                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8197                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8198                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8200                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8201                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8202                 I40E_INSET_SCTP_VT,
8203                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8204                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8205                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8206                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8207                 I40E_INSET_IPV4_TTL,
8208                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8209                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8210                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8211                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8212                 I40E_INSET_IPV6_HOP_LIMIT,
8213                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8214                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8216                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8217                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8218                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8219                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8220                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8221                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8222                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8223                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8224                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8225                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8226                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8227                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8228                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8229                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8230                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8231                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8232                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8233                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8234                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8235                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8236                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8237                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8238                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8239                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8240                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8241                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8242                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8243                 I40E_INSET_SCTP_VT,
8244                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8246                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8247                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8248                 I40E_INSET_IPV6_HOP_LIMIT,
8249                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251                 I40E_INSET_LAST_ETHER_TYPE,
8252         };
8253
8254         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8255                 return 0;
8256         if (filter == RTE_ETH_FILTER_HASH)
8257                 valid = valid_hash_inset_table[pctype];
8258         else
8259                 valid = valid_fdir_inset_table[pctype];
8260
8261         return valid;
8262 }
8263
8264 /**
8265  * Validate if the input set is allowed for a specific PCTYPE
8266  */
8267 int
8268 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8269                 enum rte_filter_type filter, uint64_t inset)
8270 {
8271         uint64_t valid;
8272
8273         valid = i40e_get_valid_input_set(pctype, filter);
8274         if (inset & (~valid))
8275                 return -EINVAL;
8276
8277         return 0;
8278 }
8279
8280 /* default input set fields combination per pctype */
8281 uint64_t
8282 i40e_get_default_input_set(uint16_t pctype)
8283 {
8284         static const uint64_t default_inset_table[] = {
8285                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8286                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8287                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8288                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8290                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8291                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8292                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8293                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8294                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8297                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8299                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8300                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8301                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8302                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8303                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8304                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8305                         I40E_INSET_SCTP_VT,
8306                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8307                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8308                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8309                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8310                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8311                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8312                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8313                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8314                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8316                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8317                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8318                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8319                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8320                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8323                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8324                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8325                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8326                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8327                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8328                         I40E_INSET_SCTP_VT,
8329                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8330                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8331                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8332                         I40E_INSET_LAST_ETHER_TYPE,
8333         };
8334
8335         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8336                 return 0;
8337
8338         return default_inset_table[pctype];
8339 }
8340
8341 /**
8342  * Parse the input set from index to logical bit masks
8343  */
8344 static int
8345 i40e_parse_input_set(uint64_t *inset,
8346                      enum i40e_filter_pctype pctype,
8347                      enum rte_eth_input_set_field *field,
8348                      uint16_t size)
8349 {
8350         uint16_t i, j;
8351         int ret = -EINVAL;
8352
8353         static const struct {
8354                 enum rte_eth_input_set_field field;
8355                 uint64_t inset;
8356         } inset_convert_table[] = {
8357                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8358                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8359                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8360                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8361                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8362                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8363                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8364                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8365                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8366                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8367                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8368                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8369                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8370                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8371                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8372                         I40E_INSET_IPV6_NEXT_HDR},
8373                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8374                         I40E_INSET_IPV6_HOP_LIMIT},
8375                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8376                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8377                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8378                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8379                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8380                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8381                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8382                         I40E_INSET_SCTP_VT},
8383                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8384                         I40E_INSET_TUNNEL_DMAC},
8385                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8386                         I40E_INSET_VLAN_TUNNEL},
8387                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8388                         I40E_INSET_TUNNEL_ID},
8389                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8390                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8391                         I40E_INSET_FLEX_PAYLOAD_W1},
8392                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8393                         I40E_INSET_FLEX_PAYLOAD_W2},
8394                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8395                         I40E_INSET_FLEX_PAYLOAD_W3},
8396                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8397                         I40E_INSET_FLEX_PAYLOAD_W4},
8398                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8399                         I40E_INSET_FLEX_PAYLOAD_W5},
8400                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8401                         I40E_INSET_FLEX_PAYLOAD_W6},
8402                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8403                         I40E_INSET_FLEX_PAYLOAD_W7},
8404                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8405                         I40E_INSET_FLEX_PAYLOAD_W8},
8406         };
8407
8408         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8409                 return ret;
8410
8411         /* Only one item allowed for default or all */
8412         if (size == 1) {
8413                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8414                         *inset = i40e_get_default_input_set(pctype);
8415                         return 0;
8416                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8417                         *inset = I40E_INSET_NONE;
8418                         return 0;
8419                 }
8420         }
8421
8422         for (i = 0, *inset = 0; i < size; i++) {
8423                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8424                         if (field[i] == inset_convert_table[j].field) {
8425                                 *inset |= inset_convert_table[j].inset;
8426                                 break;
8427                         }
8428                 }
8429
8430                 /* It contains unsupported input set, return immediately */
8431                 if (j == RTE_DIM(inset_convert_table))
8432                         return ret;
8433         }
8434
8435         return 0;
8436 }
8437
8438 /**
8439  * Translate the input set from bit masks to register aware bit masks
8440  * and vice versa
8441  */
8442 uint64_t
8443 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8444 {
8445         uint64_t val = 0;
8446         uint16_t i;
8447
8448         struct inset_map {
8449                 uint64_t inset;
8450                 uint64_t inset_reg;
8451         };
8452
8453         static const struct inset_map inset_map_common[] = {
8454                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8455                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8456                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8457                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8458                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8459                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8460                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8461                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8462                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8463                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8464                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8465                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8466                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8467                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8468                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8469                 {I40E_INSET_TUNNEL_DMAC,
8470                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8471                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8472                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8473                 {I40E_INSET_TUNNEL_SRC_PORT,
8474                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8475                 {I40E_INSET_TUNNEL_DST_PORT,
8476                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8477                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8478                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8479                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8480                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8481                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8482                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8483                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8484                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8485                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8486         };
8487
8488     /* some different registers map in x722*/
8489         static const struct inset_map inset_map_diff_x722[] = {
8490                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8491                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8492                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8493                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8494         };
8495
8496         static const struct inset_map inset_map_diff_not_x722[] = {
8497                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8498                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8499                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8500                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8501         };
8502
8503         if (input == 0)
8504                 return val;
8505
8506         /* Translate input set to register aware inset */
8507         if (type == I40E_MAC_X722) {
8508                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8509                         if (input & inset_map_diff_x722[i].inset)
8510                                 val |= inset_map_diff_x722[i].inset_reg;
8511                 }
8512         } else {
8513                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8514                         if (input & inset_map_diff_not_x722[i].inset)
8515                                 val |= inset_map_diff_not_x722[i].inset_reg;
8516                 }
8517         }
8518
8519         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8520                 if (input & inset_map_common[i].inset)
8521                         val |= inset_map_common[i].inset_reg;
8522         }
8523
8524         return val;
8525 }
8526
8527 int
8528 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8529 {
8530         uint8_t i, idx = 0;
8531         uint64_t inset_need_mask = inset;
8532
8533         static const struct {
8534                 uint64_t inset;
8535                 uint32_t mask;
8536         } inset_mask_map[] = {
8537                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8538                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8539                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8540                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8541                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8542                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8543                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8544                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8545         };
8546
8547         if (!inset || !mask || !nb_elem)
8548                 return 0;
8549
8550         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8551                 /* Clear the inset bit, if no MASK is required,
8552                  * for example proto + ttl
8553                  */
8554                 if ((inset & inset_mask_map[i].inset) ==
8555                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8556                         inset_need_mask &= ~inset_mask_map[i].inset;
8557                 if (!inset_need_mask)
8558                         return 0;
8559         }
8560         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8561                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8562                     inset_mask_map[i].inset) {
8563                         if (idx >= nb_elem) {
8564                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8565                                 return -EINVAL;
8566                         }
8567                         mask[idx] = inset_mask_map[i].mask;
8568                         idx++;
8569                 }
8570         }
8571
8572         return idx;
8573 }
8574
8575 void
8576 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8577 {
8578         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8579
8580         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8581         if (reg != val)
8582                 i40e_write_rx_ctl(hw, addr, val);
8583         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8584                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8585 }
8586
8587 static void
8588 i40e_filter_input_set_init(struct i40e_pf *pf)
8589 {
8590         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8591         enum i40e_filter_pctype pctype;
8592         uint64_t input_set, inset_reg;
8593         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8594         int num, i;
8595
8596         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8597              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8598                 if (hw->mac.type == I40E_MAC_X722) {
8599                         if (!I40E_VALID_PCTYPE_X722(pctype))
8600                                 continue;
8601                 } else {
8602                         if (!I40E_VALID_PCTYPE(pctype))
8603                                 continue;
8604                 }
8605
8606                 input_set = i40e_get_default_input_set(pctype);
8607
8608                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8609                                                    I40E_INSET_MASK_NUM_REG);
8610                 if (num < 0)
8611                         return;
8612                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8613                                         input_set);
8614
8615                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8616                                       (uint32_t)(inset_reg & UINT32_MAX));
8617                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8618                                      (uint32_t)((inset_reg >>
8619                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8620                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8621                                       (uint32_t)(inset_reg & UINT32_MAX));
8622                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8623                                      (uint32_t)((inset_reg >>
8624                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8625
8626                 for (i = 0; i < num; i++) {
8627                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8628                                              mask_reg[i]);
8629                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8630                                              mask_reg[i]);
8631                 }
8632                 /*clear unused mask registers of the pctype */
8633                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8634                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8635                                              0);
8636                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8637                                              0);
8638                 }
8639                 I40E_WRITE_FLUSH(hw);
8640
8641                 /* store the default input set */
8642                 pf->hash_input_set[pctype] = input_set;
8643                 pf->fdir.input_set[pctype] = input_set;
8644         }
8645 }
8646
8647 int
8648 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8649                          struct rte_eth_input_set_conf *conf)
8650 {
8651         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8652         enum i40e_filter_pctype pctype;
8653         uint64_t input_set, inset_reg = 0;
8654         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8655         int ret, i, num;
8656
8657         if (!conf) {
8658                 PMD_DRV_LOG(ERR, "Invalid pointer");
8659                 return -EFAULT;
8660         }
8661         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8662             conf->op != RTE_ETH_INPUT_SET_ADD) {
8663                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8664                 return -EINVAL;
8665         }
8666
8667         if (!I40E_VALID_FLOW(conf->flow_type)) {
8668                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8669                 return -EINVAL;
8670         }
8671
8672         if (hw->mac.type == I40E_MAC_X722) {
8673                 /* get translated pctype value in fd pctype register */
8674                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8675                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8676                         conf->flow_type)));
8677         } else
8678                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8679
8680         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8681                                    conf->inset_size);
8682         if (ret) {
8683                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8684                 return -EINVAL;
8685         }
8686         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8687                                     input_set) != 0) {
8688                 PMD_DRV_LOG(ERR, "Invalid input set");
8689                 return -EINVAL;
8690         }
8691         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8692                 /* get inset value in register */
8693                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8694                 inset_reg <<= I40E_32_BIT_WIDTH;
8695                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8696                 input_set |= pf->hash_input_set[pctype];
8697         }
8698         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8699                                            I40E_INSET_MASK_NUM_REG);
8700         if (num < 0)
8701                 return -EINVAL;
8702
8703         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8704
8705         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8706                               (uint32_t)(inset_reg & UINT32_MAX));
8707         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8708                              (uint32_t)((inset_reg >>
8709                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8710
8711         for (i = 0; i < num; i++)
8712                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8713                                      mask_reg[i]);
8714         /*clear unused mask registers of the pctype */
8715         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8716                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8717                                      0);
8718         I40E_WRITE_FLUSH(hw);
8719
8720         pf->hash_input_set[pctype] = input_set;
8721         return 0;
8722 }
8723
8724 int
8725 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8726                          struct rte_eth_input_set_conf *conf)
8727 {
8728         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8729         enum i40e_filter_pctype pctype;
8730         uint64_t input_set, inset_reg = 0;
8731         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8732         int ret, i, num;
8733
8734         if (!hw || !conf) {
8735                 PMD_DRV_LOG(ERR, "Invalid pointer");
8736                 return -EFAULT;
8737         }
8738         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8739             conf->op != RTE_ETH_INPUT_SET_ADD) {
8740                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8741                 return -EINVAL;
8742         }
8743
8744         if (!I40E_VALID_FLOW(conf->flow_type)) {
8745                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8746                 return -EINVAL;
8747         }
8748
8749         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8750
8751         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8752                                    conf->inset_size);
8753         if (ret) {
8754                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8755                 return -EINVAL;
8756         }
8757         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8758                                     input_set) != 0) {
8759                 PMD_DRV_LOG(ERR, "Invalid input set");
8760                 return -EINVAL;
8761         }
8762
8763         /* get inset value in register */
8764         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8765         inset_reg <<= I40E_32_BIT_WIDTH;
8766         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8767
8768         /* Can not change the inset reg for flex payload for fdir,
8769          * it is done by writing I40E_PRTQF_FD_FLXINSET
8770          * in i40e_set_flex_mask_on_pctype.
8771          */
8772         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8773                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8774         else
8775                 input_set |= pf->fdir.input_set[pctype];
8776         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8777                                            I40E_INSET_MASK_NUM_REG);
8778         if (num < 0)
8779                 return -EINVAL;
8780
8781         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8782
8783         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8784                               (uint32_t)(inset_reg & UINT32_MAX));
8785         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8786                              (uint32_t)((inset_reg >>
8787                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8788
8789         for (i = 0; i < num; i++)
8790                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8791                                      mask_reg[i]);
8792         /*clear unused mask registers of the pctype */
8793         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8794                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8795                                      0);
8796         I40E_WRITE_FLUSH(hw);
8797
8798         pf->fdir.input_set[pctype] = input_set;
8799         return 0;
8800 }
8801
8802 static int
8803 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8804 {
8805         int ret = 0;
8806
8807         if (!hw || !info) {
8808                 PMD_DRV_LOG(ERR, "Invalid pointer");
8809                 return -EFAULT;
8810         }
8811
8812         switch (info->info_type) {
8813         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8814                 i40e_get_symmetric_hash_enable_per_port(hw,
8815                                         &(info->info.enable));
8816                 break;
8817         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8818                 ret = i40e_get_hash_filter_global_config(hw,
8819                                 &(info->info.global_conf));
8820                 break;
8821         default:
8822                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8823                                                         info->info_type);
8824                 ret = -EINVAL;
8825                 break;
8826         }
8827
8828         return ret;
8829 }
8830
8831 static int
8832 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8833 {
8834         int ret = 0;
8835
8836         if (!hw || !info) {
8837                 PMD_DRV_LOG(ERR, "Invalid pointer");
8838                 return -EFAULT;
8839         }
8840
8841         switch (info->info_type) {
8842         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8843                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8844                 break;
8845         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8846                 ret = i40e_set_hash_filter_global_config(hw,
8847                                 &(info->info.global_conf));
8848                 break;
8849         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8850                 ret = i40e_hash_filter_inset_select(hw,
8851                                                &(info->info.input_set_conf));
8852                 break;
8853
8854         default:
8855                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8856                                                         info->info_type);
8857                 ret = -EINVAL;
8858                 break;
8859         }
8860
8861         return ret;
8862 }
8863
8864 /* Operations for hash function */
8865 static int
8866 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8867                       enum rte_filter_op filter_op,
8868                       void *arg)
8869 {
8870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8871         int ret = 0;
8872
8873         switch (filter_op) {
8874         case RTE_ETH_FILTER_NOP:
8875                 break;
8876         case RTE_ETH_FILTER_GET:
8877                 ret = i40e_hash_filter_get(hw,
8878                         (struct rte_eth_hash_filter_info *)arg);
8879                 break;
8880         case RTE_ETH_FILTER_SET:
8881                 ret = i40e_hash_filter_set(hw,
8882                         (struct rte_eth_hash_filter_info *)arg);
8883                 break;
8884         default:
8885                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8886                                                                 filter_op);
8887                 ret = -ENOTSUP;
8888                 break;
8889         }
8890
8891         return ret;
8892 }
8893
8894 /* Convert ethertype filter structure */
8895 static int
8896 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8897                               struct i40e_ethertype_filter *filter)
8898 {
8899         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8900         filter->input.ether_type = input->ether_type;
8901         filter->flags = input->flags;
8902         filter->queue = input->queue;
8903
8904         return 0;
8905 }
8906
8907 /* Check if there exists the ehtertype filter */
8908 struct i40e_ethertype_filter *
8909 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8910                                 const struct i40e_ethertype_filter_input *input)
8911 {
8912         int ret;
8913
8914         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8915         if (ret < 0)
8916                 return NULL;
8917
8918         return ethertype_rule->hash_map[ret];
8919 }
8920
8921 /* Add ethertype filter in SW list */
8922 static int
8923 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8924                                 struct i40e_ethertype_filter *filter)
8925 {
8926         struct i40e_ethertype_rule *rule = &pf->ethertype;
8927         int ret;
8928
8929         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8930         if (ret < 0) {
8931                 PMD_DRV_LOG(ERR,
8932                             "Failed to insert ethertype filter"
8933                             " to hash table %d!",
8934                             ret);
8935                 return ret;
8936         }
8937         rule->hash_map[ret] = filter;
8938
8939         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8940
8941         return 0;
8942 }
8943
8944 /* Delete ethertype filter in SW list */
8945 int
8946 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8947                              struct i40e_ethertype_filter_input *input)
8948 {
8949         struct i40e_ethertype_rule *rule = &pf->ethertype;
8950         struct i40e_ethertype_filter *filter;
8951         int ret;
8952
8953         ret = rte_hash_del_key(rule->hash_table, input);
8954         if (ret < 0) {
8955                 PMD_DRV_LOG(ERR,
8956                             "Failed to delete ethertype filter"
8957                             " to hash table %d!",
8958                             ret);
8959                 return ret;
8960         }
8961         filter = rule->hash_map[ret];
8962         rule->hash_map[ret] = NULL;
8963
8964         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8965         rte_free(filter);
8966
8967         return 0;
8968 }
8969
8970 /*
8971  * Configure ethertype filter, which can director packet by filtering
8972  * with mac address and ether_type or only ether_type
8973  */
8974 int
8975 i40e_ethertype_filter_set(struct i40e_pf *pf,
8976                         struct rte_eth_ethertype_filter *filter,
8977                         bool add)
8978 {
8979         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8980         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8981         struct i40e_ethertype_filter *ethertype_filter, *node;
8982         struct i40e_ethertype_filter check_filter;
8983         struct i40e_control_filter_stats stats;
8984         uint16_t flags = 0;
8985         int ret;
8986
8987         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8988                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8989                 return -EINVAL;
8990         }
8991         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8992                 filter->ether_type == ETHER_TYPE_IPv6) {
8993                 PMD_DRV_LOG(ERR,
8994                         "unsupported ether_type(0x%04x) in control packet filter.",
8995                         filter->ether_type);
8996                 return -EINVAL;
8997         }
8998         if (filter->ether_type == ETHER_TYPE_VLAN)
8999                 PMD_DRV_LOG(WARNING,
9000                         "filter vlan ether_type in first tag is not supported.");
9001
9002         /* Check if there is the filter in SW list */
9003         memset(&check_filter, 0, sizeof(check_filter));
9004         i40e_ethertype_filter_convert(filter, &check_filter);
9005         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9006                                                &check_filter.input);
9007         if (add && node) {
9008                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9009                 return -EINVAL;
9010         }
9011
9012         if (!add && !node) {
9013                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9014                 return -EINVAL;
9015         }
9016
9017         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9018                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9019         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9020                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9021         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9022
9023         memset(&stats, 0, sizeof(stats));
9024         ret = i40e_aq_add_rem_control_packet_filter(hw,
9025                         filter->mac_addr.addr_bytes,
9026                         filter->ether_type, flags,
9027                         pf->main_vsi->seid,
9028                         filter->queue, add, &stats, NULL);
9029
9030         PMD_DRV_LOG(INFO,
9031                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9032                 ret, stats.mac_etype_used, stats.etype_used,
9033                 stats.mac_etype_free, stats.etype_free);
9034         if (ret < 0)
9035                 return -ENOSYS;
9036
9037         /* Add or delete a filter in SW list */
9038         if (add) {
9039                 ethertype_filter = rte_zmalloc("ethertype_filter",
9040                                        sizeof(*ethertype_filter), 0);
9041                 rte_memcpy(ethertype_filter, &check_filter,
9042                            sizeof(check_filter));
9043                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9044         } else {
9045                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9046         }
9047
9048         return ret;
9049 }
9050
9051 /*
9052  * Handle operations for ethertype filter.
9053  */
9054 static int
9055 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9056                                 enum rte_filter_op filter_op,
9057                                 void *arg)
9058 {
9059         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9060         int ret = 0;
9061
9062         if (filter_op == RTE_ETH_FILTER_NOP)
9063                 return ret;
9064
9065         if (arg == NULL) {
9066                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9067                             filter_op);
9068                 return -EINVAL;
9069         }
9070
9071         switch (filter_op) {
9072         case RTE_ETH_FILTER_ADD:
9073                 ret = i40e_ethertype_filter_set(pf,
9074                         (struct rte_eth_ethertype_filter *)arg,
9075                         TRUE);
9076                 break;
9077         case RTE_ETH_FILTER_DELETE:
9078                 ret = i40e_ethertype_filter_set(pf,
9079                         (struct rte_eth_ethertype_filter *)arg,
9080                         FALSE);
9081                 break;
9082         default:
9083                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9084                 ret = -ENOSYS;
9085                 break;
9086         }
9087         return ret;
9088 }
9089
9090 static int
9091 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9092                      enum rte_filter_type filter_type,
9093                      enum rte_filter_op filter_op,
9094                      void *arg)
9095 {
9096         int ret = 0;
9097
9098         if (dev == NULL)
9099                 return -EINVAL;
9100
9101         switch (filter_type) {
9102         case RTE_ETH_FILTER_NONE:
9103                 /* For global configuration */
9104                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9105                 break;
9106         case RTE_ETH_FILTER_HASH:
9107                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9108                 break;
9109         case RTE_ETH_FILTER_MACVLAN:
9110                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9111                 break;
9112         case RTE_ETH_FILTER_ETHERTYPE:
9113                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9114                 break;
9115         case RTE_ETH_FILTER_TUNNEL:
9116                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9117                 break;
9118         case RTE_ETH_FILTER_FDIR:
9119                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9120                 break;
9121         case RTE_ETH_FILTER_GENERIC:
9122                 if (filter_op != RTE_ETH_FILTER_GET)
9123                         return -EINVAL;
9124                 *(const void **)arg = &i40e_flow_ops;
9125                 break;
9126         default:
9127                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9128                                                         filter_type);
9129                 ret = -EINVAL;
9130                 break;
9131         }
9132
9133         return ret;
9134 }
9135
9136 /*
9137  * Check and enable Extended Tag.
9138  * Enabling Extended Tag is important for 40G performance.
9139  */
9140 static void
9141 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9142 {
9143         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9144         uint32_t buf = 0;
9145         int ret;
9146
9147         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9148                                       PCI_DEV_CAP_REG);
9149         if (ret < 0) {
9150                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9151                             PCI_DEV_CAP_REG);
9152                 return;
9153         }
9154         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9155                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9156                 return;
9157         }
9158
9159         buf = 0;
9160         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9161                                       PCI_DEV_CTRL_REG);
9162         if (ret < 0) {
9163                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9164                             PCI_DEV_CTRL_REG);
9165                 return;
9166         }
9167         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9168                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9169                 return;
9170         }
9171         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9172         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9173                                        PCI_DEV_CTRL_REG);
9174         if (ret < 0) {
9175                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9176                             PCI_DEV_CTRL_REG);
9177                 return;
9178         }
9179 }
9180
9181 /*
9182  * As some registers wouldn't be reset unless a global hardware reset,
9183  * hardware initialization is needed to put those registers into an
9184  * expected initial state.
9185  */
9186 static void
9187 i40e_hw_init(struct rte_eth_dev *dev)
9188 {
9189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9190
9191         i40e_enable_extended_tag(dev);
9192
9193         /* clear the PF Queue Filter control register */
9194         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9195
9196         /* Disable symmetric hash per port */
9197         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9198 }
9199
9200 enum i40e_filter_pctype
9201 i40e_flowtype_to_pctype(uint16_t flow_type)
9202 {
9203         static const enum i40e_filter_pctype pctype_table[] = {
9204                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9205                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9206                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9207                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9208                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9209                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9210                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9211                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9212                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9213                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9214                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9215                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9216                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9217                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9218                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9219                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9220                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9221                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9222                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9223         };
9224
9225         return pctype_table[flow_type];
9226 }
9227
9228 uint16_t
9229 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9230 {
9231         static const uint16_t flowtype_table[] = {
9232                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9233                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9234                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9235                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9236                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9237                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9238                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9239                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9240                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9241                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9242                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9243                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9244                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9245                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9246                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9247                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9248                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9249                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9250                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9251                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9252                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9253                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9255                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9256                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9257                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9259                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9260                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9261                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9262                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9263         };
9264
9265         return flowtype_table[pctype];
9266 }
9267
9268 /*
9269  * On X710, performance number is far from the expectation on recent firmware
9270  * versions; on XL710, performance number is also far from the expectation on
9271  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9272  * mode is enabled and port MAC address is equal to the packet destination MAC
9273  * address. The fix for this issue may not be integrated in the following
9274  * firmware version. So the workaround in software driver is needed. It needs
9275  * to modify the initial values of 3 internal only registers for both X710 and
9276  * XL710. Note that the values for X710 or XL710 could be different, and the
9277  * workaround can be removed when it is fixed in firmware in the future.
9278  */
9279
9280 /* For both X710 and XL710 */
9281 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9282 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x20000200
9283 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9284
9285 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9286 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9287
9288 /* For X722 */
9289 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9290 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9291
9292 /* For X710 */
9293 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9294 /* For XL710 */
9295 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9296 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9297
9298 static int
9299 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9300 {
9301         enum i40e_status_code status;
9302         struct i40e_aq_get_phy_abilities_resp phy_ab;
9303         int ret = -ENOTSUP;
9304         int retries = 0;
9305
9306         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9307                                               NULL);
9308
9309         while (status) {
9310                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9311                         status);
9312                 retries++;
9313                 rte_delay_us(100000);
9314                 if  (retries < 5)
9315                         status = i40e_aq_get_phy_capabilities(hw, false,
9316                                         true, &phy_ab, NULL);
9317                 else
9318                         return ret;
9319         }
9320         return 0;
9321 }
9322
9323 static void
9324 i40e_configure_registers(struct i40e_hw *hw)
9325 {
9326         static struct {
9327                 uint32_t addr;
9328                 uint64_t val;
9329         } reg_table[] = {
9330                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9331                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9332                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9333         };
9334         uint64_t reg;
9335         uint32_t i;
9336         int ret;
9337
9338         for (i = 0; i < RTE_DIM(reg_table); i++) {
9339                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9340                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9341                                 reg_table[i].val =
9342                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9343                         else /* For X710/XL710/XXV710 */
9344                                 if (hw->aq.fw_maj_ver < 6)
9345                                         reg_table[i].val =
9346                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9347                                 else
9348                                         reg_table[i].val =
9349                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9350                 }
9351
9352                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9353                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9354                                 reg_table[i].val =
9355                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9356                         else /* For X710/XL710/XXV710 */
9357                                 reg_table[i].val =
9358                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9359                 }
9360
9361                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9362                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9363                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9364                                 reg_table[i].val =
9365                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9366                         else /* For X710 */
9367                                 reg_table[i].val =
9368                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9369                 }
9370
9371                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9372                                                         &reg, NULL);
9373                 if (ret < 0) {
9374                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9375                                                         reg_table[i].addr);
9376                         break;
9377                 }
9378                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9379                                                 reg_table[i].addr, reg);
9380                 if (reg == reg_table[i].val)
9381                         continue;
9382
9383                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9384                                                 reg_table[i].val, NULL);
9385                 if (ret < 0) {
9386                         PMD_DRV_LOG(ERR,
9387                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9388                                 reg_table[i].val, reg_table[i].addr);
9389                         break;
9390                 }
9391                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9392                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9393         }
9394 }
9395
9396 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9397 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9398 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9399 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9400 static int
9401 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9402 {
9403         uint32_t reg;
9404         int ret;
9405
9406         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9407                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9408                 return -EINVAL;
9409         }
9410
9411         /* Configure for double VLAN RX stripping */
9412         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9413         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9414                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9415                 ret = i40e_aq_debug_write_register(hw,
9416                                                    I40E_VSI_TSR(vsi->vsi_id),
9417                                                    reg, NULL);
9418                 if (ret < 0) {
9419                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9420                                     vsi->vsi_id);
9421                         return I40E_ERR_CONFIG;
9422                 }
9423         }
9424
9425         /* Configure for double VLAN TX insertion */
9426         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9427         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9428                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9429                 ret = i40e_aq_debug_write_register(hw,
9430                                                    I40E_VSI_L2TAGSTXVALID(
9431                                                    vsi->vsi_id), reg, NULL);
9432                 if (ret < 0) {
9433                         PMD_DRV_LOG(ERR,
9434                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9435                                 vsi->vsi_id);
9436                         return I40E_ERR_CONFIG;
9437                 }
9438         }
9439
9440         return 0;
9441 }
9442
9443 /**
9444  * i40e_aq_add_mirror_rule
9445  * @hw: pointer to the hardware structure
9446  * @seid: VEB seid to add mirror rule to
9447  * @dst_id: destination vsi seid
9448  * @entries: Buffer which contains the entities to be mirrored
9449  * @count: number of entities contained in the buffer
9450  * @rule_id:the rule_id of the rule to be added
9451  *
9452  * Add a mirror rule for a given veb.
9453  *
9454  **/
9455 static enum i40e_status_code
9456 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9457                         uint16_t seid, uint16_t dst_id,
9458                         uint16_t rule_type, uint16_t *entries,
9459                         uint16_t count, uint16_t *rule_id)
9460 {
9461         struct i40e_aq_desc desc;
9462         struct i40e_aqc_add_delete_mirror_rule cmd;
9463         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9464                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9465                 &desc.params.raw;
9466         uint16_t buff_len;
9467         enum i40e_status_code status;
9468
9469         i40e_fill_default_direct_cmd_desc(&desc,
9470                                           i40e_aqc_opc_add_mirror_rule);
9471         memset(&cmd, 0, sizeof(cmd));
9472
9473         buff_len = sizeof(uint16_t) * count;
9474         desc.datalen = rte_cpu_to_le_16(buff_len);
9475         if (buff_len > 0)
9476                 desc.flags |= rte_cpu_to_le_16(
9477                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9478         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9479                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9480         cmd.num_entries = rte_cpu_to_le_16(count);
9481         cmd.seid = rte_cpu_to_le_16(seid);
9482         cmd.destination = rte_cpu_to_le_16(dst_id);
9483
9484         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9485         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9486         PMD_DRV_LOG(INFO,
9487                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9488                 hw->aq.asq_last_status, resp->rule_id,
9489                 resp->mirror_rules_used, resp->mirror_rules_free);
9490         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9491
9492         return status;
9493 }
9494
9495 /**
9496  * i40e_aq_del_mirror_rule
9497  * @hw: pointer to the hardware structure
9498  * @seid: VEB seid to add mirror rule to
9499  * @entries: Buffer which contains the entities to be mirrored
9500  * @count: number of entities contained in the buffer
9501  * @rule_id:the rule_id of the rule to be delete
9502  *
9503  * Delete a mirror rule for a given veb.
9504  *
9505  **/
9506 static enum i40e_status_code
9507 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9508                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9509                 uint16_t count, uint16_t rule_id)
9510 {
9511         struct i40e_aq_desc desc;
9512         struct i40e_aqc_add_delete_mirror_rule cmd;
9513         uint16_t buff_len = 0;
9514         enum i40e_status_code status;
9515         void *buff = NULL;
9516
9517         i40e_fill_default_direct_cmd_desc(&desc,
9518                                           i40e_aqc_opc_delete_mirror_rule);
9519         memset(&cmd, 0, sizeof(cmd));
9520         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9521                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9522                                                           I40E_AQ_FLAG_RD));
9523                 cmd.num_entries = count;
9524                 buff_len = sizeof(uint16_t) * count;
9525                 desc.datalen = rte_cpu_to_le_16(buff_len);
9526                 buff = (void *)entries;
9527         } else
9528                 /* rule id is filled in destination field for deleting mirror rule */
9529                 cmd.destination = rte_cpu_to_le_16(rule_id);
9530
9531         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9532                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9533         cmd.seid = rte_cpu_to_le_16(seid);
9534
9535         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9536         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9537
9538         return status;
9539 }
9540
9541 /**
9542  * i40e_mirror_rule_set
9543  * @dev: pointer to the hardware structure
9544  * @mirror_conf: mirror rule info
9545  * @sw_id: mirror rule's sw_id
9546  * @on: enable/disable
9547  *
9548  * set a mirror rule.
9549  *
9550  **/
9551 static int
9552 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9553                         struct rte_eth_mirror_conf *mirror_conf,
9554                         uint8_t sw_id, uint8_t on)
9555 {
9556         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9557         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9558         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9559         struct i40e_mirror_rule *parent = NULL;
9560         uint16_t seid, dst_seid, rule_id;
9561         uint16_t i, j = 0;
9562         int ret;
9563
9564         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9565
9566         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9567                 PMD_DRV_LOG(ERR,
9568                         "mirror rule can not be configured without veb or vfs.");
9569                 return -ENOSYS;
9570         }
9571         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9572                 PMD_DRV_LOG(ERR, "mirror table is full.");
9573                 return -ENOSPC;
9574         }
9575         if (mirror_conf->dst_pool > pf->vf_num) {
9576                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9577                                  mirror_conf->dst_pool);
9578                 return -EINVAL;
9579         }
9580
9581         seid = pf->main_vsi->veb->seid;
9582
9583         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9584                 if (sw_id <= it->index) {
9585                         mirr_rule = it;
9586                         break;
9587                 }
9588                 parent = it;
9589         }
9590         if (mirr_rule && sw_id == mirr_rule->index) {
9591                 if (on) {
9592                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9593                         return -EEXIST;
9594                 } else {
9595                         ret = i40e_aq_del_mirror_rule(hw, seid,
9596                                         mirr_rule->rule_type,
9597                                         mirr_rule->entries,
9598                                         mirr_rule->num_entries, mirr_rule->id);
9599                         if (ret < 0) {
9600                                 PMD_DRV_LOG(ERR,
9601                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9602                                         ret, hw->aq.asq_last_status);
9603                                 return -ENOSYS;
9604                         }
9605                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9606                         rte_free(mirr_rule);
9607                         pf->nb_mirror_rule--;
9608                         return 0;
9609                 }
9610         } else if (!on) {
9611                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9612                 return -ENOENT;
9613         }
9614
9615         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9616                                 sizeof(struct i40e_mirror_rule) , 0);
9617         if (!mirr_rule) {
9618                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9619                 return I40E_ERR_NO_MEMORY;
9620         }
9621         switch (mirror_conf->rule_type) {
9622         case ETH_MIRROR_VLAN:
9623                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9624                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9625                                 mirr_rule->entries[j] =
9626                                         mirror_conf->vlan.vlan_id[i];
9627                                 j++;
9628                         }
9629                 }
9630                 if (j == 0) {
9631                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9632                         rte_free(mirr_rule);
9633                         return -EINVAL;
9634                 }
9635                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9636                 break;
9637         case ETH_MIRROR_VIRTUAL_POOL_UP:
9638         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9639                 /* check if the specified pool bit is out of range */
9640                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9641                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9642                         rte_free(mirr_rule);
9643                         return -EINVAL;
9644                 }
9645                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9646                         if (mirror_conf->pool_mask & (1ULL << i)) {
9647                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9648                                 j++;
9649                         }
9650                 }
9651                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9652                         /* add pf vsi to entries */
9653                         mirr_rule->entries[j] = pf->main_vsi_seid;
9654                         j++;
9655                 }
9656                 if (j == 0) {
9657                         PMD_DRV_LOG(ERR, "pool is not specified.");
9658                         rte_free(mirr_rule);
9659                         return -EINVAL;
9660                 }
9661                 /* egress and ingress in aq commands means from switch but not port */
9662                 mirr_rule->rule_type =
9663                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9664                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9665                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9666                 break;
9667         case ETH_MIRROR_UPLINK_PORT:
9668                 /* egress and ingress in aq commands means from switch but not port*/
9669                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9670                 break;
9671         case ETH_MIRROR_DOWNLINK_PORT:
9672                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9673                 break;
9674         default:
9675                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9676                         mirror_conf->rule_type);
9677                 rte_free(mirr_rule);
9678                 return -EINVAL;
9679         }
9680
9681         /* If the dst_pool is equal to vf_num, consider it as PF */
9682         if (mirror_conf->dst_pool == pf->vf_num)
9683                 dst_seid = pf->main_vsi_seid;
9684         else
9685                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9686
9687         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9688                                       mirr_rule->rule_type, mirr_rule->entries,
9689                                       j, &rule_id);
9690         if (ret < 0) {
9691                 PMD_DRV_LOG(ERR,
9692                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9693                         ret, hw->aq.asq_last_status);
9694                 rte_free(mirr_rule);
9695                 return -ENOSYS;
9696         }
9697
9698         mirr_rule->index = sw_id;
9699         mirr_rule->num_entries = j;
9700         mirr_rule->id = rule_id;
9701         mirr_rule->dst_vsi_seid = dst_seid;
9702
9703         if (parent)
9704                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9705         else
9706                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9707
9708         pf->nb_mirror_rule++;
9709         return 0;
9710 }
9711
9712 /**
9713  * i40e_mirror_rule_reset
9714  * @dev: pointer to the device
9715  * @sw_id: mirror rule's sw_id
9716  *
9717  * reset a mirror rule.
9718  *
9719  **/
9720 static int
9721 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9722 {
9723         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9724         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9725         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9726         uint16_t seid;
9727         int ret;
9728
9729         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9730
9731         seid = pf->main_vsi->veb->seid;
9732
9733         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9734                 if (sw_id == it->index) {
9735                         mirr_rule = it;
9736                         break;
9737                 }
9738         }
9739         if (mirr_rule) {
9740                 ret = i40e_aq_del_mirror_rule(hw, seid,
9741                                 mirr_rule->rule_type,
9742                                 mirr_rule->entries,
9743                                 mirr_rule->num_entries, mirr_rule->id);
9744                 if (ret < 0) {
9745                         PMD_DRV_LOG(ERR,
9746                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9747                                 ret, hw->aq.asq_last_status);
9748                         return -ENOSYS;
9749                 }
9750                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9751                 rte_free(mirr_rule);
9752                 pf->nb_mirror_rule--;
9753         } else {
9754                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9755                 return -ENOENT;
9756         }
9757         return 0;
9758 }
9759
9760 static uint64_t
9761 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9762 {
9763         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9764         uint64_t systim_cycles;
9765
9766         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9767         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9768                         << 32;
9769
9770         return systim_cycles;
9771 }
9772
9773 static uint64_t
9774 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9775 {
9776         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9777         uint64_t rx_tstamp;
9778
9779         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9780         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9781                         << 32;
9782
9783         return rx_tstamp;
9784 }
9785
9786 static uint64_t
9787 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9788 {
9789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9790         uint64_t tx_tstamp;
9791
9792         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9793         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9794                         << 32;
9795
9796         return tx_tstamp;
9797 }
9798
9799 static void
9800 i40e_start_timecounters(struct rte_eth_dev *dev)
9801 {
9802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9803         struct i40e_adapter *adapter =
9804                         (struct i40e_adapter *)dev->data->dev_private;
9805         struct rte_eth_link link;
9806         uint32_t tsync_inc_l;
9807         uint32_t tsync_inc_h;
9808
9809         /* Get current link speed. */
9810         memset(&link, 0, sizeof(link));
9811         i40e_dev_link_update(dev, 1);
9812         rte_i40e_dev_atomic_read_link_status(dev, &link);
9813
9814         switch (link.link_speed) {
9815         case ETH_SPEED_NUM_40G:
9816                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9817                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9818                 break;
9819         case ETH_SPEED_NUM_10G:
9820                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9821                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9822                 break;
9823         case ETH_SPEED_NUM_1G:
9824                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9825                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9826                 break;
9827         default:
9828                 tsync_inc_l = 0x0;
9829                 tsync_inc_h = 0x0;
9830         }
9831
9832         /* Set the timesync increment value. */
9833         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9834         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9835
9836         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9837         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9838         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9839
9840         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9841         adapter->systime_tc.cc_shift = 0;
9842         adapter->systime_tc.nsec_mask = 0;
9843
9844         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9845         adapter->rx_tstamp_tc.cc_shift = 0;
9846         adapter->rx_tstamp_tc.nsec_mask = 0;
9847
9848         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9849         adapter->tx_tstamp_tc.cc_shift = 0;
9850         adapter->tx_tstamp_tc.nsec_mask = 0;
9851 }
9852
9853 static int
9854 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9855 {
9856         struct i40e_adapter *adapter =
9857                         (struct i40e_adapter *)dev->data->dev_private;
9858
9859         adapter->systime_tc.nsec += delta;
9860         adapter->rx_tstamp_tc.nsec += delta;
9861         adapter->tx_tstamp_tc.nsec += delta;
9862
9863         return 0;
9864 }
9865
9866 static int
9867 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9868 {
9869         uint64_t ns;
9870         struct i40e_adapter *adapter =
9871                         (struct i40e_adapter *)dev->data->dev_private;
9872
9873         ns = rte_timespec_to_ns(ts);
9874
9875         /* Set the timecounters to a new value. */
9876         adapter->systime_tc.nsec = ns;
9877         adapter->rx_tstamp_tc.nsec = ns;
9878         adapter->tx_tstamp_tc.nsec = ns;
9879
9880         return 0;
9881 }
9882
9883 static int
9884 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9885 {
9886         uint64_t ns, systime_cycles;
9887         struct i40e_adapter *adapter =
9888                         (struct i40e_adapter *)dev->data->dev_private;
9889
9890         systime_cycles = i40e_read_systime_cyclecounter(dev);
9891         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9892         *ts = rte_ns_to_timespec(ns);
9893
9894         return 0;
9895 }
9896
9897 static int
9898 i40e_timesync_enable(struct rte_eth_dev *dev)
9899 {
9900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9901         uint32_t tsync_ctl_l;
9902         uint32_t tsync_ctl_h;
9903
9904         /* Stop the timesync system time. */
9905         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9906         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9907         /* Reset the timesync system time value. */
9908         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9909         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9910
9911         i40e_start_timecounters(dev);
9912
9913         /* Clear timesync registers. */
9914         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9915         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9916         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9917         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9918         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9919         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9920
9921         /* Enable timestamping of PTP packets. */
9922         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9923         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9924
9925         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9926         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9927         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9928
9929         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9930         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9931
9932         return 0;
9933 }
9934
9935 static int
9936 i40e_timesync_disable(struct rte_eth_dev *dev)
9937 {
9938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9939         uint32_t tsync_ctl_l;
9940         uint32_t tsync_ctl_h;
9941
9942         /* Disable timestamping of transmitted PTP packets. */
9943         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9944         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9945
9946         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9947         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9948
9949         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9950         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9951
9952         /* Reset the timesync increment value. */
9953         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9954         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9955
9956         return 0;
9957 }
9958
9959 static int
9960 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9961                                 struct timespec *timestamp, uint32_t flags)
9962 {
9963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9964         struct i40e_adapter *adapter =
9965                 (struct i40e_adapter *)dev->data->dev_private;
9966
9967         uint32_t sync_status;
9968         uint32_t index = flags & 0x03;
9969         uint64_t rx_tstamp_cycles;
9970         uint64_t ns;
9971
9972         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9973         if ((sync_status & (1 << index)) == 0)
9974                 return -EINVAL;
9975
9976         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9977         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9978         *timestamp = rte_ns_to_timespec(ns);
9979
9980         return 0;
9981 }
9982
9983 static int
9984 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9985                                 struct timespec *timestamp)
9986 {
9987         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9988         struct i40e_adapter *adapter =
9989                 (struct i40e_adapter *)dev->data->dev_private;
9990
9991         uint32_t sync_status;
9992         uint64_t tx_tstamp_cycles;
9993         uint64_t ns;
9994
9995         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9996         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9997                 return -EINVAL;
9998
9999         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10000         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10001         *timestamp = rte_ns_to_timespec(ns);
10002
10003         return 0;
10004 }
10005
10006 /*
10007  * i40e_parse_dcb_configure - parse dcb configure from user
10008  * @dev: the device being configured
10009  * @dcb_cfg: pointer of the result of parse
10010  * @*tc_map: bit map of enabled traffic classes
10011  *
10012  * Returns 0 on success, negative value on failure
10013  */
10014 static int
10015 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10016                          struct i40e_dcbx_config *dcb_cfg,
10017                          uint8_t *tc_map)
10018 {
10019         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10020         uint8_t i, tc_bw, bw_lf;
10021
10022         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10023
10024         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10025         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10026                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10027                 return -EINVAL;
10028         }
10029
10030         /* assume each tc has the same bw */
10031         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10032         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10033                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10034         /* to ensure the sum of tcbw is equal to 100 */
10035         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10036         for (i = 0; i < bw_lf; i++)
10037                 dcb_cfg->etscfg.tcbwtable[i]++;
10038
10039         /* assume each tc has the same Transmission Selection Algorithm */
10040         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10041                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10042
10043         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10044                 dcb_cfg->etscfg.prioritytable[i] =
10045                                 dcb_rx_conf->dcb_tc[i];
10046
10047         /* FW needs one App to configure HW */
10048         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10049         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10050         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10051         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10052
10053         if (dcb_rx_conf->nb_tcs == 0)
10054                 *tc_map = 1; /* tc0 only */
10055         else
10056                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10057
10058         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10059                 dcb_cfg->pfc.willing = 0;
10060                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10061                 dcb_cfg->pfc.pfcenable = *tc_map;
10062         }
10063         return 0;
10064 }
10065
10066
10067 static enum i40e_status_code
10068 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10069                               struct i40e_aqc_vsi_properties_data *info,
10070                               uint8_t enabled_tcmap)
10071 {
10072         enum i40e_status_code ret;
10073         int i, total_tc = 0;
10074         uint16_t qpnum_per_tc, bsf, qp_idx;
10075         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10076         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10077         uint16_t used_queues;
10078
10079         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10080         if (ret != I40E_SUCCESS)
10081                 return ret;
10082
10083         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10084                 if (enabled_tcmap & (1 << i))
10085                         total_tc++;
10086         }
10087         if (total_tc == 0)
10088                 total_tc = 1;
10089         vsi->enabled_tc = enabled_tcmap;
10090
10091         /* different VSI has different queues assigned */
10092         if (vsi->type == I40E_VSI_MAIN)
10093                 used_queues = dev_data->nb_rx_queues -
10094                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10095         else if (vsi->type == I40E_VSI_VMDQ2)
10096                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10097         else {
10098                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10099                 return I40E_ERR_NO_AVAILABLE_VSI;
10100         }
10101
10102         qpnum_per_tc = used_queues / total_tc;
10103         /* Number of queues per enabled TC */
10104         if (qpnum_per_tc == 0) {
10105                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10106                 return I40E_ERR_INVALID_QP_ID;
10107         }
10108         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10109                                 I40E_MAX_Q_PER_TC);
10110         bsf = rte_bsf32(qpnum_per_tc);
10111
10112         /**
10113          * Configure TC and queue mapping parameters, for enabled TC,
10114          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10115          * default queue will serve it.
10116          */
10117         qp_idx = 0;
10118         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10119                 if (vsi->enabled_tc & (1 << i)) {
10120                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10121                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10122                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10123                         qp_idx += qpnum_per_tc;
10124                 } else
10125                         info->tc_mapping[i] = 0;
10126         }
10127
10128         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10129         if (vsi->type == I40E_VSI_SRIOV) {
10130                 info->mapping_flags |=
10131                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10132                 for (i = 0; i < vsi->nb_qps; i++)
10133                         info->queue_mapping[i] =
10134                                 rte_cpu_to_le_16(vsi->base_queue + i);
10135         } else {
10136                 info->mapping_flags |=
10137                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10138                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10139         }
10140         info->valid_sections |=
10141                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10142
10143         return I40E_SUCCESS;
10144 }
10145
10146 /*
10147  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10148  * @veb: VEB to be configured
10149  * @tc_map: enabled TC bitmap
10150  *
10151  * Returns 0 on success, negative value on failure
10152  */
10153 static enum i40e_status_code
10154 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10155 {
10156         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10157         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10158         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10159         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10160         enum i40e_status_code ret = I40E_SUCCESS;
10161         int i;
10162         uint32_t bw_max;
10163
10164         /* Check if enabled_tc is same as existing or new TCs */
10165         if (veb->enabled_tc == tc_map)
10166                 return ret;
10167
10168         /* configure tc bandwidth */
10169         memset(&veb_bw, 0, sizeof(veb_bw));
10170         veb_bw.tc_valid_bits = tc_map;
10171         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10172         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10173                 if (tc_map & BIT_ULL(i))
10174                         veb_bw.tc_bw_share_credits[i] = 1;
10175         }
10176         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10177                                                    &veb_bw, NULL);
10178         if (ret) {
10179                 PMD_INIT_LOG(ERR,
10180                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10181                         hw->aq.asq_last_status);
10182                 return ret;
10183         }
10184
10185         memset(&ets_query, 0, sizeof(ets_query));
10186         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10187                                                    &ets_query, NULL);
10188         if (ret != I40E_SUCCESS) {
10189                 PMD_DRV_LOG(ERR,
10190                         "Failed to get switch_comp ETS configuration %u",
10191                         hw->aq.asq_last_status);
10192                 return ret;
10193         }
10194         memset(&bw_query, 0, sizeof(bw_query));
10195         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10196                                                   &bw_query, NULL);
10197         if (ret != I40E_SUCCESS) {
10198                 PMD_DRV_LOG(ERR,
10199                         "Failed to get switch_comp bandwidth configuration %u",
10200                         hw->aq.asq_last_status);
10201                 return ret;
10202         }
10203
10204         /* store and print out BW info */
10205         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10206         veb->bw_info.bw_max = ets_query.tc_bw_max;
10207         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10208         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10209         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10210                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10211                      I40E_16_BIT_WIDTH);
10212         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10213                 veb->bw_info.bw_ets_share_credits[i] =
10214                                 bw_query.tc_bw_share_credits[i];
10215                 veb->bw_info.bw_ets_credits[i] =
10216                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10217                 /* 4 bits per TC, 4th bit is reserved */
10218                 veb->bw_info.bw_ets_max[i] =
10219                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10220                                   RTE_LEN2MASK(3, uint8_t));
10221                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10222                             veb->bw_info.bw_ets_share_credits[i]);
10223                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10224                             veb->bw_info.bw_ets_credits[i]);
10225                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10226                             veb->bw_info.bw_ets_max[i]);
10227         }
10228
10229         veb->enabled_tc = tc_map;
10230
10231         return ret;
10232 }
10233
10234
10235 /*
10236  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10237  * @vsi: VSI to be configured
10238  * @tc_map: enabled TC bitmap
10239  *
10240  * Returns 0 on success, negative value on failure
10241  */
10242 static enum i40e_status_code
10243 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10244 {
10245         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10246         struct i40e_vsi_context ctxt;
10247         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10248         enum i40e_status_code ret = I40E_SUCCESS;
10249         int i;
10250
10251         /* Check if enabled_tc is same as existing or new TCs */
10252         if (vsi->enabled_tc == tc_map)
10253                 return ret;
10254
10255         /* configure tc bandwidth */
10256         memset(&bw_data, 0, sizeof(bw_data));
10257         bw_data.tc_valid_bits = tc_map;
10258         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10259         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10260                 if (tc_map & BIT_ULL(i))
10261                         bw_data.tc_bw_credits[i] = 1;
10262         }
10263         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10264         if (ret) {
10265                 PMD_INIT_LOG(ERR,
10266                         "AQ command Config VSI BW allocation per TC failed = %d",
10267                         hw->aq.asq_last_status);
10268                 goto out;
10269         }
10270         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10271                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10272
10273         /* Update Queue Pairs Mapping for currently enabled UPs */
10274         ctxt.seid = vsi->seid;
10275         ctxt.pf_num = hw->pf_id;
10276         ctxt.vf_num = 0;
10277         ctxt.uplink_seid = vsi->uplink_seid;
10278         ctxt.info = vsi->info;
10279         i40e_get_cap(hw);
10280         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10281         if (ret)
10282                 goto out;
10283
10284         /* Update the VSI after updating the VSI queue-mapping information */
10285         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10286         if (ret) {
10287                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10288                         hw->aq.asq_last_status);
10289                 goto out;
10290         }
10291         /* update the local VSI info with updated queue map */
10292         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10293                                         sizeof(vsi->info.tc_mapping));
10294         (void)rte_memcpy(&vsi->info.queue_mapping,
10295                         &ctxt.info.queue_mapping,
10296                 sizeof(vsi->info.queue_mapping));
10297         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10298         vsi->info.valid_sections = 0;
10299
10300         /* query and update current VSI BW information */
10301         ret = i40e_vsi_get_bw_config(vsi);
10302         if (ret) {
10303                 PMD_INIT_LOG(ERR,
10304                          "Failed updating vsi bw info, err %s aq_err %s",
10305                          i40e_stat_str(hw, ret),
10306                          i40e_aq_str(hw, hw->aq.asq_last_status));
10307                 goto out;
10308         }
10309
10310         vsi->enabled_tc = tc_map;
10311
10312 out:
10313         return ret;
10314 }
10315
10316 /*
10317  * i40e_dcb_hw_configure - program the dcb setting to hw
10318  * @pf: pf the configuration is taken on
10319  * @new_cfg: new configuration
10320  * @tc_map: enabled TC bitmap
10321  *
10322  * Returns 0 on success, negative value on failure
10323  */
10324 static enum i40e_status_code
10325 i40e_dcb_hw_configure(struct i40e_pf *pf,
10326                       struct i40e_dcbx_config *new_cfg,
10327                       uint8_t tc_map)
10328 {
10329         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10330         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10331         struct i40e_vsi *main_vsi = pf->main_vsi;
10332         struct i40e_vsi_list *vsi_list;
10333         enum i40e_status_code ret;
10334         int i;
10335         uint32_t val;
10336
10337         /* Use the FW API if FW > v4.4*/
10338         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10339               (hw->aq.fw_maj_ver >= 5))) {
10340                 PMD_INIT_LOG(ERR,
10341                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10342                 return I40E_ERR_FIRMWARE_API_VERSION;
10343         }
10344
10345         /* Check if need reconfiguration */
10346         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10347                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10348                 return I40E_SUCCESS;
10349         }
10350
10351         /* Copy the new config to the current config */
10352         *old_cfg = *new_cfg;
10353         old_cfg->etsrec = old_cfg->etscfg;
10354         ret = i40e_set_dcb_config(hw);
10355         if (ret) {
10356                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10357                          i40e_stat_str(hw, ret),
10358                          i40e_aq_str(hw, hw->aq.asq_last_status));
10359                 return ret;
10360         }
10361         /* set receive Arbiter to RR mode and ETS scheme by default */
10362         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10363                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10364                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10365                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10366                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10367                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10368                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10369                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10370                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10371                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10372                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10373                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10374                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10375         }
10376         /* get local mib to check whether it is configured correctly */
10377         /* IEEE mode */
10378         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10379         /* Get Local DCB Config */
10380         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10381                                      &hw->local_dcbx_config);
10382
10383         /* if Veb is created, need to update TC of it at first */
10384         if (main_vsi->veb) {
10385                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10386                 if (ret)
10387                         PMD_INIT_LOG(WARNING,
10388                                  "Failed configuring TC for VEB seid=%d",
10389                                  main_vsi->veb->seid);
10390         }
10391         /* Update each VSI */
10392         i40e_vsi_config_tc(main_vsi, tc_map);
10393         if (main_vsi->veb) {
10394                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10395                         /* Beside main VSI and VMDQ VSIs, only enable default
10396                          * TC for other VSIs
10397                          */
10398                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10399                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10400                                                          tc_map);
10401                         else
10402                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10403                                                          I40E_DEFAULT_TCMAP);
10404                         if (ret)
10405                                 PMD_INIT_LOG(WARNING,
10406                                         "Failed configuring TC for VSI seid=%d",
10407                                         vsi_list->vsi->seid);
10408                         /* continue */
10409                 }
10410         }
10411         return I40E_SUCCESS;
10412 }
10413
10414 /*
10415  * i40e_dcb_init_configure - initial dcb config
10416  * @dev: device being configured
10417  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10418  *
10419  * Returns 0 on success, negative value on failure
10420  */
10421 static int
10422 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10423 {
10424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10426         int i, ret = 0;
10427
10428         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10429                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10430                 return -ENOTSUP;
10431         }
10432
10433         /* DCB initialization:
10434          * Update DCB configuration from the Firmware and configure
10435          * LLDP MIB change event.
10436          */
10437         if (sw_dcb == TRUE) {
10438                 ret = i40e_init_dcb(hw);
10439                 /* If lldp agent is stopped, the return value from
10440                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10441                  * adminq status. Otherwise, it should return success.
10442                  */
10443                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10444                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10445                         memset(&hw->local_dcbx_config, 0,
10446                                 sizeof(struct i40e_dcbx_config));
10447                         /* set dcb default configuration */
10448                         hw->local_dcbx_config.etscfg.willing = 0;
10449                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10450                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10451                         hw->local_dcbx_config.etscfg.tsatable[0] =
10452                                                 I40E_IEEE_TSA_ETS;
10453                         /* all UPs mapping to TC0 */
10454                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10455                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10456                         hw->local_dcbx_config.etsrec =
10457                                 hw->local_dcbx_config.etscfg;
10458                         hw->local_dcbx_config.pfc.willing = 0;
10459                         hw->local_dcbx_config.pfc.pfccap =
10460                                                 I40E_MAX_TRAFFIC_CLASS;
10461                         /* FW needs one App to configure HW */
10462                         hw->local_dcbx_config.numapps = 1;
10463                         hw->local_dcbx_config.app[0].selector =
10464                                                 I40E_APP_SEL_ETHTYPE;
10465                         hw->local_dcbx_config.app[0].priority = 3;
10466                         hw->local_dcbx_config.app[0].protocolid =
10467                                                 I40E_APP_PROTOID_FCOE;
10468                         ret = i40e_set_dcb_config(hw);
10469                         if (ret) {
10470                                 PMD_INIT_LOG(ERR,
10471                                         "default dcb config fails. err = %d, aq_err = %d.",
10472                                         ret, hw->aq.asq_last_status);
10473                                 return -ENOSYS;
10474                         }
10475                 } else {
10476                         PMD_INIT_LOG(ERR,
10477                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10478                                 ret, hw->aq.asq_last_status);
10479                         return -ENOTSUP;
10480                 }
10481         } else {
10482                 ret = i40e_aq_start_lldp(hw, NULL);
10483                 if (ret != I40E_SUCCESS)
10484                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10485
10486                 ret = i40e_init_dcb(hw);
10487                 if (!ret) {
10488                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10489                                 PMD_INIT_LOG(ERR,
10490                                         "HW doesn't support DCBX offload.");
10491                                 return -ENOTSUP;
10492                         }
10493                 } else {
10494                         PMD_INIT_LOG(ERR,
10495                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10496                                 ret, hw->aq.asq_last_status);
10497                         return -ENOTSUP;
10498                 }
10499         }
10500         return 0;
10501 }
10502
10503 /*
10504  * i40e_dcb_setup - setup dcb related config
10505  * @dev: device being configured
10506  *
10507  * Returns 0 on success, negative value on failure
10508  */
10509 static int
10510 i40e_dcb_setup(struct rte_eth_dev *dev)
10511 {
10512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10513         struct i40e_dcbx_config dcb_cfg;
10514         uint8_t tc_map = 0;
10515         int ret = 0;
10516
10517         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10518                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10519                 return -ENOTSUP;
10520         }
10521
10522         if (pf->vf_num != 0)
10523                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10524
10525         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10526         if (ret) {
10527                 PMD_INIT_LOG(ERR, "invalid dcb config");
10528                 return -EINVAL;
10529         }
10530         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10531         if (ret) {
10532                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10533                 return -ENOSYS;
10534         }
10535
10536         return 0;
10537 }
10538
10539 static int
10540 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10541                       struct rte_eth_dcb_info *dcb_info)
10542 {
10543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10544         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10545         struct i40e_vsi *vsi = pf->main_vsi;
10546         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10547         uint16_t bsf, tc_mapping;
10548         int i, j = 0;
10549
10550         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10551                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10552         else
10553                 dcb_info->nb_tcs = 1;
10554         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10555                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10556         for (i = 0; i < dcb_info->nb_tcs; i++)
10557                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10558
10559         /* get queue mapping if vmdq is disabled */
10560         if (!pf->nb_cfg_vmdq_vsi) {
10561                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10562                         if (!(vsi->enabled_tc & (1 << i)))
10563                                 continue;
10564                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10565                         dcb_info->tc_queue.tc_rxq[j][i].base =
10566                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10567                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10568                         dcb_info->tc_queue.tc_txq[j][i].base =
10569                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10570                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10571                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10572                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10573                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10574                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10575                 }
10576                 return 0;
10577         }
10578
10579         /* get queue mapping if vmdq is enabled */
10580         do {
10581                 vsi = pf->vmdq[j].vsi;
10582                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10583                         if (!(vsi->enabled_tc & (1 << i)))
10584                                 continue;
10585                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10586                         dcb_info->tc_queue.tc_rxq[j][i].base =
10587                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10588                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10589                         dcb_info->tc_queue.tc_txq[j][i].base =
10590                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10591                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10592                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10593                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10594                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10595                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10596                 }
10597                 j++;
10598         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10599         return 0;
10600 }
10601
10602 static int
10603 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10604 {
10605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10608         uint16_t interval =
10609                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10610         uint16_t msix_intr;
10611
10612         msix_intr = intr_handle->intr_vec[queue_id];
10613         if (msix_intr == I40E_MISC_VEC_ID)
10614                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10615                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10616                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10617                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10618                                (interval <<
10619                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10620         else
10621                 I40E_WRITE_REG(hw,
10622                                I40E_PFINT_DYN_CTLN(msix_intr -
10623                                                    I40E_RX_VEC_START),
10624                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10625                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10626                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10627                                (interval <<
10628                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10629
10630         I40E_WRITE_FLUSH(hw);
10631         rte_intr_enable(&pci_dev->intr_handle);
10632
10633         return 0;
10634 }
10635
10636 static int
10637 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10638 {
10639         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10640         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10641         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10642         uint16_t msix_intr;
10643
10644         msix_intr = intr_handle->intr_vec[queue_id];
10645         if (msix_intr == I40E_MISC_VEC_ID)
10646                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10647         else
10648                 I40E_WRITE_REG(hw,
10649                                I40E_PFINT_DYN_CTLN(msix_intr -
10650                                                    I40E_RX_VEC_START),
10651                                0);
10652         I40E_WRITE_FLUSH(hw);
10653
10654         return 0;
10655 }
10656
10657 static int i40e_get_regs(struct rte_eth_dev *dev,
10658                          struct rte_dev_reg_info *regs)
10659 {
10660         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10661         uint32_t *ptr_data = regs->data;
10662         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10663         const struct i40e_reg_info *reg_info;
10664
10665         if (ptr_data == NULL) {
10666                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10667                 regs->width = sizeof(uint32_t);
10668                 return 0;
10669         }
10670
10671         /* The first few registers have to be read using AQ operations */
10672         reg_idx = 0;
10673         while (i40e_regs_adminq[reg_idx].name) {
10674                 reg_info = &i40e_regs_adminq[reg_idx++];
10675                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10676                         for (arr_idx2 = 0;
10677                                         arr_idx2 <= reg_info->count2;
10678                                         arr_idx2++) {
10679                                 reg_offset = arr_idx * reg_info->stride1 +
10680                                         arr_idx2 * reg_info->stride2;
10681                                 reg_offset += reg_info->base_addr;
10682                                 ptr_data[reg_offset >> 2] =
10683                                         i40e_read_rx_ctl(hw, reg_offset);
10684                         }
10685         }
10686
10687         /* The remaining registers can be read using primitives */
10688         reg_idx = 0;
10689         while (i40e_regs_others[reg_idx].name) {
10690                 reg_info = &i40e_regs_others[reg_idx++];
10691                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10692                         for (arr_idx2 = 0;
10693                                         arr_idx2 <= reg_info->count2;
10694                                         arr_idx2++) {
10695                                 reg_offset = arr_idx * reg_info->stride1 +
10696                                         arr_idx2 * reg_info->stride2;
10697                                 reg_offset += reg_info->base_addr;
10698                                 ptr_data[reg_offset >> 2] =
10699                                         I40E_READ_REG(hw, reg_offset);
10700                         }
10701         }
10702
10703         return 0;
10704 }
10705
10706 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10707 {
10708         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10709
10710         /* Convert word count to byte count */
10711         return hw->nvm.sr_size << 1;
10712 }
10713
10714 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10715                            struct rte_dev_eeprom_info *eeprom)
10716 {
10717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10718         uint16_t *data = eeprom->data;
10719         uint16_t offset, length, cnt_words;
10720         int ret_code;
10721
10722         offset = eeprom->offset >> 1;
10723         length = eeprom->length >> 1;
10724         cnt_words = length;
10725
10726         if (offset > hw->nvm.sr_size ||
10727                 offset + length > hw->nvm.sr_size) {
10728                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10729                 return -EINVAL;
10730         }
10731
10732         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10733
10734         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10735         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10736                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10737                 return -EIO;
10738         }
10739
10740         return 0;
10741 }
10742
10743 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10744                                       struct ether_addr *mac_addr)
10745 {
10746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10747
10748         if (!is_valid_assigned_ether_addr(mac_addr)) {
10749                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10750                 return;
10751         }
10752
10753         /* Flags: 0x3 updates port address */
10754         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10755 }
10756
10757 static int
10758 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10759 {
10760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10761         struct rte_eth_dev_data *dev_data = pf->dev_data;
10762         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10763         int ret = 0;
10764
10765         /* check if mtu is within the allowed range */
10766         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10767                 return -EINVAL;
10768
10769         /* mtu setting is forbidden if port is start */
10770         if (dev_data->dev_started) {
10771                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10772                             dev_data->port_id);
10773                 return -EBUSY;
10774         }
10775
10776         if (frame_size > ETHER_MAX_LEN)
10777                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10778         else
10779                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10780
10781         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10782
10783         return ret;
10784 }
10785
10786 /* Restore ethertype filter */
10787 static void
10788 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10789 {
10790         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10791         struct i40e_ethertype_filter_list
10792                 *ethertype_list = &pf->ethertype.ethertype_list;
10793         struct i40e_ethertype_filter *f;
10794         struct i40e_control_filter_stats stats;
10795         uint16_t flags;
10796
10797         TAILQ_FOREACH(f, ethertype_list, rules) {
10798                 flags = 0;
10799                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10800                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10801                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10802                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10803                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10804
10805                 memset(&stats, 0, sizeof(stats));
10806                 i40e_aq_add_rem_control_packet_filter(hw,
10807                                             f->input.mac_addr.addr_bytes,
10808                                             f->input.ether_type,
10809                                             flags, pf->main_vsi->seid,
10810                                             f->queue, 1, &stats, NULL);
10811         }
10812         PMD_DRV_LOG(INFO, "Ethertype filter:"
10813                     " mac_etype_used = %u, etype_used = %u,"
10814                     " mac_etype_free = %u, etype_free = %u",
10815                     stats.mac_etype_used, stats.etype_used,
10816                     stats.mac_etype_free, stats.etype_free);
10817 }
10818
10819 /* Restore tunnel filter */
10820 static void
10821 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10822 {
10823         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10824         struct i40e_vsi *vsi;
10825         struct i40e_pf_vf *vf;
10826         struct i40e_tunnel_filter_list
10827                 *tunnel_list = &pf->tunnel.tunnel_list;
10828         struct i40e_tunnel_filter *f;
10829         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10830         bool big_buffer = 0;
10831
10832         TAILQ_FOREACH(f, tunnel_list, rules) {
10833                 if (!f->is_to_vf)
10834                         vsi = pf->main_vsi;
10835                 else {
10836                         vf = &pf->vfs[f->vf_id];
10837                         vsi = vf->vsi;
10838                 }
10839                 memset(&cld_filter, 0, sizeof(cld_filter));
10840                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10841                         (struct ether_addr *)&cld_filter.element.outer_mac);
10842                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10843                         (struct ether_addr *)&cld_filter.element.inner_mac);
10844                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10845                 cld_filter.element.flags = f->input.flags;
10846                 cld_filter.element.tenant_id = f->input.tenant_id;
10847                 cld_filter.element.queue_number = f->queue;
10848                 rte_memcpy(cld_filter.general_fields,
10849                            f->input.general_fields,
10850                            sizeof(f->input.general_fields));
10851
10852                 if (((f->input.flags &
10853                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10854                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10855                     ((f->input.flags &
10856                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10857                      I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10858                     ((f->input.flags &
10859                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10860                      I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10861                         big_buffer = 1;
10862
10863                 if (big_buffer)
10864                         i40e_aq_add_cloud_filters_big_buffer(hw,
10865                                              vsi->seid, &cld_filter, 1);
10866                 else
10867                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10868                                                   &cld_filter.element, 1);
10869         }
10870 }
10871
10872 static void
10873 i40e_filter_restore(struct i40e_pf *pf)
10874 {
10875         i40e_ethertype_filter_restore(pf);
10876         i40e_tunnel_filter_restore(pf);
10877         i40e_fdir_filter_restore(pf);
10878 }
10879
10880 static bool
10881 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10882 {
10883         if (strcmp(dev->device->driver->name, drv->driver.name))
10884                 return false;
10885
10886         return true;
10887 }
10888
10889 bool
10890 is_i40e_supported(struct rte_eth_dev *dev)
10891 {
10892         return is_device_supported(dev, &rte_i40e_pmd);
10893 }
10894
10895 /* Create a QinQ cloud filter
10896  *
10897  * The Fortville NIC has limited resources for tunnel filters,
10898  * so we can only reuse existing filters.
10899  *
10900  * In step 1 we define which Field Vector fields can be used for
10901  * filter types.
10902  * As we do not have the inner tag defined as a field,
10903  * we have to define it first, by reusing one of L1 entries.
10904  *
10905  * In step 2 we are replacing one of existing filter types with
10906  * a new one for QinQ.
10907  * As we reusing L1 and replacing L2, some of the default filter
10908  * types will disappear,which depends on L1 and L2 entries we reuse.
10909  *
10910  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10911  *
10912  * 1.   Create L1 filter of outer vlan (12b) which will be in use
10913  *              later when we define the cloud filter.
10914  *      a.      Valid_flags.replace_cloud = 0
10915  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
10916  *      c.      New_filter = 0x10
10917  *      d.      TR bit = 0xff (optional, not used here)
10918  *      e.      Buffer – 2 entries:
10919  *              i.      Byte 0 = 8 (outer vlan FV index).
10920  *                      Byte 1 = 0 (rsv)
10921  *                      Byte 2-3 = 0x0fff
10922  *              ii.     Byte 0 = 37 (inner vlan FV index).
10923  *                      Byte 1 =0 (rsv)
10924  *                      Byte 2-3 = 0x0fff
10925  *
10926  * Step 2:
10927  * 2.   Create cloud filter using two L1 filters entries: stag and
10928  *              new filter(outer vlan+ inner vlan)
10929  *      a.      Valid_flags.replace_cloud = 1
10930  *      b.      Old_filter = 1 (instead of outer IP)
10931  *      c.      New_filter = 0x10
10932  *      d.      Buffer – 2 entries:
10933  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
10934  *                      Byte 1-3 = 0 (rsv)
10935  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10936  *                      Byte 9-11 = 0 (rsv)
10937  */
10938 static int
10939 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10940 {
10941         int ret = -ENOTSUP;
10942         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
10943         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
10944         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10945
10946         /* Init */
10947         memset(&filter_replace, 0,
10948                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10949         memset(&filter_replace_buf, 0,
10950                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10951
10952         /* create L1 filter */
10953         filter_replace.old_filter_type =
10954                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10955         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10956         filter_replace.tr_bit = 0;
10957
10958         /* Prepare the buffer, 2 entries */
10959         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10960         filter_replace_buf.data[0] |=
10961                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10962         /* Field Vector 12b mask */
10963         filter_replace_buf.data[2] = 0xff;
10964         filter_replace_buf.data[3] = 0x0f;
10965         filter_replace_buf.data[4] =
10966                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10967         filter_replace_buf.data[4] |=
10968                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10969         /* Field Vector 12b mask */
10970         filter_replace_buf.data[6] = 0xff;
10971         filter_replace_buf.data[7] = 0x0f;
10972         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10973                         &filter_replace_buf);
10974         if (ret != I40E_SUCCESS)
10975                 return ret;
10976
10977         /* Apply the second L2 cloud filter */
10978         memset(&filter_replace, 0,
10979                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10980         memset(&filter_replace_buf, 0,
10981                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10982
10983         /* create L2 filter, input for L2 filter will be L1 filter  */
10984         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10985         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10986         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10987
10988         /* Prepare the buffer, 2 entries */
10989         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10990         filter_replace_buf.data[0] |=
10991                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10992         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10993         filter_replace_buf.data[4] |=
10994                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10995         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10996                         &filter_replace_buf);
10997         return ret;
10998 }
10999
11000 RTE_INIT(i40e_init_log);
11001 static void
11002 i40e_init_log(void)
11003 {
11004         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11005         if (i40e_logtype_init >= 0)
11006                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11007         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11008         if (i40e_logtype_driver >= 0)
11009                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11010 }