drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 661
 662 #ifndef I40E_GLQF_ORT
 663 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 664 #endif
 665 #ifndef I40E_GLQF_PIT
 666 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 667 #endif
 668 #ifndef I40E_GLQF_L3_MAP
 669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 670 #endif
 671
 672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 673 {
 674         /*
 675          * Initialize registers for parsing packet type of QinQ
 676          * This should be removed from code once proper
 677          * configuration API is added to avoid configuration conflicts
 678          * between ports of the same device.
 679          */
 680         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 681         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 682 }
 683
 684 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 685
 686 /*
 687  * Add a ethertype filter to drop all flow control frames transmitted
 688  * from VSIs.
 689 */
 690 static void
 691 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 692 {
 693         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 694         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 695                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 696                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 697         int ret;
 698
 699         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 700                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 701                                 pf->main_vsi_seid, 0,
 702                                 TRUE, NULL, NULL);
 703         if (ret)
 704                 PMD_INIT_LOG(ERR,
 705                         "Failed to add filter to drop flow control frames from VSIs.");
 706 }
 707
 708 static int
 709 floating_veb_list_handler(__rte_unused const char *key,
 710                           const char *floating_veb_value,
 711                           void *opaque)
 712 {
 713         int idx = 0;
 714         unsigned int count = 0;
 715         char *end = NULL;
 716         int min, max;
 717         bool *vf_floating_veb = opaque;
 718
 719         while (isblank(*floating_veb_value))
 720                 floating_veb_value++;
 721
 722         /* Reset floating VEB configuration for VFs */
 723         for (idx = 0; idx < I40E_MAX_VF; idx++)
 724                 vf_floating_veb[idx] = false;
 725
 726         min = I40E_MAX_VF;
 727         do {
 728                 while (isblank(*floating_veb_value))
 729                         floating_veb_value++;
 730                 if (*floating_veb_value == '\0')
 731                         return -1;
 732                 errno = 0;
 733                 idx = strtoul(floating_veb_value, &end, 10);
 734                 if (errno || end == NULL)
 735                         return -1;
 736                 while (isblank(*end))
 737                         end++;
 738                 if (*end == '-') {
 739                         min = idx;
 740                 } else if ((*end == ';') || (*end == '\0')) {
 741                         max = idx;
 742                         if (min == I40E_MAX_VF)
 743                                 min = idx;
 744                         if (max >= I40E_MAX_VF)
 745                                 max = I40E_MAX_VF - 1;
 746                         for (idx = min; idx <= max; idx++) {
 747                                 vf_floating_veb[idx] = true;
 748                                 count++;
 749                         }
 750                         min = I40E_MAX_VF;
 751                 } else {
 752                         return -1;
 753                 }
 754                 floating_veb_value = end + 1;
 755         } while (*end != '\0');
 756
 757         if (count == 0)
 758                 return -1;
 759
 760         return 0;
 761 }
 762
 763 static void
 764 config_vf_floating_veb(struct rte_devargs *devargs,
 765                        uint16_t floating_veb,
 766                        bool *vf_floating_veb)
 767 {
 768         struct rte_kvargs *kvlist;
 769         int i;
 770         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 771
 772         if (!floating_veb)
 773                 return;
 774         /* All the VFs attach to the floating VEB by default
 775          * when the floating VEB is enabled.
 776          */
 777         for (i = 0; i < I40E_MAX_VF; i++)
 778                 vf_floating_veb[i] = true;
 779
 780         if (devargs == NULL)
 781                 return;
 782
 783         kvlist = rte_kvargs_parse(devargs->args, NULL);
 784         if (kvlist == NULL)
 785                 return;
 786
 787         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 788                 rte_kvargs_free(kvlist);
 789                 return;
 790         }
 791         /* When the floating_veb_list parameter exists, all the VFs
 792          * will attach to the legacy VEB firstly, then configure VFs
 793          * to the floating VEB according to the floating_veb_list.
 794          */
 795         if (rte_kvargs_process(kvlist, floating_veb_list,
 796                                floating_veb_list_handler,
 797                                vf_floating_veb) < 0) {
 798                 rte_kvargs_free(kvlist);
 799                 return;
 800         }
 801         rte_kvargs_free(kvlist);
 802 }
 803
 804 static int
 805 i40e_check_floating_handler(__rte_unused const char *key,
 806                             const char *value,
 807                             __rte_unused void *opaque)
 808 {
 809         if (strcmp(value, "1"))
 810                 return -1;
 811
 812         return 0;
 813 }
 814
 815 static int
 816 is_floating_veb_supported(struct rte_devargs *devargs)
 817 {
 818         struct rte_kvargs *kvlist;
 819         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 820
 821         if (devargs == NULL)
 822                 return 0;
 823
 824         kvlist = rte_kvargs_parse(devargs->args, NULL);
 825         if (kvlist == NULL)
 826                 return 0;
 827
 828         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 829                 rte_kvargs_free(kvlist);
 830                 return 0;
 831         }
 832         /* Floating VEB is enabled when there's key-value:
 833          * enable_floating_veb=1
 834          */
 835         if (rte_kvargs_process(kvlist, floating_veb_key,
 836                                i40e_check_floating_handler, NULL) < 0) {
 837                 rte_kvargs_free(kvlist);
 838                 return 0;
 839         }
 840         rte_kvargs_free(kvlist);
 841
 842         return 1;
 843 }
 844
 845 static void
 846 config_floating_veb(struct rte_eth_dev *dev)
 847 {
 848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 849         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 851
 852         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 853
 854         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 855                 pf->floating_veb =
 856                         is_floating_veb_supported(pci_dev->device.devargs);
 857                 config_vf_floating_veb(pci_dev->device.devargs,
 858                                        pf->floating_veb,
 859                                        pf->floating_veb_list);
 860         } else {
 861                 pf->floating_veb = false;
 862         }
 863 }
 864
 865 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 866 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 867
 868 static int
 869 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 870 {
 871         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 872         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 873         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 874         int ret;
 875
 876         struct rte_hash_parameters ethertype_hash_params = {
 877                 .name = ethertype_hash_name,
 878                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 879                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 880                 .hash_func = rte_hash_crc,
 881                 .hash_func_init_val = 0,
 882                 .socket_id = rte_socket_id(),
 883         };
 884
 885         /* Initialize ethertype filter rule list and hash */
 886         TAILQ_INIT(&ethertype_rule->ethertype_list);
 887         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 888                  "ethertype_%s", dev->device->name);
 889         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 890         if (!ethertype_rule->hash_table) {
 891                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 892                 return -EINVAL;
 893         }
 894         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 895                                        sizeof(struct i40e_ethertype_filter *) *
 896                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 897                                        0);
 898         if (!ethertype_rule->hash_map) {
 899                 PMD_INIT_LOG(ERR,
 900                              "Failed to allocate memory for ethertype hash map!");
 901                 ret = -ENOMEM;
 902                 goto err_ethertype_hash_map_alloc;
 903         }
 904
 905         return 0;
 906
 907 err_ethertype_hash_map_alloc:
 908         rte_hash_free(ethertype_rule->hash_table);
 909
 910         return ret;
 911 }
 912
 913 static int
 914 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 915 {
 916         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 917         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 918         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 919         int ret;
 920
 921         struct rte_hash_parameters tunnel_hash_params = {
 922                 .name = tunnel_hash_name,
 923                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 924                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 925                 .hash_func = rte_hash_crc,
 926                 .hash_func_init_val = 0,
 927                 .socket_id = rte_socket_id(),
 928         };
 929
 930         /* Initialize tunnel filter rule list and hash */
 931         TAILQ_INIT(&tunnel_rule->tunnel_list);
 932         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 933                  "tunnel_%s", dev->device->name);
 934         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 935         if (!tunnel_rule->hash_table) {
 936                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 937                 return -EINVAL;
 938         }
 939         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 940                                     sizeof(struct i40e_tunnel_filter *) *
 941                                     I40E_MAX_TUNNEL_FILTER_NUM,
 942                                     0);
 943         if (!tunnel_rule->hash_map) {
 944                 PMD_INIT_LOG(ERR,
 945                              "Failed to allocate memory for tunnel hash map!");
 946                 ret = -ENOMEM;
 947                 goto err_tunnel_hash_map_alloc;
 948         }
 949
 950         return 0;
 951
 952 err_tunnel_hash_map_alloc:
 953         rte_hash_free(tunnel_rule->hash_table);
 954
 955         return ret;
 956 }
 957
 958 static int
 959 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 960 {
 961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 962         struct i40e_fdir_info *fdir_info = &pf->fdir;
 963         char fdir_hash_name[RTE_HASH_NAMESIZE];
 964         int ret;
 965
 966         struct rte_hash_parameters fdir_hash_params = {
 967                 .name = fdir_hash_name,
 968                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 969                 .key_len = sizeof(struct i40e_fdir_input),
 970                 .hash_func = rte_hash_crc,
 971                 .hash_func_init_val = 0,
 972                 .socket_id = rte_socket_id(),
 973         };
 974
 975         /* Initialize flow director filter rule list and hash */
 976         TAILQ_INIT(&fdir_info->fdir_list);
 977         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 978                  "fdir_%s", dev->device->name);
 979         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 980         if (!fdir_info->hash_table) {
 981                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 982                 return -EINVAL;
 983         }
 984         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
 985                                           sizeof(struct i40e_fdir_filter *) *
 986                                           I40E_MAX_FDIR_FILTER_NUM,
 987                                           0);
 988         if (!fdir_info->hash_map) {
 989                 PMD_INIT_LOG(ERR,
 990                              "Failed to allocate memory for fdir hash map!");
 991                 ret = -ENOMEM;
 992                 goto err_fdir_hash_map_alloc;
 993         }
 994         return 0;
 995
 996 err_fdir_hash_map_alloc:
 997         rte_hash_free(fdir_info->hash_table);
 998
 999         return ret;
1000 }
1001
1002 static void
1003 i40e_init_customized_info(struct i40e_pf *pf)
1004 {
1005         int i;
1006
1007         /* Initialize customized pctype */
1008         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1009                 pf->customized_pctype[i].index = i;
1010                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1011                 pf->customized_pctype[i].valid = false;
1012         }
1013
1014         pf->gtp_support = false;
1015 }
1016
1017 void
1018 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1019 {
1020         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1021         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1022         struct i40e_queue_regions *info = &pf->queue_region;
1023         uint16_t i;
1024
1025         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1026                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1027
1028         memset(info, 0, sizeof(struct i40e_queue_regions));
1029 }
1030
1031 static int
1032 eth_i40e_dev_init(struct rte_eth_dev *dev)
1033 {
1034         struct rte_pci_device *pci_dev;
1035         struct rte_intr_handle *intr_handle;
1036         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1037         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1038         struct i40e_vsi *vsi;
1039         int ret;
1040         uint32_t len;
1041         uint8_t aq_fail = 0;
1042
1043         PMD_INIT_FUNC_TRACE();
1044
1045         dev->dev_ops = &i40e_eth_dev_ops;
1046         dev->rx_pkt_burst = i40e_recv_pkts;
1047         dev->tx_pkt_burst = i40e_xmit_pkts;
1048         dev->tx_pkt_prepare = i40e_prep_pkts;
1049
1050         /* for secondary processes, we don't initialise any further as primary
1051          * has already done this work. Only check we don't need a different
1052          * RX function */
1053         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1054                 i40e_set_rx_function(dev);
1055                 i40e_set_tx_function(dev);
1056                 return 0;
1057         }
1058         i40e_set_default_ptype_table(dev);
1059         i40e_set_default_pctype_table(dev);
1060         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1061         intr_handle = &pci_dev->intr_handle;
1062
1063         rte_eth_copy_pci_info(dev, pci_dev);
1064
1065         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1066         pf->adapter->eth_dev = dev;
1067         pf->dev_data = dev->data;
1068
1069         hw->back = I40E_PF_TO_ADAPTER(pf);
1070         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1071         if (!hw->hw_addr) {
1072                 PMD_INIT_LOG(ERR,
1073                         "Hardware is not available, as address is NULL");
1074                 return -ENODEV;
1075         }
1076
1077         hw->vendor_id = pci_dev->id.vendor_id;
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1080         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1081         hw->bus.device = pci_dev->addr.devid;
1082         hw->bus.func = pci_dev->addr.function;
1083         hw->adapter_stopped = 0;
1084
1085         /* Make sure all is clean before doing PF reset */
1086         i40e_clear_hw(hw);
1087
1088         /* Initialize the hardware */
1089         i40e_hw_init(dev);
1090
1091         /* Reset here to make sure all is clean for each PF */
1092         ret = i40e_pf_reset(hw);
1093         if (ret) {
1094                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1095                 return ret;
1096         }
1097
1098         /* Initialize the shared code (base driver) */
1099         ret = i40e_init_shared_code(hw);
1100         if (ret) {
1101                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1102                 return ret;
1103         }
1104
1105         /*
1106          * To work around the NVM issue, initialize registers
1107          * for packet type of QinQ by software.
1108          * It should be removed once issues are fixed in NVM.
1109          */
1110         i40e_GLQF_reg_init(hw);
1111
1112         /* Initialize the input set for filters (hash and fd) to default value */
1113         i40e_filter_input_set_init(pf);
1114
1115         /* Initialize the parameters for adminq */
1116         i40e_init_adminq_parameter(hw);
1117         ret = i40e_init_adminq(hw);
1118         if (ret != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1120                 return -EIO;
1121         }
1122         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1123                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1124                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1125                      ((hw->nvm.version >> 12) & 0xf),
1126                      ((hw->nvm.version >> 4) & 0xff),
1127                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1128
1129         /* initialise the L3_MAP register */
1130         ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1131                                    0x00000028,  NULL);
1132         if (ret)
1133                 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1134
1135         /* Need the special FW version to support floating VEB */
1136         config_floating_veb(dev);
1137         /* Clear PXE mode */
1138         i40e_clear_pxe_mode(hw);
1139         i40e_dev_sync_phy_type(hw);
1140
1141         /*
1142          * On X710, performance number is far from the expectation on recent
1143          * firmware versions. The fix for this issue may not be integrated in
1144          * the following firmware version. So the workaround in software driver
1145          * is needed. It needs to modify the initial values of 3 internal only
1146          * registers. Note that the workaround can be removed when it is fixed
1147          * in firmware in the future.
1148          */
1149         i40e_configure_registers(hw);
1150
1151         /* Get hw capabilities */
1152         ret = i40e_get_cap(hw);
1153         if (ret != I40E_SUCCESS) {
1154                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1155                 goto err_get_capabilities;
1156         }
1157
1158         /* Initialize parameters for PF */
1159         ret = i40e_pf_parameter_init(dev);
1160         if (ret != 0) {
1161                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1162                 goto err_parameter_init;
1163         }
1164
1165         /* Initialize the queue management */
1166         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1167         if (ret < 0) {
1168                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1169                 goto err_qp_pool_init;
1170         }
1171         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1172                                 hw->func_caps.num_msix_vectors - 1);
1173         if (ret < 0) {
1174                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1175                 goto err_msix_pool_init;
1176         }
1177
1178         /* Initialize lan hmc */
1179         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1180                                 hw->func_caps.num_rx_qp, 0, 0);
1181         if (ret != I40E_SUCCESS) {
1182                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1183                 goto err_init_lan_hmc;
1184         }
1185
1186         /* Configure lan hmc */
1187         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1188         if (ret != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1190                 goto err_configure_lan_hmc;
1191         }
1192
1193         /* Get and check the mac address */
1194         i40e_get_mac_addr(hw, hw->mac.addr);
1195         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR, "mac address is not valid");
1197                 ret = -EIO;
1198                 goto err_get_mac_addr;
1199         }
1200         /* Copy the permanent MAC address */
1201         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1202                         (struct ether_addr *) hw->mac.perm_addr);
1203
1204         /* Disable flow control */
1205         hw->fc.requested_mode = I40E_FC_NONE;
1206         i40e_set_fc(hw, &aq_fail, TRUE);
1207
1208         /* Set the global registers with default ether type value */
1209         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1210         if (ret != I40E_SUCCESS) {
1211                 PMD_INIT_LOG(ERR,
1212                         "Failed to set the default outer VLAN ether type");
1213                 goto err_setup_pf_switch;
1214         }
1215
1216         /* PF setup, which includes VSI setup */
1217         ret = i40e_pf_setup(pf);
1218         if (ret) {
1219                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1220                 goto err_setup_pf_switch;
1221         }
1222
1223         /* reset all stats of the device, including pf and main vsi */
1224         i40e_dev_stats_reset(dev);
1225
1226         vsi = pf->main_vsi;
1227
1228         /* Disable double vlan by default */
1229         i40e_vsi_config_double_vlan(vsi, FALSE);
1230
1231         /* Disable S-TAG identification when floating_veb is disabled */
1232         if (!pf->floating_veb) {
1233                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1234                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1235                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1236                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1237                 }
1238         }
1239
1240         if (!vsi->max_macaddrs)
1241                 len = ETHER_ADDR_LEN;
1242         else
1243                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1244
1245         /* Should be after VSI initialized */
1246         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1247         if (!dev->data->mac_addrs) {
1248                 PMD_INIT_LOG(ERR,
1249                         "Failed to allocated memory for storing mac address");
1250                 goto err_mac_alloc;
1251         }
1252         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1253                                         &dev->data->mac_addrs[0]);
1254
1255         /* Init dcb to sw mode by default */
1256         ret = i40e_dcb_init_configure(dev, TRUE);
1257         if (ret != I40E_SUCCESS) {
1258                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1259                 pf->flags &= ~I40E_FLAG_DCB;
1260         }
1261         /* Update HW struct after DCB configuration */
1262         i40e_get_cap(hw);
1263
1264         /* initialize pf host driver to setup SRIOV resource if applicable */
1265         i40e_pf_host_init(dev);
1266
1267         /* register callback func to eal lib */
1268         rte_intr_callback_register(intr_handle,
1269                                    i40e_dev_interrupt_handler, dev);
1270
1271         /* configure and enable device interrupt */
1272         i40e_pf_config_irq0(hw, TRUE);
1273         i40e_pf_enable_irq0(hw);
1274
1275         /* enable uio intr after callback register */
1276         rte_intr_enable(intr_handle);
1277
1278         /* By default disable flexible payload in global configuration */
1279         i40e_flex_payload_reg_set_default(hw);
1280
1281         /*
1282          * Add an ethertype filter to drop all flow control frames transmitted
1283          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1284          * frames to wire.
1285          */
1286         i40e_add_tx_flow_control_drop_filter(pf);
1287
1288         /* Set the max frame size to 0x2600 by default,
1289          * in case other drivers changed the default value.
1290          */
1291         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1292
1293         /* initialize mirror rule list */
1294         TAILQ_INIT(&pf->mirror_list);
1295
1296         /* initialize Traffic Manager configuration */
1297         i40e_tm_conf_init(dev);
1298
1299         /* Initialize customized information */
1300         i40e_init_customized_info(pf);
1301
1302         ret = i40e_init_ethtype_filter_list(dev);
1303         if (ret < 0)
1304                 goto err_init_ethtype_filter_list;
1305         ret = i40e_init_tunnel_filter_list(dev);
1306         if (ret < 0)
1307                 goto err_init_tunnel_filter_list;
1308         ret = i40e_init_fdir_filter_list(dev);
1309         if (ret < 0)
1310                 goto err_init_fdir_filter_list;
1311
1312         /* initialize queue region configuration */
1313         i40e_init_queue_region_conf(dev);
1314
1315         return 0;
1316
1317 err_init_fdir_filter_list:
1318         rte_free(pf->tunnel.hash_table);
1319         rte_free(pf->tunnel.hash_map);
1320 err_init_tunnel_filter_list:
1321         rte_free(pf->ethertype.hash_table);
1322         rte_free(pf->ethertype.hash_map);
1323 err_init_ethtype_filter_list:
1324         rte_free(dev->data->mac_addrs);
1325 err_mac_alloc:
1326         i40e_vsi_release(pf->main_vsi);
1327 err_setup_pf_switch:
1328 err_get_mac_addr:
1329 err_configure_lan_hmc:
1330         (void)i40e_shutdown_lan_hmc(hw);
1331 err_init_lan_hmc:
1332         i40e_res_pool_destroy(&pf->msix_pool);
1333 err_msix_pool_init:
1334         i40e_res_pool_destroy(&pf->qp_pool);
1335 err_qp_pool_init:
1336 err_parameter_init:
1337 err_get_capabilities:
1338         (void)i40e_shutdown_adminq(hw);
1339
1340         return ret;
1341 }
1342
1343 static void
1344 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1345 {
1346         struct i40e_ethertype_filter *p_ethertype;
1347         struct i40e_ethertype_rule *ethertype_rule;
1348
1349         ethertype_rule = &pf->ethertype;
1350         /* Remove all ethertype filter rules and hash */
1351         if (ethertype_rule->hash_map)
1352                 rte_free(ethertype_rule->hash_map);
1353         if (ethertype_rule->hash_table)
1354                 rte_hash_free(ethertype_rule->hash_table);
1355
1356         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1357                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1358                              p_ethertype, rules);
1359                 rte_free(p_ethertype);
1360         }
1361 }
1362
1363 static void
1364 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1365 {
1366         struct i40e_tunnel_filter *p_tunnel;
1367         struct i40e_tunnel_rule *tunnel_rule;
1368
1369         tunnel_rule = &pf->tunnel;
1370         /* Remove all tunnel director rules and hash */
1371         if (tunnel_rule->hash_map)
1372                 rte_free(tunnel_rule->hash_map);
1373         if (tunnel_rule->hash_table)
1374                 rte_hash_free(tunnel_rule->hash_table);
1375
1376         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1377                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1378                 rte_free(p_tunnel);
1379         }
1380 }
1381
1382 static void
1383 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1384 {
1385         struct i40e_fdir_filter *p_fdir;
1386         struct i40e_fdir_info *fdir_info;
1387
1388         fdir_info = &pf->fdir;
1389         /* Remove all flow director rules and hash */
1390         if (fdir_info->hash_map)
1391                 rte_free(fdir_info->hash_map);
1392         if (fdir_info->hash_table)
1393                 rte_hash_free(fdir_info->hash_table);
1394
1395         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1396                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1397                 rte_free(p_fdir);
1398         }
1399 }
1400
1401 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1402 {
1403         /*
1404          * Disable by default flexible payload
1405          * for corresponding L2/L3/L4 layers.
1406          */
1407         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1408         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1409         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1410 }
1411
1412 static int
1413 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1414 {
1415         struct i40e_pf *pf;
1416         struct rte_pci_device *pci_dev;
1417         struct rte_intr_handle *intr_handle;
1418         struct i40e_hw *hw;
1419         struct i40e_filter_control_settings settings;
1420         struct rte_flow *p_flow;
1421         int ret;
1422         uint8_t aq_fail = 0;
1423
1424         PMD_INIT_FUNC_TRACE();
1425
1426         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1427                 return 0;
1428
1429         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1430         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1431         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1432         intr_handle = &pci_dev->intr_handle;
1433
1434         if (hw->adapter_stopped == 0)
1435                 i40e_dev_close(dev);
1436
1437         dev->dev_ops = NULL;
1438         dev->rx_pkt_burst = NULL;
1439         dev->tx_pkt_burst = NULL;
1440
1441         /* Clear PXE mode */
1442         i40e_clear_pxe_mode(hw);
1443
1444         /* Unconfigure filter control */
1445         memset(&settings, 0, sizeof(settings));
1446         ret = i40e_set_filter_control(hw, &settings);
1447         if (ret)
1448                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1449                                         ret);
1450
1451         /* Disable flow control */
1452         hw->fc.requested_mode = I40E_FC_NONE;
1453         i40e_set_fc(hw, &aq_fail, TRUE);
1454
1455         /* uninitialize pf host driver */
1456         i40e_pf_host_uninit(dev);
1457
1458         rte_free(dev->data->mac_addrs);
1459         dev->data->mac_addrs = NULL;
1460
1461         /* disable uio intr before callback unregister */
1462         rte_intr_disable(intr_handle);
1463
1464         /* register callback func to eal lib */
1465         rte_intr_callback_unregister(intr_handle,
1466                                      i40e_dev_interrupt_handler, dev);
1467
1468         i40e_rm_ethtype_filter_list(pf);
1469         i40e_rm_tunnel_filter_list(pf);
1470         i40e_rm_fdir_filter_list(pf);
1471
1472         /* Remove all flows */
1473         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1474                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1475                 rte_free(p_flow);
1476         }
1477
1478         /* Remove all Traffic Manager configuration */
1479         i40e_tm_conf_uninit(dev);
1480
1481         return 0;
1482 }
1483
1484 static int
1485 i40e_dev_configure(struct rte_eth_dev *dev)
1486 {
1487         struct i40e_adapter *ad =
1488                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1489         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1490         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1491         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1492         int i, ret;
1493
1494         ret = i40e_dev_sync_phy_type(hw);
1495         if (ret)
1496                 return ret;
1497
1498         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1499          * bulk allocation or vector Rx preconditions we will reset it.
1500          */
1501         ad->rx_bulk_alloc_allowed = true;
1502         ad->rx_vec_allowed = true;
1503         ad->tx_simple_allowed = true;
1504         ad->tx_vec_allowed = true;
1505
1506         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1507                 ret = i40e_fdir_setup(pf);
1508                 if (ret != I40E_SUCCESS) {
1509                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1510                         return -ENOTSUP;
1511                 }
1512                 ret = i40e_fdir_configure(dev);
1513                 if (ret < 0) {
1514                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1515                         goto err;
1516                 }
1517         } else
1518                 i40e_fdir_teardown(pf);
1519
1520         ret = i40e_dev_init_vlan(dev);
1521         if (ret < 0)
1522                 goto err;
1523
1524         /* VMDQ setup.
1525          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1526          *  RSS setting have different requirements.
1527          *  General PMD driver call sequence are NIC init, configure,
1528          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1529          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1530          *  applicable. So, VMDQ setting has to be done before
1531          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1532          *  For RSS setting, it will try to calculate actual configured RX queue
1533          *  number, which will be available after rx_queue_setup(). dev_start()
1534          *  function is good to place RSS setup.
1535          */
1536         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1537                 ret = i40e_vmdq_setup(dev);
1538                 if (ret)
1539                         goto err;
1540         }
1541
1542         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1543                 ret = i40e_dcb_setup(dev);
1544                 if (ret) {
1545                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1546                         goto err_dcb;
1547                 }
1548         }
1549
1550         TAILQ_INIT(&pf->flow_list);
1551
1552         return 0;
1553
1554 err_dcb:
1555         /* need to release vmdq resource if exists */
1556         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1557                 i40e_vsi_release(pf->vmdq[i].vsi);
1558                 pf->vmdq[i].vsi = NULL;
1559         }
1560         rte_free(pf->vmdq);
1561         pf->vmdq = NULL;
1562 err:
1563         /* need to release fdir resource if exists */
1564         i40e_fdir_teardown(pf);
1565         return ret;
1566 }
1567
1568 void
1569 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1570 {
1571         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1574         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1575         uint16_t msix_vect = vsi->msix_intr;
1576         uint16_t i;
1577
1578         for (i = 0; i < vsi->nb_qps; i++) {
1579                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1580                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1581                 rte_wmb();
1582         }
1583
1584         if (vsi->type != I40E_VSI_SRIOV) {
1585                 if (!rte_intr_allow_others(intr_handle)) {
1586                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1587                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1588                         I40E_WRITE_REG(hw,
1589                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1590                                        0);
1591                 } else {
1592                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1593                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1596                                                        msix_vect - 1), 0);
1597                 }
1598         } else {
1599                 uint32_t reg;
1600                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1601                         vsi->user_param + (msix_vect - 1);
1602
1603                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1604                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1605         }
1606         I40E_WRITE_FLUSH(hw);
1607 }
1608
1609 static void
1610 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1611                        int base_queue, int nb_queue,
1612                        uint16_t itr_idx)
1613 {
1614         int i;
1615         uint32_t val;
1616         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1617
1618         /* Bind all RX queues to allocated MSIX interrupt */
1619         for (i = 0; i < nb_queue; i++) {
1620                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1621                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1622                         ((base_queue + i + 1) <<
1623                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1624                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1625                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1626
1627                 if (i == nb_queue - 1)
1628                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1629                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1630         }
1631
1632         /* Write first RX queue to Link list register as the head element */
1633         if (vsi->type != I40E_VSI_SRIOV) {
1634                 uint16_t interval =
1635                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1639                                        (base_queue <<
1640                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1641                                        (0x0 <<
1642                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1643                         I40E_WRITE_REG(hw,
1644                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1645                                        interval);
1646                 } else {
1647                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1648                                        (base_queue <<
1649                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1652                         I40E_WRITE_REG(hw,
1653                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1654                                                        msix_vect - 1),
1655                                        interval);
1656                 }
1657         } else {
1658                 uint32_t reg;
1659
1660                 if (msix_vect == I40E_MISC_VEC_ID) {
1661                         I40E_WRITE_REG(hw,
1662                                        I40E_VPINT_LNKLST0(vsi->user_param),
1663                                        (base_queue <<
1664                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1665                                        (0x0 <<
1666                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1667                 } else {
1668                         /* num_msix_vectors_vf needs to minus irq0 */
1669                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1670                                 vsi->user_param + (msix_vect - 1);
1671
1672                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1673                                        (base_queue <<
1674                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1675                                        (0x0 <<
1676                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677                 }
1678         }
1679
1680         I40E_WRITE_FLUSH(hw);
1681 }
1682
1683 void
1684 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1685 {
1686         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1687         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1690         uint16_t msix_vect = vsi->msix_intr;
1691         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1692         uint16_t queue_idx = 0;
1693         int record = 0;
1694         uint32_t val;
1695         int i;
1696
1697         for (i = 0; i < vsi->nb_qps; i++) {
1698                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1699                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1700         }
1701
1702         /* INTENA flag is not auto-cleared for interrupt */
1703         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1704         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1705                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1706                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1707         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1708
1709         /* VF bind interrupt */
1710         if (vsi->type == I40E_VSI_SRIOV) {
1711                 __vsi_queues_bind_intr(vsi, msix_vect,
1712                                        vsi->base_queue, vsi->nb_qps,
1713                                        itr_idx);
1714                 return;
1715         }
1716
1717         /* PF & VMDq bind interrupt */
1718         if (rte_intr_dp_is_en(intr_handle)) {
1719                 if (vsi->type == I40E_VSI_MAIN) {
1720                         queue_idx = 0;
1721                         record = 1;
1722                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1723                         struct i40e_vsi *main_vsi =
1724                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1725                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1726                         record = 1;
1727                 }
1728         }
1729
1730         for (i = 0; i < vsi->nb_used_qps; i++) {
1731                 if (nb_msix <= 1) {
1732                         if (!rte_intr_allow_others(intr_handle))
1733                                 /* allow to share MISC_VEC_ID */
1734                                 msix_vect = I40E_MISC_VEC_ID;
1735
1736                         /* no enough msix_vect, map all to one */
1737                         __vsi_queues_bind_intr(vsi, msix_vect,
1738                                                vsi->base_queue + i,
1739                                                vsi->nb_used_qps - i,
1740                                                itr_idx);
1741                         for (; !!record && i < vsi->nb_used_qps; i++)
1742                                 intr_handle->intr_vec[queue_idx + i] =
1743                                         msix_vect;
1744                         break;
1745                 }
1746                 /* 1:1 queue/msix_vect mapping */
1747                 __vsi_queues_bind_intr(vsi, msix_vect,
1748                                        vsi->base_queue + i, 1,
1749                                        itr_idx);
1750                 if (!!record)
1751                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1752
1753                 msix_vect++;
1754                 nb_msix--;
1755         }
1756 }
1757
1758 static void
1759 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1760 {
1761         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1762         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1763         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1764         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1765         uint16_t interval = i40e_calc_itr_interval(\
1766                 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1767         uint16_t msix_intr, i;
1768
1769         if (rte_intr_allow_others(intr_handle))
1770                 for (i = 0; i < vsi->nb_msix; i++) {
1771                         msix_intr = vsi->msix_intr + i;
1772                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1773                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1774                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1775                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1776                                 (interval <<
1777                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1778                 }
1779         else
1780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1781                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1782                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1783                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1784                                (interval <<
1785                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1786
1787         I40E_WRITE_FLUSH(hw);
1788 }
1789
1790 static void
1791 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1792 {
1793         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797         uint16_t msix_intr, i;
1798
1799         if (rte_intr_allow_others(intr_handle))
1800                 for (i = 0; i < vsi->nb_msix; i++) {
1801                         msix_intr = vsi->msix_intr + i;
1802                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1803                                        0);
1804                 }
1805         else
1806                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1807
1808         I40E_WRITE_FLUSH(hw);
1809 }
1810
1811 static inline uint8_t
1812 i40e_parse_link_speeds(uint16_t link_speeds)
1813 {
1814         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1815
1816         if (link_speeds & ETH_LINK_SPEED_40G)
1817                 link_speed |= I40E_LINK_SPEED_40GB;
1818         if (link_speeds & ETH_LINK_SPEED_25G)
1819                 link_speed |= I40E_LINK_SPEED_25GB;
1820         if (link_speeds & ETH_LINK_SPEED_20G)
1821                 link_speed |= I40E_LINK_SPEED_20GB;
1822         if (link_speeds & ETH_LINK_SPEED_10G)
1823                 link_speed |= I40E_LINK_SPEED_10GB;
1824         if (link_speeds & ETH_LINK_SPEED_1G)
1825                 link_speed |= I40E_LINK_SPEED_1GB;
1826         if (link_speeds & ETH_LINK_SPEED_100M)
1827                 link_speed |= I40E_LINK_SPEED_100MB;
1828
1829         return link_speed;
1830 }
1831
1832 static int
1833 i40e_phy_conf_link(struct i40e_hw *hw,
1834                    uint8_t abilities,
1835                    uint8_t force_speed,
1836                    bool is_up)
1837 {
1838         enum i40e_status_code status;
1839         struct i40e_aq_get_phy_abilities_resp phy_ab;
1840         struct i40e_aq_set_phy_config phy_conf;
1841         enum i40e_aq_phy_type cnt;
1842         uint32_t phy_type_mask = 0;
1843
1844         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1845                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1846                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1847                         I40E_AQ_PHY_FLAG_LOW_POWER;
1848         const uint8_t advt = I40E_LINK_SPEED_40GB |
1849                         I40E_LINK_SPEED_25GB |
1850                         I40E_LINK_SPEED_10GB |
1851                         I40E_LINK_SPEED_1GB |
1852                         I40E_LINK_SPEED_100MB;
1853         int ret = -ENOTSUP;
1854
1855
1856         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1857                                               NULL);
1858         if (status)
1859                 return ret;
1860
1861         /* If link already up, no need to set up again */
1862         if (is_up && phy_ab.phy_type != 0)
1863                 return I40E_SUCCESS;
1864
1865         memset(&phy_conf, 0, sizeof(phy_conf));
1866
1867         /* bits 0-2 use the values from get_phy_abilities_resp */
1868         abilities &= ~mask;
1869         abilities |= phy_ab.abilities & mask;
1870
1871         /* update ablities and speed */
1872         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1873                 phy_conf.link_speed = advt;
1874         else
1875                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1876
1877         phy_conf.abilities = abilities;
1878
1879
1880
1881         /* To enable link, phy_type mask needs to include each type */
1882         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1883                 phy_type_mask |= 1 << cnt;
1884
1885         /* use get_phy_abilities_resp value for the rest */
1886         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1887         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1888                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1889                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1890         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1891         phy_conf.eee_capability = phy_ab.eee_capability;
1892         phy_conf.eeer = phy_ab.eeer_val;
1893         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1894
1895         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1896                     phy_ab.abilities, phy_ab.link_speed);
1897         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1898                     phy_conf.abilities, phy_conf.link_speed);
1899
1900         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1901         if (status)
1902                 return ret;
1903
1904         return I40E_SUCCESS;
1905 }
1906
1907 static int
1908 i40e_apply_link_speed(struct rte_eth_dev *dev)
1909 {
1910         uint8_t speed;
1911         uint8_t abilities = 0;
1912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         struct rte_eth_conf *conf = &dev->data->dev_conf;
1914
1915         speed = i40e_parse_link_speeds(conf->link_speeds);
1916         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1917         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1918                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1919         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1920
1921         return i40e_phy_conf_link(hw, abilities, speed, true);
1922 }
1923
1924 static int
1925 i40e_dev_start(struct rte_eth_dev *dev)
1926 {
1927         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_vsi *main_vsi = pf->main_vsi;
1930         int ret, i;
1931         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1932         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1933         uint32_t intr_vector = 0;
1934         struct i40e_vsi *vsi;
1935
1936         hw->adapter_stopped = 0;
1937
1938         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1939                 PMD_INIT_LOG(ERR,
1940                 "Invalid link_speeds for port %u, autonegotiation disabled",
1941                               dev->data->port_id);
1942                 return -EINVAL;
1943         }
1944
1945         rte_intr_disable(intr_handle);
1946
1947         if ((rte_intr_cap_multiple(intr_handle) ||
1948              !RTE_ETH_DEV_SRIOV(dev).active) &&
1949             dev->data->dev_conf.intr_conf.rxq != 0) {
1950                 intr_vector = dev->data->nb_rx_queues;
1951                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1952                 if (ret)
1953                         return ret;
1954         }
1955
1956         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1957                 intr_handle->intr_vec =
1958                         rte_zmalloc("intr_vec",
1959                                     dev->data->nb_rx_queues * sizeof(int),
1960                                     0);
1961                 if (!intr_handle->intr_vec) {
1962                         PMD_INIT_LOG(ERR,
1963                                 "Failed to allocate %d rx_queues intr_vec",
1964                                 dev->data->nb_rx_queues);
1965                         return -ENOMEM;
1966                 }
1967         }
1968
1969         /* Initialize VSI */
1970         ret = i40e_dev_rxtx_init(pf);
1971         if (ret != I40E_SUCCESS) {
1972                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1973                 goto err_up;
1974         }
1975
1976         /* Map queues with MSIX interrupt */
1977         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1978                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1979         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1980         i40e_vsi_enable_queues_intr(main_vsi);
1981
1982         /* Map VMDQ VSI queues with MSIX interrupt */
1983         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1984                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1985                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1986                                           I40E_ITR_INDEX_DEFAULT);
1987                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1988         }
1989
1990         /* enable FDIR MSIX interrupt */
1991         if (pf->fdir.fdir_vsi) {
1992                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1993                                           I40E_ITR_INDEX_NONE);
1994                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1995         }
1996
1997         /* Enable all queues which have been configured */
1998         ret = i40e_dev_switch_queues(pf, TRUE);
1999         if (ret != I40E_SUCCESS) {
2000                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2001                 goto err_up;
2002         }
2003
2004         /* Enable receiving broadcast packets */
2005         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2006         if (ret != I40E_SUCCESS)
2007                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2008
2009         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2011                                                 true, NULL);
2012                 if (ret != I40E_SUCCESS)
2013                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2014         }
2015
2016         /* Enable the VLAN promiscuous mode. */
2017         if (pf->vfs) {
2018                 for (i = 0; i < pf->vf_num; i++) {
2019                         vsi = pf->vfs[i].vsi;
2020                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2021                                                      true, NULL);
2022                 }
2023         }
2024
2025         /* Enable mac loopback mode */
2026         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2027             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2028                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2029                 if (ret != I40E_SUCCESS) {
2030                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2031                         goto err_up;
2032                 }
2033         }
2034
2035         /* Apply link configure */
2036         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2037                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2038                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2039                                 ETH_LINK_SPEED_40G)) {
2040                 PMD_DRV_LOG(ERR, "Invalid link setting");
2041                 goto err_up;
2042         }
2043         ret = i40e_apply_link_speed(dev);
2044         if (I40E_SUCCESS != ret) {
2045                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2046                 goto err_up;
2047         }
2048
2049         if (!rte_intr_allow_others(intr_handle)) {
2050                 rte_intr_callback_unregister(intr_handle,
2051                                              i40e_dev_interrupt_handler,
2052                                              (void *)dev);
2053                 /* configure and enable device interrupt */
2054                 i40e_pf_config_irq0(hw, FALSE);
2055                 i40e_pf_enable_irq0(hw);
2056
2057                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2058                         PMD_INIT_LOG(INFO,
2059                                 "lsc won't enable because of no intr multiplex");
2060         } else {
2061                 ret = i40e_aq_set_phy_int_mask(hw,
2062                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2063                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2064                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2065                 if (ret != I40E_SUCCESS)
2066                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2067
2068                 /* Call get_link_info aq commond to enable/disable LSE */
2069                 i40e_dev_link_update(dev, 0);
2070         }
2071
2072         /* enable uio intr after callback register */
2073         rte_intr_enable(intr_handle);
2074
2075         i40e_filter_restore(pf);
2076
2077         if (pf->tm_conf.root && !pf->tm_conf.committed)
2078                 PMD_DRV_LOG(WARNING,
2079                             "please call hierarchy_commit() "
2080                             "before starting the port");
2081
2082         return I40E_SUCCESS;
2083
2084 err_up:
2085         i40e_dev_switch_queues(pf, FALSE);
2086         i40e_dev_clear_queues(dev);
2087
2088         return ret;
2089 }
2090
2091 static void
2092 i40e_dev_stop(struct rte_eth_dev *dev)
2093 {
2094         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2095         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2096         struct i40e_vsi *main_vsi = pf->main_vsi;
2097         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099         int i;
2100
2101         if (hw->adapter_stopped == 1)
2102                 return;
2103         /* Disable all queues */
2104         i40e_dev_switch_queues(pf, FALSE);
2105
2106         /* un-map queues with interrupt registers */
2107         i40e_vsi_disable_queues_intr(main_vsi);
2108         i40e_vsi_queues_unbind_intr(main_vsi);
2109
2110         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2111                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2112                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2113         }
2114
2115         if (pf->fdir.fdir_vsi) {
2116                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2117                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2118         }
2119         /* Clear all queues and release memory */
2120         i40e_dev_clear_queues(dev);
2121
2122         /* Set link down */
2123         i40e_dev_set_link_down(dev);
2124
2125         if (!rte_intr_allow_others(intr_handle))
2126                 /* resume to the default handler */
2127                 rte_intr_callback_register(intr_handle,
2128                                            i40e_dev_interrupt_handler,
2129                                            (void *)dev);
2130
2131         /* Clean datapath event and queue/vec mapping */
2132         rte_intr_efd_disable(intr_handle);
2133         if (intr_handle->intr_vec) {
2134                 rte_free(intr_handle->intr_vec);
2135                 intr_handle->intr_vec = NULL;
2136         }
2137
2138         /* reset hierarchy commit */
2139         pf->tm_conf.committed = false;
2140
2141         /* Remove all the queue region configuration */
2142         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2143
2144         hw->adapter_stopped = 1;
2145 }
2146
2147 static void
2148 i40e_dev_close(struct rte_eth_dev *dev)
2149 {
2150         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2152         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2153         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2154         struct i40e_mirror_rule *p_mirror;
2155         uint32_t reg;
2156         int i;
2157         int ret;
2158
2159         PMD_INIT_FUNC_TRACE();
2160
2161         i40e_dev_stop(dev);
2162
2163         /* Remove all mirror rules */
2164         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2165                 ret = i40e_aq_del_mirror_rule(hw,
2166                                               pf->main_vsi->veb->seid,
2167                                               p_mirror->rule_type,
2168                                               p_mirror->entries,
2169                                               p_mirror->num_entries,
2170                                               p_mirror->id);
2171                 if (ret < 0)
2172                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2173                                     "status = %d, aq_err = %d.", ret,
2174                                     hw->aq.asq_last_status);
2175
2176                 /* remove mirror software resource anyway */
2177                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2178                 rte_free(p_mirror);
2179                 pf->nb_mirror_rule--;
2180         }
2181
2182         i40e_dev_free_queues(dev);
2183
2184         /* Disable interrupt */
2185         i40e_pf_disable_irq0(hw);
2186         rte_intr_disable(intr_handle);
2187
2188         /* shutdown and destroy the HMC */
2189         i40e_shutdown_lan_hmc(hw);
2190
2191         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2192                 i40e_vsi_release(pf->vmdq[i].vsi);
2193                 pf->vmdq[i].vsi = NULL;
2194         }
2195         rte_free(pf->vmdq);
2196         pf->vmdq = NULL;
2197
2198         /* release all the existing VSIs and VEBs */
2199         i40e_fdir_teardown(pf);
2200         i40e_vsi_release(pf->main_vsi);
2201
2202         /* shutdown the adminq */
2203         i40e_aq_queue_shutdown(hw, true);
2204         i40e_shutdown_adminq(hw);
2205
2206         i40e_res_pool_destroy(&pf->qp_pool);
2207         i40e_res_pool_destroy(&pf->msix_pool);
2208
2209         /* Disable flexible payload in global configuration */
2210         i40e_flex_payload_reg_set_default(hw);
2211
2212         /* force a PF reset to clean anything leftover */
2213         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2214         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2215                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2216         I40E_WRITE_FLUSH(hw);
2217 }
2218
2219 /*
2220  * Reset PF device only to re-initialize resources in PMD layer
2221  */
2222 static int
2223 i40e_dev_reset(struct rte_eth_dev *dev)
2224 {
2225         int ret;
2226
2227         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2228          * its VF to make them align with it. The detailed notification
2229          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2230          * To avoid unexpected behavior in VF, currently reset of PF with
2231          * SR-IOV activation is not supported. It might be supported later.
2232          */
2233         if (dev->data->sriov.active)
2234                 return -ENOTSUP;
2235
2236         ret = eth_i40e_dev_uninit(dev);
2237         if (ret)
2238                 return ret;
2239
2240         ret = eth_i40e_dev_init(dev);
2241
2242         return ret;
2243 }
2244
2245 static void
2246 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2247 {
2248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct i40e_vsi *vsi = pf->main_vsi;
2251         int status;
2252
2253         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2254                                                      true, NULL, true);
2255         if (status != I40E_SUCCESS)
2256                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2257
2258         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2259                                                         TRUE, NULL);
2260         if (status != I40E_SUCCESS)
2261                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2262
2263 }
2264
2265 static void
2266 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2267 {
2268         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2269         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2270         struct i40e_vsi *vsi = pf->main_vsi;
2271         int status;
2272
2273         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2274                                                      false, NULL, true);
2275         if (status != I40E_SUCCESS)
2276                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2277
2278         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2279                                                         false, NULL);
2280         if (status != I40E_SUCCESS)
2281                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2282 }
2283
2284 static void
2285 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2286 {
2287         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         struct i40e_vsi *vsi = pf->main_vsi;
2290         int ret;
2291
2292         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2293         if (ret != I40E_SUCCESS)
2294                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2295 }
2296
2297 static void
2298 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2299 {
2300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302         struct i40e_vsi *vsi = pf->main_vsi;
2303         int ret;
2304
2305         if (dev->data->promiscuous == 1)
2306                 return; /* must remain in all_multicast mode */
2307
2308         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2309                                 vsi->seid, FALSE, NULL);
2310         if (ret != I40E_SUCCESS)
2311                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2312 }
2313
2314 /*
2315  * Set device link up.
2316  */
2317 static int
2318 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2319 {
2320         /* re-apply link speed setting */
2321         return i40e_apply_link_speed(dev);
2322 }
2323
2324 /*
2325  * Set device link down.
2326  */
2327 static int
2328 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2329 {
2330         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2331         uint8_t abilities = 0;
2332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333
2334         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2335         return i40e_phy_conf_link(hw, abilities, speed, false);
2336 }
2337
2338 int
2339 i40e_dev_link_update(struct rte_eth_dev *dev,
2340                      int wait_to_complete)
2341 {
2342 #define CHECK_INTERVAL 100  /* 100ms */
2343 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2345         struct i40e_link_status link_status;
2346         struct rte_eth_link link, old;
2347         int status;
2348         unsigned rep_cnt = MAX_REPEAT_TIME;
2349         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2350
2351         memset(&link, 0, sizeof(link));
2352         memset(&old, 0, sizeof(old));
2353         memset(&link_status, 0, sizeof(link_status));
2354         rte_i40e_dev_atomic_read_link_status(dev, &old);
2355
2356         do {
2357                 /* Get link status information from hardware */
2358                 status = i40e_aq_get_link_info(hw, enable_lse,
2359                                                 &link_status, NULL);
2360                 if (status != I40E_SUCCESS) {
2361                         link.link_speed = ETH_SPEED_NUM_100M;
2362                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2363                         PMD_DRV_LOG(ERR, "Failed to get link info");
2364                         goto out;
2365                 }
2366
2367                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2368                 if (!wait_to_complete || link.link_status)
2369                         break;
2370
2371                 rte_delay_ms(CHECK_INTERVAL);
2372         } while (--rep_cnt);
2373
2374         if (!link.link_status)
2375                 goto out;
2376
2377         /* i40e uses full duplex only */
2378         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2379
2380         /* Parse the link status */
2381         switch (link_status.link_speed) {
2382         case I40E_LINK_SPEED_100MB:
2383                 link.link_speed = ETH_SPEED_NUM_100M;
2384                 break;
2385         case I40E_LINK_SPEED_1GB:
2386                 link.link_speed = ETH_SPEED_NUM_1G;
2387                 break;
2388         case I40E_LINK_SPEED_10GB:
2389                 link.link_speed = ETH_SPEED_NUM_10G;
2390                 break;
2391         case I40E_LINK_SPEED_20GB:
2392                 link.link_speed = ETH_SPEED_NUM_20G;
2393                 break;
2394         case I40E_LINK_SPEED_25GB:
2395                 link.link_speed = ETH_SPEED_NUM_25G;
2396                 break;
2397         case I40E_LINK_SPEED_40GB:
2398                 link.link_speed = ETH_SPEED_NUM_40G;
2399                 break;
2400         default:
2401                 link.link_speed = ETH_SPEED_NUM_100M;
2402                 break;
2403         }
2404
2405         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2406                         ETH_LINK_SPEED_FIXED);
2407
2408 out:
2409         rte_i40e_dev_atomic_write_link_status(dev, &link);
2410         if (link.link_status == old.link_status)
2411                 return -1;
2412
2413         i40e_notify_all_vfs_link_status(dev);
2414
2415         return 0;
2416 }
2417
2418 /* Get all the statistics of a VSI */
2419 void
2420 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2421 {
2422         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2423         struct i40e_eth_stats *nes = &vsi->eth_stats;
2424         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2425         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2426
2427         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2428                             vsi->offset_loaded, &oes->rx_bytes,
2429                             &nes->rx_bytes);
2430         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2431                             vsi->offset_loaded, &oes->rx_unicast,
2432                             &nes->rx_unicast);
2433         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2434                             vsi->offset_loaded, &oes->rx_multicast,
2435                             &nes->rx_multicast);
2436         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2437                             vsi->offset_loaded, &oes->rx_broadcast,
2438                             &nes->rx_broadcast);
2439         /* exclude CRC bytes */
2440         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2441                 nes->rx_broadcast) * ETHER_CRC_LEN;
2442
2443         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2444                             &oes->rx_discards, &nes->rx_discards);
2445         /* GLV_REPC not supported */
2446         /* GLV_RMPC not supported */
2447         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2448                             &oes->rx_unknown_protocol,
2449                             &nes->rx_unknown_protocol);
2450         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2451                             vsi->offset_loaded, &oes->tx_bytes,
2452                             &nes->tx_bytes);
2453         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2454                             vsi->offset_loaded, &oes->tx_unicast,
2455                             &nes->tx_unicast);
2456         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2457                             vsi->offset_loaded, &oes->tx_multicast,
2458                             &nes->tx_multicast);
2459         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2460                             vsi->offset_loaded,  &oes->tx_broadcast,
2461                             &nes->tx_broadcast);
2462         /* GLV_TDPC not supported */
2463         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2464                             &oes->tx_errors, &nes->tx_errors);
2465         vsi->offset_loaded = true;
2466
2467         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2468                     vsi->vsi_id);
2469         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2470         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2471         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2472         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2473         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2474         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2475                     nes->rx_unknown_protocol);
2476         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2477         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2478         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2479         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2480         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2481         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2482         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2483                     vsi->vsi_id);
2484 }
2485
2486 static void
2487 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2488 {
2489         unsigned int i;
2490         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2491         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2492
2493         /* Get rx/tx bytes of internal transfer packets */
2494         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2495                         I40E_GLV_GORCL(hw->port),
2496                         pf->offset_loaded,
2497                         &pf->internal_stats_offset.rx_bytes,
2498                         &pf->internal_stats.rx_bytes);
2499
2500         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2501                         I40E_GLV_GOTCL(hw->port),
2502                         pf->offset_loaded,
2503                         &pf->internal_stats_offset.tx_bytes,
2504                         &pf->internal_stats.tx_bytes);
2505         /* Get total internal rx packet count */
2506         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2507                             I40E_GLV_UPRCL(hw->port),
2508                             pf->offset_loaded,
2509                             &pf->internal_stats_offset.rx_unicast,
2510                             &pf->internal_stats.rx_unicast);
2511         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2512                             I40E_GLV_MPRCL(hw->port),
2513                             pf->offset_loaded,
2514                             &pf->internal_stats_offset.rx_multicast,
2515                             &pf->internal_stats.rx_multicast);
2516         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2517                             I40E_GLV_BPRCL(hw->port),
2518                             pf->offset_loaded,
2519                             &pf->internal_stats_offset.rx_broadcast,
2520                             &pf->internal_stats.rx_broadcast);
2521
2522         /* exclude CRC size */
2523         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2524                 pf->internal_stats.rx_multicast +
2525                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2526
2527         /* Get statistics of struct i40e_eth_stats */
2528         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2529                             I40E_GLPRT_GORCL(hw->port),
2530                             pf->offset_loaded, &os->eth.rx_bytes,
2531                             &ns->eth.rx_bytes);
2532         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2533                             I40E_GLPRT_UPRCL(hw->port),
2534                             pf->offset_loaded, &os->eth.rx_unicast,
2535                             &ns->eth.rx_unicast);
2536         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2537                             I40E_GLPRT_MPRCL(hw->port),
2538                             pf->offset_loaded, &os->eth.rx_multicast,
2539                             &ns->eth.rx_multicast);
2540         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2541                             I40E_GLPRT_BPRCL(hw->port),
2542                             pf->offset_loaded, &os->eth.rx_broadcast,
2543                             &ns->eth.rx_broadcast);
2544         /* Workaround: CRC size should not be included in byte statistics,
2545          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2546          */
2547         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2548                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2549
2550         /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2551          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2552          * value.
2553          */
2554         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2555                 ns->eth.rx_bytes = 0;
2556         /* exlude internal rx bytes */
2557         else
2558                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2559
2560         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2561                             pf->offset_loaded, &os->eth.rx_discards,
2562                             &ns->eth.rx_discards);
2563         /* GLPRT_REPC not supported */
2564         /* GLPRT_RMPC not supported */
2565         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2566                             pf->offset_loaded,
2567                             &os->eth.rx_unknown_protocol,
2568                             &ns->eth.rx_unknown_protocol);
2569         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2570                             I40E_GLPRT_GOTCL(hw->port),
2571                             pf->offset_loaded, &os->eth.tx_bytes,
2572                             &ns->eth.tx_bytes);
2573         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2574                             I40E_GLPRT_UPTCL(hw->port),
2575                             pf->offset_loaded, &os->eth.tx_unicast,
2576                             &ns->eth.tx_unicast);
2577         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2578                             I40E_GLPRT_MPTCL(hw->port),
2579                             pf->offset_loaded, &os->eth.tx_multicast,
2580                             &ns->eth.tx_multicast);
2581         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2582                             I40E_GLPRT_BPTCL(hw->port),
2583                             pf->offset_loaded, &os->eth.tx_broadcast,
2584                             &ns->eth.tx_broadcast);
2585         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2586                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2587
2588         /* exclude internal tx bytes */
2589         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2590                 ns->eth.tx_bytes = 0;
2591         else
2592                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2593
2594         /* GLPRT_TEPC not supported */
2595
2596         /* additional port specific stats */
2597         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2598                             pf->offset_loaded, &os->tx_dropped_link_down,
2599                             &ns->tx_dropped_link_down);
2600         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2601                             pf->offset_loaded, &os->crc_errors,
2602                             &ns->crc_errors);
2603         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2604                             pf->offset_loaded, &os->illegal_bytes,
2605                             &ns->illegal_bytes);
2606         /* GLPRT_ERRBC not supported */
2607         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2608                             pf->offset_loaded, &os->mac_local_faults,
2609                             &ns->mac_local_faults);
2610         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2611                             pf->offset_loaded, &os->mac_remote_faults,
2612                             &ns->mac_remote_faults);
2613         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2614                             pf->offset_loaded, &os->rx_length_errors,
2615                             &ns->rx_length_errors);
2616         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2617                             pf->offset_loaded, &os->link_xon_rx,
2618                             &ns->link_xon_rx);
2619         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2620                             pf->offset_loaded, &os->link_xoff_rx,
2621                             &ns->link_xoff_rx);
2622         for (i = 0; i < 8; i++) {
2623                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2624                                     pf->offset_loaded,
2625                                     &os->priority_xon_rx[i],
2626                                     &ns->priority_xon_rx[i]);
2627                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2628                                     pf->offset_loaded,
2629                                     &os->priority_xoff_rx[i],
2630                                     &ns->priority_xoff_rx[i]);
2631         }
2632         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2633                             pf->offset_loaded, &os->link_xon_tx,
2634                             &ns->link_xon_tx);
2635         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2636                             pf->offset_loaded, &os->link_xoff_tx,
2637                             &ns->link_xoff_tx);
2638         for (i = 0; i < 8; i++) {
2639                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2640                                     pf->offset_loaded,
2641                                     &os->priority_xon_tx[i],
2642                                     &ns->priority_xon_tx[i]);
2643                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2644                                     pf->offset_loaded,
2645                                     &os->priority_xoff_tx[i],
2646                                     &ns->priority_xoff_tx[i]);
2647                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2648                                     pf->offset_loaded,
2649                                     &os->priority_xon_2_xoff[i],
2650                                     &ns->priority_xon_2_xoff[i]);
2651         }
2652         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2653                             I40E_GLPRT_PRC64L(hw->port),
2654                             pf->offset_loaded, &os->rx_size_64,
2655                             &ns->rx_size_64);
2656         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2657                             I40E_GLPRT_PRC127L(hw->port),
2658                             pf->offset_loaded, &os->rx_size_127,
2659                             &ns->rx_size_127);
2660         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2661                             I40E_GLPRT_PRC255L(hw->port),
2662                             pf->offset_loaded, &os->rx_size_255,
2663                             &ns->rx_size_255);
2664         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2665                             I40E_GLPRT_PRC511L(hw->port),
2666                             pf->offset_loaded, &os->rx_size_511,
2667                             &ns->rx_size_511);
2668         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2669                             I40E_GLPRT_PRC1023L(hw->port),
2670                             pf->offset_loaded, &os->rx_size_1023,
2671                             &ns->rx_size_1023);
2672         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2673                             I40E_GLPRT_PRC1522L(hw->port),
2674                             pf->offset_loaded, &os->rx_size_1522,
2675                             &ns->rx_size_1522);
2676         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2677                             I40E_GLPRT_PRC9522L(hw->port),
2678                             pf->offset_loaded, &os->rx_size_big,
2679                             &ns->rx_size_big);
2680         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2681                             pf->offset_loaded, &os->rx_undersize,
2682                             &ns->rx_undersize);
2683         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2684                             pf->offset_loaded, &os->rx_fragments,
2685                             &ns->rx_fragments);
2686         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2687                             pf->offset_loaded, &os->rx_oversize,
2688                             &ns->rx_oversize);
2689         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2690                             pf->offset_loaded, &os->rx_jabber,
2691                             &ns->rx_jabber);
2692         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2693                             I40E_GLPRT_PTC64L(hw->port),
2694                             pf->offset_loaded, &os->tx_size_64,
2695                             &ns->tx_size_64);
2696         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2697                             I40E_GLPRT_PTC127L(hw->port),
2698                             pf->offset_loaded, &os->tx_size_127,
2699                             &ns->tx_size_127);
2700         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2701                             I40E_GLPRT_PTC255L(hw->port),
2702                             pf->offset_loaded, &os->tx_size_255,
2703                             &ns->tx_size_255);
2704         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2705                             I40E_GLPRT_PTC511L(hw->port),
2706                             pf->offset_loaded, &os->tx_size_511,
2707                             &ns->tx_size_511);
2708         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2709                             I40E_GLPRT_PTC1023L(hw->port),
2710                             pf->offset_loaded, &os->tx_size_1023,
2711                             &ns->tx_size_1023);
2712         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2713                             I40E_GLPRT_PTC1522L(hw->port),
2714                             pf->offset_loaded, &os->tx_size_1522,
2715                             &ns->tx_size_1522);
2716         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2717                             I40E_GLPRT_PTC9522L(hw->port),
2718                             pf->offset_loaded, &os->tx_size_big,
2719                             &ns->tx_size_big);
2720         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2721                            pf->offset_loaded,
2722                            &os->fd_sb_match, &ns->fd_sb_match);
2723         /* GLPRT_MSPDC not supported */
2724         /* GLPRT_XEC not supported */
2725
2726         pf->offset_loaded = true;
2727
2728         if (pf->main_vsi)
2729                 i40e_update_vsi_stats(pf->main_vsi);
2730 }
2731
2732 /* Get all statistics of a port */
2733 static int
2734 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2735 {
2736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2739         unsigned i;
2740
2741         /* call read registers - updates values, now write them to struct */
2742         i40e_read_stats_registers(pf, hw);
2743
2744         stats->ipackets = ns->eth.rx_unicast +
2745                         ns->eth.rx_multicast +
2746                         ns->eth.rx_broadcast -
2747                         ns->eth.rx_discards -
2748                         pf->main_vsi->eth_stats.rx_discards;
2749         stats->opackets = ns->eth.tx_unicast +
2750                         ns->eth.tx_multicast +
2751                         ns->eth.tx_broadcast;
2752         stats->ibytes   = ns->eth.rx_bytes;
2753         stats->obytes   = ns->eth.tx_bytes;
2754         stats->oerrors  = ns->eth.tx_errors +
2755                         pf->main_vsi->eth_stats.tx_errors;
2756
2757         /* Rx Errors */
2758         stats->imissed  = ns->eth.rx_discards +
2759                         pf->main_vsi->eth_stats.rx_discards;
2760         stats->ierrors  = ns->crc_errors +
2761                         ns->rx_length_errors + ns->rx_undersize +
2762                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2763
2764         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2765         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2766         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2767         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2768         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2769         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2770         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2771                     ns->eth.rx_unknown_protocol);
2772         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2773         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2774         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2775         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2776         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2777         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2778
2779         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2780                     ns->tx_dropped_link_down);
2781         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2782         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2783                     ns->illegal_bytes);
2784         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2785         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2786                     ns->mac_local_faults);
2787         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2788                     ns->mac_remote_faults);
2789         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2790                     ns->rx_length_errors);
2791         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2792         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2793         for (i = 0; i < 8; i++) {
2794                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2795                                 i, ns->priority_xon_rx[i]);
2796                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2797                                 i, ns->priority_xoff_rx[i]);
2798         }
2799         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2800         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2801         for (i = 0; i < 8; i++) {
2802                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2803                                 i, ns->priority_xon_tx[i]);
2804                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2805                                 i, ns->priority_xoff_tx[i]);
2806                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2807                                 i, ns->priority_xon_2_xoff[i]);
2808         }
2809         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2810         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2811         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2812         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2813         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2814         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2815         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2816         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2817         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2818         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2819         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2820         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2821         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2822         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2823         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2824         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2825         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2826         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2827         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2828                         ns->mac_short_packet_dropped);
2829         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2830                     ns->checksum_error);
2831         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2832         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2833         return 0;
2834 }
2835
2836 /* Reset the statistics */
2837 static void
2838 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2839 {
2840         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842
2843         /* Mark PF and VSI stats to update the offset, aka "reset" */
2844         pf->offset_loaded = false;
2845         if (pf->main_vsi)
2846                 pf->main_vsi->offset_loaded = false;
2847
2848         /* read the stats, reading current register values into offset */
2849         i40e_read_stats_registers(pf, hw);
2850 }
2851
2852 static uint32_t
2853 i40e_xstats_calc_num(void)
2854 {
2855         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2856                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2857                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2858 }
2859
2860 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2861                                      struct rte_eth_xstat_name *xstats_names,
2862                                      __rte_unused unsigned limit)
2863 {
2864         unsigned count = 0;
2865         unsigned i, prio;
2866
2867         if (xstats_names == NULL)
2868                 return i40e_xstats_calc_num();
2869
2870         /* Note: limit checked in rte_eth_xstats_names() */
2871
2872         /* Get stats from i40e_eth_stats struct */
2873         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2874                 snprintf(xstats_names[count].name,
2875                          sizeof(xstats_names[count].name),
2876                          "%s", rte_i40e_stats_strings[i].name);
2877                 count++;
2878         }
2879
2880         /* Get individiual stats from i40e_hw_port struct */
2881         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2882                 snprintf(xstats_names[count].name,
2883                         sizeof(xstats_names[count].name),
2884                          "%s", rte_i40e_hw_port_strings[i].name);
2885                 count++;
2886         }
2887
2888         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2889                 for (prio = 0; prio < 8; prio++) {
2890                         snprintf(xstats_names[count].name,
2891                                  sizeof(xstats_names[count].name),
2892                                  "rx_priority%u_%s", prio,
2893                                  rte_i40e_rxq_prio_strings[i].name);
2894                         count++;
2895                 }
2896         }
2897
2898         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2899                 for (prio = 0; prio < 8; prio++) {
2900                         snprintf(xstats_names[count].name,
2901                                  sizeof(xstats_names[count].name),
2902                                  "tx_priority%u_%s", prio,
2903                                  rte_i40e_txq_prio_strings[i].name);
2904                         count++;
2905                 }
2906         }
2907         return count;
2908 }
2909
2910 static int
2911 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2912                     unsigned n)
2913 {
2914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2916         unsigned i, count, prio;
2917         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2918
2919         count = i40e_xstats_calc_num();
2920         if (n < count)
2921                 return count;
2922
2923         i40e_read_stats_registers(pf, hw);
2924
2925         if (xstats == NULL)
2926                 return 0;
2927
2928         count = 0;
2929
2930         /* Get stats from i40e_eth_stats struct */
2931         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2932                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2933                         rte_i40e_stats_strings[i].offset);
2934                 xstats[count].id = count;
2935                 count++;
2936         }
2937
2938         /* Get individiual stats from i40e_hw_port struct */
2939         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2940                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2941                         rte_i40e_hw_port_strings[i].offset);
2942                 xstats[count].id = count;
2943                 count++;
2944         }
2945
2946         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2947                 for (prio = 0; prio < 8; prio++) {
2948                         xstats[count].value =
2949                                 *(uint64_t *)(((char *)hw_stats) +
2950                                 rte_i40e_rxq_prio_strings[i].offset +
2951                                 (sizeof(uint64_t) * prio));
2952                         xstats[count].id = count;
2953                         count++;
2954                 }
2955         }
2956
2957         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2958                 for (prio = 0; prio < 8; prio++) {
2959                         xstats[count].value =
2960                                 *(uint64_t *)(((char *)hw_stats) +
2961                                 rte_i40e_txq_prio_strings[i].offset +
2962                                 (sizeof(uint64_t) * prio));
2963                         xstats[count].id = count;
2964                         count++;
2965                 }
2966         }
2967
2968         return count;
2969 }
2970
2971 static int
2972 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2973                                  __rte_unused uint16_t queue_id,
2974                                  __rte_unused uint8_t stat_idx,
2975                                  __rte_unused uint8_t is_rx)
2976 {
2977         PMD_INIT_FUNC_TRACE();
2978
2979         return -ENOSYS;
2980 }
2981
2982 static int
2983 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2984 {
2985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986         u32 full_ver;
2987         u8 ver, patch;
2988         u16 build;
2989         int ret;
2990
2991         full_ver = hw->nvm.oem_ver;
2992         ver = (u8)(full_ver >> 24);
2993         build = (u16)((full_ver >> 8) & 0xffff);
2994         patch = (u8)(full_ver & 0xff);
2995
2996         ret = snprintf(fw_version, fw_size,
2997                  "%d.%d%d 0x%08x %d.%d.%d",
2998                  ((hw->nvm.version >> 12) & 0xf),
2999                  ((hw->nvm.version >> 4) & 0xff),
3000                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3001                  ver, build, patch);
3002
3003         ret += 1; /* add the size of '\0' */
3004         if (fw_size < (u32)ret)
3005                 return ret;
3006         else
3007                 return 0;
3008 }
3009
3010 static void
3011 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3012 {
3013         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3015         struct i40e_vsi *vsi = pf->main_vsi;
3016         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3017
3018         dev_info->pci_dev = pci_dev;
3019         dev_info->max_rx_queues = vsi->nb_qps;
3020         dev_info->max_tx_queues = vsi->nb_qps;
3021         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3022         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3023         dev_info->max_mac_addrs = vsi->max_macaddrs;
3024         dev_info->max_vfs = pci_dev->max_vfs;
3025         dev_info->rx_offload_capa =
3026                 DEV_RX_OFFLOAD_VLAN_STRIP |
3027                 DEV_RX_OFFLOAD_QINQ_STRIP |
3028                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3029                 DEV_RX_OFFLOAD_UDP_CKSUM |
3030                 DEV_RX_OFFLOAD_TCP_CKSUM;
3031         dev_info->tx_offload_capa =
3032                 DEV_TX_OFFLOAD_VLAN_INSERT |
3033                 DEV_TX_OFFLOAD_QINQ_INSERT |
3034                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3035                 DEV_TX_OFFLOAD_UDP_CKSUM |
3036                 DEV_TX_OFFLOAD_TCP_CKSUM |
3037                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3038                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3039                 DEV_TX_OFFLOAD_TCP_TSO |
3040                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3041                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3042                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3043                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3044         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3045                                                 sizeof(uint32_t);
3046         dev_info->reta_size = pf->hash_lut_size;
3047         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3048
3049         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3050                 .rx_thresh = {
3051                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3052                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3053                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3054                 },
3055                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3056                 .rx_drop_en = 0,
3057         };
3058
3059         dev_info->default_txconf = (struct rte_eth_txconf) {
3060                 .tx_thresh = {
3061                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3062                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3063                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3064                 },
3065                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3066                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3067                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3068                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3069         };
3070
3071         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3072                 .nb_max = I40E_MAX_RING_DESC,
3073                 .nb_min = I40E_MIN_RING_DESC,
3074                 .nb_align = I40E_ALIGN_RING_DESC,
3075         };
3076
3077         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3078                 .nb_max = I40E_MAX_RING_DESC,
3079                 .nb_min = I40E_MIN_RING_DESC,
3080                 .nb_align = I40E_ALIGN_RING_DESC,
3081                 .nb_seg_max = I40E_TX_MAX_SEG,
3082                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3083         };
3084
3085         if (pf->flags & I40E_FLAG_VMDQ) {
3086                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3087                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3088                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3089                                                 pf->max_nb_vmdq_vsi;
3090                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3091                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3092                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3093         }
3094
3095         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3096                 /* For XL710 */
3097                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3098         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3099                 /* For XXV710 */
3100                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3101         else
3102                 /* For X710 */
3103                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3104 }
3105
3106 static int
3107 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3108 {
3109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110         struct i40e_vsi *vsi = pf->main_vsi;
3111         PMD_INIT_FUNC_TRACE();
3112
3113         if (on)
3114                 return i40e_vsi_add_vlan(vsi, vlan_id);
3115         else
3116                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3117 }
3118
3119 static int
3120 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3121                                 enum rte_vlan_type vlan_type,
3122                                 uint16_t tpid, int qinq)
3123 {
3124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125         uint64_t reg_r = 0;
3126         uint64_t reg_w = 0;
3127         uint16_t reg_id = 3;
3128         int ret;
3129
3130         if (qinq) {
3131                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3132                         reg_id = 2;
3133         }
3134
3135         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3136                                           &reg_r, NULL);
3137         if (ret != I40E_SUCCESS) {
3138                 PMD_DRV_LOG(ERR,
3139                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3140                            reg_id);
3141                 return -EIO;
3142         }
3143         PMD_DRV_LOG(DEBUG,
3144                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3145                     reg_id, reg_r);
3146
3147         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3148         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3149         if (reg_r == reg_w) {
3150                 PMD_DRV_LOG(DEBUG, "No need to write");
3151                 return 0;
3152         }
3153
3154         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3155                                            reg_w, NULL);
3156         if (ret != I40E_SUCCESS) {
3157                 PMD_DRV_LOG(ERR,
3158                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3159                             reg_id);
3160                 return -EIO;
3161         }
3162         PMD_DRV_LOG(DEBUG,
3163                     "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3164                     reg_w, reg_id);
3165
3166         return 0;
3167 }
3168
3169 static int
3170 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3171                    enum rte_vlan_type vlan_type,
3172                    uint16_t tpid)
3173 {
3174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3175         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3176         int ret = 0;
3177
3178         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3179              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3180             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3181                 PMD_DRV_LOG(ERR,
3182                             "Unsupported vlan type.");
3183                 return -EINVAL;
3184         }
3185         /* 802.1ad frames ability is added in NVM API 1.7*/
3186         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3187                 if (qinq) {
3188                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3189                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3190                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3191                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3192                 } else {
3193                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3194                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3195                 }
3196                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3197                 if (ret != I40E_SUCCESS) {
3198                         PMD_DRV_LOG(ERR,
3199                                     "Set switch config failed aq_err: %d",
3200                                     hw->aq.asq_last_status);
3201                         ret = -EIO;
3202                 }
3203         } else
3204                 /* If NVM API < 1.7, keep the register setting */
3205                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3206                                                       tpid, qinq);
3207
3208         return ret;
3209 }
3210
3211 static int
3212 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3213 {
3214         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3215         struct i40e_vsi *vsi = pf->main_vsi;
3216
3217         if (mask & ETH_VLAN_FILTER_MASK) {
3218                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3219                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3220                 else
3221                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3222         }
3223
3224         if (mask & ETH_VLAN_STRIP_MASK) {
3225                 /* Enable or disable VLAN stripping */
3226                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3227                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3228                 else
3229                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3230         }
3231
3232         if (mask & ETH_VLAN_EXTEND_MASK) {
3233                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3234                         i40e_vsi_config_double_vlan(vsi, TRUE);
3235                         /* Set global registers with default ethertype. */
3236                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3237                                            ETHER_TYPE_VLAN);
3238                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3239                                            ETHER_TYPE_VLAN);
3240                 }
3241                 else
3242                         i40e_vsi_config_double_vlan(vsi, FALSE);
3243         }
3244
3245         return 0;
3246 }
3247
3248 static void
3249 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3250                           __rte_unused uint16_t queue,
3251                           __rte_unused int on)
3252 {
3253         PMD_INIT_FUNC_TRACE();
3254 }
3255
3256 static int
3257 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3258 {
3259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3260         struct i40e_vsi *vsi = pf->main_vsi;
3261         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3262         struct i40e_vsi_vlan_pvid_info info;
3263
3264         memset(&info, 0, sizeof(info));
3265         info.on = on;
3266         if (info.on)
3267                 info.config.pvid = pvid;
3268         else {
3269                 info.config.reject.tagged =
3270                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3271                 info.config.reject.untagged =
3272                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3273         }
3274
3275         return i40e_vsi_vlan_pvid_set(vsi, &info);
3276 }
3277
3278 static int
3279 i40e_dev_led_on(struct rte_eth_dev *dev)
3280 {
3281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3282         uint32_t mode = i40e_led_get(hw);
3283
3284         if (mode == 0)
3285                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3286
3287         return 0;
3288 }
3289
3290 static int
3291 i40e_dev_led_off(struct rte_eth_dev *dev)
3292 {
3293         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294         uint32_t mode = i40e_led_get(hw);
3295
3296         if (mode != 0)
3297                 i40e_led_set(hw, 0, false);
3298
3299         return 0;
3300 }
3301
3302 static int
3303 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3304 {
3305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3306         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3307
3308         fc_conf->pause_time = pf->fc_conf.pause_time;
3309
3310         /* read out from register, in case they are modified by other port */
3311         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3312                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3313         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3314                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3315
3316         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3317         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3318
3319          /* Return current mode according to actual setting*/
3320         switch (hw->fc.current_mode) {
3321         case I40E_FC_FULL:
3322                 fc_conf->mode = RTE_FC_FULL;
3323                 break;
3324         case I40E_FC_TX_PAUSE:
3325                 fc_conf->mode = RTE_FC_TX_PAUSE;
3326                 break;
3327         case I40E_FC_RX_PAUSE:
3328                 fc_conf->mode = RTE_FC_RX_PAUSE;
3329                 break;
3330         case I40E_FC_NONE:
3331         default:
3332                 fc_conf->mode = RTE_FC_NONE;
3333         };
3334
3335         return 0;
3336 }
3337
3338 static int
3339 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3340 {
3341         uint32_t mflcn_reg, fctrl_reg, reg;
3342         uint32_t max_high_water;
3343         uint8_t i, aq_failure;
3344         int err;
3345         struct i40e_hw *hw;
3346         struct i40e_pf *pf;
3347         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3348                 [RTE_FC_NONE] = I40E_FC_NONE,
3349                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3350                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3351                 [RTE_FC_FULL] = I40E_FC_FULL
3352         };
3353
3354         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3355
3356         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3357         if ((fc_conf->high_water > max_high_water) ||
3358                         (fc_conf->high_water < fc_conf->low_water)) {
3359                 PMD_INIT_LOG(ERR,
3360                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3361                         max_high_water);
3362                 return -EINVAL;
3363         }
3364
3365         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3366         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3367         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3368
3369         pf->fc_conf.pause_time = fc_conf->pause_time;
3370         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3371         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3372
3373         PMD_INIT_FUNC_TRACE();
3374
3375         /* All the link flow control related enable/disable register
3376          * configuration is handle by the F/W
3377          */
3378         err = i40e_set_fc(hw, &aq_failure, true);
3379         if (err < 0)
3380                 return -ENOSYS;
3381
3382         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3383                 /* Configure flow control refresh threshold,
3384                  * the value for stat_tx_pause_refresh_timer[8]
3385                  * is used for global pause operation.
3386                  */
3387
3388                 I40E_WRITE_REG(hw,
3389                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3390                                pf->fc_conf.pause_time);
3391
3392                 /* configure the timer value included in transmitted pause
3393                  * frame,
3394                  * the value for stat_tx_pause_quanta[8] is used for global
3395                  * pause operation
3396                  */
3397                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3398                                pf->fc_conf.pause_time);
3399
3400                 fctrl_reg = I40E_READ_REG(hw,
3401                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3402
3403                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3404                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3405                 else
3406                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3407
3408                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3409                                fctrl_reg);
3410         } else {
3411                 /* Configure pause time (2 TCs per register) */
3412                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3413                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3414                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3415
3416                 /* Configure flow control refresh threshold value */
3417                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3418                                pf->fc_conf.pause_time / 2);
3419
3420                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3421
3422                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3423                  *depending on configuration
3424                  */
3425                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3426                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3427                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3428                 } else {
3429                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3430                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3431                 }
3432
3433                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3434         }
3435
3436         /* config the water marker both based on the packets and bytes */
3437         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3438                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3439                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3440         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3441                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3442                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3443         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3444                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3445                        << I40E_KILOSHIFT);
3446         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3447                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3448                        << I40E_KILOSHIFT);
3449
3450         I40E_WRITE_FLUSH(hw);
3451
3452         return 0;
3453 }
3454
3455 static int
3456 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3457                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3458 {
3459         PMD_INIT_FUNC_TRACE();
3460
3461         return -ENOSYS;
3462 }
3463
3464 /* Add a MAC address, and update filters */
3465 static int
3466 i40e_macaddr_add(struct rte_eth_dev *dev,
3467                  struct ether_addr *mac_addr,
3468                  __rte_unused uint32_t index,
3469                  uint32_t pool)
3470 {
3471         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3472         struct i40e_mac_filter_info mac_filter;
3473         struct i40e_vsi *vsi;
3474         int ret;
3475
3476         /* If VMDQ not enabled or configured, return */
3477         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3478                           !pf->nb_cfg_vmdq_vsi)) {
3479                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3480                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3481                         pool);
3482                 return -ENOTSUP;
3483         }
3484
3485         if (pool > pf->nb_cfg_vmdq_vsi) {
3486                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3487                                 pool, pf->nb_cfg_vmdq_vsi);
3488                 return -EINVAL;
3489         }
3490
3491         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3492         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3493                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3494         else
3495                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3496
3497         if (pool == 0)
3498                 vsi = pf->main_vsi;
3499         else
3500                 vsi = pf->vmdq[pool - 1].vsi;
3501
3502         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3503         if (ret != I40E_SUCCESS) {
3504                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3505                 return -ENODEV;
3506         }
3507         return 0;
3508 }
3509
3510 /* Remove a MAC address, and update filters */
3511 static void
3512 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3513 {
3514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3515         struct i40e_vsi *vsi;
3516         struct rte_eth_dev_data *data = dev->data;
3517         struct ether_addr *macaddr;
3518         int ret;
3519         uint32_t i;
3520         uint64_t pool_sel;
3521
3522         macaddr = &(data->mac_addrs[index]);
3523
3524         pool_sel = dev->data->mac_pool_sel[index];
3525
3526         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3527                 if (pool_sel & (1ULL << i)) {
3528                         if (i == 0)
3529                                 vsi = pf->main_vsi;
3530                         else {
3531                                 /* No VMDQ pool enabled or configured */
3532                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3533                                         (i > pf->nb_cfg_vmdq_vsi)) {
3534                                         PMD_DRV_LOG(ERR,
3535                                                 "No VMDQ pool enabled/configured");
3536                                         return;
3537                                 }
3538                                 vsi = pf->vmdq[i - 1].vsi;
3539                         }
3540                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3541
3542                         if (ret) {
3543                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3544                                 return;
3545                         }
3546                 }
3547         }
3548 }
3549
3550 /* Set perfect match or hash match of MAC and VLAN for a VF */
3551 static int
3552 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3553                  struct rte_eth_mac_filter *filter,
3554                  bool add)
3555 {
3556         struct i40e_hw *hw;
3557         struct i40e_mac_filter_info mac_filter;
3558         struct ether_addr old_mac;
3559         struct ether_addr *new_mac;
3560         struct i40e_pf_vf *vf = NULL;
3561         uint16_t vf_id;
3562         int ret;
3563
3564         if (pf == NULL) {
3565                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3566                 return -EINVAL;
3567         }
3568         hw = I40E_PF_TO_HW(pf);
3569
3570         if (filter == NULL) {
3571                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3572                 return -EINVAL;
3573         }
3574
3575         new_mac = &filter->mac_addr;
3576
3577         if (is_zero_ether_addr(new_mac)) {
3578                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3579                 return -EINVAL;
3580         }
3581
3582         vf_id = filter->dst_id;
3583
3584         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3585                 PMD_DRV_LOG(ERR, "Invalid argument.");
3586                 return -EINVAL;
3587         }
3588         vf = &pf->vfs[vf_id];
3589
3590         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3591                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3592                 return -EINVAL;
3593         }
3594
3595         if (add) {
3596                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3597                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3598                                 ETHER_ADDR_LEN);
3599                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3600                                  ETHER_ADDR_LEN);
3601
3602                 mac_filter.filter_type = filter->filter_type;
3603                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3604                 if (ret != I40E_SUCCESS) {
3605                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3606                         return -1;
3607                 }
3608                 ether_addr_copy(new_mac, &pf->dev_addr);
3609         } else {
3610                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3611                                 ETHER_ADDR_LEN);
3612                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3613                 if (ret != I40E_SUCCESS) {
3614                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3615                         return -1;
3616                 }
3617
3618                 /* Clear device address as it has been removed */
3619                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3620                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3621         }
3622
3623         return 0;
3624 }
3625
3626 /* MAC filter handle */
3627 static int
3628 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3629                 void *arg)
3630 {
3631         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3632         struct rte_eth_mac_filter *filter;
3633         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3634         int ret = I40E_NOT_SUPPORTED;
3635
3636         filter = (struct rte_eth_mac_filter *)(arg);
3637
3638         switch (filter_op) {
3639         case RTE_ETH_FILTER_NOP:
3640                 ret = I40E_SUCCESS;
3641                 break;
3642         case RTE_ETH_FILTER_ADD:
3643                 i40e_pf_disable_irq0(hw);
3644                 if (filter->is_vf)
3645                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3646                 i40e_pf_enable_irq0(hw);
3647                 break;
3648         case RTE_ETH_FILTER_DELETE:
3649                 i40e_pf_disable_irq0(hw);
3650                 if (filter->is_vf)
3651                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3652                 i40e_pf_enable_irq0(hw);
3653                 break;
3654         default:
3655                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3656                 ret = I40E_ERR_PARAM;
3657                 break;
3658         }
3659
3660         return ret;
3661 }
3662
3663 static int
3664 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3665 {
3666         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3667         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3668         int ret;
3669
3670         if (!lut)
3671                 return -EINVAL;
3672
3673         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3674                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3675                                           lut, lut_size);
3676                 if (ret) {
3677                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3678                         return ret;
3679                 }
3680         } else {
3681                 uint32_t *lut_dw = (uint32_t *)lut;
3682                 uint16_t i, lut_size_dw = lut_size / 4;
3683
3684                 for (i = 0; i < lut_size_dw; i++)
3685                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3686         }
3687
3688         return 0;
3689 }
3690
3691 static int
3692 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3693 {
3694         struct i40e_pf *pf;
3695         struct i40e_hw *hw;
3696         int ret;
3697
3698         if (!vsi || !lut)
3699                 return -EINVAL;
3700
3701         pf = I40E_VSI_TO_PF(vsi);
3702         hw = I40E_VSI_TO_HW(vsi);
3703
3704         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3705                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3706                                           lut, lut_size);
3707                 if (ret) {
3708                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3709                         return ret;
3710                 }
3711         } else {
3712                 uint32_t *lut_dw = (uint32_t *)lut;
3713                 uint16_t i, lut_size_dw = lut_size / 4;
3714
3715                 for (i = 0; i < lut_size_dw; i++)
3716                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3717                 I40E_WRITE_FLUSH(hw);
3718         }
3719
3720         return 0;
3721 }
3722
3723 static int
3724 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3725                          struct rte_eth_rss_reta_entry64 *reta_conf,
3726                          uint16_t reta_size)
3727 {
3728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3729         uint16_t i, lut_size = pf->hash_lut_size;
3730         uint16_t idx, shift;
3731         uint8_t *lut;
3732         int ret;
3733
3734         if (reta_size != lut_size ||
3735                 reta_size > ETH_RSS_RETA_SIZE_512) {
3736                 PMD_DRV_LOG(ERR,
3737                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3738                         reta_size, lut_size);
3739                 return -EINVAL;
3740         }
3741
3742         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3743         if (!lut) {
3744                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3745                 return -ENOMEM;
3746         }
3747         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3748         if (ret)
3749                 goto out;
3750         for (i = 0; i < reta_size; i++) {
3751                 idx = i / RTE_RETA_GROUP_SIZE;
3752                 shift = i % RTE_RETA_GROUP_SIZE;
3753                 if (reta_conf[idx].mask & (1ULL << shift))
3754                         lut[i] = reta_conf[idx].reta[shift];
3755         }
3756         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3757
3758 out:
3759         rte_free(lut);
3760
3761         return ret;
3762 }
3763
3764 static int
3765 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3766                         struct rte_eth_rss_reta_entry64 *reta_conf,
3767                         uint16_t reta_size)
3768 {
3769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3770         uint16_t i, lut_size = pf->hash_lut_size;
3771         uint16_t idx, shift;
3772         uint8_t *lut;
3773         int ret;
3774
3775         if (reta_size != lut_size ||
3776                 reta_size > ETH_RSS_RETA_SIZE_512) {
3777                 PMD_DRV_LOG(ERR,
3778                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3779                         reta_size, lut_size);
3780                 return -EINVAL;
3781         }
3782
3783         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3784         if (!lut) {
3785                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3786                 return -ENOMEM;
3787         }
3788
3789         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3790         if (ret)
3791                 goto out;
3792         for (i = 0; i < reta_size; i++) {
3793                 idx = i / RTE_RETA_GROUP_SIZE;
3794                 shift = i % RTE_RETA_GROUP_SIZE;
3795                 if (reta_conf[idx].mask & (1ULL << shift))
3796                         reta_conf[idx].reta[shift] = lut[i];
3797         }
3798
3799 out:
3800         rte_free(lut);
3801
3802         return ret;
3803 }
3804
3805 /**
3806  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3807  * @hw:   pointer to the HW structure
3808  * @mem:  pointer to mem struct to fill out
3809  * @size: size of memory requested
3810  * @alignment: what to align the allocation to
3811  **/
3812 enum i40e_status_code
3813 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3814                         struct i40e_dma_mem *mem,
3815                         u64 size,
3816                         u32 alignment)
3817 {
3818         const struct rte_memzone *mz = NULL;
3819         char z_name[RTE_MEMZONE_NAMESIZE];
3820
3821         if (!mem)
3822                 return I40E_ERR_PARAM;
3823
3824         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3825         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3826                                          alignment, RTE_PGSIZE_2M);
3827         if (!mz)
3828                 return I40E_ERR_NO_MEMORY;
3829
3830         mem->size = size;
3831         mem->va = mz->addr;
3832         mem->pa = mz->iova;
3833         mem->zone = (const void *)mz;
3834         PMD_DRV_LOG(DEBUG,
3835                 "memzone %s allocated with physical address: %"PRIu64,
3836                 mz->name, mem->pa);
3837
3838         return I40E_SUCCESS;
3839 }
3840
3841 /**
3842  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3843  * @hw:   pointer to the HW structure
3844  * @mem:  ptr to mem struct to free
3845  **/
3846 enum i40e_status_code
3847 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3848                     struct i40e_dma_mem *mem)
3849 {
3850         if (!mem)
3851                 return I40E_ERR_PARAM;
3852
3853         PMD_DRV_LOG(DEBUG,
3854                 "memzone %s to be freed with physical address: %"PRIu64,
3855                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3856         rte_memzone_free((const struct rte_memzone *)mem->zone);
3857         mem->zone = NULL;
3858         mem->va = NULL;
3859         mem->pa = (u64)0;
3860
3861         return I40E_SUCCESS;
3862 }
3863
3864 /**
3865  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3866  * @hw:   pointer to the HW structure
3867  * @mem:  pointer to mem struct to fill out
3868  * @size: size of memory requested
3869  **/
3870 enum i40e_status_code
3871 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3872                          struct i40e_virt_mem *mem,
3873                          u32 size)
3874 {
3875         if (!mem)
3876                 return I40E_ERR_PARAM;
3877
3878         mem->size = size;
3879         mem->va = rte_zmalloc("i40e", size, 0);
3880
3881         if (mem->va)
3882                 return I40E_SUCCESS;
3883         else
3884                 return I40E_ERR_NO_MEMORY;
3885 }
3886
3887 /**
3888  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3889  * @hw:   pointer to the HW structure
3890  * @mem:  pointer to mem struct to free
3891  **/
3892 enum i40e_status_code
3893 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3894                      struct i40e_virt_mem *mem)
3895 {
3896         if (!mem)
3897                 return I40E_ERR_PARAM;
3898
3899         rte_free(mem->va);
3900         mem->va = NULL;
3901
3902         return I40E_SUCCESS;
3903 }
3904
3905 void
3906 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3907 {
3908         rte_spinlock_init(&sp->spinlock);
3909 }
3910
3911 void
3912 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3913 {
3914         rte_spinlock_lock(&sp->spinlock);
3915 }
3916
3917 void
3918 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3919 {
3920         rte_spinlock_unlock(&sp->spinlock);
3921 }
3922
3923 void
3924 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3925 {
3926         return;
3927 }
3928
3929 /**
3930  * Get the hardware capabilities, which will be parsed
3931  * and saved into struct i40e_hw.
3932  */
3933 static int
3934 i40e_get_cap(struct i40e_hw *hw)
3935 {
3936         struct i40e_aqc_list_capabilities_element_resp *buf;
3937         uint16_t len, size = 0;
3938         int ret;
3939
3940         /* Calculate a huge enough buff for saving response data temporarily */
3941         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3942                                                 I40E_MAX_CAP_ELE_NUM;
3943         buf = rte_zmalloc("i40e", len, 0);
3944         if (!buf) {
3945                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3946                 return I40E_ERR_NO_MEMORY;
3947         }
3948
3949         /* Get, parse the capabilities and save it to hw */
3950         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3951                         i40e_aqc_opc_list_func_capabilities, NULL);
3952         if (ret != I40E_SUCCESS)
3953                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3954
3955         /* Free the temporary buffer after being used */
3956         rte_free(buf);
3957
3958         return ret;
3959 }
3960
3961 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
3962 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
3963 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
3964
3965 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
3966                 const char *value,
3967                 void *opaque)
3968 {
3969         struct i40e_pf *pf;
3970         unsigned long num;
3971         char *end;
3972
3973         pf = (struct i40e_pf *)opaque;
3974         RTE_SET_USED(key);
3975
3976         errno = 0;
3977         num = strtoul(value, &end, 0);
3978         if (errno != 0 || end == value || *end != 0) {
3979                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
3980                             "kept the value = %hu", value, pf->vf_nb_qp_max);
3981                 return -(EINVAL);
3982         }
3983
3984         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
3985                 pf->vf_nb_qp_max = (uint16_t)num;
3986         else
3987                 /* here return 0 to make next valid same argument work */
3988                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
3989                             "power of 2 and equal or less than 16 !, Now it is "
3990                             "kept the value = %hu", num, pf->vf_nb_qp_max);
3991
3992         return 0;
3993 }
3994
3995 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
3996 {
3997         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
3998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3999         struct rte_kvargs *kvlist;
4000
4001         /* set default queue number per VF as 4 */
4002         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4003
4004         if (dev->device->devargs == NULL)
4005                 return 0;
4006
4007         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4008         if (kvlist == NULL)
4009                 return -(EINVAL);
4010
4011         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4012                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4013                             "the first invalid or last valid one is used !",
4014                             QUEUE_NUM_PER_VF_ARG);
4015
4016         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4017                            i40e_pf_parse_vf_queue_number_handler, pf);
4018
4019         rte_kvargs_free(kvlist);
4020
4021         return 0;
4022 }
4023
4024 static int
4025 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4026 {
4027         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4028         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4029         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4030         uint16_t qp_count = 0, vsi_count = 0;
4031
4032         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4033                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4034                 return -EINVAL;
4035         }
4036
4037         i40e_pf_config_vf_rxq_number(dev);
4038
4039         /* Add the parameter init for LFC */
4040         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4041         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4042         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4043
4044         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4045         pf->max_num_vsi = hw->func_caps.num_vsis;
4046         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4047         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4048
4049         /* FDir queue/VSI allocation */
4050         pf->fdir_qp_offset = 0;
4051         if (hw->func_caps.fd) {
4052                 pf->flags |= I40E_FLAG_FDIR;
4053                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4054         } else {
4055                 pf->fdir_nb_qps = 0;
4056         }
4057         qp_count += pf->fdir_nb_qps;
4058         vsi_count += 1;
4059
4060         /* LAN queue/VSI allocation */
4061         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4062         if (!hw->func_caps.rss) {
4063                 pf->lan_nb_qps = 1;
4064         } else {
4065                 pf->flags |= I40E_FLAG_RSS;
4066                 if (hw->mac.type == I40E_MAC_X722)
4067                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4068                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4069         }
4070         qp_count += pf->lan_nb_qps;
4071         vsi_count += 1;
4072
4073         /* VF queue/VSI allocation */
4074         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4075         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4076                 pf->flags |= I40E_FLAG_SRIOV;
4077                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4078                 pf->vf_num = pci_dev->max_vfs;
4079                 PMD_DRV_LOG(DEBUG,
4080                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4081                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4082         } else {
4083                 pf->vf_nb_qps = 0;
4084                 pf->vf_num = 0;
4085         }
4086         qp_count += pf->vf_nb_qps * pf->vf_num;
4087         vsi_count += pf->vf_num;
4088
4089         /* VMDq queue/VSI allocation */
4090         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4091         pf->vmdq_nb_qps = 0;
4092         pf->max_nb_vmdq_vsi = 0;
4093         if (hw->func_caps.vmdq) {
4094                 if (qp_count < hw->func_caps.num_tx_qp &&
4095                         vsi_count < hw->func_caps.num_vsis) {
4096                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4097                                 qp_count) / pf->vmdq_nb_qp_max;
4098
4099                         /* Limit the maximum number of VMDq vsi to the maximum
4100                          * ethdev can support
4101                          */
4102                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4103                                 hw->func_caps.num_vsis - vsi_count);
4104                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4105                                 ETH_64_POOLS);
4106                         if (pf->max_nb_vmdq_vsi) {
4107                                 pf->flags |= I40E_FLAG_VMDQ;
4108                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4109                                 PMD_DRV_LOG(DEBUG,
4110                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4111                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4112                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4113                         } else {
4114                                 PMD_DRV_LOG(INFO,
4115                                         "No enough queues left for VMDq");
4116                         }
4117                 } else {
4118                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4119                 }
4120         }
4121         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4122         vsi_count += pf->max_nb_vmdq_vsi;
4123
4124         if (hw->func_caps.dcb)
4125                 pf->flags |= I40E_FLAG_DCB;
4126
4127         if (qp_count > hw->func_caps.num_tx_qp) {
4128                 PMD_DRV_LOG(ERR,
4129                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4130                         qp_count, hw->func_caps.num_tx_qp);
4131                 return -EINVAL;
4132         }
4133         if (vsi_count > hw->func_caps.num_vsis) {
4134                 PMD_DRV_LOG(ERR,
4135                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4136                         vsi_count, hw->func_caps.num_vsis);
4137                 return -EINVAL;
4138         }
4139
4140         return 0;
4141 }
4142
4143 static int
4144 i40e_pf_get_switch_config(struct i40e_pf *pf)
4145 {
4146         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4147         struct i40e_aqc_get_switch_config_resp *switch_config;
4148         struct i40e_aqc_switch_config_element_resp *element;
4149         uint16_t start_seid = 0, num_reported;
4150         int ret;
4151
4152         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4153                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4154         if (!switch_config) {
4155                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4156                 return -ENOMEM;
4157         }
4158
4159         /* Get the switch configurations */
4160         ret = i40e_aq_get_switch_config(hw, switch_config,
4161                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4162         if (ret != I40E_SUCCESS) {
4163                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4164                 goto fail;
4165         }
4166         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4167         if (num_reported != 1) { /* The number should be 1 */
4168                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4169                 goto fail;
4170         }
4171
4172         /* Parse the switch configuration elements */
4173         element = &(switch_config->element[0]);
4174         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4175                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4176                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4177         } else
4178                 PMD_DRV_LOG(INFO, "Unknown element type");
4179
4180 fail:
4181         rte_free(switch_config);
4182
4183         return ret;
4184 }
4185
4186 static int
4187 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4188                         uint32_t num)
4189 {
4190         struct pool_entry *entry;
4191
4192         if (pool == NULL || num == 0)
4193                 return -EINVAL;
4194
4195         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4196         if (entry == NULL) {
4197                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4198                 return -ENOMEM;
4199         }
4200
4201         /* queue heap initialize */
4202         pool->num_free = num;
4203         pool->num_alloc = 0;
4204         pool->base = base;
4205         LIST_INIT(&pool->alloc_list);
4206         LIST_INIT(&pool->free_list);
4207
4208         /* Initialize element  */
4209         entry->base = 0;
4210         entry->len = num;
4211
4212         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4213         return 0;
4214 }
4215
4216 static void
4217 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4218 {
4219         struct pool_entry *entry, *next_entry;
4220
4221         if (pool == NULL)
4222                 return;
4223
4224         for (entry = LIST_FIRST(&pool->alloc_list);
4225                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4226                         entry = next_entry) {
4227                 LIST_REMOVE(entry, next);
4228                 rte_free(entry);
4229         }
4230
4231         for (entry = LIST_FIRST(&pool->free_list);
4232                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4233                         entry = next_entry) {
4234                 LIST_REMOVE(entry, next);
4235                 rte_free(entry);
4236         }
4237
4238         pool->num_free = 0;
4239         pool->num_alloc = 0;
4240         pool->base = 0;
4241         LIST_INIT(&pool->alloc_list);
4242         LIST_INIT(&pool->free_list);
4243 }
4244
4245 static int
4246 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4247                        uint32_t base)
4248 {
4249         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4250         uint32_t pool_offset;
4251         int insert;
4252
4253         if (pool == NULL) {
4254                 PMD_DRV_LOG(ERR, "Invalid parameter");
4255                 return -EINVAL;
4256         }
4257
4258         pool_offset = base - pool->base;
4259         /* Lookup in alloc list */
4260         LIST_FOREACH(entry, &pool->alloc_list, next) {
4261                 if (entry->base == pool_offset) {
4262                         valid_entry = entry;
4263                         LIST_REMOVE(entry, next);
4264                         break;
4265                 }
4266         }
4267
4268         /* Not find, return */
4269         if (valid_entry == NULL) {
4270                 PMD_DRV_LOG(ERR, "Failed to find entry");
4271                 return -EINVAL;
4272         }
4273
4274         /**
4275          * Found it, move it to free list  and try to merge.
4276          * In order to make merge easier, always sort it by qbase.
4277          * Find adjacent prev and last entries.
4278          */
4279         prev = next = NULL;
4280         LIST_FOREACH(entry, &pool->free_list, next) {
4281                 if (entry->base > valid_entry->base) {
4282                         next = entry;
4283                         break;
4284                 }
4285                 prev = entry;
4286         }
4287
4288         insert = 0;
4289         /* Try to merge with next one*/
4290         if (next != NULL) {
4291                 /* Merge with next one */
4292                 if (valid_entry->base + valid_entry->len == next->base) {
4293                         next->base = valid_entry->base;
4294                         next->len += valid_entry->len;
4295                         rte_free(valid_entry);
4296                         valid_entry = next;
4297                         insert = 1;
4298                 }
4299         }
4300
4301         if (prev != NULL) {
4302                 /* Merge with previous one */
4303                 if (prev->base + prev->len == valid_entry->base) {
4304                         prev->len += valid_entry->len;
4305                         /* If it merge with next one, remove next node */
4306                         if (insert == 1) {
4307                                 LIST_REMOVE(valid_entry, next);
4308                                 rte_free(valid_entry);
4309                         } else {
4310                                 rte_free(valid_entry);
4311                                 insert = 1;
4312                         }
4313                 }
4314         }
4315
4316         /* Not find any entry to merge, insert */
4317         if (insert == 0) {
4318                 if (prev != NULL)
4319                         LIST_INSERT_AFTER(prev, valid_entry, next);
4320                 else if (next != NULL)
4321                         LIST_INSERT_BEFORE(next, valid_entry, next);
4322                 else /* It's empty list, insert to head */
4323                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4324         }
4325
4326         pool->num_free += valid_entry->len;
4327         pool->num_alloc -= valid_entry->len;
4328
4329         return 0;
4330 }
4331
4332 static int
4333 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4334                        uint16_t num)
4335 {
4336         struct pool_entry *entry, *valid_entry;
4337
4338         if (pool == NULL || num == 0) {
4339                 PMD_DRV_LOG(ERR, "Invalid parameter");
4340                 return -EINVAL;
4341         }
4342
4343         if (pool->num_free < num) {
4344                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4345                             num, pool->num_free);
4346                 return -ENOMEM;
4347         }
4348
4349         valid_entry = NULL;
4350         /* Lookup  in free list and find most fit one */
4351         LIST_FOREACH(entry, &pool->free_list, next) {
4352                 if (entry->len >= num) {
4353                         /* Find best one */
4354                         if (entry->len == num) {
4355                                 valid_entry = entry;
4356                                 break;
4357                         }
4358                         if (valid_entry == NULL || valid_entry->len > entry->len)
4359                                 valid_entry = entry;
4360                 }
4361         }
4362
4363         /* Not find one to satisfy the request, return */
4364         if (valid_entry == NULL) {
4365                 PMD_DRV_LOG(ERR, "No valid entry found");
4366                 return -ENOMEM;
4367         }
4368         /**
4369          * The entry have equal queue number as requested,
4370          * remove it from alloc_list.
4371          */
4372         if (valid_entry->len == num) {
4373                 LIST_REMOVE(valid_entry, next);
4374         } else {
4375                 /**
4376                  * The entry have more numbers than requested,
4377                  * create a new entry for alloc_list and minus its
4378                  * queue base and number in free_list.
4379                  */
4380                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4381                 if (entry == NULL) {
4382                         PMD_DRV_LOG(ERR,
4383                                 "Failed to allocate memory for resource pool");
4384                         return -ENOMEM;
4385                 }
4386                 entry->base = valid_entry->base;
4387                 entry->len = num;
4388                 valid_entry->base += num;
4389                 valid_entry->len -= num;
4390                 valid_entry = entry;
4391         }
4392
4393         /* Insert it into alloc list, not sorted */
4394         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4395
4396         pool->num_free -= valid_entry->len;
4397         pool->num_alloc += valid_entry->len;
4398
4399         return valid_entry->base + pool->base;
4400 }
4401
4402 /**
4403  * bitmap_is_subset - Check whether src2 is subset of src1
4404  **/
4405 static inline int
4406 bitmap_is_subset(uint8_t src1, uint8_t src2)
4407 {
4408         return !((src1 ^ src2) & src2);
4409 }
4410
4411 static enum i40e_status_code
4412 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4413 {
4414         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4415
4416         /* If DCB is not supported, only default TC is supported */
4417         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4418                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4419                 return I40E_NOT_SUPPORTED;
4420         }
4421
4422         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4423                 PMD_DRV_LOG(ERR,
4424                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4425                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4426                 return I40E_NOT_SUPPORTED;
4427         }
4428         return I40E_SUCCESS;
4429 }
4430
4431 int
4432 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4433                                 struct i40e_vsi_vlan_pvid_info *info)
4434 {
4435         struct i40e_hw *hw;
4436         struct i40e_vsi_context ctxt;
4437         uint8_t vlan_flags = 0;
4438         int ret;
4439
4440         if (vsi == NULL || info == NULL) {
4441                 PMD_DRV_LOG(ERR, "invalid parameters");
4442                 return I40E_ERR_PARAM;
4443         }
4444
4445         if (info->on) {
4446                 vsi->info.pvid = info->config.pvid;
4447                 /**
4448                  * If insert pvid is enabled, only tagged pkts are
4449                  * allowed to be sent out.
4450                  */
4451                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4452                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4453         } else {
4454                 vsi->info.pvid = 0;
4455                 if (info->config.reject.tagged == 0)
4456                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4457
4458                 if (info->config.reject.untagged == 0)
4459                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4460         }
4461         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4462                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4463         vsi->info.port_vlan_flags |= vlan_flags;
4464         vsi->info.valid_sections =
4465                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4466         memset(&ctxt, 0, sizeof(ctxt));
4467         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4468         ctxt.seid = vsi->seid;
4469
4470         hw = I40E_VSI_TO_HW(vsi);
4471         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4472         if (ret != I40E_SUCCESS)
4473                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4474
4475         return ret;
4476 }
4477
4478 static int
4479 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4480 {
4481         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4482         int i, ret;
4483         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4484
4485         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4486         if (ret != I40E_SUCCESS)
4487                 return ret;
4488
4489         if (!vsi->seid) {
4490                 PMD_DRV_LOG(ERR, "seid not valid");
4491                 return -EINVAL;
4492         }
4493
4494         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4495         tc_bw_data.tc_valid_bits = enabled_tcmap;
4496         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4497                 tc_bw_data.tc_bw_credits[i] =
4498                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4499
4500         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4501         if (ret != I40E_SUCCESS) {
4502                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4503                 return ret;
4504         }
4505
4506         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4507                                         sizeof(vsi->info.qs_handle));
4508         return I40E_SUCCESS;
4509 }
4510
4511 static enum i40e_status_code
4512 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4513                                  struct i40e_aqc_vsi_properties_data *info,
4514                                  uint8_t enabled_tcmap)
4515 {
4516         enum i40e_status_code ret;
4517         int i, total_tc = 0;
4518         uint16_t qpnum_per_tc, bsf, qp_idx;
4519
4520         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4521         if (ret != I40E_SUCCESS)
4522                 return ret;
4523
4524         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4525                 if (enabled_tcmap & (1 << i))
4526                         total_tc++;
4527         if (total_tc == 0)
4528                 total_tc = 1;
4529         vsi->enabled_tc = enabled_tcmap;
4530
4531         /* Number of queues per enabled TC */
4532         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4533         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4534         bsf = rte_bsf32(qpnum_per_tc);
4535
4536         /* Adjust the queue number to actual queues that can be applied */
4537         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4538                 vsi->nb_qps = qpnum_per_tc * total_tc;
4539
4540         /**
4541          * Configure TC and queue mapping parameters, for enabled TC,
4542          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4543          * default queue will serve it.
4544          */
4545         qp_idx = 0;
4546         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4547                 if (vsi->enabled_tc & (1 << i)) {
4548                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4549                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4550                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4551                         qp_idx += qpnum_per_tc;
4552                 } else
4553                         info->tc_mapping[i] = 0;
4554         }
4555
4556         /* Associate queue number with VSI */
4557         if (vsi->type == I40E_VSI_SRIOV) {
4558                 info->mapping_flags |=
4559                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4560                 for (i = 0; i < vsi->nb_qps; i++)
4561                         info->queue_mapping[i] =
4562                                 rte_cpu_to_le_16(vsi->base_queue + i);
4563         } else {
4564                 info->mapping_flags |=
4565                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4566                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4567         }
4568         info->valid_sections |=
4569                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4570
4571         return I40E_SUCCESS;
4572 }
4573
4574 static int
4575 i40e_veb_release(struct i40e_veb *veb)
4576 {
4577         struct i40e_vsi *vsi;
4578         struct i40e_hw *hw;
4579
4580         if (veb == NULL)
4581                 return -EINVAL;
4582
4583         if (!TAILQ_EMPTY(&veb->head)) {
4584                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4585                 return -EACCES;
4586         }
4587         /* associate_vsi field is NULL for floating VEB */
4588         if (veb->associate_vsi != NULL) {
4589                 vsi = veb->associate_vsi;
4590                 hw = I40E_VSI_TO_HW(vsi);
4591
4592                 vsi->uplink_seid = veb->uplink_seid;
4593                 vsi->veb = NULL;
4594         } else {
4595                 veb->associate_pf->main_vsi->floating_veb = NULL;
4596                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4597         }
4598
4599         i40e_aq_delete_element(hw, veb->seid, NULL);
4600         rte_free(veb);
4601         return I40E_SUCCESS;
4602 }
4603
4604 /* Setup a veb */
4605 static struct i40e_veb *
4606 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4607 {
4608         struct i40e_veb *veb;
4609         int ret;
4610         struct i40e_hw *hw;
4611
4612         if (pf == NULL) {
4613                 PMD_DRV_LOG(ERR,
4614                             "veb setup failed, associated PF shouldn't null");
4615                 return NULL;
4616         }
4617         hw = I40E_PF_TO_HW(pf);
4618
4619         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4620         if (!veb) {
4621                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4622                 goto fail;
4623         }
4624
4625         veb->associate_vsi = vsi;
4626         veb->associate_pf = pf;
4627         TAILQ_INIT(&veb->head);
4628         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4629
4630         /* create floating veb if vsi is NULL */
4631         if (vsi != NULL) {
4632                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4633                                       I40E_DEFAULT_TCMAP, false,
4634                                       &veb->seid, false, NULL);
4635         } else {
4636                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4637                                       true, &veb->seid, false, NULL);
4638         }
4639
4640         if (ret != I40E_SUCCESS) {
4641                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4642                             hw->aq.asq_last_status);
4643                 goto fail;
4644         }
4645         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4646
4647         /* get statistics index */
4648         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4649                                 &veb->stats_idx, NULL, NULL, NULL);
4650         if (ret != I40E_SUCCESS) {
4651                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4652                             hw->aq.asq_last_status);
4653                 goto fail;
4654         }
4655         /* Get VEB bandwidth, to be implemented */
4656         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4657         if (vsi)
4658                 vsi->uplink_seid = veb->seid;
4659
4660         return veb;
4661 fail:
4662         rte_free(veb);
4663         return NULL;
4664 }
4665
4666 int
4667 i40e_vsi_release(struct i40e_vsi *vsi)
4668 {
4669         struct i40e_pf *pf;
4670         struct i40e_hw *hw;
4671         struct i40e_vsi_list *vsi_list;
4672         void *temp;
4673         int ret;
4674         struct i40e_mac_filter *f;
4675         uint16_t user_param;
4676
4677         if (!vsi)
4678                 return I40E_SUCCESS;
4679
4680         if (!vsi->adapter)
4681                 return -EFAULT;
4682
4683         user_param = vsi->user_param;
4684
4685         pf = I40E_VSI_TO_PF(vsi);
4686         hw = I40E_VSI_TO_HW(vsi);
4687
4688         /* VSI has child to attach, release child first */
4689         if (vsi->veb) {
4690                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4691                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4692                                 return -1;
4693                 }
4694                 i40e_veb_release(vsi->veb);
4695         }
4696
4697         if (vsi->floating_veb) {
4698                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4699                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4700                                 return -1;
4701                 }
4702         }
4703
4704         /* Remove all macvlan filters of the VSI */
4705         i40e_vsi_remove_all_macvlan_filter(vsi);
4706         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4707                 rte_free(f);
4708
4709         if (vsi->type != I40E_VSI_MAIN &&
4710             ((vsi->type != I40E_VSI_SRIOV) ||
4711             !pf->floating_veb_list[user_param])) {
4712                 /* Remove vsi from parent's sibling list */
4713                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4714                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4715                         return I40E_ERR_PARAM;
4716                 }
4717                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4718                                 &vsi->sib_vsi_list, list);
4719
4720                 /* Remove all switch element of the VSI */
4721                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4722                 if (ret != I40E_SUCCESS)
4723                         PMD_DRV_LOG(ERR, "Failed to delete element");
4724         }
4725
4726         if ((vsi->type == I40E_VSI_SRIOV) &&
4727             pf->floating_veb_list[user_param]) {
4728                 /* Remove vsi from parent's sibling list */
4729                 if (vsi->parent_vsi == NULL ||
4730                     vsi->parent_vsi->floating_veb == NULL) {
4731                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4732                         return I40E_ERR_PARAM;
4733                 }
4734                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4735                              &vsi->sib_vsi_list, list);
4736
4737                 /* Remove all switch element of the VSI */
4738                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4739                 if (ret != I40E_SUCCESS)
4740                         PMD_DRV_LOG(ERR, "Failed to delete element");
4741         }
4742
4743         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4744
4745         if (vsi->type != I40E_VSI_SRIOV)
4746                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4747         rte_free(vsi);
4748
4749         return I40E_SUCCESS;
4750 }
4751
4752 static int
4753 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4754 {
4755         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4756         struct i40e_aqc_remove_macvlan_element_data def_filter;
4757         struct i40e_mac_filter_info filter;
4758         int ret;
4759
4760         if (vsi->type != I40E_VSI_MAIN)
4761                 return I40E_ERR_CONFIG;
4762         memset(&def_filter, 0, sizeof(def_filter));
4763         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4764                                         ETH_ADDR_LEN);
4765         def_filter.vlan_tag = 0;
4766         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4767                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4768         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4769         if (ret != I40E_SUCCESS) {
4770                 struct i40e_mac_filter *f;
4771                 struct ether_addr *mac;
4772
4773                 PMD_DRV_LOG(DEBUG,
4774                             "Cannot remove the default macvlan filter");
4775                 /* It needs to add the permanent mac into mac list */
4776                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4777                 if (f == NULL) {
4778                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4779                         return I40E_ERR_NO_MEMORY;
4780                 }
4781                 mac = &f->mac_info.mac_addr;
4782                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4783                                 ETH_ADDR_LEN);
4784                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4785                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4786                 vsi->mac_num++;
4787
4788                 return ret;
4789         }
4790         rte_memcpy(&filter.mac_addr,
4791                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4792         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4793         return i40e_vsi_add_mac(vsi, &filter);
4794 }
4795
4796 /*
4797  * i40e_vsi_get_bw_config - Query VSI BW Information
4798  * @vsi: the VSI to be queried
4799  *
4800  * Returns 0 on success, negative value on failure
4801  */
4802 static enum i40e_status_code
4803 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4804 {
4805         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4806         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4807         struct i40e_hw *hw = &vsi->adapter->hw;
4808         i40e_status ret;
4809         int i;
4810         uint32_t bw_max;
4811
4812         memset(&bw_config, 0, sizeof(bw_config));
4813         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4814         if (ret != I40E_SUCCESS) {
4815                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4816                             hw->aq.asq_last_status);
4817                 return ret;
4818         }
4819
4820         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4821         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4822                                         &ets_sla_config, NULL);
4823         if (ret != I40E_SUCCESS) {
4824                 PMD_DRV_LOG(ERR,
4825                         "VSI failed to get TC bandwdith configuration %u",
4826                         hw->aq.asq_last_status);
4827                 return ret;
4828         }
4829
4830         /* store and print out BW info */
4831         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4832         vsi->bw_info.bw_max = bw_config.max_bw;
4833         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4834         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4835         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4836                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4837                      I40E_16_BIT_WIDTH);
4838         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4839                 vsi->bw_info.bw_ets_share_credits[i] =
4840                                 ets_sla_config.share_credits[i];
4841                 vsi->bw_info.bw_ets_credits[i] =
4842                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4843                 /* 4 bits per TC, 4th bit is reserved */
4844                 vsi->bw_info.bw_ets_max[i] =
4845                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4846                                   RTE_LEN2MASK(3, uint8_t));
4847                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4848                             vsi->bw_info.bw_ets_share_credits[i]);
4849                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4850                             vsi->bw_info.bw_ets_credits[i]);
4851                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4852                             vsi->bw_info.bw_ets_max[i]);
4853         }
4854
4855         return I40E_SUCCESS;
4856 }
4857
4858 /* i40e_enable_pf_lb
4859  * @pf: pointer to the pf structure
4860  *
4861  * allow loopback on pf
4862  */
4863 static inline void
4864 i40e_enable_pf_lb(struct i40e_pf *pf)
4865 {
4866         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4867         struct i40e_vsi_context ctxt;
4868         int ret;
4869
4870         /* Use the FW API if FW >= v5.0 */
4871         if (hw->aq.fw_maj_ver < 5) {
4872                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4873                 return;
4874         }
4875
4876         memset(&ctxt, 0, sizeof(ctxt));
4877         ctxt.seid = pf->main_vsi_seid;
4878         ctxt.pf_num = hw->pf_id;
4879         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4880         if (ret) {
4881                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4882                             ret, hw->aq.asq_last_status);
4883                 return;
4884         }
4885         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4886         ctxt.info.valid_sections =
4887                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4888         ctxt.info.switch_id |=
4889                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4890
4891         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4892         if (ret)
4893                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4894                             hw->aq.asq_last_status);
4895 }
4896
4897 /* Setup a VSI */
4898 struct i40e_vsi *
4899 i40e_vsi_setup(struct i40e_pf *pf,
4900                enum i40e_vsi_type type,
4901                struct i40e_vsi *uplink_vsi,
4902                uint16_t user_param)
4903 {
4904         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4905         struct i40e_vsi *vsi;
4906         struct i40e_mac_filter_info filter;
4907         int ret;
4908         struct i40e_vsi_context ctxt;
4909         struct ether_addr broadcast =
4910                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4911
4912         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4913             uplink_vsi == NULL) {
4914                 PMD_DRV_LOG(ERR,
4915                         "VSI setup failed, VSI link shouldn't be NULL");
4916                 return NULL;
4917         }
4918
4919         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4920                 PMD_DRV_LOG(ERR,
4921                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4922                 return NULL;
4923         }
4924
4925         /* two situations
4926          * 1.type is not MAIN and uplink vsi is not NULL
4927          * If uplink vsi didn't setup VEB, create one first under veb field
4928          * 2.type is SRIOV and the uplink is NULL
4929          * If floating VEB is NULL, create one veb under floating veb field
4930          */
4931
4932         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4933             uplink_vsi->veb == NULL) {
4934                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4935
4936                 if (uplink_vsi->veb == NULL) {
4937                         PMD_DRV_LOG(ERR, "VEB setup failed");
4938                         return NULL;
4939                 }
4940                 /* set ALLOWLOOPBACk on pf, when veb is created */
4941                 i40e_enable_pf_lb(pf);
4942         }
4943
4944         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4945             pf->main_vsi->floating_veb == NULL) {
4946                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4947
4948                 if (pf->main_vsi->floating_veb == NULL) {
4949                         PMD_DRV_LOG(ERR, "VEB setup failed");
4950                         return NULL;
4951                 }
4952         }
4953
4954         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4955         if (!vsi) {
4956                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4957                 return NULL;
4958         }
4959         TAILQ_INIT(&vsi->mac_list);
4960         vsi->type = type;
4961         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4962         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4963         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4964         vsi->user_param = user_param;
4965         vsi->vlan_anti_spoof_on = 0;
4966         vsi->vlan_filter_on = 0;
4967         /* Allocate queues */
4968         switch (vsi->type) {
4969         case I40E_VSI_MAIN  :
4970                 vsi->nb_qps = pf->lan_nb_qps;
4971                 break;
4972         case I40E_VSI_SRIOV :
4973                 vsi->nb_qps = pf->vf_nb_qps;
4974                 break;
4975         case I40E_VSI_VMDQ2:
4976                 vsi->nb_qps = pf->vmdq_nb_qps;
4977                 break;
4978         case I40E_VSI_FDIR:
4979                 vsi->nb_qps = pf->fdir_nb_qps;
4980                 break;
4981         default:
4982                 goto fail_mem;
4983         }
4984         /*
4985          * The filter status descriptor is reported in rx queue 0,
4986          * while the tx queue for fdir filter programming has no
4987          * such constraints, can be non-zero queues.
4988          * To simplify it, choose FDIR vsi use queue 0 pair.
4989          * To make sure it will use queue 0 pair, queue allocation
4990          * need be done before this function is called
4991          */
4992         if (type != I40E_VSI_FDIR) {
4993                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4994                         if (ret < 0) {
4995                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4996                                                 vsi->seid, ret);
4997                                 goto fail_mem;
4998                         }
4999                         vsi->base_queue = ret;
5000         } else
5001                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5002
5003         /* VF has MSIX interrupt in VF range, don't allocate here */
5004         if (type == I40E_VSI_MAIN) {
5005                 ret = i40e_res_pool_alloc(&pf->msix_pool,
5006                                           RTE_MIN(vsi->nb_qps,
5007                                                   RTE_MAX_RXTX_INTR_VEC_ID));
5008                 if (ret < 0) {
5009                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5010                                     vsi->seid, ret);
5011                         goto fail_queue_alloc;
5012                 }
5013                 vsi->msix_intr = ret;
5014                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5015         } else if (type != I40E_VSI_SRIOV) {
5016                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5017                 if (ret < 0) {
5018                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5019                         goto fail_queue_alloc;
5020                 }
5021                 vsi->msix_intr = ret;
5022                 vsi->nb_msix = 1;
5023         } else {
5024                 vsi->msix_intr = 0;
5025                 vsi->nb_msix = 0;
5026         }
5027
5028         /* Add VSI */
5029         if (type == I40E_VSI_MAIN) {
5030                 /* For main VSI, no need to add since it's default one */
5031                 vsi->uplink_seid = pf->mac_seid;
5032                 vsi->seid = pf->main_vsi_seid;
5033                 /* Bind queues with specific MSIX interrupt */
5034                 /**
5035                  * Needs 2 interrupt at least, one for misc cause which will
5036                  * enabled from OS side, Another for queues binding the
5037                  * interrupt from device side only.
5038                  */
5039
5040                 /* Get default VSI parameters from hardware */
5041                 memset(&ctxt, 0, sizeof(ctxt));
5042                 ctxt.seid = vsi->seid;
5043                 ctxt.pf_num = hw->pf_id;
5044                 ctxt.uplink_seid = vsi->uplink_seid;
5045                 ctxt.vf_num = 0;
5046                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5047                 if (ret != I40E_SUCCESS) {
5048                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5049                         goto fail_msix_alloc;
5050                 }
5051                 rte_memcpy(&vsi->info, &ctxt.info,
5052                         sizeof(struct i40e_aqc_vsi_properties_data));
5053                 vsi->vsi_id = ctxt.vsi_number;
5054                 vsi->info.valid_sections = 0;
5055
5056                 /* Configure tc, enabled TC0 only */
5057                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5058                         I40E_SUCCESS) {
5059                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5060                         goto fail_msix_alloc;
5061                 }
5062
5063                 /* TC, queue mapping */
5064                 memset(&ctxt, 0, sizeof(ctxt));
5065                 vsi->info.valid_sections |=
5066                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5067                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5068                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5069                 rte_memcpy(&ctxt.info, &vsi->info,
5070                         sizeof(struct i40e_aqc_vsi_properties_data));
5071                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072                                                 I40E_DEFAULT_TCMAP);
5073                 if (ret != I40E_SUCCESS) {
5074                         PMD_DRV_LOG(ERR,
5075                                 "Failed to configure TC queue mapping");
5076                         goto fail_msix_alloc;
5077                 }
5078                 ctxt.seid = vsi->seid;
5079                 ctxt.pf_num = hw->pf_id;
5080                 ctxt.uplink_seid = vsi->uplink_seid;
5081                 ctxt.vf_num = 0;
5082
5083                 /* Update VSI parameters */
5084                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5085                 if (ret != I40E_SUCCESS) {
5086                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5087                         goto fail_msix_alloc;
5088                 }
5089
5090                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5091                                                 sizeof(vsi->info.tc_mapping));
5092                 rte_memcpy(&vsi->info.queue_mapping,
5093                                 &ctxt.info.queue_mapping,
5094                         sizeof(vsi->info.queue_mapping));
5095                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5096                 vsi->info.valid_sections = 0;
5097
5098                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5099                                 ETH_ADDR_LEN);
5100
5101                 /**
5102                  * Updating default filter settings are necessary to prevent
5103                  * reception of tagged packets.
5104                  * Some old firmware configurations load a default macvlan
5105                  * filter which accepts both tagged and untagged packets.
5106                  * The updating is to use a normal filter instead if needed.
5107                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5108                  * The firmware with correct configurations load the default
5109                  * macvlan filter which is expected and cannot be removed.
5110                  */
5111                 i40e_update_default_filter_setting(vsi);
5112                 i40e_config_qinq(hw, vsi);
5113         } else if (type == I40E_VSI_SRIOV) {
5114                 memset(&ctxt, 0, sizeof(ctxt));
5115                 /**
5116                  * For other VSI, the uplink_seid equals to uplink VSI's
5117                  * uplink_seid since they share same VEB
5118                  */
5119                 if (uplink_vsi == NULL)
5120                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5121                 else
5122                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5123                 ctxt.pf_num = hw->pf_id;
5124                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5125                 ctxt.uplink_seid = vsi->uplink_seid;
5126                 ctxt.connection_type = 0x1;
5127                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5128
5129                 /* Use the VEB configuration if FW >= v5.0 */
5130                 if (hw->aq.fw_maj_ver >= 5) {
5131                         /* Configure switch ID */
5132                         ctxt.info.valid_sections |=
5133                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5134                         ctxt.info.switch_id =
5135                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5136                 }
5137
5138                 /* Configure port/vlan */
5139                 ctxt.info.valid_sections |=
5140                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5141                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5142                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5143                                                 hw->func_caps.enabled_tcmap);
5144                 if (ret != I40E_SUCCESS) {
5145                         PMD_DRV_LOG(ERR,
5146                                 "Failed to configure TC queue mapping");
5147                         goto fail_msix_alloc;
5148                 }
5149
5150                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5151                 ctxt.info.valid_sections |=
5152                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5153                 /**
5154                  * Since VSI is not created yet, only configure parameter,
5155                  * will add vsi below.
5156                  */
5157
5158                 i40e_config_qinq(hw, vsi);
5159         } else if (type == I40E_VSI_VMDQ2) {
5160                 memset(&ctxt, 0, sizeof(ctxt));
5161                 /*
5162                  * For other VSI, the uplink_seid equals to uplink VSI's
5163                  * uplink_seid since they share same VEB
5164                  */
5165                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5166                 ctxt.pf_num = hw->pf_id;
5167                 ctxt.vf_num = 0;
5168                 ctxt.uplink_seid = vsi->uplink_seid;
5169                 ctxt.connection_type = 0x1;
5170                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5171
5172                 ctxt.info.valid_sections |=
5173                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5174                 /* user_param carries flag to enable loop back */
5175                 if (user_param) {
5176                         ctxt.info.switch_id =
5177                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5178                         ctxt.info.switch_id |=
5179                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5180                 }
5181
5182                 /* Configure port/vlan */
5183                 ctxt.info.valid_sections |=
5184                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5185                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5186                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5187                                                 I40E_DEFAULT_TCMAP);
5188                 if (ret != I40E_SUCCESS) {
5189                         PMD_DRV_LOG(ERR,
5190                                 "Failed to configure TC queue mapping");
5191                         goto fail_msix_alloc;
5192                 }
5193                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5194                 ctxt.info.valid_sections |=
5195                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5196         } else if (type == I40E_VSI_FDIR) {
5197                 memset(&ctxt, 0, sizeof(ctxt));
5198                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5199                 ctxt.pf_num = hw->pf_id;
5200                 ctxt.vf_num = 0;
5201                 ctxt.uplink_seid = vsi->uplink_seid;
5202                 ctxt.connection_type = 0x1;     /* regular data port */
5203                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5204                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5205                                                 I40E_DEFAULT_TCMAP);
5206                 if (ret != I40E_SUCCESS) {
5207                         PMD_DRV_LOG(ERR,
5208                                 "Failed to configure TC queue mapping.");
5209                         goto fail_msix_alloc;
5210                 }
5211                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5212                 ctxt.info.valid_sections |=
5213                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5214         } else {
5215                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5216                 goto fail_msix_alloc;
5217         }
5218
5219         if (vsi->type != I40E_VSI_MAIN) {
5220                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5221                 if (ret != I40E_SUCCESS) {
5222                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5223                                     hw->aq.asq_last_status);
5224                         goto fail_msix_alloc;
5225                 }
5226                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5227                 vsi->info.valid_sections = 0;
5228                 vsi->seid = ctxt.seid;
5229                 vsi->vsi_id = ctxt.vsi_number;
5230                 vsi->sib_vsi_list.vsi = vsi;
5231                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5232                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5233                                           &vsi->sib_vsi_list, list);
5234                 } else {
5235                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5236                                           &vsi->sib_vsi_list, list);
5237                 }
5238         }
5239
5240         /* MAC/VLAN configuration */
5241         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5242         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5243
5244         ret = i40e_vsi_add_mac(vsi, &filter);
5245         if (ret != I40E_SUCCESS) {
5246                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5247                 goto fail_msix_alloc;
5248         }
5249
5250         /* Get VSI BW information */
5251         i40e_vsi_get_bw_config(vsi);
5252         return vsi;
5253 fail_msix_alloc:
5254         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5255 fail_queue_alloc:
5256         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5257 fail_mem:
5258         rte_free(vsi);
5259         return NULL;
5260 }
5261
5262 /* Configure vlan filter on or off */
5263 int
5264 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5265 {
5266         int i, num;
5267         struct i40e_mac_filter *f;
5268         void *temp;
5269         struct i40e_mac_filter_info *mac_filter;
5270         enum rte_mac_filter_type desired_filter;
5271         int ret = I40E_SUCCESS;
5272
5273         if (on) {
5274                 /* Filter to match MAC and VLAN */
5275                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5276         } else {
5277                 /* Filter to match only MAC */
5278                 desired_filter = RTE_MAC_PERFECT_MATCH;
5279         }
5280
5281         num = vsi->mac_num;
5282
5283         mac_filter = rte_zmalloc("mac_filter_info_data",
5284                                  num * sizeof(*mac_filter), 0);
5285         if (mac_filter == NULL) {
5286                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5287                 return I40E_ERR_NO_MEMORY;
5288         }
5289
5290         i = 0;
5291
5292         /* Remove all existing mac */
5293         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5294                 mac_filter[i] = f->mac_info;
5295                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5296                 if (ret) {
5297                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5298                                     on ? "enable" : "disable");
5299                         goto DONE;
5300                 }
5301                 i++;
5302         }
5303
5304         /* Override with new filter */
5305         for (i = 0; i < num; i++) {
5306                 mac_filter[i].filter_type = desired_filter;
5307                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5308                 if (ret) {
5309                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5310                                     on ? "enable" : "disable");
5311                         goto DONE;
5312                 }
5313         }
5314
5315 DONE:
5316         rte_free(mac_filter);
5317         return ret;
5318 }
5319
5320 /* Configure vlan stripping on or off */
5321 int
5322 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5323 {
5324         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5325         struct i40e_vsi_context ctxt;
5326         uint8_t vlan_flags;
5327         int ret = I40E_SUCCESS;
5328
5329         /* Check if it has been already on or off */
5330         if (vsi->info.valid_sections &
5331                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5332                 if (on) {
5333                         if ((vsi->info.port_vlan_flags &
5334                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5335                                 return 0; /* already on */
5336                 } else {
5337                         if ((vsi->info.port_vlan_flags &
5338                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5339                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5340                                 return 0; /* already off */
5341                 }
5342         }
5343
5344         if (on)
5345                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5346         else
5347                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5348         vsi->info.valid_sections =
5349                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5350         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5351         vsi->info.port_vlan_flags |= vlan_flags;
5352         ctxt.seid = vsi->seid;
5353         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5354         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5355         if (ret)
5356                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5357                             on ? "enable" : "disable");
5358
5359         return ret;
5360 }
5361
5362 static int
5363 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5364 {
5365         struct rte_eth_dev_data *data = dev->data;
5366         int ret;
5367         int mask = 0;
5368
5369         /* Apply vlan offload setting */
5370         mask = ETH_VLAN_STRIP_MASK |
5371                ETH_VLAN_FILTER_MASK |
5372                ETH_VLAN_EXTEND_MASK;
5373         ret = i40e_vlan_offload_set(dev, mask);
5374         if (ret) {
5375                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5376                 return ret;
5377         }
5378
5379         /* Apply pvid setting */
5380         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5381                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5382         if (ret)
5383                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5384
5385         return ret;
5386 }
5387
5388 static int
5389 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5390 {
5391         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5392
5393         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5394 }
5395
5396 static int
5397 i40e_update_flow_control(struct i40e_hw *hw)
5398 {
5399 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5400         struct i40e_link_status link_status;
5401         uint32_t rxfc = 0, txfc = 0, reg;
5402         uint8_t an_info;
5403         int ret;
5404
5405         memset(&link_status, 0, sizeof(link_status));
5406         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5407         if (ret != I40E_SUCCESS) {
5408                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5409                 goto write_reg; /* Disable flow control */
5410         }
5411
5412         an_info = hw->phy.link_info.an_info;
5413         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5414                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5415                 ret = I40E_ERR_NOT_READY;
5416                 goto write_reg; /* Disable flow control */
5417         }
5418         /**
5419          * If link auto negotiation is enabled, flow control needs to
5420          * be configured according to it
5421          */
5422         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5423         case I40E_LINK_PAUSE_RXTX:
5424                 rxfc = 1;
5425                 txfc = 1;
5426                 hw->fc.current_mode = I40E_FC_FULL;
5427                 break;
5428         case I40E_AQ_LINK_PAUSE_RX:
5429                 rxfc = 1;
5430                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5431                 break;
5432         case I40E_AQ_LINK_PAUSE_TX:
5433                 txfc = 1;
5434                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5435                 break;
5436         default:
5437                 hw->fc.current_mode = I40E_FC_NONE;
5438                 break;
5439         }
5440
5441 write_reg:
5442         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5443                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5444         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5445         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5446         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5447         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5448
5449         return ret;
5450 }
5451
5452 /* PF setup */
5453 static int
5454 i40e_pf_setup(struct i40e_pf *pf)
5455 {
5456         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5457         struct i40e_filter_control_settings settings;
5458         struct i40e_vsi *vsi;
5459         int ret;
5460
5461         /* Clear all stats counters */
5462         pf->offset_loaded = FALSE;
5463         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5464         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5465         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5466         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5467
5468         ret = i40e_pf_get_switch_config(pf);
5469         if (ret != I40E_SUCCESS) {
5470                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5471                 return ret;
5472         }
5473         if (pf->flags & I40E_FLAG_FDIR) {
5474                 /* make queue allocated first, let FDIR use queue pair 0*/
5475                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5476                 if (ret != I40E_FDIR_QUEUE_ID) {
5477                         PMD_DRV_LOG(ERR,
5478                                 "queue allocation fails for FDIR: ret =%d",
5479                                 ret);
5480                         pf->flags &= ~I40E_FLAG_FDIR;
5481                 }
5482         }
5483         /*  main VSI setup */
5484         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5485         if (!vsi) {
5486                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5487                 return I40E_ERR_NOT_READY;
5488         }
5489         pf->main_vsi = vsi;
5490
5491         /* Configure filter control */
5492         memset(&settings, 0, sizeof(settings));
5493         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5494                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5495         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5496                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5497         else {
5498                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5499                         hw->func_caps.rss_table_size);
5500                 return I40E_ERR_PARAM;
5501         }
5502         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5503                 hw->func_caps.rss_table_size);
5504         pf->hash_lut_size = hw->func_caps.rss_table_size;
5505
5506         /* Enable ethtype and macvlan filters */
5507         settings.enable_ethtype = TRUE;
5508         settings.enable_macvlan = TRUE;
5509         ret = i40e_set_filter_control(hw, &settings);
5510         if (ret)
5511                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5512                                                                 ret);
5513
5514         /* Update flow control according to the auto negotiation */
5515         i40e_update_flow_control(hw);
5516
5517         return I40E_SUCCESS;
5518 }
5519
5520 int
5521 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5522 {
5523         uint32_t reg;
5524         uint16_t j;
5525
5526         /**
5527          * Set or clear TX Queue Disable flags,
5528          * which is required by hardware.
5529          */
5530         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5531         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5532
5533         /* Wait until the request is finished */
5534         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5535                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5536                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5537                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5538                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5539                                                         & 0x1))) {
5540                         break;
5541                 }
5542         }
5543         if (on) {
5544                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5545                         return I40E_SUCCESS; /* already on, skip next steps */
5546
5547                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5548                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5549         } else {
5550                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5551                         return I40E_SUCCESS; /* already off, skip next steps */
5552                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5553         }
5554         /* Write the register */
5555         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5556         /* Check the result */
5557         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5558                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5559                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5560                 if (on) {
5561                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5562                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5563                                 break;
5564                 } else {
5565                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5566                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5567                                 break;
5568                 }
5569         }
5570         /* Check if it is timeout */
5571         if (j >= I40E_CHK_Q_ENA_COUNT) {
5572                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5573                             (on ? "enable" : "disable"), q_idx);
5574                 return I40E_ERR_TIMEOUT;
5575         }
5576
5577         return I40E_SUCCESS;
5578 }
5579
5580 /* Swith on or off the tx queues */
5581 static int
5582 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5583 {
5584         struct rte_eth_dev_data *dev_data = pf->dev_data;
5585         struct i40e_tx_queue *txq;
5586         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5587         uint16_t i;
5588         int ret;
5589
5590         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5591                 txq = dev_data->tx_queues[i];
5592                 /* Don't operate the queue if not configured or
5593                  * if starting only per queue */
5594                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5595                         continue;
5596                 if (on)
5597                         ret = i40e_dev_tx_queue_start(dev, i);
5598                 else
5599                         ret = i40e_dev_tx_queue_stop(dev, i);
5600                 if ( ret != I40E_SUCCESS)
5601                         return ret;
5602         }
5603
5604         return I40E_SUCCESS;
5605 }
5606
5607 int
5608 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5609 {
5610         uint32_t reg;
5611         uint16_t j;
5612
5613         /* Wait until the request is finished */
5614         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5615                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5616                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5617                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5618                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5619                         break;
5620         }
5621
5622         if (on) {
5623                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5624                         return I40E_SUCCESS; /* Already on, skip next steps */
5625                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5626         } else {
5627                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5628                         return I40E_SUCCESS; /* Already off, skip next steps */
5629                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5630         }
5631
5632         /* Write the register */
5633         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5634         /* Check the result */
5635         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5636                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5637                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5638                 if (on) {
5639                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5640                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5641                                 break;
5642                 } else {
5643                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5644                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5645                                 break;
5646                 }
5647         }
5648
5649         /* Check if it is timeout */
5650         if (j >= I40E_CHK_Q_ENA_COUNT) {
5651                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5652                             (on ? "enable" : "disable"), q_idx);
5653                 return I40E_ERR_TIMEOUT;
5654         }
5655
5656         return I40E_SUCCESS;
5657 }
5658 /* Switch on or off the rx queues */
5659 static int
5660 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5661 {
5662         struct rte_eth_dev_data *dev_data = pf->dev_data;
5663         struct i40e_rx_queue *rxq;
5664         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5665         uint16_t i;
5666         int ret;
5667
5668         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5669                 rxq = dev_data->rx_queues[i];
5670                 /* Don't operate the queue if not configured or
5671                  * if starting only per queue */
5672                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5673                         continue;
5674                 if (on)
5675                         ret = i40e_dev_rx_queue_start(dev, i);
5676                 else
5677                         ret = i40e_dev_rx_queue_stop(dev, i);
5678                 if (ret != I40E_SUCCESS)
5679                         return ret;
5680         }
5681
5682         return I40E_SUCCESS;
5683 }
5684
5685 /* Switch on or off all the rx/tx queues */
5686 int
5687 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5688 {
5689         int ret;
5690
5691         if (on) {
5692                 /* enable rx queues before enabling tx queues */
5693                 ret = i40e_dev_switch_rx_queues(pf, on);
5694                 if (ret) {
5695                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5696                         return ret;
5697                 }
5698                 ret = i40e_dev_switch_tx_queues(pf, on);
5699         } else {
5700                 /* Stop tx queues before stopping rx queues */
5701                 ret = i40e_dev_switch_tx_queues(pf, on);
5702                 if (ret) {
5703                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5704                         return ret;
5705                 }
5706                 ret = i40e_dev_switch_rx_queues(pf, on);
5707         }
5708
5709         return ret;
5710 }
5711
5712 /* Initialize VSI for TX */
5713 static int
5714 i40e_dev_tx_init(struct i40e_pf *pf)
5715 {
5716         struct rte_eth_dev_data *data = pf->dev_data;
5717         uint16_t i;
5718         uint32_t ret = I40E_SUCCESS;
5719         struct i40e_tx_queue *txq;
5720
5721         for (i = 0; i < data->nb_tx_queues; i++) {
5722                 txq = data->tx_queues[i];
5723                 if (!txq || !txq->q_set)
5724                         continue;
5725                 ret = i40e_tx_queue_init(txq);
5726                 if (ret != I40E_SUCCESS)
5727                         break;
5728         }
5729         if (ret == I40E_SUCCESS)
5730                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5731                                      ->eth_dev);
5732
5733         return ret;
5734 }
5735
5736 /* Initialize VSI for RX */
5737 static int
5738 i40e_dev_rx_init(struct i40e_pf *pf)
5739 {
5740         struct rte_eth_dev_data *data = pf->dev_data;
5741         int ret = I40E_SUCCESS;
5742         uint16_t i;
5743         struct i40e_rx_queue *rxq;
5744
5745         i40e_pf_config_mq_rx(pf);
5746         for (i = 0; i < data->nb_rx_queues; i++) {
5747                 rxq = data->rx_queues[i];
5748                 if (!rxq || !rxq->q_set)
5749                         continue;
5750
5751                 ret = i40e_rx_queue_init(rxq);
5752                 if (ret != I40E_SUCCESS) {
5753                         PMD_DRV_LOG(ERR,
5754                                 "Failed to do RX queue initialization");
5755                         break;
5756                 }
5757         }
5758         if (ret == I40E_SUCCESS)
5759                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5760                                      ->eth_dev);
5761
5762         return ret;
5763 }
5764
5765 static int
5766 i40e_dev_rxtx_init(struct i40e_pf *pf)
5767 {
5768         int err;
5769
5770         err = i40e_dev_tx_init(pf);
5771         if (err) {
5772                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5773                 return err;
5774         }
5775         err = i40e_dev_rx_init(pf);
5776         if (err) {
5777                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5778                 return err;
5779         }
5780
5781         return err;
5782 }
5783
5784 static int
5785 i40e_vmdq_setup(struct rte_eth_dev *dev)
5786 {
5787         struct rte_eth_conf *conf = &dev->data->dev_conf;
5788         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5789         int i, err, conf_vsis, j, loop;
5790         struct i40e_vsi *vsi;
5791         struct i40e_vmdq_info *vmdq_info;
5792         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5793         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5794
5795         /*
5796          * Disable interrupt to avoid message from VF. Furthermore, it will
5797          * avoid race condition in VSI creation/destroy.
5798          */
5799         i40e_pf_disable_irq0(hw);
5800
5801         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5802                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5803                 return -ENOTSUP;
5804         }
5805
5806         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5807         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5808                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5809                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5810                         pf->max_nb_vmdq_vsi);
5811                 return -ENOTSUP;
5812         }
5813
5814         if (pf->vmdq != NULL) {
5815                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5816                 return 0;
5817         }
5818
5819         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5820                                 sizeof(*vmdq_info) * conf_vsis, 0);
5821
5822         if (pf->vmdq == NULL) {
5823                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5824                 return -ENOMEM;
5825         }
5826
5827         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5828
5829         /* Create VMDQ VSI */
5830         for (i = 0; i < conf_vsis; i++) {
5831                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5832                                 vmdq_conf->enable_loop_back);
5833                 if (vsi == NULL) {
5834                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5835                         err = -1;
5836                         goto err_vsi_setup;
5837                 }
5838                 vmdq_info = &pf->vmdq[i];
5839                 vmdq_info->pf = pf;
5840                 vmdq_info->vsi = vsi;
5841         }
5842         pf->nb_cfg_vmdq_vsi = conf_vsis;
5843
5844         /* Configure Vlan */
5845         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5846         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5847                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5848                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5849                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5850                                         vmdq_conf->pool_map[i].vlan_id, j);
5851
5852                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5853                                                 vmdq_conf->pool_map[i].vlan_id);
5854                                 if (err) {
5855                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5856                                         err = -1;
5857                                         goto err_vsi_setup;
5858                                 }
5859                         }
5860                 }
5861         }
5862
5863         i40e_pf_enable_irq0(hw);
5864
5865         return 0;
5866
5867 err_vsi_setup:
5868         for (i = 0; i < conf_vsis; i++)
5869                 if (pf->vmdq[i].vsi == NULL)
5870                         break;
5871                 else
5872                         i40e_vsi_release(pf->vmdq[i].vsi);
5873
5874         rte_free(pf->vmdq);
5875         pf->vmdq = NULL;
5876         i40e_pf_enable_irq0(hw);
5877         return err;
5878 }
5879
5880 static void
5881 i40e_stat_update_32(struct i40e_hw *hw,
5882                    uint32_t reg,
5883                    bool offset_loaded,
5884                    uint64_t *offset,
5885                    uint64_t *stat)
5886 {
5887         uint64_t new_data;
5888
5889         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5890         if (!offset_loaded)
5891                 *offset = new_data;
5892
5893         if (new_data >= *offset)
5894                 *stat = (uint64_t)(new_data - *offset);
5895         else
5896                 *stat = (uint64_t)((new_data +
5897                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5898 }
5899
5900 static void
5901 i40e_stat_update_48(struct i40e_hw *hw,
5902                    uint32_t hireg,
5903                    uint32_t loreg,
5904                    bool offset_loaded,
5905                    uint64_t *offset,
5906                    uint64_t *stat)
5907 {
5908         uint64_t new_data;
5909
5910         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5911         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5912                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5913
5914         if (!offset_loaded)
5915                 *offset = new_data;
5916
5917         if (new_data >= *offset)
5918                 *stat = new_data - *offset;
5919         else
5920                 *stat = (uint64_t)((new_data +
5921                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5922
5923         *stat &= I40E_48_BIT_MASK;
5924 }
5925
5926 /* Disable IRQ0 */
5927 void
5928 i40e_pf_disable_irq0(struct i40e_hw *hw)
5929 {
5930         /* Disable all interrupt types */
5931         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5932         I40E_WRITE_FLUSH(hw);
5933 }
5934
5935 /* Enable IRQ0 */
5936 void
5937 i40e_pf_enable_irq0(struct i40e_hw *hw)
5938 {
5939         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5940                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5941                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5942                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5943         I40E_WRITE_FLUSH(hw);
5944 }
5945
5946 static void
5947 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5948 {
5949         /* read pending request and disable first */
5950         i40e_pf_disable_irq0(hw);
5951         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5952         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5953                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5954
5955         if (no_queue)
5956                 /* Link no queues with irq0 */
5957                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5958                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5959 }
5960
5961 static void
5962 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5963 {
5964         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5965         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5966         int i;
5967         uint16_t abs_vf_id;
5968         uint32_t index, offset, val;
5969
5970         if (!pf->vfs)
5971                 return;
5972         /**
5973          * Try to find which VF trigger a reset, use absolute VF id to access
5974          * since the reg is global register.
5975          */
5976         for (i = 0; i < pf->vf_num; i++) {
5977                 abs_vf_id = hw->func_caps.vf_base_id + i;
5978                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5979                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5980                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5981                 /* VFR event occurred */
5982                 if (val & (0x1 << offset)) {
5983                         int ret;
5984
5985                         /* Clear the event first */
5986                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5987                                                         (0x1 << offset));
5988                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5989                         /**
5990                          * Only notify a VF reset event occurred,
5991                          * don't trigger another SW reset
5992                          */
5993                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5994                         if (ret != I40E_SUCCESS)
5995                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5996                 }
5997         }
5998 }
5999
6000 static void
6001 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6002 {
6003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6004         int i;
6005
6006         for (i = 0; i < pf->vf_num; i++)
6007                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6008 }
6009
6010 static void
6011 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6012 {
6013         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6014         struct i40e_arq_event_info info;
6015         uint16_t pending, opcode;
6016         int ret;
6017
6018         info.buf_len = I40E_AQ_BUF_SZ;
6019         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6020         if (!info.msg_buf) {
6021                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6022                 return;
6023         }
6024
6025         pending = 1;
6026         while (pending) {
6027                 ret = i40e_clean_arq_element(hw, &info, &pending);
6028
6029                 if (ret != I40E_SUCCESS) {
6030                         PMD_DRV_LOG(INFO,
6031                                 "Failed to read msg from AdminQ, aq_err: %u",
6032                                 hw->aq.asq_last_status);
6033                         break;
6034                 }
6035                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6036
6037                 switch (opcode) {
6038                 case i40e_aqc_opc_send_msg_to_pf:
6039                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6040                         i40e_pf_host_handle_vf_msg(dev,
6041                                         rte_le_to_cpu_16(info.desc.retval),
6042                                         rte_le_to_cpu_32(info.desc.cookie_high),
6043                                         rte_le_to_cpu_32(info.desc.cookie_low),
6044                                         info.msg_buf,
6045                                         info.msg_len);
6046                         break;
6047                 case i40e_aqc_opc_get_link_status:
6048                         ret = i40e_dev_link_update(dev, 0);
6049                         if (!ret)
6050                                 _rte_eth_dev_callback_process(dev,
6051                                         RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6052                         break;
6053                 default:
6054                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6055                                     opcode);
6056                         break;
6057                 }
6058         }
6059         rte_free(info.msg_buf);
6060 }
6061
6062 /**
6063  * Interrupt handler triggered by NIC  for handling
6064  * specific interrupt.
6065  *
6066  * @param handle
6067  *  Pointer to interrupt handle.
6068  * @param param
6069  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6070  *
6071  * @return
6072  *  void
6073  */
6074 static void
6075 i40e_dev_interrupt_handler(void *param)
6076 {
6077         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6078         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6079         uint32_t icr0;
6080
6081         /* Disable interrupt */
6082         i40e_pf_disable_irq0(hw);
6083
6084         /* read out interrupt causes */
6085         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6086
6087         /* No interrupt event indicated */
6088         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6089                 PMD_DRV_LOG(INFO, "No interrupt event");
6090                 goto done;
6091         }
6092         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6093                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6094         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6095                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6096         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6097                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6098         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6099                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6100         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6101                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6102         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6103                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6104         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6105                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6106
6107         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6108                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6109                 i40e_dev_handle_vfr_event(dev);
6110         }
6111         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6112                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6113                 i40e_dev_handle_aq_msg(dev);
6114         }
6115
6116 done:
6117         /* Enable interrupt */
6118         i40e_pf_enable_irq0(hw);
6119         rte_intr_enable(dev->intr_handle);
6120 }
6121
6122 int
6123 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6124                          struct i40e_macvlan_filter *filter,
6125                          int total)
6126 {
6127         int ele_num, ele_buff_size;
6128         int num, actual_num, i;
6129         uint16_t flags;
6130         int ret = I40E_SUCCESS;
6131         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6132         struct i40e_aqc_add_macvlan_element_data *req_list;
6133
6134         if (filter == NULL  || total == 0)
6135                 return I40E_ERR_PARAM;
6136         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6137         ele_buff_size = hw->aq.asq_buf_size;
6138
6139         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6140         if (req_list == NULL) {
6141                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6142                 return I40E_ERR_NO_MEMORY;
6143         }
6144
6145         num = 0;
6146         do {
6147                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6148                 memset(req_list, 0, ele_buff_size);
6149
6150                 for (i = 0; i < actual_num; i++) {
6151                         rte_memcpy(req_list[i].mac_addr,
6152                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6153                         req_list[i].vlan_tag =
6154                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6155
6156                         switch (filter[num + i].filter_type) {
6157                         case RTE_MAC_PERFECT_MATCH:
6158                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6159                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6160                                 break;
6161                         case RTE_MACVLAN_PERFECT_MATCH:
6162                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6163                                 break;
6164                         case RTE_MAC_HASH_MATCH:
6165                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6166                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6167                                 break;
6168                         case RTE_MACVLAN_HASH_MATCH:
6169                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6170                                 break;
6171                         default:
6172                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6173                                 ret = I40E_ERR_PARAM;
6174                                 goto DONE;
6175                         }
6176
6177                         req_list[i].queue_number = 0;
6178
6179                         req_list[i].flags = rte_cpu_to_le_16(flags);
6180                 }
6181
6182                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6183                                                 actual_num, NULL);
6184                 if (ret != I40E_SUCCESS) {
6185                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6186                         goto DONE;
6187                 }
6188                 num += actual_num;
6189         } while (num < total);
6190
6191 DONE:
6192         rte_free(req_list);
6193         return ret;
6194 }
6195
6196 int
6197 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6198                             struct i40e_macvlan_filter *filter,
6199                             int total)
6200 {
6201         int ele_num, ele_buff_size;
6202         int num, actual_num, i;
6203         uint16_t flags;
6204         int ret = I40E_SUCCESS;
6205         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6206         struct i40e_aqc_remove_macvlan_element_data *req_list;
6207
6208         if (filter == NULL  || total == 0)
6209                 return I40E_ERR_PARAM;
6210
6211         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6212         ele_buff_size = hw->aq.asq_buf_size;
6213
6214         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6215         if (req_list == NULL) {
6216                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6217                 return I40E_ERR_NO_MEMORY;
6218         }
6219
6220         num = 0;
6221         do {
6222                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6223                 memset(req_list, 0, ele_buff_size);
6224
6225                 for (i = 0; i < actual_num; i++) {
6226                         rte_memcpy(req_list[i].mac_addr,
6227                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6228                         req_list[i].vlan_tag =
6229                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6230
6231                         switch (filter[num + i].filter_type) {
6232                         case RTE_MAC_PERFECT_MATCH:
6233                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6234                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6235                                 break;
6236                         case RTE_MACVLAN_PERFECT_MATCH:
6237                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6238                                 break;
6239                         case RTE_MAC_HASH_MATCH:
6240                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6241                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6242                                 break;
6243                         case RTE_MACVLAN_HASH_MATCH:
6244                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6245                                 break;
6246                         default:
6247                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6248                                 ret = I40E_ERR_PARAM;
6249                                 goto DONE;
6250                         }
6251                         req_list[i].flags = rte_cpu_to_le_16(flags);
6252                 }
6253
6254                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6255                                                 actual_num, NULL);
6256                 if (ret != I40E_SUCCESS) {
6257                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6258                         goto DONE;
6259                 }
6260                 num += actual_num;
6261         } while (num < total);
6262
6263 DONE:
6264         rte_free(req_list);
6265         return ret;
6266 }
6267
6268 /* Find out specific MAC filter */
6269 static struct i40e_mac_filter *
6270 i40e_find_mac_filter(struct i40e_vsi *vsi,
6271                          struct ether_addr *macaddr)
6272 {
6273         struct i40e_mac_filter *f;
6274
6275         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6276                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6277                         return f;
6278         }
6279
6280         return NULL;
6281 }
6282
6283 static bool
6284 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6285                          uint16_t vlan_id)
6286 {
6287         uint32_t vid_idx, vid_bit;
6288
6289         if (vlan_id > ETH_VLAN_ID_MAX)
6290                 return 0;
6291
6292         vid_idx = I40E_VFTA_IDX(vlan_id);
6293         vid_bit = I40E_VFTA_BIT(vlan_id);
6294
6295         if (vsi->vfta[vid_idx] & vid_bit)
6296                 return 1;
6297         else
6298                 return 0;
6299 }
6300
6301 static void
6302 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6303                        uint16_t vlan_id, bool on)
6304 {
6305         uint32_t vid_idx, vid_bit;
6306
6307         vid_idx = I40E_VFTA_IDX(vlan_id);
6308         vid_bit = I40E_VFTA_BIT(vlan_id);
6309
6310         if (on)
6311                 vsi->vfta[vid_idx] |= vid_bit;
6312         else
6313                 vsi->vfta[vid_idx] &= ~vid_bit;
6314 }
6315
6316 void
6317 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6318                      uint16_t vlan_id, bool on)
6319 {
6320         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6321         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6322         int ret;
6323
6324         if (vlan_id > ETH_VLAN_ID_MAX)
6325                 return;
6326
6327         i40e_store_vlan_filter(vsi, vlan_id, on);
6328
6329         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6330                 return;
6331
6332         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6333
6334         if (on) {
6335                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6336                                        &vlan_data, 1, NULL);
6337                 if (ret != I40E_SUCCESS)
6338                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6339         } else {
6340                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6341                                           &vlan_data, 1, NULL);
6342                 if (ret != I40E_SUCCESS)
6343                         PMD_DRV_LOG(ERR,
6344                                     "Failed to remove vlan filter");
6345         }
6346 }
6347
6348 /**
6349  * Find all vlan options for specific mac addr,
6350  * return with actual vlan found.
6351  */
6352 int
6353 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6354                            struct i40e_macvlan_filter *mv_f,
6355                            int num, struct ether_addr *addr)
6356 {
6357         int i;
6358         uint32_t j, k;
6359
6360         /**
6361          * Not to use i40e_find_vlan_filter to decrease the loop time,
6362          * although the code looks complex.
6363           */
6364         if (num < vsi->vlan_num)
6365                 return I40E_ERR_PARAM;
6366
6367         i = 0;
6368         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6369                 if (vsi->vfta[j]) {
6370                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6371                                 if (vsi->vfta[j] & (1 << k)) {
6372                                         if (i > num - 1) {
6373                                                 PMD_DRV_LOG(ERR,
6374                                                         "vlan number doesn't match");
6375                                                 return I40E_ERR_PARAM;
6376                                         }
6377                                         rte_memcpy(&mv_f[i].macaddr,
6378                                                         addr, ETH_ADDR_LEN);
6379                                         mv_f[i].vlan_id =
6380                                                 j * I40E_UINT32_BIT_SIZE + k;
6381                                         i++;
6382                                 }
6383                         }
6384                 }
6385         }
6386         return I40E_SUCCESS;
6387 }
6388
6389 static inline int
6390 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6391                            struct i40e_macvlan_filter *mv_f,
6392                            int num,
6393                            uint16_t vlan)
6394 {
6395         int i = 0;
6396         struct i40e_mac_filter *f;
6397
6398         if (num < vsi->mac_num)
6399                 return I40E_ERR_PARAM;
6400
6401         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6402                 if (i > num - 1) {
6403                         PMD_DRV_LOG(ERR, "buffer number not match");
6404                         return I40E_ERR_PARAM;
6405                 }
6406                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6407                                 ETH_ADDR_LEN);
6408                 mv_f[i].vlan_id = vlan;
6409                 mv_f[i].filter_type = f->mac_info.filter_type;
6410                 i++;
6411         }
6412
6413         return I40E_SUCCESS;
6414 }
6415
6416 static int
6417 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6418 {
6419         int i, j, num;
6420         struct i40e_mac_filter *f;
6421         struct i40e_macvlan_filter *mv_f;
6422         int ret = I40E_SUCCESS;
6423
6424         if (vsi == NULL || vsi->mac_num == 0)
6425                 return I40E_ERR_PARAM;
6426
6427         /* Case that no vlan is set */
6428         if (vsi->vlan_num == 0)
6429                 num = vsi->mac_num;
6430         else
6431                 num = vsi->mac_num * vsi->vlan_num;
6432
6433         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6434         if (mv_f == NULL) {
6435                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6436                 return I40E_ERR_NO_MEMORY;
6437         }
6438
6439         i = 0;
6440         if (vsi->vlan_num == 0) {
6441                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6442                         rte_memcpy(&mv_f[i].macaddr,
6443                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6444                         mv_f[i].filter_type = f->mac_info.filter_type;
6445                         mv_f[i].vlan_id = 0;
6446                         i++;
6447                 }
6448         } else {
6449                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6450                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6451                                         vsi->vlan_num, &f->mac_info.mac_addr);
6452                         if (ret != I40E_SUCCESS)
6453                                 goto DONE;
6454                         for (j = i; j < i + vsi->vlan_num; j++)
6455                                 mv_f[j].filter_type = f->mac_info.filter_type;
6456                         i += vsi->vlan_num;
6457                 }
6458         }
6459
6460         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6461 DONE:
6462         rte_free(mv_f);
6463
6464         return ret;
6465 }
6466
6467 int
6468 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6469 {
6470         struct i40e_macvlan_filter *mv_f;
6471         int mac_num;
6472         int ret = I40E_SUCCESS;
6473
6474         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6475                 return I40E_ERR_PARAM;
6476
6477         /* If it's already set, just return */
6478         if (i40e_find_vlan_filter(vsi,vlan))
6479                 return I40E_SUCCESS;
6480
6481         mac_num = vsi->mac_num;
6482
6483         if (mac_num == 0) {
6484                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6485                 return I40E_ERR_PARAM;
6486         }
6487
6488         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6489
6490         if (mv_f == NULL) {
6491                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6492                 return I40E_ERR_NO_MEMORY;
6493         }
6494
6495         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6496
6497         if (ret != I40E_SUCCESS)
6498                 goto DONE;
6499
6500         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6501
6502         if (ret != I40E_SUCCESS)
6503                 goto DONE;
6504
6505         i40e_set_vlan_filter(vsi, vlan, 1);
6506
6507         vsi->vlan_num++;
6508         ret = I40E_SUCCESS;
6509 DONE:
6510         rte_free(mv_f);
6511         return ret;
6512 }
6513
6514 int
6515 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6516 {
6517         struct i40e_macvlan_filter *mv_f;
6518         int mac_num;
6519         int ret = I40E_SUCCESS;
6520
6521         /**
6522          * Vlan 0 is the generic filter for untagged packets
6523          * and can't be removed.
6524          */
6525         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6526                 return I40E_ERR_PARAM;
6527
6528         /* If can't find it, just return */
6529         if (!i40e_find_vlan_filter(vsi, vlan))
6530                 return I40E_ERR_PARAM;
6531
6532         mac_num = vsi->mac_num;
6533
6534         if (mac_num == 0) {
6535                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6536                 return I40E_ERR_PARAM;
6537         }
6538
6539         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6540
6541         if (mv_f == NULL) {
6542                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6543                 return I40E_ERR_NO_MEMORY;
6544         }
6545
6546         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6547
6548         if (ret != I40E_SUCCESS)
6549                 goto DONE;
6550
6551         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6552
6553         if (ret != I40E_SUCCESS)
6554                 goto DONE;
6555
6556         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6557         if (vsi->vlan_num == 1) {
6558                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6559                 if (ret != I40E_SUCCESS)
6560                         goto DONE;
6561
6562                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6563                 if (ret != I40E_SUCCESS)
6564                         goto DONE;
6565         }
6566
6567         i40e_set_vlan_filter(vsi, vlan, 0);
6568
6569         vsi->vlan_num--;
6570         ret = I40E_SUCCESS;
6571 DONE:
6572         rte_free(mv_f);
6573         return ret;
6574 }
6575
6576 int
6577 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6578 {
6579         struct i40e_mac_filter *f;
6580         struct i40e_macvlan_filter *mv_f;
6581         int i, vlan_num = 0;
6582         int ret = I40E_SUCCESS;
6583
6584         /* If it's add and we've config it, return */
6585         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6586         if (f != NULL)
6587                 return I40E_SUCCESS;
6588         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6589                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6590
6591                 /**
6592                  * If vlan_num is 0, that's the first time to add mac,
6593                  * set mask for vlan_id 0.
6594                  */
6595                 if (vsi->vlan_num == 0) {
6596                         i40e_set_vlan_filter(vsi, 0, 1);
6597                         vsi->vlan_num = 1;
6598                 }
6599                 vlan_num = vsi->vlan_num;
6600         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6601                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6602                 vlan_num = 1;
6603
6604         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6605         if (mv_f == NULL) {
6606                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6607                 return I40E_ERR_NO_MEMORY;
6608         }
6609
6610         for (i = 0; i < vlan_num; i++) {
6611                 mv_f[i].filter_type = mac_filter->filter_type;
6612                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6613                                 ETH_ADDR_LEN);
6614         }
6615
6616         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6617                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6618                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6619                                         &mac_filter->mac_addr);
6620                 if (ret != I40E_SUCCESS)
6621                         goto DONE;
6622         }
6623
6624         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6625         if (ret != I40E_SUCCESS)
6626                 goto DONE;
6627
6628         /* Add the mac addr into mac list */
6629         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6630         if (f == NULL) {
6631                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6632                 ret = I40E_ERR_NO_MEMORY;
6633                 goto DONE;
6634         }
6635         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6636                         ETH_ADDR_LEN);
6637         f->mac_info.filter_type = mac_filter->filter_type;
6638         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6639         vsi->mac_num++;
6640
6641         ret = I40E_SUCCESS;
6642 DONE:
6643         rte_free(mv_f);
6644
6645         return ret;
6646 }
6647
6648 int
6649 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6650 {
6651         struct i40e_mac_filter *f;
6652         struct i40e_macvlan_filter *mv_f;
6653         int i, vlan_num;
6654         enum rte_mac_filter_type filter_type;
6655         int ret = I40E_SUCCESS;
6656
6657         /* Can't find it, return an error */
6658         f = i40e_find_mac_filter(vsi, addr);
6659         if (f == NULL)
6660                 return I40E_ERR_PARAM;
6661
6662         vlan_num = vsi->vlan_num;
6663         filter_type = f->mac_info.filter_type;
6664         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6665                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6666                 if (vlan_num == 0) {
6667                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6668                         return I40E_ERR_PARAM;
6669                 }
6670         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6671                         filter_type == RTE_MAC_HASH_MATCH)
6672                 vlan_num = 1;
6673
6674         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6675         if (mv_f == NULL) {
6676                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6677                 return I40E_ERR_NO_MEMORY;
6678         }
6679
6680         for (i = 0; i < vlan_num; i++) {
6681                 mv_f[i].filter_type = filter_type;
6682                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6683                                 ETH_ADDR_LEN);
6684         }
6685         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6686                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6687                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6688                 if (ret != I40E_SUCCESS)
6689                         goto DONE;
6690         }
6691
6692         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6693         if (ret != I40E_SUCCESS)
6694                 goto DONE;
6695
6696         /* Remove the mac addr into mac list */
6697         TAILQ_REMOVE(&vsi->mac_list, f, next);
6698         rte_free(f);
6699         vsi->mac_num--;
6700
6701         ret = I40E_SUCCESS;
6702 DONE:
6703         rte_free(mv_f);
6704         return ret;
6705 }
6706
6707 /* Configure hash enable flags for RSS */
6708 uint64_t
6709 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6710 {
6711         uint64_t hena = 0;
6712         int i;
6713
6714         if (!flags)
6715                 return hena;
6716
6717         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6718                 if (flags & (1ULL << i))
6719                         hena |= adapter->pctypes_tbl[i];
6720         }
6721
6722         return hena;
6723 }
6724
6725 /* Parse the hash enable flags */
6726 uint64_t
6727 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6728 {
6729         uint64_t rss_hf = 0;
6730
6731         if (!flags)
6732                 return rss_hf;
6733         int i;
6734
6735         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6736                 if (flags & adapter->pctypes_tbl[i])
6737                         rss_hf |= (1ULL << i);
6738         }
6739         return rss_hf;
6740 }
6741
6742 /* Disable RSS */
6743 static void
6744 i40e_pf_disable_rss(struct i40e_pf *pf)
6745 {
6746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6747
6748         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6749         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6750         I40E_WRITE_FLUSH(hw);
6751 }
6752
6753 static int
6754 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6755 {
6756         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6757         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6758         int ret = 0;
6759
6760         if (!key || key_len == 0) {
6761                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6762                 return 0;
6763         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6764                 sizeof(uint32_t)) {
6765                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6766                 return -EINVAL;
6767         }
6768
6769         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6770                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6771                         (struct i40e_aqc_get_set_rss_key_data *)key;
6772
6773                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6774                 if (ret)
6775                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6776         } else {
6777                 uint32_t *hash_key = (uint32_t *)key;
6778                 uint16_t i;
6779
6780                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6781                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6782                 I40E_WRITE_FLUSH(hw);
6783         }
6784
6785         return ret;
6786 }
6787
6788 static int
6789 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6790 {
6791         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6792         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6793         int ret;
6794
6795         if (!key || !key_len)
6796                 return -EINVAL;
6797
6798         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6799                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6800                         (struct i40e_aqc_get_set_rss_key_data *)key);
6801                 if (ret) {
6802                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6803                         return ret;
6804                 }
6805         } else {
6806                 uint32_t *key_dw = (uint32_t *)key;
6807                 uint16_t i;
6808
6809                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6810                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6811         }
6812         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6813
6814         return 0;
6815 }
6816
6817 static int
6818 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6819 {
6820         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6821         uint64_t hena;
6822         int ret;
6823
6824         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6825                                rss_conf->rss_key_len);
6826         if (ret)
6827                 return ret;
6828
6829         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6830         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6831         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6832         I40E_WRITE_FLUSH(hw);
6833
6834         return 0;
6835 }
6836
6837 static int
6838 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6839                          struct rte_eth_rss_conf *rss_conf)
6840 {
6841         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6842         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6843         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6844         uint64_t hena;
6845
6846         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6847         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6848
6849         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6850                 if (rss_hf != 0) /* Enable RSS */
6851                         return -EINVAL;
6852                 return 0; /* Nothing to do */
6853         }
6854         /* RSS enabled */
6855         if (rss_hf == 0) /* Disable RSS */
6856                 return -EINVAL;
6857
6858         return i40e_hw_rss_hash_set(pf, rss_conf);
6859 }
6860
6861 static int
6862 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6863                            struct rte_eth_rss_conf *rss_conf)
6864 {
6865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867         uint64_t hena;
6868
6869         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6870                          &rss_conf->rss_key_len);
6871
6872         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6873         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6874         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6875
6876         return 0;
6877 }
6878
6879 static int
6880 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6881 {
6882         switch (filter_type) {
6883         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6884                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6885                 break;
6886         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6887                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6888                 break;
6889         case RTE_TUNNEL_FILTER_IMAC_TENID:
6890                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6891                 break;
6892         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6893                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6894                 break;
6895         case ETH_TUNNEL_FILTER_IMAC:
6896                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6897                 break;
6898         case ETH_TUNNEL_FILTER_OIP:
6899                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6900                 break;
6901         case ETH_TUNNEL_FILTER_IIP:
6902                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6903                 break;
6904         default:
6905                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6906                 return -EINVAL;
6907         }
6908
6909         return 0;
6910 }
6911
6912 /* Convert tunnel filter structure */
6913 static int
6914 i40e_tunnel_filter_convert(
6915         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6916         struct i40e_tunnel_filter *tunnel_filter)
6917 {
6918         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6919                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6920         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6921                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6922         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6923         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6924              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6925             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6926                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6927         else
6928                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6929         tunnel_filter->input.flags = cld_filter->element.flags;
6930         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6931         tunnel_filter->queue = cld_filter->element.queue_number;
6932         rte_memcpy(tunnel_filter->input.general_fields,
6933                    cld_filter->general_fields,
6934                    sizeof(cld_filter->general_fields));
6935
6936         return 0;
6937 }
6938
6939 /* Check if there exists the tunnel filter */
6940 struct i40e_tunnel_filter *
6941 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6942                              const struct i40e_tunnel_filter_input *input)
6943 {
6944         int ret;
6945
6946         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6947         if (ret < 0)
6948                 return NULL;
6949
6950         return tunnel_rule->hash_map[ret];
6951 }
6952
6953 /* Add a tunnel filter into the SW list */
6954 static int
6955 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6956                              struct i40e_tunnel_filter *tunnel_filter)
6957 {
6958         struct i40e_tunnel_rule *rule = &pf->tunnel;
6959         int ret;
6960
6961         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6962         if (ret < 0) {
6963                 PMD_DRV_LOG(ERR,
6964                             "Failed to insert tunnel filter to hash table %d!",
6965                             ret);
6966                 return ret;
6967         }
6968         rule->hash_map[ret] = tunnel_filter;
6969
6970         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6971
6972         return 0;
6973 }
6974
6975 /* Delete a tunnel filter from the SW list */
6976 int
6977 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6978                           struct i40e_tunnel_filter_input *input)
6979 {
6980         struct i40e_tunnel_rule *rule = &pf->tunnel;
6981         struct i40e_tunnel_filter *tunnel_filter;
6982         int ret;
6983
6984         ret = rte_hash_del_key(rule->hash_table, input);
6985         if (ret < 0) {
6986                 PMD_DRV_LOG(ERR,
6987                             "Failed to delete tunnel filter to hash table %d!",
6988                             ret);
6989                 return ret;
6990         }
6991         tunnel_filter = rule->hash_map[ret];
6992         rule->hash_map[ret] = NULL;
6993
6994         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6995         rte_free(tunnel_filter);
6996
6997         return 0;
6998 }
6999
7000 int
7001 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7002                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7003                         uint8_t add)
7004 {
7005         uint16_t ip_type;
7006         uint32_t ipv4_addr, ipv4_addr_le;
7007         uint8_t i, tun_type = 0;
7008         /* internal varialbe to convert ipv6 byte order */
7009         uint32_t convert_ipv6[4];
7010         int val, ret = 0;
7011         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7012         struct i40e_vsi *vsi = pf->main_vsi;
7013         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7014         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7015         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7016         struct i40e_tunnel_filter *tunnel, *node;
7017         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7018
7019         cld_filter = rte_zmalloc("tunnel_filter",
7020                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7021         0);
7022
7023         if (NULL == cld_filter) {
7024                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7025                 return -ENOMEM;
7026         }
7027         pfilter = cld_filter;
7028
7029         ether_addr_copy(&tunnel_filter->outer_mac,
7030                         (struct ether_addr *)&pfilter->element.outer_mac);
7031         ether_addr_copy(&tunnel_filter->inner_mac,
7032                         (struct ether_addr *)&pfilter->element.inner_mac);
7033
7034         pfilter->element.inner_vlan =
7035                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7036         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7037                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7038                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7039                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7040                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7041                                 &ipv4_addr_le,
7042                                 sizeof(pfilter->element.ipaddr.v4.data));
7043         } else {
7044                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7045                 for (i = 0; i < 4; i++) {
7046                         convert_ipv6[i] =
7047                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7048                 }
7049                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7050                            &convert_ipv6,
7051                            sizeof(pfilter->element.ipaddr.v6.data));
7052         }
7053
7054         /* check tunneled type */
7055         switch (tunnel_filter->tunnel_type) {
7056         case RTE_TUNNEL_TYPE_VXLAN:
7057                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7058                 break;
7059         case RTE_TUNNEL_TYPE_NVGRE:
7060                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7061                 break;
7062         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7063                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7064                 break;
7065         default:
7066                 /* Other tunnel types is not supported. */
7067                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7068                 rte_free(cld_filter);
7069                 return -EINVAL;
7070         }
7071
7072         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7073                                        &pfilter->element.flags);
7074         if (val < 0) {
7075                 rte_free(cld_filter);
7076                 return -EINVAL;
7077         }
7078
7079         pfilter->element.flags |= rte_cpu_to_le_16(
7080                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7081                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7082         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7083         pfilter->element.queue_number =
7084                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7085
7086         /* Check if there is the filter in SW list */
7087         memset(&check_filter, 0, sizeof(check_filter));
7088         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7089         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7090         if (add && node) {
7091                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7092                 return -EINVAL;
7093         }
7094
7095         if (!add && !node) {
7096                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7097                 return -EINVAL;
7098         }
7099
7100         if (add) {
7101                 ret = i40e_aq_add_cloud_filters(hw,
7102                                         vsi->seid, &cld_filter->element, 1);
7103                 if (ret < 0) {
7104                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7105                         return -ENOTSUP;
7106                 }
7107                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7108                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7109                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7110         } else {
7111                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7112                                                    &cld_filter->element, 1);
7113                 if (ret < 0) {
7114                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7115                         return -ENOTSUP;
7116                 }
7117                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7118         }
7119
7120         rte_free(cld_filter);
7121         return ret;
7122 }
7123
7124 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7125 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7126 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7127 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7128 #define I40E_TR_GRE_KEY_MASK                    0x400
7129 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7130 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7131
7132 static enum
7133 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7134 {
7135         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7136         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7138         enum i40e_status_code status = I40E_SUCCESS;
7139
7140         memset(&filter_replace, 0,
7141                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7142         memset(&filter_replace_buf, 0,
7143                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7144
7145         /* create L1 filter */
7146         filter_replace.old_filter_type =
7147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7148         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7149         filter_replace.tr_bit = 0;
7150
7151         /* Prepare the buffer, 3 entries */
7152         filter_replace_buf.data[0] =
7153                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7154         filter_replace_buf.data[0] |=
7155                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7156         filter_replace_buf.data[2] = 0xFF;
7157         filter_replace_buf.data[3] = 0xFF;
7158         filter_replace_buf.data[4] =
7159                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7160         filter_replace_buf.data[4] |=
7161                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7162         filter_replace_buf.data[7] = 0xF0;
7163         filter_replace_buf.data[8]
7164                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7165         filter_replace_buf.data[8] |=
7166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7167         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7168                 I40E_TR_GENEVE_KEY_MASK |
7169                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7170         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7171                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7172                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7173
7174         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7175                                                &filter_replace_buf);
7176         return status;
7177 }
7178
7179 static enum
7180 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7181 {
7182         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7183         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7185         enum i40e_status_code status = I40E_SUCCESS;
7186
7187         /* For MPLSoUDP */
7188         memset(&filter_replace, 0,
7189                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7190         memset(&filter_replace_buf, 0,
7191                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7192         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7193                 I40E_AQC_MIRROR_CLOUD_FILTER;
7194         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7195         filter_replace.new_filter_type =
7196                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7197         /* Prepare the buffer, 2 entries */
7198         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7199         filter_replace_buf.data[0] |=
7200                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7201         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7202         filter_replace_buf.data[4] |=
7203                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7204         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7205                                                &filter_replace_buf);
7206         if (status < 0)
7207                 return status;
7208
7209         /* For MPLSoGRE */
7210         memset(&filter_replace, 0,
7211                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7212         memset(&filter_replace_buf, 0,
7213                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7214
7215         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7216                 I40E_AQC_MIRROR_CLOUD_FILTER;
7217         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7218         filter_replace.new_filter_type =
7219                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7220         /* Prepare the buffer, 2 entries */
7221         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7222         filter_replace_buf.data[0] |=
7223                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7224         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7225         filter_replace_buf.data[4] |=
7226                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7227
7228         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7229                                                &filter_replace_buf);
7230         return status;
7231 }
7232
7233 static enum i40e_status_code
7234 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7235 {
7236         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7237         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7238         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7239         enum i40e_status_code status = I40E_SUCCESS;
7240
7241         /* For GTP-C */
7242         memset(&filter_replace, 0,
7243                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7244         memset(&filter_replace_buf, 0,
7245                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7246         /* create L1 filter */
7247         filter_replace.old_filter_type =
7248                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7249         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7250         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7251                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7252         /* Prepare the buffer, 2 entries */
7253         filter_replace_buf.data[0] =
7254                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7255         filter_replace_buf.data[0] |=
7256                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7257         filter_replace_buf.data[2] = 0xFF;
7258         filter_replace_buf.data[3] = 0xFF;
7259         filter_replace_buf.data[4] =
7260                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7261         filter_replace_buf.data[4] |=
7262                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7263         filter_replace_buf.data[6] = 0xFF;
7264         filter_replace_buf.data[7] = 0xFF;
7265         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7266                                                &filter_replace_buf);
7267         if (status < 0)
7268                 return status;
7269
7270         /* for GTP-U */
7271         memset(&filter_replace, 0,
7272                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7273         memset(&filter_replace_buf, 0,
7274                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7275         /* create L1 filter */
7276         filter_replace.old_filter_type =
7277                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7278         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7279         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7280                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7281         /* Prepare the buffer, 2 entries */
7282         filter_replace_buf.data[0] =
7283                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7284         filter_replace_buf.data[0] |=
7285                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7286         filter_replace_buf.data[2] = 0xFF;
7287         filter_replace_buf.data[3] = 0xFF;
7288         filter_replace_buf.data[4] =
7289                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7290         filter_replace_buf.data[4] |=
7291                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7292         filter_replace_buf.data[6] = 0xFF;
7293         filter_replace_buf.data[7] = 0xFF;
7294
7295         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7296                                                &filter_replace_buf);
7297         return status;
7298 }
7299
7300 static enum
7301 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7302 {
7303         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7304         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7305         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7306         enum i40e_status_code status = I40E_SUCCESS;
7307
7308         /* for GTP-C */
7309         memset(&filter_replace, 0,
7310                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7311         memset(&filter_replace_buf, 0,
7312                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7313         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7314         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7315         filter_replace.new_filter_type =
7316                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7317         /* Prepare the buffer, 2 entries */
7318         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7319         filter_replace_buf.data[0] |=
7320                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7321         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7322         filter_replace_buf.data[4] |=
7323                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7324         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7325                                                &filter_replace_buf);
7326         if (status < 0)
7327                 return status;
7328
7329         /* for GTP-U */
7330         memset(&filter_replace, 0,
7331                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7332         memset(&filter_replace_buf, 0,
7333                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7334         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7335         filter_replace.old_filter_type =
7336                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7337         filter_replace.new_filter_type =
7338                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7339         /* Prepare the buffer, 2 entries */
7340         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7341         filter_replace_buf.data[0] |=
7342                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7343         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7344         filter_replace_buf.data[4] |=
7345                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7346
7347         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7348                                                &filter_replace_buf);
7349         return status;
7350 }
7351
7352 int
7353 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7354                       struct i40e_tunnel_filter_conf *tunnel_filter,
7355                       uint8_t add)
7356 {
7357         uint16_t ip_type;
7358         uint32_t ipv4_addr, ipv4_addr_le;
7359         uint8_t i, tun_type = 0;
7360         /* internal variable to convert ipv6 byte order */
7361         uint32_t convert_ipv6[4];
7362         int val, ret = 0;
7363         struct i40e_pf_vf *vf = NULL;
7364         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7365         struct i40e_vsi *vsi;
7366         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7367         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7368         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7369         struct i40e_tunnel_filter *tunnel, *node;
7370         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7371         uint32_t teid_le;
7372         bool big_buffer = 0;
7373
7374         cld_filter = rte_zmalloc("tunnel_filter",
7375                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7376                          0);
7377
7378         if (cld_filter == NULL) {
7379                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7380                 return -ENOMEM;
7381         }
7382         pfilter = cld_filter;
7383
7384         ether_addr_copy(&tunnel_filter->outer_mac,
7385                         (struct ether_addr *)&pfilter->element.outer_mac);
7386         ether_addr_copy(&tunnel_filter->inner_mac,
7387                         (struct ether_addr *)&pfilter->element.inner_mac);
7388
7389         pfilter->element.inner_vlan =
7390                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7391         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7392                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7393                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7394                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7395                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7396                                 &ipv4_addr_le,
7397                                 sizeof(pfilter->element.ipaddr.v4.data));
7398         } else {
7399                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7400                 for (i = 0; i < 4; i++) {
7401                         convert_ipv6[i] =
7402                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7403                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7404                 }
7405                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7406                            &convert_ipv6,
7407                            sizeof(pfilter->element.ipaddr.v6.data));
7408         }
7409
7410         /* check tunneled type */
7411         switch (tunnel_filter->tunnel_type) {
7412         case I40E_TUNNEL_TYPE_VXLAN:
7413                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7414                 break;
7415         case I40E_TUNNEL_TYPE_NVGRE:
7416                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7417                 break;
7418         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7419                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7420                 break;
7421         case I40E_TUNNEL_TYPE_MPLSoUDP:
7422                 if (!pf->mpls_replace_flag) {
7423                         i40e_replace_mpls_l1_filter(pf);
7424                         i40e_replace_mpls_cloud_filter(pf);
7425                         pf->mpls_replace_flag = 1;
7426                 }
7427                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7428                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7429                         teid_le >> 4;
7430                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7431                         (teid_le & 0xF) << 12;
7432                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7433                         0x40;
7434                 big_buffer = 1;
7435                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7436                 break;
7437         case I40E_TUNNEL_TYPE_MPLSoGRE:
7438                 if (!pf->mpls_replace_flag) {
7439                         i40e_replace_mpls_l1_filter(pf);
7440                         i40e_replace_mpls_cloud_filter(pf);
7441                         pf->mpls_replace_flag = 1;
7442                 }
7443                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7444                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7445                         teid_le >> 4;
7446                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7447                         (teid_le & 0xF) << 12;
7448                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7449                         0x0;
7450                 big_buffer = 1;
7451                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7452                 break;
7453         case I40E_TUNNEL_TYPE_GTPC:
7454                 if (!pf->gtp_replace_flag) {
7455                         i40e_replace_gtp_l1_filter(pf);
7456                         i40e_replace_gtp_cloud_filter(pf);
7457                         pf->gtp_replace_flag = 1;
7458                 }
7459                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7460                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7461                         (teid_le >> 16) & 0xFFFF;
7462                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7463                         teid_le & 0xFFFF;
7464                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7465                         0x0;
7466                 big_buffer = 1;
7467                 break;
7468         case I40E_TUNNEL_TYPE_GTPU:
7469                 if (!pf->gtp_replace_flag) {
7470                         i40e_replace_gtp_l1_filter(pf);
7471                         i40e_replace_gtp_cloud_filter(pf);
7472                         pf->gtp_replace_flag = 1;
7473                 }
7474                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7475                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7476                         (teid_le >> 16) & 0xFFFF;
7477                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7478                         teid_le & 0xFFFF;
7479                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7480                         0x0;
7481                 big_buffer = 1;
7482                 break;
7483         case I40E_TUNNEL_TYPE_QINQ:
7484                 if (!pf->qinq_replace_flag) {
7485                         ret = i40e_cloud_filter_qinq_create(pf);
7486                         if (ret < 0)
7487                                 PMD_DRV_LOG(DEBUG,
7488                                             "QinQ tunnel filter already created.");
7489                         pf->qinq_replace_flag = 1;
7490                 }
7491                 /*      Add in the General fields the values of
7492                  *      the Outer and Inner VLAN
7493                  *      Big Buffer should be set, see changes in
7494                  *      i40e_aq_add_cloud_filters
7495                  */
7496                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7497                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7498                 big_buffer = 1;
7499                 break;
7500         default:
7501                 /* Other tunnel types is not supported. */
7502                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7503                 rte_free(cld_filter);
7504                 return -EINVAL;
7505         }
7506
7507         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7508                 pfilter->element.flags =
7509                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7510         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7511                 pfilter->element.flags =
7512                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7513         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7514                 pfilter->element.flags =
7515                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7516         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7517                 pfilter->element.flags =
7518                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7519         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7520                 pfilter->element.flags |=
7521                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7522         else {
7523                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7524                                                 &pfilter->element.flags);
7525                 if (val < 0) {
7526                         rte_free(cld_filter);
7527                         return -EINVAL;
7528                 }
7529         }
7530
7531         pfilter->element.flags |= rte_cpu_to_le_16(
7532                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7533                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7534         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7535         pfilter->element.queue_number =
7536                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7537
7538         if (!tunnel_filter->is_to_vf)
7539                 vsi = pf->main_vsi;
7540         else {
7541                 if (tunnel_filter->vf_id >= pf->vf_num) {
7542                         PMD_DRV_LOG(ERR, "Invalid argument.");
7543                         return -EINVAL;
7544                 }
7545                 vf = &pf->vfs[tunnel_filter->vf_id];
7546                 vsi = vf->vsi;
7547         }
7548
7549         /* Check if there is the filter in SW list */
7550         memset(&check_filter, 0, sizeof(check_filter));
7551         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7552         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7553         check_filter.vf_id = tunnel_filter->vf_id;
7554         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7555         if (add && node) {
7556                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7557                 return -EINVAL;
7558         }
7559
7560         if (!add && !node) {
7561                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7562                 return -EINVAL;
7563         }
7564
7565         if (add) {
7566                 if (big_buffer)
7567                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7568                                                    vsi->seid, cld_filter, 1);
7569                 else
7570                         ret = i40e_aq_add_cloud_filters(hw,
7571                                         vsi->seid, &cld_filter->element, 1);
7572                 if (ret < 0) {
7573                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7574                         return -ENOTSUP;
7575                 }
7576                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7577                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7578                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7579         } else {
7580                 if (big_buffer)
7581                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7582                                 hw, vsi->seid, cld_filter, 1);
7583                 else
7584                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7585                                                    &cld_filter->element, 1);
7586                 if (ret < 0) {
7587                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7588                         return -ENOTSUP;
7589                 }
7590                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7591         }
7592
7593         rte_free(cld_filter);
7594         return ret;
7595 }
7596
7597 static int
7598 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7599 {
7600         uint8_t i;
7601
7602         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7603                 if (pf->vxlan_ports[i] == port)
7604                         return i;
7605         }
7606
7607         return -1;
7608 }
7609
7610 static int
7611 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7612 {
7613         int  idx, ret;
7614         uint8_t filter_idx;
7615         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7616
7617         idx = i40e_get_vxlan_port_idx(pf, port);
7618
7619         /* Check if port already exists */
7620         if (idx >= 0) {
7621                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7622                 return -EINVAL;
7623         }
7624
7625         /* Now check if there is space to add the new port */
7626         idx = i40e_get_vxlan_port_idx(pf, 0);
7627         if (idx < 0) {
7628                 PMD_DRV_LOG(ERR,
7629                         "Maximum number of UDP ports reached, not adding port %d",
7630                         port);
7631                 return -ENOSPC;
7632         }
7633
7634         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7635                                         &filter_idx, NULL);
7636         if (ret < 0) {
7637                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7638                 return -1;
7639         }
7640
7641         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7642                          port,  filter_idx);
7643
7644         /* New port: add it and mark its index in the bitmap */
7645         pf->vxlan_ports[idx] = port;
7646         pf->vxlan_bitmap |= (1 << idx);
7647
7648         if (!(pf->flags & I40E_FLAG_VXLAN))
7649                 pf->flags |= I40E_FLAG_VXLAN;
7650
7651         return 0;
7652 }
7653
7654 static int
7655 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7656 {
7657         int idx;
7658         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7659
7660         if (!(pf->flags & I40E_FLAG_VXLAN)) {
7661                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7662                 return -EINVAL;
7663         }
7664
7665         idx = i40e_get_vxlan_port_idx(pf, port);
7666
7667         if (idx < 0) {
7668                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7669                 return -EINVAL;
7670         }
7671
7672         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7673                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7674                 return -1;
7675         }
7676
7677         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7678                         port, idx);
7679
7680         pf->vxlan_ports[idx] = 0;
7681         pf->vxlan_bitmap &= ~(1 << idx);
7682
7683         if (!pf->vxlan_bitmap)
7684                 pf->flags &= ~I40E_FLAG_VXLAN;
7685
7686         return 0;
7687 }
7688
7689 /* Add UDP tunneling port */
7690 static int
7691 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7692                              struct rte_eth_udp_tunnel *udp_tunnel)
7693 {
7694         int ret = 0;
7695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7696
7697         if (udp_tunnel == NULL)
7698                 return -EINVAL;
7699
7700         switch (udp_tunnel->prot_type) {
7701         case RTE_TUNNEL_TYPE_VXLAN:
7702                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7703                 break;
7704
7705         case RTE_TUNNEL_TYPE_GENEVE:
7706         case RTE_TUNNEL_TYPE_TEREDO:
7707                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7708                 ret = -1;
7709                 break;
7710
7711         default:
7712                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7713                 ret = -1;
7714                 break;
7715         }
7716
7717         return ret;
7718 }
7719
7720 /* Remove UDP tunneling port */
7721 static int
7722 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7723                              struct rte_eth_udp_tunnel *udp_tunnel)
7724 {
7725         int ret = 0;
7726         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7727
7728         if (udp_tunnel == NULL)
7729                 return -EINVAL;
7730
7731         switch (udp_tunnel->prot_type) {
7732         case RTE_TUNNEL_TYPE_VXLAN:
7733                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7734                 break;
7735         case RTE_TUNNEL_TYPE_GENEVE:
7736         case RTE_TUNNEL_TYPE_TEREDO:
7737                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7738                 ret = -1;
7739                 break;
7740         default:
7741                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7742                 ret = -1;
7743                 break;
7744         }
7745
7746         return ret;
7747 }
7748
7749 /* Calculate the maximum number of contiguous PF queues that are configured */
7750 static int
7751 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7752 {
7753         struct rte_eth_dev_data *data = pf->dev_data;
7754         int i, num;
7755         struct i40e_rx_queue *rxq;
7756
7757         num = 0;
7758         for (i = 0; i < pf->lan_nb_qps; i++) {
7759                 rxq = data->rx_queues[i];
7760                 if (rxq && rxq->q_set)
7761                         num++;
7762                 else
7763                         break;
7764         }
7765
7766         return num;
7767 }
7768
7769 /* Configure RSS */
7770 static int
7771 i40e_pf_config_rss(struct i40e_pf *pf)
7772 {
7773         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7774         struct rte_eth_rss_conf rss_conf;
7775         uint32_t i, lut = 0;
7776         uint16_t j, num;
7777
7778         /*
7779          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7780          * It's necessary to calculate the actual PF queues that are configured.
7781          */
7782         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7783                 num = i40e_pf_calc_configured_queues_num(pf);
7784         else
7785                 num = pf->dev_data->nb_rx_queues;
7786
7787         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7788         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7789                         num);
7790
7791         if (num == 0) {
7792                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7793                 return -ENOTSUP;
7794         }
7795
7796         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7797                 if (j == num)
7798                         j = 0;
7799                 lut = (lut << 8) | (j & ((0x1 <<
7800                         hw->func_caps.rss_table_entry_width) - 1));
7801                 if ((i & 3) == 3)
7802                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7803         }
7804
7805         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7806         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7807                 i40e_pf_disable_rss(pf);
7808                 return 0;
7809         }
7810         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7811                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7812                 /* Random default keys */
7813                 static uint32_t rss_key_default[] = {0x6b793944,
7814                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7815                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7816                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7817
7818                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7819                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7820                                                         sizeof(uint32_t);
7821         }
7822
7823         return i40e_hw_rss_hash_set(pf, &rss_conf);
7824 }
7825
7826 static int
7827 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7828                                struct rte_eth_tunnel_filter_conf *filter)
7829 {
7830         if (pf == NULL || filter == NULL) {
7831                 PMD_DRV_LOG(ERR, "Invalid parameter");
7832                 return -EINVAL;
7833         }
7834
7835         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7836                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7837                 return -EINVAL;
7838         }
7839
7840         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7841                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7842                 return -EINVAL;
7843         }
7844
7845         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7846                 (is_zero_ether_addr(&filter->outer_mac))) {
7847                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7848                 return -EINVAL;
7849         }
7850
7851         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7852                 (is_zero_ether_addr(&filter->inner_mac))) {
7853                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7854                 return -EINVAL;
7855         }
7856
7857         return 0;
7858 }
7859
7860 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7861 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7862 static int
7863 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7864 {
7865         uint32_t val, reg;
7866         int ret = -EINVAL;
7867
7868         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7869         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7870
7871         if (len == 3) {
7872                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7873         } else if (len == 4) {
7874                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7875         } else {
7876                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7877                 return ret;
7878         }
7879
7880         if (reg != val) {
7881                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7882                                                    reg, NULL);
7883                 if (ret != 0)
7884                         return ret;
7885         } else {
7886                 ret = 0;
7887         }
7888         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7889                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7890
7891         return ret;
7892 }
7893
7894 static int
7895 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7896 {
7897         int ret = -EINVAL;
7898
7899         if (!hw || !cfg)
7900                 return -EINVAL;
7901
7902         switch (cfg->cfg_type) {
7903         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7904                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7905                 break;
7906         default:
7907                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 static int
7915 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7916                                enum rte_filter_op filter_op,
7917                                void *arg)
7918 {
7919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7920         int ret = I40E_ERR_PARAM;
7921
7922         switch (filter_op) {
7923         case RTE_ETH_FILTER_SET:
7924                 ret = i40e_dev_global_config_set(hw,
7925                         (struct rte_eth_global_cfg *)arg);
7926                 break;
7927         default:
7928                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7929                 break;
7930         }
7931
7932         return ret;
7933 }
7934
7935 static int
7936 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7937                           enum rte_filter_op filter_op,
7938                           void *arg)
7939 {
7940         struct rte_eth_tunnel_filter_conf *filter;
7941         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7942         int ret = I40E_SUCCESS;
7943
7944         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7945
7946         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7947                 return I40E_ERR_PARAM;
7948
7949         switch (filter_op) {
7950         case RTE_ETH_FILTER_NOP:
7951                 if (!(pf->flags & I40E_FLAG_VXLAN))
7952                         ret = I40E_NOT_SUPPORTED;
7953                 break;
7954         case RTE_ETH_FILTER_ADD:
7955                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7956                 break;
7957         case RTE_ETH_FILTER_DELETE:
7958                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7959                 break;
7960         default:
7961                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7962                 ret = I40E_ERR_PARAM;
7963                 break;
7964         }
7965
7966         return ret;
7967 }
7968
7969 static int
7970 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7971 {
7972         int ret = 0;
7973         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7974
7975         /* RSS setup */
7976         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7977                 ret = i40e_pf_config_rss(pf);
7978         else
7979                 i40e_pf_disable_rss(pf);
7980
7981         return ret;
7982 }
7983
7984 /* Get the symmetric hash enable configurations per port */
7985 static void
7986 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7987 {
7988         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7989
7990         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7991 }
7992
7993 /* Set the symmetric hash enable configurations per port */
7994 static void
7995 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7996 {
7997         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7998
7999         if (enable > 0) {
8000                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8001                         PMD_DRV_LOG(INFO,
8002                                 "Symmetric hash has already been enabled");
8003                         return;
8004                 }
8005                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8006         } else {
8007                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8008                         PMD_DRV_LOG(INFO,
8009                                 "Symmetric hash has already been disabled");
8010                         return;
8011                 }
8012                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8013         }
8014         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8015         I40E_WRITE_FLUSH(hw);
8016 }
8017
8018 /*
8019  * Get global configurations of hash function type and symmetric hash enable
8020  * per flow type (pctype). Note that global configuration means it affects all
8021  * the ports on the same NIC.
8022  */
8023 static int
8024 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8025                                    struct rte_eth_hash_global_conf *g_cfg)
8026 {
8027         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8028         uint32_t reg;
8029         uint16_t i, j;
8030
8031         memset(g_cfg, 0, sizeof(*g_cfg));
8032         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8033         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8034                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8035         else
8036                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8037         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8038                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8039
8040         /*
8041          * We work only with lowest 32 bits which is not correct, but to work
8042          * properly the valid_bit_mask size should be increased up to 64 bits
8043          * and this will brake ABI. This modification will be done in next
8044          * release
8045          */
8046         g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8047
8048         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8049                 if (!adapter->pctypes_tbl[i])
8050                         continue;
8051                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8052                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8053                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8054                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8055                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8056                                         g_cfg->sym_hash_enable_mask[0] |=
8057                                                                 (1UL << i);
8058                                 }
8059                         }
8060                 }
8061         }
8062
8063         return 0;
8064 }
8065
8066 static int
8067 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8068                               const struct rte_eth_hash_global_conf *g_cfg)
8069 {
8070         uint32_t i;
8071         uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8072
8073         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8074                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8075                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8076                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8077                                                 g_cfg->hash_func);
8078                 return -EINVAL;
8079         }
8080
8081         /*
8082          * As i40e supports less than 32 flow types, only first 32 bits need to
8083          * be checked.
8084          */
8085         mask0 = g_cfg->valid_bit_mask[0];
8086         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8087                 if (i == 0) {
8088                         /* Check if any unsupported flow type configured */
8089                         if ((mask0 | i40e_mask) ^ i40e_mask)
8090                                 goto mask_err;
8091                 } else {
8092                         if (g_cfg->valid_bit_mask[i])
8093                                 goto mask_err;
8094                 }
8095         }
8096
8097         return 0;
8098
8099 mask_err:
8100         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8101
8102         return -EINVAL;
8103 }
8104
8105 /*
8106  * Set global configurations of hash function type and symmetric hash enable
8107  * per flow type (pctype). Note any modifying global configuration will affect
8108  * all the ports on the same NIC.
8109  */
8110 static int
8111 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8112                                    struct rte_eth_hash_global_conf *g_cfg)
8113 {
8114         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8115         int ret;
8116         uint16_t i, j;
8117         uint32_t reg;
8118         /*
8119          * We work only with lowest 32 bits which is not correct, but to work
8120          * properly the valid_bit_mask size should be increased up to 64 bits
8121          * and this will brake ABI. This modification will be done in next
8122          * release
8123          */
8124         uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8125                                         (uint32_t)adapter->flow_types_mask;
8126
8127         /* Check the input parameters */
8128         ret = i40e_hash_global_config_check(adapter, g_cfg);
8129         if (ret < 0)
8130                 return ret;
8131
8132         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8133                 if (mask0 & (1UL << i)) {
8134                         reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8135                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8136
8137                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8138                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8139                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8140                                         i40e_write_rx_ctl(hw,
8141                                                           I40E_GLQF_HSYM(j),
8142                                                           reg);
8143                         }
8144                 }
8145         }
8146
8147         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8148         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8149                 /* Toeplitz */
8150                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8151                         PMD_DRV_LOG(DEBUG,
8152                                 "Hash function already set to Toeplitz");
8153                         goto out;
8154                 }
8155                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8156         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8157                 /* Simple XOR */
8158                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8159                         PMD_DRV_LOG(DEBUG,
8160                                 "Hash function already set to Simple XOR");
8161                         goto out;
8162                 }
8163                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8164         } else
8165                 /* Use the default, and keep it as it is */
8166                 goto out;
8167
8168         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8169
8170 out:
8171         I40E_WRITE_FLUSH(hw);
8172
8173         return 0;
8174 }
8175
8176 /**
8177  * Valid input sets for hash and flow director filters per PCTYPE
8178  */
8179 static uint64_t
8180 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8181                 enum rte_filter_type filter)
8182 {
8183         uint64_t valid;
8184
8185         static const uint64_t valid_hash_inset_table[] = {
8186                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8187                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8188                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8189                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8190                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8191                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8192                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8193                         I40E_INSET_FLEX_PAYLOAD,
8194                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8195                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8196                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8197                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8198                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8199                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8200                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8202                         I40E_INSET_FLEX_PAYLOAD,
8203                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8204                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8205                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8206                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8207                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8208                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8209                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8210                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8211                         I40E_INSET_FLEX_PAYLOAD,
8212                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8213                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8214                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8216                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8217                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8218                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8219                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8220                         I40E_INSET_FLEX_PAYLOAD,
8221                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8222                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8223                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8225                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8226                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8227                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8228                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8229                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8230                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8231                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8232                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8233                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8234                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8235                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8236                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8237                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8238                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8239                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8240                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8241                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8242                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8243                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8244                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8245                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8246                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8247                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8248                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8249                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8250                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8252                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8253                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8254                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8255                         I40E_INSET_FLEX_PAYLOAD,
8256                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8257                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8258                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8259                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8260                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8261                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8262                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8263                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8264                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8265                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8266                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8267                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8268                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8269                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8270                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8271                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8272                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8273                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8274                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8275                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8276                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8277                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8278                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8279                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8280                         I40E_INSET_FLEX_PAYLOAD,
8281                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8282                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8283                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8285                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8286                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8287                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8288                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8289                         I40E_INSET_FLEX_PAYLOAD,
8290                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8291                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8292                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8294                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8295                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8296                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8297                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8298                         I40E_INSET_FLEX_PAYLOAD,
8299                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8300                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8301                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8302                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8303                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8304                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8305                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8306                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8307                         I40E_INSET_FLEX_PAYLOAD,
8308                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8309                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8310                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8311                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8312                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8313                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8314                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8315                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8316                         I40E_INSET_FLEX_PAYLOAD,
8317                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8318                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8319                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8321                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8322                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8323                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8324                         I40E_INSET_FLEX_PAYLOAD,
8325                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8326                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8327                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8328                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8329                         I40E_INSET_FLEX_PAYLOAD,
8330         };
8331
8332         /**
8333          * Flow director supports only fields defined in
8334          * union rte_eth_fdir_flow.
8335          */
8336         static const uint64_t valid_fdir_inset_table[] = {
8337                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8338                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8340                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8341                 I40E_INSET_IPV4_TTL,
8342                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8343                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8344                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8345                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8346                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8347                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8348                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8349                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8350                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8351                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8352                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8353                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8354                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8355                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8356                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8357                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8358                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8359                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8360                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8361                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8362                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8363                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8364                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8365                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8366                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8367                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8368                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8369                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8370                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8371                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8372                 I40E_INSET_SCTP_VT,
8373                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8374                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8375                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8376                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8377                 I40E_INSET_IPV4_TTL,
8378                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8379                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8380                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8381                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8382                 I40E_INSET_IPV6_HOP_LIMIT,
8383                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8384                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8385                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8386                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8387                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8388                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8389                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8390                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8391                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8392                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8393                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8394                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8395                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8396                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8397                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8398                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8399                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8400                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8401                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8402                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8403                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8404                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8405                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8406                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8407                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8408                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8409                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8410                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8412                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8413                 I40E_INSET_SCTP_VT,
8414                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8415                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8416                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8417                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8418                 I40E_INSET_IPV6_HOP_LIMIT,
8419                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8420                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8421                 I40E_INSET_LAST_ETHER_TYPE,
8422         };
8423
8424         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8425                 return 0;
8426         if (filter == RTE_ETH_FILTER_HASH)
8427                 valid = valid_hash_inset_table[pctype];
8428         else
8429                 valid = valid_fdir_inset_table[pctype];
8430
8431         return valid;
8432 }
8433
8434 /**
8435  * Validate if the input set is allowed for a specific PCTYPE
8436  */
8437 int
8438 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8439                 enum rte_filter_type filter, uint64_t inset)
8440 {
8441         uint64_t valid;
8442
8443         valid = i40e_get_valid_input_set(pctype, filter);
8444         if (inset & (~valid))
8445                 return -EINVAL;
8446
8447         return 0;
8448 }
8449
8450 /* default input set fields combination per pctype */
8451 uint64_t
8452 i40e_get_default_input_set(uint16_t pctype)
8453 {
8454         static const uint64_t default_inset_table[] = {
8455                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8456                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8457                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8458                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8459                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8460                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8461                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8462                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8463                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8464                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8465                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8466                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8467                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8468                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8469                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8470                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8471                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8472                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8473                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8474                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8475                         I40E_INSET_SCTP_VT,
8476                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8477                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8478                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8479                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8480                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8481                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8482                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8483                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8484                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8485                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8486                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8487                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8488                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8489                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8490                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8491                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8492                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8493                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8495                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8496                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8497                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8498                         I40E_INSET_SCTP_VT,
8499                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8500                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8501                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8502                         I40E_INSET_LAST_ETHER_TYPE,
8503         };
8504
8505         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8506                 return 0;
8507
8508         return default_inset_table[pctype];
8509 }
8510
8511 /**
8512  * Parse the input set from index to logical bit masks
8513  */
8514 static int
8515 i40e_parse_input_set(uint64_t *inset,
8516                      enum i40e_filter_pctype pctype,
8517                      enum rte_eth_input_set_field *field,
8518                      uint16_t size)
8519 {
8520         uint16_t i, j;
8521         int ret = -EINVAL;
8522
8523         static const struct {
8524                 enum rte_eth_input_set_field field;
8525                 uint64_t inset;
8526         } inset_convert_table[] = {
8527                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8528                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8529                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8530                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8531                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8532                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8533                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8534                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8535                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8536                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8537                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8538                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8539                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8540                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8541                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8542                         I40E_INSET_IPV6_NEXT_HDR},
8543                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8544                         I40E_INSET_IPV6_HOP_LIMIT},
8545                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8546                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8547                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8548                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8549                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8550                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8551                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8552                         I40E_INSET_SCTP_VT},
8553                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8554                         I40E_INSET_TUNNEL_DMAC},
8555                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8556                         I40E_INSET_VLAN_TUNNEL},
8557                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8558                         I40E_INSET_TUNNEL_ID},
8559                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8560                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8561                         I40E_INSET_FLEX_PAYLOAD_W1},
8562                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8563                         I40E_INSET_FLEX_PAYLOAD_W2},
8564                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8565                         I40E_INSET_FLEX_PAYLOAD_W3},
8566                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8567                         I40E_INSET_FLEX_PAYLOAD_W4},
8568                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8569                         I40E_INSET_FLEX_PAYLOAD_W5},
8570                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8571                         I40E_INSET_FLEX_PAYLOAD_W6},
8572                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8573                         I40E_INSET_FLEX_PAYLOAD_W7},
8574                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8575                         I40E_INSET_FLEX_PAYLOAD_W8},
8576         };
8577
8578         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8579                 return ret;
8580
8581         /* Only one item allowed for default or all */
8582         if (size == 1) {
8583                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8584                         *inset = i40e_get_default_input_set(pctype);
8585                         return 0;
8586                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8587                         *inset = I40E_INSET_NONE;
8588                         return 0;
8589                 }
8590         }
8591
8592         for (i = 0, *inset = 0; i < size; i++) {
8593                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8594                         if (field[i] == inset_convert_table[j].field) {
8595                                 *inset |= inset_convert_table[j].inset;
8596                                 break;
8597                         }
8598                 }
8599
8600                 /* It contains unsupported input set, return immediately */
8601                 if (j == RTE_DIM(inset_convert_table))
8602                         return ret;
8603         }
8604
8605         return 0;
8606 }
8607
8608 /**
8609  * Translate the input set from bit masks to register aware bit masks
8610  * and vice versa
8611  */
8612 uint64_t
8613 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8614 {
8615         uint64_t val = 0;
8616         uint16_t i;
8617
8618         struct inset_map {
8619                 uint64_t inset;
8620                 uint64_t inset_reg;
8621         };
8622
8623         static const struct inset_map inset_map_common[] = {
8624                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8625                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8626                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8627                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8628                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8629                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8630                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8631                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8632                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8633                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8634                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8635                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8636                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8637                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8638                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8639                 {I40E_INSET_TUNNEL_DMAC,
8640                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8641                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8642                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8643                 {I40E_INSET_TUNNEL_SRC_PORT,
8644                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8645                 {I40E_INSET_TUNNEL_DST_PORT,
8646                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8647                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8648                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8649                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8650                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8651                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8652                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8653                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8654                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8655                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8656         };
8657
8658     /* some different registers map in x722*/
8659         static const struct inset_map inset_map_diff_x722[] = {
8660                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8661                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8662                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8663                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8664         };
8665
8666         static const struct inset_map inset_map_diff_not_x722[] = {
8667                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8668                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8669                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8670                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8671         };
8672
8673         if (input == 0)
8674                 return val;
8675
8676         /* Translate input set to register aware inset */
8677         if (type == I40E_MAC_X722) {
8678                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8679                         if (input & inset_map_diff_x722[i].inset)
8680                                 val |= inset_map_diff_x722[i].inset_reg;
8681                 }
8682         } else {
8683                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8684                         if (input & inset_map_diff_not_x722[i].inset)
8685                                 val |= inset_map_diff_not_x722[i].inset_reg;
8686                 }
8687         }
8688
8689         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8690                 if (input & inset_map_common[i].inset)
8691                         val |= inset_map_common[i].inset_reg;
8692         }
8693
8694         return val;
8695 }
8696
8697 int
8698 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8699 {
8700         uint8_t i, idx = 0;
8701         uint64_t inset_need_mask = inset;
8702
8703         static const struct {
8704                 uint64_t inset;
8705                 uint32_t mask;
8706         } inset_mask_map[] = {
8707                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8708                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8709                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8710                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8711                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8712                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8713                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8714                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8715         };
8716
8717         if (!inset || !mask || !nb_elem)
8718                 return 0;
8719
8720         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8721                 /* Clear the inset bit, if no MASK is required,
8722                  * for example proto + ttl
8723                  */
8724                 if ((inset & inset_mask_map[i].inset) ==
8725                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8726                         inset_need_mask &= ~inset_mask_map[i].inset;
8727                 if (!inset_need_mask)
8728                         return 0;
8729         }
8730         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8731                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8732                     inset_mask_map[i].inset) {
8733                         if (idx >= nb_elem) {
8734                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8735                                 return -EINVAL;
8736                         }
8737                         mask[idx] = inset_mask_map[i].mask;
8738                         idx++;
8739                 }
8740         }
8741
8742         return idx;
8743 }
8744
8745 void
8746 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8747 {
8748         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8749
8750         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8751         if (reg != val)
8752                 i40e_write_rx_ctl(hw, addr, val);
8753         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8754                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8755 }
8756
8757 static void
8758 i40e_filter_input_set_init(struct i40e_pf *pf)
8759 {
8760         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8761         enum i40e_filter_pctype pctype;
8762         uint64_t input_set, inset_reg;
8763         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8764         int num, i;
8765         uint16_t flow_type;
8766
8767         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8768              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8769                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8770
8771                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8772                         continue;
8773
8774                 input_set = i40e_get_default_input_set(pctype);
8775
8776                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8777                                                    I40E_INSET_MASK_NUM_REG);
8778                 if (num < 0)
8779                         return;
8780                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8781                                         input_set);
8782
8783                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8784                                       (uint32_t)(inset_reg & UINT32_MAX));
8785                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8786                                      (uint32_t)((inset_reg >>
8787                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8788                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8789                                       (uint32_t)(inset_reg & UINT32_MAX));
8790                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8791                                      (uint32_t)((inset_reg >>
8792                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8793
8794                 for (i = 0; i < num; i++) {
8795                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8796                                              mask_reg[i]);
8797                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8798                                              mask_reg[i]);
8799                 }
8800                 /*clear unused mask registers of the pctype */
8801                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8802                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8803                                              0);
8804                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8805                                              0);
8806                 }
8807                 I40E_WRITE_FLUSH(hw);
8808
8809                 /* store the default input set */
8810                 pf->hash_input_set[pctype] = input_set;
8811                 pf->fdir.input_set[pctype] = input_set;
8812         }
8813 }
8814
8815 int
8816 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8817                          struct rte_eth_input_set_conf *conf)
8818 {
8819         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8820         enum i40e_filter_pctype pctype;
8821         uint64_t input_set, inset_reg = 0;
8822         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8823         int ret, i, num;
8824
8825         if (!conf) {
8826                 PMD_DRV_LOG(ERR, "Invalid pointer");
8827                 return -EFAULT;
8828         }
8829         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8830             conf->op != RTE_ETH_INPUT_SET_ADD) {
8831                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8832                 return -EINVAL;
8833         }
8834
8835         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8836         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8837                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8838                 return -EINVAL;
8839         }
8840
8841         if (hw->mac.type == I40E_MAC_X722) {
8842                 /* get translated pctype value in fd pctype register */
8843                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8844                         I40E_GLQF_FD_PCTYPES((int)pctype));
8845         }
8846
8847         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8848                                    conf->inset_size);
8849         if (ret) {
8850                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8851                 return -EINVAL;
8852         }
8853
8854         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8855                 /* get inset value in register */
8856                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8857                 inset_reg <<= I40E_32_BIT_WIDTH;
8858                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8859                 input_set |= pf->hash_input_set[pctype];
8860         }
8861         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8862                                            I40E_INSET_MASK_NUM_REG);
8863         if (num < 0)
8864                 return -EINVAL;
8865
8866         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8867
8868         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8869                               (uint32_t)(inset_reg & UINT32_MAX));
8870         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8871                              (uint32_t)((inset_reg >>
8872                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8873
8874         for (i = 0; i < num; i++)
8875                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8876                                      mask_reg[i]);
8877         /*clear unused mask registers of the pctype */
8878         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8879                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8880                                      0);
8881         I40E_WRITE_FLUSH(hw);
8882
8883         pf->hash_input_set[pctype] = input_set;
8884         return 0;
8885 }
8886
8887 int
8888 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8889                          struct rte_eth_input_set_conf *conf)
8890 {
8891         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8892         enum i40e_filter_pctype pctype;
8893         uint64_t input_set, inset_reg = 0;
8894         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8895         int ret, i, num;
8896
8897         if (!hw || !conf) {
8898                 PMD_DRV_LOG(ERR, "Invalid pointer");
8899                 return -EFAULT;
8900         }
8901         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8902             conf->op != RTE_ETH_INPUT_SET_ADD) {
8903                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8904                 return -EINVAL;
8905         }
8906
8907         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8908
8909         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8910                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8911                 return -EINVAL;
8912         }
8913
8914         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8915                                    conf->inset_size);
8916         if (ret) {
8917                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8918                 return -EINVAL;
8919         }
8920
8921         /* get inset value in register */
8922         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8923         inset_reg <<= I40E_32_BIT_WIDTH;
8924         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8925
8926         /* Can not change the inset reg for flex payload for fdir,
8927          * it is done by writing I40E_PRTQF_FD_FLXINSET
8928          * in i40e_set_flex_mask_on_pctype.
8929          */
8930         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8931                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8932         else
8933                 input_set |= pf->fdir.input_set[pctype];
8934         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8935                                            I40E_INSET_MASK_NUM_REG);
8936         if (num < 0)
8937                 return -EINVAL;
8938
8939         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8940
8941         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8942                               (uint32_t)(inset_reg & UINT32_MAX));
8943         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8944                              (uint32_t)((inset_reg >>
8945                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8946
8947         for (i = 0; i < num; i++)
8948                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8949                                      mask_reg[i]);
8950         /*clear unused mask registers of the pctype */
8951         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8952                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8953                                      0);
8954         I40E_WRITE_FLUSH(hw);
8955
8956         pf->fdir.input_set[pctype] = input_set;
8957         return 0;
8958 }
8959
8960 static int
8961 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8962 {
8963         int ret = 0;
8964
8965         if (!hw || !info) {
8966                 PMD_DRV_LOG(ERR, "Invalid pointer");
8967                 return -EFAULT;
8968         }
8969
8970         switch (info->info_type) {
8971         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8972                 i40e_get_symmetric_hash_enable_per_port(hw,
8973                                         &(info->info.enable));
8974                 break;
8975         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8976                 ret = i40e_get_hash_filter_global_config(hw,
8977                                 &(info->info.global_conf));
8978                 break;
8979         default:
8980                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8981                                                         info->info_type);
8982                 ret = -EINVAL;
8983                 break;
8984         }
8985
8986         return ret;
8987 }
8988
8989 static int
8990 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8991 {
8992         int ret = 0;
8993
8994         if (!hw || !info) {
8995                 PMD_DRV_LOG(ERR, "Invalid pointer");
8996                 return -EFAULT;
8997         }
8998
8999         switch (info->info_type) {
9000         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9001                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9002                 break;
9003         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9004                 ret = i40e_set_hash_filter_global_config(hw,
9005                                 &(info->info.global_conf));
9006                 break;
9007         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9008                 ret = i40e_hash_filter_inset_select(hw,
9009                                                &(info->info.input_set_conf));
9010                 break;
9011
9012         default:
9013                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9014                                                         info->info_type);
9015                 ret = -EINVAL;
9016                 break;
9017         }
9018
9019         return ret;
9020 }
9021
9022 /* Operations for hash function */
9023 static int
9024 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9025                       enum rte_filter_op filter_op,
9026                       void *arg)
9027 {
9028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9029         int ret = 0;
9030
9031         switch (filter_op) {
9032         case RTE_ETH_FILTER_NOP:
9033                 break;
9034         case RTE_ETH_FILTER_GET:
9035                 ret = i40e_hash_filter_get(hw,
9036                         (struct rte_eth_hash_filter_info *)arg);
9037                 break;
9038         case RTE_ETH_FILTER_SET:
9039                 ret = i40e_hash_filter_set(hw,
9040                         (struct rte_eth_hash_filter_info *)arg);
9041                 break;
9042         default:
9043                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9044                                                                 filter_op);
9045                 ret = -ENOTSUP;
9046                 break;
9047         }
9048
9049         return ret;
9050 }
9051
9052 /* Convert ethertype filter structure */
9053 static int
9054 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9055                               struct i40e_ethertype_filter *filter)
9056 {
9057         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9058         filter->input.ether_type = input->ether_type;
9059         filter->flags = input->flags;
9060         filter->queue = input->queue;
9061
9062         return 0;
9063 }
9064
9065 /* Check if there exists the ehtertype filter */
9066 struct i40e_ethertype_filter *
9067 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9068                                 const struct i40e_ethertype_filter_input *input)
9069 {
9070         int ret;
9071
9072         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9073         if (ret < 0)
9074                 return NULL;
9075
9076         return ethertype_rule->hash_map[ret];
9077 }
9078
9079 /* Add ethertype filter in SW list */
9080 static int
9081 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9082                                 struct i40e_ethertype_filter *filter)
9083 {
9084         struct i40e_ethertype_rule *rule = &pf->ethertype;
9085         int ret;
9086
9087         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9088         if (ret < 0) {
9089                 PMD_DRV_LOG(ERR,
9090                             "Failed to insert ethertype filter"
9091                             " to hash table %d!",
9092                             ret);
9093                 return ret;
9094         }
9095         rule->hash_map[ret] = filter;
9096
9097         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9098
9099         return 0;
9100 }
9101
9102 /* Delete ethertype filter in SW list */
9103 int
9104 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9105                              struct i40e_ethertype_filter_input *input)
9106 {
9107         struct i40e_ethertype_rule *rule = &pf->ethertype;
9108         struct i40e_ethertype_filter *filter;
9109         int ret;
9110
9111         ret = rte_hash_del_key(rule->hash_table, input);
9112         if (ret < 0) {
9113                 PMD_DRV_LOG(ERR,
9114                             "Failed to delete ethertype filter"
9115                             " to hash table %d!",
9116                             ret);
9117                 return ret;
9118         }
9119         filter = rule->hash_map[ret];
9120         rule->hash_map[ret] = NULL;
9121
9122         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9123         rte_free(filter);
9124
9125         return 0;
9126 }
9127
9128 /*
9129  * Configure ethertype filter, which can director packet by filtering
9130  * with mac address and ether_type or only ether_type
9131  */
9132 int
9133 i40e_ethertype_filter_set(struct i40e_pf *pf,
9134                         struct rte_eth_ethertype_filter *filter,
9135                         bool add)
9136 {
9137         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9138         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9139         struct i40e_ethertype_filter *ethertype_filter, *node;
9140         struct i40e_ethertype_filter check_filter;
9141         struct i40e_control_filter_stats stats;
9142         uint16_t flags = 0;
9143         int ret;
9144
9145         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9146                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9147                 return -EINVAL;
9148         }
9149         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9150                 filter->ether_type == ETHER_TYPE_IPv6) {
9151                 PMD_DRV_LOG(ERR,
9152                         "unsupported ether_type(0x%04x) in control packet filter.",
9153                         filter->ether_type);
9154                 return -EINVAL;
9155         }
9156         if (filter->ether_type == ETHER_TYPE_VLAN)
9157                 PMD_DRV_LOG(WARNING,
9158                         "filter vlan ether_type in first tag is not supported.");
9159
9160         /* Check if there is the filter in SW list */
9161         memset(&check_filter, 0, sizeof(check_filter));
9162         i40e_ethertype_filter_convert(filter, &check_filter);
9163         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9164                                                &check_filter.input);
9165         if (add && node) {
9166                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9167                 return -EINVAL;
9168         }
9169
9170         if (!add && !node) {
9171                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9172                 return -EINVAL;
9173         }
9174
9175         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9176                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9177         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9178                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9179         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9180
9181         memset(&stats, 0, sizeof(stats));
9182         ret = i40e_aq_add_rem_control_packet_filter(hw,
9183                         filter->mac_addr.addr_bytes,
9184                         filter->ether_type, flags,
9185                         pf->main_vsi->seid,
9186                         filter->queue, add, &stats, NULL);
9187
9188         PMD_DRV_LOG(INFO,
9189                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9190                 ret, stats.mac_etype_used, stats.etype_used,
9191                 stats.mac_etype_free, stats.etype_free);
9192         if (ret < 0)
9193                 return -ENOSYS;
9194
9195         /* Add or delete a filter in SW list */
9196         if (add) {
9197                 ethertype_filter = rte_zmalloc("ethertype_filter",
9198                                        sizeof(*ethertype_filter), 0);
9199                 rte_memcpy(ethertype_filter, &check_filter,
9200                            sizeof(check_filter));
9201                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9202         } else {
9203                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9204         }
9205
9206         return ret;
9207 }
9208
9209 /*
9210  * Handle operations for ethertype filter.
9211  */
9212 static int
9213 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9214                                 enum rte_filter_op filter_op,
9215                                 void *arg)
9216 {
9217         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9218         int ret = 0;
9219
9220         if (filter_op == RTE_ETH_FILTER_NOP)
9221                 return ret;
9222
9223         if (arg == NULL) {
9224                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9225                             filter_op);
9226                 return -EINVAL;
9227         }
9228
9229         switch (filter_op) {
9230         case RTE_ETH_FILTER_ADD:
9231                 ret = i40e_ethertype_filter_set(pf,
9232                         (struct rte_eth_ethertype_filter *)arg,
9233                         TRUE);
9234                 break;
9235         case RTE_ETH_FILTER_DELETE:
9236                 ret = i40e_ethertype_filter_set(pf,
9237                         (struct rte_eth_ethertype_filter *)arg,
9238                         FALSE);
9239                 break;
9240         default:
9241                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9242                 ret = -ENOSYS;
9243                 break;
9244         }
9245         return ret;
9246 }
9247
9248 static int
9249 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9250                      enum rte_filter_type filter_type,
9251                      enum rte_filter_op filter_op,
9252                      void *arg)
9253 {
9254         int ret = 0;
9255
9256         if (dev == NULL)
9257                 return -EINVAL;
9258
9259         switch (filter_type) {
9260         case RTE_ETH_FILTER_NONE:
9261                 /* For global configuration */
9262                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9263                 break;
9264         case RTE_ETH_FILTER_HASH:
9265                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9266                 break;
9267         case RTE_ETH_FILTER_MACVLAN:
9268                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9269                 break;
9270         case RTE_ETH_FILTER_ETHERTYPE:
9271                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9272                 break;
9273         case RTE_ETH_FILTER_TUNNEL:
9274                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9275                 break;
9276         case RTE_ETH_FILTER_FDIR:
9277                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9278                 break;
9279         case RTE_ETH_FILTER_GENERIC:
9280                 if (filter_op != RTE_ETH_FILTER_GET)
9281                         return -EINVAL;
9282                 *(const void **)arg = &i40e_flow_ops;
9283                 break;
9284         default:
9285                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9286                                                         filter_type);
9287                 ret = -EINVAL;
9288                 break;
9289         }
9290
9291         return ret;
9292 }
9293
9294 /*
9295  * Check and enable Extended Tag.
9296  * Enabling Extended Tag is important for 40G performance.
9297  */
9298 static void
9299 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9300 {
9301         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9302         uint32_t buf = 0;
9303         int ret;
9304
9305         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9306                                       PCI_DEV_CAP_REG);
9307         if (ret < 0) {
9308                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9309                             PCI_DEV_CAP_REG);
9310                 return;
9311         }
9312         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9313                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9314                 return;
9315         }
9316
9317         buf = 0;
9318         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9319                                       PCI_DEV_CTRL_REG);
9320         if (ret < 0) {
9321                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9322                             PCI_DEV_CTRL_REG);
9323                 return;
9324         }
9325         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9326                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9327                 return;
9328         }
9329         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9330         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9331                                        PCI_DEV_CTRL_REG);
9332         if (ret < 0) {
9333                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9334                             PCI_DEV_CTRL_REG);
9335                 return;
9336         }
9337 }
9338
9339 /*
9340  * As some registers wouldn't be reset unless a global hardware reset,
9341  * hardware initialization is needed to put those registers into an
9342  * expected initial state.
9343  */
9344 static void
9345 i40e_hw_init(struct rte_eth_dev *dev)
9346 {
9347         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9348
9349         i40e_enable_extended_tag(dev);
9350
9351         /* clear the PF Queue Filter control register */
9352         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9353
9354         /* Disable symmetric hash per port */
9355         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9356 }
9357
9358 /*
9359  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9360  * however this function will return only one highest pctype index,
9361  * which is not quite correct. This is known problem of i40e driver
9362  * and needs to be fixed later.
9363  */
9364 enum i40e_filter_pctype
9365 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9366 {
9367         int i;
9368         uint64_t pctype_mask;
9369
9370         if (flow_type < I40E_FLOW_TYPE_MAX) {
9371                 pctype_mask = adapter->pctypes_tbl[flow_type];
9372                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9373                         if (pctype_mask & (1ULL << i))
9374                                 return (enum i40e_filter_pctype)i;
9375                 }
9376         }
9377         return I40E_FILTER_PCTYPE_INVALID;
9378 }
9379
9380 uint16_t
9381 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9382                         enum i40e_filter_pctype pctype)
9383 {
9384         uint16_t flowtype;
9385         uint64_t pctype_mask = 1ULL << pctype;
9386
9387         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9388              flowtype++) {
9389                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9390                         return flowtype;
9391         }
9392
9393         return RTE_ETH_FLOW_UNKNOWN;
9394 }
9395
9396 /*
9397  * On X710, performance number is far from the expectation on recent firmware
9398  * versions; on XL710, performance number is also far from the expectation on
9399  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9400  * mode is enabled and port MAC address is equal to the packet destination MAC
9401  * address. The fix for this issue may not be integrated in the following
9402  * firmware version. So the workaround in software driver is needed. It needs
9403  * to modify the initial values of 3 internal only registers for both X710 and
9404  * XL710. Note that the values for X710 or XL710 could be different, and the
9405  * workaround can be removed when it is fixed in firmware in the future.
9406  */
9407
9408 /* For both X710 and XL710 */
9409 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9410 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9411 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9412
9413 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9414 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9415
9416 /* For X722 */
9417 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9418 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9419
9420 /* For X710 */
9421 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9422 /* For XL710 */
9423 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9424 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9425
9426 static int
9427 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9428 {
9429         enum i40e_status_code status;
9430         struct i40e_aq_get_phy_abilities_resp phy_ab;
9431         int ret = -ENOTSUP;
9432         int retries = 0;
9433
9434         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9435                                               NULL);
9436
9437         while (status) {
9438                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9439                         status);
9440                 retries++;
9441                 rte_delay_us(100000);
9442                 if  (retries < 5)
9443                         status = i40e_aq_get_phy_capabilities(hw, false,
9444                                         true, &phy_ab, NULL);
9445                 else
9446                         return ret;
9447         }
9448         return 0;
9449 }
9450
9451 static void
9452 i40e_configure_registers(struct i40e_hw *hw)
9453 {
9454         static struct {
9455                 uint32_t addr;
9456                 uint64_t val;
9457         } reg_table[] = {
9458                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9459                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9460                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9461         };
9462         uint64_t reg;
9463         uint32_t i;
9464         int ret;
9465
9466         for (i = 0; i < RTE_DIM(reg_table); i++) {
9467                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9468                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9469                                 reg_table[i].val =
9470                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9471                         else /* For X710/XL710/XXV710 */
9472                                 if (hw->aq.fw_maj_ver < 6)
9473                                         reg_table[i].val =
9474                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9475                                 else
9476                                         reg_table[i].val =
9477                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9478                 }
9479
9480                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9481                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9482                                 reg_table[i].val =
9483                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9484                         else /* For X710/XL710/XXV710 */
9485                                 reg_table[i].val =
9486                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9487                 }
9488
9489                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9490                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9491                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9492                                 reg_table[i].val =
9493                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9494                         else /* For X710 */
9495                                 reg_table[i].val =
9496                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9497                 }
9498
9499                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9500                                                         &reg, NULL);
9501                 if (ret < 0) {
9502                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9503                                                         reg_table[i].addr);
9504                         break;
9505                 }
9506                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9507                                                 reg_table[i].addr, reg);
9508                 if (reg == reg_table[i].val)
9509                         continue;
9510
9511                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9512                                                 reg_table[i].val, NULL);
9513                 if (ret < 0) {
9514                         PMD_DRV_LOG(ERR,
9515                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9516                                 reg_table[i].val, reg_table[i].addr);
9517                         break;
9518                 }
9519                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9520                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9521         }
9522 }
9523
9524 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9525 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9526 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9527 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9528 static int
9529 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9530 {
9531         uint32_t reg;
9532         int ret;
9533
9534         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9535                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9536                 return -EINVAL;
9537         }
9538
9539         /* Configure for double VLAN RX stripping */
9540         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9541         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9542                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9543                 ret = i40e_aq_debug_write_register(hw,
9544                                                    I40E_VSI_TSR(vsi->vsi_id),
9545                                                    reg, NULL);
9546                 if (ret < 0) {
9547                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9548                                     vsi->vsi_id);
9549                         return I40E_ERR_CONFIG;
9550                 }
9551         }
9552
9553         /* Configure for double VLAN TX insertion */
9554         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9555         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9556                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9557                 ret = i40e_aq_debug_write_register(hw,
9558                                                    I40E_VSI_L2TAGSTXVALID(
9559                                                    vsi->vsi_id), reg, NULL);
9560                 if (ret < 0) {
9561                         PMD_DRV_LOG(ERR,
9562                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
9563                                 vsi->vsi_id);
9564                         return I40E_ERR_CONFIG;
9565                 }
9566         }
9567
9568         return 0;
9569 }
9570
9571 /**
9572  * i40e_aq_add_mirror_rule
9573  * @hw: pointer to the hardware structure
9574  * @seid: VEB seid to add mirror rule to
9575  * @dst_id: destination vsi seid
9576  * @entries: Buffer which contains the entities to be mirrored
9577  * @count: number of entities contained in the buffer
9578  * @rule_id:the rule_id of the rule to be added
9579  *
9580  * Add a mirror rule for a given veb.
9581  *
9582  **/
9583 static enum i40e_status_code
9584 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9585                         uint16_t seid, uint16_t dst_id,
9586                         uint16_t rule_type, uint16_t *entries,
9587                         uint16_t count, uint16_t *rule_id)
9588 {
9589         struct i40e_aq_desc desc;
9590         struct i40e_aqc_add_delete_mirror_rule cmd;
9591         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9592                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9593                 &desc.params.raw;
9594         uint16_t buff_len;
9595         enum i40e_status_code status;
9596
9597         i40e_fill_default_direct_cmd_desc(&desc,
9598                                           i40e_aqc_opc_add_mirror_rule);
9599         memset(&cmd, 0, sizeof(cmd));
9600
9601         buff_len = sizeof(uint16_t) * count;
9602         desc.datalen = rte_cpu_to_le_16(buff_len);
9603         if (buff_len > 0)
9604                 desc.flags |= rte_cpu_to_le_16(
9605                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9606         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9607                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9608         cmd.num_entries = rte_cpu_to_le_16(count);
9609         cmd.seid = rte_cpu_to_le_16(seid);
9610         cmd.destination = rte_cpu_to_le_16(dst_id);
9611
9612         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9613         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9614         PMD_DRV_LOG(INFO,
9615                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9616                 hw->aq.asq_last_status, resp->rule_id,
9617                 resp->mirror_rules_used, resp->mirror_rules_free);
9618         *rule_id = rte_le_to_cpu_16(resp->rule_id);
9619
9620         return status;
9621 }
9622
9623 /**
9624  * i40e_aq_del_mirror_rule
9625  * @hw: pointer to the hardware structure
9626  * @seid: VEB seid to add mirror rule to
9627  * @entries: Buffer which contains the entities to be mirrored
9628  * @count: number of entities contained in the buffer
9629  * @rule_id:the rule_id of the rule to be delete
9630  *
9631  * Delete a mirror rule for a given veb.
9632  *
9633  **/
9634 static enum i40e_status_code
9635 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9636                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9637                 uint16_t count, uint16_t rule_id)
9638 {
9639         struct i40e_aq_desc desc;
9640         struct i40e_aqc_add_delete_mirror_rule cmd;
9641         uint16_t buff_len = 0;
9642         enum i40e_status_code status;
9643         void *buff = NULL;
9644
9645         i40e_fill_default_direct_cmd_desc(&desc,
9646                                           i40e_aqc_opc_delete_mirror_rule);
9647         memset(&cmd, 0, sizeof(cmd));
9648         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9649                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9650                                                           I40E_AQ_FLAG_RD));
9651                 cmd.num_entries = count;
9652                 buff_len = sizeof(uint16_t) * count;
9653                 desc.datalen = rte_cpu_to_le_16(buff_len);
9654                 buff = (void *)entries;
9655         } else
9656                 /* rule id is filled in destination field for deleting mirror rule */
9657                 cmd.destination = rte_cpu_to_le_16(rule_id);
9658
9659         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9660                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9661         cmd.seid = rte_cpu_to_le_16(seid);
9662
9663         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9664         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9665
9666         return status;
9667 }
9668
9669 /**
9670  * i40e_mirror_rule_set
9671  * @dev: pointer to the hardware structure
9672  * @mirror_conf: mirror rule info
9673  * @sw_id: mirror rule's sw_id
9674  * @on: enable/disable
9675  *
9676  * set a mirror rule.
9677  *
9678  **/
9679 static int
9680 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9681                         struct rte_eth_mirror_conf *mirror_conf,
9682                         uint8_t sw_id, uint8_t on)
9683 {
9684         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9685         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9686         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9687         struct i40e_mirror_rule *parent = NULL;
9688         uint16_t seid, dst_seid, rule_id;
9689         uint16_t i, j = 0;
9690         int ret;
9691
9692         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9693
9694         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9695                 PMD_DRV_LOG(ERR,
9696                         "mirror rule can not be configured without veb or vfs.");
9697                 return -ENOSYS;
9698         }
9699         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9700                 PMD_DRV_LOG(ERR, "mirror table is full.");
9701                 return -ENOSPC;
9702         }
9703         if (mirror_conf->dst_pool > pf->vf_num) {
9704                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9705                                  mirror_conf->dst_pool);
9706                 return -EINVAL;
9707         }
9708
9709         seid = pf->main_vsi->veb->seid;
9710
9711         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9712                 if (sw_id <= it->index) {
9713                         mirr_rule = it;
9714                         break;
9715                 }
9716                 parent = it;
9717         }
9718         if (mirr_rule && sw_id == mirr_rule->index) {
9719                 if (on) {
9720                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9721                         return -EEXIST;
9722                 } else {
9723                         ret = i40e_aq_del_mirror_rule(hw, seid,
9724                                         mirr_rule->rule_type,
9725                                         mirr_rule->entries,
9726                                         mirr_rule->num_entries, mirr_rule->id);
9727                         if (ret < 0) {
9728                                 PMD_DRV_LOG(ERR,
9729                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9730                                         ret, hw->aq.asq_last_status);
9731                                 return -ENOSYS;
9732                         }
9733                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9734                         rte_free(mirr_rule);
9735                         pf->nb_mirror_rule--;
9736                         return 0;
9737                 }
9738         } else if (!on) {
9739                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9740                 return -ENOENT;
9741         }
9742
9743         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9744                                 sizeof(struct i40e_mirror_rule) , 0);
9745         if (!mirr_rule) {
9746                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9747                 return I40E_ERR_NO_MEMORY;
9748         }
9749         switch (mirror_conf->rule_type) {
9750         case ETH_MIRROR_VLAN:
9751                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9752                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9753                                 mirr_rule->entries[j] =
9754                                         mirror_conf->vlan.vlan_id[i];
9755                                 j++;
9756                         }
9757                 }
9758                 if (j == 0) {
9759                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9760                         rte_free(mirr_rule);
9761                         return -EINVAL;
9762                 }
9763                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9764                 break;
9765         case ETH_MIRROR_VIRTUAL_POOL_UP:
9766         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9767                 /* check if the specified pool bit is out of range */
9768                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9769                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9770                         rte_free(mirr_rule);
9771                         return -EINVAL;
9772                 }
9773                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9774                         if (mirror_conf->pool_mask & (1ULL << i)) {
9775                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9776                                 j++;
9777                         }
9778                 }
9779                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9780                         /* add pf vsi to entries */
9781                         mirr_rule->entries[j] = pf->main_vsi_seid;
9782                         j++;
9783                 }
9784                 if (j == 0) {
9785                         PMD_DRV_LOG(ERR, "pool is not specified.");
9786                         rte_free(mirr_rule);
9787                         return -EINVAL;
9788                 }
9789                 /* egress and ingress in aq commands means from switch but not port */
9790                 mirr_rule->rule_type =
9791                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9792                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9793                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9794                 break;
9795         case ETH_MIRROR_UPLINK_PORT:
9796                 /* egress and ingress in aq commands means from switch but not port*/
9797                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9798                 break;
9799         case ETH_MIRROR_DOWNLINK_PORT:
9800                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9801                 break;
9802         default:
9803                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9804                         mirror_conf->rule_type);
9805                 rte_free(mirr_rule);
9806                 return -EINVAL;
9807         }
9808
9809         /* If the dst_pool is equal to vf_num, consider it as PF */
9810         if (mirror_conf->dst_pool == pf->vf_num)
9811                 dst_seid = pf->main_vsi_seid;
9812         else
9813                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9814
9815         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9816                                       mirr_rule->rule_type, mirr_rule->entries,
9817                                       j, &rule_id);
9818         if (ret < 0) {
9819                 PMD_DRV_LOG(ERR,
9820                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9821                         ret, hw->aq.asq_last_status);
9822                 rte_free(mirr_rule);
9823                 return -ENOSYS;
9824         }
9825
9826         mirr_rule->index = sw_id;
9827         mirr_rule->num_entries = j;
9828         mirr_rule->id = rule_id;
9829         mirr_rule->dst_vsi_seid = dst_seid;
9830
9831         if (parent)
9832                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9833         else
9834                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9835
9836         pf->nb_mirror_rule++;
9837         return 0;
9838 }
9839
9840 /**
9841  * i40e_mirror_rule_reset
9842  * @dev: pointer to the device
9843  * @sw_id: mirror rule's sw_id
9844  *
9845  * reset a mirror rule.
9846  *
9847  **/
9848 static int
9849 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9850 {
9851         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9853         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9854         uint16_t seid;
9855         int ret;
9856
9857         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9858
9859         seid = pf->main_vsi->veb->seid;
9860
9861         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9862                 if (sw_id == it->index) {
9863                         mirr_rule = it;
9864                         break;
9865                 }
9866         }
9867         if (mirr_rule) {
9868                 ret = i40e_aq_del_mirror_rule(hw, seid,
9869                                 mirr_rule->rule_type,
9870                                 mirr_rule->entries,
9871                                 mirr_rule->num_entries, mirr_rule->id);
9872                 if (ret < 0) {
9873                         PMD_DRV_LOG(ERR,
9874                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9875                                 ret, hw->aq.asq_last_status);
9876                         return -ENOSYS;
9877                 }
9878                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9879                 rte_free(mirr_rule);
9880                 pf->nb_mirror_rule--;
9881         } else {
9882                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9883                 return -ENOENT;
9884         }
9885         return 0;
9886 }
9887
9888 static uint64_t
9889 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9890 {
9891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9892         uint64_t systim_cycles;
9893
9894         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9895         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9896                         << 32;
9897
9898         return systim_cycles;
9899 }
9900
9901 static uint64_t
9902 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9903 {
9904         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9905         uint64_t rx_tstamp;
9906
9907         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9908         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9909                         << 32;
9910
9911         return rx_tstamp;
9912 }
9913
9914 static uint64_t
9915 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9916 {
9917         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9918         uint64_t tx_tstamp;
9919
9920         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9921         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9922                         << 32;
9923
9924         return tx_tstamp;
9925 }
9926
9927 static void
9928 i40e_start_timecounters(struct rte_eth_dev *dev)
9929 {
9930         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9931         struct i40e_adapter *adapter =
9932                         (struct i40e_adapter *)dev->data->dev_private;
9933         struct rte_eth_link link;
9934         uint32_t tsync_inc_l;
9935         uint32_t tsync_inc_h;
9936
9937         /* Get current link speed. */
9938         memset(&link, 0, sizeof(link));
9939         i40e_dev_link_update(dev, 1);
9940         rte_i40e_dev_atomic_read_link_status(dev, &link);
9941
9942         switch (link.link_speed) {
9943         case ETH_SPEED_NUM_40G:
9944                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9945                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9946                 break;
9947         case ETH_SPEED_NUM_10G:
9948                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9949                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9950                 break;
9951         case ETH_SPEED_NUM_1G:
9952                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9953                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9954                 break;
9955         default:
9956                 tsync_inc_l = 0x0;
9957                 tsync_inc_h = 0x0;
9958         }
9959
9960         /* Set the timesync increment value. */
9961         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9962         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9963
9964         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9965         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9966         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9967
9968         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9969         adapter->systime_tc.cc_shift = 0;
9970         adapter->systime_tc.nsec_mask = 0;
9971
9972         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9973         adapter->rx_tstamp_tc.cc_shift = 0;
9974         adapter->rx_tstamp_tc.nsec_mask = 0;
9975
9976         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9977         adapter->tx_tstamp_tc.cc_shift = 0;
9978         adapter->tx_tstamp_tc.nsec_mask = 0;
9979 }
9980
9981 static int
9982 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9983 {
9984         struct i40e_adapter *adapter =
9985                         (struct i40e_adapter *)dev->data->dev_private;
9986
9987         adapter->systime_tc.nsec += delta;
9988         adapter->rx_tstamp_tc.nsec += delta;
9989         adapter->tx_tstamp_tc.nsec += delta;
9990
9991         return 0;
9992 }
9993
9994 static int
9995 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9996 {
9997         uint64_t ns;
9998         struct i40e_adapter *adapter =
9999                         (struct i40e_adapter *)dev->data->dev_private;
10000
10001         ns = rte_timespec_to_ns(ts);
10002
10003         /* Set the timecounters to a new value. */
10004         adapter->systime_tc.nsec = ns;
10005         adapter->rx_tstamp_tc.nsec = ns;
10006         adapter->tx_tstamp_tc.nsec = ns;
10007
10008         return 0;
10009 }
10010
10011 static int
10012 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10013 {
10014         uint64_t ns, systime_cycles;
10015         struct i40e_adapter *adapter =
10016                         (struct i40e_adapter *)dev->data->dev_private;
10017
10018         systime_cycles = i40e_read_systime_cyclecounter(dev);
10019         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10020         *ts = rte_ns_to_timespec(ns);
10021
10022         return 0;
10023 }
10024
10025 static int
10026 i40e_timesync_enable(struct rte_eth_dev *dev)
10027 {
10028         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10029         uint32_t tsync_ctl_l;
10030         uint32_t tsync_ctl_h;
10031
10032         /* Stop the timesync system time. */
10033         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10034         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10035         /* Reset the timesync system time value. */
10036         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10037         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10038
10039         i40e_start_timecounters(dev);
10040
10041         /* Clear timesync registers. */
10042         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10043         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10044         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10045         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10046         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10047         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10048
10049         /* Enable timestamping of PTP packets. */
10050         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10051         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10052
10053         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10054         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10055         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10056
10057         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10058         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10059
10060         return 0;
10061 }
10062
10063 static int
10064 i40e_timesync_disable(struct rte_eth_dev *dev)
10065 {
10066         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10067         uint32_t tsync_ctl_l;
10068         uint32_t tsync_ctl_h;
10069
10070         /* Disable timestamping of transmitted PTP packets. */
10071         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10072         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10073
10074         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10075         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10076
10077         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10078         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10079
10080         /* Reset the timesync increment value. */
10081         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10082         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10083
10084         return 0;
10085 }
10086
10087 static int
10088 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10089                                 struct timespec *timestamp, uint32_t flags)
10090 {
10091         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10092         struct i40e_adapter *adapter =
10093                 (struct i40e_adapter *)dev->data->dev_private;
10094
10095         uint32_t sync_status;
10096         uint32_t index = flags & 0x03;
10097         uint64_t rx_tstamp_cycles;
10098         uint64_t ns;
10099
10100         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10101         if ((sync_status & (1 << index)) == 0)
10102                 return -EINVAL;
10103
10104         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10105         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10106         *timestamp = rte_ns_to_timespec(ns);
10107
10108         return 0;
10109 }
10110
10111 static int
10112 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10113                                 struct timespec *timestamp)
10114 {
10115         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10116         struct i40e_adapter *adapter =
10117                 (struct i40e_adapter *)dev->data->dev_private;
10118
10119         uint32_t sync_status;
10120         uint64_t tx_tstamp_cycles;
10121         uint64_t ns;
10122
10123         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10124         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10125                 return -EINVAL;
10126
10127         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10128         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10129         *timestamp = rte_ns_to_timespec(ns);
10130
10131         return 0;
10132 }
10133
10134 /*
10135  * i40e_parse_dcb_configure - parse dcb configure from user
10136  * @dev: the device being configured
10137  * @dcb_cfg: pointer of the result of parse
10138  * @*tc_map: bit map of enabled traffic classes
10139  *
10140  * Returns 0 on success, negative value on failure
10141  */
10142 static int
10143 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10144                          struct i40e_dcbx_config *dcb_cfg,
10145                          uint8_t *tc_map)
10146 {
10147         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10148         uint8_t i, tc_bw, bw_lf;
10149
10150         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10151
10152         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10153         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10154                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10155                 return -EINVAL;
10156         }
10157
10158         /* assume each tc has the same bw */
10159         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10160         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10161                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10162         /* to ensure the sum of tcbw is equal to 100 */
10163         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10164         for (i = 0; i < bw_lf; i++)
10165                 dcb_cfg->etscfg.tcbwtable[i]++;
10166
10167         /* assume each tc has the same Transmission Selection Algorithm */
10168         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10169                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10170
10171         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10172                 dcb_cfg->etscfg.prioritytable[i] =
10173                                 dcb_rx_conf->dcb_tc[i];
10174
10175         /* FW needs one App to configure HW */
10176         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10177         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10178         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10179         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10180
10181         if (dcb_rx_conf->nb_tcs == 0)
10182                 *tc_map = 1; /* tc0 only */
10183         else
10184                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10185
10186         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10187                 dcb_cfg->pfc.willing = 0;
10188                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10189                 dcb_cfg->pfc.pfcenable = *tc_map;
10190         }
10191         return 0;
10192 }
10193
10194
10195 static enum i40e_status_code
10196 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10197                               struct i40e_aqc_vsi_properties_data *info,
10198                               uint8_t enabled_tcmap)
10199 {
10200         enum i40e_status_code ret;
10201         int i, total_tc = 0;
10202         uint16_t qpnum_per_tc, bsf, qp_idx;
10203         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10204         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10205         uint16_t used_queues;
10206
10207         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10208         if (ret != I40E_SUCCESS)
10209                 return ret;
10210
10211         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10212                 if (enabled_tcmap & (1 << i))
10213                         total_tc++;
10214         }
10215         if (total_tc == 0)
10216                 total_tc = 1;
10217         vsi->enabled_tc = enabled_tcmap;
10218
10219         /* different VSI has different queues assigned */
10220         if (vsi->type == I40E_VSI_MAIN)
10221                 used_queues = dev_data->nb_rx_queues -
10222                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10223         else if (vsi->type == I40E_VSI_VMDQ2)
10224                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10225         else {
10226                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10227                 return I40E_ERR_NO_AVAILABLE_VSI;
10228         }
10229
10230         qpnum_per_tc = used_queues / total_tc;
10231         /* Number of queues per enabled TC */
10232         if (qpnum_per_tc == 0) {
10233                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10234                 return I40E_ERR_INVALID_QP_ID;
10235         }
10236         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10237                                 I40E_MAX_Q_PER_TC);
10238         bsf = rte_bsf32(qpnum_per_tc);
10239
10240         /**
10241          * Configure TC and queue mapping parameters, for enabled TC,
10242          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10243          * default queue will serve it.
10244          */
10245         qp_idx = 0;
10246         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10247                 if (vsi->enabled_tc & (1 << i)) {
10248                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10249                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10250                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10251                         qp_idx += qpnum_per_tc;
10252                 } else
10253                         info->tc_mapping[i] = 0;
10254         }
10255
10256         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10257         if (vsi->type == I40E_VSI_SRIOV) {
10258                 info->mapping_flags |=
10259                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10260                 for (i = 0; i < vsi->nb_qps; i++)
10261                         info->queue_mapping[i] =
10262                                 rte_cpu_to_le_16(vsi->base_queue + i);
10263         } else {
10264                 info->mapping_flags |=
10265                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10266                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10267         }
10268         info->valid_sections |=
10269                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10270
10271         return I40E_SUCCESS;
10272 }
10273
10274 /*
10275  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10276  * @veb: VEB to be configured
10277  * @tc_map: enabled TC bitmap
10278  *
10279  * Returns 0 on success, negative value on failure
10280  */
10281 static enum i40e_status_code
10282 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10283 {
10284         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10285         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10286         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10287         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10288         enum i40e_status_code ret = I40E_SUCCESS;
10289         int i;
10290         uint32_t bw_max;
10291
10292         /* Check if enabled_tc is same as existing or new TCs */
10293         if (veb->enabled_tc == tc_map)
10294                 return ret;
10295
10296         /* configure tc bandwidth */
10297         memset(&veb_bw, 0, sizeof(veb_bw));
10298         veb_bw.tc_valid_bits = tc_map;
10299         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10300         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10301                 if (tc_map & BIT_ULL(i))
10302                         veb_bw.tc_bw_share_credits[i] = 1;
10303         }
10304         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10305                                                    &veb_bw, NULL);
10306         if (ret) {
10307                 PMD_INIT_LOG(ERR,
10308                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10309                         hw->aq.asq_last_status);
10310                 return ret;
10311         }
10312
10313         memset(&ets_query, 0, sizeof(ets_query));
10314         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10315                                                    &ets_query, NULL);
10316         if (ret != I40E_SUCCESS) {
10317                 PMD_DRV_LOG(ERR,
10318                         "Failed to get switch_comp ETS configuration %u",
10319                         hw->aq.asq_last_status);
10320                 return ret;
10321         }
10322         memset(&bw_query, 0, sizeof(bw_query));
10323         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10324                                                   &bw_query, NULL);
10325         if (ret != I40E_SUCCESS) {
10326                 PMD_DRV_LOG(ERR,
10327                         "Failed to get switch_comp bandwidth configuration %u",
10328                         hw->aq.asq_last_status);
10329                 return ret;
10330         }
10331
10332         /* store and print out BW info */
10333         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10334         veb->bw_info.bw_max = ets_query.tc_bw_max;
10335         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10336         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10337         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10338                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10339                      I40E_16_BIT_WIDTH);
10340         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10341                 veb->bw_info.bw_ets_share_credits[i] =
10342                                 bw_query.tc_bw_share_credits[i];
10343                 veb->bw_info.bw_ets_credits[i] =
10344                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10345                 /* 4 bits per TC, 4th bit is reserved */
10346                 veb->bw_info.bw_ets_max[i] =
10347                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10348                                   RTE_LEN2MASK(3, uint8_t));
10349                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10350                             veb->bw_info.bw_ets_share_credits[i]);
10351                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10352                             veb->bw_info.bw_ets_credits[i]);
10353                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10354                             veb->bw_info.bw_ets_max[i]);
10355         }
10356
10357         veb->enabled_tc = tc_map;
10358
10359         return ret;
10360 }
10361
10362
10363 /*
10364  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10365  * @vsi: VSI to be configured
10366  * @tc_map: enabled TC bitmap
10367  *
10368  * Returns 0 on success, negative value on failure
10369  */
10370 static enum i40e_status_code
10371 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10372 {
10373         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10374         struct i40e_vsi_context ctxt;
10375         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10376         enum i40e_status_code ret = I40E_SUCCESS;
10377         int i;
10378
10379         /* Check if enabled_tc is same as existing or new TCs */
10380         if (vsi->enabled_tc == tc_map)
10381                 return ret;
10382
10383         /* configure tc bandwidth */
10384         memset(&bw_data, 0, sizeof(bw_data));
10385         bw_data.tc_valid_bits = tc_map;
10386         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10387         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10388                 if (tc_map & BIT_ULL(i))
10389                         bw_data.tc_bw_credits[i] = 1;
10390         }
10391         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10392         if (ret) {
10393                 PMD_INIT_LOG(ERR,
10394                         "AQ command Config VSI BW allocation per TC failed = %d",
10395                         hw->aq.asq_last_status);
10396                 goto out;
10397         }
10398         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10399                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10400
10401         /* Update Queue Pairs Mapping for currently enabled UPs */
10402         ctxt.seid = vsi->seid;
10403         ctxt.pf_num = hw->pf_id;
10404         ctxt.vf_num = 0;
10405         ctxt.uplink_seid = vsi->uplink_seid;
10406         ctxt.info = vsi->info;
10407         i40e_get_cap(hw);
10408         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10409         if (ret)
10410                 goto out;
10411
10412         /* Update the VSI after updating the VSI queue-mapping information */
10413         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10414         if (ret) {
10415                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10416                         hw->aq.asq_last_status);
10417                 goto out;
10418         }
10419         /* update the local VSI info with updated queue map */
10420         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10421                                         sizeof(vsi->info.tc_mapping));
10422         rte_memcpy(&vsi->info.queue_mapping,
10423                         &ctxt.info.queue_mapping,
10424                 sizeof(vsi->info.queue_mapping));
10425         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10426         vsi->info.valid_sections = 0;
10427
10428         /* query and update current VSI BW information */
10429         ret = i40e_vsi_get_bw_config(vsi);
10430         if (ret) {
10431                 PMD_INIT_LOG(ERR,
10432                          "Failed updating vsi bw info, err %s aq_err %s",
10433                          i40e_stat_str(hw, ret),
10434                          i40e_aq_str(hw, hw->aq.asq_last_status));
10435                 goto out;
10436         }
10437
10438         vsi->enabled_tc = tc_map;
10439
10440 out:
10441         return ret;
10442 }
10443
10444 /*
10445  * i40e_dcb_hw_configure - program the dcb setting to hw
10446  * @pf: pf the configuration is taken on
10447  * @new_cfg: new configuration
10448  * @tc_map: enabled TC bitmap
10449  *
10450  * Returns 0 on success, negative value on failure
10451  */
10452 static enum i40e_status_code
10453 i40e_dcb_hw_configure(struct i40e_pf *pf,
10454                       struct i40e_dcbx_config *new_cfg,
10455                       uint8_t tc_map)
10456 {
10457         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10458         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10459         struct i40e_vsi *main_vsi = pf->main_vsi;
10460         struct i40e_vsi_list *vsi_list;
10461         enum i40e_status_code ret;
10462         int i;
10463         uint32_t val;
10464
10465         /* Use the FW API if FW > v4.4*/
10466         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10467               (hw->aq.fw_maj_ver >= 5))) {
10468                 PMD_INIT_LOG(ERR,
10469                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10470                 return I40E_ERR_FIRMWARE_API_VERSION;
10471         }
10472
10473         /* Check if need reconfiguration */
10474         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10475                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10476                 return I40E_SUCCESS;
10477         }
10478
10479         /* Copy the new config to the current config */
10480         *old_cfg = *new_cfg;
10481         old_cfg->etsrec = old_cfg->etscfg;
10482         ret = i40e_set_dcb_config(hw);
10483         if (ret) {
10484                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10485                          i40e_stat_str(hw, ret),
10486                          i40e_aq_str(hw, hw->aq.asq_last_status));
10487                 return ret;
10488         }
10489         /* set receive Arbiter to RR mode and ETS scheme by default */
10490         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10491                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10492                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10493                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10494                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10495                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10496                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10497                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10498                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10499                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10500                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10501                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10502                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10503         }
10504         /* get local mib to check whether it is configured correctly */
10505         /* IEEE mode */
10506         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10507         /* Get Local DCB Config */
10508         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10509                                      &hw->local_dcbx_config);
10510
10511         /* if Veb is created, need to update TC of it at first */
10512         if (main_vsi->veb) {
10513                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10514                 if (ret)
10515                         PMD_INIT_LOG(WARNING,
10516                                  "Failed configuring TC for VEB seid=%d",
10517                                  main_vsi->veb->seid);
10518         }
10519         /* Update each VSI */
10520         i40e_vsi_config_tc(main_vsi, tc_map);
10521         if (main_vsi->veb) {
10522                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10523                         /* Beside main VSI and VMDQ VSIs, only enable default
10524                          * TC for other VSIs
10525                          */
10526                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10527                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10528                                                          tc_map);
10529                         else
10530                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10531                                                          I40E_DEFAULT_TCMAP);
10532                         if (ret)
10533                                 PMD_INIT_LOG(WARNING,
10534                                         "Failed configuring TC for VSI seid=%d",
10535                                         vsi_list->vsi->seid);
10536                         /* continue */
10537                 }
10538         }
10539         return I40E_SUCCESS;
10540 }
10541
10542 /*
10543  * i40e_dcb_init_configure - initial dcb config
10544  * @dev: device being configured
10545  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10546  *
10547  * Returns 0 on success, negative value on failure
10548  */
10549 int
10550 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10551 {
10552         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10554         int i, ret = 0;
10555
10556         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10557                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10558                 return -ENOTSUP;
10559         }
10560
10561         /* DCB initialization:
10562          * Update DCB configuration from the Firmware and configure
10563          * LLDP MIB change event.
10564          */
10565         if (sw_dcb == TRUE) {
10566                 ret = i40e_init_dcb(hw);
10567                 /* If lldp agent is stopped, the return value from
10568                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10569                  * adminq status. Otherwise, it should return success.
10570                  */
10571                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10572                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10573                         memset(&hw->local_dcbx_config, 0,
10574                                 sizeof(struct i40e_dcbx_config));
10575                         /* set dcb default configuration */
10576                         hw->local_dcbx_config.etscfg.willing = 0;
10577                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10578                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10579                         hw->local_dcbx_config.etscfg.tsatable[0] =
10580                                                 I40E_IEEE_TSA_ETS;
10581                         /* all UPs mapping to TC0 */
10582                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10583                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10584                         hw->local_dcbx_config.etsrec =
10585                                 hw->local_dcbx_config.etscfg;
10586                         hw->local_dcbx_config.pfc.willing = 0;
10587                         hw->local_dcbx_config.pfc.pfccap =
10588                                                 I40E_MAX_TRAFFIC_CLASS;
10589                         /* FW needs one App to configure HW */
10590                         hw->local_dcbx_config.numapps = 1;
10591                         hw->local_dcbx_config.app[0].selector =
10592                                                 I40E_APP_SEL_ETHTYPE;
10593                         hw->local_dcbx_config.app[0].priority = 3;
10594                         hw->local_dcbx_config.app[0].protocolid =
10595                                                 I40E_APP_PROTOID_FCOE;
10596                         ret = i40e_set_dcb_config(hw);
10597                         if (ret) {
10598                                 PMD_INIT_LOG(ERR,
10599                                         "default dcb config fails. err = %d, aq_err = %d.",
10600                                         ret, hw->aq.asq_last_status);
10601                                 return -ENOSYS;
10602                         }
10603                 } else {
10604                         PMD_INIT_LOG(ERR,
10605                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10606                                 ret, hw->aq.asq_last_status);
10607                         return -ENOTSUP;
10608                 }
10609         } else {
10610                 ret = i40e_aq_start_lldp(hw, NULL);
10611                 if (ret != I40E_SUCCESS)
10612                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10613
10614                 ret = i40e_init_dcb(hw);
10615                 if (!ret) {
10616                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10617                                 PMD_INIT_LOG(ERR,
10618                                         "HW doesn't support DCBX offload.");
10619                                 return -ENOTSUP;
10620                         }
10621                 } else {
10622                         PMD_INIT_LOG(ERR,
10623                                 "DCBX configuration failed, err = %d, aq_err = %d.",
10624                                 ret, hw->aq.asq_last_status);
10625                         return -ENOTSUP;
10626                 }
10627         }
10628         return 0;
10629 }
10630
10631 /*
10632  * i40e_dcb_setup - setup dcb related config
10633  * @dev: device being configured
10634  *
10635  * Returns 0 on success, negative value on failure
10636  */
10637 static int
10638 i40e_dcb_setup(struct rte_eth_dev *dev)
10639 {
10640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10641         struct i40e_dcbx_config dcb_cfg;
10642         uint8_t tc_map = 0;
10643         int ret = 0;
10644
10645         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10646                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10647                 return -ENOTSUP;
10648         }
10649
10650         if (pf->vf_num != 0)
10651                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10652
10653         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10654         if (ret) {
10655                 PMD_INIT_LOG(ERR, "invalid dcb config");
10656                 return -EINVAL;
10657         }
10658         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10659         if (ret) {
10660                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10661                 return -ENOSYS;
10662         }
10663
10664         return 0;
10665 }
10666
10667 static int
10668 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10669                       struct rte_eth_dcb_info *dcb_info)
10670 {
10671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10672         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10673         struct i40e_vsi *vsi = pf->main_vsi;
10674         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10675         uint16_t bsf, tc_mapping;
10676         int i, j = 0;
10677
10678         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10679                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10680         else
10681                 dcb_info->nb_tcs = 1;
10682         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10683                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10684         for (i = 0; i < dcb_info->nb_tcs; i++)
10685                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10686
10687         /* get queue mapping if vmdq is disabled */
10688         if (!pf->nb_cfg_vmdq_vsi) {
10689                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10690                         if (!(vsi->enabled_tc & (1 << i)))
10691                                 continue;
10692                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10693                         dcb_info->tc_queue.tc_rxq[j][i].base =
10694                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10695                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10696                         dcb_info->tc_queue.tc_txq[j][i].base =
10697                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10698                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10699                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10700                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10701                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10702                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10703                 }
10704                 return 0;
10705         }
10706
10707         /* get queue mapping if vmdq is enabled */
10708         do {
10709                 vsi = pf->vmdq[j].vsi;
10710                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10711                         if (!(vsi->enabled_tc & (1 << i)))
10712                                 continue;
10713                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10714                         dcb_info->tc_queue.tc_rxq[j][i].base =
10715                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10716                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10717                         dcb_info->tc_queue.tc_txq[j][i].base =
10718                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10719                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10720                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10721                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10722                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10723                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10724                 }
10725                 j++;
10726         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10727         return 0;
10728 }
10729
10730 static int
10731 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10732 {
10733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10736         uint16_t interval =
10737                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10738         uint16_t msix_intr;
10739
10740         msix_intr = intr_handle->intr_vec[queue_id];
10741         if (msix_intr == I40E_MISC_VEC_ID)
10742                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10743                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10744                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10745                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10746                                (interval <<
10747                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10748         else
10749                 I40E_WRITE_REG(hw,
10750                                I40E_PFINT_DYN_CTLN(msix_intr -
10751                                                    I40E_RX_VEC_START),
10752                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10753                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10754                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10755                                (interval <<
10756                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10757
10758         I40E_WRITE_FLUSH(hw);
10759         rte_intr_enable(&pci_dev->intr_handle);
10760
10761         return 0;
10762 }
10763
10764 static int
10765 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10766 {
10767         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10768         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10770         uint16_t msix_intr;
10771
10772         msix_intr = intr_handle->intr_vec[queue_id];
10773         if (msix_intr == I40E_MISC_VEC_ID)
10774                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10775         else
10776                 I40E_WRITE_REG(hw,
10777                                I40E_PFINT_DYN_CTLN(msix_intr -
10778                                                    I40E_RX_VEC_START),
10779                                0);
10780         I40E_WRITE_FLUSH(hw);
10781
10782         return 0;
10783 }
10784
10785 static int i40e_get_regs(struct rte_eth_dev *dev,
10786                          struct rte_dev_reg_info *regs)
10787 {
10788         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10789         uint32_t *ptr_data = regs->data;
10790         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10791         const struct i40e_reg_info *reg_info;
10792
10793         if (ptr_data == NULL) {
10794                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10795                 regs->width = sizeof(uint32_t);
10796                 return 0;
10797         }
10798
10799         /* The first few registers have to be read using AQ operations */
10800         reg_idx = 0;
10801         while (i40e_regs_adminq[reg_idx].name) {
10802                 reg_info = &i40e_regs_adminq[reg_idx++];
10803                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10804                         for (arr_idx2 = 0;
10805                                         arr_idx2 <= reg_info->count2;
10806                                         arr_idx2++) {
10807                                 reg_offset = arr_idx * reg_info->stride1 +
10808                                         arr_idx2 * reg_info->stride2;
10809                                 reg_offset += reg_info->base_addr;
10810                                 ptr_data[reg_offset >> 2] =
10811                                         i40e_read_rx_ctl(hw, reg_offset);
10812                         }
10813         }
10814
10815         /* The remaining registers can be read using primitives */
10816         reg_idx = 0;
10817         while (i40e_regs_others[reg_idx].name) {
10818                 reg_info = &i40e_regs_others[reg_idx++];
10819                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10820                         for (arr_idx2 = 0;
10821                                         arr_idx2 <= reg_info->count2;
10822                                         arr_idx2++) {
10823                                 reg_offset = arr_idx * reg_info->stride1 +
10824                                         arr_idx2 * reg_info->stride2;
10825                                 reg_offset += reg_info->base_addr;
10826                                 ptr_data[reg_offset >> 2] =
10827                                         I40E_READ_REG(hw, reg_offset);
10828                         }
10829         }
10830
10831         return 0;
10832 }
10833
10834 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10835 {
10836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10837
10838         /* Convert word count to byte count */
10839         return hw->nvm.sr_size << 1;
10840 }
10841
10842 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10843                            struct rte_dev_eeprom_info *eeprom)
10844 {
10845         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10846         uint16_t *data = eeprom->data;
10847         uint16_t offset, length, cnt_words;
10848         int ret_code;
10849
10850         offset = eeprom->offset >> 1;
10851         length = eeprom->length >> 1;
10852         cnt_words = length;
10853
10854         if (offset > hw->nvm.sr_size ||
10855                 offset + length > hw->nvm.sr_size) {
10856                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10857                 return -EINVAL;
10858         }
10859
10860         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10861
10862         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10863         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10864                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10865                 return -EIO;
10866         }
10867
10868         return 0;
10869 }
10870
10871 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10872                                       struct ether_addr *mac_addr)
10873 {
10874         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10875
10876         if (!is_valid_assigned_ether_addr(mac_addr)) {
10877                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10878                 return;
10879         }
10880
10881         /* Flags: 0x3 updates port address */
10882         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10883 }
10884
10885 static int
10886 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10887 {
10888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10889         struct rte_eth_dev_data *dev_data = pf->dev_data;
10890         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10891         int ret = 0;
10892
10893         /* check if mtu is within the allowed range */
10894         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10895                 return -EINVAL;
10896
10897         /* mtu setting is forbidden if port is start */
10898         if (dev_data->dev_started) {
10899                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10900                             dev_data->port_id);
10901                 return -EBUSY;
10902         }
10903
10904         if (frame_size > ETHER_MAX_LEN)
10905                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10906         else
10907                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10908
10909         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10910
10911         return ret;
10912 }
10913
10914 /* Restore ethertype filter */
10915 static void
10916 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10917 {
10918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10919         struct i40e_ethertype_filter_list
10920                 *ethertype_list = &pf->ethertype.ethertype_list;
10921         struct i40e_ethertype_filter *f;
10922         struct i40e_control_filter_stats stats;
10923         uint16_t flags;
10924
10925         TAILQ_FOREACH(f, ethertype_list, rules) {
10926                 flags = 0;
10927                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10928                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10929                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10930                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10931                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10932
10933                 memset(&stats, 0, sizeof(stats));
10934                 i40e_aq_add_rem_control_packet_filter(hw,
10935                                             f->input.mac_addr.addr_bytes,
10936                                             f->input.ether_type,
10937                                             flags, pf->main_vsi->seid,
10938                                             f->queue, 1, &stats, NULL);
10939         }
10940         PMD_DRV_LOG(INFO, "Ethertype filter:"
10941                     " mac_etype_used = %u, etype_used = %u,"
10942                     " mac_etype_free = %u, etype_free = %u",
10943                     stats.mac_etype_used, stats.etype_used,
10944                     stats.mac_etype_free, stats.etype_free);
10945 }
10946
10947 /* Restore tunnel filter */
10948 static void
10949 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10950 {
10951         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10952         struct i40e_vsi *vsi;
10953         struct i40e_pf_vf *vf;
10954         struct i40e_tunnel_filter_list
10955                 *tunnel_list = &pf->tunnel.tunnel_list;
10956         struct i40e_tunnel_filter *f;
10957         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10958         bool big_buffer = 0;
10959
10960         TAILQ_FOREACH(f, tunnel_list, rules) {
10961                 if (!f->is_to_vf)
10962                         vsi = pf->main_vsi;
10963                 else {
10964                         vf = &pf->vfs[f->vf_id];
10965                         vsi = vf->vsi;
10966                 }
10967                 memset(&cld_filter, 0, sizeof(cld_filter));
10968                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10969                         (struct ether_addr *)&cld_filter.element.outer_mac);
10970                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10971                         (struct ether_addr *)&cld_filter.element.inner_mac);
10972                 cld_filter.element.inner_vlan = f->input.inner_vlan;
10973                 cld_filter.element.flags = f->input.flags;
10974                 cld_filter.element.tenant_id = f->input.tenant_id;
10975                 cld_filter.element.queue_number = f->queue;
10976                 rte_memcpy(cld_filter.general_fields,
10977                            f->input.general_fields,
10978                            sizeof(f->input.general_fields));
10979
10980                 if (((f->input.flags &
10981                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10982                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10983                     ((f->input.flags &
10984                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10985                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10986                     ((f->input.flags &
10987                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10988                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
10989                         big_buffer = 1;
10990
10991                 if (big_buffer)
10992                         i40e_aq_add_cloud_filters_big_buffer(hw,
10993                                              vsi->seid, &cld_filter, 1);
10994                 else
10995                         i40e_aq_add_cloud_filters(hw, vsi->seid,
10996                                                   &cld_filter.element, 1);
10997         }
10998 }
10999
11000 static void
11001 i40e_filter_restore(struct i40e_pf *pf)
11002 {
11003         i40e_ethertype_filter_restore(pf);
11004         i40e_tunnel_filter_restore(pf);
11005         i40e_fdir_filter_restore(pf);
11006 }
11007
11008 static bool
11009 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11010 {
11011         if (strcmp(dev->device->driver->name, drv->driver.name))
11012                 return false;
11013
11014         return true;
11015 }
11016
11017 bool
11018 is_i40e_supported(struct rte_eth_dev *dev)
11019 {
11020         return is_device_supported(dev, &rte_i40e_pmd);
11021 }
11022
11023 struct i40e_customized_pctype*
11024 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11025 {
11026         int i;
11027
11028         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11029                 if (pf->customized_pctype[i].index == index)
11030                         return &pf->customized_pctype[i];
11031         }
11032         return NULL;
11033 }
11034
11035 static int
11036 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11037                               uint32_t pkg_size, uint32_t proto_num,
11038                               struct rte_pmd_i40e_proto_info *proto)
11039 {
11040         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11041         uint32_t pctype_num;
11042         struct rte_pmd_i40e_ptype_info *pctype;
11043         uint32_t buff_size;
11044         struct i40e_customized_pctype *new_pctype = NULL;
11045         uint8_t proto_id;
11046         uint8_t pctype_value;
11047         char name[64];
11048         uint32_t i, j, n;
11049         int ret;
11050
11051         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11052                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11053                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11054         if (ret) {
11055                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11056                 return -1;
11057         }
11058         if (!pctype_num) {
11059                 PMD_DRV_LOG(INFO, "No new pctype added");
11060                 return -1;
11061         }
11062
11063         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11064         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11065         if (!pctype) {
11066                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11067                 return -1;
11068         }
11069         /* get information about new pctype list */
11070         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11071                                         (uint8_t *)pctype, buff_size,
11072                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11073         if (ret) {
11074                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11075                 rte_free(pctype);
11076                 return -1;
11077         }
11078
11079         /* Update customized pctype. */
11080         for (i = 0; i < pctype_num; i++) {
11081                 pctype_value = pctype[i].ptype_id;
11082                 memset(name, 0, sizeof(name));
11083                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11084                         proto_id = pctype[i].protocols[j];
11085                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11086                                 continue;
11087                         for (n = 0; n < proto_num; n++) {
11088                                 if (proto[n].proto_id != proto_id)
11089                                         continue;
11090                                 strcat(name, proto[n].name);
11091                                 strcat(name, "_");
11092                                 break;
11093                         }
11094                 }
11095                 name[strlen(name) - 1] = '\0';
11096                 if (!strcmp(name, "GTPC"))
11097                         new_pctype =
11098                                 i40e_find_customized_pctype(pf,
11099                                                       I40E_CUSTOMIZED_GTPC);
11100                 else if (!strcmp(name, "GTPU_IPV4"))
11101                         new_pctype =
11102                                 i40e_find_customized_pctype(pf,
11103                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11104                 else if (!strcmp(name, "GTPU_IPV6"))
11105                         new_pctype =
11106                                 i40e_find_customized_pctype(pf,
11107                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11108                 else if (!strcmp(name, "GTPU"))
11109                         new_pctype =
11110                                 i40e_find_customized_pctype(pf,
11111                                                       I40E_CUSTOMIZED_GTPU);
11112                 if (new_pctype) {
11113                         new_pctype->pctype = pctype_value;
11114                         new_pctype->valid = true;
11115                 }
11116         }
11117
11118         rte_free(pctype);
11119         return 0;
11120 }
11121
11122 static int
11123 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11124                                uint32_t pkg_size, uint32_t proto_num,
11125                                struct rte_pmd_i40e_proto_info *proto)
11126 {
11127         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11128         uint16_t port_id = dev->data->port_id;
11129         uint32_t ptype_num;
11130         struct rte_pmd_i40e_ptype_info *ptype;
11131         uint32_t buff_size;
11132         uint8_t proto_id;
11133         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11134         uint32_t i, j, n;
11135         bool in_tunnel;
11136         int ret;
11137
11138         /* get information about new ptype num */
11139         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11140                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11141                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11142         if (ret) {
11143                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11144                 return ret;
11145         }
11146         if (!ptype_num) {
11147                 PMD_DRV_LOG(INFO, "No new ptype added");
11148                 return -1;
11149         }
11150
11151         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11152         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11153         if (!ptype) {
11154                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11155                 return -1;
11156         }
11157
11158         /* get information about new ptype list */
11159         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11160                                         (uint8_t *)ptype, buff_size,
11161                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11162         if (ret) {
11163                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11164                 rte_free(ptype);
11165                 return ret;
11166         }
11167
11168         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11169         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11170         if (!ptype_mapping) {
11171                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11172                 rte_free(ptype);
11173                 return -1;
11174         }
11175
11176         /* Update ptype mapping table. */
11177         for (i = 0; i < ptype_num; i++) {
11178                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11179                 ptype_mapping[i].sw_ptype = 0;
11180                 in_tunnel = false;
11181                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11182                         proto_id = ptype[i].protocols[j];
11183                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11184                                 continue;
11185                         for (n = 0; n < proto_num; n++) {
11186                                 if (proto[n].proto_id != proto_id)
11187                                         continue;
11188                                 memset(name, 0, sizeof(name));
11189                                 strcpy(name, proto[n].name);
11190                                 if (!strncmp(name, "PPPOE", 5))
11191                                         ptype_mapping[i].sw_ptype |=
11192                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11193                                 else if (!strncmp(name, "OIPV4", 5)) {
11194                                         ptype_mapping[i].sw_ptype |=
11195                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11196                                         in_tunnel = true;
11197                                 } else if (!strncmp(name, "IPV4", 4) &&
11198                                            !in_tunnel)
11199                                         ptype_mapping[i].sw_ptype |=
11200                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11201                                 else if (!strncmp(name, "IPV4FRAG", 8) &&
11202                                          in_tunnel) {
11203                                         ptype_mapping[i].sw_ptype |=
11204                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11205                                         ptype_mapping[i].sw_ptype |=
11206                                                 RTE_PTYPE_INNER_L4_FRAG;
11207                                 } else if (!strncmp(name, "IPV4", 4) &&
11208                                            in_tunnel)
11209                                         ptype_mapping[i].sw_ptype |=
11210                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11211                                 else if (!strncmp(name, "OIPV6", 5)) {
11212                                         ptype_mapping[i].sw_ptype |=
11213                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11214                                         in_tunnel = true;
11215                                 } else if (!strncmp(name, "IPV6", 4) &&
11216                                            !in_tunnel)
11217                                         ptype_mapping[i].sw_ptype |=
11218                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11219                                 else if (!strncmp(name, "IPV6FRAG", 8) &&
11220                                          in_tunnel) {
11221                                         ptype_mapping[i].sw_ptype |=
11222                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11223                                         ptype_mapping[i].sw_ptype |=
11224                                                 RTE_PTYPE_INNER_L4_FRAG;
11225                                 } else if (!strncmp(name, "IPV6", 4) &&
11226                                            in_tunnel)
11227                                         ptype_mapping[i].sw_ptype |=
11228                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11229                                 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11230                                         ptype_mapping[i].sw_ptype |=
11231                                                 RTE_PTYPE_L4_UDP;
11232                                 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11233                                         ptype_mapping[i].sw_ptype |=
11234                                                 RTE_PTYPE_INNER_L4_UDP;
11235                                 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11236                                         ptype_mapping[i].sw_ptype |=
11237                                                 RTE_PTYPE_L4_TCP;
11238                                 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11239                                         ptype_mapping[i].sw_ptype |=
11240                                                 RTE_PTYPE_INNER_L4_TCP;
11241                                 else if (!strncmp(name, "SCTP", 4) &&
11242                                          !in_tunnel)
11243                                         ptype_mapping[i].sw_ptype |=
11244                                                 RTE_PTYPE_L4_SCTP;
11245                                 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11246                                         ptype_mapping[i].sw_ptype |=
11247                                                 RTE_PTYPE_INNER_L4_SCTP;
11248                                 else if ((!strncmp(name, "ICMP", 4) ||
11249                                           !strncmp(name, "ICMPV6", 6)) &&
11250                                          !in_tunnel)
11251                                         ptype_mapping[i].sw_ptype |=
11252                                                 RTE_PTYPE_L4_ICMP;
11253                                 else if ((!strncmp(name, "ICMP", 4) ||
11254                                           !strncmp(name, "ICMPV6", 6)) &&
11255                                          in_tunnel)
11256                                         ptype_mapping[i].sw_ptype |=
11257                                                 RTE_PTYPE_INNER_L4_ICMP;
11258                                 else if (!strncmp(name, "GTPC", 4)) {
11259                                         ptype_mapping[i].sw_ptype |=
11260                                                 RTE_PTYPE_TUNNEL_GTPC;
11261                                         in_tunnel = true;
11262                                 } else if (!strncmp(name, "GTPU", 4)) {
11263                                         ptype_mapping[i].sw_ptype |=
11264                                                 RTE_PTYPE_TUNNEL_GTPU;
11265                                         in_tunnel = true;
11266                                 } else if (!strncmp(name, "GRENAT", 6)) {
11267                                         ptype_mapping[i].sw_ptype |=
11268                                                 RTE_PTYPE_TUNNEL_GRENAT;
11269                                         in_tunnel = true;
11270                                 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11271                                         ptype_mapping[i].sw_ptype |=
11272                                                 RTE_PTYPE_TUNNEL_L2TP;
11273                                         in_tunnel = true;
11274                                 }
11275
11276                                 break;
11277                         }
11278                 }
11279         }
11280
11281         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11282                                                 ptype_num, 0);
11283         if (ret)
11284                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11285
11286         rte_free(ptype_mapping);
11287         rte_free(ptype);
11288         return ret;
11289 }
11290
11291 void
11292 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11293                               uint32_t pkg_size)
11294 {
11295         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11296         uint32_t proto_num;
11297         struct rte_pmd_i40e_proto_info *proto;
11298         uint32_t buff_size;
11299         uint32_t i;
11300         int ret;
11301
11302         /* get information about protocol number */
11303         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11304                                        (uint8_t *)&proto_num, sizeof(proto_num),
11305                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11306         if (ret) {
11307                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11308                 return;
11309         }
11310         if (!proto_num) {
11311                 PMD_DRV_LOG(INFO, "No new protocol added");
11312                 return;
11313         }
11314
11315         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11316         proto = rte_zmalloc("new_proto", buff_size, 0);
11317         if (!proto) {
11318                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11319                 return;
11320         }
11321
11322         /* get information about protocol list */
11323         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11324                                         (uint8_t *)proto, buff_size,
11325                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11326         if (ret) {
11327                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11328                 rte_free(proto);
11329                 return;
11330         }
11331
11332         /* Check if GTP is supported. */
11333         for (i = 0; i < proto_num; i++) {
11334                 if (!strncmp(proto[i].name, "GTP", 3)) {
11335                         pf->gtp_support = true;
11336                         break;
11337                 }
11338         }
11339
11340         /* Update customized pctype info */
11341         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11342                                             proto_num, proto);
11343         if (ret)
11344                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11345
11346         /* Update customized ptype info */
11347         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11348                                            proto_num, proto);
11349         if (ret)
11350                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11351
11352         rte_free(proto);
11353 }
11354
11355 /* Create a QinQ cloud filter
11356  *
11357  * The Fortville NIC has limited resources for tunnel filters,
11358  * so we can only reuse existing filters.
11359  *
11360  * In step 1 we define which Field Vector fields can be used for
11361  * filter types.
11362  * As we do not have the inner tag defined as a field,
11363  * we have to define it first, by reusing one of L1 entries.
11364  *
11365  * In step 2 we are replacing one of existing filter types with
11366  * a new one for QinQ.
11367  * As we reusing L1 and replacing L2, some of the default filter
11368  * types will disappear,which depends on L1 and L2 entries we reuse.
11369  *
11370  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11371  *
11372  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11373  *              later when we define the cloud filter.
11374  *      a.      Valid_flags.replace_cloud = 0
11375  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11376  *      c.      New_filter = 0x10
11377  *      d.      TR bit = 0xff (optional, not used here)
11378  *      e.      Buffer – 2 entries:
11379  *              i.      Byte 0 = 8 (outer vlan FV index).
11380  *                      Byte 1 = 0 (rsv)
11381  *                      Byte 2-3 = 0x0fff
11382  *              ii.     Byte 0 = 37 (inner vlan FV index).
11383  *                      Byte 1 =0 (rsv)
11384  *                      Byte 2-3 = 0x0fff
11385  *
11386  * Step 2:
11387  * 2.   Create cloud filter using two L1 filters entries: stag and
11388  *              new filter(outer vlan+ inner vlan)
11389  *      a.      Valid_flags.replace_cloud = 1
11390  *      b.      Old_filter = 1 (instead of outer IP)
11391  *      c.      New_filter = 0x10
11392  *      d.      Buffer – 2 entries:
11393  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11394  *                      Byte 1-3 = 0 (rsv)
11395  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11396  *                      Byte 9-11 = 0 (rsv)
11397  */
11398 static int
11399 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11400 {
11401         int ret = -ENOTSUP;
11402         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11403         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11404         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11405
11406         /* Init */
11407         memset(&filter_replace, 0,
11408                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11409         memset(&filter_replace_buf, 0,
11410                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11411
11412         /* create L1 filter */
11413         filter_replace.old_filter_type =
11414                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11415         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11416         filter_replace.tr_bit = 0;
11417
11418         /* Prepare the buffer, 2 entries */
11419         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11420         filter_replace_buf.data[0] |=
11421                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11422         /* Field Vector 12b mask */
11423         filter_replace_buf.data[2] = 0xff;
11424         filter_replace_buf.data[3] = 0x0f;
11425         filter_replace_buf.data[4] =
11426                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11427         filter_replace_buf.data[4] |=
11428                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11429         /* Field Vector 12b mask */
11430         filter_replace_buf.data[6] = 0xff;
11431         filter_replace_buf.data[7] = 0x0f;
11432         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11433                         &filter_replace_buf);
11434         if (ret != I40E_SUCCESS)
11435                 return ret;
11436
11437         /* Apply the second L2 cloud filter */
11438         memset(&filter_replace, 0,
11439                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11440         memset(&filter_replace_buf, 0,
11441                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11442
11443         /* create L2 filter, input for L2 filter will be L1 filter  */
11444         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11445         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11446         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11447
11448         /* Prepare the buffer, 2 entries */
11449         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11450         filter_replace_buf.data[0] |=
11451                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11452         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11453         filter_replace_buf.data[4] |=
11454                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11455         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11456                         &filter_replace_buf);
11457         return ret;
11458 }
11459
11460 RTE_INIT(i40e_init_log);
11461 static void
11462 i40e_init_log(void)
11463 {
11464         i40e_logtype_init = rte_log_register("pmd.i40e.init");
11465         if (i40e_logtype_init >= 0)
11466                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11467         i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11468         if (i40e_logtype_driver >= 0)
11469                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
11470 }