drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61 #include "i40e_pf.h"
  62
  63 /* Maximun number of MAC addresses */
  64 #define I40E_NUM_MACADDR_MAX       64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 /* Default queue interrupt throttling time in microseconds */
  78 #define I40E_ITR_INDEX_DEFAULT          0
  79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  80 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA  0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 115
 116 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 117 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 118 static int i40e_dev_configure(struct rte_eth_dev *dev);
 119 static int i40e_dev_start(struct rte_eth_dev *dev);
 120 static void i40e_dev_stop(struct rte_eth_dev *dev);
 121 static void i40e_dev_close(struct rte_eth_dev *dev);
 122 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 127 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 128 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 129                                struct rte_eth_stats *stats);
 130 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 131 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 132                                             uint16_t queue_id,
 133                                             uint8_t stat_idx,
 134                                             uint8_t is_rx);
 135 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 136                               struct rte_eth_dev_info *dev_info);
 137 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 138                                 uint16_t vlan_id,
 139                                 int on);
 140 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 141 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 142 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 143                                       uint16_t queue,
 144                                       int on);
 145 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 146 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 147 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 148 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 149                               struct rte_eth_fc_conf *fc_conf);
 150 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 151                                        struct rte_eth_pfc_conf *pfc_conf);
 152 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 153                           struct ether_addr *mac_addr,
 154                           uint32_t index,
 155                           uint32_t pool);
 156 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 157 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 158                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 159                                     uint16_t reta_size);
 160 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 161                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 162                                    uint16_t reta_size);
 163
 164 static int i40e_get_cap(struct i40e_hw *hw);
 165 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 166 static int i40e_pf_setup(struct i40e_pf *pf);
 167 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 168 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 169 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 170                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 171 static void i40e_stat_update_48(struct i40e_hw *hw,
 172                                uint32_t hireg,
 173                                uint32_t loreg,
 174                                bool offset_loaded,
 175                                uint64_t *offset,
 176                                uint64_t *stat);
 177 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 178 static void i40e_dev_interrupt_handler(
 179                 __rte_unused struct rte_intr_handle *handle, void *param);
 180 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 181                                 uint32_t base, uint32_t num);
 182 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 183 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 184                         uint32_t base);
 185 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 186                         uint16_t num);
 187 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 188 static int i40e_veb_release(struct i40e_veb *veb);
 189 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 190                                                 struct i40e_vsi *vsi);
 191 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 192 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 193 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 194                                              struct i40e_macvlan_filter *mv_f,
 195                                              int num,
 196                                              struct ether_addr *addr);
 197 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 198                                              struct i40e_macvlan_filter *mv_f,
 199                                              int num,
 200                                              uint16_t vlan);
 201 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 202 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 203                                     struct rte_eth_rss_conf *rss_conf);
 204 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 205                                       struct rte_eth_rss_conf *rss_conf);
 206 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 207                                 struct rte_eth_udp_tunnel *udp_tunnel);
 208 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 209                                 struct rte_eth_udp_tunnel *udp_tunnel);
 210 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 211                         struct rte_eth_ethertype_filter *filter,
 212                         bool add);
 213 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 214                                 enum rte_filter_op filter_op,
 215                                 void *arg);
 216 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 217                                 enum rte_filter_type filter_type,
 218                                 enum rte_filter_op filter_op,
 219                                 void *arg);
 220 static void i40e_configure_registers(struct i40e_hw *hw);
 221 static void i40e_hw_init(struct i40e_hw *hw);
 222 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 223 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 224                         struct rte_eth_mirror_conf *mirror_conf,
 225                         uint8_t sw_id, uint8_t on);
 226 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 227
 228 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 229 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 230 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 231                                            struct timespec *timestamp,
 232                                            uint32_t flags);
 233 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 234                                            struct timespec *timestamp);
 235
 236 static const struct rte_pci_id pci_id_i40e_map[] = {
 237 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 238 #include "rte_pci_dev_ids.h"
 239 { .vendor_id = 0, /* sentinel */ },
 240 };
 241
 242 static const struct eth_dev_ops i40e_eth_dev_ops = {
 243         .dev_configure                = i40e_dev_configure,
 244         .dev_start                    = i40e_dev_start,
 245         .dev_stop                     = i40e_dev_stop,
 246         .dev_close                    = i40e_dev_close,
 247         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 248         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 249         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 250         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 251         .dev_set_link_up              = i40e_dev_set_link_up,
 252         .dev_set_link_down            = i40e_dev_set_link_down,
 253         .link_update                  = i40e_dev_link_update,
 254         .stats_get                    = i40e_dev_stats_get,
 255         .stats_reset                  = i40e_dev_stats_reset,
 256         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 257         .dev_infos_get                = i40e_dev_info_get,
 258         .vlan_filter_set              = i40e_vlan_filter_set,
 259         .vlan_tpid_set                = i40e_vlan_tpid_set,
 260         .vlan_offload_set             = i40e_vlan_offload_set,
 261         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 262         .vlan_pvid_set                = i40e_vlan_pvid_set,
 263         .rx_queue_start               = i40e_dev_rx_queue_start,
 264         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 265         .tx_queue_start               = i40e_dev_tx_queue_start,
 266         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 267         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 268         .rx_queue_release             = i40e_dev_rx_queue_release,
 269         .rx_queue_count               = i40e_dev_rx_queue_count,
 270         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 271         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 272         .tx_queue_release             = i40e_dev_tx_queue_release,
 273         .dev_led_on                   = i40e_dev_led_on,
 274         .dev_led_off                  = i40e_dev_led_off,
 275         .flow_ctrl_set                = i40e_flow_ctrl_set,
 276         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 277         .mac_addr_add                 = i40e_macaddr_add,
 278         .mac_addr_remove              = i40e_macaddr_remove,
 279         .reta_update                  = i40e_dev_rss_reta_update,
 280         .reta_query                   = i40e_dev_rss_reta_query,
 281         .rss_hash_update              = i40e_dev_rss_hash_update,
 282         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 283         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 284         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 285         .filter_ctrl                  = i40e_dev_filter_ctrl,
 286         .mirror_rule_set              = i40e_mirror_rule_set,
 287         .mirror_rule_reset            = i40e_mirror_rule_reset,
 288         .timesync_enable              = i40e_timesync_enable,
 289         .timesync_disable             = i40e_timesync_disable,
 290         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 291         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 292 };
 293
 294 static struct eth_driver rte_i40e_pmd = {
 295         .pci_drv = {
 296                 .name = "rte_i40e_pmd",
 297                 .id_table = pci_id_i40e_map,
 298                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 299                         RTE_PCI_DRV_DETACHABLE,
 300         },
 301         .eth_dev_init = eth_i40e_dev_init,
 302         .eth_dev_uninit = eth_i40e_dev_uninit,
 303         .dev_private_size = sizeof(struct i40e_adapter),
 304 };
 305
 306 static inline int
 307 i40e_align_floor(int n)
 308 {
 309         if (n == 0)
 310                 return 0;
 311         return (1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)));
 312 }
 313
 314 static inline int
 315 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 316                                      struct rte_eth_link *link)
 317 {
 318         struct rte_eth_link *dst = link;
 319         struct rte_eth_link *src = &(dev->data->dev_link);
 320
 321         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 322                                         *(uint64_t *)src) == 0)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 static inline int
 329 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 330                                       struct rte_eth_link *link)
 331 {
 332         struct rte_eth_link *dst = &(dev->data->dev_link);
 333         struct rte_eth_link *src = link;
 334
 335         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 336                                         *(uint64_t *)src) == 0)
 337                 return -1;
 338
 339         return 0;
 340 }
 341
 342 /*
 343  * Driver initialization routine.
 344  * Invoked once at EAL init time.
 345  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 346  */
 347 static int
 348 rte_i40e_pmd_init(const char *name __rte_unused,
 349                   const char *params __rte_unused)
 350 {
 351         PMD_INIT_FUNC_TRACE();
 352         rte_eth_driver_register(&rte_i40e_pmd);
 353
 354         return 0;
 355 }
 356
 357 static struct rte_driver rte_i40e_driver = {
 358         .type = PMD_PDEV,
 359         .init = rte_i40e_pmd_init,
 360 };
 361
 362 PMD_REGISTER_DRIVER(rte_i40e_driver);
 363
 364 /*
 365  * Initialize registers for flexible payload, which should be set by NVM.
 366  * This should be removed from code once it is fixed in NVM.
 367  */
 368 #ifndef I40E_GLQF_ORT
 369 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 370 #endif
 371 #ifndef I40E_GLQF_PIT
 372 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 373 #endif
 374
 375 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 376 {
 377         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 378         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 379         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 380         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 381         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 382         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 383         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 384         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 385         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 386         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 387
 388         /* GLQF_PIT Registers */
 389         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 390         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 391 }
 392
 393 static int
 394 eth_i40e_dev_init(struct rte_eth_dev *dev)
 395 {
 396         struct rte_pci_device *pci_dev;
 397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 399         struct i40e_vsi *vsi;
 400         int ret;
 401         uint32_t len;
 402         uint8_t aq_fail = 0;
 403
 404         PMD_INIT_FUNC_TRACE();
 405
 406         dev->dev_ops = &i40e_eth_dev_ops;
 407         dev->rx_pkt_burst = i40e_recv_pkts;
 408         dev->tx_pkt_burst = i40e_xmit_pkts;
 409
 410         /* for secondary processes, we don't initialise any further as primary
 411          * has already done this work. Only check we don't need a different
 412          * RX function */
 413         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 414                 if (dev->data->scattered_rx)
 415                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 416                 return 0;
 417         }
 418         pci_dev = dev->pci_dev;
 419         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 420         pf->adapter->eth_dev = dev;
 421         pf->dev_data = dev->data;
 422
 423         hw->back = I40E_PF_TO_ADAPTER(pf);
 424         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 425         if (!hw->hw_addr) {
 426                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 427                              "as address is NULL");
 428                 return -ENODEV;
 429         }
 430
 431         hw->vendor_id = pci_dev->id.vendor_id;
 432         hw->device_id = pci_dev->id.device_id;
 433         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 434         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 435         hw->bus.device = pci_dev->addr.devid;
 436         hw->bus.func = pci_dev->addr.function;
 437         hw->adapter_stopped = 0;
 438
 439         /* Make sure all is clean before doing PF reset */
 440         i40e_clear_hw(hw);
 441
 442         /* Initialize the hardware */
 443         i40e_hw_init(hw);
 444
 445         /* Reset here to make sure all is clean for each PF */
 446         ret = i40e_pf_reset(hw);
 447         if (ret) {
 448                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 449                 return ret;
 450         }
 451
 452         /* Initialize the shared code (base driver) */
 453         ret = i40e_init_shared_code(hw);
 454         if (ret) {
 455                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 456                 return ret;
 457         }
 458
 459         /*
 460          * To work around the NVM issue,initialize registers
 461          * for flexible payload by software.
 462          * It should be removed once issues are fixed in NVM.
 463          */
 464         i40e_flex_payload_reg_init(hw);
 465
 466         /* Initialize the parameters for adminq */
 467         i40e_init_adminq_parameter(hw);
 468         ret = i40e_init_adminq(hw);
 469         if (ret != I40E_SUCCESS) {
 470                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 471                 return -EIO;
 472         }
 473         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 474                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 475                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 476                      ((hw->nvm.version >> 12) & 0xf),
 477                      ((hw->nvm.version >> 4) & 0xff),
 478                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 479
 480         /* Disable LLDP */
 481         ret = i40e_aq_stop_lldp(hw, true, NULL);
 482         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 483                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 484
 485         /* Clear PXE mode */
 486         i40e_clear_pxe_mode(hw);
 487
 488         /*
 489          * On X710, performance number is far from the expectation on recent
 490          * firmware versions. The fix for this issue may not be integrated in
 491          * the following firmware version. So the workaround in software driver
 492          * is needed. It needs to modify the initial values of 3 internal only
 493          * registers. Note that the workaround can be removed when it is fixed
 494          * in firmware in the future.
 495          */
 496         i40e_configure_registers(hw);
 497
 498         /* Get hw capabilities */
 499         ret = i40e_get_cap(hw);
 500         if (ret != I40E_SUCCESS) {
 501                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 502                 goto err_get_capabilities;
 503         }
 504
 505         /* Initialize parameters for PF */
 506         ret = i40e_pf_parameter_init(dev);
 507         if (ret != 0) {
 508                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 509                 goto err_parameter_init;
 510         }
 511
 512         /* Initialize the queue management */
 513         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 514         if (ret < 0) {
 515                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 516                 goto err_qp_pool_init;
 517         }
 518         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 519                                 hw->func_caps.num_msix_vectors - 1);
 520         if (ret < 0) {
 521                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 522                 goto err_msix_pool_init;
 523         }
 524
 525         /* Initialize lan hmc */
 526         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 527                                 hw->func_caps.num_rx_qp, 0, 0);
 528         if (ret != I40E_SUCCESS) {
 529                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 530                 goto err_init_lan_hmc;
 531         }
 532
 533         /* Configure lan hmc */
 534         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 535         if (ret != I40E_SUCCESS) {
 536                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 537                 goto err_configure_lan_hmc;
 538         }
 539
 540         /* Get and check the mac address */
 541         i40e_get_mac_addr(hw, hw->mac.addr);
 542         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 543                 PMD_INIT_LOG(ERR, "mac address is not valid");
 544                 ret = -EIO;
 545                 goto err_get_mac_addr;
 546         }
 547         /* Copy the permanent MAC address */
 548         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 549                         (struct ether_addr *) hw->mac.perm_addr);
 550
 551         /* Disable flow control */
 552         hw->fc.requested_mode = I40E_FC_NONE;
 553         i40e_set_fc(hw, &aq_fail, TRUE);
 554
 555         /* PF setup, which includes VSI setup */
 556         ret = i40e_pf_setup(pf);
 557         if (ret) {
 558                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 559                 goto err_setup_pf_switch;
 560         }
 561
 562         vsi = pf->main_vsi;
 563
 564         /* Disable double vlan by default */
 565         i40e_vsi_config_double_vlan(vsi, FALSE);
 566
 567         if (!vsi->max_macaddrs)
 568                 len = ETHER_ADDR_LEN;
 569         else
 570                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 571
 572         /* Should be after VSI initialized */
 573         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 574         if (!dev->data->mac_addrs) {
 575                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 576                                         "for storing mac address");
 577                 goto err_mac_alloc;
 578         }
 579         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 580                                         &dev->data->mac_addrs[0]);
 581
 582         /* initialize pf host driver to setup SRIOV resource if applicable */
 583         i40e_pf_host_init(dev);
 584
 585         /* register callback func to eal lib */
 586         rte_intr_callback_register(&(pci_dev->intr_handle),
 587                 i40e_dev_interrupt_handler, (void *)dev);
 588
 589         /* configure and enable device interrupt */
 590         i40e_pf_config_irq0(hw);
 591         i40e_pf_enable_irq0(hw);
 592
 593         /* enable uio intr after callback register */
 594         rte_intr_enable(&(pci_dev->intr_handle));
 595
 596         /* initialize mirror rule list */
 597         TAILQ_INIT(&pf->mirror_list);
 598
 599         return 0;
 600
 601 err_mac_alloc:
 602         i40e_vsi_release(pf->main_vsi);
 603 err_setup_pf_switch:
 604 err_get_mac_addr:
 605 err_configure_lan_hmc:
 606         (void)i40e_shutdown_lan_hmc(hw);
 607 err_init_lan_hmc:
 608         i40e_res_pool_destroy(&pf->msix_pool);
 609 err_msix_pool_init:
 610         i40e_res_pool_destroy(&pf->qp_pool);
 611 err_qp_pool_init:
 612 err_parameter_init:
 613 err_get_capabilities:
 614         (void)i40e_shutdown_adminq(hw);
 615
 616         return ret;
 617 }
 618
 619 static int
 620 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 621 {
 622         struct rte_pci_device *pci_dev;
 623         struct i40e_hw *hw;
 624         struct i40e_filter_control_settings settings;
 625         int ret;
 626         uint8_t aq_fail = 0;
 627
 628         PMD_INIT_FUNC_TRACE();
 629
 630         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 631                 return 0;
 632
 633         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 634         pci_dev = dev->pci_dev;
 635
 636         if (hw->adapter_stopped == 0)
 637                 i40e_dev_close(dev);
 638
 639         dev->dev_ops = NULL;
 640         dev->rx_pkt_burst = NULL;
 641         dev->tx_pkt_burst = NULL;
 642
 643         /* Disable LLDP */
 644         ret = i40e_aq_stop_lldp(hw, true, NULL);
 645         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 646                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 647
 648         /* Clear PXE mode */
 649         i40e_clear_pxe_mode(hw);
 650
 651         /* Unconfigure filter control */
 652         memset(&settings, 0, sizeof(settings));
 653         ret = i40e_set_filter_control(hw, &settings);
 654         if (ret)
 655                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 656                                         ret);
 657
 658         /* Disable flow control */
 659         hw->fc.requested_mode = I40E_FC_NONE;
 660         i40e_set_fc(hw, &aq_fail, TRUE);
 661
 662         /* uninitialize pf host driver */
 663         i40e_pf_host_uninit(dev);
 664
 665         rte_free(dev->data->mac_addrs);
 666         dev->data->mac_addrs = NULL;
 667
 668         /* disable uio intr before callback unregister */
 669         rte_intr_disable(&(pci_dev->intr_handle));
 670
 671         /* register callback func to eal lib */
 672         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 673                 i40e_dev_interrupt_handler, (void *)dev);
 674
 675         return 0;
 676 }
 677
 678 static int
 679 i40e_dev_configure(struct rte_eth_dev *dev)
 680 {
 681         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 682         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 683         int ret;
 684
 685         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 686                 ret = i40e_fdir_setup(pf);
 687                 if (ret != I40E_SUCCESS) {
 688                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 689                         return -ENOTSUP;
 690                 }
 691                 ret = i40e_fdir_configure(dev);
 692                 if (ret < 0) {
 693                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 694                         goto err;
 695                 }
 696         } else
 697                 i40e_fdir_teardown(pf);
 698
 699         ret = i40e_dev_init_vlan(dev);
 700         if (ret < 0)
 701                 goto err;
 702
 703         /* VMDQ setup.
 704          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 705          *  RSS setting have different requirements.
 706          *  General PMD driver call sequence are NIC init, configure,
 707          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 708          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 709          *  applicable. So, VMDQ setting has to be done before
 710          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 711          *  For RSS setting, it will try to calculate actual configured RX queue
 712          *  number, which will be available after rx_queue_setup(). dev_start()
 713          *  function is good to place RSS setup.
 714          */
 715         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 716                 ret = i40e_vmdq_setup(dev);
 717                 if (ret)
 718                         goto err;
 719         }
 720         return 0;
 721 err:
 722         i40e_fdir_teardown(pf);
 723         return ret;
 724 }
 725
 726 void
 727 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 728 {
 729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 730         uint16_t msix_vect = vsi->msix_intr;
 731         uint16_t i;
 732
 733         for (i = 0; i < vsi->nb_qps; i++) {
 734                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 735                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 736                 rte_wmb();
 737         }
 738
 739         if (vsi->type != I40E_VSI_SRIOV) {
 740                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 741                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 742                                 msix_vect - 1), 0);
 743         } else {
 744                 uint32_t reg;
 745                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 746                         vsi->user_param + (msix_vect - 1);
 747
 748                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 749         }
 750         I40E_WRITE_FLUSH(hw);
 751 }
 752
 753 static inline uint16_t
 754 i40e_calc_itr_interval(int16_t interval)
 755 {
 756         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 757                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 758
 759         /* Convert to hardware count, as writing each 1 represents 2 us */
 760         return (interval/2);
 761 }
 762
 763 void
 764 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 765 {
 766         uint32_t val;
 767         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 768         uint16_t msix_vect = vsi->msix_intr;
 769         int i;
 770
 771         for (i = 0; i < vsi->nb_qps; i++)
 772                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 773
 774         /* Bind all RX queues to allocated MSIX interrupt */
 775         for (i = 0; i < vsi->nb_qps; i++) {
 776                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 777                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 778                         ((vsi->base_queue + i + 1) <<
 779                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 780                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 781                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 782
 783                 if (i == vsi->nb_qps - 1)
 784                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 785                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 786         }
 787
 788         /* Write first RX queue to Link list register as the head element */
 789         if (vsi->type != I40E_VSI_SRIOV) {
 790                 uint16_t interval =
 791                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 792
 793                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 794                                                 (vsi->base_queue <<
 795                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 796                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 797
 798                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 799                                                 msix_vect - 1), interval);
 800
 801 #ifndef I40E_GLINT_CTL
 802 #define I40E_GLINT_CTL                     0x0003F800
 803 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 804 #endif
 805                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 806                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 807                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 808         } else {
 809                 uint32_t reg;
 810
 811                 /* num_msix_vectors_vf needs to minus irq0 */
 812                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 813                         vsi->user_param + (msix_vect - 1);
 814
 815                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 816                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 817                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 818         }
 819
 820         I40E_WRITE_FLUSH(hw);
 821 }
 822
 823 static void
 824 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 825 {
 826         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 827         uint16_t interval = i40e_calc_itr_interval(\
 828                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 829
 830         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 831                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 832                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 833                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 834                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 835 }
 836
 837 static void
 838 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 839 {
 840         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 841
 842         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 843 }
 844
 845 static inline uint8_t
 846 i40e_parse_link_speed(uint16_t eth_link_speed)
 847 {
 848         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 849
 850         switch (eth_link_speed) {
 851         case ETH_LINK_SPEED_40G:
 852                 link_speed = I40E_LINK_SPEED_40GB;
 853                 break;
 854         case ETH_LINK_SPEED_20G:
 855                 link_speed = I40E_LINK_SPEED_20GB;
 856                 break;
 857         case ETH_LINK_SPEED_10G:
 858                 link_speed = I40E_LINK_SPEED_10GB;
 859                 break;
 860         case ETH_LINK_SPEED_1000:
 861                 link_speed = I40E_LINK_SPEED_1GB;
 862                 break;
 863         case ETH_LINK_SPEED_100:
 864                 link_speed = I40E_LINK_SPEED_100MB;
 865                 break;
 866         }
 867
 868         return link_speed;
 869 }
 870
 871 static int
 872 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 873 {
 874         enum i40e_status_code status;
 875         struct i40e_aq_get_phy_abilities_resp phy_ab;
 876         struct i40e_aq_set_phy_config phy_conf;
 877         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 878                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 879                         I40E_AQ_PHY_FLAG_LOW_POWER;
 880         const uint8_t advt = I40E_LINK_SPEED_40GB |
 881                         I40E_LINK_SPEED_10GB |
 882                         I40E_LINK_SPEED_1GB |
 883                         I40E_LINK_SPEED_100MB;
 884         int ret = -ENOTSUP;
 885
 886         /* Skip it on 40G interfaces, as a workaround for the link issue */
 887         if (i40e_is_40G_device(hw->device_id))
 888                 return I40E_SUCCESS;
 889
 890         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 891                                               NULL);
 892         if (status)
 893                 return ret;
 894
 895         memset(&phy_conf, 0, sizeof(phy_conf));
 896
 897         /* bits 0-2 use the values from get_phy_abilities_resp */
 898         abilities &= ~mask;
 899         abilities |= phy_ab.abilities & mask;
 900
 901         /* update ablities and speed */
 902         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 903                 phy_conf.link_speed = advt;
 904         else
 905                 phy_conf.link_speed = force_speed;
 906
 907         phy_conf.abilities = abilities;
 908
 909         /* use get_phy_abilities_resp value for the rest */
 910         phy_conf.phy_type = phy_ab.phy_type;
 911         phy_conf.eee_capability = phy_ab.eee_capability;
 912         phy_conf.eeer = phy_ab.eeer_val;
 913         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 914
 915         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 916                     phy_ab.abilities, phy_ab.link_speed);
 917         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 918                     phy_conf.abilities, phy_conf.link_speed);
 919
 920         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 921         if (status)
 922                 return ret;
 923
 924         return I40E_SUCCESS;
 925 }
 926
 927 static int
 928 i40e_apply_link_speed(struct rte_eth_dev *dev)
 929 {
 930         uint8_t speed;
 931         uint8_t abilities = 0;
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933         struct rte_eth_conf *conf = &dev->data->dev_conf;
 934
 935         speed = i40e_parse_link_speed(conf->link_speed);
 936         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 937         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 938                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 939         else
 940                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 941
 942         return i40e_phy_conf_link(hw, abilities, speed);
 943 }
 944
 945 static int
 946 i40e_dev_start(struct rte_eth_dev *dev)
 947 {
 948         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 949         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 950         struct i40e_vsi *main_vsi = pf->main_vsi;
 951         int ret, i;
 952
 953         hw->adapter_stopped = 0;
 954
 955         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
 956                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
 957                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
 958                              dev->data->dev_conf.link_duplex,
 959                              dev->data->port_id);
 960                 return -EINVAL;
 961         }
 962
 963         /* Initialize VSI */
 964         ret = i40e_dev_rxtx_init(pf);
 965         if (ret != I40E_SUCCESS) {
 966                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
 967                 goto err_up;
 968         }
 969
 970         /* Map queues with MSIX interrupt */
 971         i40e_vsi_queues_bind_intr(main_vsi);
 972         i40e_vsi_enable_queues_intr(main_vsi);
 973
 974         /* Map VMDQ VSI queues with MSIX interrupt */
 975         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 976                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
 977                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
 978         }
 979
 980         /* enable FDIR MSIX interrupt */
 981         if (pf->fdir.fdir_vsi) {
 982                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
 983                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
 984         }
 985
 986         /* Enable all queues which have been configured */
 987         ret = i40e_dev_switch_queues(pf, TRUE);
 988         if (ret != I40E_SUCCESS) {
 989                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
 990                 goto err_up;
 991         }
 992
 993         /* Enable receiving broadcast packets */
 994         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
 995         if (ret != I40E_SUCCESS)
 996                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
 997
 998         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
 999                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1000                                                 true, NULL);
1001                 if (ret != I40E_SUCCESS)
1002                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1003         }
1004
1005         /* Apply link configure */
1006         ret = i40e_apply_link_speed(dev);
1007         if (I40E_SUCCESS != ret) {
1008                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1009                 goto err_up;
1010         }
1011
1012         return I40E_SUCCESS;
1013
1014 err_up:
1015         i40e_dev_switch_queues(pf, FALSE);
1016         i40e_dev_clear_queues(dev);
1017
1018         return ret;
1019 }
1020
1021 static void
1022 i40e_dev_stop(struct rte_eth_dev *dev)
1023 {
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_vsi *main_vsi = pf->main_vsi;
1026         struct i40e_mirror_rule *p_mirror;
1027         int i;
1028
1029         /* Disable all queues */
1030         i40e_dev_switch_queues(pf, FALSE);
1031
1032         /* un-map queues with interrupt registers */
1033         i40e_vsi_disable_queues_intr(main_vsi);
1034         i40e_vsi_queues_unbind_intr(main_vsi);
1035
1036         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1037                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1038                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1039         }
1040
1041         if (pf->fdir.fdir_vsi) {
1042                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1043                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1044         }
1045         /* Clear all queues and release memory */
1046         i40e_dev_clear_queues(dev);
1047
1048         /* Set link down */
1049         i40e_dev_set_link_down(dev);
1050
1051         /* Remove all mirror rules */
1052         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1053                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1054                 rte_free(p_mirror);
1055         }
1056         pf->nb_mirror_rule = 0;
1057
1058 }
1059
1060 static void
1061 i40e_dev_close(struct rte_eth_dev *dev)
1062 {
1063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1064         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1065         uint32_t reg;
1066
1067         PMD_INIT_FUNC_TRACE();
1068
1069         i40e_dev_stop(dev);
1070         hw->adapter_stopped = 1;
1071
1072         /* Disable interrupt */
1073         i40e_pf_disable_irq0(hw);
1074         rte_intr_disable(&(dev->pci_dev->intr_handle));
1075
1076         /* shutdown and destroy the HMC */
1077         i40e_shutdown_lan_hmc(hw);
1078
1079         /* release all the existing VSIs and VEBs */
1080         i40e_fdir_teardown(pf);
1081         i40e_vsi_release(pf->main_vsi);
1082
1083         /* shutdown the adminq */
1084         i40e_aq_queue_shutdown(hw, true);
1085         i40e_shutdown_adminq(hw);
1086
1087         i40e_res_pool_destroy(&pf->qp_pool);
1088         i40e_res_pool_destroy(&pf->msix_pool);
1089
1090         /* force a PF reset to clean anything leftover */
1091         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1092         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1093                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1094         I40E_WRITE_FLUSH(hw);
1095 }
1096
1097 static void
1098 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1099 {
1100         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102         struct i40e_vsi *vsi = pf->main_vsi;
1103         int status;
1104
1105         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1106                                                         true, NULL);
1107         if (status != I40E_SUCCESS)
1108                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1109
1110         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1111                                                         TRUE, NULL);
1112         if (status != I40E_SUCCESS)
1113                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1114
1115 }
1116
1117 static void
1118 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1119 {
1120         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1121         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1122         struct i40e_vsi *vsi = pf->main_vsi;
1123         int status;
1124
1125         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1126                                                         false, NULL);
1127         if (status != I40E_SUCCESS)
1128                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1129
1130         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1131                                                         false, NULL);
1132         if (status != I40E_SUCCESS)
1133                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1134 }
1135
1136 static void
1137 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1138 {
1139         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1140         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141         struct i40e_vsi *vsi = pf->main_vsi;
1142         int ret;
1143
1144         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1145         if (ret != I40E_SUCCESS)
1146                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1147 }
1148
1149 static void
1150 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1151 {
1152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1154         struct i40e_vsi *vsi = pf->main_vsi;
1155         int ret;
1156
1157         if (dev->data->promiscuous == 1)
1158                 return; /* must remain in all_multicast mode */
1159
1160         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1161                                 vsi->seid, FALSE, NULL);
1162         if (ret != I40E_SUCCESS)
1163                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1164 }
1165
1166 /*
1167  * Set device link up.
1168  */
1169 static int
1170 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1171 {
1172         /* re-apply link speed setting */
1173         return i40e_apply_link_speed(dev);
1174 }
1175
1176 /*
1177  * Set device link down.
1178  */
1179 static int
1180 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1181 {
1182         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1183         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1184         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1185
1186         return i40e_phy_conf_link(hw, abilities, speed);
1187 }
1188
1189 int
1190 i40e_dev_link_update(struct rte_eth_dev *dev,
1191                      int wait_to_complete)
1192 {
1193 #define CHECK_INTERVAL 100  /* 100ms */
1194 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1195         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196         struct i40e_link_status link_status;
1197         struct rte_eth_link link, old;
1198         int status;
1199         unsigned rep_cnt = MAX_REPEAT_TIME;
1200
1201         memset(&link, 0, sizeof(link));
1202         memset(&old, 0, sizeof(old));
1203         memset(&link_status, 0, sizeof(link_status));
1204         rte_i40e_dev_atomic_read_link_status(dev, &old);
1205
1206         do {
1207                 /* Get link status information from hardware */
1208                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1209                 if (status != I40E_SUCCESS) {
1210                         link.link_speed = ETH_LINK_SPEED_100;
1211                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1212                         PMD_DRV_LOG(ERR, "Failed to get link info");
1213                         goto out;
1214                 }
1215
1216                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1217                 if (!wait_to_complete)
1218                         break;
1219
1220                 rte_delay_ms(CHECK_INTERVAL);
1221         } while (!link.link_status && rep_cnt--);
1222
1223         if (!link.link_status)
1224                 goto out;
1225
1226         /* i40e uses full duplex only */
1227         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1228
1229         /* Parse the link status */
1230         switch (link_status.link_speed) {
1231         case I40E_LINK_SPEED_100MB:
1232                 link.link_speed = ETH_LINK_SPEED_100;
1233                 break;
1234         case I40E_LINK_SPEED_1GB:
1235                 link.link_speed = ETH_LINK_SPEED_1000;
1236                 break;
1237         case I40E_LINK_SPEED_10GB:
1238                 link.link_speed = ETH_LINK_SPEED_10G;
1239                 break;
1240         case I40E_LINK_SPEED_20GB:
1241                 link.link_speed = ETH_LINK_SPEED_20G;
1242                 break;
1243         case I40E_LINK_SPEED_40GB:
1244                 link.link_speed = ETH_LINK_SPEED_40G;
1245                 break;
1246         default:
1247                 link.link_speed = ETH_LINK_SPEED_100;
1248                 break;
1249         }
1250
1251 out:
1252         rte_i40e_dev_atomic_write_link_status(dev, &link);
1253         if (link.link_status == old.link_status)
1254                 return -1;
1255
1256         return 0;
1257 }
1258
1259 /* Get all the statistics of a VSI */
1260 void
1261 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1262 {
1263         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1264         struct i40e_eth_stats *nes = &vsi->eth_stats;
1265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1266         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1267
1268         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1269                             vsi->offset_loaded, &oes->rx_bytes,
1270                             &nes->rx_bytes);
1271         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1272                             vsi->offset_loaded, &oes->rx_unicast,
1273                             &nes->rx_unicast);
1274         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1275                             vsi->offset_loaded, &oes->rx_multicast,
1276                             &nes->rx_multicast);
1277         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1278                             vsi->offset_loaded, &oes->rx_broadcast,
1279                             &nes->rx_broadcast);
1280         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1281                             &oes->rx_discards, &nes->rx_discards);
1282         /* GLV_REPC not supported */
1283         /* GLV_RMPC not supported */
1284         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1285                             &oes->rx_unknown_protocol,
1286                             &nes->rx_unknown_protocol);
1287         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1288                             vsi->offset_loaded, &oes->tx_bytes,
1289                             &nes->tx_bytes);
1290         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1291                             vsi->offset_loaded, &oes->tx_unicast,
1292                             &nes->tx_unicast);
1293         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1294                             vsi->offset_loaded, &oes->tx_multicast,
1295                             &nes->tx_multicast);
1296         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1297                             vsi->offset_loaded,  &oes->tx_broadcast,
1298                             &nes->tx_broadcast);
1299         /* GLV_TDPC not supported */
1300         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1301                             &oes->tx_errors, &nes->tx_errors);
1302         vsi->offset_loaded = true;
1303
1304         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1305                     vsi->vsi_id);
1306         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1307         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1308         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1309         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1310         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1311         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1312                     nes->rx_unknown_protocol);
1313         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1314         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1315         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1316         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1317         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1318         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1319         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1320                     vsi->vsi_id);
1321 }
1322
1323 /* Get all statistics of a port */
1324 static void
1325 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1326 {
1327         uint32_t i;
1328         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1330         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1331         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1332
1333         /* Get statistics of struct i40e_eth_stats */
1334         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1335                             I40E_GLPRT_GORCL(hw->port),
1336                             pf->offset_loaded, &os->eth.rx_bytes,
1337                             &ns->eth.rx_bytes);
1338         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1339                             I40E_GLPRT_UPRCL(hw->port),
1340                             pf->offset_loaded, &os->eth.rx_unicast,
1341                             &ns->eth.rx_unicast);
1342         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1343                             I40E_GLPRT_MPRCL(hw->port),
1344                             pf->offset_loaded, &os->eth.rx_multicast,
1345                             &ns->eth.rx_multicast);
1346         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1347                             I40E_GLPRT_BPRCL(hw->port),
1348                             pf->offset_loaded, &os->eth.rx_broadcast,
1349                             &ns->eth.rx_broadcast);
1350         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1351                             pf->offset_loaded, &os->eth.rx_discards,
1352                             &ns->eth.rx_discards);
1353         /* GLPRT_REPC not supported */
1354         /* GLPRT_RMPC not supported */
1355         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1356                             pf->offset_loaded,
1357                             &os->eth.rx_unknown_protocol,
1358                             &ns->eth.rx_unknown_protocol);
1359         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1360                             I40E_GLPRT_GOTCL(hw->port),
1361                             pf->offset_loaded, &os->eth.tx_bytes,
1362                             &ns->eth.tx_bytes);
1363         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1364                             I40E_GLPRT_UPTCL(hw->port),
1365                             pf->offset_loaded, &os->eth.tx_unicast,
1366                             &ns->eth.tx_unicast);
1367         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1368                             I40E_GLPRT_MPTCL(hw->port),
1369                             pf->offset_loaded, &os->eth.tx_multicast,
1370                             &ns->eth.tx_multicast);
1371         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1372                             I40E_GLPRT_BPTCL(hw->port),
1373                             pf->offset_loaded, &os->eth.tx_broadcast,
1374                             &ns->eth.tx_broadcast);
1375         /* GLPRT_TEPC not supported */
1376
1377         /* additional port specific stats */
1378         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1379                             pf->offset_loaded, &os->tx_dropped_link_down,
1380                             &ns->tx_dropped_link_down);
1381         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1382                             pf->offset_loaded, &os->crc_errors,
1383                             &ns->crc_errors);
1384         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1385                             pf->offset_loaded, &os->illegal_bytes,
1386                             &ns->illegal_bytes);
1387         /* GLPRT_ERRBC not supported */
1388         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1389                             pf->offset_loaded, &os->mac_local_faults,
1390                             &ns->mac_local_faults);
1391         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1392                             pf->offset_loaded, &os->mac_remote_faults,
1393                             &ns->mac_remote_faults);
1394         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1395                             pf->offset_loaded, &os->rx_length_errors,
1396                             &ns->rx_length_errors);
1397         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1398                             pf->offset_loaded, &os->link_xon_rx,
1399                             &ns->link_xon_rx);
1400         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1401                             pf->offset_loaded, &os->link_xoff_rx,
1402                             &ns->link_xoff_rx);
1403         for (i = 0; i < 8; i++) {
1404                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1405                                     pf->offset_loaded,
1406                                     &os->priority_xon_rx[i],
1407                                     &ns->priority_xon_rx[i]);
1408                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1409                                     pf->offset_loaded,
1410                                     &os->priority_xoff_rx[i],
1411                                     &ns->priority_xoff_rx[i]);
1412         }
1413         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1414                             pf->offset_loaded, &os->link_xon_tx,
1415                             &ns->link_xon_tx);
1416         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1417                             pf->offset_loaded, &os->link_xoff_tx,
1418                             &ns->link_xoff_tx);
1419         for (i = 0; i < 8; i++) {
1420                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1421                                     pf->offset_loaded,
1422                                     &os->priority_xon_tx[i],
1423                                     &ns->priority_xon_tx[i]);
1424                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1425                                     pf->offset_loaded,
1426                                     &os->priority_xoff_tx[i],
1427                                     &ns->priority_xoff_tx[i]);
1428                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1429                                     pf->offset_loaded,
1430                                     &os->priority_xon_2_xoff[i],
1431                                     &ns->priority_xon_2_xoff[i]);
1432         }
1433         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1434                             I40E_GLPRT_PRC64L(hw->port),
1435                             pf->offset_loaded, &os->rx_size_64,
1436                             &ns->rx_size_64);
1437         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1438                             I40E_GLPRT_PRC127L(hw->port),
1439                             pf->offset_loaded, &os->rx_size_127,
1440                             &ns->rx_size_127);
1441         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1442                             I40E_GLPRT_PRC255L(hw->port),
1443                             pf->offset_loaded, &os->rx_size_255,
1444                             &ns->rx_size_255);
1445         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1446                             I40E_GLPRT_PRC511L(hw->port),
1447                             pf->offset_loaded, &os->rx_size_511,
1448                             &ns->rx_size_511);
1449         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1450                             I40E_GLPRT_PRC1023L(hw->port),
1451                             pf->offset_loaded, &os->rx_size_1023,
1452                             &ns->rx_size_1023);
1453         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1454                             I40E_GLPRT_PRC1522L(hw->port),
1455                             pf->offset_loaded, &os->rx_size_1522,
1456                             &ns->rx_size_1522);
1457         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1458                             I40E_GLPRT_PRC9522L(hw->port),
1459                             pf->offset_loaded, &os->rx_size_big,
1460                             &ns->rx_size_big);
1461         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1462                             pf->offset_loaded, &os->rx_undersize,
1463                             &ns->rx_undersize);
1464         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1465                             pf->offset_loaded, &os->rx_fragments,
1466                             &ns->rx_fragments);
1467         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1468                             pf->offset_loaded, &os->rx_oversize,
1469                             &ns->rx_oversize);
1470         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1471                             pf->offset_loaded, &os->rx_jabber,
1472                             &ns->rx_jabber);
1473         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1474                             I40E_GLPRT_PTC64L(hw->port),
1475                             pf->offset_loaded, &os->tx_size_64,
1476                             &ns->tx_size_64);
1477         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1478                             I40E_GLPRT_PTC127L(hw->port),
1479                             pf->offset_loaded, &os->tx_size_127,
1480                             &ns->tx_size_127);
1481         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1482                             I40E_GLPRT_PTC255L(hw->port),
1483                             pf->offset_loaded, &os->tx_size_255,
1484                             &ns->tx_size_255);
1485         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1486                             I40E_GLPRT_PTC511L(hw->port),
1487                             pf->offset_loaded, &os->tx_size_511,
1488                             &ns->tx_size_511);
1489         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1490                             I40E_GLPRT_PTC1023L(hw->port),
1491                             pf->offset_loaded, &os->tx_size_1023,
1492                             &ns->tx_size_1023);
1493         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1494                             I40E_GLPRT_PTC1522L(hw->port),
1495                             pf->offset_loaded, &os->tx_size_1522,
1496                             &ns->tx_size_1522);
1497         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1498                             I40E_GLPRT_PTC9522L(hw->port),
1499                             pf->offset_loaded, &os->tx_size_big,
1500                             &ns->tx_size_big);
1501         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1502                            pf->offset_loaded,
1503                            &os->fd_sb_match, &ns->fd_sb_match);
1504         /* GLPRT_MSPDC not supported */
1505         /* GLPRT_XEC not supported */
1506
1507         pf->offset_loaded = true;
1508
1509         if (pf->main_vsi)
1510                 i40e_update_vsi_stats(pf->main_vsi);
1511
1512         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1513                                                 ns->eth.rx_broadcast;
1514         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1515                                                 ns->eth.tx_broadcast;
1516         stats->ibytes   = ns->eth.rx_bytes;
1517         stats->obytes   = ns->eth.tx_bytes;
1518         stats->oerrors  = ns->eth.tx_errors;
1519         stats->imcasts  = ns->eth.rx_multicast;
1520         stats->fdirmatch = ns->fd_sb_match;
1521
1522         /* Rx Errors */
1523         stats->ibadcrc  = ns->crc_errors;
1524         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1525                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1526         stats->imissed  = ns->eth.rx_discards;
1527         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1528
1529         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1530         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1531         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1532         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1533         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1534         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1535         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1536                     ns->eth.rx_unknown_protocol);
1537         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1538         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1539         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1540         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1541         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1542         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1543
1544         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1545                     ns->tx_dropped_link_down);
1546         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1547         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1548                     ns->illegal_bytes);
1549         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1550         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1551                     ns->mac_local_faults);
1552         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1553                     ns->mac_remote_faults);
1554         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1555                     ns->rx_length_errors);
1556         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1557         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1558         for (i = 0; i < 8; i++) {
1559                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1560                                 i, ns->priority_xon_rx[i]);
1561                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1562                                 i, ns->priority_xoff_rx[i]);
1563         }
1564         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1565         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1566         for (i = 0; i < 8; i++) {
1567                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1568                                 i, ns->priority_xon_tx[i]);
1569                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1570                                 i, ns->priority_xoff_tx[i]);
1571                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1572                                 i, ns->priority_xon_2_xoff[i]);
1573         }
1574         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1575         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1576         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1577         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1578         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1579         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1580         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1581         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1582         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1583         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1584         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1585         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1586         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1587         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1588         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1589         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1590         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1591         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1592         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1593                         ns->mac_short_packet_dropped);
1594         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1595                     ns->checksum_error);
1596         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1597         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1598 }
1599
1600 /* Reset the statistics */
1601 static void
1602 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1603 {
1604         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1605
1606         /* It results in reloading the start point of each counter */
1607         pf->offset_loaded = false;
1608 }
1609
1610 static int
1611 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1612                                  __rte_unused uint16_t queue_id,
1613                                  __rte_unused uint8_t stat_idx,
1614                                  __rte_unused uint8_t is_rx)
1615 {
1616         PMD_INIT_FUNC_TRACE();
1617
1618         return -ENOSYS;
1619 }
1620
1621 static void
1622 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1623 {
1624         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1625         struct i40e_vsi *vsi = pf->main_vsi;
1626
1627         dev_info->max_rx_queues = vsi->nb_qps;
1628         dev_info->max_tx_queues = vsi->nb_qps;
1629         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1630         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1631         dev_info->max_mac_addrs = vsi->max_macaddrs;
1632         dev_info->max_vfs = dev->pci_dev->max_vfs;
1633         dev_info->rx_offload_capa =
1634                 DEV_RX_OFFLOAD_VLAN_STRIP |
1635                 DEV_RX_OFFLOAD_QINQ_STRIP |
1636                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1637                 DEV_RX_OFFLOAD_UDP_CKSUM |
1638                 DEV_RX_OFFLOAD_TCP_CKSUM;
1639         dev_info->tx_offload_capa =
1640                 DEV_TX_OFFLOAD_VLAN_INSERT |
1641                 DEV_TX_OFFLOAD_QINQ_INSERT |
1642                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1643                 DEV_TX_OFFLOAD_UDP_CKSUM |
1644                 DEV_TX_OFFLOAD_TCP_CKSUM |
1645                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1646                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1647                 DEV_TX_OFFLOAD_TCP_TSO;
1648         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1649                                                 sizeof(uint32_t);
1650         dev_info->reta_size = pf->hash_lut_size;
1651         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1652
1653         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1654                 .rx_thresh = {
1655                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1656                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1657                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1658                 },
1659                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1660                 .rx_drop_en = 0,
1661         };
1662
1663         dev_info->default_txconf = (struct rte_eth_txconf) {
1664                 .tx_thresh = {
1665                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1666                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1667                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1668                 },
1669                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1670                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1671                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1672                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1673         };
1674
1675         if (pf->flags & I40E_FLAG_VMDQ) {
1676                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1677                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1678                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1679                                                 pf->max_nb_vmdq_vsi;
1680                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1681                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1682                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1683         }
1684 }
1685
1686 static int
1687 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1688 {
1689         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1690         struct i40e_vsi *vsi = pf->main_vsi;
1691         PMD_INIT_FUNC_TRACE();
1692
1693         if (on)
1694                 return i40e_vsi_add_vlan(vsi, vlan_id);
1695         else
1696                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1697 }
1698
1699 static void
1700 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1701                    __rte_unused uint16_t tpid)
1702 {
1703         PMD_INIT_FUNC_TRACE();
1704 }
1705
1706 static void
1707 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1708 {
1709         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1710         struct i40e_vsi *vsi = pf->main_vsi;
1711
1712         if (mask & ETH_VLAN_STRIP_MASK) {
1713                 /* Enable or disable VLAN stripping */
1714                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1715                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1716                 else
1717                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1718         }
1719
1720         if (mask & ETH_VLAN_EXTEND_MASK) {
1721                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1722                         i40e_vsi_config_double_vlan(vsi, TRUE);
1723                 else
1724                         i40e_vsi_config_double_vlan(vsi, FALSE);
1725         }
1726 }
1727
1728 static void
1729 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1730                           __rte_unused uint16_t queue,
1731                           __rte_unused int on)
1732 {
1733         PMD_INIT_FUNC_TRACE();
1734 }
1735
1736 static int
1737 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1738 {
1739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1740         struct i40e_vsi *vsi = pf->main_vsi;
1741         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1742         struct i40e_vsi_vlan_pvid_info info;
1743
1744         memset(&info, 0, sizeof(info));
1745         info.on = on;
1746         if (info.on)
1747                 info.config.pvid = pvid;
1748         else {
1749                 info.config.reject.tagged =
1750                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1751                 info.config.reject.untagged =
1752                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1753         }
1754
1755         return i40e_vsi_vlan_pvid_set(vsi, &info);
1756 }
1757
1758 static int
1759 i40e_dev_led_on(struct rte_eth_dev *dev)
1760 {
1761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1762         uint32_t mode = i40e_led_get(hw);
1763
1764         if (mode == 0)
1765                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1766
1767         return 0;
1768 }
1769
1770 static int
1771 i40e_dev_led_off(struct rte_eth_dev *dev)
1772 {
1773         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1774         uint32_t mode = i40e_led_get(hw);
1775
1776         if (mode != 0)
1777                 i40e_led_set(hw, 0, false);
1778
1779         return 0;
1780 }
1781
1782 static int
1783 i40e_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1784                    __rte_unused struct rte_eth_fc_conf *fc_conf)
1785 {
1786         PMD_INIT_FUNC_TRACE();
1787
1788         return -ENOSYS;
1789 }
1790
1791 static int
1792 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1793                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1794 {
1795         PMD_INIT_FUNC_TRACE();
1796
1797         return -ENOSYS;
1798 }
1799
1800 /* Add a MAC address, and update filters */
1801 static void
1802 i40e_macaddr_add(struct rte_eth_dev *dev,
1803                  struct ether_addr *mac_addr,
1804                  __rte_unused uint32_t index,
1805                  uint32_t pool)
1806 {
1807         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1808         struct i40e_mac_filter_info mac_filter;
1809         struct i40e_vsi *vsi;
1810         int ret;
1811
1812         /* If VMDQ not enabled or configured, return */
1813         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
1814                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
1815                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
1816                         pool);
1817                 return;
1818         }
1819
1820         if (pool > pf->nb_cfg_vmdq_vsi) {
1821                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
1822                                 pool, pf->nb_cfg_vmdq_vsi);
1823                 return;
1824         }
1825
1826         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
1827         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
1828
1829         if (pool == 0)
1830                 vsi = pf->main_vsi;
1831         else
1832                 vsi = pf->vmdq[pool - 1].vsi;
1833
1834         ret = i40e_vsi_add_mac(vsi, &mac_filter);
1835         if (ret != I40E_SUCCESS) {
1836                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
1837                 return;
1838         }
1839 }
1840
1841 /* Remove a MAC address, and update filters */
1842 static void
1843 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
1844 {
1845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1846         struct i40e_vsi *vsi;
1847         struct rte_eth_dev_data *data = dev->data;
1848         struct ether_addr *macaddr;
1849         int ret;
1850         uint32_t i;
1851         uint64_t pool_sel;
1852
1853         macaddr = &(data->mac_addrs[index]);
1854
1855         pool_sel = dev->data->mac_pool_sel[index];
1856
1857         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
1858                 if (pool_sel & (1ULL << i)) {
1859                         if (i == 0)
1860                                 vsi = pf->main_vsi;
1861                         else {
1862                                 /* No VMDQ pool enabled or configured */
1863                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
1864                                         (i > pf->nb_cfg_vmdq_vsi)) {
1865                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
1866                                                         "/configured");
1867                                         return;
1868                                 }
1869                                 vsi = pf->vmdq[i - 1].vsi;
1870                         }
1871                         ret = i40e_vsi_delete_mac(vsi, macaddr);
1872
1873                         if (ret) {
1874                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
1875                                 return;
1876                         }
1877                 }
1878         }
1879 }
1880
1881 /* Set perfect match or hash match of MAC and VLAN for a VF */
1882 static int
1883 i40e_vf_mac_filter_set(struct i40e_pf *pf,
1884                  struct rte_eth_mac_filter *filter,
1885                  bool add)
1886 {
1887         struct i40e_hw *hw;
1888         struct i40e_mac_filter_info mac_filter;
1889         struct ether_addr old_mac;
1890         struct ether_addr *new_mac;
1891         struct i40e_pf_vf *vf = NULL;
1892         uint16_t vf_id;
1893         int ret;
1894
1895         if (pf == NULL) {
1896                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
1897                 return -EINVAL;
1898         }
1899         hw = I40E_PF_TO_HW(pf);
1900
1901         if (filter == NULL) {
1902                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
1903                 return -EINVAL;
1904         }
1905
1906         new_mac = &filter->mac_addr;
1907
1908         if (is_zero_ether_addr(new_mac)) {
1909                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
1910                 return -EINVAL;
1911         }
1912
1913         vf_id = filter->dst_id;
1914
1915         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
1916                 PMD_DRV_LOG(ERR, "Invalid argument.");
1917                 return -EINVAL;
1918         }
1919         vf = &pf->vfs[vf_id];
1920
1921         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
1922                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
1923                 return -EINVAL;
1924         }
1925
1926         if (add) {
1927                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
1928                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
1929                                 ETHER_ADDR_LEN);
1930                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
1931                                  ETHER_ADDR_LEN);
1932
1933                 mac_filter.filter_type = filter->filter_type;
1934                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
1935                 if (ret != I40E_SUCCESS) {
1936                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
1937                         return -1;
1938                 }
1939                 ether_addr_copy(new_mac, &pf->dev_addr);
1940         } else {
1941                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
1942                                 ETHER_ADDR_LEN);
1943                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
1944                 if (ret != I40E_SUCCESS) {
1945                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
1946                         return -1;
1947                 }
1948
1949                 /* Clear device address as it has been removed */
1950                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
1951                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
1952         }
1953
1954         return 0;
1955 }
1956
1957 /* MAC filter handle */
1958 static int
1959 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
1960                 void *arg)
1961 {
1962         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1963         struct rte_eth_mac_filter *filter;
1964         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1965         int ret = I40E_NOT_SUPPORTED;
1966
1967         filter = (struct rte_eth_mac_filter *)(arg);
1968
1969         switch (filter_op) {
1970         case RTE_ETH_FILTER_NOP:
1971                 ret = I40E_SUCCESS;
1972                 break;
1973         case RTE_ETH_FILTER_ADD:
1974                 i40e_pf_disable_irq0(hw);
1975                 if (filter->is_vf)
1976                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
1977                 i40e_pf_enable_irq0(hw);
1978                 break;
1979         case RTE_ETH_FILTER_DELETE:
1980                 i40e_pf_disable_irq0(hw);
1981                 if (filter->is_vf)
1982                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
1983                 i40e_pf_enable_irq0(hw);
1984                 break;
1985         default:
1986                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1987                 ret = I40E_ERR_PARAM;
1988                 break;
1989         }
1990
1991         return ret;
1992 }
1993
1994 static int
1995 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
1996                          struct rte_eth_rss_reta_entry64 *reta_conf,
1997                          uint16_t reta_size)
1998 {
1999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2001         uint32_t lut, l;
2002         uint16_t i, j, lut_size = pf->hash_lut_size;
2003         uint16_t idx, shift;
2004         uint8_t mask;
2005
2006         if (reta_size != lut_size ||
2007                 reta_size > ETH_RSS_RETA_SIZE_512) {
2008                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2009                         "(%d) doesn't match the number hardware can supported "
2010                                         "(%d)\n", reta_size, lut_size);
2011                 return -EINVAL;
2012         }
2013
2014         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2015                 idx = i / RTE_RETA_GROUP_SIZE;
2016                 shift = i % RTE_RETA_GROUP_SIZE;
2017                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2018                                                 I40E_4_BIT_MASK);
2019                 if (!mask)
2020                         continue;
2021                 if (mask == I40E_4_BIT_MASK)
2022                         l = 0;
2023                 else
2024                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2025                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2026                         if (mask & (0x1 << j))
2027                                 lut |= reta_conf[idx].reta[shift + j] <<
2028                                                         (CHAR_BIT * j);
2029                         else
2030                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2031                 }
2032                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2033         }
2034
2035         return 0;
2036 }
2037
2038 static int
2039 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2040                         struct rte_eth_rss_reta_entry64 *reta_conf,
2041                         uint16_t reta_size)
2042 {
2043         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045         uint32_t lut;
2046         uint16_t i, j, lut_size = pf->hash_lut_size;
2047         uint16_t idx, shift;
2048         uint8_t mask;
2049
2050         if (reta_size != lut_size ||
2051                 reta_size > ETH_RSS_RETA_SIZE_512) {
2052                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2053                         "(%d) doesn't match the number hardware can supported "
2054                                         "(%d)\n", reta_size, lut_size);
2055                 return -EINVAL;
2056         }
2057
2058         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2059                 idx = i / RTE_RETA_GROUP_SIZE;
2060                 shift = i % RTE_RETA_GROUP_SIZE;
2061                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2062                                                 I40E_4_BIT_MASK);
2063                 if (!mask)
2064                         continue;
2065
2066                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2067                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2068                         if (mask & (0x1 << j))
2069                                 reta_conf[idx].reta[shift + j] = ((lut >>
2070                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2071                 }
2072         }
2073
2074         return 0;
2075 }
2076
2077 /**
2078  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2079  * @hw:   pointer to the HW structure
2080  * @mem:  pointer to mem struct to fill out
2081  * @size: size of memory requested
2082  * @alignment: what to align the allocation to
2083  **/
2084 enum i40e_status_code
2085 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2086                         struct i40e_dma_mem *mem,
2087                         u64 size,
2088                         u32 alignment)
2089 {
2090         static uint64_t id = 0;
2091         const struct rte_memzone *mz = NULL;
2092         char z_name[RTE_MEMZONE_NAMESIZE];
2093
2094         if (!mem)
2095                 return I40E_ERR_PARAM;
2096
2097         id++;
2098         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2099 #ifdef RTE_LIBRTE_XEN_DOM0
2100         mz = rte_memzone_reserve_bounded(z_name, size, 0, 0, alignment,
2101                                                         RTE_PGSIZE_2M);
2102 #else
2103         mz = rte_memzone_reserve_aligned(z_name, size, 0, 0, alignment);
2104 #endif
2105         if (!mz)
2106                 return I40E_ERR_NO_MEMORY;
2107
2108         mem->id = id;
2109         mem->size = size;
2110         mem->va = mz->addr;
2111 #ifdef RTE_LIBRTE_XEN_DOM0
2112         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2113 #else
2114         mem->pa = mz->phys_addr;
2115 #endif
2116
2117         return I40E_SUCCESS;
2118 }
2119
2120 /**
2121  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2122  * @hw:   pointer to the HW structure
2123  * @mem:  ptr to mem struct to free
2124  **/
2125 enum i40e_status_code
2126 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2127                     struct i40e_dma_mem *mem)
2128 {
2129         if (!mem || !mem->va)
2130                 return I40E_ERR_PARAM;
2131
2132         mem->va = NULL;
2133         mem->pa = (u64)0;
2134
2135         return I40E_SUCCESS;
2136 }
2137
2138 /**
2139  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2140  * @hw:   pointer to the HW structure
2141  * @mem:  pointer to mem struct to fill out
2142  * @size: size of memory requested
2143  **/
2144 enum i40e_status_code
2145 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2146                          struct i40e_virt_mem *mem,
2147                          u32 size)
2148 {
2149         if (!mem)
2150                 return I40E_ERR_PARAM;
2151
2152         mem->size = size;
2153         mem->va = rte_zmalloc("i40e", size, 0);
2154
2155         if (mem->va)
2156                 return I40E_SUCCESS;
2157         else
2158                 return I40E_ERR_NO_MEMORY;
2159 }
2160
2161 /**
2162  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2163  * @hw:   pointer to the HW structure
2164  * @mem:  pointer to mem struct to free
2165  **/
2166 enum i40e_status_code
2167 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2168                      struct i40e_virt_mem *mem)
2169 {
2170         if (!mem)
2171                 return I40E_ERR_PARAM;
2172
2173         rte_free(mem->va);
2174         mem->va = NULL;
2175
2176         return I40E_SUCCESS;
2177 }
2178
2179 void
2180 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2181 {
2182         rte_spinlock_init(&sp->spinlock);
2183 }
2184
2185 void
2186 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2187 {
2188         rte_spinlock_lock(&sp->spinlock);
2189 }
2190
2191 void
2192 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2193 {
2194         rte_spinlock_unlock(&sp->spinlock);
2195 }
2196
2197 void
2198 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2199 {
2200         return;
2201 }
2202
2203 /**
2204  * Get the hardware capabilities, which will be parsed
2205  * and saved into struct i40e_hw.
2206  */
2207 static int
2208 i40e_get_cap(struct i40e_hw *hw)
2209 {
2210         struct i40e_aqc_list_capabilities_element_resp *buf;
2211         uint16_t len, size = 0;
2212         int ret;
2213
2214         /* Calculate a huge enough buff for saving response data temporarily */
2215         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2216                                                 I40E_MAX_CAP_ELE_NUM;
2217         buf = rte_zmalloc("i40e", len, 0);
2218         if (!buf) {
2219                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2220                 return I40E_ERR_NO_MEMORY;
2221         }
2222
2223         /* Get, parse the capabilities and save it to hw */
2224         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2225                         i40e_aqc_opc_list_func_capabilities, NULL);
2226         if (ret != I40E_SUCCESS)
2227                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2228
2229         /* Free the temporary buffer after being used */
2230         rte_free(buf);
2231
2232         return ret;
2233 }
2234
2235 static int
2236 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2240         uint16_t sum_queues = 0, sum_vsis, left_queues;
2241
2242         /* First check if FW support SRIOV */
2243         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2244                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2245                 return -EINVAL;
2246         }
2247
2248         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2249         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2250         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2251         /* Allocate queues for pf */
2252         if (hw->func_caps.rss) {
2253                 pf->flags |= I40E_FLAG_RSS;
2254                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2255                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2256                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2257         } else
2258                 pf->lan_nb_qps = 1;
2259         sum_queues = pf->lan_nb_qps;
2260         /* Default VSI is not counted in */
2261         sum_vsis = 0;
2262         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2263
2264         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2265                 pf->flags |= I40E_FLAG_SRIOV;
2266                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2267                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2268                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2269                                      "max supported %u.",
2270                                      dev->pci_dev->max_vfs,
2271                                      hw->func_caps.num_vfs);
2272                         return -EINVAL;
2273                 }
2274                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2275                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2276                                      "max support %u queues.",
2277                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2278                         return -EINVAL;
2279                 }
2280                 pf->vf_num = dev->pci_dev->max_vfs;
2281                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2282                 sum_vsis   += pf->vf_num;
2283                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2284                              pf->vf_num, pf->vf_nb_qps);
2285         } else
2286                 pf->vf_num = 0;
2287
2288         if (hw->func_caps.vmdq) {
2289                 pf->flags |= I40E_FLAG_VMDQ;
2290                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2291                 pf->max_nb_vmdq_vsi = 1;
2292                 /*
2293                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2294                  * later.
2295                  */
2296                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2297                 sum_vsis += pf->max_nb_vmdq_vsi;
2298         } else {
2299                 pf->vmdq_nb_qps = 0;
2300                 pf->max_nb_vmdq_vsi = 0;
2301         }
2302         pf->nb_cfg_vmdq_vsi = 0;
2303
2304         if (hw->func_caps.fd) {
2305                 pf->flags |= I40E_FLAG_FDIR;
2306                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2307                 /**
2308                  * Each flow director consumes one VSI and one queue,
2309                  * but can't calculate out predictably here.
2310                  */
2311         }
2312
2313         if (sum_vsis > pf->max_num_vsi ||
2314                 sum_queues > hw->func_caps.num_rx_qp) {
2315                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2316                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2317                              pf->max_num_vsi, sum_vsis);
2318                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2319                              hw->func_caps.num_rx_qp, sum_queues);
2320                 return -EINVAL;
2321         }
2322
2323         /* Adjust VMDQ setting to support as many VMs as possible */
2324         if (pf->flags & I40E_FLAG_VMDQ) {
2325                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2326
2327                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2328                                         pf->max_num_vsi - sum_vsis);
2329
2330                 /* Limit the max VMDQ number that rte_ether that can support  */
2331                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2332                                         ETH_64_POOLS - 1);
2333
2334                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2335                                 pf->max_nb_vmdq_vsi);
2336                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2337         }
2338
2339         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2340          * cause */
2341         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2342                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2343                              sum_vsis, hw->func_caps.num_msix_vectors);
2344                 return -EINVAL;
2345         }
2346         return I40E_SUCCESS;
2347 }
2348
2349 static int
2350 i40e_pf_get_switch_config(struct i40e_pf *pf)
2351 {
2352         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2353         struct i40e_aqc_get_switch_config_resp *switch_config;
2354         struct i40e_aqc_switch_config_element_resp *element;
2355         uint16_t start_seid = 0, num_reported;
2356         int ret;
2357
2358         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2359                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2360         if (!switch_config) {
2361                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2362                 return -ENOMEM;
2363         }
2364
2365         /* Get the switch configurations */
2366         ret = i40e_aq_get_switch_config(hw, switch_config,
2367                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2368         if (ret != I40E_SUCCESS) {
2369                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2370                 goto fail;
2371         }
2372         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2373         if (num_reported != 1) { /* The number should be 1 */
2374                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2375                 goto fail;
2376         }
2377
2378         /* Parse the switch configuration elements */
2379         element = &(switch_config->element[0]);
2380         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2381                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2382                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2383         } else
2384                 PMD_DRV_LOG(INFO, "Unknown element type");
2385
2386 fail:
2387         rte_free(switch_config);
2388
2389         return ret;
2390 }
2391
2392 static int
2393 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2394                         uint32_t num)
2395 {
2396         struct pool_entry *entry;
2397
2398         if (pool == NULL || num == 0)
2399                 return -EINVAL;
2400
2401         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2402         if (entry == NULL) {
2403                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2404                 return -ENOMEM;
2405         }
2406
2407         /* queue heap initialize */
2408         pool->num_free = num;
2409         pool->num_alloc = 0;
2410         pool->base = base;
2411         LIST_INIT(&pool->alloc_list);
2412         LIST_INIT(&pool->free_list);
2413
2414         /* Initialize element  */
2415         entry->base = 0;
2416         entry->len = num;
2417
2418         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2419         return 0;
2420 }
2421
2422 static void
2423 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2424 {
2425         struct pool_entry *entry;
2426
2427         if (pool == NULL)
2428                 return;
2429
2430         LIST_FOREACH(entry, &pool->alloc_list, next) {
2431                 LIST_REMOVE(entry, next);
2432                 rte_free(entry);
2433         }
2434
2435         LIST_FOREACH(entry, &pool->free_list, next) {
2436                 LIST_REMOVE(entry, next);
2437                 rte_free(entry);
2438         }
2439
2440         pool->num_free = 0;
2441         pool->num_alloc = 0;
2442         pool->base = 0;
2443         LIST_INIT(&pool->alloc_list);
2444         LIST_INIT(&pool->free_list);
2445 }
2446
2447 static int
2448 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2449                        uint32_t base)
2450 {
2451         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2452         uint32_t pool_offset;
2453         int insert;
2454
2455         if (pool == NULL) {
2456                 PMD_DRV_LOG(ERR, "Invalid parameter");
2457                 return -EINVAL;
2458         }
2459
2460         pool_offset = base - pool->base;
2461         /* Lookup in alloc list */
2462         LIST_FOREACH(entry, &pool->alloc_list, next) {
2463                 if (entry->base == pool_offset) {
2464                         valid_entry = entry;
2465                         LIST_REMOVE(entry, next);
2466                         break;
2467                 }
2468         }
2469
2470         /* Not find, return */
2471         if (valid_entry == NULL) {
2472                 PMD_DRV_LOG(ERR, "Failed to find entry");
2473                 return -EINVAL;
2474         }
2475
2476         /**
2477          * Found it, move it to free list  and try to merge.
2478          * In order to make merge easier, always sort it by qbase.
2479          * Find adjacent prev and last entries.
2480          */
2481         prev = next = NULL;
2482         LIST_FOREACH(entry, &pool->free_list, next) {
2483                 if (entry->base > valid_entry->base) {
2484                         next = entry;
2485                         break;
2486                 }
2487                 prev = entry;
2488         }
2489
2490         insert = 0;
2491         /* Try to merge with next one*/
2492         if (next != NULL) {
2493                 /* Merge with next one */
2494                 if (valid_entry->base + valid_entry->len == next->base) {
2495                         next->base = valid_entry->base;
2496                         next->len += valid_entry->len;
2497                         rte_free(valid_entry);
2498                         valid_entry = next;
2499                         insert = 1;
2500                 }
2501         }
2502
2503         if (prev != NULL) {
2504                 /* Merge with previous one */
2505                 if (prev->base + prev->len == valid_entry->base) {
2506                         prev->len += valid_entry->len;
2507                         /* If it merge with next one, remove next node */
2508                         if (insert == 1) {
2509                                 LIST_REMOVE(valid_entry, next);
2510                                 rte_free(valid_entry);
2511                         } else {
2512                                 rte_free(valid_entry);
2513                                 insert = 1;
2514                         }
2515                 }
2516         }
2517
2518         /* Not find any entry to merge, insert */
2519         if (insert == 0) {
2520                 if (prev != NULL)
2521                         LIST_INSERT_AFTER(prev, valid_entry, next);
2522                 else if (next != NULL)
2523                         LIST_INSERT_BEFORE(next, valid_entry, next);
2524                 else /* It's empty list, insert to head */
2525                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2526         }
2527
2528         pool->num_free += valid_entry->len;
2529         pool->num_alloc -= valid_entry->len;
2530
2531         return 0;
2532 }
2533
2534 static int
2535 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2536                        uint16_t num)
2537 {
2538         struct pool_entry *entry, *valid_entry;
2539
2540         if (pool == NULL || num == 0) {
2541                 PMD_DRV_LOG(ERR, "Invalid parameter");
2542                 return -EINVAL;
2543         }
2544
2545         if (pool->num_free < num) {
2546                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2547                             num, pool->num_free);
2548                 return -ENOMEM;
2549         }
2550
2551         valid_entry = NULL;
2552         /* Lookup  in free list and find most fit one */
2553         LIST_FOREACH(entry, &pool->free_list, next) {
2554                 if (entry->len >= num) {
2555                         /* Find best one */
2556                         if (entry->len == num) {
2557                                 valid_entry = entry;
2558                                 break;
2559                         }
2560                         if (valid_entry == NULL || valid_entry->len > entry->len)
2561                                 valid_entry = entry;
2562                 }
2563         }
2564
2565         /* Not find one to satisfy the request, return */
2566         if (valid_entry == NULL) {
2567                 PMD_DRV_LOG(ERR, "No valid entry found");
2568                 return -ENOMEM;
2569         }
2570         /**
2571          * The entry have equal queue number as requested,
2572          * remove it from alloc_list.
2573          */
2574         if (valid_entry->len == num) {
2575                 LIST_REMOVE(valid_entry, next);
2576         } else {
2577                 /**
2578                  * The entry have more numbers than requested,
2579                  * create a new entry for alloc_list and minus its
2580                  * queue base and number in free_list.
2581                  */
2582                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2583                 if (entry == NULL) {
2584                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2585                                     "resource pool");
2586                         return -ENOMEM;
2587                 }
2588                 entry->base = valid_entry->base;
2589                 entry->len = num;
2590                 valid_entry->base += num;
2591                 valid_entry->len -= num;
2592                 valid_entry = entry;
2593         }
2594
2595         /* Insert it into alloc list, not sorted */
2596         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2597
2598         pool->num_free -= valid_entry->len;
2599         pool->num_alloc += valid_entry->len;
2600
2601         return (valid_entry->base + pool->base);
2602 }
2603
2604 /**
2605  * bitmap_is_subset - Check whether src2 is subset of src1
2606  **/
2607 static inline int
2608 bitmap_is_subset(uint8_t src1, uint8_t src2)
2609 {
2610         return !((src1 ^ src2) & src2);
2611 }
2612
2613 static int
2614 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2615 {
2616         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2617
2618         /* If DCB is not supported, only default TC is supported */
2619         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2620                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2621                 return -EINVAL;
2622         }
2623
2624         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2625                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2626                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2627                             enabled_tcmap);
2628                 return -EINVAL;
2629         }
2630         return I40E_SUCCESS;
2631 }
2632
2633 int
2634 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2635                                 struct i40e_vsi_vlan_pvid_info *info)
2636 {
2637         struct i40e_hw *hw;
2638         struct i40e_vsi_context ctxt;
2639         uint8_t vlan_flags = 0;
2640         int ret;
2641
2642         if (vsi == NULL || info == NULL) {
2643                 PMD_DRV_LOG(ERR, "invalid parameters");
2644                 return I40E_ERR_PARAM;
2645         }
2646
2647         if (info->on) {
2648                 vsi->info.pvid = info->config.pvid;
2649                 /**
2650                  * If insert pvid is enabled, only tagged pkts are
2651                  * allowed to be sent out.
2652                  */
2653                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2654                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2655         } else {
2656                 vsi->info.pvid = 0;
2657                 if (info->config.reject.tagged == 0)
2658                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2659
2660                 if (info->config.reject.untagged == 0)
2661                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2662         }
2663         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2664                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2665         vsi->info.port_vlan_flags |= vlan_flags;
2666         vsi->info.valid_sections =
2667                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2668         memset(&ctxt, 0, sizeof(ctxt));
2669         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2670         ctxt.seid = vsi->seid;
2671
2672         hw = I40E_VSI_TO_HW(vsi);
2673         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2674         if (ret != I40E_SUCCESS)
2675                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2676
2677         return ret;
2678 }
2679
2680 static int
2681 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2682 {
2683         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2684         int i, ret;
2685         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2686
2687         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2688         if (ret != I40E_SUCCESS)
2689                 return ret;
2690
2691         if (!vsi->seid) {
2692                 PMD_DRV_LOG(ERR, "seid not valid");
2693                 return -EINVAL;
2694         }
2695
2696         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2697         tc_bw_data.tc_valid_bits = enabled_tcmap;
2698         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2699                 tc_bw_data.tc_bw_credits[i] =
2700                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2701
2702         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2703         if (ret != I40E_SUCCESS) {
2704                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2705                 return ret;
2706         }
2707
2708         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2709                                         sizeof(vsi->info.qs_handle));
2710         return I40E_SUCCESS;
2711 }
2712
2713 static int
2714 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2715                                  struct i40e_aqc_vsi_properties_data *info,
2716                                  uint8_t enabled_tcmap)
2717 {
2718         int ret, total_tc = 0, i;
2719         uint16_t qpnum_per_tc, bsf, qp_idx;
2720
2721         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2722         if (ret != I40E_SUCCESS)
2723                 return ret;
2724
2725         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2726                 if (enabled_tcmap & (1 << i))
2727                         total_tc++;
2728         vsi->enabled_tc = enabled_tcmap;
2729
2730         /* Number of queues per enabled TC */
2731         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2732         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2733         bsf = rte_bsf32(qpnum_per_tc);
2734
2735         /* Adjust the queue number to actual queues that can be applied */
2736         vsi->nb_qps = qpnum_per_tc * total_tc;
2737
2738         /**
2739          * Configure TC and queue mapping parameters, for enabled TC,
2740          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2741          * default queue will serve it.
2742          */
2743         qp_idx = 0;
2744         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2745                 if (vsi->enabled_tc & (1 << i)) {
2746                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2747                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2748                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2749                         qp_idx += qpnum_per_tc;
2750                 } else
2751                         info->tc_mapping[i] = 0;
2752         }
2753
2754         /* Associate queue number with VSI */
2755         if (vsi->type == I40E_VSI_SRIOV) {
2756                 info->mapping_flags |=
2757                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2758                 for (i = 0; i < vsi->nb_qps; i++)
2759                         info->queue_mapping[i] =
2760                                 rte_cpu_to_le_16(vsi->base_queue + i);
2761         } else {
2762                 info->mapping_flags |=
2763                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2764                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2765         }
2766         info->valid_sections |=
2767                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2768
2769         return I40E_SUCCESS;
2770 }
2771
2772 static int
2773 i40e_veb_release(struct i40e_veb *veb)
2774 {
2775         struct i40e_vsi *vsi;
2776         struct i40e_hw *hw;
2777
2778         if (veb == NULL || veb->associate_vsi == NULL)
2779                 return -EINVAL;
2780
2781         if (!TAILQ_EMPTY(&veb->head)) {
2782                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2783                 return -EACCES;
2784         }
2785
2786         vsi = veb->associate_vsi;
2787         hw = I40E_VSI_TO_HW(vsi);
2788
2789         vsi->uplink_seid = veb->uplink_seid;
2790         i40e_aq_delete_element(hw, veb->seid, NULL);
2791         rte_free(veb);
2792         vsi->veb = NULL;
2793         return I40E_SUCCESS;
2794 }
2795
2796 /* Setup a veb */
2797 static struct i40e_veb *
2798 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2799 {
2800         struct i40e_veb *veb;
2801         int ret;
2802         struct i40e_hw *hw;
2803
2804         if (NULL == pf || vsi == NULL) {
2805                 PMD_DRV_LOG(ERR, "veb setup failed, "
2806                             "associated VSI shouldn't null");
2807                 return NULL;
2808         }
2809         hw = I40E_PF_TO_HW(pf);
2810
2811         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
2812         if (!veb) {
2813                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
2814                 goto fail;
2815         }
2816
2817         veb->associate_vsi = vsi;
2818         TAILQ_INIT(&veb->head);
2819         veb->uplink_seid = vsi->uplink_seid;
2820
2821         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
2822                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
2823
2824         if (ret != I40E_SUCCESS) {
2825                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
2826                             hw->aq.asq_last_status);
2827                 goto fail;
2828         }
2829
2830         /* get statistics index */
2831         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
2832                                 &veb->stats_idx, NULL, NULL, NULL);
2833         if (ret != I40E_SUCCESS) {
2834                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
2835                             hw->aq.asq_last_status);
2836                 goto fail;
2837         }
2838
2839         /* Get VEB bandwidth, to be implemented */
2840         /* Now associated vsi binding to the VEB, set uplink to this VEB */
2841         vsi->uplink_seid = veb->seid;
2842
2843         return veb;
2844 fail:
2845         rte_free(veb);
2846         return NULL;
2847 }
2848
2849 int
2850 i40e_vsi_release(struct i40e_vsi *vsi)
2851 {
2852         struct i40e_pf *pf;
2853         struct i40e_hw *hw;
2854         struct i40e_vsi_list *vsi_list;
2855         int ret;
2856         struct i40e_mac_filter *f;
2857
2858         if (!vsi)
2859                 return I40E_SUCCESS;
2860
2861         pf = I40E_VSI_TO_PF(vsi);
2862         hw = I40E_VSI_TO_HW(vsi);
2863
2864         /* VSI has child to attach, release child first */
2865         if (vsi->veb) {
2866                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
2867                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
2868                                 return -1;
2869                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
2870                 }
2871                 i40e_veb_release(vsi->veb);
2872         }
2873
2874         /* Remove all macvlan filters of the VSI */
2875         i40e_vsi_remove_all_macvlan_filter(vsi);
2876         TAILQ_FOREACH(f, &vsi->mac_list, next)
2877                 rte_free(f);
2878
2879         if (vsi->type != I40E_VSI_MAIN) {
2880                 /* Remove vsi from parent's sibling list */
2881                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
2882                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
2883                         return I40E_ERR_PARAM;
2884                 }
2885                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
2886                                 &vsi->sib_vsi_list, list);
2887
2888                 /* Remove all switch element of the VSI */
2889                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
2890                 if (ret != I40E_SUCCESS)
2891                         PMD_DRV_LOG(ERR, "Failed to delete element");
2892         }
2893         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
2894
2895         if (vsi->type != I40E_VSI_SRIOV)
2896                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
2897         rte_free(vsi);
2898
2899         return I40E_SUCCESS;
2900 }
2901
2902 static int
2903 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
2904 {
2905         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2906         struct i40e_aqc_remove_macvlan_element_data def_filter;
2907         struct i40e_mac_filter_info filter;
2908         int ret;
2909
2910         if (vsi->type != I40E_VSI_MAIN)
2911                 return I40E_ERR_CONFIG;
2912         memset(&def_filter, 0, sizeof(def_filter));
2913         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
2914                                         ETH_ADDR_LEN);
2915         def_filter.vlan_tag = 0;
2916         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
2917                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2918         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
2919         if (ret != I40E_SUCCESS) {
2920                 struct i40e_mac_filter *f;
2921                 struct ether_addr *mac;
2922
2923                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
2924                             "macvlan filter");
2925                 /* It needs to add the permanent mac into mac list */
2926                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
2927                 if (f == NULL) {
2928                         PMD_DRV_LOG(ERR, "failed to allocate memory");
2929                         return I40E_ERR_NO_MEMORY;
2930                 }
2931                 mac = &f->mac_info.mac_addr;
2932                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
2933                                 ETH_ADDR_LEN);
2934                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2935                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
2936                 vsi->mac_num++;
2937
2938                 return ret;
2939         }
2940         (void)rte_memcpy(&filter.mac_addr,
2941                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
2942         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2943         return i40e_vsi_add_mac(vsi, &filter);
2944 }
2945
2946 static int
2947 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
2948 {
2949         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
2950         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
2951         struct i40e_hw *hw = &vsi->adapter->hw;
2952         i40e_status ret;
2953         int i;
2954
2955         memset(&bw_config, 0, sizeof(bw_config));
2956         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
2957         if (ret != I40E_SUCCESS) {
2958                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
2959                             hw->aq.asq_last_status);
2960                 return ret;
2961         }
2962
2963         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
2964         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
2965                                         &ets_sla_config, NULL);
2966         if (ret != I40E_SUCCESS) {
2967                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
2968                             "configuration %u", hw->aq.asq_last_status);
2969                 return ret;
2970         }
2971
2972         /* Not store the info yet, just print out */
2973         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
2974         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
2975         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2976                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
2977                             ets_sla_config.share_credits[i]);
2978                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
2979                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
2980                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
2981                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
2982                             (i * 4));
2983         }
2984
2985         return 0;
2986 }
2987
2988 /* Setup a VSI */
2989 struct i40e_vsi *
2990 i40e_vsi_setup(struct i40e_pf *pf,
2991                enum i40e_vsi_type type,
2992                struct i40e_vsi *uplink_vsi,
2993                uint16_t user_param)
2994 {
2995         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2996         struct i40e_vsi *vsi;
2997         struct i40e_mac_filter_info filter;
2998         int ret;
2999         struct i40e_vsi_context ctxt;
3000         struct ether_addr broadcast =
3001                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3002
3003         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3004                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3005                             "VSI link shouldn't be NULL");
3006                 return NULL;
3007         }
3008
3009         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3010                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3011                             "uplink VSI should be NULL");
3012                 return NULL;
3013         }
3014
3015         /* If uplink vsi didn't setup VEB, create one first */
3016         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3017                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3018
3019                 if (NULL == uplink_vsi->veb) {
3020                         PMD_DRV_LOG(ERR, "VEB setup failed");
3021                         return NULL;
3022                 }
3023         }
3024
3025         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3026         if (!vsi) {
3027                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3028                 return NULL;
3029         }
3030         TAILQ_INIT(&vsi->mac_list);
3031         vsi->type = type;
3032         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3033         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3034         vsi->parent_vsi = uplink_vsi;
3035         vsi->user_param = user_param;
3036         /* Allocate queues */
3037         switch (vsi->type) {
3038         case I40E_VSI_MAIN  :
3039                 vsi->nb_qps = pf->lan_nb_qps;
3040                 break;
3041         case I40E_VSI_SRIOV :
3042                 vsi->nb_qps = pf->vf_nb_qps;
3043                 break;
3044         case I40E_VSI_VMDQ2:
3045                 vsi->nb_qps = pf->vmdq_nb_qps;
3046                 break;
3047         case I40E_VSI_FDIR:
3048                 vsi->nb_qps = pf->fdir_nb_qps;
3049                 break;
3050         default:
3051                 goto fail_mem;
3052         }
3053         /*
3054          * The filter status descriptor is reported in rx queue 0,
3055          * while the tx queue for fdir filter programming has no
3056          * such constraints, can be non-zero queues.
3057          * To simplify it, choose FDIR vsi use queue 0 pair.
3058          * To make sure it will use queue 0 pair, queue allocation
3059          * need be done before this function is called
3060          */
3061         if (type != I40E_VSI_FDIR) {
3062                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3063                         if (ret < 0) {
3064                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3065                                                 vsi->seid, ret);
3066                                 goto fail_mem;
3067                         }
3068                         vsi->base_queue = ret;
3069         } else
3070                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3071
3072         /* VF has MSIX interrupt in VF range, don't allocate here */
3073         if (type != I40E_VSI_SRIOV) {
3074                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3075                 if (ret < 0) {
3076                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3077                         goto fail_queue_alloc;
3078                 }
3079                 vsi->msix_intr = ret;
3080         } else
3081                 vsi->msix_intr = 0;
3082         /* Add VSI */
3083         if (type == I40E_VSI_MAIN) {
3084                 /* For main VSI, no need to add since it's default one */
3085                 vsi->uplink_seid = pf->mac_seid;
3086                 vsi->seid = pf->main_vsi_seid;
3087                 /* Bind queues with specific MSIX interrupt */
3088                 /**
3089                  * Needs 2 interrupt at least, one for misc cause which will
3090                  * enabled from OS side, Another for queues binding the
3091                  * interrupt from device side only.
3092                  */
3093
3094                 /* Get default VSI parameters from hardware */
3095                 memset(&ctxt, 0, sizeof(ctxt));
3096                 ctxt.seid = vsi->seid;
3097                 ctxt.pf_num = hw->pf_id;
3098                 ctxt.uplink_seid = vsi->uplink_seid;
3099                 ctxt.vf_num = 0;
3100                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3101                 if (ret != I40E_SUCCESS) {
3102                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3103                         goto fail_msix_alloc;
3104                 }
3105                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3106                         sizeof(struct i40e_aqc_vsi_properties_data));
3107                 vsi->vsi_id = ctxt.vsi_number;
3108                 vsi->info.valid_sections = 0;
3109
3110                 /* Configure tc, enabled TC0 only */
3111                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3112                         I40E_SUCCESS) {
3113                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3114                         goto fail_msix_alloc;
3115                 }
3116
3117                 /* TC, queue mapping */
3118                 memset(&ctxt, 0, sizeof(ctxt));
3119                 vsi->info.valid_sections |=
3120                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3121                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3122                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3123                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3124                         sizeof(struct i40e_aqc_vsi_properties_data));
3125                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3126                                                 I40E_DEFAULT_TCMAP);
3127                 if (ret != I40E_SUCCESS) {
3128                         PMD_DRV_LOG(ERR, "Failed to configure "
3129                                     "TC queue mapping");
3130                         goto fail_msix_alloc;
3131                 }
3132                 ctxt.seid = vsi->seid;
3133                 ctxt.pf_num = hw->pf_id;
3134                 ctxt.uplink_seid = vsi->uplink_seid;
3135                 ctxt.vf_num = 0;
3136
3137                 /* Update VSI parameters */
3138                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3139                 if (ret != I40E_SUCCESS) {
3140                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3141                         goto fail_msix_alloc;
3142                 }
3143
3144                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3145                                                 sizeof(vsi->info.tc_mapping));
3146                 (void)rte_memcpy(&vsi->info.queue_mapping,
3147                                 &ctxt.info.queue_mapping,
3148                         sizeof(vsi->info.queue_mapping));
3149                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3150                 vsi->info.valid_sections = 0;
3151
3152                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3153                                 ETH_ADDR_LEN);
3154
3155                 /**
3156                  * Updating default filter settings are necessary to prevent
3157                  * reception of tagged packets.
3158                  * Some old firmware configurations load a default macvlan
3159                  * filter which accepts both tagged and untagged packets.
3160                  * The updating is to use a normal filter instead if needed.
3161                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3162                  * The firmware with correct configurations load the default
3163                  * macvlan filter which is expected and cannot be removed.
3164                  */
3165                 i40e_update_default_filter_setting(vsi);
3166                 i40e_config_qinq(hw, vsi);
3167         } else if (type == I40E_VSI_SRIOV) {
3168                 memset(&ctxt, 0, sizeof(ctxt));
3169                 /**
3170                  * For other VSI, the uplink_seid equals to uplink VSI's
3171                  * uplink_seid since they share same VEB
3172                  */
3173                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3174                 ctxt.pf_num = hw->pf_id;
3175                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3176                 ctxt.uplink_seid = vsi->uplink_seid;
3177                 ctxt.connection_type = 0x1;
3178                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3179
3180                 /**
3181                  * Do not configure switch ID to enable VEB switch by
3182                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3183                  * if the source mac address of packet sent from VF is not
3184                  * listed in the VEB's mac table, the VEB will switch the
3185                  * packet back to the VF. Need to enable it when HW issue
3186                  * is fixed.
3187                  */
3188
3189                 /* Configure port/vlan */
3190                 ctxt.info.valid_sections |=
3191                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3192                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3193                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3194                                                 I40E_DEFAULT_TCMAP);
3195                 if (ret != I40E_SUCCESS) {
3196                         PMD_DRV_LOG(ERR, "Failed to configure "
3197                                     "TC queue mapping");
3198                         goto fail_msix_alloc;
3199                 }
3200                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3201                 ctxt.info.valid_sections |=
3202                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3203                 /**
3204                  * Since VSI is not created yet, only configure parameter,
3205                  * will add vsi below.
3206                  */
3207
3208                 i40e_config_qinq(hw, vsi);
3209         } else if (type == I40E_VSI_VMDQ2) {
3210                 memset(&ctxt, 0, sizeof(ctxt));
3211                 /*
3212                  * For other VSI, the uplink_seid equals to uplink VSI's
3213                  * uplink_seid since they share same VEB
3214                  */
3215                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3216                 ctxt.pf_num = hw->pf_id;
3217                 ctxt.vf_num = 0;
3218                 ctxt.uplink_seid = vsi->uplink_seid;
3219                 ctxt.connection_type = 0x1;
3220                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3221
3222                 ctxt.info.valid_sections |=
3223                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3224                 /* user_param carries flag to enable loop back */
3225                 if (user_param) {
3226                         ctxt.info.switch_id =
3227                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3228                         ctxt.info.switch_id |=
3229                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3230                 }
3231
3232                 /* Configure port/vlan */
3233                 ctxt.info.valid_sections |=
3234                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3235                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3236                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3237                                                 I40E_DEFAULT_TCMAP);
3238                 if (ret != I40E_SUCCESS) {
3239                         PMD_DRV_LOG(ERR, "Failed to configure "
3240                                         "TC queue mapping");
3241                         goto fail_msix_alloc;
3242                 }
3243                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3244                 ctxt.info.valid_sections |=
3245                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3246         } else if (type == I40E_VSI_FDIR) {
3247                 memset(&ctxt, 0, sizeof(ctxt));
3248                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3249                 ctxt.pf_num = hw->pf_id;
3250                 ctxt.vf_num = 0;
3251                 ctxt.uplink_seid = vsi->uplink_seid;
3252                 ctxt.connection_type = 0x1;     /* regular data port */
3253                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3254                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3255                                                 I40E_DEFAULT_TCMAP);
3256                 if (ret != I40E_SUCCESS) {
3257                         PMD_DRV_LOG(ERR, "Failed to configure "
3258                                         "TC queue mapping.");
3259                         goto fail_msix_alloc;
3260                 }
3261                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3262                 ctxt.info.valid_sections |=
3263                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3264         } else {
3265                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3266                 goto fail_msix_alloc;
3267         }
3268
3269         if (vsi->type != I40E_VSI_MAIN) {
3270                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3271                 if (ret != I40E_SUCCESS) {
3272                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3273                                     hw->aq.asq_last_status);
3274                         goto fail_msix_alloc;
3275                 }
3276                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3277                 vsi->info.valid_sections = 0;
3278                 vsi->seid = ctxt.seid;
3279                 vsi->vsi_id = ctxt.vsi_number;
3280                 vsi->sib_vsi_list.vsi = vsi;
3281                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3282                                 &vsi->sib_vsi_list, list);
3283         }
3284
3285         /* MAC/VLAN configuration */
3286         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3287         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3288
3289         ret = i40e_vsi_add_mac(vsi, &filter);
3290         if (ret != I40E_SUCCESS) {
3291                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3292                 goto fail_msix_alloc;
3293         }
3294
3295         /* Get VSI BW information */
3296         i40e_vsi_dump_bw_config(vsi);
3297         return vsi;
3298 fail_msix_alloc:
3299         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3300 fail_queue_alloc:
3301         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3302 fail_mem:
3303         rte_free(vsi);
3304         return NULL;
3305 }
3306
3307 /* Configure vlan stripping on or off */
3308 int
3309 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3310 {
3311         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3312         struct i40e_vsi_context ctxt;
3313         uint8_t vlan_flags;
3314         int ret = I40E_SUCCESS;
3315
3316         /* Check if it has been already on or off */
3317         if (vsi->info.valid_sections &
3318                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3319                 if (on) {
3320                         if ((vsi->info.port_vlan_flags &
3321                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3322                                 return 0; /* already on */
3323                 } else {
3324                         if ((vsi->info.port_vlan_flags &
3325                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3326                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3327                                 return 0; /* already off */
3328                 }
3329         }
3330
3331         if (on)
3332                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3333         else
3334                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3335         vsi->info.valid_sections =
3336                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3337         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3338         vsi->info.port_vlan_flags |= vlan_flags;
3339         ctxt.seid = vsi->seid;
3340         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3341         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3342         if (ret)
3343                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3344                             on ? "enable" : "disable");
3345
3346         return ret;
3347 }
3348
3349 static int
3350 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3351 {
3352         struct rte_eth_dev_data *data = dev->data;
3353         int ret;
3354
3355         /* Apply vlan offload setting */
3356         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3357
3358         /* Apply double-vlan setting, not implemented yet */
3359
3360         /* Apply pvid setting */
3361         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3362                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3363         if (ret)
3364                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3365
3366         return ret;
3367 }
3368
3369 static int
3370 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3371 {
3372         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3373
3374         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3375 }
3376
3377 static int
3378 i40e_update_flow_control(struct i40e_hw *hw)
3379 {
3380 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3381         struct i40e_link_status link_status;
3382         uint32_t rxfc = 0, txfc = 0, reg;
3383         uint8_t an_info;
3384         int ret;
3385
3386         memset(&link_status, 0, sizeof(link_status));
3387         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3388         if (ret != I40E_SUCCESS) {
3389                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3390                 goto write_reg; /* Disable flow control */
3391         }
3392
3393         an_info = hw->phy.link_info.an_info;
3394         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3395                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3396                 ret = I40E_ERR_NOT_READY;
3397                 goto write_reg; /* Disable flow control */
3398         }
3399         /**
3400          * If link auto negotiation is enabled, flow control needs to
3401          * be configured according to it
3402          */
3403         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3404         case I40E_LINK_PAUSE_RXTX:
3405                 rxfc = 1;
3406                 txfc = 1;
3407                 hw->fc.current_mode = I40E_FC_FULL;
3408                 break;
3409         case I40E_AQ_LINK_PAUSE_RX:
3410                 rxfc = 1;
3411                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3412                 break;
3413         case I40E_AQ_LINK_PAUSE_TX:
3414                 txfc = 1;
3415                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3416                 break;
3417         default:
3418                 hw->fc.current_mode = I40E_FC_NONE;
3419                 break;
3420         }
3421
3422 write_reg:
3423         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3424                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3425         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3426         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3427         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3428         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3429
3430         return ret;
3431 }
3432
3433 /* PF setup */
3434 static int
3435 i40e_pf_setup(struct i40e_pf *pf)
3436 {
3437         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3438         struct i40e_filter_control_settings settings;
3439         struct i40e_vsi *vsi;
3440         int ret;
3441
3442         /* Clear all stats counters */
3443         pf->offset_loaded = FALSE;
3444         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3445         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3446
3447         ret = i40e_pf_get_switch_config(pf);
3448         if (ret != I40E_SUCCESS) {
3449                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3450                 return ret;
3451         }
3452         if (pf->flags & I40E_FLAG_FDIR) {
3453                 /* make queue allocated first, let FDIR use queue pair 0*/
3454                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3455                 if (ret != I40E_FDIR_QUEUE_ID) {
3456                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3457                                     " ret =%d", ret);
3458                         pf->flags &= ~I40E_FLAG_FDIR;
3459                 }
3460         }
3461         /*  main VSI setup */
3462         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3463         if (!vsi) {
3464                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3465                 return I40E_ERR_NOT_READY;
3466         }
3467         pf->main_vsi = vsi;
3468
3469         /* Configure filter control */
3470         memset(&settings, 0, sizeof(settings));
3471         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3472                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3473         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3474                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3475         else {
3476                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3477                                                 hw->func_caps.rss_table_size);
3478                 return I40E_ERR_PARAM;
3479         }
3480         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3481                         "size: %u\n", hw->func_caps.rss_table_size);
3482         pf->hash_lut_size = hw->func_caps.rss_table_size;
3483
3484         /* Enable ethtype and macvlan filters */
3485         settings.enable_ethtype = TRUE;
3486         settings.enable_macvlan = TRUE;
3487         ret = i40e_set_filter_control(hw, &settings);
3488         if (ret)
3489                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3490                                                                 ret);
3491
3492         /* Update flow control according to the auto negotiation */
3493         i40e_update_flow_control(hw);
3494
3495         return I40E_SUCCESS;
3496 }
3497
3498 int
3499 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3500 {
3501         uint32_t reg;
3502         uint16_t j;
3503
3504         /**
3505          * Set or clear TX Queue Disable flags,
3506          * which is required by hardware.
3507          */
3508         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3509         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3510
3511         /* Wait until the request is finished */
3512         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3513                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3514                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3515                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3516                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3517                                                         & 0x1))) {
3518                         break;
3519                 }
3520         }
3521         if (on) {
3522                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3523                         return I40E_SUCCESS; /* already on, skip next steps */
3524
3525                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3526                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3527         } else {
3528                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3529                         return I40E_SUCCESS; /* already off, skip next steps */
3530                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3531         }
3532         /* Write the register */
3533         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3534         /* Check the result */
3535         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3536                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3537                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3538                 if (on) {
3539                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3540                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3541                                 break;
3542                 } else {
3543                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3544                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3545                                 break;
3546                 }
3547         }
3548         /* Check if it is timeout */
3549         if (j >= I40E_CHK_Q_ENA_COUNT) {
3550                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3551                             (on ? "enable" : "disable"), q_idx);
3552                 return I40E_ERR_TIMEOUT;
3553         }
3554
3555         return I40E_SUCCESS;
3556 }
3557
3558 /* Swith on or off the tx queues */
3559 static int
3560 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3561 {
3562         struct rte_eth_dev_data *dev_data = pf->dev_data;
3563         struct i40e_tx_queue *txq;
3564         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3565         uint16_t i;
3566         int ret;
3567
3568         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3569                 txq = dev_data->tx_queues[i];
3570                 /* Don't operate the queue if not configured or
3571                  * if starting only per queue */
3572                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3573                         continue;
3574                 if (on)
3575                         ret = i40e_dev_tx_queue_start(dev, i);
3576                 else
3577                         ret = i40e_dev_tx_queue_stop(dev, i);
3578                 if ( ret != I40E_SUCCESS)
3579                         return ret;
3580         }
3581
3582         return I40E_SUCCESS;
3583 }
3584
3585 int
3586 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3587 {
3588         uint32_t reg;
3589         uint16_t j;
3590
3591         /* Wait until the request is finished */
3592         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3593                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3594                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3595                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3596                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3597                         break;
3598         }
3599
3600         if (on) {
3601                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3602                         return I40E_SUCCESS; /* Already on, skip next steps */
3603                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3604         } else {
3605                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3606                         return I40E_SUCCESS; /* Already off, skip next steps */
3607                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3608         }
3609
3610         /* Write the register */
3611         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3612         /* Check the result */
3613         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3614                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3615                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3616                 if (on) {
3617                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3618                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3619                                 break;
3620                 } else {
3621                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3622                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3623                                 break;
3624                 }
3625         }
3626
3627         /* Check if it is timeout */
3628         if (j >= I40E_CHK_Q_ENA_COUNT) {
3629                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3630                             (on ? "enable" : "disable"), q_idx);
3631                 return I40E_ERR_TIMEOUT;
3632         }
3633
3634         return I40E_SUCCESS;
3635 }
3636 /* Switch on or off the rx queues */
3637 static int
3638 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3639 {
3640         struct rte_eth_dev_data *dev_data = pf->dev_data;
3641         struct i40e_rx_queue *rxq;
3642         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3643         uint16_t i;
3644         int ret;
3645
3646         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3647                 rxq = dev_data->rx_queues[i];
3648                 /* Don't operate the queue if not configured or
3649                  * if starting only per queue */
3650                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3651                         continue;
3652                 if (on)
3653                         ret = i40e_dev_rx_queue_start(dev, i);
3654                 else
3655                         ret = i40e_dev_rx_queue_stop(dev, i);
3656                 if (ret != I40E_SUCCESS)
3657                         return ret;
3658         }
3659
3660         return I40E_SUCCESS;
3661 }
3662
3663 /* Switch on or off all the rx/tx queues */
3664 int
3665 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3666 {
3667         int ret;
3668
3669         if (on) {
3670                 /* enable rx queues before enabling tx queues */
3671                 ret = i40e_dev_switch_rx_queues(pf, on);
3672                 if (ret) {
3673                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3674                         return ret;
3675                 }
3676                 ret = i40e_dev_switch_tx_queues(pf, on);
3677         } else {
3678                 /* Stop tx queues before stopping rx queues */
3679                 ret = i40e_dev_switch_tx_queues(pf, on);
3680                 if (ret) {
3681                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3682                         return ret;
3683                 }
3684                 ret = i40e_dev_switch_rx_queues(pf, on);
3685         }
3686
3687         return ret;
3688 }
3689
3690 /* Initialize VSI for TX */
3691 static int
3692 i40e_dev_tx_init(struct i40e_pf *pf)
3693 {
3694         struct rte_eth_dev_data *data = pf->dev_data;
3695         uint16_t i;
3696         uint32_t ret = I40E_SUCCESS;
3697         struct i40e_tx_queue *txq;
3698
3699         for (i = 0; i < data->nb_tx_queues; i++) {
3700                 txq = data->tx_queues[i];
3701                 if (!txq || !txq->q_set)
3702                         continue;
3703                 ret = i40e_tx_queue_init(txq);
3704                 if (ret != I40E_SUCCESS)
3705                         break;
3706         }
3707
3708         return ret;
3709 }
3710
3711 /* Initialize VSI for RX */
3712 static int
3713 i40e_dev_rx_init(struct i40e_pf *pf)
3714 {
3715         struct rte_eth_dev_data *data = pf->dev_data;
3716         int ret = I40E_SUCCESS;
3717         uint16_t i;
3718         struct i40e_rx_queue *rxq;
3719
3720         i40e_pf_config_mq_rx(pf);
3721         for (i = 0; i < data->nb_rx_queues; i++) {
3722                 rxq = data->rx_queues[i];
3723                 if (!rxq || !rxq->q_set)
3724                         continue;
3725
3726                 ret = i40e_rx_queue_init(rxq);
3727                 if (ret != I40E_SUCCESS) {
3728                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3729                                     "initialization");
3730                         break;
3731                 }
3732         }
3733
3734         return ret;
3735 }
3736
3737 static int
3738 i40e_dev_rxtx_init(struct i40e_pf *pf)
3739 {
3740         int err;
3741
3742         err = i40e_dev_tx_init(pf);
3743         if (err) {
3744                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3745                 return err;
3746         }
3747         err = i40e_dev_rx_init(pf);
3748         if (err) {
3749                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3750                 return err;
3751         }
3752
3753         return err;
3754 }
3755
3756 static int
3757 i40e_vmdq_setup(struct rte_eth_dev *dev)
3758 {
3759         struct rte_eth_conf *conf = &dev->data->dev_conf;
3760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3761         int i, err, conf_vsis, j, loop;
3762         struct i40e_vsi *vsi;
3763         struct i40e_vmdq_info *vmdq_info;
3764         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3765         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3766
3767         /*
3768          * Disable interrupt to avoid message from VF. Furthermore, it will
3769          * avoid race condition in VSI creation/destroy.
3770          */
3771         i40e_pf_disable_irq0(hw);
3772
3773         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3774                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3775                 return -ENOTSUP;
3776         }
3777
3778         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3779         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3780                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3781                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3782                         pf->max_nb_vmdq_vsi);
3783                 return -ENOTSUP;
3784         }
3785
3786         if (pf->vmdq != NULL) {
3787                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3788                 return 0;
3789         }
3790
3791         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3792                                 sizeof(*vmdq_info) * conf_vsis, 0);
3793
3794         if (pf->vmdq == NULL) {
3795                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3796                 return -ENOMEM;
3797         }
3798
3799         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3800
3801         /* Create VMDQ VSI */
3802         for (i = 0; i < conf_vsis; i++) {
3803                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
3804                                 vmdq_conf->enable_loop_back);
3805                 if (vsi == NULL) {
3806                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
3807                         err = -1;
3808                         goto err_vsi_setup;
3809                 }
3810                 vmdq_info = &pf->vmdq[i];
3811                 vmdq_info->pf = pf;
3812                 vmdq_info->vsi = vsi;
3813         }
3814         pf->nb_cfg_vmdq_vsi = conf_vsis;
3815
3816         /* Configure Vlan */
3817         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
3818         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
3819                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
3820                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
3821                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
3822                                         vmdq_conf->pool_map[i].vlan_id, j);
3823
3824                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
3825                                                 vmdq_conf->pool_map[i].vlan_id);
3826                                 if (err) {
3827                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
3828                                         err = -1;
3829                                         goto err_vsi_setup;
3830                                 }
3831                         }
3832                 }
3833         }
3834
3835         i40e_pf_enable_irq0(hw);
3836
3837         return 0;
3838
3839 err_vsi_setup:
3840         for (i = 0; i < conf_vsis; i++)
3841                 if (pf->vmdq[i].vsi == NULL)
3842                         break;
3843                 else
3844                         i40e_vsi_release(pf->vmdq[i].vsi);
3845
3846         rte_free(pf->vmdq);
3847         pf->vmdq = NULL;
3848         i40e_pf_enable_irq0(hw);
3849         return err;
3850 }
3851
3852 static void
3853 i40e_stat_update_32(struct i40e_hw *hw,
3854                    uint32_t reg,
3855                    bool offset_loaded,
3856                    uint64_t *offset,
3857                    uint64_t *stat)
3858 {
3859         uint64_t new_data;
3860
3861         new_data = (uint64_t)I40E_READ_REG(hw, reg);
3862         if (!offset_loaded)
3863                 *offset = new_data;
3864
3865         if (new_data >= *offset)
3866                 *stat = (uint64_t)(new_data - *offset);
3867         else
3868                 *stat = (uint64_t)((new_data +
3869                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
3870 }
3871
3872 static void
3873 i40e_stat_update_48(struct i40e_hw *hw,
3874                    uint32_t hireg,
3875                    uint32_t loreg,
3876                    bool offset_loaded,
3877                    uint64_t *offset,
3878                    uint64_t *stat)
3879 {
3880         uint64_t new_data;
3881
3882         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
3883         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
3884                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
3885
3886         if (!offset_loaded)
3887                 *offset = new_data;
3888
3889         if (new_data >= *offset)
3890                 *stat = new_data - *offset;
3891         else
3892                 *stat = (uint64_t)((new_data +
3893                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
3894
3895         *stat &= I40E_48_BIT_MASK;
3896 }
3897
3898 /* Disable IRQ0 */
3899 void
3900 i40e_pf_disable_irq0(struct i40e_hw *hw)
3901 {
3902         /* Disable all interrupt types */
3903         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
3904         I40E_WRITE_FLUSH(hw);
3905 }
3906
3907 /* Enable IRQ0 */
3908 void
3909 i40e_pf_enable_irq0(struct i40e_hw *hw)
3910 {
3911         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
3912                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
3913                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3914                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
3915         I40E_WRITE_FLUSH(hw);
3916 }
3917
3918 static void
3919 i40e_pf_config_irq0(struct i40e_hw *hw)
3920 {
3921         /* read pending request and disable first */
3922         i40e_pf_disable_irq0(hw);
3923         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
3924         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
3925                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
3926
3927         /* Link no queues with irq0 */
3928         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
3929                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
3930 }
3931
3932 static void
3933 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
3934 {
3935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3937         int i;
3938         uint16_t abs_vf_id;
3939         uint32_t index, offset, val;
3940
3941         if (!pf->vfs)
3942                 return;
3943         /**
3944          * Try to find which VF trigger a reset, use absolute VF id to access
3945          * since the reg is global register.
3946          */
3947         for (i = 0; i < pf->vf_num; i++) {
3948                 abs_vf_id = hw->func_caps.vf_base_id + i;
3949                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
3950                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
3951                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
3952                 /* VFR event occured */
3953                 if (val & (0x1 << offset)) {
3954                         int ret;
3955
3956                         /* Clear the event first */
3957                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
3958                                                         (0x1 << offset));
3959                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
3960                         /**
3961                          * Only notify a VF reset event occured,
3962                          * don't trigger another SW reset
3963                          */
3964                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
3965                         if (ret != I40E_SUCCESS)
3966                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
3967                 }
3968         }
3969 }
3970
3971 static void
3972 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
3973 {
3974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975         struct i40e_arq_event_info info;
3976         uint16_t pending, opcode;
3977         int ret;
3978
3979         info.buf_len = I40E_AQ_BUF_SZ;
3980         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
3981         if (!info.msg_buf) {
3982                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
3983                 return;
3984         }
3985
3986         pending = 1;
3987         while (pending) {
3988                 ret = i40e_clean_arq_element(hw, &info, &pending);
3989
3990                 if (ret != I40E_SUCCESS) {
3991                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
3992                                     "aq_err: %u", hw->aq.asq_last_status);
3993                         break;
3994                 }
3995                 opcode = rte_le_to_cpu_16(info.desc.opcode);
3996
3997                 switch (opcode) {
3998                 case i40e_aqc_opc_send_msg_to_pf:
3999                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4000                         i40e_pf_host_handle_vf_msg(dev,
4001                                         rte_le_to_cpu_16(info.desc.retval),
4002                                         rte_le_to_cpu_32(info.desc.cookie_high),
4003                                         rte_le_to_cpu_32(info.desc.cookie_low),
4004                                         info.msg_buf,
4005                                         info.msg_len);
4006                         break;
4007                 default:
4008                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4009                                     opcode);
4010                         break;
4011                 }
4012         }
4013         rte_free(info.msg_buf);
4014 }
4015
4016 /*
4017  * Interrupt handler is registered as the alarm callback for handling LSC
4018  * interrupt in a definite of time, in order to wait the NIC into a stable
4019  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4020  * no need for link down interrupt.
4021  */
4022 static void
4023 i40e_dev_interrupt_delayed_handler(void *param)
4024 {
4025         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4026         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4027         uint32_t icr0;
4028
4029         /* read interrupt causes again */
4030         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4031
4032 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4033         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4034                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4035         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4036                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4037         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4038                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4039         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4040                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4041         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4042                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4043                                                                 "state\n");
4044         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4045                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4046         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4047                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4048 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4049
4050         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4051                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4052                 i40e_dev_handle_vfr_event(dev);
4053         }
4054         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4055                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4056                 i40e_dev_handle_aq_msg(dev);
4057         }
4058
4059         /* handle the link up interrupt in an alarm callback */
4060         i40e_dev_link_update(dev, 0);
4061         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4062
4063         i40e_pf_enable_irq0(hw);
4064         rte_intr_enable(&(dev->pci_dev->intr_handle));
4065 }
4066
4067 /**
4068  * Interrupt handler triggered by NIC  for handling
4069  * specific interrupt.
4070  *
4071  * @param handle
4072  *  Pointer to interrupt handle.
4073  * @param param
4074  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4075  *
4076  * @return
4077  *  void
4078  */
4079 static void
4080 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4081                            void *param)
4082 {
4083         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4085         uint32_t icr0;
4086
4087         /* Disable interrupt */
4088         i40e_pf_disable_irq0(hw);
4089
4090         /* read out interrupt causes */
4091         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4092
4093         /* No interrupt event indicated */
4094         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4095                 PMD_DRV_LOG(INFO, "No interrupt event");
4096                 goto done;
4097         }
4098 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4099         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4100                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4101         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4102                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4103         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4104                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4105         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4106                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4107         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4108                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4109         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4110                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4111         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4112                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4113 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4114
4115         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4116                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4117                 i40e_dev_handle_vfr_event(dev);
4118         }
4119         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4120                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4121                 i40e_dev_handle_aq_msg(dev);
4122         }
4123
4124         /* Link Status Change interrupt */
4125         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4126 #define I40E_US_PER_SECOND 1000000
4127                 struct rte_eth_link link;
4128
4129                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4130                 memset(&link, 0, sizeof(link));
4131                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4132                 i40e_dev_link_update(dev, 0);
4133
4134                 /*
4135                  * For link up interrupt, it needs to wait 1 second to let the
4136                  * hardware be a stable state. Otherwise several consecutive
4137                  * interrupts can be observed.
4138                  * For link down interrupt, no need to wait.
4139                  */
4140                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4141                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4142                         return;
4143                 else
4144                         _rte_eth_dev_callback_process(dev,
4145                                 RTE_ETH_EVENT_INTR_LSC);
4146         }
4147
4148 done:
4149         /* Enable interrupt */
4150         i40e_pf_enable_irq0(hw);
4151         rte_intr_enable(&(dev->pci_dev->intr_handle));
4152 }
4153
4154 static int
4155 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4156                          struct i40e_macvlan_filter *filter,
4157                          int total)
4158 {
4159         int ele_num, ele_buff_size;
4160         int num, actual_num, i;
4161         uint16_t flags;
4162         int ret = I40E_SUCCESS;
4163         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4164         struct i40e_aqc_add_macvlan_element_data *req_list;
4165
4166         if (filter == NULL  || total == 0)
4167                 return I40E_ERR_PARAM;
4168         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4169         ele_buff_size = hw->aq.asq_buf_size;
4170
4171         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4172         if (req_list == NULL) {
4173                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4174                 return I40E_ERR_NO_MEMORY;
4175         }
4176
4177         num = 0;
4178         do {
4179                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4180                 memset(req_list, 0, ele_buff_size);
4181
4182                 for (i = 0; i < actual_num; i++) {
4183                         (void)rte_memcpy(req_list[i].mac_addr,
4184                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4185                         req_list[i].vlan_tag =
4186                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4187
4188                         switch (filter[num + i].filter_type) {
4189                         case RTE_MAC_PERFECT_MATCH:
4190                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4191                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4192                                 break;
4193                         case RTE_MACVLAN_PERFECT_MATCH:
4194                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4195                                 break;
4196                         case RTE_MAC_HASH_MATCH:
4197                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4198                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4199                                 break;
4200                         case RTE_MACVLAN_HASH_MATCH:
4201                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4202                                 break;
4203                         default:
4204                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4205                                 ret = I40E_ERR_PARAM;
4206                                 goto DONE;
4207                         }
4208
4209                         req_list[i].queue_number = 0;
4210
4211                         req_list[i].flags = rte_cpu_to_le_16(flags);
4212                 }
4213
4214                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4215                                                 actual_num, NULL);
4216                 if (ret != I40E_SUCCESS) {
4217                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4218                         goto DONE;
4219                 }
4220                 num += actual_num;
4221         } while (num < total);
4222
4223 DONE:
4224         rte_free(req_list);
4225         return ret;
4226 }
4227
4228 static int
4229 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4230                             struct i40e_macvlan_filter *filter,
4231                             int total)
4232 {
4233         int ele_num, ele_buff_size;
4234         int num, actual_num, i;
4235         uint16_t flags;
4236         int ret = I40E_SUCCESS;
4237         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4238         struct i40e_aqc_remove_macvlan_element_data *req_list;
4239
4240         if (filter == NULL  || total == 0)
4241                 return I40E_ERR_PARAM;
4242
4243         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4244         ele_buff_size = hw->aq.asq_buf_size;
4245
4246         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4247         if (req_list == NULL) {
4248                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4249                 return I40E_ERR_NO_MEMORY;
4250         }
4251
4252         num = 0;
4253         do {
4254                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4255                 memset(req_list, 0, ele_buff_size);
4256
4257                 for (i = 0; i < actual_num; i++) {
4258                         (void)rte_memcpy(req_list[i].mac_addr,
4259                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4260                         req_list[i].vlan_tag =
4261                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4262
4263                         switch (filter[num + i].filter_type) {
4264                         case RTE_MAC_PERFECT_MATCH:
4265                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4266                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4267                                 break;
4268                         case RTE_MACVLAN_PERFECT_MATCH:
4269                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4270                                 break;
4271                         case RTE_MAC_HASH_MATCH:
4272                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4273                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4274                                 break;
4275                         case RTE_MACVLAN_HASH_MATCH:
4276                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4277                                 break;
4278                         default:
4279                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4280                                 ret = I40E_ERR_PARAM;
4281                                 goto DONE;
4282                         }
4283                         req_list[i].flags = rte_cpu_to_le_16(flags);
4284                 }
4285
4286                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4287                                                 actual_num, NULL);
4288                 if (ret != I40E_SUCCESS) {
4289                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4290                         goto DONE;
4291                 }
4292                 num += actual_num;
4293         } while (num < total);
4294
4295 DONE:
4296         rte_free(req_list);
4297         return ret;
4298 }
4299
4300 /* Find out specific MAC filter */
4301 static struct i40e_mac_filter *
4302 i40e_find_mac_filter(struct i40e_vsi *vsi,
4303                          struct ether_addr *macaddr)
4304 {
4305         struct i40e_mac_filter *f;
4306
4307         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4308                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4309                         return f;
4310         }
4311
4312         return NULL;
4313 }
4314
4315 static bool
4316 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4317                          uint16_t vlan_id)
4318 {
4319         uint32_t vid_idx, vid_bit;
4320
4321         if (vlan_id > ETH_VLAN_ID_MAX)
4322                 return 0;
4323
4324         vid_idx = I40E_VFTA_IDX(vlan_id);
4325         vid_bit = I40E_VFTA_BIT(vlan_id);
4326
4327         if (vsi->vfta[vid_idx] & vid_bit)
4328                 return 1;
4329         else
4330                 return 0;
4331 }
4332
4333 static void
4334 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4335                          uint16_t vlan_id, bool on)
4336 {
4337         uint32_t vid_idx, vid_bit;
4338
4339         if (vlan_id > ETH_VLAN_ID_MAX)
4340                 return;
4341
4342         vid_idx = I40E_VFTA_IDX(vlan_id);
4343         vid_bit = I40E_VFTA_BIT(vlan_id);
4344
4345         if (on)
4346                 vsi->vfta[vid_idx] |= vid_bit;
4347         else
4348                 vsi->vfta[vid_idx] &= ~vid_bit;
4349 }
4350
4351 /**
4352  * Find all vlan options for specific mac addr,
4353  * return with actual vlan found.
4354  */
4355 static inline int
4356 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4357                            struct i40e_macvlan_filter *mv_f,
4358                            int num, struct ether_addr *addr)
4359 {
4360         int i;
4361         uint32_t j, k;
4362
4363         /**
4364          * Not to use i40e_find_vlan_filter to decrease the loop time,
4365          * although the code looks complex.
4366           */
4367         if (num < vsi->vlan_num)
4368                 return I40E_ERR_PARAM;
4369
4370         i = 0;
4371         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4372                 if (vsi->vfta[j]) {
4373                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4374                                 if (vsi->vfta[j] & (1 << k)) {
4375                                         if (i > num - 1) {
4376                                                 PMD_DRV_LOG(ERR, "vlan number "
4377                                                             "not match");
4378                                                 return I40E_ERR_PARAM;
4379                                         }
4380                                         (void)rte_memcpy(&mv_f[i].macaddr,
4381                                                         addr, ETH_ADDR_LEN);
4382                                         mv_f[i].vlan_id =
4383                                                 j * I40E_UINT32_BIT_SIZE + k;
4384                                         i++;
4385                                 }
4386                         }
4387                 }
4388         }
4389         return I40E_SUCCESS;
4390 }
4391
4392 static inline int
4393 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4394                            struct i40e_macvlan_filter *mv_f,
4395                            int num,
4396                            uint16_t vlan)
4397 {
4398         int i = 0;
4399         struct i40e_mac_filter *f;
4400
4401         if (num < vsi->mac_num)
4402                 return I40E_ERR_PARAM;
4403
4404         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4405                 if (i > num - 1) {
4406                         PMD_DRV_LOG(ERR, "buffer number not match");
4407                         return I40E_ERR_PARAM;
4408                 }
4409                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4410                                 ETH_ADDR_LEN);
4411                 mv_f[i].vlan_id = vlan;
4412                 mv_f[i].filter_type = f->mac_info.filter_type;
4413                 i++;
4414         }
4415
4416         return I40E_SUCCESS;
4417 }
4418
4419 static int
4420 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4421 {
4422         int i, num;
4423         struct i40e_mac_filter *f;
4424         struct i40e_macvlan_filter *mv_f;
4425         int ret = I40E_SUCCESS;
4426
4427         if (vsi == NULL || vsi->mac_num == 0)
4428                 return I40E_ERR_PARAM;
4429
4430         /* Case that no vlan is set */
4431         if (vsi->vlan_num == 0)
4432                 num = vsi->mac_num;
4433         else
4434                 num = vsi->mac_num * vsi->vlan_num;
4435
4436         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4437         if (mv_f == NULL) {
4438                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4439                 return I40E_ERR_NO_MEMORY;
4440         }
4441
4442         i = 0;
4443         if (vsi->vlan_num == 0) {
4444                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4445                         (void)rte_memcpy(&mv_f[i].macaddr,
4446                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4447                         mv_f[i].vlan_id = 0;
4448                         i++;
4449                 }
4450         } else {
4451                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4452                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4453                                         vsi->vlan_num, &f->mac_info.mac_addr);
4454                         if (ret != I40E_SUCCESS)
4455                                 goto DONE;
4456                         i += vsi->vlan_num;
4457                 }
4458         }
4459
4460         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4461 DONE:
4462         rte_free(mv_f);
4463
4464         return ret;
4465 }
4466
4467 int
4468 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4469 {
4470         struct i40e_macvlan_filter *mv_f;
4471         int mac_num;
4472         int ret = I40E_SUCCESS;
4473
4474         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4475                 return I40E_ERR_PARAM;
4476
4477         /* If it's already set, just return */
4478         if (i40e_find_vlan_filter(vsi,vlan))
4479                 return I40E_SUCCESS;
4480
4481         mac_num = vsi->mac_num;
4482
4483         if (mac_num == 0) {
4484                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4485                 return I40E_ERR_PARAM;
4486         }
4487
4488         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4489
4490         if (mv_f == NULL) {
4491                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4492                 return I40E_ERR_NO_MEMORY;
4493         }
4494
4495         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4496
4497         if (ret != I40E_SUCCESS)
4498                 goto DONE;
4499
4500         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4501
4502         if (ret != I40E_SUCCESS)
4503                 goto DONE;
4504
4505         i40e_set_vlan_filter(vsi, vlan, 1);
4506
4507         vsi->vlan_num++;
4508         ret = I40E_SUCCESS;
4509 DONE:
4510         rte_free(mv_f);
4511         return ret;
4512 }
4513
4514 int
4515 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4516 {
4517         struct i40e_macvlan_filter *mv_f;
4518         int mac_num;
4519         int ret = I40E_SUCCESS;
4520
4521         /**
4522          * Vlan 0 is the generic filter for untagged packets
4523          * and can't be removed.
4524          */
4525         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4526                 return I40E_ERR_PARAM;
4527
4528         /* If can't find it, just return */
4529         if (!i40e_find_vlan_filter(vsi, vlan))
4530                 return I40E_ERR_PARAM;
4531
4532         mac_num = vsi->mac_num;
4533
4534         if (mac_num == 0) {
4535                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4536                 return I40E_ERR_PARAM;
4537         }
4538
4539         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4540
4541         if (mv_f == NULL) {
4542                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4543                 return I40E_ERR_NO_MEMORY;
4544         }
4545
4546         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4547
4548         if (ret != I40E_SUCCESS)
4549                 goto DONE;
4550
4551         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4552
4553         if (ret != I40E_SUCCESS)
4554                 goto DONE;
4555
4556         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4557         if (vsi->vlan_num == 1) {
4558                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4559                 if (ret != I40E_SUCCESS)
4560                         goto DONE;
4561
4562                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4563                 if (ret != I40E_SUCCESS)
4564                         goto DONE;
4565         }
4566
4567         i40e_set_vlan_filter(vsi, vlan, 0);
4568
4569         vsi->vlan_num--;
4570         ret = I40E_SUCCESS;
4571 DONE:
4572         rte_free(mv_f);
4573         return ret;
4574 }
4575
4576 int
4577 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4578 {
4579         struct i40e_mac_filter *f;
4580         struct i40e_macvlan_filter *mv_f;
4581         int i, vlan_num = 0;
4582         int ret = I40E_SUCCESS;
4583
4584         /* If it's add and we've config it, return */
4585         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4586         if (f != NULL)
4587                 return I40E_SUCCESS;
4588         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4589                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4590
4591                 /**
4592                  * If vlan_num is 0, that's the first time to add mac,
4593                  * set mask for vlan_id 0.
4594                  */
4595                 if (vsi->vlan_num == 0) {
4596                         i40e_set_vlan_filter(vsi, 0, 1);
4597                         vsi->vlan_num = 1;
4598                 }
4599                 vlan_num = vsi->vlan_num;
4600         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4601                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4602                 vlan_num = 1;
4603
4604         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4605         if (mv_f == NULL) {
4606                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4607                 return I40E_ERR_NO_MEMORY;
4608         }
4609
4610         for (i = 0; i < vlan_num; i++) {
4611                 mv_f[i].filter_type = mac_filter->filter_type;
4612                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4613                                 ETH_ADDR_LEN);
4614         }
4615
4616         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4617                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4618                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4619                                         &mac_filter->mac_addr);
4620                 if (ret != I40E_SUCCESS)
4621                         goto DONE;
4622         }
4623
4624         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4625         if (ret != I40E_SUCCESS)
4626                 goto DONE;
4627
4628         /* Add the mac addr into mac list */
4629         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4630         if (f == NULL) {
4631                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4632                 ret = I40E_ERR_NO_MEMORY;
4633                 goto DONE;
4634         }
4635         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4636                         ETH_ADDR_LEN);
4637         f->mac_info.filter_type = mac_filter->filter_type;
4638         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4639         vsi->mac_num++;
4640
4641         ret = I40E_SUCCESS;
4642 DONE:
4643         rte_free(mv_f);
4644
4645         return ret;
4646 }
4647
4648 int
4649 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4650 {
4651         struct i40e_mac_filter *f;
4652         struct i40e_macvlan_filter *mv_f;
4653         int i, vlan_num;
4654         enum rte_mac_filter_type filter_type;
4655         int ret = I40E_SUCCESS;
4656
4657         /* Can't find it, return an error */
4658         f = i40e_find_mac_filter(vsi, addr);
4659         if (f == NULL)
4660                 return I40E_ERR_PARAM;
4661
4662         vlan_num = vsi->vlan_num;
4663         filter_type = f->mac_info.filter_type;
4664         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4665                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4666                 if (vlan_num == 0) {
4667                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4668                         return I40E_ERR_PARAM;
4669                 }
4670         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4671                         filter_type == RTE_MAC_HASH_MATCH)
4672                 vlan_num = 1;
4673
4674         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4675         if (mv_f == NULL) {
4676                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4677                 return I40E_ERR_NO_MEMORY;
4678         }
4679
4680         for (i = 0; i < vlan_num; i++) {
4681                 mv_f[i].filter_type = filter_type;
4682                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4683                                 ETH_ADDR_LEN);
4684         }
4685         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4686                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4687                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4688                 if (ret != I40E_SUCCESS)
4689                         goto DONE;
4690         }
4691
4692         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4693         if (ret != I40E_SUCCESS)
4694                 goto DONE;
4695
4696         /* Remove the mac addr into mac list */
4697         TAILQ_REMOVE(&vsi->mac_list, f, next);
4698         rte_free(f);
4699         vsi->mac_num--;
4700
4701         ret = I40E_SUCCESS;
4702 DONE:
4703         rte_free(mv_f);
4704         return ret;
4705 }
4706
4707 /* Configure hash enable flags for RSS */
4708 uint64_t
4709 i40e_config_hena(uint64_t flags)
4710 {
4711         uint64_t hena = 0;
4712
4713         if (!flags)
4714                 return hena;
4715
4716         if (flags & ETH_RSS_FRAG_IPV4)
4717                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4718         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4719                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4720         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4721                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4722         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4723                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4724         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4725                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4726         if (flags & ETH_RSS_FRAG_IPV6)
4727                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4728         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4729                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4730         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4731                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4732         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4733                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4734         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4735                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4736         if (flags & ETH_RSS_L2_PAYLOAD)
4737                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4738
4739         return hena;
4740 }
4741
4742 /* Parse the hash enable flags */
4743 uint64_t
4744 i40e_parse_hena(uint64_t flags)
4745 {
4746         uint64_t rss_hf = 0;
4747
4748         if (!flags)
4749                 return rss_hf;
4750         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4751                 rss_hf |= ETH_RSS_FRAG_IPV4;
4752         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4753                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4754         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4755                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4756         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4757                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4758         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4759                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4760         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4761                 rss_hf |= ETH_RSS_FRAG_IPV6;
4762         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4763                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4764         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4765                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4766         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4767                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4768         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4769                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4770         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4771                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4772
4773         return rss_hf;
4774 }
4775
4776 /* Disable RSS */
4777 static void
4778 i40e_pf_disable_rss(struct i40e_pf *pf)
4779 {
4780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4781         uint64_t hena;
4782
4783         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4784         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4785         hena &= ~I40E_RSS_HENA_ALL;
4786         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4787         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4788         I40E_WRITE_FLUSH(hw);
4789 }
4790
4791 static int
4792 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4793 {
4794         uint32_t *hash_key;
4795         uint8_t hash_key_len;
4796         uint64_t rss_hf;
4797         uint16_t i;
4798         uint64_t hena;
4799
4800         hash_key = (uint32_t *)(rss_conf->rss_key);
4801         hash_key_len = rss_conf->rss_key_len;
4802         if (hash_key != NULL && hash_key_len >=
4803                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
4804                 /* Fill in RSS hash key */
4805                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4806                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
4807         }
4808
4809         rss_hf = rss_conf->rss_hf;
4810         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4811         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4812         hena &= ~I40E_RSS_HENA_ALL;
4813         hena |= i40e_config_hena(rss_hf);
4814         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4815         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4816         I40E_WRITE_FLUSH(hw);
4817
4818         return 0;
4819 }
4820
4821 static int
4822 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
4823                          struct rte_eth_rss_conf *rss_conf)
4824 {
4825         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
4827         uint64_t hena;
4828
4829         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4830         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4831         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
4832                 if (rss_hf != 0) /* Enable RSS */
4833                         return -EINVAL;
4834                 return 0; /* Nothing to do */
4835         }
4836         /* RSS enabled */
4837         if (rss_hf == 0) /* Disable RSS */
4838                 return -EINVAL;
4839
4840         return i40e_hw_rss_hash_set(hw, rss_conf);
4841 }
4842
4843 static int
4844 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
4845                            struct rte_eth_rss_conf *rss_conf)
4846 {
4847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4848         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
4849         uint64_t hena;
4850         uint16_t i;
4851
4852         if (hash_key != NULL) {
4853                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
4854                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
4855                 rss_conf->rss_key_len = i * sizeof(uint32_t);
4856         }
4857         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4858         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4859         rss_conf->rss_hf = i40e_parse_hena(hena);
4860
4861         return 0;
4862 }
4863
4864 static int
4865 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
4866 {
4867         switch (filter_type) {
4868         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
4869                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
4870                 break;
4871         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
4872                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
4873                 break;
4874         case RTE_TUNNEL_FILTER_IMAC_TENID:
4875                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
4876                 break;
4877         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
4878                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
4879                 break;
4880         case ETH_TUNNEL_FILTER_IMAC:
4881                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
4882                 break;
4883         default:
4884                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
4885                 return -EINVAL;
4886         }
4887
4888         return 0;
4889 }
4890
4891 static int
4892 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
4893                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
4894                         uint8_t add)
4895 {
4896         uint16_t ip_type;
4897         uint8_t tun_type = 0;
4898         int val, ret = 0;
4899         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4900         struct i40e_vsi *vsi = pf->main_vsi;
4901         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
4902         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
4903
4904         cld_filter = rte_zmalloc("tunnel_filter",
4905                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
4906                 0);
4907
4908         if (NULL == cld_filter) {
4909                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
4910                 return -EINVAL;
4911         }
4912         pfilter = cld_filter;
4913
4914         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
4915                         sizeof(struct ether_addr));
4916         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
4917                         sizeof(struct ether_addr));
4918
4919         pfilter->inner_vlan = tunnel_filter->inner_vlan;
4920         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
4921                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
4922                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
4923                                 &tunnel_filter->ip_addr,
4924                                 sizeof(pfilter->ipaddr.v4.data));
4925         } else {
4926                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
4927                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
4928                                 &tunnel_filter->ip_addr,
4929                                 sizeof(pfilter->ipaddr.v6.data));
4930         }
4931
4932         /* check tunneled type */
4933         switch (tunnel_filter->tunnel_type) {
4934         case RTE_TUNNEL_TYPE_VXLAN:
4935                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
4936                 break;
4937         case RTE_TUNNEL_TYPE_NVGRE:
4938                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
4939                 break;
4940         default:
4941                 /* Other tunnel types is not supported. */
4942                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
4943                 rte_free(cld_filter);
4944                 return -EINVAL;
4945         }
4946
4947         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
4948                                                 &pfilter->flags);
4949         if (val < 0) {
4950                 rte_free(cld_filter);
4951                 return -EINVAL;
4952         }
4953
4954         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
4955                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
4956         pfilter->tenant_id = tunnel_filter->tenant_id;
4957         pfilter->queue_number = tunnel_filter->queue_id;
4958
4959         if (add)
4960                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
4961         else
4962                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4963                                                 cld_filter, 1);
4964
4965         rte_free(cld_filter);
4966         return ret;
4967 }
4968
4969 static int
4970 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
4971 {
4972         uint8_t i;
4973
4974         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
4975                 if (pf->vxlan_ports[i] == port)
4976                         return i;
4977         }
4978
4979         return -1;
4980 }
4981
4982 static int
4983 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
4984 {
4985         int  idx, ret;
4986         uint8_t filter_idx;
4987         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4988
4989         idx = i40e_get_vxlan_port_idx(pf, port);
4990
4991         /* Check if port already exists */
4992         if (idx >= 0) {
4993                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
4994                 return -EINVAL;
4995         }
4996
4997         /* Now check if there is space to add the new port */
4998         idx = i40e_get_vxlan_port_idx(pf, 0);
4999         if (idx < 0) {
5000                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5001                         "not adding port %d", port);
5002                 return -ENOSPC;
5003         }
5004
5005         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5006                                         &filter_idx, NULL);
5007         if (ret < 0) {
5008                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5009                 return -1;
5010         }
5011
5012         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5013                          port,  filter_idx);
5014
5015         /* New port: add it and mark its index in the bitmap */
5016         pf->vxlan_ports[idx] = port;
5017         pf->vxlan_bitmap |= (1 << idx);
5018
5019         if (!(pf->flags & I40E_FLAG_VXLAN))
5020                 pf->flags |= I40E_FLAG_VXLAN;
5021
5022         return 0;
5023 }
5024
5025 static int
5026 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5027 {
5028         int idx;
5029         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5030
5031         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5032                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5033                 return -EINVAL;
5034         }
5035
5036         idx = i40e_get_vxlan_port_idx(pf, port);
5037
5038         if (idx < 0) {
5039                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5040                 return -EINVAL;
5041         }
5042
5043         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5044                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5045                 return -1;
5046         }
5047
5048         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5049                         port, idx);
5050
5051         pf->vxlan_ports[idx] = 0;
5052         pf->vxlan_bitmap &= ~(1 << idx);
5053
5054         if (!pf->vxlan_bitmap)
5055                 pf->flags &= ~I40E_FLAG_VXLAN;
5056
5057         return 0;
5058 }
5059
5060 /* Add UDP tunneling port */
5061 static int
5062 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5063                         struct rte_eth_udp_tunnel *udp_tunnel)
5064 {
5065         int ret = 0;
5066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5067
5068         if (udp_tunnel == NULL)
5069                 return -EINVAL;
5070
5071         switch (udp_tunnel->prot_type) {
5072         case RTE_TUNNEL_TYPE_VXLAN:
5073                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5074                 break;
5075
5076         case RTE_TUNNEL_TYPE_GENEVE:
5077         case RTE_TUNNEL_TYPE_TEREDO:
5078                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5079                 ret = -1;
5080                 break;
5081
5082         default:
5083                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5084                 ret = -1;
5085                 break;
5086         }
5087
5088         return ret;
5089 }
5090
5091 /* Remove UDP tunneling port */
5092 static int
5093 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5094                         struct rte_eth_udp_tunnel *udp_tunnel)
5095 {
5096         int ret = 0;
5097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5098
5099         if (udp_tunnel == NULL)
5100                 return -EINVAL;
5101
5102         switch (udp_tunnel->prot_type) {
5103         case RTE_TUNNEL_TYPE_VXLAN:
5104                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5105                 break;
5106         case RTE_TUNNEL_TYPE_GENEVE:
5107         case RTE_TUNNEL_TYPE_TEREDO:
5108                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5109                 ret = -1;
5110                 break;
5111         default:
5112                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5113                 ret = -1;
5114                 break;
5115         }
5116
5117         return ret;
5118 }
5119
5120 /* Calculate the maximum number of contiguous PF queues that are configured */
5121 static int
5122 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5123 {
5124         struct rte_eth_dev_data *data = pf->dev_data;
5125         int i, num;
5126         struct i40e_rx_queue *rxq;
5127
5128         num = 0;
5129         for (i = 0; i < pf->lan_nb_qps; i++) {
5130                 rxq = data->rx_queues[i];
5131                 if (rxq && rxq->q_set)
5132                         num++;
5133                 else
5134                         break;
5135         }
5136
5137         return num;
5138 }
5139
5140 /* Configure RSS */
5141 static int
5142 i40e_pf_config_rss(struct i40e_pf *pf)
5143 {
5144         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5145         struct rte_eth_rss_conf rss_conf;
5146         uint32_t i, lut = 0;
5147         uint16_t j, num;
5148
5149         /*
5150          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5151          * It's necessary to calulate the actual PF queues that are configured.
5152          */
5153         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5154                 num = i40e_pf_calc_configured_queues_num(pf);
5155                 num = i40e_align_floor(num);
5156         } else
5157                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5158
5159         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5160                         num);
5161
5162         if (num == 0) {
5163                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5164                 return -ENOTSUP;
5165         }
5166
5167         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5168                 if (j == num)
5169                         j = 0;
5170                 lut = (lut << 8) | (j & ((0x1 <<
5171                         hw->func_caps.rss_table_entry_width) - 1));
5172                 if ((i & 3) == 3)
5173                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5174         }
5175
5176         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5177         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5178                 i40e_pf_disable_rss(pf);
5179                 return 0;
5180         }
5181         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5182                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5183                 /* Random default keys */
5184                 static uint32_t rss_key_default[] = {0x6b793944,
5185                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5186                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5187                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5188
5189                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5190                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5191                                                         sizeof(uint32_t);
5192         }
5193
5194         return i40e_hw_rss_hash_set(hw, &rss_conf);
5195 }
5196
5197 static int
5198 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5199                         struct rte_eth_tunnel_filter_conf *filter)
5200 {
5201         if (pf == NULL || filter == NULL) {
5202                 PMD_DRV_LOG(ERR, "Invalid parameter");
5203                 return -EINVAL;
5204         }
5205
5206         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5207                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5208                 return -EINVAL;
5209         }
5210
5211         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5212                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5213                 return -EINVAL;
5214         }
5215
5216         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5217                 (is_zero_ether_addr(filter->outer_mac))) {
5218                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5219                 return -EINVAL;
5220         }
5221
5222         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5223                 (is_zero_ether_addr(filter->inner_mac))) {
5224                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5225                 return -EINVAL;
5226         }
5227
5228         return 0;
5229 }
5230
5231 static int
5232 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5233                         void *arg)
5234 {
5235         struct rte_eth_tunnel_filter_conf *filter;
5236         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5237         int ret = I40E_SUCCESS;
5238
5239         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5240
5241         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5242                 return I40E_ERR_PARAM;
5243
5244         switch (filter_op) {
5245         case RTE_ETH_FILTER_NOP:
5246                 if (!(pf->flags & I40E_FLAG_VXLAN))
5247                         ret = I40E_NOT_SUPPORTED;
5248         case RTE_ETH_FILTER_ADD:
5249                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5250                 break;
5251         case RTE_ETH_FILTER_DELETE:
5252                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5253                 break;
5254         default:
5255                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5256                 ret = I40E_ERR_PARAM;
5257                 break;
5258         }
5259
5260         return ret;
5261 }
5262
5263 static int
5264 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5265 {
5266         int ret = 0;
5267         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5268
5269         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5270                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5271                 return -ENOTSUP;
5272         }
5273
5274         /* RSS setup */
5275         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5276                 ret = i40e_pf_config_rss(pf);
5277         else
5278                 i40e_pf_disable_rss(pf);
5279
5280         return ret;
5281 }
5282
5283 /* Get the symmetric hash enable configurations per port */
5284 static void
5285 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5286 {
5287         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5288
5289         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5290 }
5291
5292 /* Set the symmetric hash enable configurations per port */
5293 static void
5294 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5295 {
5296         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5297
5298         if (enable > 0) {
5299                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5300                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5301                                                         "been enabled");
5302                         return;
5303                 }
5304                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5305         } else {
5306                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5307                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5308                                                         "been disabled");
5309                         return;
5310                 }
5311                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5312         }
5313         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5314         I40E_WRITE_FLUSH(hw);
5315 }
5316
5317 /*
5318  * Get global configurations of hash function type and symmetric hash enable
5319  * per flow type (pctype). Note that global configuration means it affects all
5320  * the ports on the same NIC.
5321  */
5322 static int
5323 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5324                                    struct rte_eth_hash_global_conf *g_cfg)
5325 {
5326         uint32_t reg, mask = I40E_FLOW_TYPES;
5327         uint16_t i;
5328         enum i40e_filter_pctype pctype;
5329
5330         memset(g_cfg, 0, sizeof(*g_cfg));
5331         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5332         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5333                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5334         else
5335                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5336         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5337                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5338
5339         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5340                 if (!(mask & (1UL << i)))
5341                         continue;
5342                 mask &= ~(1UL << i);
5343                 /* Bit set indicats the coresponding flow type is supported */
5344                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5345                 pctype = i40e_flowtype_to_pctype(i);
5346                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5347                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5348                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5349         }
5350
5351         return 0;
5352 }
5353
5354 static int
5355 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5356 {
5357         uint32_t i;
5358         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5359
5360         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5361                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5362                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5363                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5364                                                 g_cfg->hash_func);
5365                 return -EINVAL;
5366         }
5367
5368         /*
5369          * As i40e supports less than 32 flow types, only first 32 bits need to
5370          * be checked.
5371          */
5372         mask0 = g_cfg->valid_bit_mask[0];
5373         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5374                 if (i == 0) {
5375                         /* Check if any unsupported flow type configured */
5376                         if ((mask0 | i40e_mask) ^ i40e_mask)
5377                                 goto mask_err;
5378                 } else {
5379                         if (g_cfg->valid_bit_mask[i])
5380                                 goto mask_err;
5381                 }
5382         }
5383
5384         return 0;
5385
5386 mask_err:
5387         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5388
5389         return -EINVAL;
5390 }
5391
5392 /*
5393  * Set global configurations of hash function type and symmetric hash enable
5394  * per flow type (pctype). Note any modifying global configuration will affect
5395  * all the ports on the same NIC.
5396  */
5397 static int
5398 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5399                                    struct rte_eth_hash_global_conf *g_cfg)
5400 {
5401         int ret;
5402         uint16_t i;
5403         uint32_t reg;
5404         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5405         enum i40e_filter_pctype pctype;
5406
5407         /* Check the input parameters */
5408         ret = i40e_hash_global_config_check(g_cfg);
5409         if (ret < 0)
5410                 return ret;
5411
5412         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5413                 if (!(mask0 & (1UL << i)))
5414                         continue;
5415                 mask0 &= ~(1UL << i);
5416                 pctype = i40e_flowtype_to_pctype(i);
5417                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5418                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5419                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5420         }
5421
5422         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5423         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5424                 /* Toeplitz */
5425                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5426                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5427                                                                 "Toeplitz");
5428                         goto out;
5429                 }
5430                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5431         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5432                 /* Simple XOR */
5433                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5434                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5435                                                         "Simple XOR");
5436                         goto out;
5437                 }
5438                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5439         } else
5440                 /* Use the default, and keep it as it is */
5441                 goto out;
5442
5443         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5444
5445 out:
5446         I40E_WRITE_FLUSH(hw);
5447
5448         return 0;
5449 }
5450
5451 static int
5452 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5453 {
5454         int ret = 0;
5455
5456         if (!hw || !info) {
5457                 PMD_DRV_LOG(ERR, "Invalid pointer");
5458                 return -EFAULT;
5459         }
5460
5461         switch (info->info_type) {
5462         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5463                 i40e_get_symmetric_hash_enable_per_port(hw,
5464                                         &(info->info.enable));
5465                 break;
5466         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5467                 ret = i40e_get_hash_filter_global_config(hw,
5468                                 &(info->info.global_conf));
5469                 break;
5470         default:
5471                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5472                                                         info->info_type);
5473                 ret = -EINVAL;
5474                 break;
5475         }
5476
5477         return ret;
5478 }
5479
5480 static int
5481 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5482 {
5483         int ret = 0;
5484
5485         if (!hw || !info) {
5486                 PMD_DRV_LOG(ERR, "Invalid pointer");
5487                 return -EFAULT;
5488         }
5489
5490         switch (info->info_type) {
5491         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5492                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5493                 break;
5494         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5495                 ret = i40e_set_hash_filter_global_config(hw,
5496                                 &(info->info.global_conf));
5497                 break;
5498         default:
5499                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5500                                                         info->info_type);
5501                 ret = -EINVAL;
5502                 break;
5503         }
5504
5505         return ret;
5506 }
5507
5508 /* Operations for hash function */
5509 static int
5510 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5511                       enum rte_filter_op filter_op,
5512                       void *arg)
5513 {
5514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5515         int ret = 0;
5516
5517         switch (filter_op) {
5518         case RTE_ETH_FILTER_NOP:
5519                 break;
5520         case RTE_ETH_FILTER_GET:
5521                 ret = i40e_hash_filter_get(hw,
5522                         (struct rte_eth_hash_filter_info *)arg);
5523                 break;
5524         case RTE_ETH_FILTER_SET:
5525                 ret = i40e_hash_filter_set(hw,
5526                         (struct rte_eth_hash_filter_info *)arg);
5527                 break;
5528         default:
5529                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5530                                                                 filter_op);
5531                 ret = -ENOTSUP;
5532                 break;
5533         }
5534
5535         return ret;
5536 }
5537
5538 /*
5539  * Configure ethertype filter, which can director packet by filtering
5540  * with mac address and ether_type or only ether_type
5541  */
5542 static int
5543 i40e_ethertype_filter_set(struct i40e_pf *pf,
5544                         struct rte_eth_ethertype_filter *filter,
5545                         bool add)
5546 {
5547         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5548         struct i40e_control_filter_stats stats;
5549         uint16_t flags = 0;
5550         int ret;
5551
5552         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5553                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5554                 return -EINVAL;
5555         }
5556         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5557                 filter->ether_type == ETHER_TYPE_IPv6) {
5558                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5559                         " control packet filter.", filter->ether_type);
5560                 return -EINVAL;
5561         }
5562         if (filter->ether_type == ETHER_TYPE_VLAN)
5563                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5564                         " not supported.");
5565
5566         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5567                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5568         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5569                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5570         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5571
5572         memset(&stats, 0, sizeof(stats));
5573         ret = i40e_aq_add_rem_control_packet_filter(hw,
5574                         filter->mac_addr.addr_bytes,
5575                         filter->ether_type, flags,
5576                         pf->main_vsi->seid,
5577                         filter->queue, add, &stats, NULL);
5578
5579         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5580                          " mac_etype_used = %u, etype_used = %u,"
5581                          " mac_etype_free = %u, etype_free = %u\n",
5582                          ret, stats.mac_etype_used, stats.etype_used,
5583                          stats.mac_etype_free, stats.etype_free);
5584         if (ret < 0)
5585                 return -ENOSYS;
5586         return 0;
5587 }
5588
5589 /*
5590  * Handle operations for ethertype filter.
5591  */
5592 static int
5593 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5594                                 enum rte_filter_op filter_op,
5595                                 void *arg)
5596 {
5597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5598         int ret = 0;
5599
5600         if (filter_op == RTE_ETH_FILTER_NOP)
5601                 return ret;
5602
5603         if (arg == NULL) {
5604                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5605                             filter_op);
5606                 return -EINVAL;
5607         }
5608
5609         switch (filter_op) {
5610         case RTE_ETH_FILTER_ADD:
5611                 ret = i40e_ethertype_filter_set(pf,
5612                         (struct rte_eth_ethertype_filter *)arg,
5613                         TRUE);
5614                 break;
5615         case RTE_ETH_FILTER_DELETE:
5616                 ret = i40e_ethertype_filter_set(pf,
5617                         (struct rte_eth_ethertype_filter *)arg,
5618                         FALSE);
5619                 break;
5620         default:
5621                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5622                 ret = -ENOSYS;
5623                 break;
5624         }
5625         return ret;
5626 }
5627
5628 static int
5629 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5630                      enum rte_filter_type filter_type,
5631                      enum rte_filter_op filter_op,
5632                      void *arg)
5633 {
5634         int ret = 0;
5635
5636         if (dev == NULL)
5637                 return -EINVAL;
5638
5639         switch (filter_type) {
5640         case RTE_ETH_FILTER_HASH:
5641                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5642                 break;
5643         case RTE_ETH_FILTER_MACVLAN:
5644                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5645                 break;
5646         case RTE_ETH_FILTER_ETHERTYPE:
5647                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5648                 break;
5649         case RTE_ETH_FILTER_TUNNEL:
5650                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5651                 break;
5652         case RTE_ETH_FILTER_FDIR:
5653                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5654                 break;
5655         default:
5656                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5657                                                         filter_type);
5658                 ret = -EINVAL;
5659                 break;
5660         }
5661
5662         return ret;
5663 }
5664
5665 /*
5666  * As some registers wouldn't be reset unless a global hardware reset,
5667  * hardware initialization is needed to put those registers into an
5668  * expected initial state.
5669  */
5670 static void
5671 i40e_hw_init(struct i40e_hw *hw)
5672 {
5673         /* clear the PF Queue Filter control register */
5674         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5675
5676         /* Disable symmetric hash per port */
5677         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5678 }
5679
5680 enum i40e_filter_pctype
5681 i40e_flowtype_to_pctype(uint16_t flow_type)
5682 {
5683         static const enum i40e_filter_pctype pctype_table[] = {
5684                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5685                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5686                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5687                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5688                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5689                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5690                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5691                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5692                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5693                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5694                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5695                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5696                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5697                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5698                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5699                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5700                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5701                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5702                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5703         };
5704
5705         return pctype_table[flow_type];
5706 }
5707
5708 uint16_t
5709 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5710 {
5711         static const uint16_t flowtype_table[] = {
5712                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5713                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5714                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5715                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5716                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5717                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5718                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5719                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5720                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5721                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5722                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5723                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5724                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5725                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5726                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5727                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5728                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5729                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5730                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5731         };
5732
5733         return flowtype_table[pctype];
5734 }
5735
5736 /*
5737  * On X710, performance number is far from the expectation on recent firmware
5738  * versions; on XL710, performance number is also far from the expectation on
5739  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5740  * mode is enabled and port MAC address is equal to the packet destination MAC
5741  * address. The fix for this issue may not be integrated in the following
5742  * firmware version. So the workaround in software driver is needed. It needs
5743  * to modify the initial values of 3 internal only registers for both X710 and
5744  * XL710. Note that the values for X710 or XL710 could be different, and the
5745  * workaround can be removed when it is fixed in firmware in the future.
5746  */
5747
5748 /* For both X710 and XL710 */
5749 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5750 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5751
5752 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5753 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5754
5755 /* For X710 */
5756 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5757 /* For XL710 */
5758 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5759 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5760
5761 static void
5762 i40e_configure_registers(struct i40e_hw *hw)
5763 {
5764         static struct {
5765                 uint32_t addr;
5766                 uint64_t val;
5767         } reg_table[] = {
5768                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5769                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5770                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5771         };
5772         uint64_t reg;
5773         uint32_t i;
5774         int ret;
5775
5776         for (i = 0; i < RTE_DIM(reg_table); i++) {
5777                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5778                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5779                                 reg_table[i].val =
5780                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5781                         else /* For X710 */
5782                                 reg_table[i].val =
5783                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5784                 }
5785
5786                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5787                                                         &reg, NULL);
5788                 if (ret < 0) {
5789                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5790                                                         reg_table[i].addr);
5791                         break;
5792                 }
5793                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5794                                                 reg_table[i].addr, reg);
5795                 if (reg == reg_table[i].val)
5796                         continue;
5797
5798                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5799                                                 reg_table[i].val, NULL);
5800                 if (ret < 0) {
5801                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5802                                 "address of 0x%"PRIx32, reg_table[i].val,
5803                                                         reg_table[i].addr);
5804                         break;
5805                 }
5806                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
5807                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
5808         }
5809 }
5810
5811 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
5812 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
5813 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
5814 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
5815 static int
5816 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
5817 {
5818         uint32_t reg;
5819         int ret;
5820
5821         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
5822                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
5823                 return -EINVAL;
5824         }
5825
5826         /* Configure for double VLAN RX stripping */
5827         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
5828         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
5829                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
5830                 ret = i40e_aq_debug_write_register(hw,
5831                                                    I40E_VSI_TSR(vsi->vsi_id),
5832                                                    reg, NULL);
5833                 if (ret < 0) {
5834                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
5835                                     vsi->vsi_id);
5836                         return I40E_ERR_CONFIG;
5837                 }
5838         }
5839
5840         /* Configure for double VLAN TX insertion */
5841         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
5842         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
5843                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
5844                 ret = i40e_aq_debug_write_register(hw,
5845                                                    I40E_VSI_L2TAGSTXVALID(
5846                                                    vsi->vsi_id), reg, NULL);
5847                 if (ret < 0) {
5848                         PMD_DRV_LOG(ERR, "Failed to update "
5849                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
5850                         return I40E_ERR_CONFIG;
5851                 }
5852         }
5853
5854         return 0;
5855 }
5856
5857 /**
5858  * i40e_aq_add_mirror_rule
5859  * @hw: pointer to the hardware structure
5860  * @seid: VEB seid to add mirror rule to
5861  * @dst_id: destination vsi seid
5862  * @entries: Buffer which contains the entities to be mirrored
5863  * @count: number of entities contained in the buffer
5864  * @rule_id:the rule_id of the rule to be added
5865  *
5866  * Add a mirror rule for a given veb.
5867  *
5868  **/
5869 static enum i40e_status_code
5870 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
5871                         uint16_t seid, uint16_t dst_id,
5872                         uint16_t rule_type, uint16_t *entries,
5873                         uint16_t count, uint16_t *rule_id)
5874 {
5875         struct i40e_aq_desc desc;
5876         struct i40e_aqc_add_delete_mirror_rule cmd;
5877         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
5878                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
5879                 &desc.params.raw;
5880         uint16_t buff_len;
5881         enum i40e_status_code status;
5882
5883         i40e_fill_default_direct_cmd_desc(&desc,
5884                                           i40e_aqc_opc_add_mirror_rule);
5885         memset(&cmd, 0, sizeof(cmd));
5886
5887         buff_len = sizeof(uint16_t) * count;
5888         desc.datalen = rte_cpu_to_le_16(buff_len);
5889         if (buff_len > 0)
5890                 desc.flags |= rte_cpu_to_le_16(
5891                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5892         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5893                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5894         cmd.num_entries = rte_cpu_to_le_16(count);
5895         cmd.seid = rte_cpu_to_le_16(seid);
5896         cmd.destination = rte_cpu_to_le_16(dst_id);
5897
5898         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5899         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
5900         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
5901                          "rule_id = %u"
5902                          " mirror_rules_used = %u, mirror_rules_free = %u,",
5903                          hw->aq.asq_last_status, resp->rule_id,
5904                          resp->mirror_rules_used, resp->mirror_rules_free);
5905         *rule_id = rte_le_to_cpu_16(resp->rule_id);
5906
5907         return status;
5908 }
5909
5910 /**
5911  * i40e_aq_del_mirror_rule
5912  * @hw: pointer to the hardware structure
5913  * @seid: VEB seid to add mirror rule to
5914  * @entries: Buffer which contains the entities to be mirrored
5915  * @count: number of entities contained in the buffer
5916  * @rule_id:the rule_id of the rule to be delete
5917  *
5918  * Delete a mirror rule for a given veb.
5919  *
5920  **/
5921 static enum i40e_status_code
5922 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
5923                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
5924                 uint16_t count, uint16_t rule_id)
5925 {
5926         struct i40e_aq_desc desc;
5927         struct i40e_aqc_add_delete_mirror_rule cmd;
5928         uint16_t buff_len = 0;
5929         enum i40e_status_code status;
5930         void *buff = NULL;
5931
5932         i40e_fill_default_direct_cmd_desc(&desc,
5933                                           i40e_aqc_opc_delete_mirror_rule);
5934         memset(&cmd, 0, sizeof(cmd));
5935         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
5936                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
5937                                                           I40E_AQ_FLAG_RD));
5938                 cmd.num_entries = count;
5939                 buff_len = sizeof(uint16_t) * count;
5940                 desc.datalen = rte_cpu_to_le_16(buff_len);
5941                 buff = (void *)entries;
5942         } else
5943                 /* rule id is filled in destination field for deleting mirror rule */
5944                 cmd.destination = rte_cpu_to_le_16(rule_id);
5945
5946         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
5947                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
5948         cmd.seid = rte_cpu_to_le_16(seid);
5949
5950         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
5951         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
5952
5953         return status;
5954 }
5955
5956 /**
5957  * i40e_mirror_rule_set
5958  * @dev: pointer to the hardware structure
5959  * @mirror_conf: mirror rule info
5960  * @sw_id: mirror rule's sw_id
5961  * @on: enable/disable
5962  *
5963  * set a mirror rule.
5964  *
5965  **/
5966 static int
5967 i40e_mirror_rule_set(struct rte_eth_dev *dev,
5968                         struct rte_eth_mirror_conf *mirror_conf,
5969                         uint8_t sw_id, uint8_t on)
5970 {
5971         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5973         struct i40e_mirror_rule *it, *mirr_rule = NULL;
5974         struct i40e_mirror_rule *parent = NULL;
5975         uint16_t seid, dst_seid, rule_id;
5976         uint16_t i, j = 0;
5977         int ret;
5978
5979         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
5980
5981         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
5982                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
5983                         " without veb or vfs.");
5984                 return -ENOSYS;
5985         }
5986         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
5987                 PMD_DRV_LOG(ERR, "mirror table is full.");
5988                 return -ENOSPC;
5989         }
5990         if (mirror_conf->dst_pool > pf->vf_num) {
5991                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
5992                                  mirror_conf->dst_pool);
5993                 return -EINVAL;
5994         }
5995
5996         seid = pf->main_vsi->veb->seid;
5997
5998         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
5999                 if (sw_id <= it->index) {
6000                         mirr_rule = it;
6001                         break;
6002                 }
6003                 parent = it;
6004         }
6005         if (mirr_rule && sw_id == mirr_rule->index) {
6006                 if (on) {
6007                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6008                         return -EEXIST;
6009                 } else {
6010                         ret = i40e_aq_del_mirror_rule(hw, seid,
6011                                         mirr_rule->rule_type,
6012                                         mirr_rule->entries,
6013                                         mirr_rule->num_entries, mirr_rule->id);
6014                         if (ret < 0) {
6015                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6016                                                    " ret = %d, aq_err = %d.",
6017                                                    ret, hw->aq.asq_last_status);
6018                                 return -ENOSYS;
6019                         }
6020                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6021                         rte_free(mirr_rule);
6022                         pf->nb_mirror_rule--;
6023                         return 0;
6024                 }
6025         } else if (!on) {
6026                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6027                 return -ENOENT;
6028         }
6029
6030         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6031                                 sizeof(struct i40e_mirror_rule) , 0);
6032         if (!mirr_rule) {
6033                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6034                 return I40E_ERR_NO_MEMORY;
6035         }
6036         switch (mirror_conf->rule_type) {
6037         case ETH_MIRROR_VLAN:
6038                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6039                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6040                                 mirr_rule->entries[j] =
6041                                         mirror_conf->vlan.vlan_id[i];
6042                                 j++;
6043                         }
6044                 }
6045                 if (j == 0) {
6046                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6047                         rte_free(mirr_rule);
6048                         return -EINVAL;
6049                 }
6050                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6051                 break;
6052         case ETH_MIRROR_VIRTUAL_POOL_UP:
6053         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6054                 /* check if the specified pool bit is out of range */
6055                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6056                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6057                         rte_free(mirr_rule);
6058                         return -EINVAL;
6059                 }
6060                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6061                         if (mirror_conf->pool_mask & (1ULL << i)) {
6062                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6063                                 j++;
6064                         }
6065                 }
6066                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6067                         /* add pf vsi to entries */
6068                         mirr_rule->entries[j] = pf->main_vsi_seid;
6069                         j++;
6070                 }
6071                 if (j == 0) {
6072                         PMD_DRV_LOG(ERR, "pool is not specified.");
6073                         rte_free(mirr_rule);
6074                         return -EINVAL;
6075                 }
6076                 /* egress and ingress in aq commands means from switch but not port */
6077                 mirr_rule->rule_type =
6078                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6079                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6080                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6081                 break;
6082         case ETH_MIRROR_UPLINK_PORT:
6083                 /* egress and ingress in aq commands means from switch but not port*/
6084                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6085                 break;
6086         case ETH_MIRROR_DOWNLINK_PORT:
6087                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6088                 break;
6089         default:
6090                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6091                         mirror_conf->rule_type);
6092                 rte_free(mirr_rule);
6093                 return -EINVAL;
6094         }
6095
6096         /* If the dst_pool is equal to vf_num, consider it as PF */
6097         if (mirror_conf->dst_pool == pf->vf_num)
6098                 dst_seid = pf->main_vsi_seid;
6099         else
6100                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6101
6102         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6103                                       mirr_rule->rule_type, mirr_rule->entries,
6104                                       j, &rule_id);
6105         if (ret < 0) {
6106                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6107                                    " ret = %d, aq_err = %d.",
6108                                    ret, hw->aq.asq_last_status);
6109                 rte_free(mirr_rule);
6110                 return -ENOSYS;
6111         }
6112
6113         mirr_rule->index = sw_id;
6114         mirr_rule->num_entries = j;
6115         mirr_rule->id = rule_id;
6116         mirr_rule->dst_vsi_seid = dst_seid;
6117
6118         if (parent)
6119                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6120         else
6121                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6122
6123         pf->nb_mirror_rule++;
6124         return 0;
6125 }
6126
6127 /**
6128  * i40e_mirror_rule_reset
6129  * @dev: pointer to the device
6130  * @sw_id: mirror rule's sw_id
6131  *
6132  * reset a mirror rule.
6133  *
6134  **/
6135 static int
6136 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6137 {
6138         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6140         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6141         uint16_t seid;
6142         int ret;
6143
6144         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6145
6146         seid = pf->main_vsi->veb->seid;
6147
6148         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6149                 if (sw_id == it->index) {
6150                         mirr_rule = it;
6151                         break;
6152                 }
6153         }
6154         if (mirr_rule) {
6155                 ret = i40e_aq_del_mirror_rule(hw, seid,
6156                                 mirr_rule->rule_type,
6157                                 mirr_rule->entries,
6158                                 mirr_rule->num_entries, mirr_rule->id);
6159                 if (ret < 0) {
6160                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6161                                            " status = %d, aq_err = %d.",
6162                                            ret, hw->aq.asq_last_status);
6163                         return -ENOSYS;
6164                 }
6165                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6166                 rte_free(mirr_rule);
6167                 pf->nb_mirror_rule--;
6168         } else {
6169                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6170                 return -ENOENT;
6171         }
6172         return 0;
6173 }
6174
6175 static int
6176 i40e_timesync_enable(struct rte_eth_dev *dev)
6177 {
6178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6179         struct rte_eth_link *link = &dev->data->dev_link;
6180         uint32_t tsync_ctl_l;
6181         uint32_t tsync_ctl_h;
6182         uint32_t tsync_inc_l;
6183         uint32_t tsync_inc_h;
6184
6185         switch (link->link_speed) {
6186         case ETH_LINK_SPEED_40G:
6187                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6188                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6189                 break;
6190         case ETH_LINK_SPEED_10G:
6191                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6192                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6193                 break;
6194         case ETH_LINK_SPEED_1000:
6195                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6196                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6197                 break;
6198         default:
6199                 tsync_inc_l = 0x0;
6200                 tsync_inc_h = 0x0;
6201         }
6202
6203         /* Clear timesync registers. */
6204         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6205         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6206         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6207         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6208         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6209         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6210         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6211
6212         /* Set the timesync increment value. */
6213         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6214         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6215
6216         /* Enable timestamping of PTP packets. */
6217         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6218         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6219
6220         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6221         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6222         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6223
6224         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6225         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6226
6227         return 0;
6228 }
6229
6230 static int
6231 i40e_timesync_disable(struct rte_eth_dev *dev)
6232 {
6233         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6234         uint32_t tsync_ctl_l;
6235         uint32_t tsync_ctl_h;
6236
6237         /* Disable timestamping of transmitted PTP packets. */
6238         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6239         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6240
6241         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6242         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6243
6244         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6245         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6246
6247         /* Set the timesync increment value. */
6248         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6249         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6250
6251         return 0;
6252 }
6253
6254 static int
6255 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6256                                 struct timespec *timestamp, uint32_t flags)
6257 {
6258         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6259         uint32_t sync_status;
6260         uint32_t rx_stmpl;
6261         uint32_t rx_stmph;
6262         uint32_t index = flags & 0x03;
6263
6264         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6265         if ((sync_status & (1 << index)) == 0)
6266                 return -EINVAL;
6267
6268         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6269         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6270
6271         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6272         timestamp->tv_nsec = 0;
6273
6274         return  0;
6275 }
6276
6277 static int
6278 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6279                                 struct timespec *timestamp)
6280 {
6281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6282         uint32_t sync_status;
6283         uint32_t tx_stmpl;
6284         uint32_t tx_stmph;
6285
6286         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6287         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6288                 return -EINVAL;
6289
6290         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6291         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6292
6293         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6294         timestamp->tv_nsec = 0;
6295
6296         return  0;
6297 }