drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* Source IPv4 address for X722 */
 215 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 216 /* Destination IPv4 address for X722 */
 217 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 218 /* IPv4 Protocol for X722 */
 219 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 220 /* IPv4 Time to Live for X722 */
 221 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 222 /* IPv4 Type of Service (TOS) */
 223 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 224 /* IPv4 Protocol */
 225 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 226 /* IPv4 Time to Live */
 227 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 228 /* Source IPv6 address */
 229 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 230 /* Destination IPv6 address */
 231 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 232 /* IPv6 Traffic Class (TC) */
 233 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 234 /* IPv6 Next Header */
 235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 236 /* IPv6 Hop Limit */
 237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 238 /* Source L4 port */
 239 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 240 /* Destination L4 port */
 241 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 242 /* SCTP verification tag */
 243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 246 /* Source port of tunneling UDP */
 247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 248 /* Destination port of tunneling UDP */
 249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 250 /* UDP Tunneling ID, NVGRE/GRE key */
 251 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 252 /* Last ether type */
 253 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 254 /* Tunneling outer destination IPv4 address */
 255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 256 /* Tunneling outer destination IPv6 address */
 257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 258 /* 1st word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 260 /* 2nd word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 262 /* 3rd word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 264 /* 4th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 266 /* 5th word of flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 268 /* 6th word of flex payload */
 269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 270 /* 7th word of flex payload */
 271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 272 /* 8th word of flex payload */
 273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 274 /* all 8 words flex payload */
 275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 276 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 277
 278 #define I40E_TRANSLATE_INSET 0
 279 #define I40E_TRANSLATE_REG   1
 280
 281 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 282 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 283 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 284 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 286 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 287
 288 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 291         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 292
 293 /* PCI offset for querying capability */
 294 #define PCI_DEV_CAP_REG            0xA4
 295 /* PCI offset for enabling/disabling Extended Tag */
 296 #define PCI_DEV_CTRL_REG           0xA8
 297 /* Bit mask of Extended Tag capability */
 298 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 299 /* Bit shift of Extended Tag enable/disable */
 300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 301 /* Bit mask of Extended Tag enable/disable */
 302 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 303
 304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 306 static int i40e_dev_configure(struct rte_eth_dev *dev);
 307 static int i40e_dev_start(struct rte_eth_dev *dev);
 308 static void i40e_dev_stop(struct rte_eth_dev *dev);
 309 static void i40e_dev_close(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 317                                struct rte_eth_stats *stats);
 318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 319                                struct rte_eth_xstat *xstats, unsigned n);
 320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 321                                      struct rte_eth_xstat_name *xstats_names,
 322                                      unsigned limit);
 323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 325                                             uint16_t queue_id,
 326                                             uint8_t stat_idx,
 327                                             uint8_t is_rx);
 328 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 329                                 char *fw_version, size_t fw_size);
 330 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 331                               struct rte_eth_dev_info *dev_info);
 332 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 333                                 uint16_t vlan_id,
 334                                 int on);
 335 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 336                               enum rte_vlan_type vlan_type,
 337                               uint16_t tpid);
 338 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 339 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 340                                       uint16_t queue,
 341                                       int on);
 342 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 343 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 344 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 345 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 346                               struct rte_eth_fc_conf *fc_conf);
 347 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 348                               struct rte_eth_fc_conf *fc_conf);
 349 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 350                                        struct rte_eth_pfc_conf *pfc_conf);
 351 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 352                           struct ether_addr *mac_addr,
 353                           uint32_t index,
 354                           uint32_t pool);
 355 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 356 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 357                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                     uint16_t reta_size);
 359 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 360                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 361                                    uint16_t reta_size);
 362
 363 static int i40e_get_cap(struct i40e_hw *hw);
 364 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 365 static int i40e_pf_setup(struct i40e_pf *pf);
 366 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 367 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 368 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 369 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 370 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 371                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 372 static void i40e_stat_update_48(struct i40e_hw *hw,
 373                                uint32_t hireg,
 374                                uint32_t loreg,
 375                                bool offset_loaded,
 376                                uint64_t *offset,
 377                                uint64_t *stat);
 378 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 379 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                        void *param);
 381 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 382                                 uint32_t base, uint32_t num);
 383 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 384 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 385                         uint32_t base);
 386 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 387                         uint16_t num);
 388 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 389 static int i40e_veb_release(struct i40e_veb *veb);
 390 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 391                                                 struct i40e_vsi *vsi);
 392 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 393 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 394 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 395                                              struct i40e_macvlan_filter *mv_f,
 396                                              int num,
 397                                              struct ether_addr *addr);
 398 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 399                                              struct i40e_macvlan_filter *mv_f,
 400                                              int num,
 401                                              uint16_t vlan);
 402 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 403 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 404                                     struct rte_eth_rss_conf *rss_conf);
 405 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 406                                       struct rte_eth_rss_conf *rss_conf);
 407 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 408                                         struct rte_eth_udp_tunnel *udp_tunnel);
 409 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 410                                         struct rte_eth_udp_tunnel *udp_tunnel);
 411 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 412 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 413                         struct rte_eth_ethertype_filter *filter,
 414                         bool add);
 415 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 416                                 enum rte_filter_op filter_op,
 417                                 void *arg);
 418 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 419                                 enum rte_filter_type filter_type,
 420                                 enum rte_filter_op filter_op,
 421                                 void *arg);
 422 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 423                                   struct rte_eth_dcb_info *dcb_info);
 424 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 425 static void i40e_configure_registers(struct i40e_hw *hw);
 426 static void i40e_hw_init(struct rte_eth_dev *dev);
 427 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 428 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 429                         struct rte_eth_mirror_conf *mirror_conf,
 430                         uint8_t sw_id, uint8_t on);
 431 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 432
 433 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 434 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 435 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp,
 437                                            uint32_t flags);
 438 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp);
 440 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 441
 442 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 443
 444 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 445                                    struct timespec *timestamp);
 446 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 447                                     const struct timespec *timestamp);
 448
 449 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 450                                          uint16_t queue_id);
 451 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 452                                           uint16_t queue_id);
 453
 454 static int i40e_get_regs(struct rte_eth_dev *dev,
 455                          struct rte_dev_reg_info *regs);
 456
 457 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 458
 459 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 460                            struct rte_dev_eeprom_info *eeprom);
 461
 462 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 463                                       struct ether_addr *mac_addr);
 464
 465 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 466
 467 static int i40e_ethertype_filter_convert(
 468         const struct rte_eth_ethertype_filter *input,
 469         struct i40e_ethertype_filter *filter);
 470 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 471                                    struct i40e_ethertype_filter *filter);
 472
 473 static int i40e_tunnel_filter_convert(
 474         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 475         struct i40e_tunnel_filter *tunnel_filter);
 476 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 477                                 struct i40e_tunnel_filter *tunnel_filter);
 478
 479 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 480 static void i40e_filter_restore(struct i40e_pf *pf);
 481
 482 static const struct rte_pci_id pci_id_i40e_map[] = {
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 492         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 493         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 494         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 495         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 496         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 497         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 498         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 499         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 500         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 501         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 502         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct eth_dev_ops i40e_eth_dev_ops = {
 507         .dev_configure                = i40e_dev_configure,
 508         .dev_start                    = i40e_dev_start,
 509         .dev_stop                     = i40e_dev_stop,
 510         .dev_close                    = i40e_dev_close,
 511         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 512         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 513         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 514         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 515         .dev_set_link_up              = i40e_dev_set_link_up,
 516         .dev_set_link_down            = i40e_dev_set_link_down,
 517         .link_update                  = i40e_dev_link_update,
 518         .stats_get                    = i40e_dev_stats_get,
 519         .xstats_get                   = i40e_dev_xstats_get,
 520         .xstats_get_names             = i40e_dev_xstats_get_names,
 521         .stats_reset                  = i40e_dev_stats_reset,
 522         .xstats_reset                 = i40e_dev_stats_reset,
 523         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 524         .fw_version_get               = i40e_fw_version_get,
 525         .dev_infos_get                = i40e_dev_info_get,
 526         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 527         .vlan_filter_set              = i40e_vlan_filter_set,
 528         .vlan_tpid_set                = i40e_vlan_tpid_set,
 529         .vlan_offload_set             = i40e_vlan_offload_set,
 530         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 531         .vlan_pvid_set                = i40e_vlan_pvid_set,
 532         .rx_queue_start               = i40e_dev_rx_queue_start,
 533         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 534         .tx_queue_start               = i40e_dev_tx_queue_start,
 535         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 536         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 537         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 538         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 539         .rx_queue_release             = i40e_dev_rx_queue_release,
 540         .rx_queue_count               = i40e_dev_rx_queue_count,
 541         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 542         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 543         .tx_queue_release             = i40e_dev_tx_queue_release,
 544         .dev_led_on                   = i40e_dev_led_on,
 545         .dev_led_off                  = i40e_dev_led_off,
 546         .flow_ctrl_get                = i40e_flow_ctrl_get,
 547         .flow_ctrl_set                = i40e_flow_ctrl_set,
 548         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 549         .mac_addr_add                 = i40e_macaddr_add,
 550         .mac_addr_remove              = i40e_macaddr_remove,
 551         .reta_update                  = i40e_dev_rss_reta_update,
 552         .reta_query                   = i40e_dev_rss_reta_query,
 553         .rss_hash_update              = i40e_dev_rss_hash_update,
 554         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 555         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 556         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 557         .filter_ctrl                  = i40e_dev_filter_ctrl,
 558         .rxq_info_get                 = i40e_rxq_info_get,
 559         .txq_info_get                 = i40e_txq_info_get,
 560         .mirror_rule_set              = i40e_mirror_rule_set,
 561         .mirror_rule_reset            = i40e_mirror_rule_reset,
 562         .timesync_enable              = i40e_timesync_enable,
 563         .timesync_disable             = i40e_timesync_disable,
 564         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 565         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 566         .get_dcb_info                 = i40e_dev_get_dcb_info,
 567         .timesync_adjust_time         = i40e_timesync_adjust_time,
 568         .timesync_read_time           = i40e_timesync_read_time,
 569         .timesync_write_time          = i40e_timesync_write_time,
 570         .get_reg                      = i40e_get_regs,
 571         .get_eeprom_length            = i40e_get_eeprom_length,
 572         .get_eeprom                   = i40e_get_eeprom,
 573         .mac_addr_set                 = i40e_set_default_mac_addr,
 574         .mtu_set                      = i40e_dev_mtu_set,
 575 };
 576
 577 /* store statistics names and its offset in stats structure */
 578 struct rte_i40e_xstats_name_off {
 579         char name[RTE_ETH_XSTATS_NAME_SIZE];
 580         unsigned offset;
 581 };
 582
 583 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 584         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 585         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 586         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 587         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 588         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 589                 rx_unknown_protocol)},
 590         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 591         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 592         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 593         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 594 };
 595
 596 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 597                 sizeof(rte_i40e_stats_strings[0]))
 598
 599 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 600         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 601                 tx_dropped_link_down)},
 602         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 603         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 604                 illegal_bytes)},
 605         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 606         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 607                 mac_local_faults)},
 608         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 609                 mac_remote_faults)},
 610         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 611                 rx_length_errors)},
 612         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 613         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 614         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 615         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 616         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 617         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 618                 rx_size_127)},
 619         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 620                 rx_size_255)},
 621         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 622                 rx_size_511)},
 623         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 624                 rx_size_1023)},
 625         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 626                 rx_size_1522)},
 627         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 628                 rx_size_big)},
 629         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 630                 rx_undersize)},
 631         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 632                 rx_oversize)},
 633         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 634                 mac_short_packet_dropped)},
 635         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 636                 rx_fragments)},
 637         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 638         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 639         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 640                 tx_size_127)},
 641         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 642                 tx_size_255)},
 643         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 644                 tx_size_511)},
 645         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 646                 tx_size_1023)},
 647         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 648                 tx_size_1522)},
 649         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 650                 tx_size_big)},
 651         {"rx_flow_director_atr_match_packets",
 652                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 653         {"rx_flow_director_sb_match_packets",
 654                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 655         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 656                 tx_lpi_status)},
 657         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 658                 rx_lpi_status)},
 659         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 660                 tx_lpi_count)},
 661         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 662                 rx_lpi_count)},
 663 };
 664
 665 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 666                 sizeof(rte_i40e_hw_port_strings[0]))
 667
 668 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 669         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 670                 priority_xon_rx)},
 671         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 672                 priority_xoff_rx)},
 673 };
 674
 675 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 676                 sizeof(rte_i40e_rxq_prio_strings[0]))
 677
 678 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 679         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 680                 priority_xon_tx)},
 681         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 682                 priority_xoff_tx)},
 683         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 684                 priority_xon_2_xoff)},
 685 };
 686
 687 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 688                 sizeof(rte_i40e_txq_prio_strings[0]))
 689
 690 static struct eth_driver rte_i40e_pmd = {
 691         .pci_drv = {
 692                 .id_table = pci_id_i40e_map,
 693                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 694                 .probe = rte_eth_dev_pci_probe,
 695                 .remove = rte_eth_dev_pci_remove,
 696         },
 697         .eth_dev_init = eth_i40e_dev_init,
 698         .eth_dev_uninit = eth_i40e_dev_uninit,
 699         .dev_private_size = sizeof(struct i40e_adapter),
 700 };
 701
 702 static inline int
 703 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 704                                      struct rte_eth_link *link)
 705 {
 706         struct rte_eth_link *dst = link;
 707         struct rte_eth_link *src = &(dev->data->dev_link);
 708
 709         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 710                                         *(uint64_t *)src) == 0)
 711                 return -1;
 712
 713         return 0;
 714 }
 715
 716 static inline int
 717 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 718                                       struct rte_eth_link *link)
 719 {
 720         struct rte_eth_link *dst = &(dev->data->dev_link);
 721         struct rte_eth_link *src = link;
 722
 723         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 724                                         *(uint64_t *)src) == 0)
 725                 return -1;
 726
 727         return 0;
 728 }
 729
 730 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 731 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 732 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 733
 734 #ifndef I40E_GLQF_ORT
 735 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 736 #endif
 737 #ifndef I40E_GLQF_PIT
 738 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 739 #endif
 740
 741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 742 {
 743         /*
 744          * Initialize registers for flexible payload, which should be set by NVM.
 745          * This should be removed from code once it is fixed in NVM.
 746          */
 747         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 750         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 751         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 752         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 753         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 754         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 755         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 756         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 757         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 758         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 759
 760         /* Initialize registers for parsing packet type of QinQ */
 761         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 762         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 763 }
 764
 765 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 766
 767 /*
 768  * Add a ethertype filter to drop all flow control frames transmitted
 769  * from VSIs.
 770 */
 771 static void
 772 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 773 {
 774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 775         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 776                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 778         int ret;
 779
 780         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 781                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 782                                 pf->main_vsi_seid, 0,
 783                                 TRUE, NULL, NULL);
 784         if (ret)
 785                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 786                                   " frames from VSIs.");
 787 }
 788
 789 static int
 790 floating_veb_list_handler(__rte_unused const char *key,
 791                           const char *floating_veb_value,
 792                           void *opaque)
 793 {
 794         int idx = 0;
 795         unsigned int count = 0;
 796         char *end = NULL;
 797         int min, max;
 798         bool *vf_floating_veb = opaque;
 799
 800         while (isblank(*floating_veb_value))
 801                 floating_veb_value++;
 802
 803         /* Reset floating VEB configuration for VFs */
 804         for (idx = 0; idx < I40E_MAX_VF; idx++)
 805                 vf_floating_veb[idx] = false;
 806
 807         min = I40E_MAX_VF;
 808         do {
 809                 while (isblank(*floating_veb_value))
 810                         floating_veb_value++;
 811                 if (*floating_veb_value == '\0')
 812                         return -1;
 813                 errno = 0;
 814                 idx = strtoul(floating_veb_value, &end, 10);
 815                 if (errno || end == NULL)
 816                         return -1;
 817                 while (isblank(*end))
 818                         end++;
 819                 if (*end == '-') {
 820                         min = idx;
 821                 } else if ((*end == ';') || (*end == '\0')) {
 822                         max = idx;
 823                         if (min == I40E_MAX_VF)
 824                                 min = idx;
 825                         if (max >= I40E_MAX_VF)
 826                                 max = I40E_MAX_VF - 1;
 827                         for (idx = min; idx <= max; idx++) {
 828                                 vf_floating_veb[idx] = true;
 829                                 count++;
 830                         }
 831                         min = I40E_MAX_VF;
 832                 } else {
 833                         return -1;
 834                 }
 835                 floating_veb_value = end + 1;
 836         } while (*end != '\0');
 837
 838         if (count == 0)
 839                 return -1;
 840
 841         return 0;
 842 }
 843
 844 static void
 845 config_vf_floating_veb(struct rte_devargs *devargs,
 846                        uint16_t floating_veb,
 847                        bool *vf_floating_veb)
 848 {
 849         struct rte_kvargs *kvlist;
 850         int i;
 851         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 852
 853         if (!floating_veb)
 854                 return;
 855         /* All the VFs attach to the floating VEB by default
 856          * when the floating VEB is enabled.
 857          */
 858         for (i = 0; i < I40E_MAX_VF; i++)
 859                 vf_floating_veb[i] = true;
 860
 861         if (devargs == NULL)
 862                 return;
 863
 864         kvlist = rte_kvargs_parse(devargs->args, NULL);
 865         if (kvlist == NULL)
 866                 return;
 867
 868         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 869                 rte_kvargs_free(kvlist);
 870                 return;
 871         }
 872         /* When the floating_veb_list parameter exists, all the VFs
 873          * will attach to the legacy VEB firstly, then configure VFs
 874          * to the floating VEB according to the floating_veb_list.
 875          */
 876         if (rte_kvargs_process(kvlist, floating_veb_list,
 877                                floating_veb_list_handler,
 878                                vf_floating_veb) < 0) {
 879                 rte_kvargs_free(kvlist);
 880                 return;
 881         }
 882         rte_kvargs_free(kvlist);
 883 }
 884
 885 static int
 886 i40e_check_floating_handler(__rte_unused const char *key,
 887                             const char *value,
 888                             __rte_unused void *opaque)
 889 {
 890         if (strcmp(value, "1"))
 891                 return -1;
 892
 893         return 0;
 894 }
 895
 896 static int
 897 is_floating_veb_supported(struct rte_devargs *devargs)
 898 {
 899         struct rte_kvargs *kvlist;
 900         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 901
 902         if (devargs == NULL)
 903                 return 0;
 904
 905         kvlist = rte_kvargs_parse(devargs->args, NULL);
 906         if (kvlist == NULL)
 907                 return 0;
 908
 909         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 910                 rte_kvargs_free(kvlist);
 911                 return 0;
 912         }
 913         /* Floating VEB is enabled when there's key-value:
 914          * enable_floating_veb=1
 915          */
 916         if (rte_kvargs_process(kvlist, floating_veb_key,
 917                                i40e_check_floating_handler, NULL) < 0) {
 918                 rte_kvargs_free(kvlist);
 919                 return 0;
 920         }
 921         rte_kvargs_free(kvlist);
 922
 923         return 1;
 924 }
 925
 926 static void
 927 config_floating_veb(struct rte_eth_dev *dev)
 928 {
 929         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932
 933         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 934
 935         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 936                 pf->floating_veb =
 937                         is_floating_veb_supported(pci_dev->device.devargs);
 938                 config_vf_floating_veb(pci_dev->device.devargs,
 939                                        pf->floating_veb,
 940                                        pf->floating_veb_list);
 941         } else {
 942                 pf->floating_veb = false;
 943         }
 944 }
 945
 946 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 947 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 948
 949 static int
 950 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 951 {
 952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 953         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 954         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 955         int ret;
 956
 957         struct rte_hash_parameters ethertype_hash_params = {
 958                 .name = ethertype_hash_name,
 959                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 960                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 961                 .hash_func = rte_hash_crc,
 962         };
 963
 964         /* Initialize ethertype filter rule list and hash */
 965         TAILQ_INIT(&ethertype_rule->ethertype_list);
 966         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 967                  "ethertype_%s", dev->data->name);
 968         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 969         if (!ethertype_rule->hash_table) {
 970                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 971                 return -EINVAL;
 972         }
 973         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 974                                        sizeof(struct i40e_ethertype_filter *) *
 975                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 976                                        0);
 977         if (!ethertype_rule->hash_map) {
 978                 PMD_INIT_LOG(ERR,
 979                              "Failed to allocate memory for ethertype hash map!");
 980                 ret = -ENOMEM;
 981                 goto err_ethertype_hash_map_alloc;
 982         }
 983
 984         return 0;
 985
 986 err_ethertype_hash_map_alloc:
 987         rte_hash_free(ethertype_rule->hash_table);
 988
 989         return ret;
 990 }
 991
 992 static int
 993 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 994 {
 995         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 996         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 997         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 998         int ret;
 999
1000         struct rte_hash_parameters tunnel_hash_params = {
1001                 .name = tunnel_hash_name,
1002                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1003                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1004                 .hash_func = rte_hash_crc,
1005         };
1006
1007         /* Initialize tunnel filter rule list and hash */
1008         TAILQ_INIT(&tunnel_rule->tunnel_list);
1009         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1010                  "tunnel_%s", dev->data->name);
1011         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1012         if (!tunnel_rule->hash_table) {
1013                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1014                 return -EINVAL;
1015         }
1016         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1017                                     sizeof(struct i40e_tunnel_filter *) *
1018                                     I40E_MAX_TUNNEL_FILTER_NUM,
1019                                     0);
1020         if (!tunnel_rule->hash_map) {
1021                 PMD_INIT_LOG(ERR,
1022                              "Failed to allocate memory for tunnel hash map!");
1023                 ret = -ENOMEM;
1024                 goto err_tunnel_hash_map_alloc;
1025         }
1026
1027         return 0;
1028
1029 err_tunnel_hash_map_alloc:
1030         rte_hash_free(tunnel_rule->hash_table);
1031
1032         return ret;
1033 }
1034
1035 static int
1036 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1037 {
1038         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1039         struct i40e_fdir_info *fdir_info = &pf->fdir;
1040         char fdir_hash_name[RTE_HASH_NAMESIZE];
1041         int ret;
1042
1043         struct rte_hash_parameters fdir_hash_params = {
1044                 .name = fdir_hash_name,
1045                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1046                 .key_len = sizeof(struct rte_eth_fdir_input),
1047                 .hash_func = rte_hash_crc,
1048         };
1049
1050         /* Initialize flow director filter rule list and hash */
1051         TAILQ_INIT(&fdir_info->fdir_list);
1052         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1053                  "fdir_%s", dev->data->name);
1054         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1055         if (!fdir_info->hash_table) {
1056                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1057                 return -EINVAL;
1058         }
1059         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1060                                           sizeof(struct i40e_fdir_filter *) *
1061                                           I40E_MAX_FDIR_FILTER_NUM,
1062                                           0);
1063         if (!fdir_info->hash_map) {
1064                 PMD_INIT_LOG(ERR,
1065                              "Failed to allocate memory for fdir hash map!");
1066                 ret = -ENOMEM;
1067                 goto err_fdir_hash_map_alloc;
1068         }
1069         return 0;
1070
1071 err_fdir_hash_map_alloc:
1072         rte_hash_free(fdir_info->hash_table);
1073
1074         return ret;
1075 }
1076
1077 static int
1078 eth_i40e_dev_init(struct rte_eth_dev *dev)
1079 {
1080         struct rte_pci_device *pci_dev;
1081         struct rte_intr_handle *intr_handle;
1082         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1083         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084         struct i40e_vsi *vsi;
1085         int ret;
1086         uint32_t len;
1087         uint8_t aq_fail = 0;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         dev->dev_ops = &i40e_eth_dev_ops;
1092         dev->rx_pkt_burst = i40e_recv_pkts;
1093         dev->tx_pkt_burst = i40e_xmit_pkts;
1094         dev->tx_pkt_prepare = i40e_prep_pkts;
1095
1096         /* for secondary processes, we don't initialise any further as primary
1097          * has already done this work. Only check we don't need a different
1098          * RX function */
1099         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1100                 i40e_set_rx_function(dev);
1101                 i40e_set_tx_function(dev);
1102                 return 0;
1103         }
1104         pci_dev = I40E_DEV_TO_PCI(dev);
1105         intr_handle = &pci_dev->intr_handle;
1106
1107         rte_eth_copy_pci_info(dev, pci_dev);
1108         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1109
1110         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1111         pf->adapter->eth_dev = dev;
1112         pf->dev_data = dev->data;
1113
1114         hw->back = I40E_PF_TO_ADAPTER(pf);
1115         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1116         if (!hw->hw_addr) {
1117                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1118                              "as address is NULL");
1119                 return -ENODEV;
1120         }
1121
1122         hw->vendor_id = pci_dev->id.vendor_id;
1123         hw->device_id = pci_dev->id.device_id;
1124         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1125         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1126         hw->bus.device = pci_dev->addr.devid;
1127         hw->bus.func = pci_dev->addr.function;
1128         hw->adapter_stopped = 0;
1129
1130         /* Make sure all is clean before doing PF reset */
1131         i40e_clear_hw(hw);
1132
1133         /* Initialize the hardware */
1134         i40e_hw_init(dev);
1135
1136         /* Reset here to make sure all is clean for each PF */
1137         ret = i40e_pf_reset(hw);
1138         if (ret) {
1139                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1140                 return ret;
1141         }
1142
1143         /* Initialize the shared code (base driver) */
1144         ret = i40e_init_shared_code(hw);
1145         if (ret) {
1146                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1147                 return ret;
1148         }
1149
1150         /*
1151          * To work around the NVM issue, initialize registers
1152          * for flexible payload and packet type of QinQ by
1153          * software. It should be removed once issues are fixed
1154          * in NVM.
1155          */
1156         i40e_GLQF_reg_init(hw);
1157
1158         /* Initialize the input set for filters (hash and fd) to default value */
1159         i40e_filter_input_set_init(pf);
1160
1161         /* Initialize the parameters for adminq */
1162         i40e_init_adminq_parameter(hw);
1163         ret = i40e_init_adminq(hw);
1164         if (ret != I40E_SUCCESS) {
1165                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1166                 return -EIO;
1167         }
1168         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1169                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1170                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1171                      ((hw->nvm.version >> 12) & 0xf),
1172                      ((hw->nvm.version >> 4) & 0xff),
1173                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1174
1175         /* Need the special FW version to support floating VEB */
1176         config_floating_veb(dev);
1177         /* Clear PXE mode */
1178         i40e_clear_pxe_mode(hw);
1179         ret = i40e_dev_sync_phy_type(hw);
1180         if (ret) {
1181                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1182                 goto err_sync_phy_type;
1183         }
1184         /*
1185          * On X710, performance number is far from the expectation on recent
1186          * firmware versions. The fix for this issue may not be integrated in
1187          * the following firmware version. So the workaround in software driver
1188          * is needed. It needs to modify the initial values of 3 internal only
1189          * registers. Note that the workaround can be removed when it is fixed
1190          * in firmware in the future.
1191          */
1192         i40e_configure_registers(hw);
1193
1194         /* Get hw capabilities */
1195         ret = i40e_get_cap(hw);
1196         if (ret != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1198                 goto err_get_capabilities;
1199         }
1200
1201         /* Initialize parameters for PF */
1202         ret = i40e_pf_parameter_init(dev);
1203         if (ret != 0) {
1204                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1205                 goto err_parameter_init;
1206         }
1207
1208         /* Initialize the queue management */
1209         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1210         if (ret < 0) {
1211                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1212                 goto err_qp_pool_init;
1213         }
1214         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1215                                 hw->func_caps.num_msix_vectors - 1);
1216         if (ret < 0) {
1217                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1218                 goto err_msix_pool_init;
1219         }
1220
1221         /* Initialize lan hmc */
1222         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1223                                 hw->func_caps.num_rx_qp, 0, 0);
1224         if (ret != I40E_SUCCESS) {
1225                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1226                 goto err_init_lan_hmc;
1227         }
1228
1229         /* Configure lan hmc */
1230         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1231         if (ret != I40E_SUCCESS) {
1232                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1233                 goto err_configure_lan_hmc;
1234         }
1235
1236         /* Get and check the mac address */
1237         i40e_get_mac_addr(hw, hw->mac.addr);
1238         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1239                 PMD_INIT_LOG(ERR, "mac address is not valid");
1240                 ret = -EIO;
1241                 goto err_get_mac_addr;
1242         }
1243         /* Copy the permanent MAC address */
1244         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1245                         (struct ether_addr *) hw->mac.perm_addr);
1246
1247         /* Disable flow control */
1248         hw->fc.requested_mode = I40E_FC_NONE;
1249         i40e_set_fc(hw, &aq_fail, TRUE);
1250
1251         /* Set the global registers with default ether type value */
1252         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1253         if (ret != I40E_SUCCESS) {
1254                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1255                              "VLAN ether type");
1256                 goto err_setup_pf_switch;
1257         }
1258
1259         /* PF setup, which includes VSI setup */
1260         ret = i40e_pf_setup(pf);
1261         if (ret) {
1262                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1263                 goto err_setup_pf_switch;
1264         }
1265
1266         /* reset all stats of the device, including pf and main vsi */
1267         i40e_dev_stats_reset(dev);
1268
1269         vsi = pf->main_vsi;
1270
1271         /* Disable double vlan by default */
1272         i40e_vsi_config_double_vlan(vsi, FALSE);
1273
1274         /* Disable S-TAG identification when floating_veb is disabled */
1275         if (!pf->floating_veb) {
1276                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1277                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1278                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1279                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1280                 }
1281         }
1282
1283         if (!vsi->max_macaddrs)
1284                 len = ETHER_ADDR_LEN;
1285         else
1286                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1287
1288         /* Should be after VSI initialized */
1289         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1290         if (!dev->data->mac_addrs) {
1291                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1292                                         "for storing mac address");
1293                 goto err_mac_alloc;
1294         }
1295         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1296                                         &dev->data->mac_addrs[0]);
1297
1298         /* initialize pf host driver to setup SRIOV resource if applicable */
1299         i40e_pf_host_init(dev);
1300
1301         /* register callback func to eal lib */
1302         rte_intr_callback_register(intr_handle,
1303                                    i40e_dev_interrupt_handler, dev);
1304
1305         /* configure and enable device interrupt */
1306         i40e_pf_config_irq0(hw, TRUE);
1307         i40e_pf_enable_irq0(hw);
1308
1309         /* enable uio intr after callback register */
1310         rte_intr_enable(intr_handle);
1311         /*
1312          * Add an ethertype filter to drop all flow control frames transmitted
1313          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1314          * frames to wire.
1315          */
1316         i40e_add_tx_flow_control_drop_filter(pf);
1317
1318         /* Set the max frame size to 0x2600 by default,
1319          * in case other drivers changed the default value.
1320          */
1321         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1322
1323         /* initialize mirror rule list */
1324         TAILQ_INIT(&pf->mirror_list);
1325
1326         /* Init dcb to sw mode by default */
1327         ret = i40e_dcb_init_configure(dev, TRUE);
1328         if (ret != I40E_SUCCESS) {
1329                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1330                 pf->flags &= ~I40E_FLAG_DCB;
1331         }
1332
1333         ret = i40e_init_ethtype_filter_list(dev);
1334         if (ret < 0)
1335                 goto err_init_ethtype_filter_list;
1336         ret = i40e_init_tunnel_filter_list(dev);
1337         if (ret < 0)
1338                 goto err_init_tunnel_filter_list;
1339         ret = i40e_init_fdir_filter_list(dev);
1340         if (ret < 0)
1341                 goto err_init_fdir_filter_list;
1342
1343         return 0;
1344
1345 err_init_fdir_filter_list:
1346         rte_free(pf->tunnel.hash_table);
1347         rte_free(pf->tunnel.hash_map);
1348 err_init_tunnel_filter_list:
1349         rte_free(pf->ethertype.hash_table);
1350         rte_free(pf->ethertype.hash_map);
1351 err_init_ethtype_filter_list:
1352         rte_free(dev->data->mac_addrs);
1353 err_mac_alloc:
1354         i40e_vsi_release(pf->main_vsi);
1355 err_setup_pf_switch:
1356 err_get_mac_addr:
1357 err_configure_lan_hmc:
1358         (void)i40e_shutdown_lan_hmc(hw);
1359 err_init_lan_hmc:
1360         i40e_res_pool_destroy(&pf->msix_pool);
1361 err_msix_pool_init:
1362         i40e_res_pool_destroy(&pf->qp_pool);
1363 err_qp_pool_init:
1364 err_parameter_init:
1365 err_get_capabilities:
1366 err_sync_phy_type:
1367         (void)i40e_shutdown_adminq(hw);
1368
1369         return ret;
1370 }
1371
1372 static void
1373 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1374 {
1375         struct i40e_ethertype_filter *p_ethertype;
1376         struct i40e_ethertype_rule *ethertype_rule;
1377
1378         ethertype_rule = &pf->ethertype;
1379         /* Remove all ethertype filter rules and hash */
1380         if (ethertype_rule->hash_map)
1381                 rte_free(ethertype_rule->hash_map);
1382         if (ethertype_rule->hash_table)
1383                 rte_hash_free(ethertype_rule->hash_table);
1384
1385         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1386                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1387                              p_ethertype, rules);
1388                 rte_free(p_ethertype);
1389         }
1390 }
1391
1392 static void
1393 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1394 {
1395         struct i40e_tunnel_filter *p_tunnel;
1396         struct i40e_tunnel_rule *tunnel_rule;
1397
1398         tunnel_rule = &pf->tunnel;
1399         /* Remove all tunnel director rules and hash */
1400         if (tunnel_rule->hash_map)
1401                 rte_free(tunnel_rule->hash_map);
1402         if (tunnel_rule->hash_table)
1403                 rte_hash_free(tunnel_rule->hash_table);
1404
1405         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1406                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1407                 rte_free(p_tunnel);
1408         }
1409 }
1410
1411 static void
1412 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1413 {
1414         struct i40e_fdir_filter *p_fdir;
1415         struct i40e_fdir_info *fdir_info;
1416
1417         fdir_info = &pf->fdir;
1418         /* Remove all flow director rules and hash */
1419         if (fdir_info->hash_map)
1420                 rte_free(fdir_info->hash_map);
1421         if (fdir_info->hash_table)
1422                 rte_hash_free(fdir_info->hash_table);
1423
1424         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1425                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1426                 rte_free(p_fdir);
1427         }
1428 }
1429
1430 static int
1431 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1432 {
1433         struct i40e_pf *pf;
1434         struct rte_pci_device *pci_dev;
1435         struct rte_intr_handle *intr_handle;
1436         struct i40e_hw *hw;
1437         struct i40e_filter_control_settings settings;
1438         int ret;
1439         uint8_t aq_fail = 0;
1440
1441         PMD_INIT_FUNC_TRACE();
1442
1443         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1444                 return 0;
1445
1446         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1447         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1448         pci_dev = I40E_DEV_TO_PCI(dev);
1449         intr_handle = &pci_dev->intr_handle;
1450
1451         if (hw->adapter_stopped == 0)
1452                 i40e_dev_close(dev);
1453
1454         dev->dev_ops = NULL;
1455         dev->rx_pkt_burst = NULL;
1456         dev->tx_pkt_burst = NULL;
1457
1458         /* Clear PXE mode */
1459         i40e_clear_pxe_mode(hw);
1460
1461         /* Unconfigure filter control */
1462         memset(&settings, 0, sizeof(settings));
1463         ret = i40e_set_filter_control(hw, &settings);
1464         if (ret)
1465                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1466                                         ret);
1467
1468         /* Disable flow control */
1469         hw->fc.requested_mode = I40E_FC_NONE;
1470         i40e_set_fc(hw, &aq_fail, TRUE);
1471
1472         /* uninitialize pf host driver */
1473         i40e_pf_host_uninit(dev);
1474
1475         rte_free(dev->data->mac_addrs);
1476         dev->data->mac_addrs = NULL;
1477
1478         /* disable uio intr before callback unregister */
1479         rte_intr_disable(intr_handle);
1480
1481         /* register callback func to eal lib */
1482         rte_intr_callback_unregister(intr_handle,
1483                                      i40e_dev_interrupt_handler, dev);
1484
1485         i40e_rm_ethtype_filter_list(pf);
1486         i40e_rm_tunnel_filter_list(pf);
1487         i40e_rm_fdir_filter_list(pf);
1488
1489         return 0;
1490 }
1491
1492 static int
1493 i40e_dev_configure(struct rte_eth_dev *dev)
1494 {
1495         struct i40e_adapter *ad =
1496                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1497         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1498         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1499         int i, ret;
1500
1501         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1502          * bulk allocation or vector Rx preconditions we will reset it.
1503          */
1504         ad->rx_bulk_alloc_allowed = true;
1505         ad->rx_vec_allowed = true;
1506         ad->tx_simple_allowed = true;
1507         ad->tx_vec_allowed = true;
1508
1509         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1510                 ret = i40e_fdir_setup(pf);
1511                 if (ret != I40E_SUCCESS) {
1512                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1513                         return -ENOTSUP;
1514                 }
1515                 ret = i40e_fdir_configure(dev);
1516                 if (ret < 0) {
1517                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1518                         goto err;
1519                 }
1520         } else
1521                 i40e_fdir_teardown(pf);
1522
1523         ret = i40e_dev_init_vlan(dev);
1524         if (ret < 0)
1525                 goto err;
1526
1527         /* VMDQ setup.
1528          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1529          *  RSS setting have different requirements.
1530          *  General PMD driver call sequence are NIC init, configure,
1531          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1532          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1533          *  applicable. So, VMDQ setting has to be done before
1534          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1535          *  For RSS setting, it will try to calculate actual configured RX queue
1536          *  number, which will be available after rx_queue_setup(). dev_start()
1537          *  function is good to place RSS setup.
1538          */
1539         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1540                 ret = i40e_vmdq_setup(dev);
1541                 if (ret)
1542                         goto err;
1543         }
1544
1545         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1546                 ret = i40e_dcb_setup(dev);
1547                 if (ret) {
1548                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1549                         goto err_dcb;
1550                 }
1551         }
1552
1553         return 0;
1554
1555 err_dcb:
1556         /* need to release vmdq resource if exists */
1557         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1558                 i40e_vsi_release(pf->vmdq[i].vsi);
1559                 pf->vmdq[i].vsi = NULL;
1560         }
1561         rte_free(pf->vmdq);
1562         pf->vmdq = NULL;
1563 err:
1564         /* need to release fdir resource if exists */
1565         i40e_fdir_teardown(pf);
1566         return ret;
1567 }
1568
1569 void
1570 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1571 {
1572         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1573         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1574         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1575         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1576         uint16_t msix_vect = vsi->msix_intr;
1577         uint16_t i;
1578
1579         for (i = 0; i < vsi->nb_qps; i++) {
1580                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1581                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1582                 rte_wmb();
1583         }
1584
1585         if (vsi->type != I40E_VSI_SRIOV) {
1586                 if (!rte_intr_allow_others(intr_handle)) {
1587                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1588                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1589                         I40E_WRITE_REG(hw,
1590                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1591                                        0);
1592                 } else {
1593                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1594                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1595                         I40E_WRITE_REG(hw,
1596                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1597                                                        msix_vect - 1), 0);
1598                 }
1599         } else {
1600                 uint32_t reg;
1601                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1602                         vsi->user_param + (msix_vect - 1);
1603
1604                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1605                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1606         }
1607         I40E_WRITE_FLUSH(hw);
1608 }
1609
1610 static void
1611 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1612                        int base_queue, int nb_queue)
1613 {
1614         int i;
1615         uint32_t val;
1616         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1617
1618         /* Bind all RX queues to allocated MSIX interrupt */
1619         for (i = 0; i < nb_queue; i++) {
1620                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1621                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1622                         ((base_queue + i + 1) <<
1623                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1624                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1625                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1626
1627                 if (i == nb_queue - 1)
1628                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1629                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1630         }
1631
1632         /* Write first RX queue to Link list register as the head element */
1633         if (vsi->type != I40E_VSI_SRIOV) {
1634                 uint16_t interval =
1635                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1636
1637                 if (msix_vect == I40E_MISC_VEC_ID) {
1638                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1639                                        (base_queue <<
1640                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1641                                        (0x0 <<
1642                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1643                         I40E_WRITE_REG(hw,
1644                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1645                                        interval);
1646                 } else {
1647                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1648                                        (base_queue <<
1649                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1650                                        (0x0 <<
1651                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1652                         I40E_WRITE_REG(hw,
1653                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1654                                                        msix_vect - 1),
1655                                        interval);
1656                 }
1657         } else {
1658                 uint32_t reg;
1659
1660                 if (msix_vect == I40E_MISC_VEC_ID) {
1661                         I40E_WRITE_REG(hw,
1662                                        I40E_VPINT_LNKLST0(vsi->user_param),
1663                                        (base_queue <<
1664                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1665                                        (0x0 <<
1666                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1667                 } else {
1668                         /* num_msix_vectors_vf needs to minus irq0 */
1669                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1670                                 vsi->user_param + (msix_vect - 1);
1671
1672                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1673                                        (base_queue <<
1674                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1675                                        (0x0 <<
1676                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677                 }
1678         }
1679
1680         I40E_WRITE_FLUSH(hw);
1681 }
1682
1683 void
1684 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1685 {
1686         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1687         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1688         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1689         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1690         uint16_t msix_vect = vsi->msix_intr;
1691         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1692         uint16_t queue_idx = 0;
1693         int record = 0;
1694         uint32_t val;
1695         int i;
1696
1697         for (i = 0; i < vsi->nb_qps; i++) {
1698                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1699                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1700         }
1701
1702         /* INTENA flag is not auto-cleared for interrupt */
1703         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1704         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1705                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1706                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1707         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1708
1709         /* VF bind interrupt */
1710         if (vsi->type == I40E_VSI_SRIOV) {
1711                 __vsi_queues_bind_intr(vsi, msix_vect,
1712                                        vsi->base_queue, vsi->nb_qps);
1713                 return;
1714         }
1715
1716         /* PF & VMDq bind interrupt */
1717         if (rte_intr_dp_is_en(intr_handle)) {
1718                 if (vsi->type == I40E_VSI_MAIN) {
1719                         queue_idx = 0;
1720                         record = 1;
1721                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1722                         struct i40e_vsi *main_vsi =
1723                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1724                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1725                         record = 1;
1726                 }
1727         }
1728
1729         for (i = 0; i < vsi->nb_used_qps; i++) {
1730                 if (nb_msix <= 1) {
1731                         if (!rte_intr_allow_others(intr_handle))
1732                                 /* allow to share MISC_VEC_ID */
1733                                 msix_vect = I40E_MISC_VEC_ID;
1734
1735                         /* no enough msix_vect, map all to one */
1736                         __vsi_queues_bind_intr(vsi, msix_vect,
1737                                                vsi->base_queue + i,
1738                                                vsi->nb_used_qps - i);
1739                         for (; !!record && i < vsi->nb_used_qps; i++)
1740                                 intr_handle->intr_vec[queue_idx + i] =
1741                                         msix_vect;
1742                         break;
1743                 }
1744                 /* 1:1 queue/msix_vect mapping */
1745                 __vsi_queues_bind_intr(vsi, msix_vect,
1746                                        vsi->base_queue + i, 1);
1747                 if (!!record)
1748                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1749
1750                 msix_vect++;
1751                 nb_msix--;
1752         }
1753 }
1754
1755 static void
1756 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1757 {
1758         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1760         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762         uint16_t interval = i40e_calc_itr_interval(\
1763                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1764         uint16_t msix_intr, i;
1765
1766         if (rte_intr_allow_others(intr_handle))
1767                 for (i = 0; i < vsi->nb_msix; i++) {
1768                         msix_intr = vsi->msix_intr + i;
1769                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1770                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1771                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1772                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1773                                 (interval <<
1774                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1775                 }
1776         else
1777                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1778                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1779                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1780                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1781                                (interval <<
1782                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1783
1784         I40E_WRITE_FLUSH(hw);
1785 }
1786
1787 static void
1788 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1789 {
1790         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1791         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1792         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1793         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1794         uint16_t msix_intr, i;
1795
1796         if (rte_intr_allow_others(intr_handle))
1797                 for (i = 0; i < vsi->nb_msix; i++) {
1798                         msix_intr = vsi->msix_intr + i;
1799                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1800                                        0);
1801                 }
1802         else
1803                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1804
1805         I40E_WRITE_FLUSH(hw);
1806 }
1807
1808 static inline uint8_t
1809 i40e_parse_link_speeds(uint16_t link_speeds)
1810 {
1811         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1812
1813         if (link_speeds & ETH_LINK_SPEED_40G)
1814                 link_speed |= I40E_LINK_SPEED_40GB;
1815         if (link_speeds & ETH_LINK_SPEED_25G)
1816                 link_speed |= I40E_LINK_SPEED_25GB;
1817         if (link_speeds & ETH_LINK_SPEED_20G)
1818                 link_speed |= I40E_LINK_SPEED_20GB;
1819         if (link_speeds & ETH_LINK_SPEED_10G)
1820                 link_speed |= I40E_LINK_SPEED_10GB;
1821         if (link_speeds & ETH_LINK_SPEED_1G)
1822                 link_speed |= I40E_LINK_SPEED_1GB;
1823         if (link_speeds & ETH_LINK_SPEED_100M)
1824                 link_speed |= I40E_LINK_SPEED_100MB;
1825
1826         return link_speed;
1827 }
1828
1829 static int
1830 i40e_phy_conf_link(struct i40e_hw *hw,
1831                    uint8_t abilities,
1832                    uint8_t force_speed)
1833 {
1834         enum i40e_status_code status;
1835         struct i40e_aq_get_phy_abilities_resp phy_ab;
1836         struct i40e_aq_set_phy_config phy_conf;
1837         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1838                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1839                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1840                         I40E_AQ_PHY_FLAG_LOW_POWER;
1841         const uint8_t advt = I40E_LINK_SPEED_40GB |
1842                         I40E_LINK_SPEED_25GB |
1843                         I40E_LINK_SPEED_10GB |
1844                         I40E_LINK_SPEED_1GB |
1845                         I40E_LINK_SPEED_100MB;
1846         int ret = -ENOTSUP;
1847
1848
1849         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1850                                               NULL);
1851         if (status)
1852                 return ret;
1853
1854         memset(&phy_conf, 0, sizeof(phy_conf));
1855
1856         /* bits 0-2 use the values from get_phy_abilities_resp */
1857         abilities &= ~mask;
1858         abilities |= phy_ab.abilities & mask;
1859
1860         /* update ablities and speed */
1861         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1862                 phy_conf.link_speed = advt;
1863         else
1864                 phy_conf.link_speed = force_speed;
1865
1866         phy_conf.abilities = abilities;
1867
1868         /* use get_phy_abilities_resp value for the rest */
1869         phy_conf.phy_type = phy_ab.phy_type;
1870         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1871         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1872         phy_conf.eee_capability = phy_ab.eee_capability;
1873         phy_conf.eeer = phy_ab.eeer_val;
1874         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1875
1876         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1877                     phy_ab.abilities, phy_ab.link_speed);
1878         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1879                     phy_conf.abilities, phy_conf.link_speed);
1880
1881         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1882         if (status)
1883                 return ret;
1884
1885         return I40E_SUCCESS;
1886 }
1887
1888 static int
1889 i40e_apply_link_speed(struct rte_eth_dev *dev)
1890 {
1891         uint8_t speed;
1892         uint8_t abilities = 0;
1893         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894         struct rte_eth_conf *conf = &dev->data->dev_conf;
1895
1896         speed = i40e_parse_link_speeds(conf->link_speeds);
1897         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1898         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1899                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1900         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1901
1902         /* Skip changing speed on 40G interfaces, FW does not support */
1903         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1904                 speed =  I40E_LINK_SPEED_UNKNOWN;
1905                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1906         }
1907
1908         return i40e_phy_conf_link(hw, abilities, speed);
1909 }
1910
1911 static int
1912 i40e_dev_start(struct rte_eth_dev *dev)
1913 {
1914         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1915         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1916         struct i40e_vsi *main_vsi = pf->main_vsi;
1917         int ret, i;
1918         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1919         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1920         uint32_t intr_vector = 0;
1921
1922         hw->adapter_stopped = 0;
1923
1924         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1925                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1926                              dev->data->port_id);
1927                 return -EINVAL;
1928         }
1929
1930         rte_intr_disable(intr_handle);
1931
1932         if ((rte_intr_cap_multiple(intr_handle) ||
1933              !RTE_ETH_DEV_SRIOV(dev).active) &&
1934             dev->data->dev_conf.intr_conf.rxq != 0) {
1935                 intr_vector = dev->data->nb_rx_queues;
1936                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1937                         return -1;
1938         }
1939
1940         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1941                 intr_handle->intr_vec =
1942                         rte_zmalloc("intr_vec",
1943                                     dev->data->nb_rx_queues * sizeof(int),
1944                                     0);
1945                 if (!intr_handle->intr_vec) {
1946                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1947                                      " intr_vec\n", dev->data->nb_rx_queues);
1948                         return -ENOMEM;
1949                 }
1950         }
1951
1952         /* Initialize VSI */
1953         ret = i40e_dev_rxtx_init(pf);
1954         if (ret != I40E_SUCCESS) {
1955                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1956                 goto err_up;
1957         }
1958
1959         /* Map queues with MSIX interrupt */
1960         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1961                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1962         i40e_vsi_queues_bind_intr(main_vsi);
1963         i40e_vsi_enable_queues_intr(main_vsi);
1964
1965         /* Map VMDQ VSI queues with MSIX interrupt */
1966         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1967                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1968                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1969                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1970         }
1971
1972         /* enable FDIR MSIX interrupt */
1973         if (pf->fdir.fdir_vsi) {
1974                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1975                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1976         }
1977
1978         /* Enable all queues which have been configured */
1979         ret = i40e_dev_switch_queues(pf, TRUE);
1980         if (ret != I40E_SUCCESS) {
1981                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1982                 goto err_up;
1983         }
1984
1985         /* Enable receiving broadcast packets */
1986         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1987         if (ret != I40E_SUCCESS)
1988                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1989
1990         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1991                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1992                                                 true, NULL);
1993                 if (ret != I40E_SUCCESS)
1994                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1995         }
1996
1997         /* Apply link configure */
1998         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1999                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2000                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2001                                 ETH_LINK_SPEED_40G)) {
2002                 PMD_DRV_LOG(ERR, "Invalid link setting");
2003                 goto err_up;
2004         }
2005         ret = i40e_apply_link_speed(dev);
2006         if (I40E_SUCCESS != ret) {
2007                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2008                 goto err_up;
2009         }
2010
2011         if (!rte_intr_allow_others(intr_handle)) {
2012                 rte_intr_callback_unregister(intr_handle,
2013                                              i40e_dev_interrupt_handler,
2014                                              (void *)dev);
2015                 /* configure and enable device interrupt */
2016                 i40e_pf_config_irq0(hw, FALSE);
2017                 i40e_pf_enable_irq0(hw);
2018
2019                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2020                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2021                                      " no intr multiplex\n");
2022         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2023                 ret = i40e_aq_set_phy_int_mask(hw,
2024                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2025                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2026                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2027                 if (ret != I40E_SUCCESS)
2028                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2029
2030                 /* Call get_link_info aq commond to enable LSE */
2031                 i40e_dev_link_update(dev, 0);
2032         }
2033
2034         /* enable uio intr after callback register */
2035         rte_intr_enable(intr_handle);
2036
2037         i40e_filter_restore(pf);
2038
2039         return I40E_SUCCESS;
2040
2041 err_up:
2042         i40e_dev_switch_queues(pf, FALSE);
2043         i40e_dev_clear_queues(dev);
2044
2045         return ret;
2046 }
2047
2048 static void
2049 i40e_dev_stop(struct rte_eth_dev *dev)
2050 {
2051         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2052         struct i40e_vsi *main_vsi = pf->main_vsi;
2053         struct i40e_mirror_rule *p_mirror;
2054         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         int i;
2057
2058         /* Disable all queues */
2059         i40e_dev_switch_queues(pf, FALSE);
2060
2061         /* un-map queues with interrupt registers */
2062         i40e_vsi_disable_queues_intr(main_vsi);
2063         i40e_vsi_queues_unbind_intr(main_vsi);
2064
2065         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2066                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2067                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2068         }
2069
2070         if (pf->fdir.fdir_vsi) {
2071                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2072                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2073         }
2074         /* Clear all queues and release memory */
2075         i40e_dev_clear_queues(dev);
2076
2077         /* Set link down */
2078         i40e_dev_set_link_down(dev);
2079
2080         /* Remove all mirror rules */
2081         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2082                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2083                 rte_free(p_mirror);
2084         }
2085         pf->nb_mirror_rule = 0;
2086
2087         if (!rte_intr_allow_others(intr_handle))
2088                 /* resume to the default handler */
2089                 rte_intr_callback_register(intr_handle,
2090                                            i40e_dev_interrupt_handler,
2091                                            (void *)dev);
2092
2093         /* Clean datapath event and queue/vec mapping */
2094         rte_intr_efd_disable(intr_handle);
2095         if (intr_handle->intr_vec) {
2096                 rte_free(intr_handle->intr_vec);
2097                 intr_handle->intr_vec = NULL;
2098         }
2099 }
2100
2101 static void
2102 i40e_dev_close(struct rte_eth_dev *dev)
2103 {
2104         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2107         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2108         uint32_t reg;
2109         int i;
2110
2111         PMD_INIT_FUNC_TRACE();
2112
2113         i40e_dev_stop(dev);
2114         hw->adapter_stopped = 1;
2115         i40e_dev_free_queues(dev);
2116
2117         /* Disable interrupt */
2118         i40e_pf_disable_irq0(hw);
2119         rte_intr_disable(intr_handle);
2120
2121         /* shutdown and destroy the HMC */
2122         i40e_shutdown_lan_hmc(hw);
2123
2124         /* release all the existing VSIs and VEBs */
2125         i40e_fdir_teardown(pf);
2126         i40e_vsi_release(pf->main_vsi);
2127
2128         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2129                 i40e_vsi_release(pf->vmdq[i].vsi);
2130                 pf->vmdq[i].vsi = NULL;
2131         }
2132
2133         rte_free(pf->vmdq);
2134         pf->vmdq = NULL;
2135
2136         /* shutdown the adminq */
2137         i40e_aq_queue_shutdown(hw, true);
2138         i40e_shutdown_adminq(hw);
2139
2140         i40e_res_pool_destroy(&pf->qp_pool);
2141         i40e_res_pool_destroy(&pf->msix_pool);
2142
2143         /* force a PF reset to clean anything leftover */
2144         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2145         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2146                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2147         I40E_WRITE_FLUSH(hw);
2148 }
2149
2150 static void
2151 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2152 {
2153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2154         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2155         struct i40e_vsi *vsi = pf->main_vsi;
2156         int status;
2157
2158         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2159                                                      true, NULL, true);
2160         if (status != I40E_SUCCESS)
2161                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2162
2163         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2164                                                         TRUE, NULL);
2165         if (status != I40E_SUCCESS)
2166                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2167
2168 }
2169
2170 static void
2171 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2172 {
2173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2174         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2175         struct i40e_vsi *vsi = pf->main_vsi;
2176         int status;
2177
2178         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2179                                                      false, NULL, true);
2180         if (status != I40E_SUCCESS)
2181                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2182
2183         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2184                                                         false, NULL);
2185         if (status != I40E_SUCCESS)
2186                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2187 }
2188
2189 static void
2190 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2191 {
2192         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2193         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2194         struct i40e_vsi *vsi = pf->main_vsi;
2195         int ret;
2196
2197         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2198         if (ret != I40E_SUCCESS)
2199                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2200 }
2201
2202 static void
2203 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2204 {
2205         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2207         struct i40e_vsi *vsi = pf->main_vsi;
2208         int ret;
2209
2210         if (dev->data->promiscuous == 1)
2211                 return; /* must remain in all_multicast mode */
2212
2213         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2214                                 vsi->seid, FALSE, NULL);
2215         if (ret != I40E_SUCCESS)
2216                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2217 }
2218
2219 /*
2220  * Set device link up.
2221  */
2222 static int
2223 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2224 {
2225         /* re-apply link speed setting */
2226         return i40e_apply_link_speed(dev);
2227 }
2228
2229 /*
2230  * Set device link down.
2231  */
2232 static int
2233 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2234 {
2235         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2236         uint8_t abilities = 0;
2237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238
2239         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2240         return i40e_phy_conf_link(hw, abilities, speed);
2241 }
2242
2243 int
2244 i40e_dev_link_update(struct rte_eth_dev *dev,
2245                      int wait_to_complete)
2246 {
2247 #define CHECK_INTERVAL 100  /* 100ms */
2248 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2249         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250         struct i40e_link_status link_status;
2251         struct rte_eth_link link, old;
2252         int status;
2253         unsigned rep_cnt = MAX_REPEAT_TIME;
2254         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2255
2256         memset(&link, 0, sizeof(link));
2257         memset(&old, 0, sizeof(old));
2258         memset(&link_status, 0, sizeof(link_status));
2259         rte_i40e_dev_atomic_read_link_status(dev, &old);
2260
2261         do {
2262                 /* Get link status information from hardware */
2263                 status = i40e_aq_get_link_info(hw, enable_lse,
2264                                                 &link_status, NULL);
2265                 if (status != I40E_SUCCESS) {
2266                         link.link_speed = ETH_SPEED_NUM_100M;
2267                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2268                         PMD_DRV_LOG(ERR, "Failed to get link info");
2269                         goto out;
2270                 }
2271
2272                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2273                 if (!wait_to_complete)
2274                         break;
2275
2276                 rte_delay_ms(CHECK_INTERVAL);
2277         } while (!link.link_status && rep_cnt--);
2278
2279         if (!link.link_status)
2280                 goto out;
2281
2282         /* i40e uses full duplex only */
2283         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2284
2285         /* Parse the link status */
2286         switch (link_status.link_speed) {
2287         case I40E_LINK_SPEED_100MB:
2288                 link.link_speed = ETH_SPEED_NUM_100M;
2289                 break;
2290         case I40E_LINK_SPEED_1GB:
2291                 link.link_speed = ETH_SPEED_NUM_1G;
2292                 break;
2293         case I40E_LINK_SPEED_10GB:
2294                 link.link_speed = ETH_SPEED_NUM_10G;
2295                 break;
2296         case I40E_LINK_SPEED_20GB:
2297                 link.link_speed = ETH_SPEED_NUM_20G;
2298                 break;
2299         case I40E_LINK_SPEED_25GB:
2300                 link.link_speed = ETH_SPEED_NUM_25G;
2301                 break;
2302         case I40E_LINK_SPEED_40GB:
2303                 link.link_speed = ETH_SPEED_NUM_40G;
2304                 break;
2305         default:
2306                 link.link_speed = ETH_SPEED_NUM_100M;
2307                 break;
2308         }
2309
2310         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2311                         ETH_LINK_SPEED_FIXED);
2312
2313 out:
2314         rte_i40e_dev_atomic_write_link_status(dev, &link);
2315         if (link.link_status == old.link_status)
2316                 return -1;
2317
2318         return 0;
2319 }
2320
2321 /* Get all the statistics of a VSI */
2322 void
2323 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2324 {
2325         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2326         struct i40e_eth_stats *nes = &vsi->eth_stats;
2327         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2328         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2329
2330         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2331                             vsi->offset_loaded, &oes->rx_bytes,
2332                             &nes->rx_bytes);
2333         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2334                             vsi->offset_loaded, &oes->rx_unicast,
2335                             &nes->rx_unicast);
2336         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2337                             vsi->offset_loaded, &oes->rx_multicast,
2338                             &nes->rx_multicast);
2339         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2340                             vsi->offset_loaded, &oes->rx_broadcast,
2341                             &nes->rx_broadcast);
2342         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2343                             &oes->rx_discards, &nes->rx_discards);
2344         /* GLV_REPC not supported */
2345         /* GLV_RMPC not supported */
2346         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2347                             &oes->rx_unknown_protocol,
2348                             &nes->rx_unknown_protocol);
2349         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2350                             vsi->offset_loaded, &oes->tx_bytes,
2351                             &nes->tx_bytes);
2352         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2353                             vsi->offset_loaded, &oes->tx_unicast,
2354                             &nes->tx_unicast);
2355         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2356                             vsi->offset_loaded, &oes->tx_multicast,
2357                             &nes->tx_multicast);
2358         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2359                             vsi->offset_loaded,  &oes->tx_broadcast,
2360                             &nes->tx_broadcast);
2361         /* GLV_TDPC not supported */
2362         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2363                             &oes->tx_errors, &nes->tx_errors);
2364         vsi->offset_loaded = true;
2365
2366         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2367                     vsi->vsi_id);
2368         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2369         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2370         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2371         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2372         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2373         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2374                     nes->rx_unknown_protocol);
2375         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2376         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2377         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2378         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2379         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2380         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2381         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2382                     vsi->vsi_id);
2383 }
2384
2385 static void
2386 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2387 {
2388         unsigned int i;
2389         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2390         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2391
2392         /* Get statistics of struct i40e_eth_stats */
2393         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2394                             I40E_GLPRT_GORCL(hw->port),
2395                             pf->offset_loaded, &os->eth.rx_bytes,
2396                             &ns->eth.rx_bytes);
2397         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2398                             I40E_GLPRT_UPRCL(hw->port),
2399                             pf->offset_loaded, &os->eth.rx_unicast,
2400                             &ns->eth.rx_unicast);
2401         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2402                             I40E_GLPRT_MPRCL(hw->port),
2403                             pf->offset_loaded, &os->eth.rx_multicast,
2404                             &ns->eth.rx_multicast);
2405         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2406                             I40E_GLPRT_BPRCL(hw->port),
2407                             pf->offset_loaded, &os->eth.rx_broadcast,
2408                             &ns->eth.rx_broadcast);
2409         /* Workaround: CRC size should not be included in byte statistics,
2410          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2411          */
2412         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2413                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2414
2415         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2416                             pf->offset_loaded, &os->eth.rx_discards,
2417                             &ns->eth.rx_discards);
2418         /* GLPRT_REPC not supported */
2419         /* GLPRT_RMPC not supported */
2420         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2421                             pf->offset_loaded,
2422                             &os->eth.rx_unknown_protocol,
2423                             &ns->eth.rx_unknown_protocol);
2424         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2425                             I40E_GLPRT_GOTCL(hw->port),
2426                             pf->offset_loaded, &os->eth.tx_bytes,
2427                             &ns->eth.tx_bytes);
2428         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2429                             I40E_GLPRT_UPTCL(hw->port),
2430                             pf->offset_loaded, &os->eth.tx_unicast,
2431                             &ns->eth.tx_unicast);
2432         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2433                             I40E_GLPRT_MPTCL(hw->port),
2434                             pf->offset_loaded, &os->eth.tx_multicast,
2435                             &ns->eth.tx_multicast);
2436         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2437                             I40E_GLPRT_BPTCL(hw->port),
2438                             pf->offset_loaded, &os->eth.tx_broadcast,
2439                             &ns->eth.tx_broadcast);
2440         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2441                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2442         /* GLPRT_TEPC not supported */
2443
2444         /* additional port specific stats */
2445         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2446                             pf->offset_loaded, &os->tx_dropped_link_down,
2447                             &ns->tx_dropped_link_down);
2448         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2449                             pf->offset_loaded, &os->crc_errors,
2450                             &ns->crc_errors);
2451         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2452                             pf->offset_loaded, &os->illegal_bytes,
2453                             &ns->illegal_bytes);
2454         /* GLPRT_ERRBC not supported */
2455         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2456                             pf->offset_loaded, &os->mac_local_faults,
2457                             &ns->mac_local_faults);
2458         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2459                             pf->offset_loaded, &os->mac_remote_faults,
2460                             &ns->mac_remote_faults);
2461         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2462                             pf->offset_loaded, &os->rx_length_errors,
2463                             &ns->rx_length_errors);
2464         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2465                             pf->offset_loaded, &os->link_xon_rx,
2466                             &ns->link_xon_rx);
2467         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2468                             pf->offset_loaded, &os->link_xoff_rx,
2469                             &ns->link_xoff_rx);
2470         for (i = 0; i < 8; i++) {
2471                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2472                                     pf->offset_loaded,
2473                                     &os->priority_xon_rx[i],
2474                                     &ns->priority_xon_rx[i]);
2475                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2476                                     pf->offset_loaded,
2477                                     &os->priority_xoff_rx[i],
2478                                     &ns->priority_xoff_rx[i]);
2479         }
2480         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2481                             pf->offset_loaded, &os->link_xon_tx,
2482                             &ns->link_xon_tx);
2483         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2484                             pf->offset_loaded, &os->link_xoff_tx,
2485                             &ns->link_xoff_tx);
2486         for (i = 0; i < 8; i++) {
2487                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2488                                     pf->offset_loaded,
2489                                     &os->priority_xon_tx[i],
2490                                     &ns->priority_xon_tx[i]);
2491                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2492                                     pf->offset_loaded,
2493                                     &os->priority_xoff_tx[i],
2494                                     &ns->priority_xoff_tx[i]);
2495                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2496                                     pf->offset_loaded,
2497                                     &os->priority_xon_2_xoff[i],
2498                                     &ns->priority_xon_2_xoff[i]);
2499         }
2500         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2501                             I40E_GLPRT_PRC64L(hw->port),
2502                             pf->offset_loaded, &os->rx_size_64,
2503                             &ns->rx_size_64);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2505                             I40E_GLPRT_PRC127L(hw->port),
2506                             pf->offset_loaded, &os->rx_size_127,
2507                             &ns->rx_size_127);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2509                             I40E_GLPRT_PRC255L(hw->port),
2510                             pf->offset_loaded, &os->rx_size_255,
2511                             &ns->rx_size_255);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2513                             I40E_GLPRT_PRC511L(hw->port),
2514                             pf->offset_loaded, &os->rx_size_511,
2515                             &ns->rx_size_511);
2516         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2517                             I40E_GLPRT_PRC1023L(hw->port),
2518                             pf->offset_loaded, &os->rx_size_1023,
2519                             &ns->rx_size_1023);
2520         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2521                             I40E_GLPRT_PRC1522L(hw->port),
2522                             pf->offset_loaded, &os->rx_size_1522,
2523                             &ns->rx_size_1522);
2524         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2525                             I40E_GLPRT_PRC9522L(hw->port),
2526                             pf->offset_loaded, &os->rx_size_big,
2527                             &ns->rx_size_big);
2528         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2529                             pf->offset_loaded, &os->rx_undersize,
2530                             &ns->rx_undersize);
2531         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2532                             pf->offset_loaded, &os->rx_fragments,
2533                             &ns->rx_fragments);
2534         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2535                             pf->offset_loaded, &os->rx_oversize,
2536                             &ns->rx_oversize);
2537         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2538                             pf->offset_loaded, &os->rx_jabber,
2539                             &ns->rx_jabber);
2540         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2541                             I40E_GLPRT_PTC64L(hw->port),
2542                             pf->offset_loaded, &os->tx_size_64,
2543                             &ns->tx_size_64);
2544         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2545                             I40E_GLPRT_PTC127L(hw->port),
2546                             pf->offset_loaded, &os->tx_size_127,
2547                             &ns->tx_size_127);
2548         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2549                             I40E_GLPRT_PTC255L(hw->port),
2550                             pf->offset_loaded, &os->tx_size_255,
2551                             &ns->tx_size_255);
2552         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2553                             I40E_GLPRT_PTC511L(hw->port),
2554                             pf->offset_loaded, &os->tx_size_511,
2555                             &ns->tx_size_511);
2556         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2557                             I40E_GLPRT_PTC1023L(hw->port),
2558                             pf->offset_loaded, &os->tx_size_1023,
2559                             &ns->tx_size_1023);
2560         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2561                             I40E_GLPRT_PTC1522L(hw->port),
2562                             pf->offset_loaded, &os->tx_size_1522,
2563                             &ns->tx_size_1522);
2564         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2565                             I40E_GLPRT_PTC9522L(hw->port),
2566                             pf->offset_loaded, &os->tx_size_big,
2567                             &ns->tx_size_big);
2568         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2569                            pf->offset_loaded,
2570                            &os->fd_sb_match, &ns->fd_sb_match);
2571         /* GLPRT_MSPDC not supported */
2572         /* GLPRT_XEC not supported */
2573
2574         pf->offset_loaded = true;
2575
2576         if (pf->main_vsi)
2577                 i40e_update_vsi_stats(pf->main_vsi);
2578 }
2579
2580 /* Get all statistics of a port */
2581 static void
2582 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2583 {
2584         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2587         unsigned i;
2588
2589         /* call read registers - updates values, now write them to struct */
2590         i40e_read_stats_registers(pf, hw);
2591
2592         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2593                         pf->main_vsi->eth_stats.rx_multicast +
2594                         pf->main_vsi->eth_stats.rx_broadcast -
2595                         pf->main_vsi->eth_stats.rx_discards;
2596         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2597                         pf->main_vsi->eth_stats.tx_multicast +
2598                         pf->main_vsi->eth_stats.tx_broadcast;
2599         stats->ibytes   = ns->eth.rx_bytes;
2600         stats->obytes   = ns->eth.tx_bytes;
2601         stats->oerrors  = ns->eth.tx_errors +
2602                         pf->main_vsi->eth_stats.tx_errors;
2603
2604         /* Rx Errors */
2605         stats->imissed  = ns->eth.rx_discards +
2606                         pf->main_vsi->eth_stats.rx_discards;
2607         stats->ierrors  = ns->crc_errors +
2608                         ns->rx_length_errors + ns->rx_undersize +
2609                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2610
2611         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2612         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2613         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2614         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2615         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2616         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2617         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2618                     ns->eth.rx_unknown_protocol);
2619         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2620         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2621         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2622         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2623         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2624         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2625
2626         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2627                     ns->tx_dropped_link_down);
2628         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2629         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2630                     ns->illegal_bytes);
2631         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2632         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2633                     ns->mac_local_faults);
2634         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2635                     ns->mac_remote_faults);
2636         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2637                     ns->rx_length_errors);
2638         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2639         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2640         for (i = 0; i < 8; i++) {
2641                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2642                                 i, ns->priority_xon_rx[i]);
2643                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2644                                 i, ns->priority_xoff_rx[i]);
2645         }
2646         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2647         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2648         for (i = 0; i < 8; i++) {
2649                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2650                                 i, ns->priority_xon_tx[i]);
2651                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2652                                 i, ns->priority_xoff_tx[i]);
2653                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2654                                 i, ns->priority_xon_2_xoff[i]);
2655         }
2656         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2657         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2658         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2659         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2660         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2661         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2662         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2663         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2664         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2665         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2666         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2667         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2668         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2669         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2670         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2671         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2672         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2673         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2674         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2675                         ns->mac_short_packet_dropped);
2676         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2677                     ns->checksum_error);
2678         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2679         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2680 }
2681
2682 /* Reset the statistics */
2683 static void
2684 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2685 {
2686         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2688
2689         /* Mark PF and VSI stats to update the offset, aka "reset" */
2690         pf->offset_loaded = false;
2691         if (pf->main_vsi)
2692                 pf->main_vsi->offset_loaded = false;
2693
2694         /* read the stats, reading current register values into offset */
2695         i40e_read_stats_registers(pf, hw);
2696 }
2697
2698 static uint32_t
2699 i40e_xstats_calc_num(void)
2700 {
2701         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2702                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2703                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2704 }
2705
2706 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2707                                      struct rte_eth_xstat_name *xstats_names,
2708                                      __rte_unused unsigned limit)
2709 {
2710         unsigned count = 0;
2711         unsigned i, prio;
2712
2713         if (xstats_names == NULL)
2714                 return i40e_xstats_calc_num();
2715
2716         /* Note: limit checked in rte_eth_xstats_names() */
2717
2718         /* Get stats from i40e_eth_stats struct */
2719         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2720                 snprintf(xstats_names[count].name,
2721                          sizeof(xstats_names[count].name),
2722                          "%s", rte_i40e_stats_strings[i].name);
2723                 count++;
2724         }
2725
2726         /* Get individiual stats from i40e_hw_port struct */
2727         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2728                 snprintf(xstats_names[count].name,
2729                         sizeof(xstats_names[count].name),
2730                          "%s", rte_i40e_hw_port_strings[i].name);
2731                 count++;
2732         }
2733
2734         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2735                 for (prio = 0; prio < 8; prio++) {
2736                         snprintf(xstats_names[count].name,
2737                                  sizeof(xstats_names[count].name),
2738                                  "rx_priority%u_%s", prio,
2739                                  rte_i40e_rxq_prio_strings[i].name);
2740                         count++;
2741                 }
2742         }
2743
2744         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2745                 for (prio = 0; prio < 8; prio++) {
2746                         snprintf(xstats_names[count].name,
2747                                  sizeof(xstats_names[count].name),
2748                                  "tx_priority%u_%s", prio,
2749                                  rte_i40e_txq_prio_strings[i].name);
2750                         count++;
2751                 }
2752         }
2753         return count;
2754 }
2755
2756 static int
2757 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2758                     unsigned n)
2759 {
2760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         unsigned i, count, prio;
2763         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2764
2765         count = i40e_xstats_calc_num();
2766         if (n < count)
2767                 return count;
2768
2769         i40e_read_stats_registers(pf, hw);
2770
2771         if (xstats == NULL)
2772                 return 0;
2773
2774         count = 0;
2775
2776         /* Get stats from i40e_eth_stats struct */
2777         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2778                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2779                         rte_i40e_stats_strings[i].offset);
2780                 xstats[count].id = count;
2781                 count++;
2782         }
2783
2784         /* Get individiual stats from i40e_hw_port struct */
2785         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2786                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2787                         rte_i40e_hw_port_strings[i].offset);
2788                 xstats[count].id = count;
2789                 count++;
2790         }
2791
2792         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2793                 for (prio = 0; prio < 8; prio++) {
2794                         xstats[count].value =
2795                                 *(uint64_t *)(((char *)hw_stats) +
2796                                 rte_i40e_rxq_prio_strings[i].offset +
2797                                 (sizeof(uint64_t) * prio));
2798                         xstats[count].id = count;
2799                         count++;
2800                 }
2801         }
2802
2803         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2804                 for (prio = 0; prio < 8; prio++) {
2805                         xstats[count].value =
2806                                 *(uint64_t *)(((char *)hw_stats) +
2807                                 rte_i40e_txq_prio_strings[i].offset +
2808                                 (sizeof(uint64_t) * prio));
2809                         xstats[count].id = count;
2810                         count++;
2811                 }
2812         }
2813
2814         return count;
2815 }
2816
2817 static int
2818 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2819                                  __rte_unused uint16_t queue_id,
2820                                  __rte_unused uint8_t stat_idx,
2821                                  __rte_unused uint8_t is_rx)
2822 {
2823         PMD_INIT_FUNC_TRACE();
2824
2825         return -ENOSYS;
2826 }
2827
2828 static int
2829 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2830 {
2831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         u32 full_ver;
2833         u8 ver, patch;
2834         u16 build;
2835         int ret;
2836
2837         full_ver = hw->nvm.oem_ver;
2838         ver = (u8)(full_ver >> 24);
2839         build = (u16)((full_ver >> 8) & 0xffff);
2840         patch = (u8)(full_ver & 0xff);
2841
2842         ret = snprintf(fw_version, fw_size,
2843                  "%d.%d%d 0x%08x %d.%d.%d",
2844                  ((hw->nvm.version >> 12) & 0xf),
2845                  ((hw->nvm.version >> 4) & 0xff),
2846                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2847                  ver, build, patch);
2848
2849         ret += 1; /* add the size of '\0' */
2850         if (fw_size < (u32)ret)
2851                 return ret;
2852         else
2853                 return 0;
2854 }
2855
2856 static void
2857 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2858 {
2859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2860         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2861         struct i40e_vsi *vsi = pf->main_vsi;
2862         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2863
2864         dev_info->pci_dev = pci_dev;
2865         dev_info->max_rx_queues = vsi->nb_qps;
2866         dev_info->max_tx_queues = vsi->nb_qps;
2867         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2868         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2869         dev_info->max_mac_addrs = vsi->max_macaddrs;
2870         dev_info->max_vfs = pci_dev->max_vfs;
2871         dev_info->rx_offload_capa =
2872                 DEV_RX_OFFLOAD_VLAN_STRIP |
2873                 DEV_RX_OFFLOAD_QINQ_STRIP |
2874                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2875                 DEV_RX_OFFLOAD_UDP_CKSUM |
2876                 DEV_RX_OFFLOAD_TCP_CKSUM;
2877         dev_info->tx_offload_capa =
2878                 DEV_TX_OFFLOAD_VLAN_INSERT |
2879                 DEV_TX_OFFLOAD_QINQ_INSERT |
2880                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2881                 DEV_TX_OFFLOAD_UDP_CKSUM |
2882                 DEV_TX_OFFLOAD_TCP_CKSUM |
2883                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2884                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2885                 DEV_TX_OFFLOAD_TCP_TSO |
2886                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2887                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2888                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2889                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2890         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2891                                                 sizeof(uint32_t);
2892         dev_info->reta_size = pf->hash_lut_size;
2893         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2894
2895         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2896                 .rx_thresh = {
2897                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2898                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2899                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2900                 },
2901                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2902                 .rx_drop_en = 0,
2903         };
2904
2905         dev_info->default_txconf = (struct rte_eth_txconf) {
2906                 .tx_thresh = {
2907                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2908                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2909                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2910                 },
2911                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2912                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2913                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2914                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2915         };
2916
2917         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2918                 .nb_max = I40E_MAX_RING_DESC,
2919                 .nb_min = I40E_MIN_RING_DESC,
2920                 .nb_align = I40E_ALIGN_RING_DESC,
2921         };
2922
2923         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2924                 .nb_max = I40E_MAX_RING_DESC,
2925                 .nb_min = I40E_MIN_RING_DESC,
2926                 .nb_align = I40E_ALIGN_RING_DESC,
2927                 .nb_seg_max = I40E_TX_MAX_SEG,
2928                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2929         };
2930
2931         if (pf->flags & I40E_FLAG_VMDQ) {
2932                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2933                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2934                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2935                                                 pf->max_nb_vmdq_vsi;
2936                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2937                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2938                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2939         }
2940
2941         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2942                 /* For XL710 */
2943                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2944         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2945                 /* For XXV710 */
2946                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2947         else
2948                 /* For X710 */
2949                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2950 }
2951
2952 static int
2953 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2954 {
2955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2956         struct i40e_vsi *vsi = pf->main_vsi;
2957         PMD_INIT_FUNC_TRACE();
2958
2959         if (on)
2960                 return i40e_vsi_add_vlan(vsi, vlan_id);
2961         else
2962                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2963 }
2964
2965 static int
2966 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2967                    enum rte_vlan_type vlan_type,
2968                    uint16_t tpid)
2969 {
2970         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         uint64_t reg_r = 0, reg_w = 0;
2972         uint16_t reg_id = 0;
2973         int ret = 0;
2974         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2975
2976         switch (vlan_type) {
2977         case ETH_VLAN_TYPE_OUTER:
2978                 if (qinq)
2979                         reg_id = 2;
2980                 else
2981                         reg_id = 3;
2982                 break;
2983         case ETH_VLAN_TYPE_INNER:
2984                 if (qinq)
2985                         reg_id = 3;
2986                 else {
2987                         ret = -EINVAL;
2988                         PMD_DRV_LOG(ERR,
2989                                 "Unsupported vlan type in single vlan.\n");
2990                         return ret;
2991                 }
2992                 break;
2993         default:
2994                 ret = -EINVAL;
2995                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2996                 return ret;
2997         }
2998         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2999                                           &reg_r, NULL);
3000         if (ret != I40E_SUCCESS) {
3001                 PMD_DRV_LOG(ERR, "Fail to debug read from "
3002                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3003                 ret = -EIO;
3004                 return ret;
3005         }
3006         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
3007                     "0x%08"PRIx64"", reg_id, reg_r);
3008
3009         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3010         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3011         if (reg_r == reg_w) {
3012                 ret = 0;
3013                 PMD_DRV_LOG(DEBUG, "No need to write");
3014                 return ret;
3015         }
3016
3017         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3018                                            reg_w, NULL);
3019         if (ret != I40E_SUCCESS) {
3020                 ret = -EIO;
3021                 PMD_DRV_LOG(ERR, "Fail to debug write to "
3022                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3023                 return ret;
3024         }
3025         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3026                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3027
3028         return ret;
3029 }
3030
3031 static void
3032 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3033 {
3034         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3035         struct i40e_vsi *vsi = pf->main_vsi;
3036
3037         if (mask & ETH_VLAN_FILTER_MASK) {
3038                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3039                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3040                 else
3041                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3042         }
3043
3044         if (mask & ETH_VLAN_STRIP_MASK) {
3045                 /* Enable or disable VLAN stripping */
3046                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3047                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3048                 else
3049                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3050         }
3051
3052         if (mask & ETH_VLAN_EXTEND_MASK) {
3053                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3054                         i40e_vsi_config_double_vlan(vsi, TRUE);
3055                         /* Set global registers with default ether type value */
3056                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3057                                            ETHER_TYPE_VLAN);
3058                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3059                                            ETHER_TYPE_VLAN);
3060                 }
3061                 else
3062                         i40e_vsi_config_double_vlan(vsi, FALSE);
3063         }
3064 }
3065
3066 static void
3067 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3068                           __rte_unused uint16_t queue,
3069                           __rte_unused int on)
3070 {
3071         PMD_INIT_FUNC_TRACE();
3072 }
3073
3074 static int
3075 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3076 {
3077         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3078         struct i40e_vsi *vsi = pf->main_vsi;
3079         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3080         struct i40e_vsi_vlan_pvid_info info;
3081
3082         memset(&info, 0, sizeof(info));
3083         info.on = on;
3084         if (info.on)
3085                 info.config.pvid = pvid;
3086         else {
3087                 info.config.reject.tagged =
3088                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3089                 info.config.reject.untagged =
3090                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3091         }
3092
3093         return i40e_vsi_vlan_pvid_set(vsi, &info);
3094 }
3095
3096 static int
3097 i40e_dev_led_on(struct rte_eth_dev *dev)
3098 {
3099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3100         uint32_t mode = i40e_led_get(hw);
3101
3102         if (mode == 0)
3103                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3104
3105         return 0;
3106 }
3107
3108 static int
3109 i40e_dev_led_off(struct rte_eth_dev *dev)
3110 {
3111         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3112         uint32_t mode = i40e_led_get(hw);
3113
3114         if (mode != 0)
3115                 i40e_led_set(hw, 0, false);
3116
3117         return 0;
3118 }
3119
3120 static int
3121 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3122 {
3123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3125
3126         fc_conf->pause_time = pf->fc_conf.pause_time;
3127         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3128         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3129
3130          /* Return current mode according to actual setting*/
3131         switch (hw->fc.current_mode) {
3132         case I40E_FC_FULL:
3133                 fc_conf->mode = RTE_FC_FULL;
3134                 break;
3135         case I40E_FC_TX_PAUSE:
3136                 fc_conf->mode = RTE_FC_TX_PAUSE;
3137                 break;
3138         case I40E_FC_RX_PAUSE:
3139                 fc_conf->mode = RTE_FC_RX_PAUSE;
3140                 break;
3141         case I40E_FC_NONE:
3142         default:
3143                 fc_conf->mode = RTE_FC_NONE;
3144         };
3145
3146         return 0;
3147 }
3148
3149 static int
3150 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3151 {
3152         uint32_t mflcn_reg, fctrl_reg, reg;
3153         uint32_t max_high_water;
3154         uint8_t i, aq_failure;
3155         int err;
3156         struct i40e_hw *hw;
3157         struct i40e_pf *pf;
3158         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3159                 [RTE_FC_NONE] = I40E_FC_NONE,
3160                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3161                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3162                 [RTE_FC_FULL] = I40E_FC_FULL
3163         };
3164
3165         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3166
3167         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3168         if ((fc_conf->high_water > max_high_water) ||
3169                         (fc_conf->high_water < fc_conf->low_water)) {
3170                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3171                         "High_water must <= %d.", max_high_water);
3172                 return -EINVAL;
3173         }
3174
3175         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3176         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3177         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3178
3179         pf->fc_conf.pause_time = fc_conf->pause_time;
3180         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3181         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3182
3183         PMD_INIT_FUNC_TRACE();
3184
3185         /* All the link flow control related enable/disable register
3186          * configuration is handle by the F/W
3187          */
3188         err = i40e_set_fc(hw, &aq_failure, true);
3189         if (err < 0)
3190                 return -ENOSYS;
3191
3192         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3193                 /* Configure flow control refresh threshold,
3194                  * the value for stat_tx_pause_refresh_timer[8]
3195                  * is used for global pause operation.
3196                  */
3197
3198                 I40E_WRITE_REG(hw,
3199                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3200                                pf->fc_conf.pause_time);
3201
3202                 /* configure the timer value included in transmitted pause
3203                  * frame,
3204                  * the value for stat_tx_pause_quanta[8] is used for global
3205                  * pause operation
3206                  */
3207                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3208                                pf->fc_conf.pause_time);
3209
3210                 fctrl_reg = I40E_READ_REG(hw,
3211                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3212
3213                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3214                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3215                 else
3216                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3217
3218                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3219                                fctrl_reg);
3220         } else {
3221                 /* Configure pause time (2 TCs per register) */
3222                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3223                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3224                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3225
3226                 /* Configure flow control refresh threshold value */
3227                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3228                                pf->fc_conf.pause_time / 2);
3229
3230                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3231
3232                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3233                  *depending on configuration
3234                  */
3235                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3236                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3237                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3238                 } else {
3239                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3240                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3241                 }
3242
3243                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3244         }
3245
3246         /* config the water marker both based on the packets and bytes */
3247         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3248                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3249                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3250         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3251                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3252                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3253         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3254                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3255                        << I40E_KILOSHIFT);
3256         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3257                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3258                        << I40E_KILOSHIFT);
3259
3260         I40E_WRITE_FLUSH(hw);
3261
3262         return 0;
3263 }
3264
3265 static int
3266 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3267                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3268 {
3269         PMD_INIT_FUNC_TRACE();
3270
3271         return -ENOSYS;
3272 }
3273
3274 /* Add a MAC address, and update filters */
3275 static void
3276 i40e_macaddr_add(struct rte_eth_dev *dev,
3277                  struct ether_addr *mac_addr,
3278                  __rte_unused uint32_t index,
3279                  uint32_t pool)
3280 {
3281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3282         struct i40e_mac_filter_info mac_filter;
3283         struct i40e_vsi *vsi;
3284         int ret;
3285
3286         /* If VMDQ not enabled or configured, return */
3287         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3288                           !pf->nb_cfg_vmdq_vsi)) {
3289                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3290                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3291                         pool);
3292                 return;
3293         }
3294
3295         if (pool > pf->nb_cfg_vmdq_vsi) {
3296                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3297                                 pool, pf->nb_cfg_vmdq_vsi);
3298                 return;
3299         }
3300
3301         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3302         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3303                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3304         else
3305                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3306
3307         if (pool == 0)
3308                 vsi = pf->main_vsi;
3309         else
3310                 vsi = pf->vmdq[pool - 1].vsi;
3311
3312         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3313         if (ret != I40E_SUCCESS) {
3314                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3315                 return;
3316         }
3317 }
3318
3319 /* Remove a MAC address, and update filters */
3320 static void
3321 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3322 {
3323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3324         struct i40e_vsi *vsi;
3325         struct rte_eth_dev_data *data = dev->data;
3326         struct ether_addr *macaddr;
3327         int ret;
3328         uint32_t i;
3329         uint64_t pool_sel;
3330
3331         macaddr = &(data->mac_addrs[index]);
3332
3333         pool_sel = dev->data->mac_pool_sel[index];
3334
3335         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3336                 if (pool_sel & (1ULL << i)) {
3337                         if (i == 0)
3338                                 vsi = pf->main_vsi;
3339                         else {
3340                                 /* No VMDQ pool enabled or configured */
3341                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3342                                         (i > pf->nb_cfg_vmdq_vsi)) {
3343                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3344                                                         "/configured");
3345                                         return;
3346                                 }
3347                                 vsi = pf->vmdq[i - 1].vsi;
3348                         }
3349                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3350
3351                         if (ret) {
3352                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3353                                 return;
3354                         }
3355                 }
3356         }
3357 }
3358
3359 /* Set perfect match or hash match of MAC and VLAN for a VF */
3360 static int
3361 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3362                  struct rte_eth_mac_filter *filter,
3363                  bool add)
3364 {
3365         struct i40e_hw *hw;
3366         struct i40e_mac_filter_info mac_filter;
3367         struct ether_addr old_mac;
3368         struct ether_addr *new_mac;
3369         struct i40e_pf_vf *vf = NULL;
3370         uint16_t vf_id;
3371         int ret;
3372
3373         if (pf == NULL) {
3374                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3375                 return -EINVAL;
3376         }
3377         hw = I40E_PF_TO_HW(pf);
3378
3379         if (filter == NULL) {
3380                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3381                 return -EINVAL;
3382         }
3383
3384         new_mac = &filter->mac_addr;
3385
3386         if (is_zero_ether_addr(new_mac)) {
3387                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3388                 return -EINVAL;
3389         }
3390
3391         vf_id = filter->dst_id;
3392
3393         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3394                 PMD_DRV_LOG(ERR, "Invalid argument.");
3395                 return -EINVAL;
3396         }
3397         vf = &pf->vfs[vf_id];
3398
3399         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3400                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3401                 return -EINVAL;
3402         }
3403
3404         if (add) {
3405                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3406                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3407                                 ETHER_ADDR_LEN);
3408                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3409                                  ETHER_ADDR_LEN);
3410
3411                 mac_filter.filter_type = filter->filter_type;
3412                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3413                 if (ret != I40E_SUCCESS) {
3414                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3415                         return -1;
3416                 }
3417                 ether_addr_copy(new_mac, &pf->dev_addr);
3418         } else {
3419                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3420                                 ETHER_ADDR_LEN);
3421                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3422                 if (ret != I40E_SUCCESS) {
3423                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3424                         return -1;
3425                 }
3426
3427                 /* Clear device address as it has been removed */
3428                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3429                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3430         }
3431
3432         return 0;
3433 }
3434
3435 /* MAC filter handle */
3436 static int
3437 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3438                 void *arg)
3439 {
3440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441         struct rte_eth_mac_filter *filter;
3442         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3443         int ret = I40E_NOT_SUPPORTED;
3444
3445         filter = (struct rte_eth_mac_filter *)(arg);
3446
3447         switch (filter_op) {
3448         case RTE_ETH_FILTER_NOP:
3449                 ret = I40E_SUCCESS;
3450                 break;
3451         case RTE_ETH_FILTER_ADD:
3452                 i40e_pf_disable_irq0(hw);
3453                 if (filter->is_vf)
3454                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3455                 i40e_pf_enable_irq0(hw);
3456                 break;
3457         case RTE_ETH_FILTER_DELETE:
3458                 i40e_pf_disable_irq0(hw);
3459                 if (filter->is_vf)
3460                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3461                 i40e_pf_enable_irq0(hw);
3462                 break;
3463         default:
3464                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3465                 ret = I40E_ERR_PARAM;
3466                 break;
3467         }
3468
3469         return ret;
3470 }
3471
3472 static int
3473 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3474 {
3475         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3476         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3477         int ret;
3478
3479         if (!lut)
3480                 return -EINVAL;
3481
3482         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3483                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3484                                           lut, lut_size);
3485                 if (ret) {
3486                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3487                         return ret;
3488                 }
3489         } else {
3490                 uint32_t *lut_dw = (uint32_t *)lut;
3491                 uint16_t i, lut_size_dw = lut_size / 4;
3492
3493                 for (i = 0; i < lut_size_dw; i++)
3494                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3495         }
3496
3497         return 0;
3498 }
3499
3500 static int
3501 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3502 {
3503         struct i40e_pf *pf;
3504         struct i40e_hw *hw;
3505         int ret;
3506
3507         if (!vsi || !lut)
3508                 return -EINVAL;
3509
3510         pf = I40E_VSI_TO_PF(vsi);
3511         hw = I40E_VSI_TO_HW(vsi);
3512
3513         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3514                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3515                                           lut, lut_size);
3516                 if (ret) {
3517                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3518                         return ret;
3519                 }
3520         } else {
3521                 uint32_t *lut_dw = (uint32_t *)lut;
3522                 uint16_t i, lut_size_dw = lut_size / 4;
3523
3524                 for (i = 0; i < lut_size_dw; i++)
3525                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3526                 I40E_WRITE_FLUSH(hw);
3527         }
3528
3529         return 0;
3530 }
3531
3532 static int
3533 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3534                          struct rte_eth_rss_reta_entry64 *reta_conf,
3535                          uint16_t reta_size)
3536 {
3537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3538         uint16_t i, lut_size = pf->hash_lut_size;
3539         uint16_t idx, shift;
3540         uint8_t *lut;
3541         int ret;
3542
3543         if (reta_size != lut_size ||
3544                 reta_size > ETH_RSS_RETA_SIZE_512) {
3545                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3546                         "(%d) doesn't match the number hardware can supported "
3547                                         "(%d)\n", reta_size, lut_size);
3548                 return -EINVAL;
3549         }
3550
3551         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3552         if (!lut) {
3553                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3554                 return -ENOMEM;
3555         }
3556         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3557         if (ret)
3558                 goto out;
3559         for (i = 0; i < reta_size; i++) {
3560                 idx = i / RTE_RETA_GROUP_SIZE;
3561                 shift = i % RTE_RETA_GROUP_SIZE;
3562                 if (reta_conf[idx].mask & (1ULL << shift))
3563                         lut[i] = reta_conf[idx].reta[shift];
3564         }
3565         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3566
3567 out:
3568         rte_free(lut);
3569
3570         return ret;
3571 }
3572
3573 static int
3574 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3575                         struct rte_eth_rss_reta_entry64 *reta_conf,
3576                         uint16_t reta_size)
3577 {
3578         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3579         uint16_t i, lut_size = pf->hash_lut_size;
3580         uint16_t idx, shift;
3581         uint8_t *lut;
3582         int ret;
3583
3584         if (reta_size != lut_size ||
3585                 reta_size > ETH_RSS_RETA_SIZE_512) {
3586                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3587                         "(%d) doesn't match the number hardware can supported "
3588                                         "(%d)\n", reta_size, lut_size);
3589                 return -EINVAL;
3590         }
3591
3592         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3593         if (!lut) {
3594                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3595                 return -ENOMEM;
3596         }
3597
3598         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3599         if (ret)
3600                 goto out;
3601         for (i = 0; i < reta_size; i++) {
3602                 idx = i / RTE_RETA_GROUP_SIZE;
3603                 shift = i % RTE_RETA_GROUP_SIZE;
3604                 if (reta_conf[idx].mask & (1ULL << shift))
3605                         reta_conf[idx].reta[shift] = lut[i];
3606         }
3607
3608 out:
3609         rte_free(lut);
3610
3611         return ret;
3612 }
3613
3614 /**
3615  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3616  * @hw:   pointer to the HW structure
3617  * @mem:  pointer to mem struct to fill out
3618  * @size: size of memory requested
3619  * @alignment: what to align the allocation to
3620  **/
3621 enum i40e_status_code
3622 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3623                         struct i40e_dma_mem *mem,
3624                         u64 size,
3625                         u32 alignment)
3626 {
3627         const struct rte_memzone *mz = NULL;
3628         char z_name[RTE_MEMZONE_NAMESIZE];
3629
3630         if (!mem)
3631                 return I40E_ERR_PARAM;
3632
3633         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3634         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3635                                          alignment, RTE_PGSIZE_2M);
3636         if (!mz)
3637                 return I40E_ERR_NO_MEMORY;
3638
3639         mem->size = size;
3640         mem->va = mz->addr;
3641         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3642         mem->zone = (const void *)mz;
3643         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3644                     "%"PRIu64, mz->name, mem->pa);
3645
3646         return I40E_SUCCESS;
3647 }
3648
3649 /**
3650  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3651  * @hw:   pointer to the HW structure
3652  * @mem:  ptr to mem struct to free
3653  **/
3654 enum i40e_status_code
3655 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3656                     struct i40e_dma_mem *mem)
3657 {
3658         if (!mem)
3659                 return I40E_ERR_PARAM;
3660
3661         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3662                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3663                     mem->pa);
3664         rte_memzone_free((const struct rte_memzone *)mem->zone);
3665         mem->zone = NULL;
3666         mem->va = NULL;
3667         mem->pa = (u64)0;
3668
3669         return I40E_SUCCESS;
3670 }
3671
3672 /**
3673  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3674  * @hw:   pointer to the HW structure
3675  * @mem:  pointer to mem struct to fill out
3676  * @size: size of memory requested
3677  **/
3678 enum i40e_status_code
3679 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3680                          struct i40e_virt_mem *mem,
3681                          u32 size)
3682 {
3683         if (!mem)
3684                 return I40E_ERR_PARAM;
3685
3686         mem->size = size;
3687         mem->va = rte_zmalloc("i40e", size, 0);
3688
3689         if (mem->va)
3690                 return I40E_SUCCESS;
3691         else
3692                 return I40E_ERR_NO_MEMORY;
3693 }
3694
3695 /**
3696  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3697  * @hw:   pointer to the HW structure
3698  * @mem:  pointer to mem struct to free
3699  **/
3700 enum i40e_status_code
3701 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3702                      struct i40e_virt_mem *mem)
3703 {
3704         if (!mem)
3705                 return I40E_ERR_PARAM;
3706
3707         rte_free(mem->va);
3708         mem->va = NULL;
3709
3710         return I40E_SUCCESS;
3711 }
3712
3713 void
3714 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3715 {
3716         rte_spinlock_init(&sp->spinlock);
3717 }
3718
3719 void
3720 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3721 {
3722         rte_spinlock_lock(&sp->spinlock);
3723 }
3724
3725 void
3726 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3727 {
3728         rte_spinlock_unlock(&sp->spinlock);
3729 }
3730
3731 void
3732 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3733 {
3734         return;
3735 }
3736
3737 /**
3738  * Get the hardware capabilities, which will be parsed
3739  * and saved into struct i40e_hw.
3740  */
3741 static int
3742 i40e_get_cap(struct i40e_hw *hw)
3743 {
3744         struct i40e_aqc_list_capabilities_element_resp *buf;
3745         uint16_t len, size = 0;
3746         int ret;
3747
3748         /* Calculate a huge enough buff for saving response data temporarily */
3749         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3750                                                 I40E_MAX_CAP_ELE_NUM;
3751         buf = rte_zmalloc("i40e", len, 0);
3752         if (!buf) {
3753                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3754                 return I40E_ERR_NO_MEMORY;
3755         }
3756
3757         /* Get, parse the capabilities and save it to hw */
3758         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3759                         i40e_aqc_opc_list_func_capabilities, NULL);
3760         if (ret != I40E_SUCCESS)
3761                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3762
3763         /* Free the temporary buffer after being used */
3764         rte_free(buf);
3765
3766         return ret;
3767 }
3768
3769 static int
3770 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3771 {
3772         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3773         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3774         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3775         uint16_t qp_count = 0, vsi_count = 0;
3776
3777         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3778                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3779                 return -EINVAL;
3780         }
3781         /* Add the parameter init for LFC */
3782         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3783         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3784         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3785
3786         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3787         pf->max_num_vsi = hw->func_caps.num_vsis;
3788         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3789         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3790         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3791
3792         /* FDir queue/VSI allocation */
3793         pf->fdir_qp_offset = 0;
3794         if (hw->func_caps.fd) {
3795                 pf->flags |= I40E_FLAG_FDIR;
3796                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3797         } else {
3798                 pf->fdir_nb_qps = 0;
3799         }
3800         qp_count += pf->fdir_nb_qps;
3801         vsi_count += 1;
3802
3803         /* LAN queue/VSI allocation */
3804         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3805         if (!hw->func_caps.rss) {
3806                 pf->lan_nb_qps = 1;
3807         } else {
3808                 pf->flags |= I40E_FLAG_RSS;
3809                 if (hw->mac.type == I40E_MAC_X722)
3810                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3811                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3812         }
3813         qp_count += pf->lan_nb_qps;
3814         vsi_count += 1;
3815
3816         /* VF queue/VSI allocation */
3817         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3818         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3819                 pf->flags |= I40E_FLAG_SRIOV;
3820                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3821                 pf->vf_num = pci_dev->max_vfs;
3822                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3823                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3824                             pf->vf_nb_qps * pf->vf_num);
3825         } else {
3826                 pf->vf_nb_qps = 0;
3827                 pf->vf_num = 0;
3828         }
3829         qp_count += pf->vf_nb_qps * pf->vf_num;
3830         vsi_count += pf->vf_num;
3831
3832         /* VMDq queue/VSI allocation */
3833         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3834         pf->vmdq_nb_qps = 0;
3835         pf->max_nb_vmdq_vsi = 0;
3836         if (hw->func_caps.vmdq) {
3837                 if (qp_count < hw->func_caps.num_tx_qp &&
3838                         vsi_count < hw->func_caps.num_vsis) {
3839                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3840                                 qp_count) / pf->vmdq_nb_qp_max;
3841
3842                         /* Limit the maximum number of VMDq vsi to the maximum
3843                          * ethdev can support
3844                          */
3845                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3846                                 hw->func_caps.num_vsis - vsi_count);
3847                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3848                                 ETH_64_POOLS);
3849                         if (pf->max_nb_vmdq_vsi) {
3850                                 pf->flags |= I40E_FLAG_VMDQ;
3851                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3852                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3853                                             "per VMDQ VSI, in total %u queues",
3854                                             pf->max_nb_vmdq_vsi,
3855                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3856                                             pf->max_nb_vmdq_vsi);
3857                         } else {
3858                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3859                                             "VMDq");
3860                         }
3861                 } else {
3862                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3863                 }
3864         }
3865         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3866         vsi_count += pf->max_nb_vmdq_vsi;
3867
3868         if (hw->func_caps.dcb)
3869                 pf->flags |= I40E_FLAG_DCB;
3870
3871         if (qp_count > hw->func_caps.num_tx_qp) {
3872                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3873                             "the hardware maximum %u", qp_count,
3874                             hw->func_caps.num_tx_qp);
3875                 return -EINVAL;
3876         }
3877         if (vsi_count > hw->func_caps.num_vsis) {
3878                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3879                             "the hardware maximum %u", vsi_count,
3880                             hw->func_caps.num_vsis);
3881                 return -EINVAL;
3882         }
3883
3884         return 0;
3885 }
3886
3887 static int
3888 i40e_pf_get_switch_config(struct i40e_pf *pf)
3889 {
3890         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3891         struct i40e_aqc_get_switch_config_resp *switch_config;
3892         struct i40e_aqc_switch_config_element_resp *element;
3893         uint16_t start_seid = 0, num_reported;
3894         int ret;
3895
3896         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3897                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3898         if (!switch_config) {
3899                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3900                 return -ENOMEM;
3901         }
3902
3903         /* Get the switch configurations */
3904         ret = i40e_aq_get_switch_config(hw, switch_config,
3905                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3906         if (ret != I40E_SUCCESS) {
3907                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3908                 goto fail;
3909         }
3910         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3911         if (num_reported != 1) { /* The number should be 1 */
3912                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3913                 goto fail;
3914         }
3915
3916         /* Parse the switch configuration elements */
3917         element = &(switch_config->element[0]);
3918         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3919                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3920                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3921         } else
3922                 PMD_DRV_LOG(INFO, "Unknown element type");
3923
3924 fail:
3925         rte_free(switch_config);
3926
3927         return ret;
3928 }
3929
3930 static int
3931 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3932                         uint32_t num)
3933 {
3934         struct pool_entry *entry;
3935
3936         if (pool == NULL || num == 0)
3937                 return -EINVAL;
3938
3939         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3940         if (entry == NULL) {
3941                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3942                 return -ENOMEM;
3943         }
3944
3945         /* queue heap initialize */
3946         pool->num_free = num;
3947         pool->num_alloc = 0;
3948         pool->base = base;
3949         LIST_INIT(&pool->alloc_list);
3950         LIST_INIT(&pool->free_list);
3951
3952         /* Initialize element  */
3953         entry->base = 0;
3954         entry->len = num;
3955
3956         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3957         return 0;
3958 }
3959
3960 static void
3961 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3962 {
3963         struct pool_entry *entry, *next_entry;
3964
3965         if (pool == NULL)
3966                 return;
3967
3968         for (entry = LIST_FIRST(&pool->alloc_list);
3969                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3970                         entry = next_entry) {
3971                 LIST_REMOVE(entry, next);
3972                 rte_free(entry);
3973         }
3974
3975         for (entry = LIST_FIRST(&pool->free_list);
3976                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3977                         entry = next_entry) {
3978                 LIST_REMOVE(entry, next);
3979                 rte_free(entry);
3980         }
3981
3982         pool->num_free = 0;
3983         pool->num_alloc = 0;
3984         pool->base = 0;
3985         LIST_INIT(&pool->alloc_list);
3986         LIST_INIT(&pool->free_list);
3987 }
3988
3989 static int
3990 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3991                        uint32_t base)
3992 {
3993         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3994         uint32_t pool_offset;
3995         int insert;
3996
3997         if (pool == NULL) {
3998                 PMD_DRV_LOG(ERR, "Invalid parameter");
3999                 return -EINVAL;
4000         }
4001
4002         pool_offset = base - pool->base;
4003         /* Lookup in alloc list */
4004         LIST_FOREACH(entry, &pool->alloc_list, next) {
4005                 if (entry->base == pool_offset) {
4006                         valid_entry = entry;
4007                         LIST_REMOVE(entry, next);
4008                         break;
4009                 }
4010         }
4011
4012         /* Not find, return */
4013         if (valid_entry == NULL) {
4014                 PMD_DRV_LOG(ERR, "Failed to find entry");
4015                 return -EINVAL;
4016         }
4017
4018         /**
4019          * Found it, move it to free list  and try to merge.
4020          * In order to make merge easier, always sort it by qbase.
4021          * Find adjacent prev and last entries.
4022          */
4023         prev = next = NULL;
4024         LIST_FOREACH(entry, &pool->free_list, next) {
4025                 if (entry->base > valid_entry->base) {
4026                         next = entry;
4027                         break;
4028                 }
4029                 prev = entry;
4030         }
4031
4032         insert = 0;
4033         /* Try to merge with next one*/
4034         if (next != NULL) {
4035                 /* Merge with next one */
4036                 if (valid_entry->base + valid_entry->len == next->base) {
4037                         next->base = valid_entry->base;
4038                         next->len += valid_entry->len;
4039                         rte_free(valid_entry);
4040                         valid_entry = next;
4041                         insert = 1;
4042                 }
4043         }
4044
4045         if (prev != NULL) {
4046                 /* Merge with previous one */
4047                 if (prev->base + prev->len == valid_entry->base) {
4048                         prev->len += valid_entry->len;
4049                         /* If it merge with next one, remove next node */
4050                         if (insert == 1) {
4051                                 LIST_REMOVE(valid_entry, next);
4052                                 rte_free(valid_entry);
4053                         } else {
4054                                 rte_free(valid_entry);
4055                                 insert = 1;
4056                         }
4057                 }
4058         }
4059
4060         /* Not find any entry to merge, insert */
4061         if (insert == 0) {
4062                 if (prev != NULL)
4063                         LIST_INSERT_AFTER(prev, valid_entry, next);
4064                 else if (next != NULL)
4065                         LIST_INSERT_BEFORE(next, valid_entry, next);
4066                 else /* It's empty list, insert to head */
4067                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4068         }
4069
4070         pool->num_free += valid_entry->len;
4071         pool->num_alloc -= valid_entry->len;
4072
4073         return 0;
4074 }
4075
4076 static int
4077 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4078                        uint16_t num)
4079 {
4080         struct pool_entry *entry, *valid_entry;
4081
4082         if (pool == NULL || num == 0) {
4083                 PMD_DRV_LOG(ERR, "Invalid parameter");
4084                 return -EINVAL;
4085         }
4086
4087         if (pool->num_free < num) {
4088                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4089                             num, pool->num_free);
4090                 return -ENOMEM;
4091         }
4092
4093         valid_entry = NULL;
4094         /* Lookup  in free list and find most fit one */
4095         LIST_FOREACH(entry, &pool->free_list, next) {
4096                 if (entry->len >= num) {
4097                         /* Find best one */
4098                         if (entry->len == num) {
4099                                 valid_entry = entry;
4100                                 break;
4101                         }
4102                         if (valid_entry == NULL || valid_entry->len > entry->len)
4103                                 valid_entry = entry;
4104                 }
4105         }
4106
4107         /* Not find one to satisfy the request, return */
4108         if (valid_entry == NULL) {
4109                 PMD_DRV_LOG(ERR, "No valid entry found");
4110                 return -ENOMEM;
4111         }
4112         /**
4113          * The entry have equal queue number as requested,
4114          * remove it from alloc_list.
4115          */
4116         if (valid_entry->len == num) {
4117                 LIST_REMOVE(valid_entry, next);
4118         } else {
4119                 /**
4120                  * The entry have more numbers than requested,
4121                  * create a new entry for alloc_list and minus its
4122                  * queue base and number in free_list.
4123                  */
4124                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4125                 if (entry == NULL) {
4126                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4127                                     "resource pool");
4128                         return -ENOMEM;
4129                 }
4130                 entry->base = valid_entry->base;
4131                 entry->len = num;
4132                 valid_entry->base += num;
4133                 valid_entry->len -= num;
4134                 valid_entry = entry;
4135         }
4136
4137         /* Insert it into alloc list, not sorted */
4138         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4139
4140         pool->num_free -= valid_entry->len;
4141         pool->num_alloc += valid_entry->len;
4142
4143         return valid_entry->base + pool->base;
4144 }
4145
4146 /**
4147  * bitmap_is_subset - Check whether src2 is subset of src1
4148  **/
4149 static inline int
4150 bitmap_is_subset(uint8_t src1, uint8_t src2)
4151 {
4152         return !((src1 ^ src2) & src2);
4153 }
4154
4155 static enum i40e_status_code
4156 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4157 {
4158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4159
4160         /* If DCB is not supported, only default TC is supported */
4161         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4162                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4163                 return I40E_NOT_SUPPORTED;
4164         }
4165
4166         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4167                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4168                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4169                             enabled_tcmap);
4170                 return I40E_NOT_SUPPORTED;
4171         }
4172         return I40E_SUCCESS;
4173 }
4174
4175 int
4176 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4177                                 struct i40e_vsi_vlan_pvid_info *info)
4178 {
4179         struct i40e_hw *hw;
4180         struct i40e_vsi_context ctxt;
4181         uint8_t vlan_flags = 0;
4182         int ret;
4183
4184         if (vsi == NULL || info == NULL) {
4185                 PMD_DRV_LOG(ERR, "invalid parameters");
4186                 return I40E_ERR_PARAM;
4187         }
4188
4189         if (info->on) {
4190                 vsi->info.pvid = info->config.pvid;
4191                 /**
4192                  * If insert pvid is enabled, only tagged pkts are
4193                  * allowed to be sent out.
4194                  */
4195                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4196                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4197         } else {
4198                 vsi->info.pvid = 0;
4199                 if (info->config.reject.tagged == 0)
4200                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4201
4202                 if (info->config.reject.untagged == 0)
4203                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4204         }
4205         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4206                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4207         vsi->info.port_vlan_flags |= vlan_flags;
4208         vsi->info.valid_sections =
4209                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4210         memset(&ctxt, 0, sizeof(ctxt));
4211         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4212         ctxt.seid = vsi->seid;
4213
4214         hw = I40E_VSI_TO_HW(vsi);
4215         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4216         if (ret != I40E_SUCCESS)
4217                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4218
4219         return ret;
4220 }
4221
4222 static int
4223 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4224 {
4225         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4226         int i, ret;
4227         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4228
4229         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4230         if (ret != I40E_SUCCESS)
4231                 return ret;
4232
4233         if (!vsi->seid) {
4234                 PMD_DRV_LOG(ERR, "seid not valid");
4235                 return -EINVAL;
4236         }
4237
4238         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4239         tc_bw_data.tc_valid_bits = enabled_tcmap;
4240         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4241                 tc_bw_data.tc_bw_credits[i] =
4242                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4243
4244         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4245         if (ret != I40E_SUCCESS) {
4246                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4247                 return ret;
4248         }
4249
4250         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4251                                         sizeof(vsi->info.qs_handle));
4252         return I40E_SUCCESS;
4253 }
4254
4255 static enum i40e_status_code
4256 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4257                                  struct i40e_aqc_vsi_properties_data *info,
4258                                  uint8_t enabled_tcmap)
4259 {
4260         enum i40e_status_code ret;
4261         int i, total_tc = 0;
4262         uint16_t qpnum_per_tc, bsf, qp_idx;
4263
4264         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4265         if (ret != I40E_SUCCESS)
4266                 return ret;
4267
4268         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4269                 if (enabled_tcmap & (1 << i))
4270                         total_tc++;
4271         vsi->enabled_tc = enabled_tcmap;
4272
4273         /* Number of queues per enabled TC */
4274         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4275         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4276         bsf = rte_bsf32(qpnum_per_tc);
4277
4278         /* Adjust the queue number to actual queues that can be applied */
4279         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4280                 vsi->nb_qps = qpnum_per_tc * total_tc;
4281
4282         /**
4283          * Configure TC and queue mapping parameters, for enabled TC,
4284          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4285          * default queue will serve it.
4286          */
4287         qp_idx = 0;
4288         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4289                 if (vsi->enabled_tc & (1 << i)) {
4290                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4291                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4292                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4293                         qp_idx += qpnum_per_tc;
4294                 } else
4295                         info->tc_mapping[i] = 0;
4296         }
4297
4298         /* Associate queue number with VSI */
4299         if (vsi->type == I40E_VSI_SRIOV) {
4300                 info->mapping_flags |=
4301                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4302                 for (i = 0; i < vsi->nb_qps; i++)
4303                         info->queue_mapping[i] =
4304                                 rte_cpu_to_le_16(vsi->base_queue + i);
4305         } else {
4306                 info->mapping_flags |=
4307                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4308                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4309         }
4310         info->valid_sections |=
4311                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4312
4313         return I40E_SUCCESS;
4314 }
4315
4316 static int
4317 i40e_veb_release(struct i40e_veb *veb)
4318 {
4319         struct i40e_vsi *vsi;
4320         struct i40e_hw *hw;
4321
4322         if (veb == NULL)
4323                 return -EINVAL;
4324
4325         if (!TAILQ_EMPTY(&veb->head)) {
4326                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4327                 return -EACCES;
4328         }
4329         /* associate_vsi field is NULL for floating VEB */
4330         if (veb->associate_vsi != NULL) {
4331                 vsi = veb->associate_vsi;
4332                 hw = I40E_VSI_TO_HW(vsi);
4333
4334                 vsi->uplink_seid = veb->uplink_seid;
4335                 vsi->veb = NULL;
4336         } else {
4337                 veb->associate_pf->main_vsi->floating_veb = NULL;
4338                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4339         }
4340
4341         i40e_aq_delete_element(hw, veb->seid, NULL);
4342         rte_free(veb);
4343         return I40E_SUCCESS;
4344 }
4345
4346 /* Setup a veb */
4347 static struct i40e_veb *
4348 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4349 {
4350         struct i40e_veb *veb;
4351         int ret;
4352         struct i40e_hw *hw;
4353
4354         if (pf == NULL) {
4355                 PMD_DRV_LOG(ERR,
4356                             "veb setup failed, associated PF shouldn't null");
4357                 return NULL;
4358         }
4359         hw = I40E_PF_TO_HW(pf);
4360
4361         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4362         if (!veb) {
4363                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4364                 goto fail;
4365         }
4366
4367         veb->associate_vsi = vsi;
4368         veb->associate_pf = pf;
4369         TAILQ_INIT(&veb->head);
4370         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4371
4372         /* create floating veb if vsi is NULL */
4373         if (vsi != NULL) {
4374                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4375                                       I40E_DEFAULT_TCMAP, false,
4376                                       &veb->seid, false, NULL);
4377         } else {
4378                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4379                                       true, &veb->seid, false, NULL);
4380         }
4381
4382         if (ret != I40E_SUCCESS) {
4383                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4384                             hw->aq.asq_last_status);
4385                 goto fail;
4386         }
4387
4388         /* get statistics index */
4389         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4390                                 &veb->stats_idx, NULL, NULL, NULL);
4391         if (ret != I40E_SUCCESS) {
4392                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4393                             hw->aq.asq_last_status);
4394                 goto fail;
4395         }
4396         /* Get VEB bandwidth, to be implemented */
4397         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4398         if (vsi)
4399                 vsi->uplink_seid = veb->seid;
4400
4401         return veb;
4402 fail:
4403         rte_free(veb);
4404         return NULL;
4405 }
4406
4407 int
4408 i40e_vsi_release(struct i40e_vsi *vsi)
4409 {
4410         struct i40e_pf *pf;
4411         struct i40e_hw *hw;
4412         struct i40e_vsi_list *vsi_list;
4413         void *temp;
4414         int ret;
4415         struct i40e_mac_filter *f;
4416         uint16_t user_param;
4417
4418         if (!vsi)
4419                 return I40E_SUCCESS;
4420
4421         user_param = vsi->user_param;
4422
4423         pf = I40E_VSI_TO_PF(vsi);
4424         hw = I40E_VSI_TO_HW(vsi);
4425
4426         /* VSI has child to attach, release child first */
4427         if (vsi->veb) {
4428                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4429                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4430                                 return -1;
4431                 }
4432                 i40e_veb_release(vsi->veb);
4433         }
4434
4435         if (vsi->floating_veb) {
4436                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4437                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4438                                 return -1;
4439                 }
4440         }
4441
4442         /* Remove all macvlan filters of the VSI */
4443         i40e_vsi_remove_all_macvlan_filter(vsi);
4444         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4445                 rte_free(f);
4446
4447         if (vsi->type != I40E_VSI_MAIN &&
4448             ((vsi->type != I40E_VSI_SRIOV) ||
4449             !pf->floating_veb_list[user_param])) {
4450                 /* Remove vsi from parent's sibling list */
4451                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4452                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4453                         return I40E_ERR_PARAM;
4454                 }
4455                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4456                                 &vsi->sib_vsi_list, list);
4457
4458                 /* Remove all switch element of the VSI */
4459                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4460                 if (ret != I40E_SUCCESS)
4461                         PMD_DRV_LOG(ERR, "Failed to delete element");
4462         }
4463
4464         if ((vsi->type == I40E_VSI_SRIOV) &&
4465             pf->floating_veb_list[user_param]) {
4466                 /* Remove vsi from parent's sibling list */
4467                 if (vsi->parent_vsi == NULL ||
4468                     vsi->parent_vsi->floating_veb == NULL) {
4469                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4470                         return I40E_ERR_PARAM;
4471                 }
4472                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4473                              &vsi->sib_vsi_list, list);
4474
4475                 /* Remove all switch element of the VSI */
4476                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4477                 if (ret != I40E_SUCCESS)
4478                         PMD_DRV_LOG(ERR, "Failed to delete element");
4479         }
4480
4481         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4482
4483         if (vsi->type != I40E_VSI_SRIOV)
4484                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4485         rte_free(vsi);
4486
4487         return I40E_SUCCESS;
4488 }
4489
4490 static int
4491 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4492 {
4493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4494         struct i40e_aqc_remove_macvlan_element_data def_filter;
4495         struct i40e_mac_filter_info filter;
4496         int ret;
4497
4498         if (vsi->type != I40E_VSI_MAIN)
4499                 return I40E_ERR_CONFIG;
4500         memset(&def_filter, 0, sizeof(def_filter));
4501         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4502                                         ETH_ADDR_LEN);
4503         def_filter.vlan_tag = 0;
4504         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4505                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4506         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4507         if (ret != I40E_SUCCESS) {
4508                 struct i40e_mac_filter *f;
4509                 struct ether_addr *mac;
4510
4511                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4512                             "macvlan filter");
4513                 /* It needs to add the permanent mac into mac list */
4514                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4515                 if (f == NULL) {
4516                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4517                         return I40E_ERR_NO_MEMORY;
4518                 }
4519                 mac = &f->mac_info.mac_addr;
4520                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4521                                 ETH_ADDR_LEN);
4522                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4523                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4524                 vsi->mac_num++;
4525
4526                 return ret;
4527         }
4528         (void)rte_memcpy(&filter.mac_addr,
4529                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4530         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4531         return i40e_vsi_add_mac(vsi, &filter);
4532 }
4533
4534 /*
4535  * i40e_vsi_get_bw_config - Query VSI BW Information
4536  * @vsi: the VSI to be queried
4537  *
4538  * Returns 0 on success, negative value on failure
4539  */
4540 static enum i40e_status_code
4541 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4542 {
4543         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4544         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4545         struct i40e_hw *hw = &vsi->adapter->hw;
4546         i40e_status ret;
4547         int i;
4548         uint32_t bw_max;
4549
4550         memset(&bw_config, 0, sizeof(bw_config));
4551         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4552         if (ret != I40E_SUCCESS) {
4553                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4554                             hw->aq.asq_last_status);
4555                 return ret;
4556         }
4557
4558         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4559         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4560                                         &ets_sla_config, NULL);
4561         if (ret != I40E_SUCCESS) {
4562                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4563                             "configuration %u", hw->aq.asq_last_status);
4564                 return ret;
4565         }
4566
4567         /* store and print out BW info */
4568         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4569         vsi->bw_info.bw_max = bw_config.max_bw;
4570         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4571         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4572         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4573                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4574                      I40E_16_BIT_WIDTH);
4575         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4576                 vsi->bw_info.bw_ets_share_credits[i] =
4577                                 ets_sla_config.share_credits[i];
4578                 vsi->bw_info.bw_ets_credits[i] =
4579                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4580                 /* 4 bits per TC, 4th bit is reserved */
4581                 vsi->bw_info.bw_ets_max[i] =
4582                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4583                                   RTE_LEN2MASK(3, uint8_t));
4584                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4585                             vsi->bw_info.bw_ets_share_credits[i]);
4586                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4587                             vsi->bw_info.bw_ets_credits[i]);
4588                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4589                             vsi->bw_info.bw_ets_max[i]);
4590         }
4591
4592         return I40E_SUCCESS;
4593 }
4594
4595 /* i40e_enable_pf_lb
4596  * @pf: pointer to the pf structure
4597  *
4598  * allow loopback on pf
4599  */
4600 static inline void
4601 i40e_enable_pf_lb(struct i40e_pf *pf)
4602 {
4603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4604         struct i40e_vsi_context ctxt;
4605         int ret;
4606
4607         /* Use the FW API if FW >= v5.0 */
4608         if (hw->aq.fw_maj_ver < 5) {
4609                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4610                 return;
4611         }
4612
4613         memset(&ctxt, 0, sizeof(ctxt));
4614         ctxt.seid = pf->main_vsi_seid;
4615         ctxt.pf_num = hw->pf_id;
4616         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4617         if (ret) {
4618                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4619                             ret, hw->aq.asq_last_status);
4620                 return;
4621         }
4622         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4623         ctxt.info.valid_sections =
4624                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4625         ctxt.info.switch_id |=
4626                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4627
4628         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4629         if (ret)
4630                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4631                             hw->aq.asq_last_status);
4632 }
4633
4634 /* Setup a VSI */
4635 struct i40e_vsi *
4636 i40e_vsi_setup(struct i40e_pf *pf,
4637                enum i40e_vsi_type type,
4638                struct i40e_vsi *uplink_vsi,
4639                uint16_t user_param)
4640 {
4641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4642         struct i40e_vsi *vsi;
4643         struct i40e_mac_filter_info filter;
4644         int ret;
4645         struct i40e_vsi_context ctxt;
4646         struct ether_addr broadcast =
4647                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4648
4649         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4650             uplink_vsi == NULL) {
4651                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4652                             "VSI link shouldn't be NULL");
4653                 return NULL;
4654         }
4655
4656         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4657                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4658                             "uplink VSI should be NULL");
4659                 return NULL;
4660         }
4661
4662         /* two situations
4663          * 1.type is not MAIN and uplink vsi is not NULL
4664          * If uplink vsi didn't setup VEB, create one first under veb field
4665          * 2.type is SRIOV and the uplink is NULL
4666          * If floating VEB is NULL, create one veb under floating veb field
4667          */
4668
4669         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4670             uplink_vsi->veb == NULL) {
4671                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4672
4673                 if (uplink_vsi->veb == NULL) {
4674                         PMD_DRV_LOG(ERR, "VEB setup failed");
4675                         return NULL;
4676                 }
4677                 /* set ALLOWLOOPBACk on pf, when veb is created */
4678                 i40e_enable_pf_lb(pf);
4679         }
4680
4681         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4682             pf->main_vsi->floating_veb == NULL) {
4683                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4684
4685                 if (pf->main_vsi->floating_veb == NULL) {
4686                         PMD_DRV_LOG(ERR, "VEB setup failed");
4687                         return NULL;
4688                 }
4689         }
4690
4691         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4692         if (!vsi) {
4693                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4694                 return NULL;
4695         }
4696         TAILQ_INIT(&vsi->mac_list);
4697         vsi->type = type;
4698         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4699         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4700         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4701         vsi->user_param = user_param;
4702         /* Allocate queues */
4703         switch (vsi->type) {
4704         case I40E_VSI_MAIN  :
4705                 vsi->nb_qps = pf->lan_nb_qps;
4706                 break;
4707         case I40E_VSI_SRIOV :
4708                 vsi->nb_qps = pf->vf_nb_qps;
4709                 break;
4710         case I40E_VSI_VMDQ2:
4711                 vsi->nb_qps = pf->vmdq_nb_qps;
4712                 break;
4713         case I40E_VSI_FDIR:
4714                 vsi->nb_qps = pf->fdir_nb_qps;
4715                 break;
4716         default:
4717                 goto fail_mem;
4718         }
4719         /*
4720          * The filter status descriptor is reported in rx queue 0,
4721          * while the tx queue for fdir filter programming has no
4722          * such constraints, can be non-zero queues.
4723          * To simplify it, choose FDIR vsi use queue 0 pair.
4724          * To make sure it will use queue 0 pair, queue allocation
4725          * need be done before this function is called
4726          */
4727         if (type != I40E_VSI_FDIR) {
4728                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4729                         if (ret < 0) {
4730                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4731                                                 vsi->seid, ret);
4732                                 goto fail_mem;
4733                         }
4734                         vsi->base_queue = ret;
4735         } else
4736                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4737
4738         /* VF has MSIX interrupt in VF range, don't allocate here */
4739         if (type == I40E_VSI_MAIN) {
4740                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4741                                           RTE_MIN(vsi->nb_qps,
4742                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4743                 if (ret < 0) {
4744                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4745                                     vsi->seid, ret);
4746                         goto fail_queue_alloc;
4747                 }
4748                 vsi->msix_intr = ret;
4749                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4750         } else if (type != I40E_VSI_SRIOV) {
4751                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4752                 if (ret < 0) {
4753                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4754                         goto fail_queue_alloc;
4755                 }
4756                 vsi->msix_intr = ret;
4757                 vsi->nb_msix = 1;
4758         } else {
4759                 vsi->msix_intr = 0;
4760                 vsi->nb_msix = 0;
4761         }
4762
4763         /* Add VSI */
4764         if (type == I40E_VSI_MAIN) {
4765                 /* For main VSI, no need to add since it's default one */
4766                 vsi->uplink_seid = pf->mac_seid;
4767                 vsi->seid = pf->main_vsi_seid;
4768                 /* Bind queues with specific MSIX interrupt */
4769                 /**
4770                  * Needs 2 interrupt at least, one for misc cause which will
4771                  * enabled from OS side, Another for queues binding the
4772                  * interrupt from device side only.
4773                  */
4774
4775                 /* Get default VSI parameters from hardware */
4776                 memset(&ctxt, 0, sizeof(ctxt));
4777                 ctxt.seid = vsi->seid;
4778                 ctxt.pf_num = hw->pf_id;
4779                 ctxt.uplink_seid = vsi->uplink_seid;
4780                 ctxt.vf_num = 0;
4781                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4782                 if (ret != I40E_SUCCESS) {
4783                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4784                         goto fail_msix_alloc;
4785                 }
4786                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4787                         sizeof(struct i40e_aqc_vsi_properties_data));
4788                 vsi->vsi_id = ctxt.vsi_number;
4789                 vsi->info.valid_sections = 0;
4790
4791                 /* Configure tc, enabled TC0 only */
4792                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4793                         I40E_SUCCESS) {
4794                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4795                         goto fail_msix_alloc;
4796                 }
4797
4798                 /* TC, queue mapping */
4799                 memset(&ctxt, 0, sizeof(ctxt));
4800                 vsi->info.valid_sections |=
4801                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4802                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4803                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4804                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4805                         sizeof(struct i40e_aqc_vsi_properties_data));
4806                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4807                                                 I40E_DEFAULT_TCMAP);
4808                 if (ret != I40E_SUCCESS) {
4809                         PMD_DRV_LOG(ERR, "Failed to configure "
4810                                     "TC queue mapping");
4811                         goto fail_msix_alloc;
4812                 }
4813                 ctxt.seid = vsi->seid;
4814                 ctxt.pf_num = hw->pf_id;
4815                 ctxt.uplink_seid = vsi->uplink_seid;
4816                 ctxt.vf_num = 0;
4817
4818                 /* Update VSI parameters */
4819                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4820                 if (ret != I40E_SUCCESS) {
4821                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4822                         goto fail_msix_alloc;
4823                 }
4824
4825                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4826                                                 sizeof(vsi->info.tc_mapping));
4827                 (void)rte_memcpy(&vsi->info.queue_mapping,
4828                                 &ctxt.info.queue_mapping,
4829                         sizeof(vsi->info.queue_mapping));
4830                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4831                 vsi->info.valid_sections = 0;
4832
4833                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4834                                 ETH_ADDR_LEN);
4835
4836                 /**
4837                  * Updating default filter settings are necessary to prevent
4838                  * reception of tagged packets.
4839                  * Some old firmware configurations load a default macvlan
4840                  * filter which accepts both tagged and untagged packets.
4841                  * The updating is to use a normal filter instead if needed.
4842                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4843                  * The firmware with correct configurations load the default
4844                  * macvlan filter which is expected and cannot be removed.
4845                  */
4846                 i40e_update_default_filter_setting(vsi);
4847                 i40e_config_qinq(hw, vsi);
4848         } else if (type == I40E_VSI_SRIOV) {
4849                 memset(&ctxt, 0, sizeof(ctxt));
4850                 /**
4851                  * For other VSI, the uplink_seid equals to uplink VSI's
4852                  * uplink_seid since they share same VEB
4853                  */
4854                 if (uplink_vsi == NULL)
4855                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4856                 else
4857                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4858                 ctxt.pf_num = hw->pf_id;
4859                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4860                 ctxt.uplink_seid = vsi->uplink_seid;
4861                 ctxt.connection_type = 0x1;
4862                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4863
4864                 /* Use the VEB configuration if FW >= v5.0 */
4865                 if (hw->aq.fw_maj_ver >= 5) {
4866                         /* Configure switch ID */
4867                         ctxt.info.valid_sections |=
4868                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4869                         ctxt.info.switch_id =
4870                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4871                 }
4872
4873                 /* Configure port/vlan */
4874                 ctxt.info.valid_sections |=
4875                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4876                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4877                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4878                                                 I40E_DEFAULT_TCMAP);
4879                 if (ret != I40E_SUCCESS) {
4880                         PMD_DRV_LOG(ERR, "Failed to configure "
4881                                     "TC queue mapping");
4882                         goto fail_msix_alloc;
4883                 }
4884                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4885                 ctxt.info.valid_sections |=
4886                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4887                 /**
4888                  * Since VSI is not created yet, only configure parameter,
4889                  * will add vsi below.
4890                  */
4891
4892                 i40e_config_qinq(hw, vsi);
4893         } else if (type == I40E_VSI_VMDQ2) {
4894                 memset(&ctxt, 0, sizeof(ctxt));
4895                 /*
4896                  * For other VSI, the uplink_seid equals to uplink VSI's
4897                  * uplink_seid since they share same VEB
4898                  */
4899                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4900                 ctxt.pf_num = hw->pf_id;
4901                 ctxt.vf_num = 0;
4902                 ctxt.uplink_seid = vsi->uplink_seid;
4903                 ctxt.connection_type = 0x1;
4904                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4905
4906                 ctxt.info.valid_sections |=
4907                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4908                 /* user_param carries flag to enable loop back */
4909                 if (user_param) {
4910                         ctxt.info.switch_id =
4911                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4912                         ctxt.info.switch_id |=
4913                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4914                 }
4915
4916                 /* Configure port/vlan */
4917                 ctxt.info.valid_sections |=
4918                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4919                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4920                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4921                                                 I40E_DEFAULT_TCMAP);
4922                 if (ret != I40E_SUCCESS) {
4923                         PMD_DRV_LOG(ERR, "Failed to configure "
4924                                         "TC queue mapping");
4925                         goto fail_msix_alloc;
4926                 }
4927                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4928                 ctxt.info.valid_sections |=
4929                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4930         } else if (type == I40E_VSI_FDIR) {
4931                 memset(&ctxt, 0, sizeof(ctxt));
4932                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4933                 ctxt.pf_num = hw->pf_id;
4934                 ctxt.vf_num = 0;
4935                 ctxt.uplink_seid = vsi->uplink_seid;
4936                 ctxt.connection_type = 0x1;     /* regular data port */
4937                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4938                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4939                                                 I40E_DEFAULT_TCMAP);
4940                 if (ret != I40E_SUCCESS) {
4941                         PMD_DRV_LOG(ERR, "Failed to configure "
4942                                         "TC queue mapping.");
4943                         goto fail_msix_alloc;
4944                 }
4945                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4946                 ctxt.info.valid_sections |=
4947                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4948         } else {
4949                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4950                 goto fail_msix_alloc;
4951         }
4952
4953         if (vsi->type != I40E_VSI_MAIN) {
4954                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4955                 if (ret != I40E_SUCCESS) {
4956                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4957                                     hw->aq.asq_last_status);
4958                         goto fail_msix_alloc;
4959                 }
4960                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4961                 vsi->info.valid_sections = 0;
4962                 vsi->seid = ctxt.seid;
4963                 vsi->vsi_id = ctxt.vsi_number;
4964                 vsi->sib_vsi_list.vsi = vsi;
4965                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4966                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4967                                           &vsi->sib_vsi_list, list);
4968                 } else {
4969                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4970                                           &vsi->sib_vsi_list, list);
4971                 }
4972         }
4973
4974         /* MAC/VLAN configuration */
4975         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4976         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4977
4978         ret = i40e_vsi_add_mac(vsi, &filter);
4979         if (ret != I40E_SUCCESS) {
4980                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4981                 goto fail_msix_alloc;
4982         }
4983
4984         /* Get VSI BW information */
4985         i40e_vsi_get_bw_config(vsi);
4986         return vsi;
4987 fail_msix_alloc:
4988         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4989 fail_queue_alloc:
4990         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4991 fail_mem:
4992         rte_free(vsi);
4993         return NULL;
4994 }
4995
4996 /* Configure vlan filter on or off */
4997 int
4998 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4999 {
5000         int i, num;
5001         struct i40e_mac_filter *f;
5002         void *temp;
5003         struct i40e_mac_filter_info *mac_filter;
5004         enum rte_mac_filter_type desired_filter;
5005         int ret = I40E_SUCCESS;
5006
5007         if (on) {
5008                 /* Filter to match MAC and VLAN */
5009                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5010         } else {
5011                 /* Filter to match only MAC */
5012                 desired_filter = RTE_MAC_PERFECT_MATCH;
5013         }
5014
5015         num = vsi->mac_num;
5016
5017         mac_filter = rte_zmalloc("mac_filter_info_data",
5018                                  num * sizeof(*mac_filter), 0);
5019         if (mac_filter == NULL) {
5020                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5021                 return I40E_ERR_NO_MEMORY;
5022         }
5023
5024         i = 0;
5025
5026         /* Remove all existing mac */
5027         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5028                 mac_filter[i] = f->mac_info;
5029                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5030                 if (ret) {
5031                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5032                                     on ? "enable" : "disable");
5033                         goto DONE;
5034                 }
5035                 i++;
5036         }
5037
5038         /* Override with new filter */
5039         for (i = 0; i < num; i++) {
5040                 mac_filter[i].filter_type = desired_filter;
5041                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5042                 if (ret) {
5043                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5044                                     on ? "enable" : "disable");
5045                         goto DONE;
5046                 }
5047         }
5048
5049 DONE:
5050         rte_free(mac_filter);
5051         return ret;
5052 }
5053
5054 /* Configure vlan stripping on or off */
5055 int
5056 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5057 {
5058         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5059         struct i40e_vsi_context ctxt;
5060         uint8_t vlan_flags;
5061         int ret = I40E_SUCCESS;
5062
5063         /* Check if it has been already on or off */
5064         if (vsi->info.valid_sections &
5065                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5066                 if (on) {
5067                         if ((vsi->info.port_vlan_flags &
5068                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5069                                 return 0; /* already on */
5070                 } else {
5071                         if ((vsi->info.port_vlan_flags &
5072                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5073                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5074                                 return 0; /* already off */
5075                 }
5076         }
5077
5078         if (on)
5079                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5080         else
5081                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5082         vsi->info.valid_sections =
5083                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5084         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5085         vsi->info.port_vlan_flags |= vlan_flags;
5086         ctxt.seid = vsi->seid;
5087         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5088         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5089         if (ret)
5090                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5091                             on ? "enable" : "disable");
5092
5093         return ret;
5094 }
5095
5096 static int
5097 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5098 {
5099         struct rte_eth_dev_data *data = dev->data;
5100         int ret;
5101         int mask = 0;
5102
5103         /* Apply vlan offload setting */
5104         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5105         i40e_vlan_offload_set(dev, mask);
5106
5107         /* Apply double-vlan setting, not implemented yet */
5108
5109         /* Apply pvid setting */
5110         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5111                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5112         if (ret)
5113                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5114
5115         return ret;
5116 }
5117
5118 static int
5119 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5120 {
5121         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5122
5123         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5124 }
5125
5126 static int
5127 i40e_update_flow_control(struct i40e_hw *hw)
5128 {
5129 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5130         struct i40e_link_status link_status;
5131         uint32_t rxfc = 0, txfc = 0, reg;
5132         uint8_t an_info;
5133         int ret;
5134
5135         memset(&link_status, 0, sizeof(link_status));
5136         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5137         if (ret != I40E_SUCCESS) {
5138                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5139                 goto write_reg; /* Disable flow control */
5140         }
5141
5142         an_info = hw->phy.link_info.an_info;
5143         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5144                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5145                 ret = I40E_ERR_NOT_READY;
5146                 goto write_reg; /* Disable flow control */
5147         }
5148         /**
5149          * If link auto negotiation is enabled, flow control needs to
5150          * be configured according to it
5151          */
5152         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5153         case I40E_LINK_PAUSE_RXTX:
5154                 rxfc = 1;
5155                 txfc = 1;
5156                 hw->fc.current_mode = I40E_FC_FULL;
5157                 break;
5158         case I40E_AQ_LINK_PAUSE_RX:
5159                 rxfc = 1;
5160                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5161                 break;
5162         case I40E_AQ_LINK_PAUSE_TX:
5163                 txfc = 1;
5164                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5165                 break;
5166         default:
5167                 hw->fc.current_mode = I40E_FC_NONE;
5168                 break;
5169         }
5170
5171 write_reg:
5172         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5173                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5174         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5175         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5176         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5177         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5178
5179         return ret;
5180 }
5181
5182 /* PF setup */
5183 static int
5184 i40e_pf_setup(struct i40e_pf *pf)
5185 {
5186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5187         struct i40e_filter_control_settings settings;
5188         struct i40e_vsi *vsi;
5189         int ret;
5190
5191         /* Clear all stats counters */
5192         pf->offset_loaded = FALSE;
5193         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5194         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5195
5196         ret = i40e_pf_get_switch_config(pf);
5197         if (ret != I40E_SUCCESS) {
5198                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5199                 return ret;
5200         }
5201         if (pf->flags & I40E_FLAG_FDIR) {
5202                 /* make queue allocated first, let FDIR use queue pair 0*/
5203                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5204                 if (ret != I40E_FDIR_QUEUE_ID) {
5205                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5206                                     " ret =%d", ret);
5207                         pf->flags &= ~I40E_FLAG_FDIR;
5208                 }
5209         }
5210         /*  main VSI setup */
5211         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5212         if (!vsi) {
5213                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5214                 return I40E_ERR_NOT_READY;
5215         }
5216         pf->main_vsi = vsi;
5217
5218         /* Configure filter control */
5219         memset(&settings, 0, sizeof(settings));
5220         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5221                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5222         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5223                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5224         else {
5225                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5226                                                 hw->func_caps.rss_table_size);
5227                 return I40E_ERR_PARAM;
5228         }
5229         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5230                         "size: %u\n", hw->func_caps.rss_table_size);
5231         pf->hash_lut_size = hw->func_caps.rss_table_size;
5232
5233         /* Enable ethtype and macvlan filters */
5234         settings.enable_ethtype = TRUE;
5235         settings.enable_macvlan = TRUE;
5236         ret = i40e_set_filter_control(hw, &settings);
5237         if (ret)
5238                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5239                                                                 ret);
5240
5241         /* Update flow control according to the auto negotiation */
5242         i40e_update_flow_control(hw);
5243
5244         return I40E_SUCCESS;
5245 }
5246
5247 int
5248 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5249 {
5250         uint32_t reg;
5251         uint16_t j;
5252
5253         /**
5254          * Set or clear TX Queue Disable flags,
5255          * which is required by hardware.
5256          */
5257         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5258         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5259
5260         /* Wait until the request is finished */
5261         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5262                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5263                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5264                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5265                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5266                                                         & 0x1))) {
5267                         break;
5268                 }
5269         }
5270         if (on) {
5271                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5272                         return I40E_SUCCESS; /* already on, skip next steps */
5273
5274                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5275                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5276         } else {
5277                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5278                         return I40E_SUCCESS; /* already off, skip next steps */
5279                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5280         }
5281         /* Write the register */
5282         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5283         /* Check the result */
5284         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5285                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5286                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5287                 if (on) {
5288                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5289                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5290                                 break;
5291                 } else {
5292                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5293                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5294                                 break;
5295                 }
5296         }
5297         /* Check if it is timeout */
5298         if (j >= I40E_CHK_Q_ENA_COUNT) {
5299                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5300                             (on ? "enable" : "disable"), q_idx);
5301                 return I40E_ERR_TIMEOUT;
5302         }
5303
5304         return I40E_SUCCESS;
5305 }
5306
5307 /* Swith on or off the tx queues */
5308 static int
5309 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5310 {
5311         struct rte_eth_dev_data *dev_data = pf->dev_data;
5312         struct i40e_tx_queue *txq;
5313         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5314         uint16_t i;
5315         int ret;
5316
5317         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5318                 txq = dev_data->tx_queues[i];
5319                 /* Don't operate the queue if not configured or
5320                  * if starting only per queue */
5321                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5322                         continue;
5323                 if (on)
5324                         ret = i40e_dev_tx_queue_start(dev, i);
5325                 else
5326                         ret = i40e_dev_tx_queue_stop(dev, i);
5327                 if ( ret != I40E_SUCCESS)
5328                         return ret;
5329         }
5330
5331         return I40E_SUCCESS;
5332 }
5333
5334 int
5335 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5336 {
5337         uint32_t reg;
5338         uint16_t j;
5339
5340         /* Wait until the request is finished */
5341         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5342                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5343                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5344                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5345                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5346                         break;
5347         }
5348
5349         if (on) {
5350                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5351                         return I40E_SUCCESS; /* Already on, skip next steps */
5352                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5353         } else {
5354                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5355                         return I40E_SUCCESS; /* Already off, skip next steps */
5356                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5357         }
5358
5359         /* Write the register */
5360         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5361         /* Check the result */
5362         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5363                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5364                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5365                 if (on) {
5366                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5367                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5368                                 break;
5369                 } else {
5370                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5371                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5372                                 break;
5373                 }
5374         }
5375
5376         /* Check if it is timeout */
5377         if (j >= I40E_CHK_Q_ENA_COUNT) {
5378                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5379                             (on ? "enable" : "disable"), q_idx);
5380                 return I40E_ERR_TIMEOUT;
5381         }
5382
5383         return I40E_SUCCESS;
5384 }
5385 /* Switch on or off the rx queues */
5386 static int
5387 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5388 {
5389         struct rte_eth_dev_data *dev_data = pf->dev_data;
5390         struct i40e_rx_queue *rxq;
5391         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5392         uint16_t i;
5393         int ret;
5394
5395         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5396                 rxq = dev_data->rx_queues[i];
5397                 /* Don't operate the queue if not configured or
5398                  * if starting only per queue */
5399                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5400                         continue;
5401                 if (on)
5402                         ret = i40e_dev_rx_queue_start(dev, i);
5403                 else
5404                         ret = i40e_dev_rx_queue_stop(dev, i);
5405                 if (ret != I40E_SUCCESS)
5406                         return ret;
5407         }
5408
5409         return I40E_SUCCESS;
5410 }
5411
5412 /* Switch on or off all the rx/tx queues */
5413 int
5414 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5415 {
5416         int ret;
5417
5418         if (on) {
5419                 /* enable rx queues before enabling tx queues */
5420                 ret = i40e_dev_switch_rx_queues(pf, on);
5421                 if (ret) {
5422                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5423                         return ret;
5424                 }
5425                 ret = i40e_dev_switch_tx_queues(pf, on);
5426         } else {
5427                 /* Stop tx queues before stopping rx queues */
5428                 ret = i40e_dev_switch_tx_queues(pf, on);
5429                 if (ret) {
5430                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5431                         return ret;
5432                 }
5433                 ret = i40e_dev_switch_rx_queues(pf, on);
5434         }
5435
5436         return ret;
5437 }
5438
5439 /* Initialize VSI for TX */
5440 static int
5441 i40e_dev_tx_init(struct i40e_pf *pf)
5442 {
5443         struct rte_eth_dev_data *data = pf->dev_data;
5444         uint16_t i;
5445         uint32_t ret = I40E_SUCCESS;
5446         struct i40e_tx_queue *txq;
5447
5448         for (i = 0; i < data->nb_tx_queues; i++) {
5449                 txq = data->tx_queues[i];
5450                 if (!txq || !txq->q_set)
5451                         continue;
5452                 ret = i40e_tx_queue_init(txq);
5453                 if (ret != I40E_SUCCESS)
5454                         break;
5455         }
5456         if (ret == I40E_SUCCESS)
5457                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5458                                      ->eth_dev);
5459
5460         return ret;
5461 }
5462
5463 /* Initialize VSI for RX */
5464 static int
5465 i40e_dev_rx_init(struct i40e_pf *pf)
5466 {
5467         struct rte_eth_dev_data *data = pf->dev_data;
5468         int ret = I40E_SUCCESS;
5469         uint16_t i;
5470         struct i40e_rx_queue *rxq;
5471
5472         i40e_pf_config_mq_rx(pf);
5473         for (i = 0; i < data->nb_rx_queues; i++) {
5474                 rxq = data->rx_queues[i];
5475                 if (!rxq || !rxq->q_set)
5476                         continue;
5477
5478                 ret = i40e_rx_queue_init(rxq);
5479                 if (ret != I40E_SUCCESS) {
5480                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5481                                     "initialization");
5482                         break;
5483                 }
5484         }
5485         if (ret == I40E_SUCCESS)
5486                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5487                                      ->eth_dev);
5488
5489         return ret;
5490 }
5491
5492 static int
5493 i40e_dev_rxtx_init(struct i40e_pf *pf)
5494 {
5495         int err;
5496
5497         err = i40e_dev_tx_init(pf);
5498         if (err) {
5499                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5500                 return err;
5501         }
5502         err = i40e_dev_rx_init(pf);
5503         if (err) {
5504                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5505                 return err;
5506         }
5507
5508         return err;
5509 }
5510
5511 static int
5512 i40e_vmdq_setup(struct rte_eth_dev *dev)
5513 {
5514         struct rte_eth_conf *conf = &dev->data->dev_conf;
5515         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5516         int i, err, conf_vsis, j, loop;
5517         struct i40e_vsi *vsi;
5518         struct i40e_vmdq_info *vmdq_info;
5519         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5520         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5521
5522         /*
5523          * Disable interrupt to avoid message from VF. Furthermore, it will
5524          * avoid race condition in VSI creation/destroy.
5525          */
5526         i40e_pf_disable_irq0(hw);
5527
5528         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5529                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5530                 return -ENOTSUP;
5531         }
5532
5533         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5534         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5535                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5536                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5537                         pf->max_nb_vmdq_vsi);
5538                 return -ENOTSUP;
5539         }
5540
5541         if (pf->vmdq != NULL) {
5542                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5543                 return 0;
5544         }
5545
5546         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5547                                 sizeof(*vmdq_info) * conf_vsis, 0);
5548
5549         if (pf->vmdq == NULL) {
5550                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5551                 return -ENOMEM;
5552         }
5553
5554         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5555
5556         /* Create VMDQ VSI */
5557         for (i = 0; i < conf_vsis; i++) {
5558                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5559                                 vmdq_conf->enable_loop_back);
5560                 if (vsi == NULL) {
5561                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5562                         err = -1;
5563                         goto err_vsi_setup;
5564                 }
5565                 vmdq_info = &pf->vmdq[i];
5566                 vmdq_info->pf = pf;
5567                 vmdq_info->vsi = vsi;
5568         }
5569         pf->nb_cfg_vmdq_vsi = conf_vsis;
5570
5571         /* Configure Vlan */
5572         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5573         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5574                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5575                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5576                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5577                                         vmdq_conf->pool_map[i].vlan_id, j);
5578
5579                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5580                                                 vmdq_conf->pool_map[i].vlan_id);
5581                                 if (err) {
5582                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5583                                         err = -1;
5584                                         goto err_vsi_setup;
5585                                 }
5586                         }
5587                 }
5588         }
5589
5590         i40e_pf_enable_irq0(hw);
5591
5592         return 0;
5593
5594 err_vsi_setup:
5595         for (i = 0; i < conf_vsis; i++)
5596                 if (pf->vmdq[i].vsi == NULL)
5597                         break;
5598                 else
5599                         i40e_vsi_release(pf->vmdq[i].vsi);
5600
5601         rte_free(pf->vmdq);
5602         pf->vmdq = NULL;
5603         i40e_pf_enable_irq0(hw);
5604         return err;
5605 }
5606
5607 static void
5608 i40e_stat_update_32(struct i40e_hw *hw,
5609                    uint32_t reg,
5610                    bool offset_loaded,
5611                    uint64_t *offset,
5612                    uint64_t *stat)
5613 {
5614         uint64_t new_data;
5615
5616         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5617         if (!offset_loaded)
5618                 *offset = new_data;
5619
5620         if (new_data >= *offset)
5621                 *stat = (uint64_t)(new_data - *offset);
5622         else
5623                 *stat = (uint64_t)((new_data +
5624                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5625 }
5626
5627 static void
5628 i40e_stat_update_48(struct i40e_hw *hw,
5629                    uint32_t hireg,
5630                    uint32_t loreg,
5631                    bool offset_loaded,
5632                    uint64_t *offset,
5633                    uint64_t *stat)
5634 {
5635         uint64_t new_data;
5636
5637         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5638         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5639                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5640
5641         if (!offset_loaded)
5642                 *offset = new_data;
5643
5644         if (new_data >= *offset)
5645                 *stat = new_data - *offset;
5646         else
5647                 *stat = (uint64_t)((new_data +
5648                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5649
5650         *stat &= I40E_48_BIT_MASK;
5651 }
5652
5653 /* Disable IRQ0 */
5654 void
5655 i40e_pf_disable_irq0(struct i40e_hw *hw)
5656 {
5657         /* Disable all interrupt types */
5658         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5659         I40E_WRITE_FLUSH(hw);
5660 }
5661
5662 /* Enable IRQ0 */
5663 void
5664 i40e_pf_enable_irq0(struct i40e_hw *hw)
5665 {
5666         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5667                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5668                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5669                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5670         I40E_WRITE_FLUSH(hw);
5671 }
5672
5673 static void
5674 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5675 {
5676         /* read pending request and disable first */
5677         i40e_pf_disable_irq0(hw);
5678         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5679         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5680                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5681
5682         if (no_queue)
5683                 /* Link no queues with irq0 */
5684                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5685                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5686 }
5687
5688 static void
5689 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5690 {
5691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5693         int i;
5694         uint16_t abs_vf_id;
5695         uint32_t index, offset, val;
5696
5697         if (!pf->vfs)
5698                 return;
5699         /**
5700          * Try to find which VF trigger a reset, use absolute VF id to access
5701          * since the reg is global register.
5702          */
5703         for (i = 0; i < pf->vf_num; i++) {
5704                 abs_vf_id = hw->func_caps.vf_base_id + i;
5705                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5706                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5707                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5708                 /* VFR event occured */
5709                 if (val & (0x1 << offset)) {
5710                         int ret;
5711
5712                         /* Clear the event first */
5713                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5714                                                         (0x1 << offset));
5715                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5716                         /**
5717                          * Only notify a VF reset event occured,
5718                          * don't trigger another SW reset
5719                          */
5720                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5721                         if (ret != I40E_SUCCESS)
5722                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5723                 }
5724         }
5725 }
5726
5727 static void
5728 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5729 {
5730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5731         struct i40e_virtchnl_pf_event event;
5732         int i;
5733
5734         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5735         event.event_data.link_event.link_status =
5736                 dev->data->dev_link.link_status;
5737         event.event_data.link_event.link_speed =
5738                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5739
5740         for (i = 0; i < pf->vf_num; i++)
5741                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5742                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5743 }
5744
5745 static void
5746 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5747 {
5748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5749         struct i40e_arq_event_info info;
5750         uint16_t pending, opcode;
5751         int ret;
5752
5753         info.buf_len = I40E_AQ_BUF_SZ;
5754         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5755         if (!info.msg_buf) {
5756                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5757                 return;
5758         }
5759
5760         pending = 1;
5761         while (pending) {
5762                 ret = i40e_clean_arq_element(hw, &info, &pending);
5763
5764                 if (ret != I40E_SUCCESS) {
5765                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5766                                     "aq_err: %u", hw->aq.asq_last_status);
5767                         break;
5768                 }
5769                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5770
5771                 switch (opcode) {
5772                 case i40e_aqc_opc_send_msg_to_pf:
5773                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5774                         i40e_pf_host_handle_vf_msg(dev,
5775                                         rte_le_to_cpu_16(info.desc.retval),
5776                                         rte_le_to_cpu_32(info.desc.cookie_high),
5777                                         rte_le_to_cpu_32(info.desc.cookie_low),
5778                                         info.msg_buf,
5779                                         info.msg_len);
5780                         break;
5781                 case i40e_aqc_opc_get_link_status:
5782                         ret = i40e_dev_link_update(dev, 0);
5783                         if (!ret) {
5784                                 i40e_notify_all_vfs_link_status(dev);
5785                                 _rte_eth_dev_callback_process(dev,
5786                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5787                         }
5788                         break;
5789                 default:
5790                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5791                                     opcode);
5792                         break;
5793                 }
5794         }
5795         rte_free(info.msg_buf);
5796 }
5797
5798 /**
5799  * Interrupt handler triggered by NIC  for handling
5800  * specific interrupt.
5801  *
5802  * @param handle
5803  *  Pointer to interrupt handle.
5804  * @param param
5805  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5806  *
5807  * @return
5808  *  void
5809  */
5810 static void
5811 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5812                            void *param)
5813 {
5814         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5816         uint32_t icr0;
5817
5818         /* Disable interrupt */
5819         i40e_pf_disable_irq0(hw);
5820
5821         /* read out interrupt causes */
5822         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5823
5824         /* No interrupt event indicated */
5825         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5826                 PMD_DRV_LOG(INFO, "No interrupt event");
5827                 goto done;
5828         }
5829 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5830         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5831                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5832         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5833                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5834         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5835                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5836         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5837                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5838         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5839                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5840         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5841                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5842         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5843                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5844 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5845
5846         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5847                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5848                 i40e_dev_handle_vfr_event(dev);
5849         }
5850         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5851                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5852                 i40e_dev_handle_aq_msg(dev);
5853         }
5854
5855 done:
5856         /* Enable interrupt */
5857         i40e_pf_enable_irq0(hw);
5858         rte_intr_enable(intr_handle);
5859 }
5860
5861 static int
5862 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5863                          struct i40e_macvlan_filter *filter,
5864                          int total)
5865 {
5866         int ele_num, ele_buff_size;
5867         int num, actual_num, i;
5868         uint16_t flags;
5869         int ret = I40E_SUCCESS;
5870         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5871         struct i40e_aqc_add_macvlan_element_data *req_list;
5872
5873         if (filter == NULL  || total == 0)
5874                 return I40E_ERR_PARAM;
5875         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5876         ele_buff_size = hw->aq.asq_buf_size;
5877
5878         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5879         if (req_list == NULL) {
5880                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5881                 return I40E_ERR_NO_MEMORY;
5882         }
5883
5884         num = 0;
5885         do {
5886                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5887                 memset(req_list, 0, ele_buff_size);
5888
5889                 for (i = 0; i < actual_num; i++) {
5890                         (void)rte_memcpy(req_list[i].mac_addr,
5891                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5892                         req_list[i].vlan_tag =
5893                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5894
5895                         switch (filter[num + i].filter_type) {
5896                         case RTE_MAC_PERFECT_MATCH:
5897                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5898                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5899                                 break;
5900                         case RTE_MACVLAN_PERFECT_MATCH:
5901                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5902                                 break;
5903                         case RTE_MAC_HASH_MATCH:
5904                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5905                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5906                                 break;
5907                         case RTE_MACVLAN_HASH_MATCH:
5908                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5909                                 break;
5910                         default:
5911                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5912                                 ret = I40E_ERR_PARAM;
5913                                 goto DONE;
5914                         }
5915
5916                         req_list[i].queue_number = 0;
5917
5918                         req_list[i].flags = rte_cpu_to_le_16(flags);
5919                 }
5920
5921                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5922                                                 actual_num, NULL);
5923                 if (ret != I40E_SUCCESS) {
5924                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5925                         goto DONE;
5926                 }
5927                 num += actual_num;
5928         } while (num < total);
5929
5930 DONE:
5931         rte_free(req_list);
5932         return ret;
5933 }
5934
5935 static int
5936 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5937                             struct i40e_macvlan_filter *filter,
5938                             int total)
5939 {
5940         int ele_num, ele_buff_size;
5941         int num, actual_num, i;
5942         uint16_t flags;
5943         int ret = I40E_SUCCESS;
5944         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5945         struct i40e_aqc_remove_macvlan_element_data *req_list;
5946
5947         if (filter == NULL  || total == 0)
5948                 return I40E_ERR_PARAM;
5949
5950         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5951         ele_buff_size = hw->aq.asq_buf_size;
5952
5953         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5954         if (req_list == NULL) {
5955                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5956                 return I40E_ERR_NO_MEMORY;
5957         }
5958
5959         num = 0;
5960         do {
5961                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5962                 memset(req_list, 0, ele_buff_size);
5963
5964                 for (i = 0; i < actual_num; i++) {
5965                         (void)rte_memcpy(req_list[i].mac_addr,
5966                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5967                         req_list[i].vlan_tag =
5968                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5969
5970                         switch (filter[num + i].filter_type) {
5971                         case RTE_MAC_PERFECT_MATCH:
5972                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5973                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5974                                 break;
5975                         case RTE_MACVLAN_PERFECT_MATCH:
5976                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5977                                 break;
5978                         case RTE_MAC_HASH_MATCH:
5979                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5980                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5981                                 break;
5982                         case RTE_MACVLAN_HASH_MATCH:
5983                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5984                                 break;
5985                         default:
5986                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5987                                 ret = I40E_ERR_PARAM;
5988                                 goto DONE;
5989                         }
5990                         req_list[i].flags = rte_cpu_to_le_16(flags);
5991                 }
5992
5993                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5994                                                 actual_num, NULL);
5995                 if (ret != I40E_SUCCESS) {
5996                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5997                         goto DONE;
5998                 }
5999                 num += actual_num;
6000         } while (num < total);
6001
6002 DONE:
6003         rte_free(req_list);
6004         return ret;
6005 }
6006
6007 /* Find out specific MAC filter */
6008 static struct i40e_mac_filter *
6009 i40e_find_mac_filter(struct i40e_vsi *vsi,
6010                          struct ether_addr *macaddr)
6011 {
6012         struct i40e_mac_filter *f;
6013
6014         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6015                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6016                         return f;
6017         }
6018
6019         return NULL;
6020 }
6021
6022 static bool
6023 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6024                          uint16_t vlan_id)
6025 {
6026         uint32_t vid_idx, vid_bit;
6027
6028         if (vlan_id > ETH_VLAN_ID_MAX)
6029                 return 0;
6030
6031         vid_idx = I40E_VFTA_IDX(vlan_id);
6032         vid_bit = I40E_VFTA_BIT(vlan_id);
6033
6034         if (vsi->vfta[vid_idx] & vid_bit)
6035                 return 1;
6036         else
6037                 return 0;
6038 }
6039
6040 static void
6041 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6042                          uint16_t vlan_id, bool on)
6043 {
6044         uint32_t vid_idx, vid_bit;
6045
6046         if (vlan_id > ETH_VLAN_ID_MAX)
6047                 return;
6048
6049         vid_idx = I40E_VFTA_IDX(vlan_id);
6050         vid_bit = I40E_VFTA_BIT(vlan_id);
6051
6052         if (on)
6053                 vsi->vfta[vid_idx] |= vid_bit;
6054         else
6055                 vsi->vfta[vid_idx] &= ~vid_bit;
6056 }
6057
6058 /**
6059  * Find all vlan options for specific mac addr,
6060  * return with actual vlan found.
6061  */
6062 static inline int
6063 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6064                            struct i40e_macvlan_filter *mv_f,
6065                            int num, struct ether_addr *addr)
6066 {
6067         int i;
6068         uint32_t j, k;
6069
6070         /**
6071          * Not to use i40e_find_vlan_filter to decrease the loop time,
6072          * although the code looks complex.
6073           */
6074         if (num < vsi->vlan_num)
6075                 return I40E_ERR_PARAM;
6076
6077         i = 0;
6078         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6079                 if (vsi->vfta[j]) {
6080                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6081                                 if (vsi->vfta[j] & (1 << k)) {
6082                                         if (i > num - 1) {
6083                                                 PMD_DRV_LOG(ERR, "vlan number "
6084                                                             "not match");
6085                                                 return I40E_ERR_PARAM;
6086                                         }
6087                                         (void)rte_memcpy(&mv_f[i].macaddr,
6088                                                         addr, ETH_ADDR_LEN);
6089                                         mv_f[i].vlan_id =
6090                                                 j * I40E_UINT32_BIT_SIZE + k;
6091                                         i++;
6092                                 }
6093                         }
6094                 }
6095         }
6096         return I40E_SUCCESS;
6097 }
6098
6099 static inline int
6100 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6101                            struct i40e_macvlan_filter *mv_f,
6102                            int num,
6103                            uint16_t vlan)
6104 {
6105         int i = 0;
6106         struct i40e_mac_filter *f;
6107
6108         if (num < vsi->mac_num)
6109                 return I40E_ERR_PARAM;
6110
6111         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6112                 if (i > num - 1) {
6113                         PMD_DRV_LOG(ERR, "buffer number not match");
6114                         return I40E_ERR_PARAM;
6115                 }
6116                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6117                                 ETH_ADDR_LEN);
6118                 mv_f[i].vlan_id = vlan;
6119                 mv_f[i].filter_type = f->mac_info.filter_type;
6120                 i++;
6121         }
6122
6123         return I40E_SUCCESS;
6124 }
6125
6126 static int
6127 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6128 {
6129         int i, num;
6130         struct i40e_mac_filter *f;
6131         struct i40e_macvlan_filter *mv_f;
6132         int ret = I40E_SUCCESS;
6133
6134         if (vsi == NULL || vsi->mac_num == 0)
6135                 return I40E_ERR_PARAM;
6136
6137         /* Case that no vlan is set */
6138         if (vsi->vlan_num == 0)
6139                 num = vsi->mac_num;
6140         else
6141                 num = vsi->mac_num * vsi->vlan_num;
6142
6143         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6144         if (mv_f == NULL) {
6145                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6146                 return I40E_ERR_NO_MEMORY;
6147         }
6148
6149         i = 0;
6150         if (vsi->vlan_num == 0) {
6151                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6152                         (void)rte_memcpy(&mv_f[i].macaddr,
6153                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6154                         mv_f[i].vlan_id = 0;
6155                         i++;
6156                 }
6157         } else {
6158                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6159                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6160                                         vsi->vlan_num, &f->mac_info.mac_addr);
6161                         if (ret != I40E_SUCCESS)
6162                                 goto DONE;
6163                         i += vsi->vlan_num;
6164                 }
6165         }
6166
6167         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6168 DONE:
6169         rte_free(mv_f);
6170
6171         return ret;
6172 }
6173
6174 int
6175 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6176 {
6177         struct i40e_macvlan_filter *mv_f;
6178         int mac_num;
6179         int ret = I40E_SUCCESS;
6180
6181         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6182                 return I40E_ERR_PARAM;
6183
6184         /* If it's already set, just return */
6185         if (i40e_find_vlan_filter(vsi,vlan))
6186                 return I40E_SUCCESS;
6187
6188         mac_num = vsi->mac_num;
6189
6190         if (mac_num == 0) {
6191                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6192                 return I40E_ERR_PARAM;
6193         }
6194
6195         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6196
6197         if (mv_f == NULL) {
6198                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6199                 return I40E_ERR_NO_MEMORY;
6200         }
6201
6202         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6203
6204         if (ret != I40E_SUCCESS)
6205                 goto DONE;
6206
6207         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6208
6209         if (ret != I40E_SUCCESS)
6210                 goto DONE;
6211
6212         i40e_set_vlan_filter(vsi, vlan, 1);
6213
6214         vsi->vlan_num++;
6215         ret = I40E_SUCCESS;
6216 DONE:
6217         rte_free(mv_f);
6218         return ret;
6219 }
6220
6221 int
6222 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6223 {
6224         struct i40e_macvlan_filter *mv_f;
6225         int mac_num;
6226         int ret = I40E_SUCCESS;
6227
6228         /**
6229          * Vlan 0 is the generic filter for untagged packets
6230          * and can't be removed.
6231          */
6232         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6233                 return I40E_ERR_PARAM;
6234
6235         /* If can't find it, just return */
6236         if (!i40e_find_vlan_filter(vsi, vlan))
6237                 return I40E_ERR_PARAM;
6238
6239         mac_num = vsi->mac_num;
6240
6241         if (mac_num == 0) {
6242                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6243                 return I40E_ERR_PARAM;
6244         }
6245
6246         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6247
6248         if (mv_f == NULL) {
6249                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6250                 return I40E_ERR_NO_MEMORY;
6251         }
6252
6253         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6254
6255         if (ret != I40E_SUCCESS)
6256                 goto DONE;
6257
6258         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6259
6260         if (ret != I40E_SUCCESS)
6261                 goto DONE;
6262
6263         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6264         if (vsi->vlan_num == 1) {
6265                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6266                 if (ret != I40E_SUCCESS)
6267                         goto DONE;
6268
6269                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6270                 if (ret != I40E_SUCCESS)
6271                         goto DONE;
6272         }
6273
6274         i40e_set_vlan_filter(vsi, vlan, 0);
6275
6276         vsi->vlan_num--;
6277         ret = I40E_SUCCESS;
6278 DONE:
6279         rte_free(mv_f);
6280         return ret;
6281 }
6282
6283 int
6284 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6285 {
6286         struct i40e_mac_filter *f;
6287         struct i40e_macvlan_filter *mv_f;
6288         int i, vlan_num = 0;
6289         int ret = I40E_SUCCESS;
6290
6291         /* If it's add and we've config it, return */
6292         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6293         if (f != NULL)
6294                 return I40E_SUCCESS;
6295         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6296                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6297
6298                 /**
6299                  * If vlan_num is 0, that's the first time to add mac,
6300                  * set mask for vlan_id 0.
6301                  */
6302                 if (vsi->vlan_num == 0) {
6303                         i40e_set_vlan_filter(vsi, 0, 1);
6304                         vsi->vlan_num = 1;
6305                 }
6306                 vlan_num = vsi->vlan_num;
6307         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6308                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6309                 vlan_num = 1;
6310
6311         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6312         if (mv_f == NULL) {
6313                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6314                 return I40E_ERR_NO_MEMORY;
6315         }
6316
6317         for (i = 0; i < vlan_num; i++) {
6318                 mv_f[i].filter_type = mac_filter->filter_type;
6319                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6320                                 ETH_ADDR_LEN);
6321         }
6322
6323         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6324                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6325                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6326                                         &mac_filter->mac_addr);
6327                 if (ret != I40E_SUCCESS)
6328                         goto DONE;
6329         }
6330
6331         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6332         if (ret != I40E_SUCCESS)
6333                 goto DONE;
6334
6335         /* Add the mac addr into mac list */
6336         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6337         if (f == NULL) {
6338                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6339                 ret = I40E_ERR_NO_MEMORY;
6340                 goto DONE;
6341         }
6342         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6343                         ETH_ADDR_LEN);
6344         f->mac_info.filter_type = mac_filter->filter_type;
6345         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6346         vsi->mac_num++;
6347
6348         ret = I40E_SUCCESS;
6349 DONE:
6350         rte_free(mv_f);
6351
6352         return ret;
6353 }
6354
6355 int
6356 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6357 {
6358         struct i40e_mac_filter *f;
6359         struct i40e_macvlan_filter *mv_f;
6360         int i, vlan_num;
6361         enum rte_mac_filter_type filter_type;
6362         int ret = I40E_SUCCESS;
6363
6364         /* Can't find it, return an error */
6365         f = i40e_find_mac_filter(vsi, addr);
6366         if (f == NULL)
6367                 return I40E_ERR_PARAM;
6368
6369         vlan_num = vsi->vlan_num;
6370         filter_type = f->mac_info.filter_type;
6371         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6372                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6373                 if (vlan_num == 0) {
6374                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6375                         return I40E_ERR_PARAM;
6376                 }
6377         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6378                         filter_type == RTE_MAC_HASH_MATCH)
6379                 vlan_num = 1;
6380
6381         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6382         if (mv_f == NULL) {
6383                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6384                 return I40E_ERR_NO_MEMORY;
6385         }
6386
6387         for (i = 0; i < vlan_num; i++) {
6388                 mv_f[i].filter_type = filter_type;
6389                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6390                                 ETH_ADDR_LEN);
6391         }
6392         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6393                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6394                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6395                 if (ret != I40E_SUCCESS)
6396                         goto DONE;
6397         }
6398
6399         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6400         if (ret != I40E_SUCCESS)
6401                 goto DONE;
6402
6403         /* Remove the mac addr into mac list */
6404         TAILQ_REMOVE(&vsi->mac_list, f, next);
6405         rte_free(f);
6406         vsi->mac_num--;
6407
6408         ret = I40E_SUCCESS;
6409 DONE:
6410         rte_free(mv_f);
6411         return ret;
6412 }
6413
6414 /* Configure hash enable flags for RSS */
6415 uint64_t
6416 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6417 {
6418         uint64_t hena = 0;
6419
6420         if (!flags)
6421                 return hena;
6422
6423         if (flags & ETH_RSS_FRAG_IPV4)
6424                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6425         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6426                 if (type == I40E_MAC_X722) {
6427                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6428                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6429                 } else
6430                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6431         }
6432         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6433                 if (type == I40E_MAC_X722) {
6434                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6435                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6436                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6437                 } else
6438                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6439         }
6440         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6441                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6442         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6443                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6444         if (flags & ETH_RSS_FRAG_IPV6)
6445                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6446         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6447                 if (type == I40E_MAC_X722) {
6448                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6449                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6450                 } else
6451                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6452         }
6453         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6454                 if (type == I40E_MAC_X722) {
6455                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6456                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6457                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6458                 } else
6459                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6460         }
6461         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6462                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6463         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6464                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6465         if (flags & ETH_RSS_L2_PAYLOAD)
6466                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6467
6468         return hena;
6469 }
6470
6471 /* Parse the hash enable flags */
6472 uint64_t
6473 i40e_parse_hena(uint64_t flags)
6474 {
6475         uint64_t rss_hf = 0;
6476
6477         if (!flags)
6478                 return rss_hf;
6479         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6480                 rss_hf |= ETH_RSS_FRAG_IPV4;
6481         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6482                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6483         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6484                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6485         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6486                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6487         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6488                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6489         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6490                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6491         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6492                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6493         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6494                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6495         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6496                 rss_hf |= ETH_RSS_FRAG_IPV6;
6497         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6498                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6499         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6500                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6501         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6502                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6503         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6504                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6505         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6506                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6507         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6508                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6509         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6510                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6511         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6512                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6513
6514         return rss_hf;
6515 }
6516
6517 /* Disable RSS */
6518 static void
6519 i40e_pf_disable_rss(struct i40e_pf *pf)
6520 {
6521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6522         uint64_t hena;
6523
6524         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6525         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6526         if (hw->mac.type == I40E_MAC_X722)
6527                 hena &= ~I40E_RSS_HENA_ALL_X722;
6528         else
6529                 hena &= ~I40E_RSS_HENA_ALL;
6530         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6531         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6532         I40E_WRITE_FLUSH(hw);
6533 }
6534
6535 static int
6536 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6537 {
6538         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6539         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6540         int ret = 0;
6541
6542         if (!key || key_len == 0) {
6543                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6544                 return 0;
6545         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6546                 sizeof(uint32_t)) {
6547                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6548                 return -EINVAL;
6549         }
6550
6551         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6552                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6553                         (struct i40e_aqc_get_set_rss_key_data *)key;
6554
6555                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6556                 if (ret)
6557                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6558                                      "via AQ");
6559         } else {
6560                 uint32_t *hash_key = (uint32_t *)key;
6561                 uint16_t i;
6562
6563                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6564                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6565                 I40E_WRITE_FLUSH(hw);
6566         }
6567
6568         return ret;
6569 }
6570
6571 static int
6572 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6573 {
6574         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6575         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6576         int ret;
6577
6578         if (!key || !key_len)
6579                 return -EINVAL;
6580
6581         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6582                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6583                         (struct i40e_aqc_get_set_rss_key_data *)key);
6584                 if (ret) {
6585                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6586                         return ret;
6587                 }
6588         } else {
6589                 uint32_t *key_dw = (uint32_t *)key;
6590                 uint16_t i;
6591
6592                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6593                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6594         }
6595         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6596
6597         return 0;
6598 }
6599
6600 static int
6601 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6602 {
6603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6604         uint64_t rss_hf;
6605         uint64_t hena;
6606         int ret;
6607
6608         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6609                                rss_conf->rss_key_len);
6610         if (ret)
6611                 return ret;
6612
6613         rss_hf = rss_conf->rss_hf;
6614         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6615         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6616         if (hw->mac.type == I40E_MAC_X722)
6617                 hena &= ~I40E_RSS_HENA_ALL_X722;
6618         else
6619                 hena &= ~I40E_RSS_HENA_ALL;
6620         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6621         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6622         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6623         I40E_WRITE_FLUSH(hw);
6624
6625         return 0;
6626 }
6627
6628 static int
6629 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6630                          struct rte_eth_rss_conf *rss_conf)
6631 {
6632         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6633         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6634         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6635         uint64_t hena;
6636
6637         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6638         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6639         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6640                  ? I40E_RSS_HENA_ALL_X722
6641                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6642                 if (rss_hf != 0) /* Enable RSS */
6643                         return -EINVAL;
6644                 return 0; /* Nothing to do */
6645         }
6646         /* RSS enabled */
6647         if (rss_hf == 0) /* Disable RSS */
6648                 return -EINVAL;
6649
6650         return i40e_hw_rss_hash_set(pf, rss_conf);
6651 }
6652
6653 static int
6654 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6655                            struct rte_eth_rss_conf *rss_conf)
6656 {
6657         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6659         uint64_t hena;
6660
6661         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6662                          &rss_conf->rss_key_len);
6663
6664         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6665         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6666         rss_conf->rss_hf = i40e_parse_hena(hena);
6667
6668         return 0;
6669 }
6670
6671 static int
6672 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6673 {
6674         switch (filter_type) {
6675         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6676                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6677                 break;
6678         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6679                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6680                 break;
6681         case RTE_TUNNEL_FILTER_IMAC_TENID:
6682                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6683                 break;
6684         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6685                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6686                 break;
6687         case ETH_TUNNEL_FILTER_IMAC:
6688                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6689                 break;
6690         case ETH_TUNNEL_FILTER_OIP:
6691                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6692                 break;
6693         case ETH_TUNNEL_FILTER_IIP:
6694                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6695                 break;
6696         default:
6697                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6698                 return -EINVAL;
6699         }
6700
6701         return 0;
6702 }
6703
6704 /* Convert tunnel filter structure */
6705 static int
6706 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6707                            *cld_filter,
6708                            struct i40e_tunnel_filter *tunnel_filter)
6709 {
6710         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6711                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6712         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6713                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6714         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6715         tunnel_filter->input.flags = cld_filter->flags;
6716         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6717         tunnel_filter->queue = cld_filter->queue_number;
6718
6719         return 0;
6720 }
6721
6722 /* Check if there exists the tunnel filter */
6723 struct i40e_tunnel_filter *
6724 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6725                              const struct i40e_tunnel_filter_input *input)
6726 {
6727         int ret;
6728
6729         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6730         if (ret < 0)
6731                 return NULL;
6732
6733         return tunnel_rule->hash_map[ret];
6734 }
6735
6736 /* Add a tunnel filter into the SW list */
6737 static int
6738 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6739                              struct i40e_tunnel_filter *tunnel_filter)
6740 {
6741         struct i40e_tunnel_rule *rule = &pf->tunnel;
6742         int ret;
6743
6744         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6745         if (ret < 0) {
6746                 PMD_DRV_LOG(ERR,
6747                             "Failed to insert tunnel filter to hash table %d!",
6748                             ret);
6749                 return ret;
6750         }
6751         rule->hash_map[ret] = tunnel_filter;
6752
6753         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6754
6755         return 0;
6756 }
6757
6758 /* Delete a tunnel filter from the SW list */
6759 int
6760 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6761                           struct i40e_tunnel_filter_input *input)
6762 {
6763         struct i40e_tunnel_rule *rule = &pf->tunnel;
6764         struct i40e_tunnel_filter *tunnel_filter;
6765         int ret;
6766
6767         ret = rte_hash_del_key(rule->hash_table, input);
6768         if (ret < 0) {
6769                 PMD_DRV_LOG(ERR,
6770                             "Failed to delete tunnel filter to hash table %d!",
6771                             ret);
6772                 return ret;
6773         }
6774         tunnel_filter = rule->hash_map[ret];
6775         rule->hash_map[ret] = NULL;
6776
6777         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6778         rte_free(tunnel_filter);
6779
6780         return 0;
6781 }
6782
6783 static int
6784 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6785                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6786                         uint8_t add)
6787 {
6788         uint16_t ip_type;
6789         uint32_t ipv4_addr;
6790         uint8_t i, tun_type = 0;
6791         /* internal varialbe to convert ipv6 byte order */
6792         uint32_t convert_ipv6[4];
6793         int val, ret = 0;
6794         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6795         struct i40e_vsi *vsi = pf->main_vsi;
6796         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6797         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6798         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6799         struct i40e_tunnel_filter *tunnel, *node;
6800         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6801
6802         cld_filter = rte_zmalloc("tunnel_filter",
6803                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6804                 0);
6805
6806         if (NULL == cld_filter) {
6807                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6808                 return -EINVAL;
6809         }
6810         pfilter = cld_filter;
6811
6812         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6813         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6814
6815         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6816         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6817                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6818                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6819                 rte_memcpy(&pfilter->ipaddr.v4.data,
6820                                 &rte_cpu_to_le_32(ipv4_addr),
6821                                 sizeof(pfilter->ipaddr.v4.data));
6822         } else {
6823                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6824                 for (i = 0; i < 4; i++) {
6825                         convert_ipv6[i] =
6826                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6827                 }
6828                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6829                                 sizeof(pfilter->ipaddr.v6.data));
6830         }
6831
6832         /* check tunneled type */
6833         switch (tunnel_filter->tunnel_type) {
6834         case RTE_TUNNEL_TYPE_VXLAN:
6835                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6836                 break;
6837         case RTE_TUNNEL_TYPE_NVGRE:
6838                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6839                 break;
6840         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6841                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6842                 break;
6843         default:
6844                 /* Other tunnel types is not supported. */
6845                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6846                 rte_free(cld_filter);
6847                 return -EINVAL;
6848         }
6849
6850         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6851                                                 &pfilter->flags);
6852         if (val < 0) {
6853                 rte_free(cld_filter);
6854                 return -EINVAL;
6855         }
6856
6857         pfilter->flags |= rte_cpu_to_le_16(
6858                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6859                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6860         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6861         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6862
6863         /* Check if there is the filter in SW list */
6864         memset(&check_filter, 0, sizeof(check_filter));
6865         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6866         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6867         if (add && node) {
6868                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6869                 return -EINVAL;
6870         }
6871
6872         if (!add && !node) {
6873                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6874                 return -EINVAL;
6875         }
6876
6877         if (add) {
6878                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6879                 if (ret < 0) {
6880                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6881                         return ret;
6882                 }
6883                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6884                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6885                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6886         } else {
6887                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6888                                                    cld_filter, 1);
6889                 if (ret < 0) {
6890                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6891                         return ret;
6892                 }
6893                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6894         }
6895
6896         rte_free(cld_filter);
6897         return ret;
6898 }
6899
6900 static int
6901 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6902 {
6903         uint8_t i;
6904
6905         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6906                 if (pf->vxlan_ports[i] == port)
6907                         return i;
6908         }
6909
6910         return -1;
6911 }
6912
6913 static int
6914 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6915 {
6916         int  idx, ret;
6917         uint8_t filter_idx;
6918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6919
6920         idx = i40e_get_vxlan_port_idx(pf, port);
6921
6922         /* Check if port already exists */
6923         if (idx >= 0) {
6924                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6925                 return -EINVAL;
6926         }
6927
6928         /* Now check if there is space to add the new port */
6929         idx = i40e_get_vxlan_port_idx(pf, 0);
6930         if (idx < 0) {
6931                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6932                         "not adding port %d", port);
6933                 return -ENOSPC;
6934         }
6935
6936         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6937                                         &filter_idx, NULL);
6938         if (ret < 0) {
6939                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6940                 return -1;
6941         }
6942
6943         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6944                          port,  filter_idx);
6945
6946         /* New port: add it and mark its index in the bitmap */
6947         pf->vxlan_ports[idx] = port;
6948         pf->vxlan_bitmap |= (1 << idx);
6949
6950         if (!(pf->flags & I40E_FLAG_VXLAN))
6951                 pf->flags |= I40E_FLAG_VXLAN;
6952
6953         return 0;
6954 }
6955
6956 static int
6957 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6958 {
6959         int idx;
6960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6961
6962         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6963                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6964                 return -EINVAL;
6965         }
6966
6967         idx = i40e_get_vxlan_port_idx(pf, port);
6968
6969         if (idx < 0) {
6970                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6971                 return -EINVAL;
6972         }
6973
6974         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6975                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6976                 return -1;
6977         }
6978
6979         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6980                         port, idx);
6981
6982         pf->vxlan_ports[idx] = 0;
6983         pf->vxlan_bitmap &= ~(1 << idx);
6984
6985         if (!pf->vxlan_bitmap)
6986                 pf->flags &= ~I40E_FLAG_VXLAN;
6987
6988         return 0;
6989 }
6990
6991 /* Add UDP tunneling port */
6992 static int
6993 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6994                              struct rte_eth_udp_tunnel *udp_tunnel)
6995 {
6996         int ret = 0;
6997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6998
6999         if (udp_tunnel == NULL)
7000                 return -EINVAL;
7001
7002         switch (udp_tunnel->prot_type) {
7003         case RTE_TUNNEL_TYPE_VXLAN:
7004                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7005                 break;
7006
7007         case RTE_TUNNEL_TYPE_GENEVE:
7008         case RTE_TUNNEL_TYPE_TEREDO:
7009                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7010                 ret = -1;
7011                 break;
7012
7013         default:
7014                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7015                 ret = -1;
7016                 break;
7017         }
7018
7019         return ret;
7020 }
7021
7022 /* Remove UDP tunneling port */
7023 static int
7024 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7025                              struct rte_eth_udp_tunnel *udp_tunnel)
7026 {
7027         int ret = 0;
7028         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7029
7030         if (udp_tunnel == NULL)
7031                 return -EINVAL;
7032
7033         switch (udp_tunnel->prot_type) {
7034         case RTE_TUNNEL_TYPE_VXLAN:
7035                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7036                 break;
7037         case RTE_TUNNEL_TYPE_GENEVE:
7038         case RTE_TUNNEL_TYPE_TEREDO:
7039                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7040                 ret = -1;
7041                 break;
7042         default:
7043                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7044                 ret = -1;
7045                 break;
7046         }
7047
7048         return ret;
7049 }
7050
7051 /* Calculate the maximum number of contiguous PF queues that are configured */
7052 static int
7053 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7054 {
7055         struct rte_eth_dev_data *data = pf->dev_data;
7056         int i, num;
7057         struct i40e_rx_queue *rxq;
7058
7059         num = 0;
7060         for (i = 0; i < pf->lan_nb_qps; i++) {
7061                 rxq = data->rx_queues[i];
7062                 if (rxq && rxq->q_set)
7063                         num++;
7064                 else
7065                         break;
7066         }
7067
7068         return num;
7069 }
7070
7071 /* Configure RSS */
7072 static int
7073 i40e_pf_config_rss(struct i40e_pf *pf)
7074 {
7075         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7076         struct rte_eth_rss_conf rss_conf;
7077         uint32_t i, lut = 0;
7078         uint16_t j, num;
7079
7080         /*
7081          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7082          * It's necessary to calulate the actual PF queues that are configured.
7083          */
7084         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7085                 num = i40e_pf_calc_configured_queues_num(pf);
7086         else
7087                 num = pf->dev_data->nb_rx_queues;
7088
7089         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7090         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7091                         num);
7092
7093         if (num == 0) {
7094                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7095                 return -ENOTSUP;
7096         }
7097
7098         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7099                 if (j == num)
7100                         j = 0;
7101                 lut = (lut << 8) | (j & ((0x1 <<
7102                         hw->func_caps.rss_table_entry_width) - 1));
7103                 if ((i & 3) == 3)
7104                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7105         }
7106
7107         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7108         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7109                 i40e_pf_disable_rss(pf);
7110                 return 0;
7111         }
7112         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7113                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7114                 /* Random default keys */
7115                 static uint32_t rss_key_default[] = {0x6b793944,
7116                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7117                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7118                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7119
7120                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7121                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7122                                                         sizeof(uint32_t);
7123         }
7124
7125         return i40e_hw_rss_hash_set(pf, &rss_conf);
7126 }
7127
7128 static int
7129 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7130                                struct rte_eth_tunnel_filter_conf *filter)
7131 {
7132         if (pf == NULL || filter == NULL) {
7133                 PMD_DRV_LOG(ERR, "Invalid parameter");
7134                 return -EINVAL;
7135         }
7136
7137         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7138                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7139                 return -EINVAL;
7140         }
7141
7142         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7143                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7144                 return -EINVAL;
7145         }
7146
7147         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7148                 (is_zero_ether_addr(&filter->outer_mac))) {
7149                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7150                 return -EINVAL;
7151         }
7152
7153         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7154                 (is_zero_ether_addr(&filter->inner_mac))) {
7155                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7156                 return -EINVAL;
7157         }
7158
7159         return 0;
7160 }
7161
7162 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7163 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7164 static int
7165 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7166 {
7167         uint32_t val, reg;
7168         int ret = -EINVAL;
7169
7170         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7171         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7172
7173         if (len == 3) {
7174                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7175         } else if (len == 4) {
7176                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7177         } else {
7178                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7179                 return ret;
7180         }
7181
7182         if (reg != val) {
7183                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7184                                                    reg, NULL);
7185                 if (ret != 0)
7186                         return ret;
7187         } else {
7188                 ret = 0;
7189         }
7190         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7191                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7192
7193         return ret;
7194 }
7195
7196 static int
7197 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7198 {
7199         int ret = -EINVAL;
7200
7201         if (!hw || !cfg)
7202                 return -EINVAL;
7203
7204         switch (cfg->cfg_type) {
7205         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7206                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7207                 break;
7208         default:
7209                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7210                 break;
7211         }
7212
7213         return ret;
7214 }
7215
7216 static int
7217 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7218                                enum rte_filter_op filter_op,
7219                                void *arg)
7220 {
7221         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7222         int ret = I40E_ERR_PARAM;
7223
7224         switch (filter_op) {
7225         case RTE_ETH_FILTER_SET:
7226                 ret = i40e_dev_global_config_set(hw,
7227                         (struct rte_eth_global_cfg *)arg);
7228                 break;
7229         default:
7230                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7231                 break;
7232         }
7233
7234         return ret;
7235 }
7236
7237 static int
7238 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7239                           enum rte_filter_op filter_op,
7240                           void *arg)
7241 {
7242         struct rte_eth_tunnel_filter_conf *filter;
7243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7244         int ret = I40E_SUCCESS;
7245
7246         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7247
7248         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7249                 return I40E_ERR_PARAM;
7250
7251         switch (filter_op) {
7252         case RTE_ETH_FILTER_NOP:
7253                 if (!(pf->flags & I40E_FLAG_VXLAN))
7254                         ret = I40E_NOT_SUPPORTED;
7255                 break;
7256         case RTE_ETH_FILTER_ADD:
7257                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7258                 break;
7259         case RTE_ETH_FILTER_DELETE:
7260                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7261                 break;
7262         default:
7263                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7264                 ret = I40E_ERR_PARAM;
7265                 break;
7266         }
7267
7268         return ret;
7269 }
7270
7271 static int
7272 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7273 {
7274         int ret = 0;
7275         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7276
7277         /* RSS setup */
7278         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7279                 ret = i40e_pf_config_rss(pf);
7280         else
7281                 i40e_pf_disable_rss(pf);
7282
7283         return ret;
7284 }
7285
7286 /* Get the symmetric hash enable configurations per port */
7287 static void
7288 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7289 {
7290         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7291
7292         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7293 }
7294
7295 /* Set the symmetric hash enable configurations per port */
7296 static void
7297 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7298 {
7299         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7300
7301         if (enable > 0) {
7302                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7303                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7304                                                         "been enabled");
7305                         return;
7306                 }
7307                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7308         } else {
7309                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7310                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7311                                                         "been disabled");
7312                         return;
7313                 }
7314                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7315         }
7316         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7317         I40E_WRITE_FLUSH(hw);
7318 }
7319
7320 /*
7321  * Get global configurations of hash function type and symmetric hash enable
7322  * per flow type (pctype). Note that global configuration means it affects all
7323  * the ports on the same NIC.
7324  */
7325 static int
7326 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7327                                    struct rte_eth_hash_global_conf *g_cfg)
7328 {
7329         uint32_t reg, mask = I40E_FLOW_TYPES;
7330         uint16_t i;
7331         enum i40e_filter_pctype pctype;
7332
7333         memset(g_cfg, 0, sizeof(*g_cfg));
7334         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7335         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7336                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7337         else
7338                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7339         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7340                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7341
7342         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7343                 if (!(mask & (1UL << i)))
7344                         continue;
7345                 mask &= ~(1UL << i);
7346                 /* Bit set indicats the coresponding flow type is supported */
7347                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7348                 /* if flowtype is invalid, continue */
7349                 if (!I40E_VALID_FLOW(i))
7350                         continue;
7351                 pctype = i40e_flowtype_to_pctype(i);
7352                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7353                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7354                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7355         }
7356
7357         return 0;
7358 }
7359
7360 static int
7361 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7362 {
7363         uint32_t i;
7364         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7365
7366         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7367                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7368                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7369                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7370                                                 g_cfg->hash_func);
7371                 return -EINVAL;
7372         }
7373
7374         /*
7375          * As i40e supports less than 32 flow types, only first 32 bits need to
7376          * be checked.
7377          */
7378         mask0 = g_cfg->valid_bit_mask[0];
7379         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7380                 if (i == 0) {
7381                         /* Check if any unsupported flow type configured */
7382                         if ((mask0 | i40e_mask) ^ i40e_mask)
7383                                 goto mask_err;
7384                 } else {
7385                         if (g_cfg->valid_bit_mask[i])
7386                                 goto mask_err;
7387                 }
7388         }
7389
7390         return 0;
7391
7392 mask_err:
7393         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7394
7395         return -EINVAL;
7396 }
7397
7398 /*
7399  * Set global configurations of hash function type and symmetric hash enable
7400  * per flow type (pctype). Note any modifying global configuration will affect
7401  * all the ports on the same NIC.
7402  */
7403 static int
7404 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7405                                    struct rte_eth_hash_global_conf *g_cfg)
7406 {
7407         int ret;
7408         uint16_t i;
7409         uint32_t reg;
7410         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7411         enum i40e_filter_pctype pctype;
7412
7413         /* Check the input parameters */
7414         ret = i40e_hash_global_config_check(g_cfg);
7415         if (ret < 0)
7416                 return ret;
7417
7418         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7419                 if (!(mask0 & (1UL << i)))
7420                         continue;
7421                 mask0 &= ~(1UL << i);
7422                 /* if flowtype is invalid, continue */
7423                 if (!I40E_VALID_FLOW(i))
7424                         continue;
7425                 pctype = i40e_flowtype_to_pctype(i);
7426                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7427                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7428                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7429         }
7430
7431         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7432         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7433                 /* Toeplitz */
7434                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7435                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7436                                                                 "Toeplitz");
7437                         goto out;
7438                 }
7439                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7440         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7441                 /* Simple XOR */
7442                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7443                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7444                                                         "Simple XOR");
7445                         goto out;
7446                 }
7447                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7448         } else
7449                 /* Use the default, and keep it as it is */
7450                 goto out;
7451
7452         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7453
7454 out:
7455         I40E_WRITE_FLUSH(hw);
7456
7457         return 0;
7458 }
7459
7460 /**
7461  * Valid input sets for hash and flow director filters per PCTYPE
7462  */
7463 static uint64_t
7464 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7465                 enum rte_filter_type filter)
7466 {
7467         uint64_t valid;
7468
7469         static const uint64_t valid_hash_inset_table[] = {
7470                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7471                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7472                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7473                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7474                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7475                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7476                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7477                         I40E_INSET_FLEX_PAYLOAD,
7478                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7479                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7480                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7481                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7482                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7483                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7484                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7485                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7486                         I40E_INSET_FLEX_PAYLOAD,
7487                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7488                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7489                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7490                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7491                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7492                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7493                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7494                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7495                         I40E_INSET_FLEX_PAYLOAD,
7496                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7497                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7498                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7499                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7500                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7501                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7502                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7503                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7504                         I40E_INSET_FLEX_PAYLOAD,
7505                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7506                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7507                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7508                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7509                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7510                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7511                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7512                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7513                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7514                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7515                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7516                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7517                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7518                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7519                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7520                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7521                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7522                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7523                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7524                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7525                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7526                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7527                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7528                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7529                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7530                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7531                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7532                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7533                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7534                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7535                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7536                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7537                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7538                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7539                         I40E_INSET_FLEX_PAYLOAD,
7540                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7541                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7542                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7543                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7544                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7545                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7546                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7547                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7548                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7549                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7550                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7551                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7552                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7553                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7554                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7555                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7556                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7557                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7558                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7559                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7560                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7561                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7562                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7563                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7564                         I40E_INSET_FLEX_PAYLOAD,
7565                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7566                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7567                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7568                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7569                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7570                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7571                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7572                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7573                         I40E_INSET_FLEX_PAYLOAD,
7574                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7575                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7576                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7577                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7578                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7579                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7580                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7581                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7582                         I40E_INSET_FLEX_PAYLOAD,
7583                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7584                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7585                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7586                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7587                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7588                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7589                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7590                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7591                         I40E_INSET_FLEX_PAYLOAD,
7592                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7593                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7594                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7595                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7596                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7597                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7598                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7599                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7600                         I40E_INSET_FLEX_PAYLOAD,
7601                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7602                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7603                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7604                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7605                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7606                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7607                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7608                         I40E_INSET_FLEX_PAYLOAD,
7609                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7610                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7611                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7613                         I40E_INSET_FLEX_PAYLOAD,
7614         };
7615
7616         /**
7617          * Flow director supports only fields defined in
7618          * union rte_eth_fdir_flow.
7619          */
7620         static const uint64_t valid_fdir_inset_table[] = {
7621                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7622                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7624                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7625                 I40E_INSET_IPV4_TTL,
7626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7627                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7629                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7630                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7632                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7634                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7635                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7637                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7639                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7640                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7642                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7644                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7645                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7647                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7649                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7650                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7651                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7652                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7654                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7655                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7656                 I40E_INSET_SCTP_VT,
7657                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7658                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7659                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7660                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7661                 I40E_INSET_IPV4_TTL,
7662                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7663                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7664                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7665                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7666                 I40E_INSET_IPV6_HOP_LIMIT,
7667                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7668                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7669                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7670                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7671                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7672                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7673                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7674                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7675                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7676                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7677                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7678                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7679                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7680                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7681                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7682                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7683                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7684                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7685                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7686                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7687                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7688                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7689                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7690                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7691                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7692                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7693                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7694                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7695                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7696                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7697                 I40E_INSET_SCTP_VT,
7698                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7699                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7700                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7701                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7702                 I40E_INSET_IPV6_HOP_LIMIT,
7703                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7704                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7705                 I40E_INSET_LAST_ETHER_TYPE,
7706         };
7707
7708         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7709                 return 0;
7710         if (filter == RTE_ETH_FILTER_HASH)
7711                 valid = valid_hash_inset_table[pctype];
7712         else
7713                 valid = valid_fdir_inset_table[pctype];
7714
7715         return valid;
7716 }
7717
7718 /**
7719  * Validate if the input set is allowed for a specific PCTYPE
7720  */
7721 static int
7722 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7723                 enum rte_filter_type filter, uint64_t inset)
7724 {
7725         uint64_t valid;
7726
7727         valid = i40e_get_valid_input_set(pctype, filter);
7728         if (inset & (~valid))
7729                 return -EINVAL;
7730
7731         return 0;
7732 }
7733
7734 /* default input set fields combination per pctype */
7735 static uint64_t
7736 i40e_get_default_input_set(uint16_t pctype)
7737 {
7738         static const uint64_t default_inset_table[] = {
7739                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7740                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7741                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7742                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7743                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7744                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7745                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7747                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7750                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7759                         I40E_INSET_SCTP_VT,
7760                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7761                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7762                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7763                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7764                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7765                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7766                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7767                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7768                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7770                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7771                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7773                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7782                         I40E_INSET_SCTP_VT,
7783                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7784                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7785                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7786                         I40E_INSET_LAST_ETHER_TYPE,
7787         };
7788
7789         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7790                 return 0;
7791
7792         return default_inset_table[pctype];
7793 }
7794
7795 /**
7796  * Parse the input set from index to logical bit masks
7797  */
7798 static int
7799 i40e_parse_input_set(uint64_t *inset,
7800                      enum i40e_filter_pctype pctype,
7801                      enum rte_eth_input_set_field *field,
7802                      uint16_t size)
7803 {
7804         uint16_t i, j;
7805         int ret = -EINVAL;
7806
7807         static const struct {
7808                 enum rte_eth_input_set_field field;
7809                 uint64_t inset;
7810         } inset_convert_table[] = {
7811                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7812                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7813                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7814                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7815                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7816                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7817                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7818                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7819                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7820                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7821                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7822                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7823                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7824                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7825                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7826                         I40E_INSET_IPV6_NEXT_HDR},
7827                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7828                         I40E_INSET_IPV6_HOP_LIMIT},
7829                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7830                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7831                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7832                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7833                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7834                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7835                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7836                         I40E_INSET_SCTP_VT},
7837                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7838                         I40E_INSET_TUNNEL_DMAC},
7839                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7840                         I40E_INSET_VLAN_TUNNEL},
7841                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7842                         I40E_INSET_TUNNEL_ID},
7843                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7844                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7845                         I40E_INSET_FLEX_PAYLOAD_W1},
7846                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7847                         I40E_INSET_FLEX_PAYLOAD_W2},
7848                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7849                         I40E_INSET_FLEX_PAYLOAD_W3},
7850                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7851                         I40E_INSET_FLEX_PAYLOAD_W4},
7852                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7853                         I40E_INSET_FLEX_PAYLOAD_W5},
7854                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7855                         I40E_INSET_FLEX_PAYLOAD_W6},
7856                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7857                         I40E_INSET_FLEX_PAYLOAD_W7},
7858                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7859                         I40E_INSET_FLEX_PAYLOAD_W8},
7860         };
7861
7862         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7863                 return ret;
7864
7865         /* Only one item allowed for default or all */
7866         if (size == 1) {
7867                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7868                         *inset = i40e_get_default_input_set(pctype);
7869                         return 0;
7870                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7871                         *inset = I40E_INSET_NONE;
7872                         return 0;
7873                 }
7874         }
7875
7876         for (i = 0, *inset = 0; i < size; i++) {
7877                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7878                         if (field[i] == inset_convert_table[j].field) {
7879                                 *inset |= inset_convert_table[j].inset;
7880                                 break;
7881                         }
7882                 }
7883
7884                 /* It contains unsupported input set, return immediately */
7885                 if (j == RTE_DIM(inset_convert_table))
7886                         return ret;
7887         }
7888
7889         return 0;
7890 }
7891
7892 /**
7893  * Translate the input set from bit masks to register aware bit masks
7894  * and vice versa
7895  */
7896 static uint64_t
7897 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7898 {
7899         uint64_t val = 0;
7900         uint16_t i;
7901
7902         struct inset_map {
7903                 uint64_t inset;
7904                 uint64_t inset_reg;
7905         };
7906
7907         static const struct inset_map inset_map_common[] = {
7908                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7909                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7910                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7911                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7912                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7913                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7914                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7915                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7916                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7917                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7918                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7919                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7920                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7921                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7922                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7923                 {I40E_INSET_TUNNEL_DMAC,
7924                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7925                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7926                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7927                 {I40E_INSET_TUNNEL_SRC_PORT,
7928                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7929                 {I40E_INSET_TUNNEL_DST_PORT,
7930                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7931                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7932                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7933                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7934                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7935                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7936                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7937                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7938                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7939                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7940         };
7941
7942     /* some different registers map in x722*/
7943         static const struct inset_map inset_map_diff_x722[] = {
7944                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7945                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7946                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7947                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7948         };
7949
7950         static const struct inset_map inset_map_diff_not_x722[] = {
7951                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7952                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7953                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7954                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7955         };
7956
7957         if (input == 0)
7958                 return val;
7959
7960         /* Translate input set to register aware inset */
7961         if (type == I40E_MAC_X722) {
7962                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7963                         if (input & inset_map_diff_x722[i].inset)
7964                                 val |= inset_map_diff_x722[i].inset_reg;
7965                 }
7966         } else {
7967                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7968                         if (input & inset_map_diff_not_x722[i].inset)
7969                                 val |= inset_map_diff_not_x722[i].inset_reg;
7970                 }
7971         }
7972
7973         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7974                 if (input & inset_map_common[i].inset)
7975                         val |= inset_map_common[i].inset_reg;
7976         }
7977
7978         return val;
7979 }
7980
7981 static int
7982 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7983 {
7984         uint8_t i, idx = 0;
7985         uint64_t inset_need_mask = inset;
7986
7987         static const struct {
7988                 uint64_t inset;
7989                 uint32_t mask;
7990         } inset_mask_map[] = {
7991                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7992                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7993                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7994                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7995                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7996                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7997                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7998                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7999         };
8000
8001         if (!inset || !mask || !nb_elem)
8002                 return 0;
8003
8004         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8005                 /* Clear the inset bit, if no MASK is required,
8006                  * for example proto + ttl
8007                  */
8008                 if ((inset & inset_mask_map[i].inset) ==
8009                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8010                         inset_need_mask &= ~inset_mask_map[i].inset;
8011                 if (!inset_need_mask)
8012                         return 0;
8013         }
8014         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8015                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8016                     inset_mask_map[i].inset) {
8017                         if (idx >= nb_elem) {
8018                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8019                                 return -EINVAL;
8020                         }
8021                         mask[idx] = inset_mask_map[i].mask;
8022                         idx++;
8023                 }
8024         }
8025
8026         return idx;
8027 }
8028
8029 static void
8030 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8031 {
8032         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8033
8034         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8035         if (reg != val)
8036                 i40e_write_rx_ctl(hw, addr, val);
8037         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8038                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8039 }
8040
8041 static void
8042 i40e_filter_input_set_init(struct i40e_pf *pf)
8043 {
8044         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8045         enum i40e_filter_pctype pctype;
8046         uint64_t input_set, inset_reg;
8047         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8048         int num, i;
8049
8050         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8051              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8052                 if (hw->mac.type == I40E_MAC_X722) {
8053                         if (!I40E_VALID_PCTYPE_X722(pctype))
8054                                 continue;
8055                 } else {
8056                         if (!I40E_VALID_PCTYPE(pctype))
8057                                 continue;
8058                 }
8059
8060                 input_set = i40e_get_default_input_set(pctype);
8061
8062                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8063                                                    I40E_INSET_MASK_NUM_REG);
8064                 if (num < 0)
8065                         return;
8066                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8067                                         input_set);
8068
8069                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8070                                       (uint32_t)(inset_reg & UINT32_MAX));
8071                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8072                                      (uint32_t)((inset_reg >>
8073                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8074                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8075                                       (uint32_t)(inset_reg & UINT32_MAX));
8076                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8077                                      (uint32_t)((inset_reg >>
8078                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8079
8080                 for (i = 0; i < num; i++) {
8081                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8082                                              mask_reg[i]);
8083                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8084                                              mask_reg[i]);
8085                 }
8086                 /*clear unused mask registers of the pctype */
8087                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8088                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8089                                              0);
8090                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8091                                              0);
8092                 }
8093                 I40E_WRITE_FLUSH(hw);
8094
8095                 /* store the default input set */
8096                 pf->hash_input_set[pctype] = input_set;
8097                 pf->fdir.input_set[pctype] = input_set;
8098         }
8099 }
8100
8101 int
8102 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8103                          struct rte_eth_input_set_conf *conf)
8104 {
8105         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8106         enum i40e_filter_pctype pctype;
8107         uint64_t input_set, inset_reg = 0;
8108         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8109         int ret, i, num;
8110
8111         if (!conf) {
8112                 PMD_DRV_LOG(ERR, "Invalid pointer");
8113                 return -EFAULT;
8114         }
8115         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8116             conf->op != RTE_ETH_INPUT_SET_ADD) {
8117                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8118                 return -EINVAL;
8119         }
8120
8121         if (!I40E_VALID_FLOW(conf->flow_type)) {
8122                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8123                 return -EINVAL;
8124         }
8125
8126         if (hw->mac.type == I40E_MAC_X722) {
8127                 /* get translated pctype value in fd pctype register */
8128                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8129                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8130                         conf->flow_type)));
8131         } else
8132                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8133
8134         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8135                                    conf->inset_size);
8136         if (ret) {
8137                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8138                 return -EINVAL;
8139         }
8140         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8141                                     input_set) != 0) {
8142                 PMD_DRV_LOG(ERR, "Invalid input set");
8143                 return -EINVAL;
8144         }
8145         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8146                 /* get inset value in register */
8147                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8148                 inset_reg <<= I40E_32_BIT_WIDTH;
8149                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8150                 input_set |= pf->hash_input_set[pctype];
8151         }
8152         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8153                                            I40E_INSET_MASK_NUM_REG);
8154         if (num < 0)
8155                 return -EINVAL;
8156
8157         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8158
8159         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8160                               (uint32_t)(inset_reg & UINT32_MAX));
8161         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8162                              (uint32_t)((inset_reg >>
8163                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8164
8165         for (i = 0; i < num; i++)
8166                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8167                                      mask_reg[i]);
8168         /*clear unused mask registers of the pctype */
8169         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8170                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8171                                      0);
8172         I40E_WRITE_FLUSH(hw);
8173
8174         pf->hash_input_set[pctype] = input_set;
8175         return 0;
8176 }
8177
8178 int
8179 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8180                          struct rte_eth_input_set_conf *conf)
8181 {
8182         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8183         enum i40e_filter_pctype pctype;
8184         uint64_t input_set, inset_reg = 0;
8185         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8186         int ret, i, num;
8187
8188         if (!hw || !conf) {
8189                 PMD_DRV_LOG(ERR, "Invalid pointer");
8190                 return -EFAULT;
8191         }
8192         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8193             conf->op != RTE_ETH_INPUT_SET_ADD) {
8194                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8195                 return -EINVAL;
8196         }
8197
8198         if (!I40E_VALID_FLOW(conf->flow_type)) {
8199                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8200                 return -EINVAL;
8201         }
8202
8203         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8204
8205         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8206                                    conf->inset_size);
8207         if (ret) {
8208                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8209                 return -EINVAL;
8210         }
8211         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8212                                     input_set) != 0) {
8213                 PMD_DRV_LOG(ERR, "Invalid input set");
8214                 return -EINVAL;
8215         }
8216
8217         /* get inset value in register */
8218         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8219         inset_reg <<= I40E_32_BIT_WIDTH;
8220         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8221
8222         /* Can not change the inset reg for flex payload for fdir,
8223          * it is done by writing I40E_PRTQF_FD_FLXINSET
8224          * in i40e_set_flex_mask_on_pctype.
8225          */
8226         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8227                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8228         else
8229                 input_set |= pf->fdir.input_set[pctype];
8230         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8231                                            I40E_INSET_MASK_NUM_REG);
8232         if (num < 0)
8233                 return -EINVAL;
8234
8235         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8236
8237         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8238                               (uint32_t)(inset_reg & UINT32_MAX));
8239         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8240                              (uint32_t)((inset_reg >>
8241                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8242
8243         for (i = 0; i < num; i++)
8244                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8245                                      mask_reg[i]);
8246         /*clear unused mask registers of the pctype */
8247         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8248                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8249                                      0);
8250         I40E_WRITE_FLUSH(hw);
8251
8252         pf->fdir.input_set[pctype] = input_set;
8253         return 0;
8254 }
8255
8256 static int
8257 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8258 {
8259         int ret = 0;
8260
8261         if (!hw || !info) {
8262                 PMD_DRV_LOG(ERR, "Invalid pointer");
8263                 return -EFAULT;
8264         }
8265
8266         switch (info->info_type) {
8267         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8268                 i40e_get_symmetric_hash_enable_per_port(hw,
8269                                         &(info->info.enable));
8270                 break;
8271         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8272                 ret = i40e_get_hash_filter_global_config(hw,
8273                                 &(info->info.global_conf));
8274                 break;
8275         default:
8276                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8277                                                         info->info_type);
8278                 ret = -EINVAL;
8279                 break;
8280         }
8281
8282         return ret;
8283 }
8284
8285 static int
8286 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8287 {
8288         int ret = 0;
8289
8290         if (!hw || !info) {
8291                 PMD_DRV_LOG(ERR, "Invalid pointer");
8292                 return -EFAULT;
8293         }
8294
8295         switch (info->info_type) {
8296         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8297                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8298                 break;
8299         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8300                 ret = i40e_set_hash_filter_global_config(hw,
8301                                 &(info->info.global_conf));
8302                 break;
8303         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8304                 ret = i40e_hash_filter_inset_select(hw,
8305                                                &(info->info.input_set_conf));
8306                 break;
8307
8308         default:
8309                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8310                                                         info->info_type);
8311                 ret = -EINVAL;
8312                 break;
8313         }
8314
8315         return ret;
8316 }
8317
8318 /* Operations for hash function */
8319 static int
8320 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8321                       enum rte_filter_op filter_op,
8322                       void *arg)
8323 {
8324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8325         int ret = 0;
8326
8327         switch (filter_op) {
8328         case RTE_ETH_FILTER_NOP:
8329                 break;
8330         case RTE_ETH_FILTER_GET:
8331                 ret = i40e_hash_filter_get(hw,
8332                         (struct rte_eth_hash_filter_info *)arg);
8333                 break;
8334         case RTE_ETH_FILTER_SET:
8335                 ret = i40e_hash_filter_set(hw,
8336                         (struct rte_eth_hash_filter_info *)arg);
8337                 break;
8338         default:
8339                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8340                                                                 filter_op);
8341                 ret = -ENOTSUP;
8342                 break;
8343         }
8344
8345         return ret;
8346 }
8347
8348 /* Convert ethertype filter structure */
8349 static int
8350 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8351                               struct i40e_ethertype_filter *filter)
8352 {
8353         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8354         filter->input.ether_type = input->ether_type;
8355         filter->flags = input->flags;
8356         filter->queue = input->queue;
8357
8358         return 0;
8359 }
8360
8361 /* Check if there exists the ehtertype filter */
8362 struct i40e_ethertype_filter *
8363 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8364                                 const struct i40e_ethertype_filter_input *input)
8365 {
8366         int ret;
8367
8368         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8369         if (ret < 0)
8370                 return NULL;
8371
8372         return ethertype_rule->hash_map[ret];
8373 }
8374
8375 /* Add ethertype filter in SW list */
8376 static int
8377 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8378                                 struct i40e_ethertype_filter *filter)
8379 {
8380         struct i40e_ethertype_rule *rule = &pf->ethertype;
8381         int ret;
8382
8383         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8384         if (ret < 0) {
8385                 PMD_DRV_LOG(ERR,
8386                             "Failed to insert ethertype filter"
8387                             " to hash table %d!",
8388                             ret);
8389                 return ret;
8390         }
8391         rule->hash_map[ret] = filter;
8392
8393         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8394
8395         return 0;
8396 }
8397
8398 /* Delete ethertype filter in SW list */
8399 int
8400 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8401                              struct i40e_ethertype_filter_input *input)
8402 {
8403         struct i40e_ethertype_rule *rule = &pf->ethertype;
8404         struct i40e_ethertype_filter *filter;
8405         int ret;
8406
8407         ret = rte_hash_del_key(rule->hash_table, input);
8408         if (ret < 0) {
8409                 PMD_DRV_LOG(ERR,
8410                             "Failed to delete ethertype filter"
8411                             " to hash table %d!",
8412                             ret);
8413                 return ret;
8414         }
8415         filter = rule->hash_map[ret];
8416         rule->hash_map[ret] = NULL;
8417
8418         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8419         rte_free(filter);
8420
8421         return 0;
8422 }
8423
8424 /*
8425  * Configure ethertype filter, which can director packet by filtering
8426  * with mac address and ether_type or only ether_type
8427  */
8428 static int
8429 i40e_ethertype_filter_set(struct i40e_pf *pf,
8430                         struct rte_eth_ethertype_filter *filter,
8431                         bool add)
8432 {
8433         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8434         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8435         struct i40e_ethertype_filter *ethertype_filter, *node;
8436         struct i40e_ethertype_filter check_filter;
8437         struct i40e_control_filter_stats stats;
8438         uint16_t flags = 0;
8439         int ret;
8440
8441         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8442                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8443                 return -EINVAL;
8444         }
8445         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8446                 filter->ether_type == ETHER_TYPE_IPv6) {
8447                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8448                         " control packet filter.", filter->ether_type);
8449                 return -EINVAL;
8450         }
8451         if (filter->ether_type == ETHER_TYPE_VLAN)
8452                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8453                         " not supported.");
8454
8455         /* Check if there is the filter in SW list */
8456         memset(&check_filter, 0, sizeof(check_filter));
8457         i40e_ethertype_filter_convert(filter, &check_filter);
8458         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8459                                                &check_filter.input);
8460         if (add && node) {
8461                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8462                 return -EINVAL;
8463         }
8464
8465         if (!add && !node) {
8466                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8467                 return -EINVAL;
8468         }
8469
8470         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8471                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8472         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8473                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8474         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8475
8476         memset(&stats, 0, sizeof(stats));
8477         ret = i40e_aq_add_rem_control_packet_filter(hw,
8478                         filter->mac_addr.addr_bytes,
8479                         filter->ether_type, flags,
8480                         pf->main_vsi->seid,
8481                         filter->queue, add, &stats, NULL);
8482
8483         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8484                          " mac_etype_used = %u, etype_used = %u,"
8485                          " mac_etype_free = %u, etype_free = %u\n",
8486                          ret, stats.mac_etype_used, stats.etype_used,
8487                          stats.mac_etype_free, stats.etype_free);
8488         if (ret < 0)
8489                 return -ENOSYS;
8490
8491         /* Add or delete a filter in SW list */
8492         if (add) {
8493                 ethertype_filter = rte_zmalloc("ethertype_filter",
8494                                        sizeof(*ethertype_filter), 0);
8495                 rte_memcpy(ethertype_filter, &check_filter,
8496                            sizeof(check_filter));
8497                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8498         } else {
8499                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8500         }
8501
8502         return ret;
8503 }
8504
8505 /*
8506  * Handle operations for ethertype filter.
8507  */
8508 static int
8509 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8510                                 enum rte_filter_op filter_op,
8511                                 void *arg)
8512 {
8513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8514         int ret = 0;
8515
8516         if (filter_op == RTE_ETH_FILTER_NOP)
8517                 return ret;
8518
8519         if (arg == NULL) {
8520                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8521                             filter_op);
8522                 return -EINVAL;
8523         }
8524
8525         switch (filter_op) {
8526         case RTE_ETH_FILTER_ADD:
8527                 ret = i40e_ethertype_filter_set(pf,
8528                         (struct rte_eth_ethertype_filter *)arg,
8529                         TRUE);
8530                 break;
8531         case RTE_ETH_FILTER_DELETE:
8532                 ret = i40e_ethertype_filter_set(pf,
8533                         (struct rte_eth_ethertype_filter *)arg,
8534                         FALSE);
8535                 break;
8536         default:
8537                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8538                 ret = -ENOSYS;
8539                 break;
8540         }
8541         return ret;
8542 }
8543
8544 static int
8545 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8546                      enum rte_filter_type filter_type,
8547                      enum rte_filter_op filter_op,
8548                      void *arg)
8549 {
8550         int ret = 0;
8551
8552         if (dev == NULL)
8553                 return -EINVAL;
8554
8555         switch (filter_type) {
8556         case RTE_ETH_FILTER_NONE:
8557                 /* For global configuration */
8558                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8559                 break;
8560         case RTE_ETH_FILTER_HASH:
8561                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8562                 break;
8563         case RTE_ETH_FILTER_MACVLAN:
8564                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8565                 break;
8566         case RTE_ETH_FILTER_ETHERTYPE:
8567                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8568                 break;
8569         case RTE_ETH_FILTER_TUNNEL:
8570                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8571                 break;
8572         case RTE_ETH_FILTER_FDIR:
8573                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8574                 break;
8575         default:
8576                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8577                                                         filter_type);
8578                 ret = -EINVAL;
8579                 break;
8580         }
8581
8582         return ret;
8583 }
8584
8585 /*
8586  * Check and enable Extended Tag.
8587  * Enabling Extended Tag is important for 40G performance.
8588  */
8589 static void
8590 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8591 {
8592         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8593         uint32_t buf = 0;
8594         int ret;
8595
8596         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8597                                       PCI_DEV_CAP_REG);
8598         if (ret < 0) {
8599                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8600                             PCI_DEV_CAP_REG);
8601                 return;
8602         }
8603         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8604                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8605                 return;
8606         }
8607
8608         buf = 0;
8609         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8610                                       PCI_DEV_CTRL_REG);
8611         if (ret < 0) {
8612                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8613                             PCI_DEV_CTRL_REG);
8614                 return;
8615         }
8616         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8617                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8618                 return;
8619         }
8620         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8621         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8622                                        PCI_DEV_CTRL_REG);
8623         if (ret < 0) {
8624                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8625                             PCI_DEV_CTRL_REG);
8626                 return;
8627         }
8628 }
8629
8630 /*
8631  * As some registers wouldn't be reset unless a global hardware reset,
8632  * hardware initialization is needed to put those registers into an
8633  * expected initial state.
8634  */
8635 static void
8636 i40e_hw_init(struct rte_eth_dev *dev)
8637 {
8638         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8639
8640         i40e_enable_extended_tag(dev);
8641
8642         /* clear the PF Queue Filter control register */
8643         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8644
8645         /* Disable symmetric hash per port */
8646         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8647 }
8648
8649 enum i40e_filter_pctype
8650 i40e_flowtype_to_pctype(uint16_t flow_type)
8651 {
8652         static const enum i40e_filter_pctype pctype_table[] = {
8653                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8654                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8655                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8656                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8657                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8658                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8659                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8660                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8661                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8662                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8663                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8664                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8665                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8666                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8667                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8668                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8669                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8670                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8671                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8672         };
8673
8674         return pctype_table[flow_type];
8675 }
8676
8677 uint16_t
8678 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8679 {
8680         static const uint16_t flowtype_table[] = {
8681                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8682                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8683                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8684                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8685                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8686                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8687                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8688                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8689                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8690                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8691                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8692                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8693                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8694                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8695                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8696                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8697                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8698                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8699                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8700                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8701                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8702                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8703                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8704                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8705                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8706                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8707                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8708                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8709                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8710                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8711                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8712         };
8713
8714         return flowtype_table[pctype];
8715 }
8716
8717 /*
8718  * On X710, performance number is far from the expectation on recent firmware
8719  * versions; on XL710, performance number is also far from the expectation on
8720  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8721  * mode is enabled and port MAC address is equal to the packet destination MAC
8722  * address. The fix for this issue may not be integrated in the following
8723  * firmware version. So the workaround in software driver is needed. It needs
8724  * to modify the initial values of 3 internal only registers for both X710 and
8725  * XL710. Note that the values for X710 or XL710 could be different, and the
8726  * workaround can be removed when it is fixed in firmware in the future.
8727  */
8728
8729 /* For both X710 and XL710 */
8730 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8731 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8732
8733 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8734 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8735
8736 /* For X710 */
8737 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8738 /* For XL710 */
8739 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8740 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8741
8742 static int
8743 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8744 {
8745         enum i40e_status_code status;
8746         struct i40e_aq_get_phy_abilities_resp phy_ab;
8747         int ret = -ENOTSUP;
8748
8749         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8750                                               NULL);
8751
8752         if (status)
8753                 return ret;
8754
8755         return 0;
8756 }
8757
8758
8759 static void
8760 i40e_configure_registers(struct i40e_hw *hw)
8761 {
8762         static struct {
8763                 uint32_t addr;
8764                 uint64_t val;
8765         } reg_table[] = {
8766                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8767                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8768                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8769         };
8770         uint64_t reg;
8771         uint32_t i;
8772         int ret;
8773
8774         for (i = 0; i < RTE_DIM(reg_table); i++) {
8775                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8776                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8777                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8778                                 reg_table[i].val =
8779                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8780                         else /* For X710 */
8781                                 reg_table[i].val =
8782                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8783                 }
8784
8785                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8786                                                         &reg, NULL);
8787                 if (ret < 0) {
8788                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8789                                                         reg_table[i].addr);
8790                         break;
8791                 }
8792                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8793                                                 reg_table[i].addr, reg);
8794                 if (reg == reg_table[i].val)
8795                         continue;
8796
8797                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8798                                                 reg_table[i].val, NULL);
8799                 if (ret < 0) {
8800                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8801                                 "address of 0x%"PRIx32, reg_table[i].val,
8802                                                         reg_table[i].addr);
8803                         break;
8804                 }
8805                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8806                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8807         }
8808 }
8809
8810 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8811 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8812 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8813 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8814 static int
8815 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8816 {
8817         uint32_t reg;
8818         int ret;
8819
8820         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8821                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8822                 return -EINVAL;
8823         }
8824
8825         /* Configure for double VLAN RX stripping */
8826         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8827         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8828                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8829                 ret = i40e_aq_debug_write_register(hw,
8830                                                    I40E_VSI_TSR(vsi->vsi_id),
8831                                                    reg, NULL);
8832                 if (ret < 0) {
8833                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8834                                     vsi->vsi_id);
8835                         return I40E_ERR_CONFIG;
8836                 }
8837         }
8838
8839         /* Configure for double VLAN TX insertion */
8840         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8841         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8842                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8843                 ret = i40e_aq_debug_write_register(hw,
8844                                                    I40E_VSI_L2TAGSTXVALID(
8845                                                    vsi->vsi_id), reg, NULL);
8846                 if (ret < 0) {
8847                         PMD_DRV_LOG(ERR, "Failed to update "
8848                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8849                         return I40E_ERR_CONFIG;
8850                 }
8851         }
8852
8853         return 0;
8854 }
8855
8856 /**
8857  * i40e_aq_add_mirror_rule
8858  * @hw: pointer to the hardware structure
8859  * @seid: VEB seid to add mirror rule to
8860  * @dst_id: destination vsi seid
8861  * @entries: Buffer which contains the entities to be mirrored
8862  * @count: number of entities contained in the buffer
8863  * @rule_id:the rule_id of the rule to be added
8864  *
8865  * Add a mirror rule for a given veb.
8866  *
8867  **/
8868 static enum i40e_status_code
8869 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8870                         uint16_t seid, uint16_t dst_id,
8871                         uint16_t rule_type, uint16_t *entries,
8872                         uint16_t count, uint16_t *rule_id)
8873 {
8874         struct i40e_aq_desc desc;
8875         struct i40e_aqc_add_delete_mirror_rule cmd;
8876         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8877                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8878                 &desc.params.raw;
8879         uint16_t buff_len;
8880         enum i40e_status_code status;
8881
8882         i40e_fill_default_direct_cmd_desc(&desc,
8883                                           i40e_aqc_opc_add_mirror_rule);
8884         memset(&cmd, 0, sizeof(cmd));
8885
8886         buff_len = sizeof(uint16_t) * count;
8887         desc.datalen = rte_cpu_to_le_16(buff_len);
8888         if (buff_len > 0)
8889                 desc.flags |= rte_cpu_to_le_16(
8890                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8891         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8892                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8893         cmd.num_entries = rte_cpu_to_le_16(count);
8894         cmd.seid = rte_cpu_to_le_16(seid);
8895         cmd.destination = rte_cpu_to_le_16(dst_id);
8896
8897         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8898         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8899         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8900                          "rule_id = %u"
8901                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8902                          hw->aq.asq_last_status, resp->rule_id,
8903                          resp->mirror_rules_used, resp->mirror_rules_free);
8904         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8905
8906         return status;
8907 }
8908
8909 /**
8910  * i40e_aq_del_mirror_rule
8911  * @hw: pointer to the hardware structure
8912  * @seid: VEB seid to add mirror rule to
8913  * @entries: Buffer which contains the entities to be mirrored
8914  * @count: number of entities contained in the buffer
8915  * @rule_id:the rule_id of the rule to be delete
8916  *
8917  * Delete a mirror rule for a given veb.
8918  *
8919  **/
8920 static enum i40e_status_code
8921 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8922                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8923                 uint16_t count, uint16_t rule_id)
8924 {
8925         struct i40e_aq_desc desc;
8926         struct i40e_aqc_add_delete_mirror_rule cmd;
8927         uint16_t buff_len = 0;
8928         enum i40e_status_code status;
8929         void *buff = NULL;
8930
8931         i40e_fill_default_direct_cmd_desc(&desc,
8932                                           i40e_aqc_opc_delete_mirror_rule);
8933         memset(&cmd, 0, sizeof(cmd));
8934         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8935                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8936                                                           I40E_AQ_FLAG_RD));
8937                 cmd.num_entries = count;
8938                 buff_len = sizeof(uint16_t) * count;
8939                 desc.datalen = rte_cpu_to_le_16(buff_len);
8940                 buff = (void *)entries;
8941         } else
8942                 /* rule id is filled in destination field for deleting mirror rule */
8943                 cmd.destination = rte_cpu_to_le_16(rule_id);
8944
8945         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8946                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8947         cmd.seid = rte_cpu_to_le_16(seid);
8948
8949         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8950         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8951
8952         return status;
8953 }
8954
8955 /**
8956  * i40e_mirror_rule_set
8957  * @dev: pointer to the hardware structure
8958  * @mirror_conf: mirror rule info
8959  * @sw_id: mirror rule's sw_id
8960  * @on: enable/disable
8961  *
8962  * set a mirror rule.
8963  *
8964  **/
8965 static int
8966 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8967                         struct rte_eth_mirror_conf *mirror_conf,
8968                         uint8_t sw_id, uint8_t on)
8969 {
8970         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8972         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8973         struct i40e_mirror_rule *parent = NULL;
8974         uint16_t seid, dst_seid, rule_id;
8975         uint16_t i, j = 0;
8976         int ret;
8977
8978         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8979
8980         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8981                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8982                         " without veb or vfs.");
8983                 return -ENOSYS;
8984         }
8985         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8986                 PMD_DRV_LOG(ERR, "mirror table is full.");
8987                 return -ENOSPC;
8988         }
8989         if (mirror_conf->dst_pool > pf->vf_num) {
8990                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8991                                  mirror_conf->dst_pool);
8992                 return -EINVAL;
8993         }
8994
8995         seid = pf->main_vsi->veb->seid;
8996
8997         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8998                 if (sw_id <= it->index) {
8999                         mirr_rule = it;
9000                         break;
9001                 }
9002                 parent = it;
9003         }
9004         if (mirr_rule && sw_id == mirr_rule->index) {
9005                 if (on) {
9006                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9007                         return -EEXIST;
9008                 } else {
9009                         ret = i40e_aq_del_mirror_rule(hw, seid,
9010                                         mirr_rule->rule_type,
9011                                         mirr_rule->entries,
9012                                         mirr_rule->num_entries, mirr_rule->id);
9013                         if (ret < 0) {
9014                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9015                                                    " ret = %d, aq_err = %d.",
9016                                                    ret, hw->aq.asq_last_status);
9017                                 return -ENOSYS;
9018                         }
9019                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9020                         rte_free(mirr_rule);
9021                         pf->nb_mirror_rule--;
9022                         return 0;
9023                 }
9024         } else if (!on) {
9025                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9026                 return -ENOENT;
9027         }
9028
9029         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9030                                 sizeof(struct i40e_mirror_rule) , 0);
9031         if (!mirr_rule) {
9032                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9033                 return I40E_ERR_NO_MEMORY;
9034         }
9035         switch (mirror_conf->rule_type) {
9036         case ETH_MIRROR_VLAN:
9037                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9038                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9039                                 mirr_rule->entries[j] =
9040                                         mirror_conf->vlan.vlan_id[i];
9041                                 j++;
9042                         }
9043                 }
9044                 if (j == 0) {
9045                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9046                         rte_free(mirr_rule);
9047                         return -EINVAL;
9048                 }
9049                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9050                 break;
9051         case ETH_MIRROR_VIRTUAL_POOL_UP:
9052         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9053                 /* check if the specified pool bit is out of range */
9054                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9055                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9056                         rte_free(mirr_rule);
9057                         return -EINVAL;
9058                 }
9059                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9060                         if (mirror_conf->pool_mask & (1ULL << i)) {
9061                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9062                                 j++;
9063                         }
9064                 }
9065                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9066                         /* add pf vsi to entries */
9067                         mirr_rule->entries[j] = pf->main_vsi_seid;
9068                         j++;
9069                 }
9070                 if (j == 0) {
9071                         PMD_DRV_LOG(ERR, "pool is not specified.");
9072                         rte_free(mirr_rule);
9073                         return -EINVAL;
9074                 }
9075                 /* egress and ingress in aq commands means from switch but not port */
9076                 mirr_rule->rule_type =
9077                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9078                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9079                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9080                 break;
9081         case ETH_MIRROR_UPLINK_PORT:
9082                 /* egress and ingress in aq commands means from switch but not port*/
9083                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9084                 break;
9085         case ETH_MIRROR_DOWNLINK_PORT:
9086                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9087                 break;
9088         default:
9089                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9090                         mirror_conf->rule_type);
9091                 rte_free(mirr_rule);
9092                 return -EINVAL;
9093         }
9094
9095         /* If the dst_pool is equal to vf_num, consider it as PF */
9096         if (mirror_conf->dst_pool == pf->vf_num)
9097                 dst_seid = pf->main_vsi_seid;
9098         else
9099                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9100
9101         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9102                                       mirr_rule->rule_type, mirr_rule->entries,
9103                                       j, &rule_id);
9104         if (ret < 0) {
9105                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9106                                    " ret = %d, aq_err = %d.",
9107                                    ret, hw->aq.asq_last_status);
9108                 rte_free(mirr_rule);
9109                 return -ENOSYS;
9110         }
9111
9112         mirr_rule->index = sw_id;
9113         mirr_rule->num_entries = j;
9114         mirr_rule->id = rule_id;
9115         mirr_rule->dst_vsi_seid = dst_seid;
9116
9117         if (parent)
9118                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9119         else
9120                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9121
9122         pf->nb_mirror_rule++;
9123         return 0;
9124 }
9125
9126 /**
9127  * i40e_mirror_rule_reset
9128  * @dev: pointer to the device
9129  * @sw_id: mirror rule's sw_id
9130  *
9131  * reset a mirror rule.
9132  *
9133  **/
9134 static int
9135 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9136 {
9137         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9138         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9139         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9140         uint16_t seid;
9141         int ret;
9142
9143         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9144
9145         seid = pf->main_vsi->veb->seid;
9146
9147         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9148                 if (sw_id == it->index) {
9149                         mirr_rule = it;
9150                         break;
9151                 }
9152         }
9153         if (mirr_rule) {
9154                 ret = i40e_aq_del_mirror_rule(hw, seid,
9155                                 mirr_rule->rule_type,
9156                                 mirr_rule->entries,
9157                                 mirr_rule->num_entries, mirr_rule->id);
9158                 if (ret < 0) {
9159                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9160                                            " status = %d, aq_err = %d.",
9161                                            ret, hw->aq.asq_last_status);
9162                         return -ENOSYS;
9163                 }
9164                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9165                 rte_free(mirr_rule);
9166                 pf->nb_mirror_rule--;
9167         } else {
9168                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9169                 return -ENOENT;
9170         }
9171         return 0;
9172 }
9173
9174 static uint64_t
9175 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9176 {
9177         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9178         uint64_t systim_cycles;
9179
9180         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9181         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9182                         << 32;
9183
9184         return systim_cycles;
9185 }
9186
9187 static uint64_t
9188 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9189 {
9190         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9191         uint64_t rx_tstamp;
9192
9193         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9194         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9195                         << 32;
9196
9197         return rx_tstamp;
9198 }
9199
9200 static uint64_t
9201 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9202 {
9203         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9204         uint64_t tx_tstamp;
9205
9206         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9207         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9208                         << 32;
9209
9210         return tx_tstamp;
9211 }
9212
9213 static void
9214 i40e_start_timecounters(struct rte_eth_dev *dev)
9215 {
9216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9217         struct i40e_adapter *adapter =
9218                         (struct i40e_adapter *)dev->data->dev_private;
9219         struct rte_eth_link link;
9220         uint32_t tsync_inc_l;
9221         uint32_t tsync_inc_h;
9222
9223         /* Get current link speed. */
9224         memset(&link, 0, sizeof(link));
9225         i40e_dev_link_update(dev, 1);
9226         rte_i40e_dev_atomic_read_link_status(dev, &link);
9227
9228         switch (link.link_speed) {
9229         case ETH_SPEED_NUM_40G:
9230                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9231                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9232                 break;
9233         case ETH_SPEED_NUM_10G:
9234                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9235                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9236                 break;
9237         case ETH_SPEED_NUM_1G:
9238                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9239                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9240                 break;
9241         default:
9242                 tsync_inc_l = 0x0;
9243                 tsync_inc_h = 0x0;
9244         }
9245
9246         /* Set the timesync increment value. */
9247         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9248         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9249
9250         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9251         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9252         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9253
9254         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9255         adapter->systime_tc.cc_shift = 0;
9256         adapter->systime_tc.nsec_mask = 0;
9257
9258         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9259         adapter->rx_tstamp_tc.cc_shift = 0;
9260         adapter->rx_tstamp_tc.nsec_mask = 0;
9261
9262         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9263         adapter->tx_tstamp_tc.cc_shift = 0;
9264         adapter->tx_tstamp_tc.nsec_mask = 0;
9265 }
9266
9267 static int
9268 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9269 {
9270         struct i40e_adapter *adapter =
9271                         (struct i40e_adapter *)dev->data->dev_private;
9272
9273         adapter->systime_tc.nsec += delta;
9274         adapter->rx_tstamp_tc.nsec += delta;
9275         adapter->tx_tstamp_tc.nsec += delta;
9276
9277         return 0;
9278 }
9279
9280 static int
9281 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9282 {
9283         uint64_t ns;
9284         struct i40e_adapter *adapter =
9285                         (struct i40e_adapter *)dev->data->dev_private;
9286
9287         ns = rte_timespec_to_ns(ts);
9288
9289         /* Set the timecounters to a new value. */
9290         adapter->systime_tc.nsec = ns;
9291         adapter->rx_tstamp_tc.nsec = ns;
9292         adapter->tx_tstamp_tc.nsec = ns;
9293
9294         return 0;
9295 }
9296
9297 static int
9298 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9299 {
9300         uint64_t ns, systime_cycles;
9301         struct i40e_adapter *adapter =
9302                         (struct i40e_adapter *)dev->data->dev_private;
9303
9304         systime_cycles = i40e_read_systime_cyclecounter(dev);
9305         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9306         *ts = rte_ns_to_timespec(ns);
9307
9308         return 0;
9309 }
9310
9311 static int
9312 i40e_timesync_enable(struct rte_eth_dev *dev)
9313 {
9314         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9315         uint32_t tsync_ctl_l;
9316         uint32_t tsync_ctl_h;
9317
9318         /* Stop the timesync system time. */
9319         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9320         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9321         /* Reset the timesync system time value. */
9322         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9323         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9324
9325         i40e_start_timecounters(dev);
9326
9327         /* Clear timesync registers. */
9328         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9329         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9330         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9331         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9332         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9333         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9334
9335         /* Enable timestamping of PTP packets. */
9336         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9337         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9338
9339         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9340         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9341         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9342
9343         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9344         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9345
9346         return 0;
9347 }
9348
9349 static int
9350 i40e_timesync_disable(struct rte_eth_dev *dev)
9351 {
9352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9353         uint32_t tsync_ctl_l;
9354         uint32_t tsync_ctl_h;
9355
9356         /* Disable timestamping of transmitted PTP packets. */
9357         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9358         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9359
9360         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9361         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9362
9363         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9364         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9365
9366         /* Reset the timesync increment value. */
9367         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9368         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9369
9370         return 0;
9371 }
9372
9373 static int
9374 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9375                                 struct timespec *timestamp, uint32_t flags)
9376 {
9377         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9378         struct i40e_adapter *adapter =
9379                 (struct i40e_adapter *)dev->data->dev_private;
9380
9381         uint32_t sync_status;
9382         uint32_t index = flags & 0x03;
9383         uint64_t rx_tstamp_cycles;
9384         uint64_t ns;
9385
9386         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9387         if ((sync_status & (1 << index)) == 0)
9388                 return -EINVAL;
9389
9390         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9391         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9392         *timestamp = rte_ns_to_timespec(ns);
9393
9394         return 0;
9395 }
9396
9397 static int
9398 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9399                                 struct timespec *timestamp)
9400 {
9401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9402         struct i40e_adapter *adapter =
9403                 (struct i40e_adapter *)dev->data->dev_private;
9404
9405         uint32_t sync_status;
9406         uint64_t tx_tstamp_cycles;
9407         uint64_t ns;
9408
9409         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9410         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9411                 return -EINVAL;
9412
9413         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9414         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9415         *timestamp = rte_ns_to_timespec(ns);
9416
9417         return 0;
9418 }
9419
9420 /*
9421  * i40e_parse_dcb_configure - parse dcb configure from user
9422  * @dev: the device being configured
9423  * @dcb_cfg: pointer of the result of parse
9424  * @*tc_map: bit map of enabled traffic classes
9425  *
9426  * Returns 0 on success, negative value on failure
9427  */
9428 static int
9429 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9430                          struct i40e_dcbx_config *dcb_cfg,
9431                          uint8_t *tc_map)
9432 {
9433         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9434         uint8_t i, tc_bw, bw_lf;
9435
9436         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9437
9438         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9439         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9440                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9441                 return -EINVAL;
9442         }
9443
9444         /* assume each tc has the same bw */
9445         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9446         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9447                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9448         /* to ensure the sum of tcbw is equal to 100 */
9449         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9450         for (i = 0; i < bw_lf; i++)
9451                 dcb_cfg->etscfg.tcbwtable[i]++;
9452
9453         /* assume each tc has the same Transmission Selection Algorithm */
9454         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9455                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9456
9457         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9458                 dcb_cfg->etscfg.prioritytable[i] =
9459                                 dcb_rx_conf->dcb_tc[i];
9460
9461         /* FW needs one App to configure HW */
9462         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9463         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9464         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9465         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9466
9467         if (dcb_rx_conf->nb_tcs == 0)
9468                 *tc_map = 1; /* tc0 only */
9469         else
9470                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9471
9472         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9473                 dcb_cfg->pfc.willing = 0;
9474                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9475                 dcb_cfg->pfc.pfcenable = *tc_map;
9476         }
9477         return 0;
9478 }
9479
9480
9481 static enum i40e_status_code
9482 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9483                               struct i40e_aqc_vsi_properties_data *info,
9484                               uint8_t enabled_tcmap)
9485 {
9486         enum i40e_status_code ret;
9487         int i, total_tc = 0;
9488         uint16_t qpnum_per_tc, bsf, qp_idx;
9489         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9490         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9491         uint16_t used_queues;
9492
9493         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9494         if (ret != I40E_SUCCESS)
9495                 return ret;
9496
9497         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9498                 if (enabled_tcmap & (1 << i))
9499                         total_tc++;
9500         }
9501         if (total_tc == 0)
9502                 total_tc = 1;
9503         vsi->enabled_tc = enabled_tcmap;
9504
9505         /* different VSI has different queues assigned */
9506         if (vsi->type == I40E_VSI_MAIN)
9507                 used_queues = dev_data->nb_rx_queues -
9508                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9509         else if (vsi->type == I40E_VSI_VMDQ2)
9510                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9511         else {
9512                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9513                 return I40E_ERR_NO_AVAILABLE_VSI;
9514         }
9515
9516         qpnum_per_tc = used_queues / total_tc;
9517         /* Number of queues per enabled TC */
9518         if (qpnum_per_tc == 0) {
9519                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9520                 return I40E_ERR_INVALID_QP_ID;
9521         }
9522         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9523                                 I40E_MAX_Q_PER_TC);
9524         bsf = rte_bsf32(qpnum_per_tc);
9525
9526         /**
9527          * Configure TC and queue mapping parameters, for enabled TC,
9528          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9529          * default queue will serve it.
9530          */
9531         qp_idx = 0;
9532         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9533                 if (vsi->enabled_tc & (1 << i)) {
9534                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9535                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9536                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9537                         qp_idx += qpnum_per_tc;
9538                 } else
9539                         info->tc_mapping[i] = 0;
9540         }
9541
9542         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9543         if (vsi->type == I40E_VSI_SRIOV) {
9544                 info->mapping_flags |=
9545                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9546                 for (i = 0; i < vsi->nb_qps; i++)
9547                         info->queue_mapping[i] =
9548                                 rte_cpu_to_le_16(vsi->base_queue + i);
9549         } else {
9550                 info->mapping_flags |=
9551                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9552                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9553         }
9554         info->valid_sections |=
9555                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9556
9557         return I40E_SUCCESS;
9558 }
9559
9560 /*
9561  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9562  * @veb: VEB to be configured
9563  * @tc_map: enabled TC bitmap
9564  *
9565  * Returns 0 on success, negative value on failure
9566  */
9567 static enum i40e_status_code
9568 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9569 {
9570         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9571         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9572         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9573         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9574         enum i40e_status_code ret = I40E_SUCCESS;
9575         int i;
9576         uint32_t bw_max;
9577
9578         /* Check if enabled_tc is same as existing or new TCs */
9579         if (veb->enabled_tc == tc_map)
9580                 return ret;
9581
9582         /* configure tc bandwidth */
9583         memset(&veb_bw, 0, sizeof(veb_bw));
9584         veb_bw.tc_valid_bits = tc_map;
9585         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9586         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9587                 if (tc_map & BIT_ULL(i))
9588                         veb_bw.tc_bw_share_credits[i] = 1;
9589         }
9590         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9591                                                    &veb_bw, NULL);
9592         if (ret) {
9593                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9594                                   " per TC failed = %d",
9595                                   hw->aq.asq_last_status);
9596                 return ret;
9597         }
9598
9599         memset(&ets_query, 0, sizeof(ets_query));
9600         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9601                                                    &ets_query, NULL);
9602         if (ret != I40E_SUCCESS) {
9603                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9604                                  " configuration %u", hw->aq.asq_last_status);
9605                 return ret;
9606         }
9607         memset(&bw_query, 0, sizeof(bw_query));
9608         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9609                                                   &bw_query, NULL);
9610         if (ret != I40E_SUCCESS) {
9611                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9612                                  " configuration %u", hw->aq.asq_last_status);
9613                 return ret;
9614         }
9615
9616         /* store and print out BW info */
9617         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9618         veb->bw_info.bw_max = ets_query.tc_bw_max;
9619         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9620         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9621         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9622                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9623                      I40E_16_BIT_WIDTH);
9624         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9625                 veb->bw_info.bw_ets_share_credits[i] =
9626                                 bw_query.tc_bw_share_credits[i];
9627                 veb->bw_info.bw_ets_credits[i] =
9628                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9629                 /* 4 bits per TC, 4th bit is reserved */
9630                 veb->bw_info.bw_ets_max[i] =
9631                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9632                                   RTE_LEN2MASK(3, uint8_t));
9633                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9634                             veb->bw_info.bw_ets_share_credits[i]);
9635                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9636                             veb->bw_info.bw_ets_credits[i]);
9637                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9638                             veb->bw_info.bw_ets_max[i]);
9639         }
9640
9641         veb->enabled_tc = tc_map;
9642
9643         return ret;
9644 }
9645
9646
9647 /*
9648  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9649  * @vsi: VSI to be configured
9650  * @tc_map: enabled TC bitmap
9651  *
9652  * Returns 0 on success, negative value on failure
9653  */
9654 static enum i40e_status_code
9655 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9656 {
9657         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9658         struct i40e_vsi_context ctxt;
9659         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9660         enum i40e_status_code ret = I40E_SUCCESS;
9661         int i;
9662
9663         /* Check if enabled_tc is same as existing or new TCs */
9664         if (vsi->enabled_tc == tc_map)
9665                 return ret;
9666
9667         /* configure tc bandwidth */
9668         memset(&bw_data, 0, sizeof(bw_data));
9669         bw_data.tc_valid_bits = tc_map;
9670         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9671         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9672                 if (tc_map & BIT_ULL(i))
9673                         bw_data.tc_bw_credits[i] = 1;
9674         }
9675         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9676         if (ret) {
9677                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9678                         " per TC failed = %d",
9679                         hw->aq.asq_last_status);
9680                 goto out;
9681         }
9682         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9683                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9684
9685         /* Update Queue Pairs Mapping for currently enabled UPs */
9686         ctxt.seid = vsi->seid;
9687         ctxt.pf_num = hw->pf_id;
9688         ctxt.vf_num = 0;
9689         ctxt.uplink_seid = vsi->uplink_seid;
9690         ctxt.info = vsi->info;
9691         i40e_get_cap(hw);
9692         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9693         if (ret)
9694                 goto out;
9695
9696         /* Update the VSI after updating the VSI queue-mapping information */
9697         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9698         if (ret) {
9699                 PMD_INIT_LOG(ERR, "Failed to configure "
9700                             "TC queue mapping = %d",
9701                             hw->aq.asq_last_status);
9702                 goto out;
9703         }
9704         /* update the local VSI info with updated queue map */
9705         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9706                                         sizeof(vsi->info.tc_mapping));
9707         (void)rte_memcpy(&vsi->info.queue_mapping,
9708                         &ctxt.info.queue_mapping,
9709                 sizeof(vsi->info.queue_mapping));
9710         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9711         vsi->info.valid_sections = 0;
9712
9713         /* query and update current VSI BW information */
9714         ret = i40e_vsi_get_bw_config(vsi);
9715         if (ret) {
9716                 PMD_INIT_LOG(ERR,
9717                          "Failed updating vsi bw info, err %s aq_err %s",
9718                          i40e_stat_str(hw, ret),
9719                          i40e_aq_str(hw, hw->aq.asq_last_status));
9720                 goto out;
9721         }
9722
9723         vsi->enabled_tc = tc_map;
9724
9725 out:
9726         return ret;
9727 }
9728
9729 /*
9730  * i40e_dcb_hw_configure - program the dcb setting to hw
9731  * @pf: pf the configuration is taken on
9732  * @new_cfg: new configuration
9733  * @tc_map: enabled TC bitmap
9734  *
9735  * Returns 0 on success, negative value on failure
9736  */
9737 static enum i40e_status_code
9738 i40e_dcb_hw_configure(struct i40e_pf *pf,
9739                       struct i40e_dcbx_config *new_cfg,
9740                       uint8_t tc_map)
9741 {
9742         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9743         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9744         struct i40e_vsi *main_vsi = pf->main_vsi;
9745         struct i40e_vsi_list *vsi_list;
9746         enum i40e_status_code ret;
9747         int i;
9748         uint32_t val;
9749
9750         /* Use the FW API if FW > v4.4*/
9751         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9752               (hw->aq.fw_maj_ver >= 5))) {
9753                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9754                                   " to configure DCB");
9755                 return I40E_ERR_FIRMWARE_API_VERSION;
9756         }
9757
9758         /* Check if need reconfiguration */
9759         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9760                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9761                 return I40E_SUCCESS;
9762         }
9763
9764         /* Copy the new config to the current config */
9765         *old_cfg = *new_cfg;
9766         old_cfg->etsrec = old_cfg->etscfg;
9767         ret = i40e_set_dcb_config(hw);
9768         if (ret) {
9769                 PMD_INIT_LOG(ERR,
9770                          "Set DCB Config failed, err %s aq_err %s\n",
9771                          i40e_stat_str(hw, ret),
9772                          i40e_aq_str(hw, hw->aq.asq_last_status));
9773                 return ret;
9774         }
9775         /* set receive Arbiter to RR mode and ETS scheme by default */
9776         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9777                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9778                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9779                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9780                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9781                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9782                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9783                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9784                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9785                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9786                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9787                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9788                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9789         }
9790         /* get local mib to check whether it is configured correctly */
9791         /* IEEE mode */
9792         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9793         /* Get Local DCB Config */
9794         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9795                                      &hw->local_dcbx_config);
9796
9797         /* if Veb is created, need to update TC of it at first */
9798         if (main_vsi->veb) {
9799                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9800                 if (ret)
9801                         PMD_INIT_LOG(WARNING,
9802                                  "Failed configuring TC for VEB seid=%d\n",
9803                                  main_vsi->veb->seid);
9804         }
9805         /* Update each VSI */
9806         i40e_vsi_config_tc(main_vsi, tc_map);
9807         if (main_vsi->veb) {
9808                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9809                         /* Beside main VSI and VMDQ VSIs, only enable default
9810                          * TC for other VSIs
9811                          */
9812                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9813                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9814                                                          tc_map);
9815                         else
9816                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9817                                                          I40E_DEFAULT_TCMAP);
9818                         if (ret)
9819                                 PMD_INIT_LOG(WARNING,
9820                                          "Failed configuring TC for VSI seid=%d\n",
9821                                          vsi_list->vsi->seid);
9822                         /* continue */
9823                 }
9824         }
9825         return I40E_SUCCESS;
9826 }
9827
9828 /*
9829  * i40e_dcb_init_configure - initial dcb config
9830  * @dev: device being configured
9831  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9832  *
9833  * Returns 0 on success, negative value on failure
9834  */
9835 static int
9836 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9837 {
9838         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9840         int ret = 0;
9841
9842         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9843                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9844                 return -ENOTSUP;
9845         }
9846
9847         /* DCB initialization:
9848          * Update DCB configuration from the Firmware and configure
9849          * LLDP MIB change event.
9850          */
9851         if (sw_dcb == TRUE) {
9852                 ret = i40e_init_dcb(hw);
9853                 /* If lldp agent is stopped, the return value from
9854                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9855                  * adminq status. Otherwise, it should return success.
9856                  */
9857                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9858                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9859                         memset(&hw->local_dcbx_config, 0,
9860                                 sizeof(struct i40e_dcbx_config));
9861                         /* set dcb default configuration */
9862                         hw->local_dcbx_config.etscfg.willing = 0;
9863                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9864                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9865                         hw->local_dcbx_config.etscfg.tsatable[0] =
9866                                                 I40E_IEEE_TSA_ETS;
9867                         hw->local_dcbx_config.etsrec =
9868                                 hw->local_dcbx_config.etscfg;
9869                         hw->local_dcbx_config.pfc.willing = 0;
9870                         hw->local_dcbx_config.pfc.pfccap =
9871                                                 I40E_MAX_TRAFFIC_CLASS;
9872                         /* FW needs one App to configure HW */
9873                         hw->local_dcbx_config.numapps = 1;
9874                         hw->local_dcbx_config.app[0].selector =
9875                                                 I40E_APP_SEL_ETHTYPE;
9876                         hw->local_dcbx_config.app[0].priority = 3;
9877                         hw->local_dcbx_config.app[0].protocolid =
9878                                                 I40E_APP_PROTOID_FCOE;
9879                         ret = i40e_set_dcb_config(hw);
9880                         if (ret) {
9881                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9882                                         " err = %d, aq_err = %d.", ret,
9883                                           hw->aq.asq_last_status);
9884                                 return -ENOSYS;
9885                         }
9886                 } else {
9887                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9888                                           " err = %d, aq_err = %d.", ret,
9889                                           hw->aq.asq_last_status);
9890                         return -ENOTSUP;
9891                 }
9892         } else {
9893                 ret = i40e_aq_start_lldp(hw, NULL);
9894                 if (ret != I40E_SUCCESS)
9895                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9896
9897                 ret = i40e_init_dcb(hw);
9898                 if (!ret) {
9899                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9900                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9901                                                   " DCBX offload.");
9902                                 return -ENOTSUP;
9903                         }
9904                 } else {
9905                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9906                                           " aq_err = %d.", ret,
9907                                           hw->aq.asq_last_status);
9908                         return -ENOTSUP;
9909                 }
9910         }
9911         return 0;
9912 }
9913
9914 /*
9915  * i40e_dcb_setup - setup dcb related config
9916  * @dev: device being configured
9917  *
9918  * Returns 0 on success, negative value on failure
9919  */
9920 static int
9921 i40e_dcb_setup(struct rte_eth_dev *dev)
9922 {
9923         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9924         struct i40e_dcbx_config dcb_cfg;
9925         uint8_t tc_map = 0;
9926         int ret = 0;
9927
9928         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9929                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9930                 return -ENOTSUP;
9931         }
9932
9933         if (pf->vf_num != 0)
9934                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9935
9936         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9937         if (ret) {
9938                 PMD_INIT_LOG(ERR, "invalid dcb config");
9939                 return -EINVAL;
9940         }
9941         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9942         if (ret) {
9943                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9944                 return -ENOSYS;
9945         }
9946
9947         return 0;
9948 }
9949
9950 static int
9951 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9952                       struct rte_eth_dcb_info *dcb_info)
9953 {
9954         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9955         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9956         struct i40e_vsi *vsi = pf->main_vsi;
9957         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9958         uint16_t bsf, tc_mapping;
9959         int i, j = 0;
9960
9961         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9962                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9963         else
9964                 dcb_info->nb_tcs = 1;
9965         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9966                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9967         for (i = 0; i < dcb_info->nb_tcs; i++)
9968                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9969
9970         /* get queue mapping if vmdq is disabled */
9971         if (!pf->nb_cfg_vmdq_vsi) {
9972                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9973                         if (!(vsi->enabled_tc & (1 << i)))
9974                                 continue;
9975                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9976                         dcb_info->tc_queue.tc_rxq[j][i].base =
9977                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9978                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9979                         dcb_info->tc_queue.tc_txq[j][i].base =
9980                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9981                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9982                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9983                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9984                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9985                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9986                 }
9987                 return 0;
9988         }
9989
9990         /* get queue mapping if vmdq is enabled */
9991         do {
9992                 vsi = pf->vmdq[j].vsi;
9993                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9994                         if (!(vsi->enabled_tc & (1 << i)))
9995                                 continue;
9996                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9997                         dcb_info->tc_queue.tc_rxq[j][i].base =
9998                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9999                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10000                         dcb_info->tc_queue.tc_txq[j][i].base =
10001                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10002                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10003                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10004                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10005                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10006                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10007                 }
10008                 j++;
10009         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10010         return 0;
10011 }
10012
10013 static int
10014 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10015 {
10016         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10017         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10018         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10019         uint16_t interval =
10020                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10021         uint16_t msix_intr;
10022
10023         msix_intr = intr_handle->intr_vec[queue_id];
10024         if (msix_intr == I40E_MISC_VEC_ID)
10025                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10026                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10027                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10028                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10029                                (interval <<
10030                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10031         else
10032                 I40E_WRITE_REG(hw,
10033                                I40E_PFINT_DYN_CTLN(msix_intr -
10034                                                    I40E_RX_VEC_START),
10035                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10036                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10037                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10038                                (interval <<
10039                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10040
10041         I40E_WRITE_FLUSH(hw);
10042         rte_intr_enable(&pci_dev->intr_handle);
10043
10044         return 0;
10045 }
10046
10047 static int
10048 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10049 {
10050         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10051         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10052         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10053         uint16_t msix_intr;
10054
10055         msix_intr = intr_handle->intr_vec[queue_id];
10056         if (msix_intr == I40E_MISC_VEC_ID)
10057                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10058         else
10059                 I40E_WRITE_REG(hw,
10060                                I40E_PFINT_DYN_CTLN(msix_intr -
10061                                                    I40E_RX_VEC_START),
10062                                0);
10063         I40E_WRITE_FLUSH(hw);
10064
10065         return 0;
10066 }
10067
10068 static int i40e_get_regs(struct rte_eth_dev *dev,
10069                          struct rte_dev_reg_info *regs)
10070 {
10071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10072         uint32_t *ptr_data = regs->data;
10073         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10074         const struct i40e_reg_info *reg_info;
10075
10076         if (ptr_data == NULL) {
10077                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10078                 regs->width = sizeof(uint32_t);
10079                 return 0;
10080         }
10081
10082         /* The first few registers have to be read using AQ operations */
10083         reg_idx = 0;
10084         while (i40e_regs_adminq[reg_idx].name) {
10085                 reg_info = &i40e_regs_adminq[reg_idx++];
10086                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10087                         for (arr_idx2 = 0;
10088                                         arr_idx2 <= reg_info->count2;
10089                                         arr_idx2++) {
10090                                 reg_offset = arr_idx * reg_info->stride1 +
10091                                         arr_idx2 * reg_info->stride2;
10092                                 reg_offset += reg_info->base_addr;
10093                                 ptr_data[reg_offset >> 2] =
10094                                         i40e_read_rx_ctl(hw, reg_offset);
10095                         }
10096         }
10097
10098         /* The remaining registers can be read using primitives */
10099         reg_idx = 0;
10100         while (i40e_regs_others[reg_idx].name) {
10101                 reg_info = &i40e_regs_others[reg_idx++];
10102                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10103                         for (arr_idx2 = 0;
10104                                         arr_idx2 <= reg_info->count2;
10105                                         arr_idx2++) {
10106                                 reg_offset = arr_idx * reg_info->stride1 +
10107                                         arr_idx2 * reg_info->stride2;
10108                                 reg_offset += reg_info->base_addr;
10109                                 ptr_data[reg_offset >> 2] =
10110                                         I40E_READ_REG(hw, reg_offset);
10111                         }
10112         }
10113
10114         return 0;
10115 }
10116
10117 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10118 {
10119         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10120
10121         /* Convert word count to byte count */
10122         return hw->nvm.sr_size << 1;
10123 }
10124
10125 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10126                            struct rte_dev_eeprom_info *eeprom)
10127 {
10128         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10129         uint16_t *data = eeprom->data;
10130         uint16_t offset, length, cnt_words;
10131         int ret_code;
10132
10133         offset = eeprom->offset >> 1;
10134         length = eeprom->length >> 1;
10135         cnt_words = length;
10136
10137         if (offset > hw->nvm.sr_size ||
10138                 offset + length > hw->nvm.sr_size) {
10139                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10140                 return -EINVAL;
10141         }
10142
10143         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10144
10145         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10146         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10147                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10148                 return -EIO;
10149         }
10150
10151         return 0;
10152 }
10153
10154 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10155                                       struct ether_addr *mac_addr)
10156 {
10157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10158
10159         if (!is_valid_assigned_ether_addr(mac_addr)) {
10160                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10161                 return;
10162         }
10163
10164         /* Flags: 0x3 updates port address */
10165         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10166 }
10167
10168 static int
10169 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10170 {
10171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10172         struct rte_eth_dev_data *dev_data = pf->dev_data;
10173         uint32_t frame_size = mtu + ETHER_HDR_LEN
10174                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10175         int ret = 0;
10176
10177         /* check if mtu is within the allowed range */
10178         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10179                 return -EINVAL;
10180
10181         /* mtu setting is forbidden if port is start */
10182         if (dev_data->dev_started) {
10183                 PMD_DRV_LOG(ERR,
10184                             "port %d must be stopped before configuration\n",
10185                             dev_data->port_id);
10186                 return -EBUSY;
10187         }
10188
10189         if (frame_size > ETHER_MAX_LEN)
10190                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10191         else
10192                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10193
10194         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10195
10196         return ret;
10197 }
10198
10199 /* Restore ethertype filter */
10200 static void
10201 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10202 {
10203         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10204         struct i40e_ethertype_filter_list
10205                 *ethertype_list = &pf->ethertype.ethertype_list;
10206         struct i40e_ethertype_filter *f;
10207         struct i40e_control_filter_stats stats;
10208         uint16_t flags;
10209
10210         TAILQ_FOREACH(f, ethertype_list, rules) {
10211                 flags = 0;
10212                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10213                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10214                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10215                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10216                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10217
10218                 memset(&stats, 0, sizeof(stats));
10219                 i40e_aq_add_rem_control_packet_filter(hw,
10220                                             f->input.mac_addr.addr_bytes,
10221                                             f->input.ether_type,
10222                                             flags, pf->main_vsi->seid,
10223                                             f->queue, 1, &stats, NULL);
10224         }
10225         PMD_DRV_LOG(INFO, "Ethertype filter:"
10226                     " mac_etype_used = %u, etype_used = %u,"
10227                     " mac_etype_free = %u, etype_free = %u\n",
10228                     stats.mac_etype_used, stats.etype_used,
10229                     stats.mac_etype_free, stats.etype_free);
10230 }
10231
10232 static void
10233 i40e_filter_restore(struct i40e_pf *pf)
10234 {
10235         i40e_ethertype_filter_restore(pf);
10236 }